2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/i2c.h>
29 #include <linux/hdmi.h>
30 #include <drm/i915_drm.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_fb_helper.h>
35 #include <drm/drm_dp_mst_helper.h>
38 * _wait_for - magic (register) wait macro
40 * Does the right thing for modeset paths when run under kdgb or similar atomic
41 * contexts. Note that it's important that we check the condition again after
42 * having timed out, since the timeout could be due to preemption or similar and
43 * we've never had a chance to check the condition before the timeout.
45 #define _wait_for(COND, MS, W) ({ \
46 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
49 if (time_after(jiffies, timeout__)) { \
54 if (W && drm_can_sleep()) { \
63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
66 DIV_ROUND_UP((US), 1000), 0)
68 #define KHz(x) (1000 * (x))
69 #define MHz(x) KHz(1000 * (x))
72 * Display related stuff
75 /* store information about an Ixxx DVO */
76 /* The i830->i865 use multiple DVOs with multiple i2cs */
77 /* the i915, i945 have a single sDVO i2c bus - which is different */
79 /* maximum connectors per crtcs in the mode set */
81 /* Maximum cursor sizes */
82 #define GEN2_CURSOR_WIDTH 64
83 #define GEN2_CURSOR_HEIGHT 64
84 #define MAX_CURSOR_WIDTH 256
85 #define MAX_CURSOR_HEIGHT 256
87 #define INTEL_I2C_BUS_DVO 1
88 #define INTEL_I2C_BUS_SDVO 2
90 /* these are outputs from the chip - integrated only
91 external chips are via DVO or SDVO output */
92 #define INTEL_OUTPUT_UNUSED 0
93 #define INTEL_OUTPUT_ANALOG 1
94 #define INTEL_OUTPUT_DVO 2
95 #define INTEL_OUTPUT_SDVO 3
96 #define INTEL_OUTPUT_LVDS 4
97 #define INTEL_OUTPUT_TVOUT 5
98 #define INTEL_OUTPUT_HDMI 6
99 #define INTEL_OUTPUT_DISPLAYPORT 7
100 #define INTEL_OUTPUT_EDP 8
101 #define INTEL_OUTPUT_DSI 9
102 #define INTEL_OUTPUT_UNKNOWN 10
103 #define INTEL_OUTPUT_DP_MST 11
105 #define INTEL_DVO_CHIP_NONE 0
106 #define INTEL_DVO_CHIP_LVDS 1
107 #define INTEL_DVO_CHIP_TMDS 2
108 #define INTEL_DVO_CHIP_TVOUT 4
110 #define INTEL_DSI_VIDEO_MODE 0
111 #define INTEL_DSI_COMMAND_MODE 1
113 struct intel_framebuffer
{
114 struct drm_framebuffer base
;
115 struct drm_i915_gem_object
*obj
;
119 struct drm_fb_helper helper
;
120 struct intel_framebuffer
*fb
;
121 struct list_head fbdev_list
;
122 struct drm_display_mode
*our_mode
;
126 struct intel_encoder
{
127 struct drm_encoder base
;
129 * The new crtc this encoder will be driven from. Only differs from
130 * base->crtc while a modeset is in progress.
132 struct intel_crtc
*new_crtc
;
135 unsigned int cloneable
;
136 bool connectors_active
;
137 void (*hot_plug
)(struct intel_encoder
*);
138 bool (*compute_config
)(struct intel_encoder
*,
139 struct intel_crtc_config
*);
140 void (*pre_pll_enable
)(struct intel_encoder
*);
141 void (*pre_enable
)(struct intel_encoder
*);
142 void (*enable
)(struct intel_encoder
*);
143 void (*mode_set
)(struct intel_encoder
*intel_encoder
);
144 void (*disable
)(struct intel_encoder
*);
145 void (*post_disable
)(struct intel_encoder
*);
146 /* Read out the current hw state of this connector, returning true if
147 * the encoder is active. If the encoder is enabled it also set the pipe
148 * it is connected to in the pipe parameter. */
149 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
150 /* Reconstructs the equivalent mode flags for the current hardware
151 * state. This must be called _after_ display->get_pipe_config has
152 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
153 * be set correctly before calling this function. */
154 void (*get_config
)(struct intel_encoder
*,
155 struct intel_crtc_config
*pipe_config
);
157 enum hpd_pin hpd_pin
;
161 struct drm_display_mode
*fixed_mode
;
162 struct drm_display_mode
*downclock_mode
;
172 bool combination_mode
; /* gen 2/4 only */
174 struct backlight_device
*device
;
178 struct intel_connector
{
179 struct drm_connector base
;
181 * The fixed encoder this connector is connected to.
183 struct intel_encoder
*encoder
;
186 * The new encoder this connector will be driven. Only differs from
187 * encoder while a modeset is in progress.
189 struct intel_encoder
*new_encoder
;
191 /* Reads out the current hw, returning true if the connector is enabled
192 * and active (i.e. dpms ON state). */
193 bool (*get_hw_state
)(struct intel_connector
*);
196 * Removes all interfaces through which the connector is accessible
197 * - like sysfs, debugfs entries -, so that no new operations can be
198 * started on the connector. Also makes sure all currently pending
199 * operations finish before returing.
201 void (*unregister
)(struct intel_connector
*);
203 /* Panel info for eDP and LVDS */
204 struct intel_panel panel
;
206 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
209 /* since POLL and HPD connectors may use the same HPD line keep the native
210 state of connector->polled in case hotplug storm detection changes it */
213 void *port
; /* store this opaque as its illegal to dereference it */
215 struct intel_dp
*mst_port
;
218 typedef struct dpll
{
230 struct intel_plane_config
{
236 struct intel_crtc_config
{
238 * quirks - bitfield with hw state readout quirks
240 * For various reasons the hw state readout code might not be able to
241 * completely faithfully read out the current state. These cases are
242 * tracked with quirk flags so that fastboot and state checker can act
245 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
246 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
247 unsigned long quirks
;
249 /* User requested mode, only valid as a starting point to
250 * compute adjusted_mode, except in the case of (S)DVO where
251 * it's also for the output timings of the (S)DVO chip.
252 * adjusted_mode will then correspond to the S(DVO) chip's
253 * preferred input timings. */
254 struct drm_display_mode requested_mode
;
255 /* Actual pipe timings ie. what we program into the pipe timing
256 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
257 struct drm_display_mode adjusted_mode
;
259 /* Pipe source size (ie. panel fitter input size)
260 * All planes will be positioned inside this space,
261 * and get clipped at the edges. */
262 int pipe_src_w
, pipe_src_h
;
264 /* Whether to set up the PCH/FDI. Note that we never allow sharing
265 * between pch encoders and cpu encoders. */
266 bool has_pch_encoder
;
268 /* CPU Transcoder for the pipe. Currently this can only differ from the
269 * pipe on Haswell (where we have a special eDP transcoder). */
270 enum transcoder cpu_transcoder
;
273 * Use reduced/limited/broadcast rbg range, compressing from the full
274 * range fed into the crtcs.
276 bool limited_color_range
;
278 /* DP has a bunch of special case unfortunately, so mark the pipe
282 /* Whether we should send NULL infoframes. Required for audio. */
285 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
286 * has_dp_encoder is set. */
290 * Enable dithering, used when the selected pipe bpp doesn't match the
295 /* Controls for the clock computation, to override various stages. */
298 /* SDVO TV has a bunch of special case. To make multifunction encoders
299 * work correctly, we need to track this at runtime.*/
303 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
304 * required. This is set in the 2nd loop of calling encoder's
305 * ->compute_config if the first pick doesn't work out.
309 /* Settings for the intel dpll used on pretty much everything but
313 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
314 enum intel_dpll_id shared_dpll
;
316 /* PORT_CLK_SEL for DDI ports. */
317 uint32_t ddi_pll_sel
;
319 /* Actual register state of the dpll, for shared dpll cross-checking. */
320 struct intel_dpll_hw_state dpll_hw_state
;
323 struct intel_link_m_n dp_m_n
;
325 /* m2_n2 for eDP downclock */
326 struct intel_link_m_n dp_m2_n2
;
329 * Frequence the dpll for the port should run at. Differs from the
330 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
331 * already multiplied by pixel_multiplier.
335 /* Used by SDVO (and if we ever fix it, HDMI). */
336 unsigned pixel_multiplier
;
338 /* Panel fitter controls for gen2-gen4 + VLV */
342 u32 lvds_border_bits
;
345 /* Panel fitter placement and size for Ironlake+ */
353 /* FDI configuration, only valid if has_pch_encoder is set. */
355 struct intel_link_m_n fdi_m_n
;
361 bool dp_encoder_is_mst
;
365 struct intel_pipe_wm
{
366 struct intel_wm_level wm
[5];
370 bool sprites_enabled
;
374 struct intel_mmio_flip
{
380 struct drm_crtc base
;
383 u8 lut_r
[256], lut_g
[256], lut_b
[256];
385 * Whether the crtc and the connected output pipeline is active. Implies
386 * that crtc->enabled is set, i.e. the current mode configuration has
387 * some outputs connected to this crtc.
390 unsigned long enabled_power_domains
;
391 bool primary_enabled
; /* is the primary plane (partially) visible? */
393 struct intel_overlay
*overlay
;
394 struct intel_unpin_work
*unpin_work
;
396 atomic_t unpin_work_count
;
398 /* Display surface base address adjustement for pageflips. Note that on
399 * gen4+ this only adjusts up to a tile, offsets within a tile are
400 * handled in the hw itself (with the TILEOFF register). */
401 unsigned long dspaddr_offset
;
403 struct drm_i915_gem_object
*cursor_bo
;
404 uint32_t cursor_addr
;
405 int16_t cursor_width
, cursor_height
;
406 uint32_t cursor_cntl
;
407 uint32_t cursor_base
;
409 struct intel_plane_config plane_config
;
410 struct intel_crtc_config config
;
411 struct intel_crtc_config
*new_config
;
414 /* reset counter value when the last flip was submitted */
415 unsigned int reset_counter
;
417 /* Access to these should be protected by dev_priv->irq_lock. */
418 bool cpu_fifo_underrun_disabled
;
419 bool pch_fifo_underrun_disabled
;
421 /* per-pipe watermark state */
423 /* watermarks currently being used */
424 struct intel_pipe_wm active
;
427 wait_queue_head_t vbl_wait
;
430 struct intel_mmio_flip mmio_flip
;
433 struct intel_plane_wm_parameters
{
434 uint32_t horiz_pixels
;
435 uint32_t vert_pixels
;
436 uint8_t bytes_per_pixel
;
442 struct drm_plane base
;
445 struct drm_i915_gem_object
*obj
;
449 unsigned int crtc_w
, crtc_h
;
450 uint32_t src_x
, src_y
;
451 uint32_t src_w
, src_h
;
453 /* Since we need to change the watermarks before/after
454 * enabling/disabling the planes, we need to store the parameters here
455 * as the other pieces of the struct may not reflect the values we want
456 * for the watermark calculations. Currently only Haswell uses this.
458 struct intel_plane_wm_parameters wm
;
460 void (*update_plane
)(struct drm_plane
*plane
,
461 struct drm_crtc
*crtc
,
462 struct drm_framebuffer
*fb
,
463 struct drm_i915_gem_object
*obj
,
464 int crtc_x
, int crtc_y
,
465 unsigned int crtc_w
, unsigned int crtc_h
,
466 uint32_t x
, uint32_t y
,
467 uint32_t src_w
, uint32_t src_h
);
468 void (*disable_plane
)(struct drm_plane
*plane
,
469 struct drm_crtc
*crtc
);
470 int (*update_colorkey
)(struct drm_plane
*plane
,
471 struct drm_intel_sprite_colorkey
*key
);
472 void (*get_colorkey
)(struct drm_plane
*plane
,
473 struct drm_intel_sprite_colorkey
*key
);
476 struct intel_watermark_params
{
477 unsigned long fifo_size
;
478 unsigned long max_wm
;
479 unsigned long default_wm
;
480 unsigned long guard_size
;
481 unsigned long cacheline_size
;
484 struct cxsr_latency
{
487 unsigned long fsb_freq
;
488 unsigned long mem_freq
;
489 unsigned long display_sr
;
490 unsigned long display_hpll_disable
;
491 unsigned long cursor_sr
;
492 unsigned long cursor_hpll_disable
;
495 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
496 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
497 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
498 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
499 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
500 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
505 uint32_t color_range
;
506 bool color_range_auto
;
509 enum hdmi_force_audio force_audio
;
510 bool rgb_quant_range_selectable
;
511 enum hdmi_picture_aspect aspect_ratio
;
512 void (*write_infoframe
)(struct drm_encoder
*encoder
,
513 enum hdmi_infoframe_type type
,
514 const void *frame
, ssize_t len
);
515 void (*set_infoframes
)(struct drm_encoder
*encoder
,
517 struct drm_display_mode
*adjusted_mode
);
520 struct intel_dp_mst_encoder
;
521 #define DP_MAX_DOWNSTREAM_PORTS 0x10
524 * HIGH_RR is the highest eDP panel refresh rate read from EDID
525 * LOW_RR is the lowest eDP panel refresh rate found from EDID
526 * parsing for same resolution.
528 enum edp_drrs_refresh_rate_type
{
531 DRRS_MAX_RR
, /* RR count */
536 uint32_t aux_ch_ctl_reg
;
539 enum hdmi_force_audio force_audio
;
540 uint32_t color_range
;
541 bool color_range_auto
;
544 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
545 uint8_t psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
546 uint8_t downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
547 struct drm_dp_aux aux
;
548 uint8_t train_set
[4];
549 int panel_power_up_delay
;
550 int panel_power_down_delay
;
551 int panel_power_cycle_delay
;
552 int backlight_on_delay
;
553 int backlight_off_delay
;
554 struct delayed_work panel_vdd_work
;
556 unsigned long last_power_cycle
;
557 unsigned long last_power_on
;
558 unsigned long last_backlight_off
;
560 bool can_mst
; /* this port supports mst */
562 int active_mst_links
;
563 /* connector directly attached - won't be use for modeset in mst world */
564 struct intel_connector
*attached_connector
;
566 /* mst connector list */
567 struct intel_dp_mst_encoder
*mst_encoders
[I915_MAX_PIPES
];
568 struct drm_dp_mst_topology_mgr mst_mgr
;
570 uint32_t (*get_aux_clock_divider
)(struct intel_dp
*dp
, int index
);
572 * This function returns the value we have to program the AUX_CTL
573 * register with to kick off an AUX transaction.
575 uint32_t (*get_aux_send_ctl
)(struct intel_dp
*dp
,
578 uint32_t aux_clock_divider
);
580 enum drrs_support_type type
;
581 enum edp_drrs_refresh_rate_type refresh_rate_type
;
587 struct intel_digital_port
{
588 struct intel_encoder base
;
592 struct intel_hdmi hdmi
;
593 bool (*hpd_pulse
)(struct intel_digital_port
*, bool);
596 struct intel_dp_mst_encoder
{
597 struct intel_encoder base
;
599 struct intel_digital_port
*primary
;
600 void *port
; /* store this opaque as its illegal to dereference it */
604 vlv_dport_to_channel(struct intel_digital_port
*dport
)
606 switch (dport
->port
) {
618 vlv_pipe_to_channel(enum pipe pipe
)
631 static inline struct drm_crtc
*
632 intel_get_crtc_for_pipe(struct drm_device
*dev
, int pipe
)
634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
635 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
638 static inline struct drm_crtc
*
639 intel_get_crtc_for_plane(struct drm_device
*dev
, int plane
)
641 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
642 return dev_priv
->plane_to_crtc_mapping
[plane
];
645 struct intel_unpin_work
{
646 struct work_struct work
;
647 struct drm_crtc
*crtc
;
648 struct drm_i915_gem_object
*old_fb_obj
;
649 struct drm_i915_gem_object
*pending_flip_obj
;
650 struct drm_pending_vblank_event
*event
;
652 #define INTEL_FLIP_INACTIVE 0
653 #define INTEL_FLIP_PENDING 1
654 #define INTEL_FLIP_COMPLETE 2
657 bool enable_stall_check
;
660 struct intel_set_config
{
661 struct drm_encoder
**save_connector_encoders
;
662 struct drm_crtc
**save_encoder_crtcs
;
663 bool *save_crtc_enabled
;
669 struct intel_load_detect_pipe
{
670 struct drm_framebuffer
*release_fb
;
671 bool load_detect_temp
;
675 static inline struct intel_encoder
*
676 intel_attached_encoder(struct drm_connector
*connector
)
678 return to_intel_connector(connector
)->encoder
;
681 static inline struct intel_digital_port
*
682 enc_to_dig_port(struct drm_encoder
*encoder
)
684 return container_of(encoder
, struct intel_digital_port
, base
.base
);
687 static inline struct intel_dp_mst_encoder
*
688 enc_to_mst(struct drm_encoder
*encoder
)
690 return container_of(encoder
, struct intel_dp_mst_encoder
, base
.base
);
693 static inline struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
695 return &enc_to_dig_port(encoder
)->dp
;
698 static inline struct intel_digital_port
*
699 dp_to_dig_port(struct intel_dp
*intel_dp
)
701 return container_of(intel_dp
, struct intel_digital_port
, dp
);
704 static inline struct intel_digital_port
*
705 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
707 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
712 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
713 enum pipe pipe
, bool enable
);
714 bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
715 enum transcoder pch_transcoder
,
717 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
718 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
719 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
720 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
721 void gen8_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
722 void gen8_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
723 void intel_runtime_pm_disable_interrupts(struct drm_device
*dev
);
724 void intel_runtime_pm_restore_interrupts(struct drm_device
*dev
);
725 static inline bool intel_irqs_enabled(struct drm_i915_private
*dev_priv
)
728 * We only use drm_irq_uninstall() at unload and VT switch, so
729 * this is the only thing we need to check.
731 return !dev_priv
->pm
._irqs_disabled
;
734 int intel_get_crtc_scanline(struct intel_crtc
*crtc
);
735 void i9xx_check_fifo_underruns(struct drm_device
*dev
);
736 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
);
739 void intel_crt_init(struct drm_device
*dev
);
743 void intel_prepare_ddi(struct drm_device
*dev
);
744 void hsw_fdi_link_train(struct drm_crtc
*crtc
);
745 void intel_ddi_init(struct drm_device
*dev
, enum port port
);
746 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
);
747 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
, enum pipe
*pipe
);
748 int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
);
749 void intel_ddi_pll_init(struct drm_device
*dev
);
750 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
);
751 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
752 enum transcoder cpu_transcoder
);
753 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
);
754 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
);
755 bool intel_ddi_pll_select(struct intel_crtc
*crtc
);
756 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
);
757 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
);
758 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
);
759 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
);
760 void intel_ddi_get_config(struct intel_encoder
*encoder
,
761 struct intel_crtc_config
*pipe_config
);
763 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
);
764 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
765 struct intel_crtc_config
*pipe_config
);
766 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
);
768 /* intel_display.c */
769 const char *intel_output_name(int output
);
770 bool intel_has_pending_fb_unpin(struct drm_device
*dev
);
771 int intel_pch_rawclk(struct drm_device
*dev
);
772 void intel_mark_busy(struct drm_device
*dev
);
773 void intel_fb_obj_invalidate(struct drm_i915_gem_object
*obj
,
774 struct intel_engine_cs
*ring
);
775 void intel_frontbuffer_flip_prepare(struct drm_device
*dev
,
776 unsigned frontbuffer_bits
);
777 void intel_frontbuffer_flip_complete(struct drm_device
*dev
,
778 unsigned frontbuffer_bits
);
779 void intel_frontbuffer_flush(struct drm_device
*dev
,
780 unsigned frontbuffer_bits
);
782 * intel_frontbuffer_flip - prepare frontbuffer flip
784 * @frontbuffer_bits: frontbuffer plane tracking bits
786 * This function gets called after scheduling a flip on @obj. This is for
787 * synchronous plane updates which will happen on the next vblank and which will
788 * not get delayed by pending gpu rendering.
790 * Can be called without any locks held.
793 void intel_frontbuffer_flip(struct drm_device
*dev
,
794 unsigned frontbuffer_bits
)
796 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
799 void intel_fb_obj_flush(struct drm_i915_gem_object
*obj
, bool retire
);
800 void intel_mark_idle(struct drm_device
*dev
);
801 void intel_crtc_restore_mode(struct drm_crtc
*crtc
);
802 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
);
803 void intel_crtc_update_dpms(struct drm_crtc
*crtc
);
804 void intel_encoder_destroy(struct drm_encoder
*encoder
);
805 void intel_connector_dpms(struct drm_connector
*, int mode
);
806 bool intel_connector_get_hw_state(struct intel_connector
*connector
);
807 void intel_modeset_check_state(struct drm_device
*dev
);
808 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
809 struct intel_digital_port
*port
);
810 void intel_connector_attach_encoder(struct intel_connector
*connector
,
811 struct intel_encoder
*encoder
);
812 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
);
813 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
814 struct drm_crtc
*crtc
);
815 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
);
816 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
817 struct drm_file
*file_priv
);
818 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
820 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
);
821 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
);
822 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
);
823 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
824 struct intel_digital_port
*dport
);
825 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
826 struct drm_display_mode
*mode
,
827 struct intel_load_detect_pipe
*old
,
828 struct drm_modeset_acquire_ctx
*ctx
);
829 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
830 struct intel_load_detect_pipe
*old
,
831 struct drm_modeset_acquire_ctx
*ctx
);
832 int intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
833 struct drm_i915_gem_object
*obj
,
834 struct intel_engine_cs
*pipelined
);
835 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
);
836 struct drm_framebuffer
*
837 __intel_framebuffer_create(struct drm_device
*dev
,
838 struct drm_mode_fb_cmd2
*mode_cmd
,
839 struct drm_i915_gem_object
*obj
);
840 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
);
841 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
);
842 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
);
844 /* shared dpll functions */
845 struct intel_shared_dpll
*intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
);
846 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
847 struct intel_shared_dpll
*pll
,
849 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
850 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
851 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
);
852 void intel_put_shared_dpll(struct intel_crtc
*crtc
);
854 /* modesetting asserts */
855 void assert_pll(struct drm_i915_private
*dev_priv
,
856 enum pipe pipe
, bool state
);
857 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
858 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
859 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
860 enum pipe pipe
, bool state
);
861 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
862 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
863 void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool state
);
864 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
865 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
866 void intel_write_eld(struct drm_encoder
*encoder
,
867 struct drm_display_mode
*mode
);
868 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
869 unsigned int tiling_mode
,
872 void intel_display_handle_reset(struct drm_device
*dev
);
873 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
);
874 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
);
875 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
876 struct intel_crtc_config
*pipe_config
);
877 int intel_dotclock_calculate(int link_freq
, const struct intel_link_m_n
*m_n
);
879 ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
881 bool intel_crtc_active(struct drm_crtc
*crtc
);
882 void hsw_enable_ips(struct intel_crtc
*crtc
);
883 void hsw_disable_ips(struct intel_crtc
*crtc
);
884 void intel_display_set_init_power(struct drm_i915_private
*dev
, bool enable
);
885 enum intel_display_power_domain
886 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
);
887 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
888 struct intel_crtc_config
*pipe_config
);
889 int intel_format_to_fourcc(int format
);
890 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
);
894 void intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
);
895 bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
896 struct intel_connector
*intel_connector
);
897 void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
898 void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
899 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
);
900 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
901 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
);
902 void intel_dp_check_link_status(struct intel_dp
*intel_dp
);
903 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
);
904 bool intel_dp_compute_config(struct intel_encoder
*encoder
,
905 struct intel_crtc_config
*pipe_config
);
906 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
);
907 bool intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
,
909 void intel_edp_backlight_on(struct intel_dp
*intel_dp
);
910 void intel_edp_backlight_off(struct intel_dp
*intel_dp
);
911 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
912 void intel_edp_panel_on(struct intel_dp
*intel_dp
);
913 void intel_edp_panel_off(struct intel_dp
*intel_dp
);
914 void intel_edp_psr_enable(struct intel_dp
*intel_dp
);
915 void intel_edp_psr_disable(struct intel_dp
*intel_dp
);
916 void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
);
917 void intel_edp_psr_invalidate(struct drm_device
*dev
,
918 unsigned frontbuffer_bits
);
919 void intel_edp_psr_flush(struct drm_device
*dev
,
920 unsigned frontbuffer_bits
);
921 void intel_edp_psr_init(struct drm_device
*dev
);
923 int intel_dp_handle_hpd_irq(struct intel_digital_port
*digport
, bool long_hpd
);
924 void intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
);
925 void intel_dp_mst_suspend(struct drm_device
*dev
);
926 void intel_dp_mst_resume(struct drm_device
*dev
);
927 int intel_dp_max_link_bw(struct intel_dp
*intel_dp
);
928 void intel_dp_hot_plug(struct intel_encoder
*intel_encoder
);
930 int intel_dp_mst_encoder_init(struct intel_digital_port
*intel_dig_port
, int conn_id
);
931 void intel_dp_mst_encoder_cleanup(struct intel_digital_port
*intel_dig_port
);
933 void intel_dsi_init(struct drm_device
*dev
);
937 void intel_dvo_init(struct drm_device
*dev
);
940 /* legacy fbdev emulation in intel_fbdev.c */
941 #ifdef CONFIG_DRM_I915_FBDEV
942 extern int intel_fbdev_init(struct drm_device
*dev
);
943 extern void intel_fbdev_initial_config(struct drm_device
*dev
);
944 extern void intel_fbdev_fini(struct drm_device
*dev
);
945 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
);
946 extern void intel_fbdev_output_poll_changed(struct drm_device
*dev
);
947 extern void intel_fbdev_restore_mode(struct drm_device
*dev
);
949 static inline int intel_fbdev_init(struct drm_device
*dev
)
954 static inline void intel_fbdev_initial_config(struct drm_device
*dev
)
958 static inline void intel_fbdev_fini(struct drm_device
*dev
)
962 static inline void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
)
966 static inline void intel_fbdev_restore_mode(struct drm_device
*dev
)
972 void intel_hdmi_init(struct drm_device
*dev
, int hdmi_reg
, enum port port
);
973 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
974 struct intel_connector
*intel_connector
);
975 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
);
976 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
977 struct intel_crtc_config
*pipe_config
);
981 void intel_lvds_init(struct drm_device
*dev
);
982 bool intel_is_dual_link_lvds(struct drm_device
*dev
);
986 int intel_connector_update_modes(struct drm_connector
*connector
,
988 int intel_ddc_get_modes(struct drm_connector
*c
, struct i2c_adapter
*adapter
);
989 void intel_attach_force_audio_property(struct drm_connector
*connector
);
990 void intel_attach_broadcast_rgb_property(struct drm_connector
*connector
);
993 /* intel_overlay.c */
994 void intel_setup_overlay(struct drm_device
*dev
);
995 void intel_cleanup_overlay(struct drm_device
*dev
);
996 int intel_overlay_switch_off(struct intel_overlay
*overlay
);
997 int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
998 struct drm_file
*file_priv
);
999 int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
1000 struct drm_file
*file_priv
);
1004 int intel_panel_init(struct intel_panel
*panel
,
1005 struct drm_display_mode
*fixed_mode
,
1006 struct drm_display_mode
*downclock_mode
);
1007 void intel_panel_fini(struct intel_panel
*panel
);
1008 void intel_fixed_panel_mode(const struct drm_display_mode
*fixed_mode
,
1009 struct drm_display_mode
*adjusted_mode
);
1010 void intel_pch_panel_fitting(struct intel_crtc
*crtc
,
1011 struct intel_crtc_config
*pipe_config
,
1013 void intel_gmch_panel_fitting(struct intel_crtc
*crtc
,
1014 struct intel_crtc_config
*pipe_config
,
1016 void intel_panel_set_backlight_acpi(struct intel_connector
*connector
,
1017 u32 level
, u32 max
);
1018 int intel_panel_setup_backlight(struct drm_connector
*connector
);
1019 void intel_panel_enable_backlight(struct intel_connector
*connector
);
1020 void intel_panel_disable_backlight(struct intel_connector
*connector
);
1021 void intel_panel_destroy_backlight(struct drm_connector
*connector
);
1022 void intel_panel_init_backlight_funcs(struct drm_device
*dev
);
1023 enum drm_connector_status
intel_panel_detect(struct drm_device
*dev
);
1024 extern struct drm_display_mode
*intel_find_panel_downclock(
1025 struct drm_device
*dev
,
1026 struct drm_display_mode
*fixed_mode
,
1027 struct drm_connector
*connector
);
1030 void intel_init_clock_gating(struct drm_device
*dev
);
1031 void intel_suspend_hw(struct drm_device
*dev
);
1032 int ilk_wm_max_level(const struct drm_device
*dev
);
1033 void intel_update_watermarks(struct drm_crtc
*crtc
);
1034 void intel_update_sprite_watermarks(struct drm_plane
*plane
,
1035 struct drm_crtc
*crtc
,
1036 uint32_t sprite_width
,
1037 uint32_t sprite_height
,
1039 bool enabled
, bool scaled
);
1040 void intel_init_pm(struct drm_device
*dev
);
1041 void intel_pm_setup(struct drm_device
*dev
);
1042 bool intel_fbc_enabled(struct drm_device
*dev
);
1043 void intel_update_fbc(struct drm_device
*dev
);
1044 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
1045 void intel_gpu_ips_teardown(void);
1046 int intel_power_domains_init(struct drm_i915_private
*);
1047 void intel_power_domains_remove(struct drm_i915_private
*);
1048 bool intel_display_power_enabled(struct drm_i915_private
*dev_priv
,
1049 enum intel_display_power_domain domain
);
1050 bool intel_display_power_enabled_unlocked(struct drm_i915_private
*dev_priv
,
1051 enum intel_display_power_domain domain
);
1052 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
1053 enum intel_display_power_domain domain
);
1054 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
1055 enum intel_display_power_domain domain
);
1056 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
);
1057 void intel_init_gt_powersave(struct drm_device
*dev
);
1058 void intel_cleanup_gt_powersave(struct drm_device
*dev
);
1059 void intel_enable_gt_powersave(struct drm_device
*dev
);
1060 void intel_disable_gt_powersave(struct drm_device
*dev
);
1061 void intel_suspend_gt_powersave(struct drm_device
*dev
);
1062 void intel_reset_gt_powersave(struct drm_device
*dev
);
1063 void ironlake_teardown_rc6(struct drm_device
*dev
);
1064 void gen6_update_ring_freq(struct drm_device
*dev
);
1065 void gen6_rps_idle(struct drm_i915_private
*dev_priv
);
1066 void gen6_rps_boost(struct drm_i915_private
*dev_priv
);
1067 void intel_aux_display_runtime_get(struct drm_i915_private
*dev_priv
);
1068 void intel_aux_display_runtime_put(struct drm_i915_private
*dev_priv
);
1069 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
);
1070 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
);
1071 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
);
1072 void intel_init_runtime_pm(struct drm_i915_private
*dev_priv
);
1073 void intel_fini_runtime_pm(struct drm_i915_private
*dev_priv
);
1074 void ilk_wm_get_hw_state(struct drm_device
*dev
);
1078 bool intel_sdvo_init(struct drm_device
*dev
, uint32_t sdvo_reg
, bool is_sdvob
);
1081 /* intel_sprite.c */
1082 int intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
);
1083 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
1085 void intel_plane_restore(struct drm_plane
*plane
);
1086 void intel_plane_disable(struct drm_plane
*plane
);
1087 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
1088 struct drm_file
*file_priv
);
1089 int intel_sprite_get_colorkey(struct drm_device
*dev
, void *data
,
1090 struct drm_file
*file_priv
);
1094 void intel_tv_init(struct drm_device
*dev
);
1096 #endif /* __INTEL_DRV_H__ */