2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <linux/sched/clock.h>
32 #include <drm/i915_drm.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_dp_dual_mode_helper.h>
39 #include <drm/drm_dp_mst_helper.h>
40 #include <drm/drm_rect.h>
41 #include <drm/drm_atomic.h>
44 * _wait_for - magic (register) wait macro
46 * Does the right thing for modeset paths when run under kdgb or similar atomic
47 * contexts. Note that it's important that we check the condition again after
48 * having timed out, since the timeout could be due to preemption or similar and
49 * we've never had a chance to check the condition before the timeout.
51 * TODO: When modesetting has fully transitioned to atomic, the below
52 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
55 #define _wait_for(COND, US, W) ({ \
56 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
59 bool expired__ = time_after(jiffies, timeout__); \
68 if ((W) && drm_can_sleep()) { \
69 usleep_range((W), (W)*2); \
77 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
79 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
80 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
86 #define _wait_for_atomic(COND, US, ATOMIC) \
88 int cpu, ret, timeout = (US) * 1000; \
90 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
93 cpu = smp_processor_id(); \
95 base = local_clock(); \
97 u64 now = local_clock(); \
104 if (now - base >= timeout) { \
111 if (unlikely(cpu != smp_processor_id())) { \
112 timeout -= now - base; \
113 cpu = smp_processor_id(); \
114 base = local_clock(); \
121 #define wait_for_us(COND, US) \
124 BUILD_BUG_ON(!__builtin_constant_p(US)); \
126 ret__ = _wait_for((COND), (US), 10); \
128 ret__ = _wait_for_atomic((COND), (US), 0); \
132 #define wait_for_atomic_us(COND, US) \
134 BUILD_BUG_ON(!__builtin_constant_p(US)); \
135 BUILD_BUG_ON((US) > 50000); \
136 _wait_for_atomic((COND), (US), 1); \
139 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
141 #define KHz(x) (1000 * (x))
142 #define MHz(x) KHz(1000 * (x))
145 * Display related stuff
148 /* store information about an Ixxx DVO */
149 /* The i830->i865 use multiple DVOs with multiple i2cs */
150 /* the i915, i945 have a single sDVO i2c bus - which is different */
151 #define MAX_OUTPUTS 6
152 /* maximum connectors per crtcs in the mode set */
154 /* Maximum cursor sizes */
155 #define GEN2_CURSOR_WIDTH 64
156 #define GEN2_CURSOR_HEIGHT 64
157 #define MAX_CURSOR_WIDTH 256
158 #define MAX_CURSOR_HEIGHT 256
160 #define INTEL_I2C_BUS_DVO 1
161 #define INTEL_I2C_BUS_SDVO 2
163 /* these are outputs from the chip - integrated only
164 external chips are via DVO or SDVO output */
165 enum intel_output_type
{
166 INTEL_OUTPUT_UNUSED
= 0,
167 INTEL_OUTPUT_ANALOG
= 1,
168 INTEL_OUTPUT_DVO
= 2,
169 INTEL_OUTPUT_SDVO
= 3,
170 INTEL_OUTPUT_LVDS
= 4,
171 INTEL_OUTPUT_TVOUT
= 5,
172 INTEL_OUTPUT_HDMI
= 6,
174 INTEL_OUTPUT_EDP
= 8,
175 INTEL_OUTPUT_DSI
= 9,
176 INTEL_OUTPUT_UNKNOWN
= 10,
177 INTEL_OUTPUT_DP_MST
= 11,
180 #define INTEL_DVO_CHIP_NONE 0
181 #define INTEL_DVO_CHIP_LVDS 1
182 #define INTEL_DVO_CHIP_TMDS 2
183 #define INTEL_DVO_CHIP_TVOUT 4
185 #define INTEL_DSI_VIDEO_MODE 0
186 #define INTEL_DSI_COMMAND_MODE 1
188 struct intel_framebuffer
{
189 struct drm_framebuffer base
;
190 struct drm_i915_gem_object
*obj
;
191 struct intel_rotation_info rot_info
;
193 /* for each plane in the normal GTT view */
197 /* for each plane in the rotated GTT view */
200 unsigned int pitch
; /* pixels */
205 struct drm_fb_helper helper
;
206 struct intel_framebuffer
*fb
;
207 struct i915_vma
*vma
;
208 async_cookie_t cookie
;
212 struct intel_encoder
{
213 struct drm_encoder base
;
215 enum intel_output_type type
;
217 unsigned int cloneable
;
218 void (*hot_plug
)(struct intel_encoder
*);
219 bool (*compute_config
)(struct intel_encoder
*,
220 struct intel_crtc_state
*,
221 struct drm_connector_state
*);
222 void (*pre_pll_enable
)(struct intel_encoder
*,
223 const struct intel_crtc_state
*,
224 const struct drm_connector_state
*);
225 void (*pre_enable
)(struct intel_encoder
*,
226 const struct intel_crtc_state
*,
227 const struct drm_connector_state
*);
228 void (*enable
)(struct intel_encoder
*,
229 const struct intel_crtc_state
*,
230 const struct drm_connector_state
*);
231 void (*disable
)(struct intel_encoder
*,
232 const struct intel_crtc_state
*,
233 const struct drm_connector_state
*);
234 void (*post_disable
)(struct intel_encoder
*,
235 const struct intel_crtc_state
*,
236 const struct drm_connector_state
*);
237 void (*post_pll_disable
)(struct intel_encoder
*,
238 const struct intel_crtc_state
*,
239 const struct drm_connector_state
*);
240 /* Read out the current hw state of this connector, returning true if
241 * the encoder is active. If the encoder is enabled it also set the pipe
242 * it is connected to in the pipe parameter. */
243 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
244 /* Reconstructs the equivalent mode flags for the current hardware
245 * state. This must be called _after_ display->get_pipe_config has
246 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
247 * be set correctly before calling this function. */
248 void (*get_config
)(struct intel_encoder
*,
249 struct intel_crtc_state
*pipe_config
);
250 /* Returns a mask of power domains that need to be referenced as part
251 * of the hardware state readout code. */
252 u64 (*get_power_domains
)(struct intel_encoder
*encoder
);
254 * Called during system suspend after all pending requests for the
255 * encoder are flushed (for example for DP AUX transactions) and
256 * device interrupts are disabled.
258 void (*suspend
)(struct intel_encoder
*);
260 enum hpd_pin hpd_pin
;
261 enum intel_display_power_domain power_domain
;
262 /* for communication with audio component; protected by av_mutex */
263 const struct drm_connector
*audio_connector
;
267 struct drm_display_mode
*fixed_mode
;
268 struct drm_display_mode
*alt_fixed_mode
;
269 struct drm_display_mode
*downclock_mode
;
278 bool combination_mode
; /* gen 2/4 only */
280 bool alternate_pwm_increment
; /* lpt+ */
283 bool util_pin_active_low
; /* bxt+ */
284 u8 controller
; /* bxt+ only */
285 struct pwm_device
*pwm
;
287 struct backlight_device
*device
;
289 /* Connector and platform specific backlight functions */
290 int (*setup
)(struct intel_connector
*connector
, enum pipe pipe
);
291 uint32_t (*get
)(struct intel_connector
*connector
);
292 void (*set
)(const struct drm_connector_state
*conn_state
, uint32_t level
);
293 void (*disable
)(const struct drm_connector_state
*conn_state
);
294 void (*enable
)(const struct intel_crtc_state
*crtc_state
,
295 const struct drm_connector_state
*conn_state
);
296 uint32_t (*hz_to_pwm
)(struct intel_connector
*connector
,
298 void (*power
)(struct intel_connector
*, bool enable
);
302 struct intel_connector
{
303 struct drm_connector base
;
305 * The fixed encoder this connector is connected to.
307 struct intel_encoder
*encoder
;
309 /* ACPI device id for ACPI and driver cooperation */
312 /* Reads out the current hw, returning true if the connector is enabled
313 * and active (i.e. dpms ON state). */
314 bool (*get_hw_state
)(struct intel_connector
*);
316 /* Panel info for eDP and LVDS */
317 struct intel_panel panel
;
319 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
321 struct edid
*detect_edid
;
323 /* since POLL and HPD connectors may use the same HPD line keep the native
324 state of connector->polled in case hotplug storm detection changes it */
327 void *port
; /* store this opaque as its illegal to dereference it */
329 struct intel_dp
*mst_port
;
331 /* Work struct to schedule a uevent on link train failure */
332 struct work_struct modeset_retry_work
;
335 struct intel_digital_connector_state
{
336 struct drm_connector_state base
;
338 enum hdmi_force_audio force_audio
;
342 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
356 struct intel_atomic_state
{
357 struct drm_atomic_state base
;
361 * Logical state of cdclk (used for all scaling, watermark,
362 * etc. calculations and checks). This is computed as if all
363 * enabled crtcs were active.
365 struct intel_cdclk_state logical
;
368 * Actual state of cdclk, can be different from the logical
369 * state only when all crtc's are DPMS off.
371 struct intel_cdclk_state actual
;
374 bool dpll_set
, modeset
;
377 * Does this transaction change the pipes that are active? This mask
378 * tracks which CRTC's have changed their active state at the end of
379 * the transaction (not counting the temporary disable during modesets).
380 * This mask should only be non-zero when intel_state->modeset is true,
381 * but the converse is not necessarily true; simply changing a mode may
382 * not flip the final active status of any CRTC's
384 unsigned int active_pipe_changes
;
386 unsigned int active_crtcs
;
387 /* minimum acceptable cdclk for each pipe */
388 int min_cdclk
[I915_MAX_PIPES
];
390 struct intel_shared_dpll_state shared_dpll
[I915_NUM_PLLS
];
393 * Current watermarks can't be trusted during hardware readout, so
394 * don't bother calculating intermediate watermarks.
396 bool skip_intermediate_wm
;
399 struct skl_wm_values wm_results
;
401 struct i915_sw_fence commit_ready
;
403 struct llist_node freed
;
406 struct intel_plane_state
{
407 struct drm_plane_state base
;
408 struct drm_rect clip
;
409 struct i915_vma
*vma
;
420 /* plane control register */
425 * = -1 : not using a scaler
426 * >= 0 : using a scalers
428 * plane requiring a scaler:
429 * - During check_plane, its bit is set in
430 * crtc_state->scaler_state.scaler_users by calling helper function
431 * update_scaler_plane.
432 * - scaler_id indicates the scaler it got assigned.
434 * plane doesn't require a scaler:
435 * - this can happen when scaling is no more required or plane simply
437 * - During check_plane, corresponding bit is reset in
438 * crtc_state->scaler_state.scaler_users by calling helper function
439 * update_scaler_plane.
443 struct drm_intel_sprite_colorkey ckey
;
446 struct intel_initial_plane_config
{
447 struct intel_framebuffer
*fb
;
453 #define SKL_MIN_SRC_W 8
454 #define SKL_MAX_SRC_W 4096
455 #define SKL_MIN_SRC_H 8
456 #define SKL_MAX_SRC_H 4096
457 #define SKL_MIN_DST_W 8
458 #define SKL_MAX_DST_W 4096
459 #define SKL_MIN_DST_H 8
460 #define SKL_MAX_DST_H 4096
462 struct intel_scaler
{
467 struct intel_crtc_scaler_state
{
468 #define SKL_NUM_SCALERS 2
469 struct intel_scaler scalers
[SKL_NUM_SCALERS
];
472 * scaler_users: keeps track of users requesting scalers on this crtc.
474 * If a bit is set, a user is using a scaler.
475 * Here user can be a plane or crtc as defined below:
476 * bits 0-30 - plane (bit position is index from drm_plane_index)
479 * Instead of creating a new index to cover planes and crtc, using
480 * existing drm_plane_index for planes which is well less than 31
481 * planes and bit 31 for crtc. This should be fine to cover all
484 * intel_atomic_setup_scalers will setup available scalers to users
485 * requesting scalers. It will gracefully fail if request exceeds
488 #define SKL_CRTC_INDEX 31
489 unsigned scaler_users
;
491 /* scaler used by crtc for panel fitting purpose */
495 /* drm_mode->private_flags */
496 #define I915_MODE_FLAG_INHERITED 1
497 /* Flag to get scanline using frame time stamps */
498 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
500 struct intel_pipe_wm
{
501 struct intel_wm_level wm
[5];
502 struct intel_wm_level raw_wm
[5];
506 bool sprites_enabled
;
510 struct skl_plane_wm
{
511 struct skl_wm_level wm
[8];
512 struct skl_wm_level trans_wm
;
516 struct skl_plane_wm planes
[I915_MAX_PLANES
];
523 VLV_WM_LEVEL_DDR_DVFS
,
527 struct vlv_wm_state
{
528 struct g4x_pipe_wm wm
[NUM_VLV_WM_LEVELS
];
529 struct g4x_sr_wm sr
[NUM_VLV_WM_LEVELS
];
534 struct vlv_fifo_state
{
535 u16 plane
[I915_MAX_PLANES
];
545 struct g4x_wm_state
{
546 struct g4x_pipe_wm wm
;
548 struct g4x_sr_wm hpll
;
554 struct intel_crtc_wm_state
{
558 * Intermediate watermarks; these can be
559 * programmed immediately since they satisfy
560 * both the current configuration we're
561 * switching away from and the new
562 * configuration we're switching to.
564 struct intel_pipe_wm intermediate
;
567 * Optimal watermarks, programmed post-vblank
568 * when this state is committed.
570 struct intel_pipe_wm optimal
;
574 /* gen9+ only needs 1-step wm programming */
575 struct skl_pipe_wm optimal
;
576 struct skl_ddb_entry ddb
;
580 /* "raw" watermarks (not inverted) */
581 struct g4x_pipe_wm raw
[NUM_VLV_WM_LEVELS
];
582 /* intermediate watermarks (inverted) */
583 struct vlv_wm_state intermediate
;
584 /* optimal watermarks (inverted) */
585 struct vlv_wm_state optimal
;
586 /* display FIFO split */
587 struct vlv_fifo_state fifo_state
;
591 /* "raw" watermarks */
592 struct g4x_pipe_wm raw
[NUM_G4X_WM_LEVELS
];
593 /* intermediate watermarks */
594 struct g4x_wm_state intermediate
;
595 /* optimal watermarks */
596 struct g4x_wm_state optimal
;
601 * Platforms with two-step watermark programming will need to
602 * update watermark programming post-vblank to switch from the
603 * safe intermediate watermarks to the optimal final
606 bool need_postvbl_update
;
609 struct intel_crtc_state
{
610 struct drm_crtc_state base
;
613 * quirks - bitfield with hw state readout quirks
615 * For various reasons the hw state readout code might not be able to
616 * completely faithfully read out the current state. These cases are
617 * tracked with quirk flags so that fastboot and state checker can act
620 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
621 unsigned long quirks
;
623 unsigned fb_bits
; /* framebuffers to flip */
624 bool update_pipe
; /* can a fast modeset be performed? */
626 bool update_wm_pre
, update_wm_post
; /* watermarks are updated */
627 bool fb_changed
; /* fb on any of the planes is changed */
628 bool fifo_changed
; /* FIFO split is changed */
630 /* Pipe source size (ie. panel fitter input size)
631 * All planes will be positioned inside this space,
632 * and get clipped at the edges. */
633 int pipe_src_w
, pipe_src_h
;
636 * Pipe pixel rate, adjusted for
637 * panel fitter/pipe scaler downscaling.
639 unsigned int pixel_rate
;
641 /* Whether to set up the PCH/FDI. Note that we never allow sharing
642 * between pch encoders and cpu encoders. */
643 bool has_pch_encoder
;
645 /* Are we sending infoframes on the attached port */
648 /* CPU Transcoder for the pipe. Currently this can only differ from the
649 * pipe on Haswell and later (where we have a special eDP transcoder)
650 * and Broxton (where we have special DSI transcoders). */
651 enum transcoder cpu_transcoder
;
654 * Use reduced/limited/broadcast rbg range, compressing from the full
655 * range fed into the crtcs.
657 bool limited_color_range
;
659 /* Bitmask of encoder types (enum intel_output_type)
660 * driven by the pipe.
662 unsigned int output_types
;
664 /* Whether we should send NULL infoframes. Required for audio. */
667 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
668 * has_dp_encoder is set. */
672 * Enable dithering, used when the selected pipe bpp doesn't match the
678 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
679 * compliance video pattern tests.
680 * Disable dither only if it is a compliance test request for
683 bool dither_force_disable
;
685 /* Controls for the clock computation, to override various stages. */
688 /* SDVO TV has a bunch of special case. To make multifunction encoders
689 * work correctly, we need to track this at runtime.*/
693 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
694 * required. This is set in the 2nd loop of calling encoder's
695 * ->compute_config if the first pick doesn't work out.
699 /* Settings for the intel dpll used on pretty much everything but
703 /* Selected dpll when shared or NULL. */
704 struct intel_shared_dpll
*shared_dpll
;
706 /* Actual register state of the dpll, for shared dpll cross-checking. */
707 struct intel_dpll_hw_state dpll_hw_state
;
709 /* DSI PLL registers */
715 struct intel_link_m_n dp_m_n
;
717 /* m2_n2 for eDP downclock */
718 struct intel_link_m_n dp_m2_n2
;
722 * Frequence the dpll for the port should run at. Differs from the
723 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
724 * already multiplied by pixel_multiplier.
728 /* Used by SDVO (and if we ever fix it, HDMI). */
729 unsigned pixel_multiplier
;
734 * Used by platforms having DP/HDMI PHY with programmable lane
735 * latency optimization.
737 uint8_t lane_lat_optim_mask
;
739 /* Panel fitter controls for gen2-gen4 + VLV */
743 u32 lvds_border_bits
;
746 /* Panel fitter placement and size for Ironlake+ */
754 /* FDI configuration, only valid if has_pch_encoder is set. */
756 struct intel_link_m_n fdi_m_n
;
759 bool ips_force_disable
;
767 struct intel_crtc_scaler_state scaler_state
;
769 /* w/a for waiting 2 vblanks during crtc enable */
770 enum pipe hsw_workaround_pipe
;
772 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
775 struct intel_crtc_wm_state wm
;
777 /* Gamma mode programmed on the pipe */
780 /* bitmask of visible planes (enum plane_id) */
783 /* HDMI scrambling status */
784 bool hdmi_scrambling
;
786 /* HDMI High TMDS char rate ratio */
787 bool hdmi_high_tmds_clock_ratio
;
789 /* output format is YCBCR 4:2:0 */
794 struct drm_crtc base
;
798 * Whether the crtc and the connected output pipeline is active. Implies
799 * that crtc->enabled is set, i.e. the current mode configuration has
800 * some outputs connected to this crtc.
805 unsigned long long enabled_power_domains
;
806 struct intel_overlay
*overlay
;
808 /* Display surface base address adjustement for pageflips. Note that on
809 * gen4+ this only adjusts up to a tile, offsets within a tile are
810 * handled in the hw itself (with the TILEOFF register). */
815 struct intel_crtc_state
*config
;
817 /* global reset count when the last flip was submitted */
818 unsigned int reset_count
;
820 /* Access to these should be protected by dev_priv->irq_lock. */
821 bool cpu_fifo_underrun_disabled
;
822 bool pch_fifo_underrun_disabled
;
824 /* per-pipe watermark state */
826 /* watermarks currently being used */
828 struct intel_pipe_wm ilk
;
829 struct vlv_wm_state vlv
;
830 struct g4x_wm_state g4x
;
837 unsigned start_vbl_count
;
838 ktime_t start_vbl_time
;
839 int min_vbl
, max_vbl
;
843 /* scalers available on this crtc */
848 struct drm_plane base
;
854 uint32_t frontbuffer_bit
;
857 u32 base
, cntl
, size
;
861 * NOTE: Do not place new plane state fields here (e.g., when adding
862 * new plane properties). New runtime state should now be placed in
863 * the intel_plane_state structure and accessed via plane_state.
866 void (*update_plane
)(struct intel_plane
*plane
,
867 const struct intel_crtc_state
*crtc_state
,
868 const struct intel_plane_state
*plane_state
);
869 void (*disable_plane
)(struct intel_plane
*plane
,
870 struct intel_crtc
*crtc
);
871 int (*check_plane
)(struct intel_plane
*plane
,
872 struct intel_crtc_state
*crtc_state
,
873 struct intel_plane_state
*state
);
876 struct intel_watermark_params
{
884 struct cxsr_latency
{
890 u16 display_hpll_disable
;
892 u16 cursor_hpll_disable
;
895 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
896 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
897 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
898 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
899 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
900 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
901 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
902 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
903 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
909 enum drm_dp_dual_mode_type type
;
914 bool rgb_quant_range_selectable
;
915 struct intel_connector
*attached_connector
;
918 struct intel_dp_mst_encoder
;
919 #define DP_MAX_DOWNSTREAM_PORTS 0x10
923 * When platform provides two set of M_N registers for dp, we can
924 * program them and switch between them incase of DRRS.
925 * But When only one such register is provided, we have to program the
926 * required divider value on that registers itself based on the DRRS state.
928 * M1_N1 : Program dp_m_n on M1_N1 registers
929 * dp_m2_n2 on M2_N2 registers (If supported)
931 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
932 * M2_N2 registers are not supported
936 /* Sets the m1_n1 and m2_n2 */
941 struct intel_dp_compliance_data
{
943 uint8_t video_pattern
;
944 uint16_t hdisplay
, vdisplay
;
948 struct intel_dp_compliance
{
949 unsigned long test_type
;
950 struct intel_dp_compliance_data test_data
;
957 i915_reg_t output_reg
;
958 i915_reg_t aux_ch_ctl_reg
;
959 i915_reg_t aux_ch_data_reg
[5];
967 bool channel_eq_status
;
968 bool reset_link_params
;
969 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
970 uint8_t psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
971 uint8_t downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
972 uint8_t edp_dpcd
[EDP_DISPLAY_CTL_CAP_SIZE
];
974 int num_source_rates
;
975 const int *source_rates
;
976 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
978 int sink_rates
[DP_MAX_SUPPORTED_RATES
];
979 bool use_rate_select
;
980 /* intersection of source and sink rates */
981 int num_common_rates
;
982 int common_rates
[DP_MAX_SUPPORTED_RATES
];
983 /* Max lane count for the current link */
984 int max_link_lane_count
;
985 /* Max rate for the current link */
987 /* sink or branch descriptor */
988 struct drm_dp_desc desc
;
989 struct drm_dp_aux aux
;
990 enum intel_display_power_domain aux_power_domain
;
991 uint8_t train_set
[4];
992 int panel_power_up_delay
;
993 int panel_power_down_delay
;
994 int panel_power_cycle_delay
;
995 int backlight_on_delay
;
996 int backlight_off_delay
;
997 struct delayed_work panel_vdd_work
;
999 unsigned long last_power_on
;
1000 unsigned long last_backlight_off
;
1001 ktime_t panel_power_off_time
;
1003 struct notifier_block edp_notifier
;
1006 * Pipe whose power sequencer is currently locked into
1007 * this port. Only relevant on VLV/CHV.
1011 * Pipe currently driving the port. Used for preventing
1012 * the use of the PPS for any pipe currentrly driving
1013 * external DP as that will mess things up on VLV.
1015 enum pipe active_pipe
;
1017 * Set if the sequencer may be reset due to a power transition,
1018 * requiring a reinitialization. Only relevant on BXT.
1021 struct edp_power_seq pps_delays
;
1023 bool can_mst
; /* this port supports mst */
1025 int active_mst_links
;
1026 /* connector directly attached - won't be use for modeset in mst world */
1027 struct intel_connector
*attached_connector
;
1029 /* mst connector list */
1030 struct intel_dp_mst_encoder
*mst_encoders
[I915_MAX_PIPES
];
1031 struct drm_dp_mst_topology_mgr mst_mgr
;
1033 uint32_t (*get_aux_clock_divider
)(struct intel_dp
*dp
, int index
);
1035 * This function returns the value we have to program the AUX_CTL
1036 * register with to kick off an AUX transaction.
1038 uint32_t (*get_aux_send_ctl
)(struct intel_dp
*dp
,
1041 uint32_t aux_clock_divider
);
1043 /* This is called before a link training is starterd */
1044 void (*prepare_link_retrain
)(struct intel_dp
*intel_dp
);
1046 /* Displayport compliance testing */
1047 struct intel_dp_compliance compliance
;
1050 struct intel_lspcon
{
1052 enum drm_lspcon_mode mode
;
1055 struct intel_digital_port
{
1056 struct intel_encoder base
;
1058 u32 saved_port_bits
;
1060 struct intel_hdmi hdmi
;
1061 struct intel_lspcon lspcon
;
1062 enum irqreturn (*hpd_pulse
)(struct intel_digital_port
*, bool);
1063 bool release_cl2_override
;
1065 enum intel_display_power_domain ddi_io_power_domain
;
1067 void (*write_infoframe
)(struct drm_encoder
*encoder
,
1068 const struct intel_crtc_state
*crtc_state
,
1069 enum hdmi_infoframe_type type
,
1070 const void *frame
, ssize_t len
);
1071 void (*set_infoframes
)(struct drm_encoder
*encoder
,
1073 const struct intel_crtc_state
*crtc_state
,
1074 const struct drm_connector_state
*conn_state
);
1075 bool (*infoframe_enabled
)(struct drm_encoder
*encoder
,
1076 const struct intel_crtc_state
*pipe_config
);
1079 struct intel_dp_mst_encoder
{
1080 struct intel_encoder base
;
1082 struct intel_digital_port
*primary
;
1083 struct intel_connector
*connector
;
1086 static inline enum dpio_channel
1087 vlv_dport_to_channel(struct intel_digital_port
*dport
)
1089 switch (dport
->port
) {
1100 static inline enum dpio_phy
1101 vlv_dport_to_phy(struct intel_digital_port
*dport
)
1103 switch (dport
->port
) {
1114 static inline enum dpio_channel
1115 vlv_pipe_to_channel(enum pipe pipe
)
1128 static inline struct intel_crtc
*
1129 intel_get_crtc_for_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1131 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
1134 static inline struct intel_crtc
*
1135 intel_get_crtc_for_plane(struct drm_i915_private
*dev_priv
, enum plane plane
)
1137 return dev_priv
->plane_to_crtc_mapping
[plane
];
1140 struct intel_load_detect_pipe
{
1141 struct drm_atomic_state
*restore_state
;
1144 static inline struct intel_encoder
*
1145 intel_attached_encoder(struct drm_connector
*connector
)
1147 return to_intel_connector(connector
)->encoder
;
1150 static inline struct intel_digital_port
*
1151 enc_to_dig_port(struct drm_encoder
*encoder
)
1153 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
1155 switch (intel_encoder
->type
) {
1156 case INTEL_OUTPUT_UNKNOWN
:
1157 WARN_ON(!HAS_DDI(to_i915(encoder
->dev
)));
1158 case INTEL_OUTPUT_DP
:
1159 case INTEL_OUTPUT_EDP
:
1160 case INTEL_OUTPUT_HDMI
:
1161 return container_of(encoder
, struct intel_digital_port
,
1168 static inline struct intel_dp_mst_encoder
*
1169 enc_to_mst(struct drm_encoder
*encoder
)
1171 return container_of(encoder
, struct intel_dp_mst_encoder
, base
.base
);
1174 static inline struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
1176 return &enc_to_dig_port(encoder
)->dp
;
1179 static inline struct intel_digital_port
*
1180 dp_to_dig_port(struct intel_dp
*intel_dp
)
1182 return container_of(intel_dp
, struct intel_digital_port
, dp
);
1185 static inline struct intel_lspcon
*
1186 dp_to_lspcon(struct intel_dp
*intel_dp
)
1188 return &dp_to_dig_port(intel_dp
)->lspcon
;
1191 static inline struct intel_digital_port
*
1192 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
1194 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
1197 static inline struct intel_plane_state
*
1198 intel_atomic_get_new_plane_state(struct intel_atomic_state
*state
,
1199 struct intel_plane
*plane
)
1201 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state
->base
,
1205 static inline struct intel_crtc_state
*
1206 intel_atomic_get_old_crtc_state(struct intel_atomic_state
*state
,
1207 struct intel_crtc
*crtc
)
1209 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state
->base
,
1213 static inline struct intel_crtc_state
*
1214 intel_atomic_get_new_crtc_state(struct intel_atomic_state
*state
,
1215 struct intel_crtc
*crtc
)
1217 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state
->base
,
1221 /* intel_fifo_underrun.c */
1222 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
1223 enum pipe pipe
, bool enable
);
1224 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
1225 enum pipe pch_transcoder
,
1227 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
1229 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
1230 enum pipe pch_transcoder
);
1231 void intel_check_cpu_fifo_underruns(struct drm_i915_private
*dev_priv
);
1232 void intel_check_pch_fifo_underruns(struct drm_i915_private
*dev_priv
);
1235 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1236 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1237 void gen6_mask_pm_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
1238 void gen6_unmask_pm_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
1239 void gen6_reset_rps_interrupts(struct drm_i915_private
*dev_priv
);
1240 void gen6_enable_rps_interrupts(struct drm_i915_private
*dev_priv
);
1241 void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv
);
1243 static inline u32
gen6_sanitize_rps_pm_mask(const struct drm_i915_private
*i915
,
1246 return mask
& ~i915
->gt_pm
.rps
.pm_intrmsk_mbz
;
1249 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
);
1250 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
);
1251 static inline bool intel_irqs_enabled(struct drm_i915_private
*dev_priv
)
1254 * We only use drm_irq_uninstall() at unload and VT switch, so
1255 * this is the only thing we need to check.
1257 return dev_priv
->runtime_pm
.irqs_enabled
;
1260 int intel_get_crtc_scanline(struct intel_crtc
*crtc
);
1261 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
1263 void gen8_irq_power_well_pre_disable(struct drm_i915_private
*dev_priv
,
1265 void gen9_reset_guc_interrupts(struct drm_i915_private
*dev_priv
);
1266 void gen9_enable_guc_interrupts(struct drm_i915_private
*dev_priv
);
1267 void gen9_disable_guc_interrupts(struct drm_i915_private
*dev_priv
);
1270 void intel_crt_init(struct drm_i915_private
*dev_priv
);
1271 void intel_crt_reset(struct drm_encoder
*encoder
);
1274 void intel_ddi_fdi_post_disable(struct intel_encoder
*intel_encoder
,
1275 const struct intel_crtc_state
*old_crtc_state
,
1276 const struct drm_connector_state
*old_conn_state
);
1277 void hsw_fdi_link_train(struct intel_crtc
*crtc
,
1278 const struct intel_crtc_state
*crtc_state
);
1279 void intel_ddi_init(struct drm_i915_private
*dev_priv
, enum port port
);
1280 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
);
1281 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
, enum pipe
*pipe
);
1282 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state
*crtc_state
);
1283 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1284 enum transcoder cpu_transcoder
);
1285 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state
*crtc_state
);
1286 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state
*crtc_state
);
1287 struct intel_encoder
*
1288 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state
*crtc_state
);
1289 void intel_ddi_set_pipe_settings(const struct intel_crtc_state
*crtc_state
);
1290 void intel_ddi_prepare_link_retrain(struct intel_dp
*intel_dp
);
1291 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
);
1292 bool intel_ddi_is_audio_enabled(struct drm_i915_private
*dev_priv
,
1293 struct intel_crtc
*intel_crtc
);
1294 void intel_ddi_get_config(struct intel_encoder
*encoder
,
1295 struct intel_crtc_state
*pipe_config
);
1297 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
1298 struct intel_crtc_state
*pipe_config
);
1299 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state
*crtc_state
,
1301 u32
bxt_signal_levels(struct intel_dp
*intel_dp
);
1302 uint32_t ddi_signal_levels(struct intel_dp
*intel_dp
);
1303 u8
intel_ddi_dp_voltage_max(struct intel_encoder
*encoder
);
1305 unsigned int intel_fb_align_height(const struct drm_framebuffer
*fb
,
1306 int plane
, unsigned int height
);
1309 void intel_init_audio_hooks(struct drm_i915_private
*dev_priv
);
1310 void intel_audio_codec_enable(struct intel_encoder
*encoder
,
1311 const struct intel_crtc_state
*crtc_state
,
1312 const struct drm_connector_state
*conn_state
);
1313 void intel_audio_codec_disable(struct intel_encoder
*encoder
);
1314 void i915_audio_component_init(struct drm_i915_private
*dev_priv
);
1315 void i915_audio_component_cleanup(struct drm_i915_private
*dev_priv
);
1316 void intel_audio_init(struct drm_i915_private
*dev_priv
);
1317 void intel_audio_deinit(struct drm_i915_private
*dev_priv
);
1320 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state
*crtc_state
);
1321 void skl_init_cdclk(struct drm_i915_private
*dev_priv
);
1322 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1323 void cnl_init_cdclk(struct drm_i915_private
*dev_priv
);
1324 void cnl_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1325 void bxt_init_cdclk(struct drm_i915_private
*dev_priv
);
1326 void bxt_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1327 void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv
);
1328 void intel_update_max_cdclk(struct drm_i915_private
*dev_priv
);
1329 void intel_update_cdclk(struct drm_i915_private
*dev_priv
);
1330 void intel_update_rawclk(struct drm_i915_private
*dev_priv
);
1331 bool intel_cdclk_state_compare(const struct intel_cdclk_state
*a
,
1332 const struct intel_cdclk_state
*b
);
1333 void intel_set_cdclk(struct drm_i915_private
*dev_priv
,
1334 const struct intel_cdclk_state
*cdclk_state
);
1336 /* intel_display.c */
1337 void i830_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
);
1338 void i830_disable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
);
1339 enum pipe
intel_crtc_pch_transcoder(struct intel_crtc
*crtc
);
1340 void intel_update_rawclk(struct drm_i915_private
*dev_priv
);
1341 int vlv_get_hpll_vco(struct drm_i915_private
*dev_priv
);
1342 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
1343 const char *name
, u32 reg
, int ref_freq
);
1344 int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv
,
1345 const char *name
, u32 reg
);
1346 void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
);
1347 void lpt_disable_iclkip(struct drm_i915_private
*dev_priv
);
1348 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
);
1349 unsigned int intel_fb_xy_to_linear(int x
, int y
,
1350 const struct intel_plane_state
*state
,
1352 void intel_add_fb_offsets(int *x
, int *y
,
1353 const struct intel_plane_state
*state
, int plane
);
1354 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
);
1355 bool intel_has_pending_fb_unpin(struct drm_i915_private
*dev_priv
);
1356 void intel_mark_busy(struct drm_i915_private
*dev_priv
);
1357 void intel_mark_idle(struct drm_i915_private
*dev_priv
);
1358 int intel_display_suspend(struct drm_device
*dev
);
1359 void intel_pps_unlock_regs_wa(struct drm_i915_private
*dev_priv
);
1360 void intel_encoder_destroy(struct drm_encoder
*encoder
);
1361 int intel_connector_init(struct intel_connector
*);
1362 struct intel_connector
*intel_connector_alloc(void);
1363 bool intel_connector_get_hw_state(struct intel_connector
*connector
);
1364 void intel_connector_attach_encoder(struct intel_connector
*connector
,
1365 struct intel_encoder
*encoder
);
1366 struct drm_display_mode
*
1367 intel_encoder_current_mode(struct intel_encoder
*encoder
);
1369 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
);
1370 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
1371 struct drm_file
*file_priv
);
1372 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1375 intel_crtc_has_type(const struct intel_crtc_state
*crtc_state
,
1376 enum intel_output_type type
)
1378 return crtc_state
->output_types
& (1 << type
);
1381 intel_crtc_has_dp_encoder(const struct intel_crtc_state
*crtc_state
)
1383 return crtc_state
->output_types
&
1384 ((1 << INTEL_OUTPUT_DP
) |
1385 (1 << INTEL_OUTPUT_DP_MST
) |
1386 (1 << INTEL_OUTPUT_EDP
));
1389 intel_wait_for_vblank(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1391 drm_wait_one_vblank(&dev_priv
->drm
, pipe
);
1394 intel_wait_for_vblank_if_active(struct drm_i915_private
*dev_priv
, int pipe
)
1396 const struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
1399 intel_wait_for_vblank(dev_priv
, pipe
);
1402 u32
intel_crtc_get_vblank_counter(struct intel_crtc
*crtc
);
1404 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
);
1405 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1406 struct intel_digital_port
*dport
,
1407 unsigned int expected_mask
);
1408 int intel_get_load_detect_pipe(struct drm_connector
*connector
,
1409 const struct drm_display_mode
*mode
,
1410 struct intel_load_detect_pipe
*old
,
1411 struct drm_modeset_acquire_ctx
*ctx
);
1412 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
1413 struct intel_load_detect_pipe
*old
,
1414 struct drm_modeset_acquire_ctx
*ctx
);
1416 intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
, unsigned int rotation
);
1417 void intel_unpin_fb_vma(struct i915_vma
*vma
);
1418 struct drm_framebuffer
*
1419 intel_framebuffer_create(struct drm_i915_gem_object
*obj
,
1420 struct drm_mode_fb_cmd2
*mode_cmd
);
1421 int intel_prepare_plane_fb(struct drm_plane
*plane
,
1422 struct drm_plane_state
*new_state
);
1423 void intel_cleanup_plane_fb(struct drm_plane
*plane
,
1424 struct drm_plane_state
*old_state
);
1425 int intel_plane_atomic_get_property(struct drm_plane
*plane
,
1426 const struct drm_plane_state
*state
,
1427 struct drm_property
*property
,
1429 int intel_plane_atomic_set_property(struct drm_plane
*plane
,
1430 struct drm_plane_state
*state
,
1431 struct drm_property
*property
,
1433 int intel_plane_atomic_calc_changes(const struct intel_crtc_state
*old_crtc_state
,
1434 struct drm_crtc_state
*crtc_state
,
1435 const struct intel_plane_state
*old_plane_state
,
1436 struct drm_plane_state
*plane_state
);
1438 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1441 int vlv_force_pll_on(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1442 const struct dpll
*dpll
);
1443 void vlv_force_pll_off(struct drm_i915_private
*dev_priv
, enum pipe pipe
);
1444 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
);
1446 /* modesetting asserts */
1447 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1449 void assert_pll(struct drm_i915_private
*dev_priv
,
1450 enum pipe pipe
, bool state
);
1451 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1452 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1453 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
);
1454 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1455 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1456 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1457 enum pipe pipe
, bool state
);
1458 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1459 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1460 void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool state
);
1461 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1462 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1463 u32
intel_compute_tile_offset(int *x
, int *y
,
1464 const struct intel_plane_state
*state
, int plane
);
1465 void intel_prepare_reset(struct drm_i915_private
*dev_priv
);
1466 void intel_finish_reset(struct drm_i915_private
*dev_priv
);
1467 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
);
1468 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
);
1469 void gen9_sanitize_dc_state(struct drm_i915_private
*dev_priv
);
1470 void bxt_enable_dc9(struct drm_i915_private
*dev_priv
);
1471 void bxt_disable_dc9(struct drm_i915_private
*dev_priv
);
1472 void gen9_enable_dc5(struct drm_i915_private
*dev_priv
);
1473 unsigned int skl_cdclk_get_vco(unsigned int freq
);
1474 void skl_enable_dc6(struct drm_i915_private
*dev_priv
);
1475 void skl_disable_dc6(struct drm_i915_private
*dev_priv
);
1476 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
1477 struct intel_crtc_state
*pipe_config
);
1478 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
);
1479 int intel_dotclock_calculate(int link_freq
, const struct intel_link_m_n
*m_n
);
1480 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
1481 struct dpll
*best_clock
);
1482 int chv_calc_dpll_params(int refclk
, struct dpll
*pll_clock
);
1484 bool intel_crtc_active(struct intel_crtc
*crtc
);
1485 void hsw_enable_ips(struct intel_crtc
*crtc
);
1486 void hsw_disable_ips(struct intel_crtc
*crtc
);
1487 enum intel_display_power_domain
intel_port_to_power_domain(enum port port
);
1488 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
1489 struct intel_crtc_state
*pipe_config
);
1491 int skl_update_scaler_crtc(struct intel_crtc_state
*crtc_state
);
1492 int skl_max_scale(struct intel_crtc
*crtc
, struct intel_crtc_state
*crtc_state
);
1494 static inline u32
intel_plane_ggtt_offset(const struct intel_plane_state
*state
)
1496 return i915_ggtt_offset(state
->vma
);
1499 u32
skl_plane_ctl(const struct intel_crtc_state
*crtc_state
,
1500 const struct intel_plane_state
*plane_state
);
1501 u32
skl_plane_stride(const struct drm_framebuffer
*fb
, int plane
,
1502 unsigned int rotation
);
1503 int skl_check_plane_surface(struct intel_plane_state
*plane_state
);
1504 int i9xx_check_plane_surface(struct intel_plane_state
*plane_state
);
1507 void intel_csr_ucode_init(struct drm_i915_private
*);
1508 void intel_csr_load_program(struct drm_i915_private
*);
1509 void intel_csr_ucode_fini(struct drm_i915_private
*);
1510 void intel_csr_ucode_suspend(struct drm_i915_private
*);
1511 void intel_csr_ucode_resume(struct drm_i915_private
*);
1514 bool intel_dp_init(struct drm_i915_private
*dev_priv
, i915_reg_t output_reg
,
1516 bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
1517 struct intel_connector
*intel_connector
);
1518 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1519 int link_rate
, uint8_t lane_count
,
1521 int intel_dp_get_link_train_fallback_values(struct intel_dp
*intel_dp
,
1522 int link_rate
, uint8_t lane_count
);
1523 void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
1524 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
);
1525 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
1526 void intel_dp_encoder_reset(struct drm_encoder
*encoder
);
1527 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
);
1528 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
);
1529 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
);
1530 bool intel_dp_compute_config(struct intel_encoder
*encoder
,
1531 struct intel_crtc_state
*pipe_config
,
1532 struct drm_connector_state
*conn_state
);
1533 bool intel_dp_is_edp(struct intel_dp
*intel_dp
);
1534 bool intel_dp_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
1535 enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
,
1537 void intel_edp_backlight_on(const struct intel_crtc_state
*crtc_state
,
1538 const struct drm_connector_state
*conn_state
);
1539 void intel_edp_backlight_off(const struct drm_connector_state
*conn_state
);
1540 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
1541 void intel_edp_panel_on(struct intel_dp
*intel_dp
);
1542 void intel_edp_panel_off(struct intel_dp
*intel_dp
);
1543 void intel_dp_mst_suspend(struct drm_device
*dev
);
1544 void intel_dp_mst_resume(struct drm_device
*dev
);
1545 int intel_dp_max_link_rate(struct intel_dp
*intel_dp
);
1546 int intel_dp_max_lane_count(struct intel_dp
*intel_dp
);
1547 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
);
1548 void intel_dp_hot_plug(struct intel_encoder
*intel_encoder
);
1549 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
);
1550 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
);
1551 void intel_plane_destroy(struct drm_plane
*plane
);
1552 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
1553 const struct intel_crtc_state
*crtc_state
);
1554 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
1555 const struct intel_crtc_state
*crtc_state
);
1556 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
1557 unsigned int frontbuffer_bits
);
1558 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
1559 unsigned int frontbuffer_bits
);
1562 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
1563 uint8_t dp_train_pat
);
1565 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
);
1566 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
);
1568 intel_dp_voltage_max(struct intel_dp
*intel_dp
);
1570 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
);
1571 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1572 uint8_t *link_bw
, uint8_t *rate_select
);
1573 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
);
1575 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
]);
1577 static inline unsigned int intel_dp_unused_lane_mask(int lane_count
)
1579 return ~((1 << lane_count
) - 1) & 0xf;
1582 bool intel_dp_read_dpcd(struct intel_dp
*intel_dp
);
1583 int intel_dp_link_required(int pixel_clock
, int bpp
);
1584 int intel_dp_max_data_rate(int max_link_clock
, int max_lanes
);
1585 bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
1586 struct intel_digital_port
*port
);
1588 /* intel_dp_aux_backlight.c */
1589 int intel_dp_aux_init_backlight_funcs(struct intel_connector
*intel_connector
);
1591 /* intel_dp_mst.c */
1592 int intel_dp_mst_encoder_init(struct intel_digital_port
*intel_dig_port
, int conn_id
);
1593 void intel_dp_mst_encoder_cleanup(struct intel_digital_port
*intel_dig_port
);
1595 void intel_dsi_init(struct drm_i915_private
*dev_priv
);
1597 /* intel_dsi_dcs_backlight.c */
1598 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector
*intel_connector
);
1601 void intel_dvo_init(struct drm_i915_private
*dev_priv
);
1602 /* intel_hotplug.c */
1603 void intel_hpd_poll_init(struct drm_i915_private
*dev_priv
);
1606 /* legacy fbdev emulation in intel_fbdev.c */
1607 #ifdef CONFIG_DRM_FBDEV_EMULATION
1608 extern int intel_fbdev_init(struct drm_device
*dev
);
1609 extern void intel_fbdev_initial_config_async(struct drm_device
*dev
);
1610 extern void intel_fbdev_unregister(struct drm_i915_private
*dev_priv
);
1611 extern void intel_fbdev_fini(struct drm_i915_private
*dev_priv
);
1612 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
);
1613 extern void intel_fbdev_output_poll_changed(struct drm_device
*dev
);
1614 extern void intel_fbdev_restore_mode(struct drm_device
*dev
);
1616 static inline int intel_fbdev_init(struct drm_device
*dev
)
1621 static inline void intel_fbdev_initial_config_async(struct drm_device
*dev
)
1625 static inline void intel_fbdev_unregister(struct drm_i915_private
*dev_priv
)
1629 static inline void intel_fbdev_fini(struct drm_i915_private
*dev_priv
)
1633 static inline void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
)
1637 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
1641 static inline void intel_fbdev_restore_mode(struct drm_device
*dev
)
1647 void intel_fbc_choose_crtc(struct drm_i915_private
*dev_priv
,
1648 struct drm_atomic_state
*state
);
1649 bool intel_fbc_is_active(struct drm_i915_private
*dev_priv
);
1650 void intel_fbc_pre_update(struct intel_crtc
*crtc
,
1651 struct intel_crtc_state
*crtc_state
,
1652 struct intel_plane_state
*plane_state
);
1653 void intel_fbc_post_update(struct intel_crtc
*crtc
);
1654 void intel_fbc_init(struct drm_i915_private
*dev_priv
);
1655 void intel_fbc_init_pipe_state(struct drm_i915_private
*dev_priv
);
1656 void intel_fbc_enable(struct intel_crtc
*crtc
,
1657 struct intel_crtc_state
*crtc_state
,
1658 struct intel_plane_state
*plane_state
);
1659 void intel_fbc_disable(struct intel_crtc
*crtc
);
1660 void intel_fbc_global_disable(struct drm_i915_private
*dev_priv
);
1661 void intel_fbc_invalidate(struct drm_i915_private
*dev_priv
,
1662 unsigned int frontbuffer_bits
,
1663 enum fb_op_origin origin
);
1664 void intel_fbc_flush(struct drm_i915_private
*dev_priv
,
1665 unsigned int frontbuffer_bits
, enum fb_op_origin origin
);
1666 void intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
);
1667 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private
*dev_priv
);
1670 void intel_hdmi_init(struct drm_i915_private
*dev_priv
, i915_reg_t hdmi_reg
,
1672 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
1673 struct intel_connector
*intel_connector
);
1674 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
);
1675 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
1676 struct intel_crtc_state
*pipe_config
,
1677 struct drm_connector_state
*conn_state
);
1678 void intel_hdmi_handle_sink_scrambling(struct intel_encoder
*intel_encoder
,
1679 struct drm_connector
*connector
,
1680 bool high_tmds_clock_ratio
,
1682 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi
*hdmi
, bool enable
);
1683 void intel_infoframe_init(struct intel_digital_port
*intel_dig_port
);
1687 void intel_lvds_init(struct drm_i915_private
*dev_priv
);
1688 struct intel_encoder
*intel_get_lvds_encoder(struct drm_device
*dev
);
1689 bool intel_is_dual_link_lvds(struct drm_device
*dev
);
1693 int intel_connector_update_modes(struct drm_connector
*connector
,
1695 int intel_ddc_get_modes(struct drm_connector
*c
, struct i2c_adapter
*adapter
);
1696 void intel_attach_force_audio_property(struct drm_connector
*connector
);
1697 void intel_attach_broadcast_rgb_property(struct drm_connector
*connector
);
1698 void intel_attach_aspect_ratio_property(struct drm_connector
*connector
);
1701 /* intel_overlay.c */
1702 void intel_setup_overlay(struct drm_i915_private
*dev_priv
);
1703 void intel_cleanup_overlay(struct drm_i915_private
*dev_priv
);
1704 int intel_overlay_switch_off(struct intel_overlay
*overlay
);
1705 int intel_overlay_put_image_ioctl(struct drm_device
*dev
, void *data
,
1706 struct drm_file
*file_priv
);
1707 int intel_overlay_attrs_ioctl(struct drm_device
*dev
, void *data
,
1708 struct drm_file
*file_priv
);
1709 void intel_overlay_reset(struct drm_i915_private
*dev_priv
);
1713 int intel_panel_init(struct intel_panel
*panel
,
1714 struct drm_display_mode
*fixed_mode
,
1715 struct drm_display_mode
*alt_fixed_mode
,
1716 struct drm_display_mode
*downclock_mode
);
1717 void intel_panel_fini(struct intel_panel
*panel
);
1718 void intel_fixed_panel_mode(const struct drm_display_mode
*fixed_mode
,
1719 struct drm_display_mode
*adjusted_mode
);
1720 void intel_pch_panel_fitting(struct intel_crtc
*crtc
,
1721 struct intel_crtc_state
*pipe_config
,
1723 void intel_gmch_panel_fitting(struct intel_crtc
*crtc
,
1724 struct intel_crtc_state
*pipe_config
,
1726 void intel_panel_set_backlight_acpi(const struct drm_connector_state
*conn_state
,
1727 u32 level
, u32 max
);
1728 int intel_panel_setup_backlight(struct drm_connector
*connector
,
1730 void intel_panel_enable_backlight(const struct intel_crtc_state
*crtc_state
,
1731 const struct drm_connector_state
*conn_state
);
1732 void intel_panel_disable_backlight(const struct drm_connector_state
*old_conn_state
);
1733 void intel_panel_destroy_backlight(struct drm_connector
*connector
);
1734 enum drm_connector_status
intel_panel_detect(struct drm_i915_private
*dev_priv
);
1735 extern struct drm_display_mode
*intel_find_panel_downclock(
1736 struct drm_i915_private
*dev_priv
,
1737 struct drm_display_mode
*fixed_mode
,
1738 struct drm_connector
*connector
);
1740 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1741 int intel_backlight_device_register(struct intel_connector
*connector
);
1742 void intel_backlight_device_unregister(struct intel_connector
*connector
);
1743 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1744 static int intel_backlight_device_register(struct intel_connector
*connector
)
1748 static inline void intel_backlight_device_unregister(struct intel_connector
*connector
)
1751 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1755 void intel_psr_enable(struct intel_dp
*intel_dp
,
1756 const struct intel_crtc_state
*crtc_state
);
1757 void intel_psr_disable(struct intel_dp
*intel_dp
,
1758 const struct intel_crtc_state
*old_crtc_state
);
1759 void intel_psr_invalidate(struct drm_i915_private
*dev_priv
,
1760 unsigned frontbuffer_bits
);
1761 void intel_psr_flush(struct drm_i915_private
*dev_priv
,
1762 unsigned frontbuffer_bits
,
1763 enum fb_op_origin origin
);
1764 void intel_psr_init(struct drm_i915_private
*dev_priv
);
1765 void intel_psr_single_frame_update(struct drm_i915_private
*dev_priv
,
1766 unsigned frontbuffer_bits
);
1768 /* intel_runtime_pm.c */
1769 int intel_power_domains_init(struct drm_i915_private
*);
1770 void intel_power_domains_fini(struct drm_i915_private
*);
1771 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
, bool resume
);
1772 void intel_power_domains_suspend(struct drm_i915_private
*dev_priv
);
1773 void intel_power_domains_verify_state(struct drm_i915_private
*dev_priv
);
1774 void bxt_display_core_init(struct drm_i915_private
*dev_priv
, bool resume
);
1775 void bxt_display_core_uninit(struct drm_i915_private
*dev_priv
);
1776 void intel_runtime_pm_enable(struct drm_i915_private
*dev_priv
);
1778 intel_display_power_domain_str(enum intel_display_power_domain domain
);
1780 bool intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1781 enum intel_display_power_domain domain
);
1782 bool __intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1783 enum intel_display_power_domain domain
);
1784 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
1785 enum intel_display_power_domain domain
);
1786 bool intel_display_power_get_if_enabled(struct drm_i915_private
*dev_priv
,
1787 enum intel_display_power_domain domain
);
1788 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
1789 enum intel_display_power_domain domain
);
1792 assert_rpm_device_not_suspended(struct drm_i915_private
*dev_priv
)
1794 WARN_ONCE(dev_priv
->runtime_pm
.suspended
,
1795 "Device suspended during HW access\n");
1799 assert_rpm_wakelock_held(struct drm_i915_private
*dev_priv
)
1801 assert_rpm_device_not_suspended(dev_priv
);
1802 WARN_ONCE(!atomic_read(&dev_priv
->runtime_pm
.wakeref_count
),
1803 "RPM wakelock ref not held during HW access");
1807 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1808 * @dev_priv: i915 device instance
1810 * This function disable asserts that check if we hold an RPM wakelock
1811 * reference, while keeping the device-not-suspended checks still enabled.
1812 * It's meant to be used only in special circumstances where our rule about
1813 * the wakelock refcount wrt. the device power state doesn't hold. According
1814 * to this rule at any point where we access the HW or want to keep the HW in
1815 * an active state we must hold an RPM wakelock reference acquired via one of
1816 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1817 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1818 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1819 * users should avoid using this function.
1821 * Any calls to this function must have a symmetric call to
1822 * enable_rpm_wakeref_asserts().
1825 disable_rpm_wakeref_asserts(struct drm_i915_private
*dev_priv
)
1827 atomic_inc(&dev_priv
->runtime_pm
.wakeref_count
);
1831 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1832 * @dev_priv: i915 device instance
1834 * This function re-enables the RPM assert checks after disabling them with
1835 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1836 * circumstances otherwise its use should be avoided.
1838 * Any calls to this function must have a symmetric call to
1839 * disable_rpm_wakeref_asserts().
1842 enable_rpm_wakeref_asserts(struct drm_i915_private
*dev_priv
)
1844 atomic_dec(&dev_priv
->runtime_pm
.wakeref_count
);
1847 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
);
1848 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private
*dev_priv
);
1849 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
);
1850 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
);
1852 void intel_display_set_init_power(struct drm_i915_private
*dev
, bool enable
);
1854 void chv_phy_powergate_lanes(struct intel_encoder
*encoder
,
1855 bool override
, unsigned int mask
);
1856 bool chv_phy_powergate_ch(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
,
1857 enum dpio_channel ch
, bool override
);
1861 void intel_init_clock_gating(struct drm_i915_private
*dev_priv
);
1862 void intel_suspend_hw(struct drm_i915_private
*dev_priv
);
1863 int ilk_wm_max_level(const struct drm_i915_private
*dev_priv
);
1864 void intel_update_watermarks(struct intel_crtc
*crtc
);
1865 void intel_init_pm(struct drm_i915_private
*dev_priv
);
1866 void intel_init_clock_gating_hooks(struct drm_i915_private
*dev_priv
);
1867 void intel_pm_setup(struct drm_i915_private
*dev_priv
);
1868 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
1869 void intel_gpu_ips_teardown(void);
1870 void intel_init_gt_powersave(struct drm_i915_private
*dev_priv
);
1871 void intel_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
);
1872 void intel_sanitize_gt_powersave(struct drm_i915_private
*dev_priv
);
1873 void intel_enable_gt_powersave(struct drm_i915_private
*dev_priv
);
1874 void intel_autoenable_gt_powersave(struct drm_i915_private
*dev_priv
);
1875 void intel_disable_gt_powersave(struct drm_i915_private
*dev_priv
);
1876 void intel_suspend_gt_powersave(struct drm_i915_private
*dev_priv
);
1877 void gen6_rps_busy(struct drm_i915_private
*dev_priv
);
1878 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
);
1879 void gen6_rps_idle(struct drm_i915_private
*dev_priv
);
1880 void gen6_rps_boost(struct drm_i915_gem_request
*rq
,
1881 struct intel_rps_client
*rps
);
1882 void g4x_wm_get_hw_state(struct drm_device
*dev
);
1883 void vlv_wm_get_hw_state(struct drm_device
*dev
);
1884 void ilk_wm_get_hw_state(struct drm_device
*dev
);
1885 void skl_wm_get_hw_state(struct drm_device
*dev
);
1886 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
1887 struct skl_ddb_allocation
*ddb
/* out */);
1888 void skl_pipe_wm_get_hw_state(struct drm_crtc
*crtc
,
1889 struct skl_pipe_wm
*out
);
1890 void g4x_wm_sanitize(struct drm_i915_private
*dev_priv
);
1891 void vlv_wm_sanitize(struct drm_i915_private
*dev_priv
);
1892 bool intel_can_enable_sagv(struct drm_atomic_state
*state
);
1893 int intel_enable_sagv(struct drm_i915_private
*dev_priv
);
1894 int intel_disable_sagv(struct drm_i915_private
*dev_priv
);
1895 bool skl_wm_level_equals(const struct skl_wm_level
*l1
,
1896 const struct skl_wm_level
*l2
);
1897 bool skl_ddb_allocation_overlaps(struct drm_i915_private
*dev_priv
,
1898 const struct skl_ddb_entry
**entries
,
1899 const struct skl_ddb_entry
*ddb
,
1901 bool ilk_disable_lp_wm(struct drm_device
*dev
);
1902 int sanitize_rc6_option(struct drm_i915_private
*dev_priv
, int enable_rc6
);
1903 int skl_check_pipe_max_pixel_rate(struct intel_crtc
*intel_crtc
,
1904 struct intel_crtc_state
*cstate
);
1905 void intel_init_ipc(struct drm_i915_private
*dev_priv
);
1906 void intel_enable_ipc(struct drm_i915_private
*dev_priv
);
1907 static inline int intel_rc6_enabled(void)
1909 return i915_modparams
.enable_rc6
;
1913 bool intel_sdvo_init(struct drm_i915_private
*dev_priv
,
1914 i915_reg_t reg
, enum port port
);
1917 /* intel_sprite.c */
1918 int intel_usecs_to_scanlines(const struct drm_display_mode
*adjusted_mode
,
1920 struct intel_plane
*intel_sprite_plane_create(struct drm_i915_private
*dev_priv
,
1921 enum pipe pipe
, int plane
);
1922 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
1923 struct drm_file
*file_priv
);
1924 void intel_pipe_update_start(const struct intel_crtc_state
*new_crtc_state
);
1925 void intel_pipe_update_end(struct intel_crtc_state
*new_crtc_state
);
1928 void intel_tv_init(struct drm_i915_private
*dev_priv
);
1930 /* intel_atomic.c */
1931 int intel_digital_connector_atomic_get_property(struct drm_connector
*connector
,
1932 const struct drm_connector_state
*state
,
1933 struct drm_property
*property
,
1935 int intel_digital_connector_atomic_set_property(struct drm_connector
*connector
,
1936 struct drm_connector_state
*state
,
1937 struct drm_property
*property
,
1939 int intel_digital_connector_atomic_check(struct drm_connector
*conn
,
1940 struct drm_connector_state
*new_state
);
1941 struct drm_connector_state
*
1942 intel_digital_connector_duplicate_state(struct drm_connector
*connector
);
1944 struct drm_crtc_state
*intel_crtc_duplicate_state(struct drm_crtc
*crtc
);
1945 void intel_crtc_destroy_state(struct drm_crtc
*crtc
,
1946 struct drm_crtc_state
*state
);
1947 struct drm_atomic_state
*intel_atomic_state_alloc(struct drm_device
*dev
);
1948 void intel_atomic_state_clear(struct drm_atomic_state
*);
1950 static inline struct intel_crtc_state
*
1951 intel_atomic_get_crtc_state(struct drm_atomic_state
*state
,
1952 struct intel_crtc
*crtc
)
1954 struct drm_crtc_state
*crtc_state
;
1955 crtc_state
= drm_atomic_get_crtc_state(state
, &crtc
->base
);
1956 if (IS_ERR(crtc_state
))
1957 return ERR_CAST(crtc_state
);
1959 return to_intel_crtc_state(crtc_state
);
1962 static inline struct intel_crtc_state
*
1963 intel_atomic_get_existing_crtc_state(struct drm_atomic_state
*state
,
1964 struct intel_crtc
*crtc
)
1966 struct drm_crtc_state
*crtc_state
;
1968 crtc_state
= drm_atomic_get_existing_crtc_state(state
, &crtc
->base
);
1971 return to_intel_crtc_state(crtc_state
);
1976 static inline struct intel_plane_state
*
1977 intel_atomic_get_existing_plane_state(struct drm_atomic_state
*state
,
1978 struct intel_plane
*plane
)
1980 struct drm_plane_state
*plane_state
;
1982 plane_state
= drm_atomic_get_existing_plane_state(state
, &plane
->base
);
1984 return to_intel_plane_state(plane_state
);
1987 int intel_atomic_setup_scalers(struct drm_i915_private
*dev_priv
,
1988 struct intel_crtc
*intel_crtc
,
1989 struct intel_crtc_state
*crtc_state
);
1991 /* intel_atomic_plane.c */
1992 struct intel_plane_state
*intel_create_plane_state(struct drm_plane
*plane
);
1993 struct drm_plane_state
*intel_plane_duplicate_state(struct drm_plane
*plane
);
1994 void intel_plane_destroy_state(struct drm_plane
*plane
,
1995 struct drm_plane_state
*state
);
1996 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs
;
1997 int intel_plane_atomic_check_with_state(const struct intel_crtc_state
*old_crtc_state
,
1998 struct intel_crtc_state
*crtc_state
,
1999 const struct intel_plane_state
*old_plane_state
,
2000 struct intel_plane_state
*intel_state
);
2003 void intel_color_init(struct drm_crtc
*crtc
);
2004 int intel_color_check(struct drm_crtc
*crtc
, struct drm_crtc_state
*state
);
2005 void intel_color_set_csc(struct drm_crtc_state
*crtc_state
);
2006 void intel_color_load_luts(struct drm_crtc_state
*crtc_state
);
2008 /* intel_lspcon.c */
2009 bool lspcon_init(struct intel_digital_port
*intel_dig_port
);
2010 void lspcon_resume(struct intel_lspcon
*lspcon
);
2011 void lspcon_wait_pcon_mode(struct intel_lspcon
*lspcon
);
2013 /* intel_pipe_crc.c */
2014 int intel_pipe_crc_create(struct drm_minor
*minor
);
2015 #ifdef CONFIG_DEBUG_FS
2016 int intel_crtc_set_crc_source(struct drm_crtc
*crtc
, const char *source_name
,
2017 size_t *values_cnt
);
2019 #define intel_crtc_set_crc_source NULL
2021 extern const struct file_operations i915_display_crc_ctl_fops
;
2022 #endif /* __INTEL_DRV_H__ */