drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_dual_mode_helper.h>
  37 #include <drm/drm_dp_mst_helper.h>
  38 #include <drm/drm_rect.h>
  39 #include <drm/drm_atomic.h>
  40
  41 /**
  42  * _wait_for - magic (register) wait macro
  43  *
  44  * Does the right thing for modeset paths when run under kdgb or similar atomic
  45  * contexts. Note that it's important that we check the condition again after
  46  * having timed out, since the timeout could be due to preemption or similar and
  47  * we've never had a chance to check the condition before the timeout.
  48  *
  49  * TODO: When modesetting has fully transitioned to atomic, the below
  50  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  51  * added.
  52  */
  53 #define _wait_for(COND, US, W) ({ \
  54         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  55         int ret__;                                                      \
  56         for (;;) {                                                      \
  57                 bool expired__ = time_after(jiffies, timeout__);        \
  58                 if (COND) {                                             \
  59                         ret__ = 0;                                      \
  60                         break;                                          \
  61                 }                                                       \
  62                 if (expired__) {                                        \
  63                         ret__ = -ETIMEDOUT;                             \
  64                         break;                                          \
  65                 }                                                       \
  66                 if ((W) && drm_can_sleep()) {                           \
  67                         usleep_range((W), (W)*2);                       \
  68                 } else {                                                \
  69                         cpu_relax();                                    \
  70                 }                                                       \
  71         }                                                               \
  72         ret__;                                                          \
  73 })
  74
  75 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  76
  77 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  78 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  79 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  80 #else
  81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  82 #endif
  83
  84 #define _wait_for_atomic(COND, US, ATOMIC) \
  85 ({ \
  86         int cpu, ret, timeout = (US) * 1000; \
  87         u64 base; \
  88         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  89         BUILD_BUG_ON((US) > 50000); \
  90         if (!(ATOMIC)) { \
  91                 preempt_disable(); \
  92                 cpu = smp_processor_id(); \
  93         } \
  94         base = local_clock(); \
  95         for (;;) { \
  96                 u64 now = local_clock(); \
  97                 if (!(ATOMIC)) \
  98                         preempt_enable(); \
  99                 if (COND) { \
 100                         ret = 0; \
 101                         break; \
 102                 } \
 103                 if (now - base >= timeout) { \
 104                         ret = -ETIMEDOUT; \
 105                         break; \
 106                 } \
 107                 cpu_relax(); \
 108                 if (!(ATOMIC)) { \
 109                         preempt_disable(); \
 110                         if (unlikely(cpu != smp_processor_id())) { \
 111                                 timeout -= now - base; \
 112                                 cpu = smp_processor_id(); \
 113                                 base = local_clock(); \
 114                         } \
 115                 } \
 116         } \
 117         ret; \
 118 })
 119
 120 #define wait_for_us(COND, US) \
 121 ({ \
 122         int ret__; \
 123         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 124         if ((US) > 10) \
 125                 ret__ = _wait_for((COND), (US), 10); \
 126         else \
 127                 ret__ = _wait_for_atomic((COND), (US), 0); \
 128         ret__; \
 129 })
 130
 131 #define wait_for_atomic(COND, MS)       _wait_for_atomic((COND), (MS) * 1000, 1)
 132 #define wait_for_atomic_us(COND, US)    _wait_for_atomic((COND), (US), 1)
 133
 134 #define KHz(x) (1000 * (x))
 135 #define MHz(x) KHz(1000 * (x))
 136
 137 /*
 138  * Display related stuff
 139  */
 140
 141 /* store information about an Ixxx DVO */
 142 /* The i830->i865 use multiple DVOs with multiple i2cs */
 143 /* the i915, i945 have a single sDVO i2c bus - which is different */
 144 #define MAX_OUTPUTS 6
 145 /* maximum connectors per crtcs in the mode set */
 146
 147 /* Maximum cursor sizes */
 148 #define GEN2_CURSOR_WIDTH 64
 149 #define GEN2_CURSOR_HEIGHT 64
 150 #define MAX_CURSOR_WIDTH 256
 151 #define MAX_CURSOR_HEIGHT 256
 152
 153 #define INTEL_I2C_BUS_DVO 1
 154 #define INTEL_I2C_BUS_SDVO 2
 155
 156 /* these are outputs from the chip - integrated only
 157    external chips are via DVO or SDVO output */
 158 enum intel_output_type {
 159         INTEL_OUTPUT_UNUSED = 0,
 160         INTEL_OUTPUT_ANALOG = 1,
 161         INTEL_OUTPUT_DVO = 2,
 162         INTEL_OUTPUT_SDVO = 3,
 163         INTEL_OUTPUT_LVDS = 4,
 164         INTEL_OUTPUT_TVOUT = 5,
 165         INTEL_OUTPUT_HDMI = 6,
 166         INTEL_OUTPUT_DP = 7,
 167         INTEL_OUTPUT_EDP = 8,
 168         INTEL_OUTPUT_DSI = 9,
 169         INTEL_OUTPUT_UNKNOWN = 10,
 170         INTEL_OUTPUT_DP_MST = 11,
 171 };
 172
 173 #define INTEL_DVO_CHIP_NONE 0
 174 #define INTEL_DVO_CHIP_LVDS 1
 175 #define INTEL_DVO_CHIP_TMDS 2
 176 #define INTEL_DVO_CHIP_TVOUT 4
 177
 178 #define INTEL_DSI_VIDEO_MODE    0
 179 #define INTEL_DSI_COMMAND_MODE  1
 180
 181 struct intel_framebuffer {
 182         struct drm_framebuffer base;
 183         struct drm_i915_gem_object *obj;
 184         struct intel_rotation_info rot_info;
 185
 186         /* for each plane in the normal GTT view */
 187         struct {
 188                 unsigned int x, y;
 189         } normal[2];
 190         /* for each plane in the rotated GTT view */
 191         struct {
 192                 unsigned int x, y;
 193                 unsigned int pitch; /* pixels */
 194         } rotated[2];
 195 };
 196
 197 struct intel_fbdev {
 198         struct drm_fb_helper helper;
 199         struct intel_framebuffer *fb;
 200         struct i915_vma *vma;
 201         async_cookie_t cookie;
 202         int preferred_bpp;
 203 };
 204
 205 struct intel_encoder {
 206         struct drm_encoder base;
 207
 208         enum intel_output_type type;
 209         enum port port;
 210         unsigned int cloneable;
 211         void (*hot_plug)(struct intel_encoder *);
 212         bool (*compute_config)(struct intel_encoder *,
 213                                struct intel_crtc_state *,
 214                                struct drm_connector_state *);
 215         void (*pre_pll_enable)(struct intel_encoder *,
 216                                struct intel_crtc_state *,
 217                                struct drm_connector_state *);
 218         void (*pre_enable)(struct intel_encoder *,
 219                            struct intel_crtc_state *,
 220                            struct drm_connector_state *);
 221         void (*enable)(struct intel_encoder *,
 222                        struct intel_crtc_state *,
 223                        struct drm_connector_state *);
 224         void (*disable)(struct intel_encoder *,
 225                         struct intel_crtc_state *,
 226                         struct drm_connector_state *);
 227         void (*post_disable)(struct intel_encoder *,
 228                              struct intel_crtc_state *,
 229                              struct drm_connector_state *);
 230         void (*post_pll_disable)(struct intel_encoder *,
 231                                  struct intel_crtc_state *,
 232                                  struct drm_connector_state *);
 233         /* Read out the current hw state of this connector, returning true if
 234          * the encoder is active. If the encoder is enabled it also set the pipe
 235          * it is connected to in the pipe parameter. */
 236         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 237         /* Reconstructs the equivalent mode flags for the current hardware
 238          * state. This must be called _after_ display->get_pipe_config has
 239          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 240          * be set correctly before calling this function. */
 241         void (*get_config)(struct intel_encoder *,
 242                            struct intel_crtc_state *pipe_config);
 243         /*
 244          * Called during system suspend after all pending requests for the
 245          * encoder are flushed (for example for DP AUX transactions) and
 246          * device interrupts are disabled.
 247          */
 248         void (*suspend)(struct intel_encoder *);
 249         int crtc_mask;
 250         enum hpd_pin hpd_pin;
 251         /* for communication with audio component; protected by av_mutex */
 252         const struct drm_connector *audio_connector;
 253 };
 254
 255 struct intel_panel {
 256         struct drm_display_mode *fixed_mode;
 257         struct drm_display_mode *downclock_mode;
 258         int fitting_mode;
 259
 260         /* backlight */
 261         struct {
 262                 bool present;
 263                 u32 level;
 264                 u32 min;
 265                 u32 max;
 266                 bool enabled;
 267                 bool combination_mode;  /* gen 2/4 only */
 268                 bool active_low_pwm;
 269                 bool alternate_pwm_increment;   /* lpt+ */
 270
 271                 /* PWM chip */
 272                 bool util_pin_active_low;       /* bxt+ */
 273                 u8 controller;          /* bxt+ only */
 274                 struct pwm_device *pwm;
 275
 276                 struct backlight_device *device;
 277
 278                 /* Connector and platform specific backlight functions */
 279                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 280                 uint32_t (*get)(struct intel_connector *connector);
 281                 void (*set)(struct intel_connector *connector, uint32_t level);
 282                 void (*disable)(struct intel_connector *connector);
 283                 void (*enable)(struct intel_connector *connector);
 284                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 285                                       uint32_t hz);
 286                 void (*power)(struct intel_connector *, bool enable);
 287         } backlight;
 288 };
 289
 290 struct intel_connector {
 291         struct drm_connector base;
 292         /*
 293          * The fixed encoder this connector is connected to.
 294          */
 295         struct intel_encoder *encoder;
 296
 297         /* ACPI device id for ACPI and driver cooperation */
 298         u32 acpi_device_id;
 299
 300         /* Reads out the current hw, returning true if the connector is enabled
 301          * and active (i.e. dpms ON state). */
 302         bool (*get_hw_state)(struct intel_connector *);
 303
 304         /* Panel info for eDP and LVDS */
 305         struct intel_panel panel;
 306
 307         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 308         struct edid *edid;
 309         struct edid *detect_edid;
 310
 311         /* since POLL and HPD connectors may use the same HPD line keep the native
 312            state of connector->polled in case hotplug storm detection changes it */
 313         u8 polled;
 314
 315         void *port; /* store this opaque as its illegal to dereference it */
 316
 317         struct intel_dp *mst_port;
 318 };
 319
 320 struct dpll {
 321         /* given values */
 322         int n;
 323         int m1, m2;
 324         int p1, p2;
 325         /* derived values */
 326         int     dot;
 327         int     vco;
 328         int     m;
 329         int     p;
 330 };
 331
 332 struct intel_atomic_state {
 333         struct drm_atomic_state base;
 334
 335         unsigned int cdclk;
 336
 337         /*
 338          * Calculated device cdclk, can be different from cdclk
 339          * only when all crtc's are DPMS off.
 340          */
 341         unsigned int dev_cdclk;
 342
 343         bool dpll_set, modeset;
 344
 345         /*
 346          * Does this transaction change the pipes that are active?  This mask
 347          * tracks which CRTC's have changed their active state at the end of
 348          * the transaction (not counting the temporary disable during modesets).
 349          * This mask should only be non-zero when intel_state->modeset is true,
 350          * but the converse is not necessarily true; simply changing a mode may
 351          * not flip the final active status of any CRTC's
 352          */
 353         unsigned int active_pipe_changes;
 354
 355         unsigned int active_crtcs;
 356         unsigned int min_pixclk[I915_MAX_PIPES];
 357
 358         /* SKL/KBL Only */
 359         unsigned int cdclk_pll_vco;
 360
 361         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 362
 363         /*
 364          * Current watermarks can't be trusted during hardware readout, so
 365          * don't bother calculating intermediate watermarks.
 366          */
 367         bool skip_intermediate_wm;
 368
 369         /* Gen9+ only */
 370         struct skl_wm_values wm_results;
 371
 372         struct i915_sw_fence commit_ready;
 373 };
 374
 375 struct intel_plane_state {
 376         struct drm_plane_state base;
 377         struct drm_rect clip;
 378
 379         struct {
 380                 u32 offset;
 381                 int x, y;
 382         } main;
 383         struct {
 384                 u32 offset;
 385                 int x, y;
 386         } aux;
 387
 388         /*
 389          * scaler_id
 390          *    = -1 : not using a scaler
 391          *    >=  0 : using a scalers
 392          *
 393          * plane requiring a scaler:
 394          *   - During check_plane, its bit is set in
 395          *     crtc_state->scaler_state.scaler_users by calling helper function
 396          *     update_scaler_plane.
 397          *   - scaler_id indicates the scaler it got assigned.
 398          *
 399          * plane doesn't require a scaler:
 400          *   - this can happen when scaling is no more required or plane simply
 401          *     got disabled.
 402          *   - During check_plane, corresponding bit is reset in
 403          *     crtc_state->scaler_state.scaler_users by calling helper function
 404          *     update_scaler_plane.
 405          */
 406         int scaler_id;
 407
 408         struct drm_intel_sprite_colorkey ckey;
 409 };
 410
 411 struct intel_initial_plane_config {
 412         struct intel_framebuffer *fb;
 413         unsigned int tiling;
 414         int size;
 415         u32 base;
 416 };
 417
 418 #define SKL_MIN_SRC_W 8
 419 #define SKL_MAX_SRC_W 4096
 420 #define SKL_MIN_SRC_H 8
 421 #define SKL_MAX_SRC_H 4096
 422 #define SKL_MIN_DST_W 8
 423 #define SKL_MAX_DST_W 4096
 424 #define SKL_MIN_DST_H 8
 425 #define SKL_MAX_DST_H 4096
 426
 427 struct intel_scaler {
 428         int in_use;
 429         uint32_t mode;
 430 };
 431
 432 struct intel_crtc_scaler_state {
 433 #define SKL_NUM_SCALERS 2
 434         struct intel_scaler scalers[SKL_NUM_SCALERS];
 435
 436         /*
 437          * scaler_users: keeps track of users requesting scalers on this crtc.
 438          *
 439          *     If a bit is set, a user is using a scaler.
 440          *     Here user can be a plane or crtc as defined below:
 441          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 442          *       bit 31    - crtc
 443          *
 444          * Instead of creating a new index to cover planes and crtc, using
 445          * existing drm_plane_index for planes which is well less than 31
 446          * planes and bit 31 for crtc. This should be fine to cover all
 447          * our platforms.
 448          *
 449          * intel_atomic_setup_scalers will setup available scalers to users
 450          * requesting scalers. It will gracefully fail if request exceeds
 451          * avilability.
 452          */
 453 #define SKL_CRTC_INDEX 31
 454         unsigned scaler_users;
 455
 456         /* scaler used by crtc for panel fitting purpose */
 457         int scaler_id;
 458 };
 459
 460 /* drm_mode->private_flags */
 461 #define I915_MODE_FLAG_INHERITED 1
 462
 463 struct intel_pipe_wm {
 464         struct intel_wm_level wm[5];
 465         struct intel_wm_level raw_wm[5];
 466         uint32_t linetime;
 467         bool fbc_wm_enabled;
 468         bool pipe_enabled;
 469         bool sprites_enabled;
 470         bool sprites_scaled;
 471 };
 472
 473 struct skl_plane_wm {
 474         struct skl_wm_level wm[8];
 475         struct skl_wm_level trans_wm;
 476 };
 477
 478 struct skl_pipe_wm {
 479         struct skl_plane_wm planes[I915_MAX_PLANES];
 480         uint32_t linetime;
 481 };
 482
 483 struct intel_crtc_wm_state {
 484         union {
 485                 struct {
 486                         /*
 487                          * Intermediate watermarks; these can be
 488                          * programmed immediately since they satisfy
 489                          * both the current configuration we're
 490                          * switching away from and the new
 491                          * configuration we're switching to.
 492                          */
 493                         struct intel_pipe_wm intermediate;
 494
 495                         /*
 496                          * Optimal watermarks, programmed post-vblank
 497                          * when this state is committed.
 498                          */
 499                         struct intel_pipe_wm optimal;
 500                 } ilk;
 501
 502                 struct {
 503                         /* gen9+ only needs 1-step wm programming */
 504                         struct skl_pipe_wm optimal;
 505                         struct skl_ddb_entry ddb;
 506                 } skl;
 507         };
 508
 509         /*
 510          * Platforms with two-step watermark programming will need to
 511          * update watermark programming post-vblank to switch from the
 512          * safe intermediate watermarks to the optimal final
 513          * watermarks.
 514          */
 515         bool need_postvbl_update;
 516 };
 517
 518 struct intel_crtc_state {
 519         struct drm_crtc_state base;
 520
 521         /**
 522          * quirks - bitfield with hw state readout quirks
 523          *
 524          * For various reasons the hw state readout code might not be able to
 525          * completely faithfully read out the current state. These cases are
 526          * tracked with quirk flags so that fastboot and state checker can act
 527          * accordingly.
 528          */
 529 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 530         unsigned long quirks;
 531
 532         unsigned fb_bits; /* framebuffers to flip */
 533         bool update_pipe; /* can a fast modeset be performed? */
 534         bool disable_cxsr;
 535         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 536         bool fb_changed; /* fb on any of the planes is changed */
 537
 538         /* Pipe source size (ie. panel fitter input size)
 539          * All planes will be positioned inside this space,
 540          * and get clipped at the edges. */
 541         int pipe_src_w, pipe_src_h;
 542
 543         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 544          * between pch encoders and cpu encoders. */
 545         bool has_pch_encoder;
 546
 547         /* Are we sending infoframes on the attached port */
 548         bool has_infoframe;
 549
 550         /* CPU Transcoder for the pipe. Currently this can only differ from the
 551          * pipe on Haswell and later (where we have a special eDP transcoder)
 552          * and Broxton (where we have special DSI transcoders). */
 553         enum transcoder cpu_transcoder;
 554
 555         /*
 556          * Use reduced/limited/broadcast rbg range, compressing from the full
 557          * range fed into the crtcs.
 558          */
 559         bool limited_color_range;
 560
 561         /* Bitmask of encoder types (enum intel_output_type)
 562          * driven by the pipe.
 563          */
 564         unsigned int output_types;
 565
 566         /* Whether we should send NULL infoframes. Required for audio. */
 567         bool has_hdmi_sink;
 568
 569         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 570          * has_dp_encoder is set. */
 571         bool has_audio;
 572
 573         /*
 574          * Enable dithering, used when the selected pipe bpp doesn't match the
 575          * plane bpp.
 576          */
 577         bool dither;
 578
 579         /* Controls for the clock computation, to override various stages. */
 580         bool clock_set;
 581
 582         /* SDVO TV has a bunch of special case. To make multifunction encoders
 583          * work correctly, we need to track this at runtime.*/
 584         bool sdvo_tv_clock;
 585
 586         /*
 587          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 588          * required. This is set in the 2nd loop of calling encoder's
 589          * ->compute_config if the first pick doesn't work out.
 590          */
 591         bool bw_constrained;
 592
 593         /* Settings for the intel dpll used on pretty much everything but
 594          * haswell. */
 595         struct dpll dpll;
 596
 597         /* Selected dpll when shared or NULL. */
 598         struct intel_shared_dpll *shared_dpll;
 599
 600         /* Actual register state of the dpll, for shared dpll cross-checking. */
 601         struct intel_dpll_hw_state dpll_hw_state;
 602
 603         /* DSI PLL registers */
 604         struct {
 605                 u32 ctrl, div;
 606         } dsi_pll;
 607
 608         int pipe_bpp;
 609         struct intel_link_m_n dp_m_n;
 610
 611         /* m2_n2 for eDP downclock */
 612         struct intel_link_m_n dp_m2_n2;
 613         bool has_drrs;
 614
 615         /*
 616          * Frequence the dpll for the port should run at. Differs from the
 617          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 618          * already multiplied by pixel_multiplier.
 619          */
 620         int port_clock;
 621
 622         /* Used by SDVO (and if we ever fix it, HDMI). */
 623         unsigned pixel_multiplier;
 624
 625         uint8_t lane_count;
 626
 627         /*
 628          * Used by platforms having DP/HDMI PHY with programmable lane
 629          * latency optimization.
 630          */
 631         uint8_t lane_lat_optim_mask;
 632
 633         /* Panel fitter controls for gen2-gen4 + VLV */
 634         struct {
 635                 u32 control;
 636                 u32 pgm_ratios;
 637                 u32 lvds_border_bits;
 638         } gmch_pfit;
 639
 640         /* Panel fitter placement and size for Ironlake+ */
 641         struct {
 642                 u32 pos;
 643                 u32 size;
 644                 bool enabled;
 645                 bool force_thru;
 646         } pch_pfit;
 647
 648         /* FDI configuration, only valid if has_pch_encoder is set. */
 649         int fdi_lanes;
 650         struct intel_link_m_n fdi_m_n;
 651
 652         bool ips_enabled;
 653
 654         bool enable_fbc;
 655
 656         bool double_wide;
 657
 658         int pbn;
 659
 660         struct intel_crtc_scaler_state scaler_state;
 661
 662         /* w/a for waiting 2 vblanks during crtc enable */
 663         enum pipe hsw_workaround_pipe;
 664
 665         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 666         bool disable_lp_wm;
 667
 668         struct intel_crtc_wm_state wm;
 669
 670         /* Gamma mode programmed on the pipe */
 671         uint32_t gamma_mode;
 672 };
 673
 674 struct vlv_wm_state {
 675         struct vlv_pipe_wm wm[3];
 676         struct vlv_sr_wm sr[3];
 677         uint8_t num_active_planes;
 678         uint8_t num_levels;
 679         uint8_t level;
 680         bool cxsr;
 681 };
 682
 683 struct intel_crtc {
 684         struct drm_crtc base;
 685         enum pipe pipe;
 686         enum plane plane;
 687         u8 lut_r[256], lut_g[256], lut_b[256];
 688         /*
 689          * Whether the crtc and the connected output pipeline is active. Implies
 690          * that crtc->enabled is set, i.e. the current mode configuration has
 691          * some outputs connected to this crtc.
 692          */
 693         bool active;
 694         bool lowfreq_avail;
 695         u8 plane_ids_mask;
 696         unsigned long enabled_power_domains;
 697         struct intel_overlay *overlay;
 698         struct intel_flip_work *flip_work;
 699
 700         atomic_t unpin_work_count;
 701
 702         /* Display surface base address adjustement for pageflips. Note that on
 703          * gen4+ this only adjusts up to a tile, offsets within a tile are
 704          * handled in the hw itself (with the TILEOFF register). */
 705         u32 dspaddr_offset;
 706         int adjusted_x;
 707         int adjusted_y;
 708
 709         uint32_t cursor_addr;
 710         uint32_t cursor_cntl;
 711         uint32_t cursor_size;
 712         uint32_t cursor_base;
 713
 714         struct intel_crtc_state *config;
 715
 716         /* global reset count when the last flip was submitted */
 717         unsigned int reset_count;
 718
 719         /* Access to these should be protected by dev_priv->irq_lock. */
 720         bool cpu_fifo_underrun_disabled;
 721         bool pch_fifo_underrun_disabled;
 722
 723         /* per-pipe watermark state */
 724         struct {
 725                 /* watermarks currently being used  */
 726                 union {
 727                         struct intel_pipe_wm ilk;
 728                 } active;
 729
 730                 /* allow CxSR on this pipe */
 731                 bool cxsr_allowed;
 732         } wm;
 733
 734         int scanline_offset;
 735
 736         struct {
 737                 unsigned start_vbl_count;
 738                 ktime_t start_vbl_time;
 739                 int min_vbl, max_vbl;
 740                 int scanline_start;
 741         } debug;
 742
 743         /* scalers available on this crtc */
 744         int num_scalers;
 745
 746         struct vlv_wm_state wm_state;
 747 };
 748
 749 struct intel_plane_wm_parameters {
 750         uint32_t horiz_pixels;
 751         uint32_t vert_pixels;
 752         /*
 753          *   For packed pixel formats:
 754          *     bytes_per_pixel - holds bytes per pixel
 755          *   For planar pixel formats:
 756          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 757          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 758          */
 759         uint8_t bytes_per_pixel;
 760         uint8_t y_bytes_per_pixel;
 761         bool enabled;
 762         bool scaled;
 763         u64 tiling;
 764         unsigned int rotation;
 765         uint16_t fifo_size;
 766 };
 767
 768 struct intel_plane {
 769         struct drm_plane base;
 770         u8 plane;
 771         enum plane_id id;
 772         enum pipe pipe;
 773         bool can_scale;
 774         int max_downscale;
 775         uint32_t frontbuffer_bit;
 776
 777         /* Since we need to change the watermarks before/after
 778          * enabling/disabling the planes, we need to store the parameters here
 779          * as the other pieces of the struct may not reflect the values we want
 780          * for the watermark calculations. Currently only Haswell uses this.
 781          */
 782         struct intel_plane_wm_parameters wm;
 783
 784         /*
 785          * NOTE: Do not place new plane state fields here (e.g., when adding
 786          * new plane properties).  New runtime state should now be placed in
 787          * the intel_plane_state structure and accessed via plane_state.
 788          */
 789
 790         void (*update_plane)(struct drm_plane *plane,
 791                              const struct intel_crtc_state *crtc_state,
 792                              const struct intel_plane_state *plane_state);
 793         void (*disable_plane)(struct drm_plane *plane,
 794                               struct drm_crtc *crtc);
 795         int (*check_plane)(struct drm_plane *plane,
 796                            struct intel_crtc_state *crtc_state,
 797                            struct intel_plane_state *state);
 798 };
 799
 800 struct intel_watermark_params {
 801         u16 fifo_size;
 802         u16 max_wm;
 803         u8 default_wm;
 804         u8 guard_size;
 805         u8 cacheline_size;
 806 };
 807
 808 struct cxsr_latency {
 809         bool is_desktop : 1;
 810         bool is_ddr3 : 1;
 811         u16 fsb_freq;
 812         u16 mem_freq;
 813         u16 display_sr;
 814         u16 display_hpll_disable;
 815         u16 cursor_sr;
 816         u16 cursor_hpll_disable;
 817 };
 818
 819 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 820 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 821 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 822 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 823 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 824 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 825 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 826 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 827 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 828
 829 struct intel_hdmi {
 830         i915_reg_t hdmi_reg;
 831         int ddc_bus;
 832         struct {
 833                 enum drm_dp_dual_mode_type type;
 834                 int max_tmds_clock;
 835         } dp_dual_mode;
 836         bool limited_color_range;
 837         bool color_range_auto;
 838         bool has_hdmi_sink;
 839         bool has_audio;
 840         enum hdmi_force_audio force_audio;
 841         bool rgb_quant_range_selectable;
 842         enum hdmi_picture_aspect aspect_ratio;
 843         struct intel_connector *attached_connector;
 844         void (*write_infoframe)(struct drm_encoder *encoder,
 845                                 enum hdmi_infoframe_type type,
 846                                 const void *frame, ssize_t len);
 847         void (*set_infoframes)(struct drm_encoder *encoder,
 848                                bool enable,
 849                                const struct drm_display_mode *adjusted_mode);
 850         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 851                                   const struct intel_crtc_state *pipe_config);
 852 };
 853
 854 struct intel_dp_mst_encoder;
 855 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 856
 857 /*
 858  * enum link_m_n_set:
 859  *      When platform provides two set of M_N registers for dp, we can
 860  *      program them and switch between them incase of DRRS.
 861  *      But When only one such register is provided, we have to program the
 862  *      required divider value on that registers itself based on the DRRS state.
 863  *
 864  * M1_N1        : Program dp_m_n on M1_N1 registers
 865  *                        dp_m2_n2 on M2_N2 registers (If supported)
 866  *
 867  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 868  *                        M2_N2 registers are not supported
 869  */
 870
 871 enum link_m_n_set {
 872         /* Sets the m1_n1 and m2_n2 */
 873         M1_N1 = 0,
 874         M2_N2
 875 };
 876
 877 struct intel_dp_desc {
 878         u8 oui[3];
 879         u8 device_id[6];
 880         u8 hw_rev;
 881         u8 sw_major_rev;
 882         u8 sw_minor_rev;
 883 } __packed;
 884
 885 struct intel_dp {
 886         i915_reg_t output_reg;
 887         i915_reg_t aux_ch_ctl_reg;
 888         i915_reg_t aux_ch_data_reg[5];
 889         uint32_t DP;
 890         int link_rate;
 891         uint8_t lane_count;
 892         uint8_t sink_count;
 893         bool link_mst;
 894         bool has_audio;
 895         bool detect_done;
 896         bool channel_eq_status;
 897         enum hdmi_force_audio force_audio;
 898         bool limited_color_range;
 899         bool color_range_auto;
 900         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 901         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 902         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 903         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 904         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 905         uint8_t num_sink_rates;
 906         int sink_rates[DP_MAX_SUPPORTED_RATES];
 907         /* sink or branch descriptor */
 908         struct intel_dp_desc desc;
 909         struct drm_dp_aux aux;
 910         uint8_t train_set[4];
 911         int panel_power_up_delay;
 912         int panel_power_down_delay;
 913         int panel_power_cycle_delay;
 914         int backlight_on_delay;
 915         int backlight_off_delay;
 916         struct delayed_work panel_vdd_work;
 917         bool want_panel_vdd;
 918         unsigned long last_power_on;
 919         unsigned long last_backlight_off;
 920         ktime_t panel_power_off_time;
 921
 922         struct notifier_block edp_notifier;
 923
 924         /*
 925          * Pipe whose power sequencer is currently locked into
 926          * this port. Only relevant on VLV/CHV.
 927          */
 928         enum pipe pps_pipe;
 929         /*
 930          * Set if the sequencer may be reset due to a power transition,
 931          * requiring a reinitialization. Only relevant on BXT.
 932          */
 933         bool pps_reset;
 934         struct edp_power_seq pps_delays;
 935
 936         bool can_mst; /* this port supports mst */
 937         bool is_mst;
 938         int active_mst_links;
 939         /* connector directly attached - won't be use for modeset in mst world */
 940         struct intel_connector *attached_connector;
 941
 942         /* mst connector list */
 943         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 944         struct drm_dp_mst_topology_mgr mst_mgr;
 945
 946         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 947         /*
 948          * This function returns the value we have to program the AUX_CTL
 949          * register with to kick off an AUX transaction.
 950          */
 951         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 952                                      bool has_aux_irq,
 953                                      int send_bytes,
 954                                      uint32_t aux_clock_divider);
 955
 956         /* This is called before a link training is starterd */
 957         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 958
 959         /* Displayport compliance testing */
 960         unsigned long compliance_test_type;
 961         unsigned long compliance_test_data;
 962         bool compliance_test_active;
 963 };
 964
 965 struct intel_lspcon {
 966         bool active;
 967         enum drm_lspcon_mode mode;
 968         bool desc_valid;
 969 };
 970
 971 struct intel_digital_port {
 972         struct intel_encoder base;
 973         enum port port;
 974         u32 saved_port_bits;
 975         struct intel_dp dp;
 976         struct intel_hdmi hdmi;
 977         struct intel_lspcon lspcon;
 978         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 979         bool release_cl2_override;
 980         uint8_t max_lanes;
 981 };
 982
 983 struct intel_dp_mst_encoder {
 984         struct intel_encoder base;
 985         enum pipe pipe;
 986         struct intel_digital_port *primary;
 987         struct intel_connector *connector;
 988 };
 989
 990 static inline enum dpio_channel
 991 vlv_dport_to_channel(struct intel_digital_port *dport)
 992 {
 993         switch (dport->port) {
 994         case PORT_B:
 995         case PORT_D:
 996                 return DPIO_CH0;
 997         case PORT_C:
 998                 return DPIO_CH1;
 999         default:
1000                 BUG();
1001         }
1002 }
1003
1004 static inline enum dpio_phy
1005 vlv_dport_to_phy(struct intel_digital_port *dport)
1006 {
1007         switch (dport->port) {
1008         case PORT_B:
1009         case PORT_C:
1010                 return DPIO_PHY0;
1011         case PORT_D:
1012                 return DPIO_PHY1;
1013         default:
1014                 BUG();
1015         }
1016 }
1017
1018 static inline enum dpio_channel
1019 vlv_pipe_to_channel(enum pipe pipe)
1020 {
1021         switch (pipe) {
1022         case PIPE_A:
1023         case PIPE_C:
1024                 return DPIO_CH0;
1025         case PIPE_B:
1026                 return DPIO_CH1;
1027         default:
1028                 BUG();
1029         }
1030 }
1031
1032 static inline struct intel_crtc *
1033 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1034 {
1035         return dev_priv->pipe_to_crtc_mapping[pipe];
1036 }
1037
1038 static inline struct intel_crtc *
1039 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1040 {
1041         return dev_priv->plane_to_crtc_mapping[plane];
1042 }
1043
1044 struct intel_flip_work {
1045         struct work_struct unpin_work;
1046         struct work_struct mmio_work;
1047
1048         struct drm_crtc *crtc;
1049         struct drm_framebuffer *old_fb;
1050         struct drm_i915_gem_object *pending_flip_obj;
1051         struct drm_pending_vblank_event *event;
1052         atomic_t pending;
1053         u32 flip_count;
1054         u32 gtt_offset;
1055         struct drm_i915_gem_request *flip_queued_req;
1056         u32 flip_queued_vblank;
1057         u32 flip_ready_vblank;
1058         unsigned int rotation;
1059 };
1060
1061 struct intel_load_detect_pipe {
1062         struct drm_atomic_state *restore_state;
1063 };
1064
1065 static inline struct intel_encoder *
1066 intel_attached_encoder(struct drm_connector *connector)
1067 {
1068         return to_intel_connector(connector)->encoder;
1069 }
1070
1071 static inline struct intel_digital_port *
1072 enc_to_dig_port(struct drm_encoder *encoder)
1073 {
1074         return container_of(encoder, struct intel_digital_port, base.base);
1075 }
1076
1077 static inline struct intel_dp_mst_encoder *
1078 enc_to_mst(struct drm_encoder *encoder)
1079 {
1080         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1081 }
1082
1083 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1084 {
1085         return &enc_to_dig_port(encoder)->dp;
1086 }
1087
1088 static inline struct intel_digital_port *
1089 dp_to_dig_port(struct intel_dp *intel_dp)
1090 {
1091         return container_of(intel_dp, struct intel_digital_port, dp);
1092 }
1093
1094 static inline struct intel_lspcon *
1095 dp_to_lspcon(struct intel_dp *intel_dp)
1096 {
1097         return &dp_to_dig_port(intel_dp)->lspcon;
1098 }
1099
1100 static inline struct intel_digital_port *
1101 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1102 {
1103         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1104 }
1105
1106 /* intel_fifo_underrun.c */
1107 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1108                                            enum pipe pipe, bool enable);
1109 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1110                                            enum transcoder pch_transcoder,
1111                                            bool enable);
1112 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1113                                          enum pipe pipe);
1114 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1115                                          enum transcoder pch_transcoder);
1116 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1117 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1118
1119 /* i915_irq.c */
1120 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1121 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1122 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
1123 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1124 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1125 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1126 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1127 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1128 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1129 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1130 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1131 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1132 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1133 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1134 {
1135         /*
1136          * We only use drm_irq_uninstall() at unload and VT switch, so
1137          * this is the only thing we need to check.
1138          */
1139         return dev_priv->pm.irqs_enabled;
1140 }
1141
1142 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1143 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1144                                      unsigned int pipe_mask);
1145 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1146                                      unsigned int pipe_mask);
1147 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1148 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1149 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1150
1151 /* intel_crt.c */
1152 void intel_crt_init(struct drm_device *dev);
1153 void intel_crt_reset(struct drm_encoder *encoder);
1154
1155 /* intel_ddi.c */
1156 void intel_ddi_clk_select(struct intel_encoder *encoder,
1157                           struct intel_shared_dpll *pll);
1158 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1159                                 struct intel_crtc_state *old_crtc_state,
1160                                 struct drm_connector_state *old_conn_state);
1161 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder);
1162 void hsw_fdi_link_train(struct drm_crtc *crtc);
1163 void intel_ddi_init(struct drm_device *dev, enum port port);
1164 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1165 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1166 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1167 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1168                                        enum transcoder cpu_transcoder);
1169 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1170 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1171 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1172                           struct intel_crtc_state *crtc_state);
1173 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1174 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1175 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1176 void intel_ddi_get_config(struct intel_encoder *encoder,
1177                           struct intel_crtc_state *pipe_config);
1178 struct intel_encoder *
1179 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1180
1181 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1182 void intel_ddi_clock_get(struct intel_encoder *encoder,
1183                          struct intel_crtc_state *pipe_config);
1184 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1185 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1186 struct intel_shared_dpll *intel_ddi_get_link_dpll(struct intel_dp *intel_dp,
1187                                                   int clock);
1188 unsigned int intel_fb_align_height(struct drm_device *dev,
1189                                    unsigned int height,
1190                                    uint32_t pixel_format,
1191                                    uint64_t fb_format_modifier);
1192 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1193                               uint64_t fb_modifier, uint32_t pixel_format);
1194
1195 /* intel_audio.c */
1196 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1197 void intel_audio_codec_enable(struct intel_encoder *encoder,
1198                               const struct intel_crtc_state *crtc_state,
1199                               const struct drm_connector_state *conn_state);
1200 void intel_audio_codec_disable(struct intel_encoder *encoder);
1201 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1202 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1203
1204 /* intel_display.c */
1205 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1206 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1207 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1208 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1209                       const char *name, u32 reg, int ref_freq);
1210 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1211 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1212 extern const struct drm_plane_funcs intel_plane_funcs;
1213 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1214 unsigned int intel_fb_xy_to_linear(int x, int y,
1215                                    const struct intel_plane_state *state,
1216                                    int plane);
1217 void intel_add_fb_offsets(int *x, int *y,
1218                           const struct intel_plane_state *state, int plane);
1219 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1220 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1221 void intel_mark_busy(struct drm_i915_private *dev_priv);
1222 void intel_mark_idle(struct drm_i915_private *dev_priv);
1223 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1224 int intel_display_suspend(struct drm_device *dev);
1225 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1226 void intel_encoder_destroy(struct drm_encoder *encoder);
1227 int intel_connector_init(struct intel_connector *);
1228 struct intel_connector *intel_connector_alloc(void);
1229 bool intel_connector_get_hw_state(struct intel_connector *connector);
1230 void intel_connector_attach_encoder(struct intel_connector *connector,
1231                                     struct intel_encoder *encoder);
1232 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1233                                              struct drm_crtc *crtc);
1234 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1235 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1236                                 struct drm_file *file_priv);
1237 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1238                                              enum pipe pipe);
1239 static inline bool
1240 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1241                     enum intel_output_type type)
1242 {
1243         return crtc_state->output_types & (1 << type);
1244 }
1245 static inline bool
1246 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1247 {
1248         return crtc_state->output_types &
1249                 ((1 << INTEL_OUTPUT_DP) |
1250                  (1 << INTEL_OUTPUT_DP_MST) |
1251                  (1 << INTEL_OUTPUT_EDP));
1252 }
1253 static inline void
1254 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1255 {
1256         drm_wait_one_vblank(&dev_priv->drm, pipe);
1257 }
1258 static inline void
1259 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1260 {
1261         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1262
1263         if (crtc->active)
1264                 intel_wait_for_vblank(dev_priv, pipe);
1265 }
1266
1267 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1268
1269 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1270 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1271                          struct intel_digital_port *dport,
1272                          unsigned int expected_mask);
1273 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1274                                 struct drm_display_mode *mode,
1275                                 struct intel_load_detect_pipe *old,
1276                                 struct drm_modeset_acquire_ctx *ctx);
1277 void intel_release_load_detect_pipe(struct drm_connector *connector,
1278                                     struct intel_load_detect_pipe *old,
1279                                     struct drm_modeset_acquire_ctx *ctx);
1280 struct i915_vma *
1281 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1282 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1283 struct drm_framebuffer *
1284 __intel_framebuffer_create(struct drm_device *dev,
1285                            struct drm_mode_fb_cmd2 *mode_cmd,
1286                            struct drm_i915_gem_object *obj);
1287 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1288 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1289 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1290 int intel_prepare_plane_fb(struct drm_plane *plane,
1291                            struct drm_plane_state *new_state);
1292 void intel_cleanup_plane_fb(struct drm_plane *plane,
1293                             struct drm_plane_state *old_state);
1294 int intel_plane_atomic_get_property(struct drm_plane *plane,
1295                                     const struct drm_plane_state *state,
1296                                     struct drm_property *property,
1297                                     uint64_t *val);
1298 int intel_plane_atomic_set_property(struct drm_plane *plane,
1299                                     struct drm_plane_state *state,
1300                                     struct drm_property *property,
1301                                     uint64_t val);
1302 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1303                                     struct drm_plane_state *plane_state);
1304
1305 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1306                                uint64_t fb_modifier, unsigned int cpp);
1307
1308 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1309                                     enum pipe pipe);
1310
1311 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1312                      const struct dpll *dpll);
1313 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1314 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1315
1316 /* modesetting asserts */
1317 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1318                            enum pipe pipe);
1319 void assert_pll(struct drm_i915_private *dev_priv,
1320                 enum pipe pipe, bool state);
1321 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1322 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1323 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1324 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1325 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1326 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1327                        enum pipe pipe, bool state);
1328 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1329 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1330 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1331 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1332 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1333 u32 intel_compute_tile_offset(int *x, int *y,
1334                               const struct intel_plane_state *state, int plane);
1335 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1336 void intel_finish_reset(struct drm_i915_private *dev_priv);
1337 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1338 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1339 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1340 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1341 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1342 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1343 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1344 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1345 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1346 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1347 unsigned int skl_cdclk_get_vco(unsigned int freq);
1348 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1349 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1350 void intel_dp_get_m_n(struct intel_crtc *crtc,
1351                       struct intel_crtc_state *pipe_config);
1352 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1353 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1354 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1355                         struct dpll *best_clock);
1356 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1357
1358 bool intel_crtc_active(struct intel_crtc *crtc);
1359 void hsw_enable_ips(struct intel_crtc *crtc);
1360 void hsw_disable_ips(struct intel_crtc *crtc);
1361 enum intel_display_power_domain
1362 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1363 enum intel_display_power_domain
1364 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1365 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1366                                  struct intel_crtc_state *pipe_config);
1367
1368 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1369 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1370
1371 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, unsigned int rotation);
1372
1373 u32 skl_plane_ctl_format(uint32_t pixel_format);
1374 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1375 u32 skl_plane_ctl_rotation(unsigned int rotation);
1376 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1377                      unsigned int rotation);
1378 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1379
1380 /* intel_csr.c */
1381 void intel_csr_ucode_init(struct drm_i915_private *);
1382 void intel_csr_load_program(struct drm_i915_private *);
1383 void intel_csr_ucode_fini(struct drm_i915_private *);
1384 void intel_csr_ucode_suspend(struct drm_i915_private *);
1385 void intel_csr_ucode_resume(struct drm_i915_private *);
1386
1387 /* intel_dp.c */
1388 bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1389 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1390                              struct intel_connector *intel_connector);
1391 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1392                               int link_rate, uint8_t lane_count,
1393                               bool link_mst);
1394 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1395 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1396 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1397 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1398 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1399 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1400 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1401 bool intel_dp_compute_config(struct intel_encoder *encoder,
1402                              struct intel_crtc_state *pipe_config,
1403                              struct drm_connector_state *conn_state);
1404 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
1405 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1406                                   bool long_hpd);
1407 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1408 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1409 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1410 void intel_edp_panel_on(struct intel_dp *intel_dp);
1411 void intel_edp_panel_off(struct intel_dp *intel_dp);
1412 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1413 void intel_dp_mst_suspend(struct drm_device *dev);
1414 void intel_dp_mst_resume(struct drm_device *dev);
1415 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1416 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1417 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1418 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1419 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1420 void intel_plane_destroy(struct drm_plane *plane);
1421 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1422                            struct intel_crtc_state *crtc_state);
1423 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1424                            struct intel_crtc_state *crtc_state);
1425 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1426                                unsigned int frontbuffer_bits);
1427 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1428                           unsigned int frontbuffer_bits);
1429
1430 void
1431 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1432                                        uint8_t dp_train_pat);
1433 void
1434 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1435 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1436 uint8_t
1437 intel_dp_voltage_max(struct intel_dp *intel_dp);
1438 uint8_t
1439 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1440 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1441                            uint8_t *link_bw, uint8_t *rate_select);
1442 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1443 bool
1444 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1445
1446 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1447 {
1448         return ~((1 << lane_count) - 1) & 0xf;
1449 }
1450
1451 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1452 bool __intel_dp_read_desc(struct intel_dp *intel_dp,
1453                           struct intel_dp_desc *desc);
1454 bool intel_dp_read_desc(struct intel_dp *intel_dp);
1455
1456 /* intel_dp_aux_backlight.c */
1457 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1458
1459 /* intel_dp_mst.c */
1460 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1461 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1462 /* intel_dsi.c */
1463 void intel_dsi_init(struct drm_device *dev);
1464
1465 /* intel_dsi_dcs_backlight.c */
1466 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1467
1468 /* intel_dvo.c */
1469 void intel_dvo_init(struct drm_device *dev);
1470 /* intel_hotplug.c */
1471 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1472
1473
1474 /* legacy fbdev emulation in intel_fbdev.c */
1475 #ifdef CONFIG_DRM_FBDEV_EMULATION
1476 extern int intel_fbdev_init(struct drm_device *dev);
1477 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1478 extern void intel_fbdev_fini(struct drm_device *dev);
1479 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1480 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1481 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1482 #else
1483 static inline int intel_fbdev_init(struct drm_device *dev)
1484 {
1485         return 0;
1486 }
1487
1488 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1489 {
1490 }
1491
1492 static inline void intel_fbdev_fini(struct drm_device *dev)
1493 {
1494 }
1495
1496 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1497 {
1498 }
1499
1500 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1501 {
1502 }
1503
1504 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1505 {
1506 }
1507 #endif
1508
1509 /* intel_fbc.c */
1510 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1511                            struct drm_atomic_state *state);
1512 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1513 void intel_fbc_pre_update(struct intel_crtc *crtc,
1514                           struct intel_crtc_state *crtc_state,
1515                           struct intel_plane_state *plane_state);
1516 void intel_fbc_post_update(struct intel_crtc *crtc);
1517 void intel_fbc_init(struct drm_i915_private *dev_priv);
1518 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1519 void intel_fbc_enable(struct intel_crtc *crtc,
1520                       struct intel_crtc_state *crtc_state,
1521                       struct intel_plane_state *plane_state);
1522 void intel_fbc_disable(struct intel_crtc *crtc);
1523 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1524 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1525                           unsigned int frontbuffer_bits,
1526                           enum fb_op_origin origin);
1527 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1528                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1529 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1530 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1531
1532 /* intel_hdmi.c */
1533 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1534 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1535                                struct intel_connector *intel_connector);
1536 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1537 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1538                                struct intel_crtc_state *pipe_config,
1539                                struct drm_connector_state *conn_state);
1540 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1541
1542
1543 /* intel_lvds.c */
1544 void intel_lvds_init(struct drm_device *dev);
1545 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1546 bool intel_is_dual_link_lvds(struct drm_device *dev);
1547
1548
1549 /* intel_modes.c */
1550 int intel_connector_update_modes(struct drm_connector *connector,
1551                                  struct edid *edid);
1552 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1553 void intel_attach_force_audio_property(struct drm_connector *connector);
1554 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1555 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1556
1557
1558 /* intel_overlay.c */
1559 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1560 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1561 int intel_overlay_switch_off(struct intel_overlay *overlay);
1562 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1563                                   struct drm_file *file_priv);
1564 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1565                               struct drm_file *file_priv);
1566 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1567
1568
1569 /* intel_panel.c */
1570 int intel_panel_init(struct intel_panel *panel,
1571                      struct drm_display_mode *fixed_mode,
1572                      struct drm_display_mode *downclock_mode);
1573 void intel_panel_fini(struct intel_panel *panel);
1574 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1575                             struct drm_display_mode *adjusted_mode);
1576 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1577                              struct intel_crtc_state *pipe_config,
1578                              int fitting_mode);
1579 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1580                               struct intel_crtc_state *pipe_config,
1581                               int fitting_mode);
1582 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1583                                     u32 level, u32 max);
1584 int intel_panel_setup_backlight(struct drm_connector *connector,
1585                                 enum pipe pipe);
1586 void intel_panel_enable_backlight(struct intel_connector *connector);
1587 void intel_panel_disable_backlight(struct intel_connector *connector);
1588 void intel_panel_destroy_backlight(struct drm_connector *connector);
1589 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1590 extern struct drm_display_mode *intel_find_panel_downclock(
1591                                 struct drm_device *dev,
1592                                 struct drm_display_mode *fixed_mode,
1593                                 struct drm_connector *connector);
1594
1595 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1596 int intel_backlight_device_register(struct intel_connector *connector);
1597 void intel_backlight_device_unregister(struct intel_connector *connector);
1598 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1599 static int intel_backlight_device_register(struct intel_connector *connector)
1600 {
1601         return 0;
1602 }
1603 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1604 {
1605 }
1606 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1607
1608
1609 /* intel_psr.c */
1610 void intel_psr_enable(struct intel_dp *intel_dp);
1611 void intel_psr_disable(struct intel_dp *intel_dp);
1612 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1613                           unsigned frontbuffer_bits);
1614 void intel_psr_flush(struct drm_i915_private *dev_priv,
1615                      unsigned frontbuffer_bits,
1616                      enum fb_op_origin origin);
1617 void intel_psr_init(struct drm_device *dev);
1618 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1619                                    unsigned frontbuffer_bits);
1620
1621 /* intel_runtime_pm.c */
1622 int intel_power_domains_init(struct drm_i915_private *);
1623 void intel_power_domains_fini(struct drm_i915_private *);
1624 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1625 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1626 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1627 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1628 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1629 const char *
1630 intel_display_power_domain_str(enum intel_display_power_domain domain);
1631
1632 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1633                                     enum intel_display_power_domain domain);
1634 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1635                                       enum intel_display_power_domain domain);
1636 void intel_display_power_get(struct drm_i915_private *dev_priv,
1637                              enum intel_display_power_domain domain);
1638 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1639                                         enum intel_display_power_domain domain);
1640 void intel_display_power_put(struct drm_i915_private *dev_priv,
1641                              enum intel_display_power_domain domain);
1642
1643 static inline void
1644 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1645 {
1646         WARN_ONCE(dev_priv->pm.suspended,
1647                   "Device suspended during HW access\n");
1648 }
1649
1650 static inline void
1651 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1652 {
1653         assert_rpm_device_not_suspended(dev_priv);
1654         /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1655          * too much noise. */
1656         if (!atomic_read(&dev_priv->pm.wakeref_count))
1657                 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1658 }
1659
1660 /**
1661  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1662  * @dev_priv: i915 device instance
1663  *
1664  * This function disable asserts that check if we hold an RPM wakelock
1665  * reference, while keeping the device-not-suspended checks still enabled.
1666  * It's meant to be used only in special circumstances where our rule about
1667  * the wakelock refcount wrt. the device power state doesn't hold. According
1668  * to this rule at any point where we access the HW or want to keep the HW in
1669  * an active state we must hold an RPM wakelock reference acquired via one of
1670  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1671  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1672  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1673  * users should avoid using this function.
1674  *
1675  * Any calls to this function must have a symmetric call to
1676  * enable_rpm_wakeref_asserts().
1677  */
1678 static inline void
1679 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1680 {
1681         atomic_inc(&dev_priv->pm.wakeref_count);
1682 }
1683
1684 /**
1685  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1686  * @dev_priv: i915 device instance
1687  *
1688  * This function re-enables the RPM assert checks after disabling them with
1689  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1690  * circumstances otherwise its use should be avoided.
1691  *
1692  * Any calls to this function must have a symmetric call to
1693  * disable_rpm_wakeref_asserts().
1694  */
1695 static inline void
1696 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1697 {
1698         atomic_dec(&dev_priv->pm.wakeref_count);
1699 }
1700
1701 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1702 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1703 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1704 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1705
1706 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1707
1708 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1709                              bool override, unsigned int mask);
1710 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1711                           enum dpio_channel ch, bool override);
1712
1713
1714 /* intel_pm.c */
1715 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1716 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1717 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1718 void intel_update_watermarks(struct intel_crtc *crtc);
1719 void intel_init_pm(struct drm_i915_private *dev_priv);
1720 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1721 void intel_pm_setup(struct drm_device *dev);
1722 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1723 void intel_gpu_ips_teardown(void);
1724 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1725 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1726 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1727 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1728 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1729 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1730 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1731 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1732 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1733 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1734 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1735                     struct intel_rps_client *rps,
1736                     unsigned long submitted);
1737 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1738 void vlv_wm_get_hw_state(struct drm_device *dev);
1739 void ilk_wm_get_hw_state(struct drm_device *dev);
1740 void skl_wm_get_hw_state(struct drm_device *dev);
1741 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1742                           struct skl_ddb_allocation *ddb /* out */);
1743 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1744                               struct skl_pipe_wm *out);
1745 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1746 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1747 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1748 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1749                          const struct skl_wm_level *l2);
1750 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
1751                                  const struct skl_ddb_entry *ddb,
1752                                  int ignore);
1753 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1754 bool ilk_disable_lp_wm(struct drm_device *dev);
1755 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1756 static inline int intel_enable_rc6(void)
1757 {
1758         return i915.enable_rc6;
1759 }
1760
1761 /* intel_sdvo.c */
1762 bool intel_sdvo_init(struct drm_device *dev,
1763                      i915_reg_t reg, enum port port);
1764
1765
1766 /* intel_sprite.c */
1767 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1768                              int usecs);
1769 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1770                                               enum pipe pipe, int plane);
1771 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1772                               struct drm_file *file_priv);
1773 void intel_pipe_update_start(struct intel_crtc *crtc);
1774 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1775
1776 /* intel_tv.c */
1777 void intel_tv_init(struct drm_device *dev);
1778
1779 /* intel_atomic.c */
1780 int intel_connector_atomic_get_property(struct drm_connector *connector,
1781                                         const struct drm_connector_state *state,
1782                                         struct drm_property *property,
1783                                         uint64_t *val);
1784 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1785 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1786                                struct drm_crtc_state *state);
1787 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1788 void intel_atomic_state_clear(struct drm_atomic_state *);
1789 struct intel_shared_dpll_config *
1790 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1791
1792 static inline struct intel_crtc_state *
1793 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1794                             struct intel_crtc *crtc)
1795 {
1796         struct drm_crtc_state *crtc_state;
1797         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1798         if (IS_ERR(crtc_state))
1799                 return ERR_CAST(crtc_state);
1800
1801         return to_intel_crtc_state(crtc_state);
1802 }
1803
1804 static inline struct intel_plane_state *
1805 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1806                                       struct intel_plane *plane)
1807 {
1808         struct drm_plane_state *plane_state;
1809
1810         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1811
1812         return to_intel_plane_state(plane_state);
1813 }
1814
1815 int intel_atomic_setup_scalers(struct drm_device *dev,
1816         struct intel_crtc *intel_crtc,
1817         struct intel_crtc_state *crtc_state);
1818
1819 /* intel_atomic_plane.c */
1820 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1821 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1822 void intel_plane_destroy_state(struct drm_plane *plane,
1823                                struct drm_plane_state *state);
1824 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1825
1826 /* intel_color.c */
1827 void intel_color_init(struct drm_crtc *crtc);
1828 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1829 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1830 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1831
1832 /* intel_lspcon.c */
1833 bool lspcon_init(struct intel_digital_port *intel_dig_port);
1834 void lspcon_resume(struct intel_lspcon *lspcon);
1835 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
1836 #endif /* __INTEL_DRV_H__ */