drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_mst_helper.h>
  37 #include <drm/drm_rect.h>
  38
  39 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
  40 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  41
  42 /**
  43  * _wait_for - magic (register) wait macro
  44  *
  45  * Does the right thing for modeset paths when run under kdgb or similar atomic
  46  * contexts. Note that it's important that we check the condition again after
  47  * having timed out, since the timeout could be due to preemption or similar and
  48  * we've never had a chance to check the condition before the timeout.
  49  */
  50 #define _wait_for(COND, MS, W) ({ \
  51         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  52         int ret__ = 0;                                                  \
  53         while (!(COND)) {                                               \
  54                 if (time_after(jiffies, timeout__)) {                   \
  55                         if (!(COND))                                    \
  56                                 ret__ = -ETIMEDOUT;                     \
  57                         break;                                          \
  58                 }                                                       \
  59                 if (W && drm_can_sleep())  {                            \
  60                         msleep(W);                                      \
  61                 } else {                                                \
  62                         cpu_relax();                                    \
  63                 }                                                       \
  64         }                                                               \
  65         ret__;                                                          \
  66 })
  67
  68 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  69 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  70 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  71                                                DIV_ROUND_UP((US), 1000), 0)
  72
  73 #define KHz(x) (1000 * (x))
  74 #define MHz(x) KHz(1000 * (x))
  75
  76 /*
  77  * Display related stuff
  78  */
  79
  80 /* store information about an Ixxx DVO */
  81 /* The i830->i865 use multiple DVOs with multiple i2cs */
  82 /* the i915, i945 have a single sDVO i2c bus - which is different */
  83 #define MAX_OUTPUTS 6
  84 /* maximum connectors per crtcs in the mode set */
  85
  86 /* Maximum cursor sizes */
  87 #define GEN2_CURSOR_WIDTH 64
  88 #define GEN2_CURSOR_HEIGHT 64
  89 #define MAX_CURSOR_WIDTH 256
  90 #define MAX_CURSOR_HEIGHT 256
  91
  92 #define INTEL_I2C_BUS_DVO 1
  93 #define INTEL_I2C_BUS_SDVO 2
  94
  95 /* these are outputs from the chip - integrated only
  96    external chips are via DVO or SDVO output */
  97 #define INTEL_OUTPUT_UNUSED 0
  98 #define INTEL_OUTPUT_ANALOG 1
  99 #define INTEL_OUTPUT_DVO 2
 100 #define INTEL_OUTPUT_SDVO 3
 101 #define INTEL_OUTPUT_LVDS 4
 102 #define INTEL_OUTPUT_TVOUT 5
 103 #define INTEL_OUTPUT_HDMI 6
 104 #define INTEL_OUTPUT_DISPLAYPORT 7
 105 #define INTEL_OUTPUT_EDP 8
 106 #define INTEL_OUTPUT_DSI 9
 107 #define INTEL_OUTPUT_UNKNOWN 10
 108 #define INTEL_OUTPUT_DP_MST 11
 109
 110 #define INTEL_DVO_CHIP_NONE 0
 111 #define INTEL_DVO_CHIP_LVDS 1
 112 #define INTEL_DVO_CHIP_TMDS 2
 113 #define INTEL_DVO_CHIP_TVOUT 4
 114
 115 #define INTEL_DSI_VIDEO_MODE    0
 116 #define INTEL_DSI_COMMAND_MODE  1
 117
 118 struct intel_framebuffer {
 119         struct drm_framebuffer base;
 120         struct drm_i915_gem_object *obj;
 121 };
 122
 123 struct intel_fbdev {
 124         struct drm_fb_helper helper;
 125         struct intel_framebuffer *fb;
 126         struct list_head fbdev_list;
 127         struct drm_display_mode *our_mode;
 128         int preferred_bpp;
 129 };
 130
 131 struct intel_encoder {
 132         struct drm_encoder base;
 133         /*
 134          * The new crtc this encoder will be driven from. Only differs from
 135          * base->crtc while a modeset is in progress.
 136          */
 137         struct intel_crtc *new_crtc;
 138
 139         int type;
 140         unsigned int cloneable;
 141         bool connectors_active;
 142         void (*hot_plug)(struct intel_encoder *);
 143         bool (*compute_config)(struct intel_encoder *,
 144                                struct intel_crtc_config *);
 145         void (*pre_pll_enable)(struct intel_encoder *);
 146         void (*pre_enable)(struct intel_encoder *);
 147         void (*enable)(struct intel_encoder *);
 148         void (*mode_set)(struct intel_encoder *intel_encoder);
 149         void (*disable)(struct intel_encoder *);
 150         void (*post_disable)(struct intel_encoder *);
 151         /* Read out the current hw state of this connector, returning true if
 152          * the encoder is active. If the encoder is enabled it also set the pipe
 153          * it is connected to in the pipe parameter. */
 154         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 155         /* Reconstructs the equivalent mode flags for the current hardware
 156          * state. This must be called _after_ display->get_pipe_config has
 157          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 158          * be set correctly before calling this function. */
 159         void (*get_config)(struct intel_encoder *,
 160                            struct intel_crtc_config *pipe_config);
 161         /*
 162          * Called during system suspend after all pending requests for the
 163          * encoder are flushed (for example for DP AUX transactions) and
 164          * device interrupts are disabled.
 165          */
 166         void (*suspend)(struct intel_encoder *);
 167         int crtc_mask;
 168         enum hpd_pin hpd_pin;
 169 };
 170
 171 struct intel_panel {
 172         struct drm_display_mode *fixed_mode;
 173         struct drm_display_mode *downclock_mode;
 174         int fitting_mode;
 175
 176         /* backlight */
 177         struct {
 178                 bool present;
 179                 u32 level;
 180                 u32 min;
 181                 u32 max;
 182                 bool enabled;
 183                 bool combination_mode;  /* gen 2/4 only */
 184                 bool active_low_pwm;
 185                 struct backlight_device *device;
 186         } backlight;
 187
 188         void (*backlight_power)(struct intel_connector *, bool enable);
 189 };
 190
 191 struct intel_connector {
 192         struct drm_connector base;
 193         /*
 194          * The fixed encoder this connector is connected to.
 195          */
 196         struct intel_encoder *encoder;
 197
 198         /*
 199          * The new encoder this connector will be driven. Only differs from
 200          * encoder while a modeset is in progress.
 201          */
 202         struct intel_encoder *new_encoder;
 203
 204         /* Reads out the current hw, returning true if the connector is enabled
 205          * and active (i.e. dpms ON state). */
 206         bool (*get_hw_state)(struct intel_connector *);
 207
 208         /*
 209          * Removes all interfaces through which the connector is accessible
 210          * - like sysfs, debugfs entries -, so that no new operations can be
 211          * started on the connector. Also makes sure all currently pending
 212          * operations finish before returing.
 213          */
 214         void (*unregister)(struct intel_connector *);
 215
 216         /* Panel info for eDP and LVDS */
 217         struct intel_panel panel;
 218
 219         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 220         struct edid *edid;
 221         struct edid *detect_edid;
 222
 223         /* since POLL and HPD connectors may use the same HPD line keep the native
 224            state of connector->polled in case hotplug storm detection changes it */
 225         u8 polled;
 226
 227         void *port; /* store this opaque as its illegal to dereference it */
 228
 229         struct intel_dp *mst_port;
 230 };
 231
 232 typedef struct dpll {
 233         /* given values */
 234         int n;
 235         int m1, m2;
 236         int p1, p2;
 237         /* derived values */
 238         int     dot;
 239         int     vco;
 240         int     m;
 241         int     p;
 242 } intel_clock_t;
 243
 244 struct intel_plane_state {
 245         struct drm_crtc *crtc;
 246         struct drm_framebuffer *fb;
 247         struct drm_rect src;
 248         struct drm_rect dst;
 249         struct drm_rect clip;
 250         struct drm_rect orig_src;
 251         struct drm_rect orig_dst;
 252         bool visible;
 253 };
 254
 255 struct intel_plane_config {
 256         bool tiled;
 257         int size;
 258         u32 base;
 259 };
 260
 261 struct intel_crtc_config {
 262         /**
 263          * quirks - bitfield with hw state readout quirks
 264          *
 265          * For various reasons the hw state readout code might not be able to
 266          * completely faithfully read out the current state. These cases are
 267          * tracked with quirk flags so that fastboot and state checker can act
 268          * accordingly.
 269          */
 270 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 271 #define PIPE_CONFIG_QUIRK_INHERITED_MODE        (1<<1) /* mode inherited from firmware */
 272         unsigned long quirks;
 273
 274         /* User requested mode, only valid as a starting point to
 275          * compute adjusted_mode, except in the case of (S)DVO where
 276          * it's also for the output timings of the (S)DVO chip.
 277          * adjusted_mode will then correspond to the S(DVO) chip's
 278          * preferred input timings. */
 279         struct drm_display_mode requested_mode;
 280         /* Actual pipe timings ie. what we program into the pipe timing
 281          * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
 282         struct drm_display_mode adjusted_mode;
 283
 284         /* Pipe source size (ie. panel fitter input size)
 285          * All planes will be positioned inside this space,
 286          * and get clipped at the edges. */
 287         int pipe_src_w, pipe_src_h;
 288
 289         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 290          * between pch encoders and cpu encoders. */
 291         bool has_pch_encoder;
 292
 293         /* CPU Transcoder for the pipe. Currently this can only differ from the
 294          * pipe on Haswell (where we have a special eDP transcoder). */
 295         enum transcoder cpu_transcoder;
 296
 297         /*
 298          * Use reduced/limited/broadcast rbg range, compressing from the full
 299          * range fed into the crtcs.
 300          */
 301         bool limited_color_range;
 302
 303         /* DP has a bunch of special case unfortunately, so mark the pipe
 304          * accordingly. */
 305         bool has_dp_encoder;
 306
 307         /* Whether we should send NULL infoframes. Required for audio. */
 308         bool has_hdmi_sink;
 309
 310         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 311          * has_dp_encoder is set. */
 312         bool has_audio;
 313
 314         /*
 315          * Enable dithering, used when the selected pipe bpp doesn't match the
 316          * plane bpp.
 317          */
 318         bool dither;
 319
 320         /* Controls for the clock computation, to override various stages. */
 321         bool clock_set;
 322
 323         /* SDVO TV has a bunch of special case. To make multifunction encoders
 324          * work correctly, we need to track this at runtime.*/
 325         bool sdvo_tv_clock;
 326
 327         /*
 328          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 329          * required. This is set in the 2nd loop of calling encoder's
 330          * ->compute_config if the first pick doesn't work out.
 331          */
 332         bool bw_constrained;
 333
 334         /* Settings for the intel dpll used on pretty much everything but
 335          * haswell. */
 336         struct dpll dpll;
 337
 338         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 339         enum intel_dpll_id shared_dpll;
 340
 341         /* PORT_CLK_SEL for DDI ports. */
 342         uint32_t ddi_pll_sel;
 343
 344         /* Actual register state of the dpll, for shared dpll cross-checking. */
 345         struct intel_dpll_hw_state dpll_hw_state;
 346
 347         int pipe_bpp;
 348         struct intel_link_m_n dp_m_n;
 349
 350         /* m2_n2 for eDP downclock */
 351         struct intel_link_m_n dp_m2_n2;
 352         bool has_drrs;
 353
 354         /*
 355          * Frequence the dpll for the port should run at. Differs from the
 356          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 357          * already multiplied by pixel_multiplier.
 358          */
 359         int port_clock;
 360
 361         /* Used by SDVO (and if we ever fix it, HDMI). */
 362         unsigned pixel_multiplier;
 363
 364         /* Panel fitter controls for gen2-gen4 + VLV */
 365         struct {
 366                 u32 control;
 367                 u32 pgm_ratios;
 368                 u32 lvds_border_bits;
 369         } gmch_pfit;
 370
 371         /* Panel fitter placement and size for Ironlake+ */
 372         struct {
 373                 u32 pos;
 374                 u32 size;
 375                 bool enabled;
 376                 bool force_thru;
 377         } pch_pfit;
 378
 379         /* FDI configuration, only valid if has_pch_encoder is set. */
 380         int fdi_lanes;
 381         struct intel_link_m_n fdi_m_n;
 382
 383         bool ips_enabled;
 384
 385         bool double_wide;
 386
 387         bool dp_encoder_is_mst;
 388         int pbn;
 389 };
 390
 391 struct intel_pipe_wm {
 392         struct intel_wm_level wm[5];
 393         uint32_t linetime;
 394         bool fbc_wm_enabled;
 395         bool pipe_enabled;
 396         bool sprites_enabled;
 397         bool sprites_scaled;
 398 };
 399
 400 struct intel_mmio_flip {
 401         u32 seqno;
 402         u32 ring_id;
 403 };
 404
 405 struct intel_crtc {
 406         struct drm_crtc base;
 407         enum pipe pipe;
 408         enum plane plane;
 409         u8 lut_r[256], lut_g[256], lut_b[256];
 410         /*
 411          * Whether the crtc and the connected output pipeline is active. Implies
 412          * that crtc->enabled is set, i.e. the current mode configuration has
 413          * some outputs connected to this crtc.
 414          */
 415         bool active;
 416         unsigned long enabled_power_domains;
 417         bool primary_enabled; /* is the primary plane (partially) visible? */
 418         bool lowfreq_avail;
 419         struct intel_overlay *overlay;
 420         struct intel_unpin_work *unpin_work;
 421
 422         atomic_t unpin_work_count;
 423
 424         /* Display surface base address adjustement for pageflips. Note that on
 425          * gen4+ this only adjusts up to a tile, offsets within a tile are
 426          * handled in the hw itself (with the TILEOFF register). */
 427         unsigned long dspaddr_offset;
 428
 429         struct drm_i915_gem_object *cursor_bo;
 430         uint32_t cursor_addr;
 431         int16_t cursor_width, cursor_height;
 432         uint32_t cursor_cntl;
 433         uint32_t cursor_size;
 434         uint32_t cursor_base;
 435
 436         struct intel_plane_config plane_config;
 437         struct intel_crtc_config config;
 438         struct intel_crtc_config *new_config;
 439         bool new_enabled;
 440
 441         /* reset counter value when the last flip was submitted */
 442         unsigned int reset_counter;
 443
 444         /* Access to these should be protected by dev_priv->irq_lock. */
 445         bool cpu_fifo_underrun_disabled;
 446         bool pch_fifo_underrun_disabled;
 447
 448         /* per-pipe watermark state */
 449         struct {
 450                 /* watermarks currently being used  */
 451                 struct intel_pipe_wm active;
 452         } wm;
 453
 454         int scanline_offset;
 455         struct intel_mmio_flip mmio_flip;
 456 };
 457
 458 struct intel_plane_wm_parameters {
 459         uint32_t horiz_pixels;
 460         uint32_t vert_pixels;
 461         uint8_t bytes_per_pixel;
 462         bool enabled;
 463         bool scaled;
 464 };
 465
 466 struct intel_plane {
 467         struct drm_plane base;
 468         int plane;
 469         enum pipe pipe;
 470         struct drm_i915_gem_object *obj;
 471         bool can_scale;
 472         int max_downscale;
 473         int crtc_x, crtc_y;
 474         unsigned int crtc_w, crtc_h;
 475         uint32_t src_x, src_y;
 476         uint32_t src_w, src_h;
 477         unsigned int rotation;
 478
 479         /* Since we need to change the watermarks before/after
 480          * enabling/disabling the planes, we need to store the parameters here
 481          * as the other pieces of the struct may not reflect the values we want
 482          * for the watermark calculations. Currently only Haswell uses this.
 483          */
 484         struct intel_plane_wm_parameters wm;
 485
 486         void (*update_plane)(struct drm_plane *plane,
 487                              struct drm_crtc *crtc,
 488                              struct drm_framebuffer *fb,
 489                              struct drm_i915_gem_object *obj,
 490                              int crtc_x, int crtc_y,
 491                              unsigned int crtc_w, unsigned int crtc_h,
 492                              uint32_t x, uint32_t y,
 493                              uint32_t src_w, uint32_t src_h);
 494         void (*disable_plane)(struct drm_plane *plane,
 495                               struct drm_crtc *crtc);
 496         int (*update_colorkey)(struct drm_plane *plane,
 497                                struct drm_intel_sprite_colorkey *key);
 498         void (*get_colorkey)(struct drm_plane *plane,
 499                              struct drm_intel_sprite_colorkey *key);
 500 };
 501
 502 struct intel_watermark_params {
 503         unsigned long fifo_size;
 504         unsigned long max_wm;
 505         unsigned long default_wm;
 506         unsigned long guard_size;
 507         unsigned long cacheline_size;
 508 };
 509
 510 struct cxsr_latency {
 511         int is_desktop;
 512         int is_ddr3;
 513         unsigned long fsb_freq;
 514         unsigned long mem_freq;
 515         unsigned long display_sr;
 516         unsigned long display_hpll_disable;
 517         unsigned long cursor_sr;
 518         unsigned long cursor_hpll_disable;
 519 };
 520
 521 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 522 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 523 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 524 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 525 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 526 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 527
 528 struct intel_hdmi {
 529         u32 hdmi_reg;
 530         int ddc_bus;
 531         uint32_t color_range;
 532         bool color_range_auto;
 533         bool has_hdmi_sink;
 534         bool has_audio;
 535         enum hdmi_force_audio force_audio;
 536         bool rgb_quant_range_selectable;
 537         enum hdmi_picture_aspect aspect_ratio;
 538         void (*write_infoframe)(struct drm_encoder *encoder,
 539                                 enum hdmi_infoframe_type type,
 540                                 const void *frame, ssize_t len);
 541         void (*set_infoframes)(struct drm_encoder *encoder,
 542                                bool enable,
 543                                struct drm_display_mode *adjusted_mode);
 544 };
 545
 546 struct intel_dp_mst_encoder;
 547 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 548
 549 /**
 550  * HIGH_RR is the highest eDP panel refresh rate read from EDID
 551  * LOW_RR is the lowest eDP panel refresh rate found from EDID
 552  * parsing for same resolution.
 553  */
 554 enum edp_drrs_refresh_rate_type {
 555         DRRS_HIGH_RR,
 556         DRRS_LOW_RR,
 557         DRRS_MAX_RR, /* RR count */
 558 };
 559
 560 struct intel_dp {
 561         uint32_t output_reg;
 562         uint32_t aux_ch_ctl_reg;
 563         uint32_t DP;
 564         bool has_audio;
 565         enum hdmi_force_audio force_audio;
 566         uint32_t color_range;
 567         bool color_range_auto;
 568         uint8_t link_bw;
 569         uint8_t lane_count;
 570         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 571         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 572         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 573         struct drm_dp_aux aux;
 574         uint8_t train_set[4];
 575         int panel_power_up_delay;
 576         int panel_power_down_delay;
 577         int panel_power_cycle_delay;
 578         int backlight_on_delay;
 579         int backlight_off_delay;
 580         struct delayed_work panel_vdd_work;
 581         bool want_panel_vdd;
 582         unsigned long last_power_cycle;
 583         unsigned long last_power_on;
 584         unsigned long last_backlight_off;
 585
 586         struct notifier_block edp_notifier;
 587
 588         /*
 589          * Pipe whose power sequencer is currently locked into
 590          * this port. Only relevant on VLV/CHV.
 591          */
 592         enum pipe pps_pipe;
 593
 594         bool use_tps3;
 595         bool can_mst; /* this port supports mst */
 596         bool is_mst;
 597         int active_mst_links;
 598         /* connector directly attached - won't be use for modeset in mst world */
 599         struct intel_connector *attached_connector;
 600
 601         /* mst connector list */
 602         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 603         struct drm_dp_mst_topology_mgr mst_mgr;
 604
 605         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 606         /*
 607          * This function returns the value we have to program the AUX_CTL
 608          * register with to kick off an AUX transaction.
 609          */
 610         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 611                                      bool has_aux_irq,
 612                                      int send_bytes,
 613                                      uint32_t aux_clock_divider);
 614         struct {
 615                 enum drrs_support_type type;
 616                 enum edp_drrs_refresh_rate_type refresh_rate_type;
 617                 struct mutex mutex;
 618         } drrs_state;
 619
 620 };
 621
 622 struct intel_digital_port {
 623         struct intel_encoder base;
 624         enum port port;
 625         u32 saved_port_bits;
 626         struct intel_dp dp;
 627         struct intel_hdmi hdmi;
 628         bool (*hpd_pulse)(struct intel_digital_port *, bool);
 629 };
 630
 631 struct intel_dp_mst_encoder {
 632         struct intel_encoder base;
 633         enum pipe pipe;
 634         struct intel_digital_port *primary;
 635         void *port; /* store this opaque as its illegal to dereference it */
 636 };
 637
 638 static inline int
 639 vlv_dport_to_channel(struct intel_digital_port *dport)
 640 {
 641         switch (dport->port) {
 642         case PORT_B:
 643         case PORT_D:
 644                 return DPIO_CH0;
 645         case PORT_C:
 646                 return DPIO_CH1;
 647         default:
 648                 BUG();
 649         }
 650 }
 651
 652 static inline int
 653 vlv_pipe_to_channel(enum pipe pipe)
 654 {
 655         switch (pipe) {
 656         case PIPE_A:
 657         case PIPE_C:
 658                 return DPIO_CH0;
 659         case PIPE_B:
 660                 return DPIO_CH1;
 661         default:
 662                 BUG();
 663         }
 664 }
 665
 666 static inline struct drm_crtc *
 667 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 668 {
 669         struct drm_i915_private *dev_priv = dev->dev_private;
 670         return dev_priv->pipe_to_crtc_mapping[pipe];
 671 }
 672
 673 static inline struct drm_crtc *
 674 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 675 {
 676         struct drm_i915_private *dev_priv = dev->dev_private;
 677         return dev_priv->plane_to_crtc_mapping[plane];
 678 }
 679
 680 struct intel_unpin_work {
 681         struct work_struct work;
 682         struct drm_crtc *crtc;
 683         struct drm_i915_gem_object *old_fb_obj;
 684         struct drm_i915_gem_object *pending_flip_obj;
 685         struct drm_pending_vblank_event *event;
 686         atomic_t pending;
 687 #define INTEL_FLIP_INACTIVE     0
 688 #define INTEL_FLIP_PENDING      1
 689 #define INTEL_FLIP_COMPLETE     2
 690         u32 flip_count;
 691         u32 gtt_offset;
 692         struct intel_engine_cs *flip_queued_ring;
 693         u32 flip_queued_seqno;
 694         int flip_queued_vblank;
 695         int flip_ready_vblank;
 696         bool enable_stall_check;
 697 };
 698
 699 struct intel_set_config {
 700         struct drm_encoder **save_connector_encoders;
 701         struct drm_crtc **save_encoder_crtcs;
 702         bool *save_crtc_enabled;
 703
 704         bool fb_changed;
 705         bool mode_changed;
 706 };
 707
 708 struct intel_load_detect_pipe {
 709         struct drm_framebuffer *release_fb;
 710         bool load_detect_temp;
 711         int dpms_mode;
 712 };
 713
 714 static inline struct intel_encoder *
 715 intel_attached_encoder(struct drm_connector *connector)
 716 {
 717         return to_intel_connector(connector)->encoder;
 718 }
 719
 720 static inline struct intel_digital_port *
 721 enc_to_dig_port(struct drm_encoder *encoder)
 722 {
 723         return container_of(encoder, struct intel_digital_port, base.base);
 724 }
 725
 726 static inline struct intel_dp_mst_encoder *
 727 enc_to_mst(struct drm_encoder *encoder)
 728 {
 729         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 730 }
 731
 732 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 733 {
 734         return &enc_to_dig_port(encoder)->dp;
 735 }
 736
 737 static inline struct intel_digital_port *
 738 dp_to_dig_port(struct intel_dp *intel_dp)
 739 {
 740         return container_of(intel_dp, struct intel_digital_port, dp);
 741 }
 742
 743 static inline struct intel_digital_port *
 744 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 745 {
 746         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 747 }
 748
 749 /*
 750  * Returns the number of planes for this pipe, ie the number of sprites + 1
 751  * (primary plane). This doesn't count the cursor plane then.
 752  */
 753 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
 754 {
 755         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
 756 }
 757
 758 /* intel_fifo_underrun.c */
 759 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 760                                            enum pipe pipe, bool enable);
 761 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 762                                            enum transcoder pch_transcoder,
 763                                            bool enable);
 764 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 765                                          enum pipe pipe);
 766 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 767                                          enum transcoder pch_transcoder);
 768 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
 769
 770 /* i915_irq.c */
 771 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 772 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 773 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 774 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 775 void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 776 void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 777 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
 778 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
 779 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 780 {
 781         /*
 782          * We only use drm_irq_uninstall() at unload and VT switch, so
 783          * this is the only thing we need to check.
 784          */
 785         return dev_priv->pm.irqs_enabled;
 786 }
 787
 788 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 789 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
 790
 791 /* intel_crt.c */
 792 void intel_crt_init(struct drm_device *dev);
 793
 794
 795 /* intel_ddi.c */
 796 void intel_prepare_ddi(struct drm_device *dev);
 797 void hsw_fdi_link_train(struct drm_crtc *crtc);
 798 void intel_ddi_init(struct drm_device *dev, enum port port);
 799 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 800 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 801 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 802 void intel_ddi_pll_init(struct drm_device *dev);
 803 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 804 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 805                                        enum transcoder cpu_transcoder);
 806 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 807 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 808 bool intel_ddi_pll_select(struct intel_crtc *crtc);
 809 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 810 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 811 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 812 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 813 void intel_ddi_get_config(struct intel_encoder *encoder,
 814                           struct intel_crtc_config *pipe_config);
 815
 816 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
 817 void intel_ddi_clock_get(struct intel_encoder *encoder,
 818                          struct intel_crtc_config *pipe_config);
 819 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
 820
 821 /* intel_frontbuffer.c */
 822 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
 823                              struct intel_engine_cs *ring);
 824 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
 825                                     unsigned frontbuffer_bits);
 826 void intel_frontbuffer_flip_complete(struct drm_device *dev,
 827                                      unsigned frontbuffer_bits);
 828 void intel_frontbuffer_flush(struct drm_device *dev,
 829                              unsigned frontbuffer_bits);
 830 /**
 831  * intel_frontbuffer_flip - synchronous frontbuffer flip
 832  * @dev: DRM device
 833  * @frontbuffer_bits: frontbuffer plane tracking bits
 834  *
 835  * This function gets called after scheduling a flip on @obj. This is for
 836  * synchronous plane updates which will happen on the next vblank and which will
 837  * not get delayed by pending gpu rendering.
 838  *
 839  * Can be called without any locks held.
 840  */
 841 static inline
 842 void intel_frontbuffer_flip(struct drm_device *dev,
 843                             unsigned frontbuffer_bits)
 844 {
 845         intel_frontbuffer_flush(dev, frontbuffer_bits);
 846 }
 847
 848 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
 849
 850
 851 /* intel_audio.c */
 852 void intel_init_audio(struct drm_device *dev);
 853 void intel_write_eld(struct intel_encoder *encoder);
 854
 855 /* intel_display.c */
 856 const char *intel_output_name(int output);
 857 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 858 int intel_pch_rawclk(struct drm_device *dev);
 859 void intel_mark_busy(struct drm_device *dev);
 860 void intel_mark_idle(struct drm_device *dev);
 861 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 862 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
 863 void intel_crtc_update_dpms(struct drm_crtc *crtc);
 864 void intel_encoder_destroy(struct drm_encoder *encoder);
 865 void intel_connector_dpms(struct drm_connector *, int mode);
 866 bool intel_connector_get_hw_state(struct intel_connector *connector);
 867 void intel_modeset_check_state(struct drm_device *dev);
 868 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 869                                 struct intel_digital_port *port);
 870 void intel_connector_attach_encoder(struct intel_connector *connector,
 871                                     struct intel_encoder *encoder);
 872 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 873 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 874                                              struct drm_crtc *crtc);
 875 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
 876 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 877                                 struct drm_file *file_priv);
 878 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 879                                              enum pipe pipe);
 880 bool intel_pipe_has_type(struct intel_crtc *crtc, int type);
 881 static inline void
 882 intel_wait_for_vblank(struct drm_device *dev, int pipe)
 883 {
 884         drm_wait_one_vblank(dev, pipe);
 885 }
 886 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 887 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 888                          struct intel_digital_port *dport);
 889 bool intel_get_load_detect_pipe(struct drm_connector *connector,
 890                                 struct drm_display_mode *mode,
 891                                 struct intel_load_detect_pipe *old,
 892                                 struct drm_modeset_acquire_ctx *ctx);
 893 void intel_release_load_detect_pipe(struct drm_connector *connector,
 894                                     struct intel_load_detect_pipe *old);
 895 int intel_pin_and_fence_fb_obj(struct drm_device *dev,
 896                                struct drm_i915_gem_object *obj,
 897                                struct intel_engine_cs *pipelined);
 898 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 899 struct drm_framebuffer *
 900 __intel_framebuffer_create(struct drm_device *dev,
 901                            struct drm_mode_fb_cmd2 *mode_cmd,
 902                            struct drm_i915_gem_object *obj);
 903 void intel_prepare_page_flip(struct drm_device *dev, int plane);
 904 void intel_finish_page_flip(struct drm_device *dev, int pipe);
 905 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 906 void intel_check_page_flip(struct drm_device *dev, int pipe);
 907
 908 /* shared dpll functions */
 909 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 910 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 911                         struct intel_shared_dpll *pll,
 912                         bool state);
 913 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 914 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 915 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
 916 void intel_put_shared_dpll(struct intel_crtc *crtc);
 917
 918 /* modesetting asserts */
 919 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 920                            enum pipe pipe);
 921 void assert_pll(struct drm_i915_private *dev_priv,
 922                 enum pipe pipe, bool state);
 923 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 924 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 925 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 926                        enum pipe pipe, bool state);
 927 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 928 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 929 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 930 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 931 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 932 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
 933                                              unsigned int tiling_mode,
 934                                              unsigned int bpp,
 935                                              unsigned int pitch);
 936 void intel_display_handle_reset(struct drm_device *dev);
 937 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 938 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 939 void intel_dp_get_m_n(struct intel_crtc *crtc,
 940                       struct intel_crtc_config *pipe_config);
 941 void intel_dp_set_m_n(struct intel_crtc *crtc);
 942 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 943 void
 944 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
 945                                 int dotclock);
 946 bool intel_crtc_active(struct drm_crtc *crtc);
 947 void hsw_enable_ips(struct intel_crtc *crtc);
 948 void hsw_disable_ips(struct intel_crtc *crtc);
 949 enum intel_display_power_domain
 950 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
 951 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 952                                  struct intel_crtc_config *pipe_config);
 953 int intel_format_to_fourcc(int format);
 954 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
 955 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
 956
 957 /* intel_dp.c */
 958 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
 959 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 960                              struct intel_connector *intel_connector);
 961 void intel_dp_start_link_train(struct intel_dp *intel_dp);
 962 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 963 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 964 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 965 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
 966 void intel_dp_check_link_status(struct intel_dp *intel_dp);
 967 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
 968 bool intel_dp_compute_config(struct intel_encoder *encoder,
 969                              struct intel_crtc_config *pipe_config);
 970 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
 971 bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
 972                         bool long_hpd);
 973 void intel_edp_backlight_on(struct intel_dp *intel_dp);
 974 void intel_edp_backlight_off(struct intel_dp *intel_dp);
 975 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
 976 void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder);
 977 void intel_edp_panel_on(struct intel_dp *intel_dp);
 978 void intel_edp_panel_off(struct intel_dp *intel_dp);
 979 void intel_edp_psr_enable(struct intel_dp *intel_dp);
 980 void intel_edp_psr_disable(struct intel_dp *intel_dp);
 981 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
 982 void intel_edp_psr_invalidate(struct drm_device *dev,
 983                               unsigned frontbuffer_bits);
 984 void intel_edp_psr_flush(struct drm_device *dev,
 985                          unsigned frontbuffer_bits);
 986 void intel_edp_psr_init(struct drm_device *dev);
 987
 988 int intel_dp_handle_hpd_irq(struct intel_digital_port *digport, bool long_hpd);
 989 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
 990 void intel_dp_mst_suspend(struct drm_device *dev);
 991 void intel_dp_mst_resume(struct drm_device *dev);
 992 int intel_dp_max_link_bw(struct intel_dp *intel_dp);
 993 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
 994 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
 995 /* intel_dp_mst.c */
 996 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
 997 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
 998 /* intel_dsi.c */
 999 void intel_dsi_init(struct drm_device *dev);
1000
1001
1002 /* intel_dvo.c */
1003 void intel_dvo_init(struct drm_device *dev);
1004
1005
1006 /* legacy fbdev emulation in intel_fbdev.c */
1007 #ifdef CONFIG_DRM_I915_FBDEV
1008 extern int intel_fbdev_init(struct drm_device *dev);
1009 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1010 extern void intel_fbdev_fini(struct drm_device *dev);
1011 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1012 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1013 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1014 #else
1015 static inline int intel_fbdev_init(struct drm_device *dev)
1016 {
1017         return 0;
1018 }
1019
1020 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1021 {
1022 }
1023
1024 static inline void intel_fbdev_fini(struct drm_device *dev)
1025 {
1026 }
1027
1028 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1029 {
1030 }
1031
1032 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1033 {
1034 }
1035 #endif
1036
1037 /* intel_hdmi.c */
1038 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1039 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1040                                struct intel_connector *intel_connector);
1041 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1042 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1043                                struct intel_crtc_config *pipe_config);
1044
1045
1046 /* intel_lvds.c */
1047 void intel_lvds_init(struct drm_device *dev);
1048 bool intel_is_dual_link_lvds(struct drm_device *dev);
1049
1050
1051 /* intel_modes.c */
1052 int intel_connector_update_modes(struct drm_connector *connector,
1053                                  struct edid *edid);
1054 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1055 void intel_attach_force_audio_property(struct drm_connector *connector);
1056 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1057
1058
1059 /* intel_overlay.c */
1060 void intel_setup_overlay(struct drm_device *dev);
1061 void intel_cleanup_overlay(struct drm_device *dev);
1062 int intel_overlay_switch_off(struct intel_overlay *overlay);
1063 int intel_overlay_put_image(struct drm_device *dev, void *data,
1064                             struct drm_file *file_priv);
1065 int intel_overlay_attrs(struct drm_device *dev, void *data,
1066                         struct drm_file *file_priv);
1067
1068
1069 /* intel_panel.c */
1070 int intel_panel_init(struct intel_panel *panel,
1071                      struct drm_display_mode *fixed_mode,
1072                      struct drm_display_mode *downclock_mode);
1073 void intel_panel_fini(struct intel_panel *panel);
1074 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1075                             struct drm_display_mode *adjusted_mode);
1076 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1077                              struct intel_crtc_config *pipe_config,
1078                              int fitting_mode);
1079 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1080                               struct intel_crtc_config *pipe_config,
1081                               int fitting_mode);
1082 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1083                                     u32 level, u32 max);
1084 int intel_panel_setup_backlight(struct drm_connector *connector);
1085 void intel_panel_enable_backlight(struct intel_connector *connector);
1086 void intel_panel_disable_backlight(struct intel_connector *connector);
1087 void intel_panel_destroy_backlight(struct drm_connector *connector);
1088 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1089 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1090 extern struct drm_display_mode *intel_find_panel_downclock(
1091                                 struct drm_device *dev,
1092                                 struct drm_display_mode *fixed_mode,
1093                                 struct drm_connector *connector);
1094
1095 /* intel_runtime_pm.c */
1096 int intel_power_domains_init(struct drm_i915_private *);
1097 void intel_power_domains_fini(struct drm_i915_private *);
1098 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1099 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1100
1101 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1102                                     enum intel_display_power_domain domain);
1103 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1104                                       enum intel_display_power_domain domain);
1105 void intel_display_power_get(struct drm_i915_private *dev_priv,
1106                              enum intel_display_power_domain domain);
1107 void intel_display_power_put(struct drm_i915_private *dev_priv,
1108                              enum intel_display_power_domain domain);
1109 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1110 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1111 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1112 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1113 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1114
1115 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1116
1117 /* intel_pm.c */
1118 void intel_init_clock_gating(struct drm_device *dev);
1119 void intel_suspend_hw(struct drm_device *dev);
1120 int ilk_wm_max_level(const struct drm_device *dev);
1121 void intel_update_watermarks(struct drm_crtc *crtc);
1122 void intel_update_sprite_watermarks(struct drm_plane *plane,
1123                                     struct drm_crtc *crtc,
1124                                     uint32_t sprite_width,
1125                                     uint32_t sprite_height,
1126                                     int pixel_size,
1127                                     bool enabled, bool scaled);
1128 void intel_init_pm(struct drm_device *dev);
1129 void intel_pm_setup(struct drm_device *dev);
1130 bool intel_fbc_enabled(struct drm_device *dev);
1131 void intel_update_fbc(struct drm_device *dev);
1132 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1133 void intel_gpu_ips_teardown(void);
1134 void intel_init_gt_powersave(struct drm_device *dev);
1135 void intel_cleanup_gt_powersave(struct drm_device *dev);
1136 void intel_enable_gt_powersave(struct drm_device *dev);
1137 void intel_disable_gt_powersave(struct drm_device *dev);
1138 void intel_suspend_gt_powersave(struct drm_device *dev);
1139 void intel_reset_gt_powersave(struct drm_device *dev);
1140 void ironlake_teardown_rc6(struct drm_device *dev);
1141 void gen6_update_ring_freq(struct drm_device *dev);
1142 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1143 void gen6_rps_boost(struct drm_i915_private *dev_priv);
1144 void ilk_wm_get_hw_state(struct drm_device *dev);
1145
1146
1147 /* intel_sdvo.c */
1148 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1149
1150
1151 /* intel_sprite.c */
1152 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1153 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1154                                enum plane plane);
1155 int intel_plane_set_property(struct drm_plane *plane,
1156                              struct drm_property *prop,
1157                              uint64_t val);
1158 int intel_plane_restore(struct drm_plane *plane);
1159 void intel_plane_disable(struct drm_plane *plane);
1160 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1161                               struct drm_file *file_priv);
1162 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
1163                               struct drm_file *file_priv);
1164
1165
1166 /* intel_tv.c */
1167 void intel_tv_init(struct drm_device *dev);
1168
1169 #endif /* __INTEL_DRV_H__ */