2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_dual_mode_helper.h>
37 #include <drm/drm_dp_mst_helper.h>
38 #include <drm/drm_rect.h>
39 #include <drm/drm_atomic.h>
42 * _wait_for - magic (register) wait macro
44 * Does the right thing for modeset paths when run under kdgb or similar atomic
45 * contexts. Note that it's important that we check the condition again after
46 * having timed out, since the timeout could be due to preemption or similar and
47 * we've never had a chance to check the condition before the timeout.
49 * TODO: When modesetting has fully transitioned to atomic, the below
50 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
53 #define _wait_for(COND, US, W) ({ \
54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
57 if (time_after(jiffies, timeout__)) { \
62 if ((W) && drm_can_sleep()) { \
63 usleep_range((W), (W)*2); \
71 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
73 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
74 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
75 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
77 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
80 #define _wait_for_atomic(COND, US, ATOMIC) \
82 int cpu, ret, timeout = (US) * 1000; \
84 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
85 BUILD_BUG_ON((US) > 50000); \
88 cpu = smp_processor_id(); \
90 base = local_clock(); \
92 u64 now = local_clock(); \
99 if (now - base >= timeout) { \
106 if (unlikely(cpu != smp_processor_id())) { \
107 timeout -= now - base; \
108 cpu = smp_processor_id(); \
109 base = local_clock(); \
116 #define wait_for_us(COND, US) \
119 BUILD_BUG_ON(!__builtin_constant_p(US)); \
121 ret__ = _wait_for((COND), (US), 10); \
123 ret__ = _wait_for_atomic((COND), (US), 0); \
127 #define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000, 1)
128 #define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US), 1)
130 #define KHz(x) (1000 * (x))
131 #define MHz(x) KHz(1000 * (x))
134 * Display related stuff
137 /* store information about an Ixxx DVO */
138 /* The i830->i865 use multiple DVOs with multiple i2cs */
139 /* the i915, i945 have a single sDVO i2c bus - which is different */
140 #define MAX_OUTPUTS 6
141 /* maximum connectors per crtcs in the mode set */
143 /* Maximum cursor sizes */
144 #define GEN2_CURSOR_WIDTH 64
145 #define GEN2_CURSOR_HEIGHT 64
146 #define MAX_CURSOR_WIDTH 256
147 #define MAX_CURSOR_HEIGHT 256
149 #define INTEL_I2C_BUS_DVO 1
150 #define INTEL_I2C_BUS_SDVO 2
152 /* these are outputs from the chip - integrated only
153 external chips are via DVO or SDVO output */
154 enum intel_output_type
{
155 INTEL_OUTPUT_UNUSED
= 0,
156 INTEL_OUTPUT_ANALOG
= 1,
157 INTEL_OUTPUT_DVO
= 2,
158 INTEL_OUTPUT_SDVO
= 3,
159 INTEL_OUTPUT_LVDS
= 4,
160 INTEL_OUTPUT_TVOUT
= 5,
161 INTEL_OUTPUT_HDMI
= 6,
163 INTEL_OUTPUT_EDP
= 8,
164 INTEL_OUTPUT_DSI
= 9,
165 INTEL_OUTPUT_UNKNOWN
= 10,
166 INTEL_OUTPUT_DP_MST
= 11,
169 #define INTEL_DVO_CHIP_NONE 0
170 #define INTEL_DVO_CHIP_LVDS 1
171 #define INTEL_DVO_CHIP_TMDS 2
172 #define INTEL_DVO_CHIP_TVOUT 4
174 #define INTEL_DSI_VIDEO_MODE 0
175 #define INTEL_DSI_COMMAND_MODE 1
177 struct intel_framebuffer
{
178 struct drm_framebuffer base
;
179 struct drm_i915_gem_object
*obj
;
180 struct intel_rotation_info rot_info
;
184 struct drm_fb_helper helper
;
185 struct intel_framebuffer
*fb
;
186 async_cookie_t cookie
;
190 struct intel_encoder
{
191 struct drm_encoder base
;
193 enum intel_output_type type
;
194 unsigned int cloneable
;
195 void (*hot_plug
)(struct intel_encoder
*);
196 bool (*compute_config
)(struct intel_encoder
*,
197 struct intel_crtc_state
*);
198 void (*pre_pll_enable
)(struct intel_encoder
*);
199 void (*pre_enable
)(struct intel_encoder
*);
200 void (*enable
)(struct intel_encoder
*);
201 void (*mode_set
)(struct intel_encoder
*intel_encoder
);
202 void (*disable
)(struct intel_encoder
*);
203 void (*post_disable
)(struct intel_encoder
*);
204 void (*post_pll_disable
)(struct intel_encoder
*);
205 /* Read out the current hw state of this connector, returning true if
206 * the encoder is active. If the encoder is enabled it also set the pipe
207 * it is connected to in the pipe parameter. */
208 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
209 /* Reconstructs the equivalent mode flags for the current hardware
210 * state. This must be called _after_ display->get_pipe_config has
211 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
212 * be set correctly before calling this function. */
213 void (*get_config
)(struct intel_encoder
*,
214 struct intel_crtc_state
*pipe_config
);
216 * Called during system suspend after all pending requests for the
217 * encoder are flushed (for example for DP AUX transactions) and
218 * device interrupts are disabled.
220 void (*suspend
)(struct intel_encoder
*);
222 enum hpd_pin hpd_pin
;
226 struct drm_display_mode
*fixed_mode
;
227 struct drm_display_mode
*downclock_mode
;
237 bool combination_mode
; /* gen 2/4 only */
241 bool util_pin_active_low
; /* bxt+ */
242 u8 controller
; /* bxt+ only */
243 struct pwm_device
*pwm
;
245 struct backlight_device
*device
;
247 /* Connector and platform specific backlight functions */
248 int (*setup
)(struct intel_connector
*connector
, enum pipe pipe
);
249 uint32_t (*get
)(struct intel_connector
*connector
);
250 void (*set
)(struct intel_connector
*connector
, uint32_t level
);
251 void (*disable
)(struct intel_connector
*connector
);
252 void (*enable
)(struct intel_connector
*connector
);
253 uint32_t (*hz_to_pwm
)(struct intel_connector
*connector
,
255 void (*power
)(struct intel_connector
*, bool enable
);
259 struct intel_connector
{
260 struct drm_connector base
;
262 * The fixed encoder this connector is connected to.
264 struct intel_encoder
*encoder
;
266 /* Reads out the current hw, returning true if the connector is enabled
267 * and active (i.e. dpms ON state). */
268 bool (*get_hw_state
)(struct intel_connector
*);
270 /* Panel info for eDP and LVDS */
271 struct intel_panel panel
;
273 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
275 struct edid
*detect_edid
;
277 /* since POLL and HPD connectors may use the same HPD line keep the native
278 state of connector->polled in case hotplug storm detection changes it */
281 void *port
; /* store this opaque as its illegal to dereference it */
283 struct intel_dp
*mst_port
;
298 struct intel_atomic_state
{
299 struct drm_atomic_state base
;
304 * Calculated device cdclk, can be different from cdclk
305 * only when all crtc's are DPMS off.
307 unsigned int dev_cdclk
;
309 bool dpll_set
, modeset
;
312 * Does this transaction change the pipes that are active? This mask
313 * tracks which CRTC's have changed their active state at the end of
314 * the transaction (not counting the temporary disable during modesets).
315 * This mask should only be non-zero when intel_state->modeset is true,
316 * but the converse is not necessarily true; simply changing a mode may
317 * not flip the final active status of any CRTC's
319 unsigned int active_pipe_changes
;
321 unsigned int active_crtcs
;
322 unsigned int min_pixclk
[I915_MAX_PIPES
];
325 unsigned int cdclk_pll_vco
;
327 struct intel_shared_dpll_config shared_dpll
[I915_NUM_PLLS
];
330 * Current watermarks can't be trusted during hardware readout, so
331 * don't bother calculating intermediate watermarks.
333 bool skip_intermediate_wm
;
336 struct skl_wm_values wm_results
;
339 struct intel_plane_state
{
340 struct drm_plane_state base
;
343 struct drm_rect clip
;
348 * = -1 : not using a scaler
349 * >= 0 : using a scalers
351 * plane requiring a scaler:
352 * - During check_plane, its bit is set in
353 * crtc_state->scaler_state.scaler_users by calling helper function
354 * update_scaler_plane.
355 * - scaler_id indicates the scaler it got assigned.
357 * plane doesn't require a scaler:
358 * - this can happen when scaling is no more required or plane simply
360 * - During check_plane, corresponding bit is reset in
361 * crtc_state->scaler_state.scaler_users by calling helper function
362 * update_scaler_plane.
366 struct drm_intel_sprite_colorkey ckey
;
368 /* async flip related structures */
369 struct drm_i915_gem_request
*wait_req
;
372 struct intel_initial_plane_config
{
373 struct intel_framebuffer
*fb
;
379 #define SKL_MIN_SRC_W 8
380 #define SKL_MAX_SRC_W 4096
381 #define SKL_MIN_SRC_H 8
382 #define SKL_MAX_SRC_H 4096
383 #define SKL_MIN_DST_W 8
384 #define SKL_MAX_DST_W 4096
385 #define SKL_MIN_DST_H 8
386 #define SKL_MAX_DST_H 4096
388 struct intel_scaler
{
393 struct intel_crtc_scaler_state
{
394 #define SKL_NUM_SCALERS 2
395 struct intel_scaler scalers
[SKL_NUM_SCALERS
];
398 * scaler_users: keeps track of users requesting scalers on this crtc.
400 * If a bit is set, a user is using a scaler.
401 * Here user can be a plane or crtc as defined below:
402 * bits 0-30 - plane (bit position is index from drm_plane_index)
405 * Instead of creating a new index to cover planes and crtc, using
406 * existing drm_plane_index for planes which is well less than 31
407 * planes and bit 31 for crtc. This should be fine to cover all
410 * intel_atomic_setup_scalers will setup available scalers to users
411 * requesting scalers. It will gracefully fail if request exceeds
414 #define SKL_CRTC_INDEX 31
415 unsigned scaler_users
;
417 /* scaler used by crtc for panel fitting purpose */
421 /* drm_mode->private_flags */
422 #define I915_MODE_FLAG_INHERITED 1
424 struct intel_pipe_wm
{
425 struct intel_wm_level wm
[5];
426 struct intel_wm_level raw_wm
[5];
430 bool sprites_enabled
;
435 struct skl_wm_level wm
[8];
436 struct skl_wm_level trans_wm
;
440 struct intel_crtc_wm_state
{
444 * Intermediate watermarks; these can be
445 * programmed immediately since they satisfy
446 * both the current configuration we're
447 * switching away from and the new
448 * configuration we're switching to.
450 struct intel_pipe_wm intermediate
;
453 * Optimal watermarks, programmed post-vblank
454 * when this state is committed.
456 struct intel_pipe_wm optimal
;
460 /* gen9+ only needs 1-step wm programming */
461 struct skl_pipe_wm optimal
;
463 /* cached plane data rate */
464 unsigned plane_data_rate
[I915_MAX_PLANES
];
465 unsigned plane_y_data_rate
[I915_MAX_PLANES
];
467 /* minimum block allocation */
468 uint16_t minimum_blocks
[I915_MAX_PLANES
];
469 uint16_t minimum_y_blocks
[I915_MAX_PLANES
];
474 * Platforms with two-step watermark programming will need to
475 * update watermark programming post-vblank to switch from the
476 * safe intermediate watermarks to the optimal final
479 bool need_postvbl_update
;
482 struct intel_crtc_state
{
483 struct drm_crtc_state base
;
486 * quirks - bitfield with hw state readout quirks
488 * For various reasons the hw state readout code might not be able to
489 * completely faithfully read out the current state. These cases are
490 * tracked with quirk flags so that fastboot and state checker can act
493 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
494 unsigned long quirks
;
496 unsigned fb_bits
; /* framebuffers to flip */
497 bool update_pipe
; /* can a fast modeset be performed? */
499 bool update_wm_pre
, update_wm_post
; /* watermarks are updated */
500 bool fb_changed
; /* fb on any of the planes is changed */
502 /* Pipe source size (ie. panel fitter input size)
503 * All planes will be positioned inside this space,
504 * and get clipped at the edges. */
505 int pipe_src_w
, pipe_src_h
;
507 /* Whether to set up the PCH/FDI. Note that we never allow sharing
508 * between pch encoders and cpu encoders. */
509 bool has_pch_encoder
;
511 /* Are we sending infoframes on the attached port */
514 /* CPU Transcoder for the pipe. Currently this can only differ from the
515 * pipe on Haswell and later (where we have a special eDP transcoder)
516 * and Broxton (where we have special DSI transcoders). */
517 enum transcoder cpu_transcoder
;
520 * Use reduced/limited/broadcast rbg range, compressing from the full
521 * range fed into the crtcs.
523 bool limited_color_range
;
525 /* Bitmask of encoder types (enum intel_output_type)
526 * driven by the pipe.
528 unsigned int output_types
;
530 /* Whether we should send NULL infoframes. Required for audio. */
533 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
534 * has_dp_encoder is set. */
538 * Enable dithering, used when the selected pipe bpp doesn't match the
543 /* Controls for the clock computation, to override various stages. */
546 /* SDVO TV has a bunch of special case. To make multifunction encoders
547 * work correctly, we need to track this at runtime.*/
551 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
552 * required. This is set in the 2nd loop of calling encoder's
553 * ->compute_config if the first pick doesn't work out.
557 /* Settings for the intel dpll used on pretty much everything but
561 /* Selected dpll when shared or NULL. */
562 struct intel_shared_dpll
*shared_dpll
;
565 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
566 * - enum skl_dpll on SKL
568 uint32_t ddi_pll_sel
;
570 /* Actual register state of the dpll, for shared dpll cross-checking. */
571 struct intel_dpll_hw_state dpll_hw_state
;
573 /* DSI PLL registers */
579 struct intel_link_m_n dp_m_n
;
581 /* m2_n2 for eDP downclock */
582 struct intel_link_m_n dp_m2_n2
;
586 * Frequence the dpll for the port should run at. Differs from the
587 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
588 * already multiplied by pixel_multiplier.
592 /* Used by SDVO (and if we ever fix it, HDMI). */
593 unsigned pixel_multiplier
;
598 * Used by platforms having DP/HDMI PHY with programmable lane
599 * latency optimization.
601 uint8_t lane_lat_optim_mask
;
603 /* Panel fitter controls for gen2-gen4 + VLV */
607 u32 lvds_border_bits
;
610 /* Panel fitter placement and size for Ironlake+ */
618 /* FDI configuration, only valid if has_pch_encoder is set. */
620 struct intel_link_m_n fdi_m_n
;
628 bool dp_encoder_is_mst
;
631 struct intel_crtc_scaler_state scaler_state
;
633 /* w/a for waiting 2 vblanks during crtc enable */
634 enum pipe hsw_workaround_pipe
;
636 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
639 struct intel_crtc_wm_state wm
;
641 /* Gamma mode programmed on the pipe */
645 struct vlv_wm_state
{
646 struct vlv_pipe_wm wm
[3];
647 struct vlv_sr_wm sr
[3];
648 uint8_t num_active_planes
;
655 struct drm_crtc base
;
658 u8 lut_r
[256], lut_g
[256], lut_b
[256];
660 * Whether the crtc and the connected output pipeline is active. Implies
661 * that crtc->enabled is set, i.e. the current mode configuration has
662 * some outputs connected to this crtc.
665 unsigned long enabled_power_domains
;
667 struct intel_overlay
*overlay
;
668 struct intel_flip_work
*flip_work
;
670 atomic_t unpin_work_count
;
672 /* Display surface base address adjustement for pageflips. Note that on
673 * gen4+ this only adjusts up to a tile, offsets within a tile are
674 * handled in the hw itself (with the TILEOFF register). */
679 uint32_t cursor_addr
;
680 uint32_t cursor_cntl
;
681 uint32_t cursor_size
;
682 uint32_t cursor_base
;
684 struct intel_crtc_state
*config
;
686 /* reset counter value when the last flip was submitted */
687 unsigned int reset_counter
;
689 /* Access to these should be protected by dev_priv->irq_lock. */
690 bool cpu_fifo_underrun_disabled
;
691 bool pch_fifo_underrun_disabled
;
693 /* per-pipe watermark state */
695 /* watermarks currently being used */
697 struct intel_pipe_wm ilk
;
698 struct skl_pipe_wm skl
;
701 /* allow CxSR on this pipe */
708 unsigned start_vbl_count
;
709 ktime_t start_vbl_time
;
710 int min_vbl
, max_vbl
;
714 /* scalers available on this crtc */
717 struct vlv_wm_state wm_state
;
720 struct intel_plane_wm_parameters
{
721 uint32_t horiz_pixels
;
722 uint32_t vert_pixels
;
724 * For packed pixel formats:
725 * bytes_per_pixel - holds bytes per pixel
726 * For planar pixel formats:
727 * bytes_per_pixel - holds bytes per pixel for uv-plane
728 * y_bytes_per_pixel - holds bytes per pixel for y-plane
730 uint8_t bytes_per_pixel
;
731 uint8_t y_bytes_per_pixel
;
735 unsigned int rotation
;
740 struct drm_plane base
;
745 uint32_t frontbuffer_bit
;
747 /* Since we need to change the watermarks before/after
748 * enabling/disabling the planes, we need to store the parameters here
749 * as the other pieces of the struct may not reflect the values we want
750 * for the watermark calculations. Currently only Haswell uses this.
752 struct intel_plane_wm_parameters wm
;
755 * NOTE: Do not place new plane state fields here (e.g., when adding
756 * new plane properties). New runtime state should now be placed in
757 * the intel_plane_state structure and accessed via plane_state.
760 void (*update_plane
)(struct drm_plane
*plane
,
761 const struct intel_crtc_state
*crtc_state
,
762 const struct intel_plane_state
*plane_state
);
763 void (*disable_plane
)(struct drm_plane
*plane
,
764 struct drm_crtc
*crtc
);
765 int (*check_plane
)(struct drm_plane
*plane
,
766 struct intel_crtc_state
*crtc_state
,
767 struct intel_plane_state
*state
);
770 struct intel_watermark_params
{
771 unsigned long fifo_size
;
772 unsigned long max_wm
;
773 unsigned long default_wm
;
774 unsigned long guard_size
;
775 unsigned long cacheline_size
;
778 struct cxsr_latency
{
781 unsigned long fsb_freq
;
782 unsigned long mem_freq
;
783 unsigned long display_sr
;
784 unsigned long display_hpll_disable
;
785 unsigned long cursor_sr
;
786 unsigned long cursor_hpll_disable
;
789 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
790 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
791 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
792 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
793 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
794 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
795 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
796 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
797 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
803 enum drm_dp_dual_mode_type type
;
806 bool limited_color_range
;
807 bool color_range_auto
;
810 enum hdmi_force_audio force_audio
;
811 bool rgb_quant_range_selectable
;
812 enum hdmi_picture_aspect aspect_ratio
;
813 struct intel_connector
*attached_connector
;
814 void (*write_infoframe
)(struct drm_encoder
*encoder
,
815 enum hdmi_infoframe_type type
,
816 const void *frame
, ssize_t len
);
817 void (*set_infoframes
)(struct drm_encoder
*encoder
,
819 const struct drm_display_mode
*adjusted_mode
);
820 bool (*infoframe_enabled
)(struct drm_encoder
*encoder
,
821 const struct intel_crtc_state
*pipe_config
);
824 struct intel_dp_mst_encoder
;
825 #define DP_MAX_DOWNSTREAM_PORTS 0x10
829 * When platform provides two set of M_N registers for dp, we can
830 * program them and switch between them incase of DRRS.
831 * But When only one such register is provided, we have to program the
832 * required divider value on that registers itself based on the DRRS state.
834 * M1_N1 : Program dp_m_n on M1_N1 registers
835 * dp_m2_n2 on M2_N2 registers (If supported)
837 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
838 * M2_N2 registers are not supported
842 /* Sets the m1_n1 and m2_n2 */
848 i915_reg_t output_reg
;
849 i915_reg_t aux_ch_ctl_reg
;
850 i915_reg_t aux_ch_data_reg
[5];
857 enum hdmi_force_audio force_audio
;
858 bool limited_color_range
;
859 bool color_range_auto
;
860 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
861 uint8_t psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
862 uint8_t downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
863 uint8_t edp_dpcd
[EDP_DISPLAY_CTL_CAP_SIZE
];
864 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
865 uint8_t num_sink_rates
;
866 int sink_rates
[DP_MAX_SUPPORTED_RATES
];
867 struct drm_dp_aux aux
;
868 uint8_t train_set
[4];
869 int panel_power_up_delay
;
870 int panel_power_down_delay
;
871 int panel_power_cycle_delay
;
872 int backlight_on_delay
;
873 int backlight_off_delay
;
874 struct delayed_work panel_vdd_work
;
876 unsigned long last_power_on
;
877 unsigned long last_backlight_off
;
878 ktime_t panel_power_off_time
;
880 struct notifier_block edp_notifier
;
883 * Pipe whose power sequencer is currently locked into
884 * this port. Only relevant on VLV/CHV.
888 * Set if the sequencer may be reset due to a power transition,
889 * requiring a reinitialization. Only relevant on BXT.
892 struct edp_power_seq pps_delays
;
894 bool can_mst
; /* this port supports mst */
896 int active_mst_links
;
897 /* connector directly attached - won't be use for modeset in mst world */
898 struct intel_connector
*attached_connector
;
900 /* mst connector list */
901 struct intel_dp_mst_encoder
*mst_encoders
[I915_MAX_PIPES
];
902 struct drm_dp_mst_topology_mgr mst_mgr
;
904 uint32_t (*get_aux_clock_divider
)(struct intel_dp
*dp
, int index
);
906 * This function returns the value we have to program the AUX_CTL
907 * register with to kick off an AUX transaction.
909 uint32_t (*get_aux_send_ctl
)(struct intel_dp
*dp
,
912 uint32_t aux_clock_divider
);
914 /* This is called before a link training is starterd */
915 void (*prepare_link_retrain
)(struct intel_dp
*intel_dp
);
917 /* Displayport compliance testing */
918 unsigned long compliance_test_type
;
919 unsigned long compliance_test_data
;
920 bool compliance_test_active
;
923 struct intel_digital_port
{
924 struct intel_encoder base
;
928 struct intel_hdmi hdmi
;
929 enum irqreturn (*hpd_pulse
)(struct intel_digital_port
*, bool);
930 bool release_cl2_override
;
932 /* for communication with audio component; protected by av_mutex */
933 const struct drm_connector
*audio_connector
;
936 struct intel_dp_mst_encoder
{
937 struct intel_encoder base
;
939 struct intel_digital_port
*primary
;
940 struct intel_connector
*connector
;
943 static inline enum dpio_channel
944 vlv_dport_to_channel(struct intel_digital_port
*dport
)
946 switch (dport
->port
) {
957 static inline enum dpio_phy
958 vlv_dport_to_phy(struct intel_digital_port
*dport
)
960 switch (dport
->port
) {
971 static inline enum dpio_channel
972 vlv_pipe_to_channel(enum pipe pipe
)
985 static inline struct drm_crtc
*
986 intel_get_crtc_for_pipe(struct drm_device
*dev
, int pipe
)
988 struct drm_i915_private
*dev_priv
= to_i915(dev
);
989 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
992 static inline struct drm_crtc
*
993 intel_get_crtc_for_plane(struct drm_device
*dev
, int plane
)
995 struct drm_i915_private
*dev_priv
= to_i915(dev
);
996 return dev_priv
->plane_to_crtc_mapping
[plane
];
999 struct intel_flip_work
{
1000 struct work_struct unpin_work
;
1001 struct work_struct mmio_work
;
1003 struct drm_crtc
*crtc
;
1004 struct drm_framebuffer
*old_fb
;
1005 struct drm_i915_gem_object
*pending_flip_obj
;
1006 struct drm_pending_vblank_event
*event
;
1010 struct drm_i915_gem_request
*flip_queued_req
;
1011 u32 flip_queued_vblank
;
1012 u32 flip_ready_vblank
;
1013 unsigned int rotation
;
1016 struct intel_load_detect_pipe
{
1017 struct drm_atomic_state
*restore_state
;
1020 static inline struct intel_encoder
*
1021 intel_attached_encoder(struct drm_connector
*connector
)
1023 return to_intel_connector(connector
)->encoder
;
1026 static inline struct intel_digital_port
*
1027 enc_to_dig_port(struct drm_encoder
*encoder
)
1029 return container_of(encoder
, struct intel_digital_port
, base
.base
);
1032 static inline struct intel_dp_mst_encoder
*
1033 enc_to_mst(struct drm_encoder
*encoder
)
1035 return container_of(encoder
, struct intel_dp_mst_encoder
, base
.base
);
1038 static inline struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
1040 return &enc_to_dig_port(encoder
)->dp
;
1043 static inline struct intel_digital_port
*
1044 dp_to_dig_port(struct intel_dp
*intel_dp
)
1046 return container_of(intel_dp
, struct intel_digital_port
, dp
);
1049 static inline struct intel_digital_port
*
1050 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
1052 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
1056 * Returns the number of planes for this pipe, ie the number of sprites + 1
1057 * (primary plane). This doesn't count the cursor plane then.
1059 static inline unsigned int intel_num_planes(struct intel_crtc
*crtc
)
1061 return INTEL_INFO(crtc
->base
.dev
)->num_sprites
[crtc
->pipe
] + 1;
1064 /* intel_fifo_underrun.c */
1065 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
1066 enum pipe pipe
, bool enable
);
1067 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
1068 enum transcoder pch_transcoder
,
1070 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
1072 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
1073 enum transcoder pch_transcoder
);
1074 void intel_check_cpu_fifo_underruns(struct drm_i915_private
*dev_priv
);
1075 void intel_check_pch_fifo_underruns(struct drm_i915_private
*dev_priv
);
1078 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1079 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1080 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1081 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1082 void gen6_reset_rps_interrupts(struct drm_i915_private
*dev_priv
);
1083 void gen6_enable_rps_interrupts(struct drm_i915_private
*dev_priv
);
1084 void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv
);
1085 u32
gen6_sanitize_rps_pm_mask(struct drm_i915_private
*dev_priv
, u32 mask
);
1086 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
);
1087 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
);
1088 static inline bool intel_irqs_enabled(struct drm_i915_private
*dev_priv
)
1091 * We only use drm_irq_uninstall() at unload and VT switch, so
1092 * this is the only thing we need to check.
1094 return dev_priv
->pm
.irqs_enabled
;
1097 int intel_get_crtc_scanline(struct intel_crtc
*crtc
);
1098 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
1099 unsigned int pipe_mask
);
1100 void gen8_irq_power_well_pre_disable(struct drm_i915_private
*dev_priv
,
1101 unsigned int pipe_mask
);
1104 void intel_crt_init(struct drm_device
*dev
);
1105 void intel_crt_reset(struct drm_encoder
*encoder
);
1108 void intel_ddi_clk_select(struct intel_encoder
*encoder
,
1109 const struct intel_crtc_state
*pipe_config
);
1110 void intel_prepare_ddi_buffer(struct intel_encoder
*encoder
);
1111 void hsw_fdi_link_train(struct drm_crtc
*crtc
);
1112 void intel_ddi_init(struct drm_device
*dev
, enum port port
);
1113 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
);
1114 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
, enum pipe
*pipe
);
1115 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
);
1116 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1117 enum transcoder cpu_transcoder
);
1118 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
);
1119 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
);
1120 bool intel_ddi_pll_select(struct intel_crtc
*crtc
,
1121 struct intel_crtc_state
*crtc_state
);
1122 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
);
1123 void intel_ddi_prepare_link_retrain(struct intel_dp
*intel_dp
);
1124 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
);
1125 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
);
1126 void intel_ddi_get_config(struct intel_encoder
*encoder
,
1127 struct intel_crtc_state
*pipe_config
);
1128 struct intel_encoder
*
1129 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state
*crtc_state
);
1131 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
);
1132 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
1133 struct intel_crtc_state
*pipe_config
);
1134 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
);
1135 uint32_t ddi_signal_levels(struct intel_dp
*intel_dp
);
1137 /* intel_frontbuffer.c */
1138 void intel_fb_obj_invalidate(struct drm_i915_gem_object
*obj
,
1139 enum fb_op_origin origin
);
1140 void intel_frontbuffer_flip_prepare(struct drm_device
*dev
,
1141 unsigned frontbuffer_bits
);
1142 void intel_frontbuffer_flip_complete(struct drm_device
*dev
,
1143 unsigned frontbuffer_bits
);
1144 void intel_frontbuffer_flip(struct drm_device
*dev
,
1145 unsigned frontbuffer_bits
);
1146 unsigned int intel_fb_align_height(struct drm_device
*dev
,
1147 unsigned int height
,
1148 uint32_t pixel_format
,
1149 uint64_t fb_format_modifier
);
1150 void intel_fb_obj_flush(struct drm_i915_gem_object
*obj
, bool retire
,
1151 enum fb_op_origin origin
);
1152 u32
intel_fb_stride_alignment(const struct drm_i915_private
*dev_priv
,
1153 uint64_t fb_modifier
, uint32_t pixel_format
);
1156 void intel_init_audio_hooks(struct drm_i915_private
*dev_priv
);
1157 void intel_audio_codec_enable(struct intel_encoder
*encoder
);
1158 void intel_audio_codec_disable(struct intel_encoder
*encoder
);
1159 void i915_audio_component_init(struct drm_i915_private
*dev_priv
);
1160 void i915_audio_component_cleanup(struct drm_i915_private
*dev_priv
);
1162 /* intel_display.c */
1163 void skl_set_preferred_cdclk_vco(struct drm_i915_private
*dev_priv
, int vco
);
1164 void intel_update_rawclk(struct drm_i915_private
*dev_priv
);
1165 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
1166 const char *name
, u32 reg
, int ref_freq
);
1167 extern const struct drm_plane_funcs intel_plane_funcs
;
1168 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
);
1169 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
);
1170 bool intel_has_pending_fb_unpin(struct drm_device
*dev
);
1171 void intel_mark_busy(struct drm_i915_private
*dev_priv
);
1172 void intel_mark_idle(struct drm_i915_private
*dev_priv
);
1173 void intel_crtc_restore_mode(struct drm_crtc
*crtc
);
1174 int intel_display_suspend(struct drm_device
*dev
);
1175 void intel_encoder_destroy(struct drm_encoder
*encoder
);
1176 int intel_connector_init(struct intel_connector
*);
1177 struct intel_connector
*intel_connector_alloc(void);
1178 bool intel_connector_get_hw_state(struct intel_connector
*connector
);
1179 void intel_connector_attach_encoder(struct intel_connector
*connector
,
1180 struct intel_encoder
*encoder
);
1181 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
1182 struct drm_crtc
*crtc
);
1183 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
);
1184 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
1185 struct drm_file
*file_priv
);
1186 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1189 intel_crtc_has_type(const struct intel_crtc_state
*crtc_state
,
1190 enum intel_output_type type
)
1192 return crtc_state
->output_types
& (1 << type
);
1195 intel_crtc_has_dp_encoder(const struct intel_crtc_state
*crtc_state
)
1197 return crtc_state
->output_types
&
1198 ((1 << INTEL_OUTPUT_DP
) |
1199 (1 << INTEL_OUTPUT_DP_MST
) |
1200 (1 << INTEL_OUTPUT_EDP
));
1203 intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
1205 drm_wait_one_vblank(dev
, pipe
);
1208 intel_wait_for_vblank_if_active(struct drm_device
*dev
, int pipe
)
1210 const struct intel_crtc
*crtc
=
1211 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
1214 intel_wait_for_vblank(dev
, pipe
);
1217 u32
intel_crtc_get_vblank_counter(struct intel_crtc
*crtc
);
1219 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
);
1220 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1221 struct intel_digital_port
*dport
,
1222 unsigned int expected_mask
);
1223 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
1224 struct drm_display_mode
*mode
,
1225 struct intel_load_detect_pipe
*old
,
1226 struct drm_modeset_acquire_ctx
*ctx
);
1227 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
1228 struct intel_load_detect_pipe
*old
,
1229 struct drm_modeset_acquire_ctx
*ctx
);
1230 int intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
,
1231 unsigned int rotation
);
1232 void intel_unpin_fb_obj(struct drm_framebuffer
*fb
, unsigned int rotation
);
1233 struct drm_framebuffer
*
1234 __intel_framebuffer_create(struct drm_device
*dev
,
1235 struct drm_mode_fb_cmd2
*mode_cmd
,
1236 struct drm_i915_gem_object
*obj
);
1237 void intel_finish_page_flip_cs(struct drm_i915_private
*dev_priv
, int pipe
);
1238 void intel_finish_page_flip_mmio(struct drm_i915_private
*dev_priv
, int pipe
);
1239 void intel_check_page_flip(struct drm_i915_private
*dev_priv
, int pipe
);
1240 int intel_prepare_plane_fb(struct drm_plane
*plane
,
1241 const struct drm_plane_state
*new_state
);
1242 void intel_cleanup_plane_fb(struct drm_plane
*plane
,
1243 const struct drm_plane_state
*old_state
);
1244 int intel_plane_atomic_get_property(struct drm_plane
*plane
,
1245 const struct drm_plane_state
*state
,
1246 struct drm_property
*property
,
1248 int intel_plane_atomic_set_property(struct drm_plane
*plane
,
1249 struct drm_plane_state
*state
,
1250 struct drm_property
*property
,
1252 int intel_plane_atomic_calc_changes(struct drm_crtc_state
*crtc_state
,
1253 struct drm_plane_state
*plane_state
);
1255 unsigned int intel_tile_height(const struct drm_i915_private
*dev_priv
,
1256 uint64_t fb_modifier
, unsigned int cpp
);
1259 intel_rotation_90_or_270(unsigned int rotation
)
1261 return rotation
& (BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
));
1264 void intel_create_rotation_property(struct drm_device
*dev
,
1265 struct intel_plane
*plane
);
1267 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1270 int vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
1271 const struct dpll
*dpll
);
1272 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
);
1273 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
);
1275 /* modesetting asserts */
1276 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1278 void assert_pll(struct drm_i915_private
*dev_priv
,
1279 enum pipe pipe
, bool state
);
1280 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1281 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1282 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
);
1283 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1284 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1285 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1286 enum pipe pipe
, bool state
);
1287 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1288 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1289 void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool state
);
1290 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1291 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1292 u32
intel_compute_tile_offset(int *x
, int *y
,
1293 const struct drm_framebuffer
*fb
, int plane
,
1295 unsigned int rotation
);
1296 void intel_prepare_reset(struct drm_i915_private
*dev_priv
);
1297 void intel_finish_reset(struct drm_i915_private
*dev_priv
);
1298 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
);
1299 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
);
1300 void bxt_init_cdclk(struct drm_i915_private
*dev_priv
);
1301 void bxt_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1302 void bxt_ddi_phy_init(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
1303 void bxt_ddi_phy_uninit(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
1304 bool bxt_ddi_phy_is_enabled(struct drm_i915_private
*dev_priv
,
1306 bool bxt_ddi_phy_verify_state(struct drm_i915_private
*dev_priv
,
1308 void gen9_sanitize_dc_state(struct drm_i915_private
*dev_priv
);
1309 void bxt_enable_dc9(struct drm_i915_private
*dev_priv
);
1310 void bxt_disable_dc9(struct drm_i915_private
*dev_priv
);
1311 void gen9_enable_dc5(struct drm_i915_private
*dev_priv
);
1312 void skl_init_cdclk(struct drm_i915_private
*dev_priv
);
1313 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1314 unsigned int skl_cdclk_get_vco(unsigned int freq
);
1315 void skl_enable_dc6(struct drm_i915_private
*dev_priv
);
1316 void skl_disable_dc6(struct drm_i915_private
*dev_priv
);
1317 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
1318 struct intel_crtc_state
*pipe_config
);
1319 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
);
1320 int intel_dotclock_calculate(int link_freq
, const struct intel_link_m_n
*m_n
);
1321 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
1322 struct dpll
*best_clock
);
1323 int chv_calc_dpll_params(int refclk
, struct dpll
*pll_clock
);
1325 bool intel_crtc_active(struct drm_crtc
*crtc
);
1326 void hsw_enable_ips(struct intel_crtc
*crtc
);
1327 void hsw_disable_ips(struct intel_crtc
*crtc
);
1328 enum intel_display_power_domain
1329 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
);
1330 enum intel_display_power_domain
1331 intel_display_port_aux_power_domain(struct intel_encoder
*intel_encoder
);
1332 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
1333 struct intel_crtc_state
*pipe_config
);
1335 int skl_update_scaler_crtc(struct intel_crtc_state
*crtc_state
);
1336 int skl_max_scale(struct intel_crtc
*crtc
, struct intel_crtc_state
*crtc_state
);
1338 u32
intel_plane_obj_offset(struct intel_plane
*intel_plane
,
1339 struct drm_i915_gem_object
*obj
,
1340 unsigned int plane
);
1342 u32
skl_plane_ctl_format(uint32_t pixel_format
);
1343 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
);
1344 u32
skl_plane_ctl_rotation(unsigned int rotation
);
1347 void intel_csr_ucode_init(struct drm_i915_private
*);
1348 void intel_csr_load_program(struct drm_i915_private
*);
1349 void intel_csr_ucode_fini(struct drm_i915_private
*);
1350 void intel_csr_ucode_suspend(struct drm_i915_private
*);
1351 void intel_csr_ucode_resume(struct drm_i915_private
*);
1354 bool intel_dp_init(struct drm_device
*dev
, i915_reg_t output_reg
, enum port port
);
1355 bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
1356 struct intel_connector
*intel_connector
);
1357 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1358 const struct intel_crtc_state
*pipe_config
);
1359 void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
1360 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
);
1361 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
1362 void intel_dp_encoder_reset(struct drm_encoder
*encoder
);
1363 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
);
1364 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
);
1365 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
);
1366 bool intel_dp_compute_config(struct intel_encoder
*encoder
,
1367 struct intel_crtc_state
*pipe_config
);
1368 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
);
1369 enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
,
1371 void intel_edp_backlight_on(struct intel_dp
*intel_dp
);
1372 void intel_edp_backlight_off(struct intel_dp
*intel_dp
);
1373 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
1374 void intel_edp_panel_on(struct intel_dp
*intel_dp
);
1375 void intel_edp_panel_off(struct intel_dp
*intel_dp
);
1376 void intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
);
1377 void intel_dp_mst_suspend(struct drm_device
*dev
);
1378 void intel_dp_mst_resume(struct drm_device
*dev
);
1379 int intel_dp_max_link_rate(struct intel_dp
*intel_dp
);
1380 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
);
1381 void intel_dp_hot_plug(struct intel_encoder
*intel_encoder
);
1382 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
);
1383 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
);
1384 void intel_plane_destroy(struct drm_plane
*plane
);
1385 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
);
1386 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
);
1387 void intel_edp_drrs_invalidate(struct drm_device
*dev
,
1388 unsigned frontbuffer_bits
);
1389 void intel_edp_drrs_flush(struct drm_device
*dev
, unsigned frontbuffer_bits
);
1390 bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
1391 struct intel_digital_port
*port
);
1394 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
1395 uint8_t dp_train_pat
);
1397 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
);
1398 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
);
1400 intel_dp_voltage_max(struct intel_dp
*intel_dp
);
1402 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
);
1403 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1404 uint8_t *link_bw
, uint8_t *rate_select
);
1405 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
);
1407 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
]);
1409 static inline unsigned int intel_dp_unused_lane_mask(int lane_count
)
1411 return ~((1 << lane_count
) - 1) & 0xf;
1414 /* intel_dp_aux_backlight.c */
1415 int intel_dp_aux_init_backlight_funcs(struct intel_connector
*intel_connector
);
1417 /* intel_dp_mst.c */
1418 int intel_dp_mst_encoder_init(struct intel_digital_port
*intel_dig_port
, int conn_id
);
1419 void intel_dp_mst_encoder_cleanup(struct intel_digital_port
*intel_dig_port
);
1421 void intel_dsi_init(struct drm_device
*dev
);
1423 /* intel_dsi_dcs_backlight.c */
1424 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector
*intel_connector
);
1427 void intel_dvo_init(struct drm_device
*dev
);
1428 /* intel_hotplug.c */
1429 void intel_hpd_poll_init(struct drm_i915_private
*dev_priv
);
1432 /* legacy fbdev emulation in intel_fbdev.c */
1433 #ifdef CONFIG_DRM_FBDEV_EMULATION
1434 extern int intel_fbdev_init(struct drm_device
*dev
);
1435 extern void intel_fbdev_initial_config_async(struct drm_device
*dev
);
1436 extern void intel_fbdev_fini(struct drm_device
*dev
);
1437 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
);
1438 extern void intel_fbdev_output_poll_changed(struct drm_device
*dev
);
1439 extern void intel_fbdev_restore_mode(struct drm_device
*dev
);
1441 static inline int intel_fbdev_init(struct drm_device
*dev
)
1446 static inline void intel_fbdev_initial_config_async(struct drm_device
*dev
)
1450 static inline void intel_fbdev_fini(struct drm_device
*dev
)
1454 static inline void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
)
1458 static inline void intel_fbdev_restore_mode(struct drm_device
*dev
)
1464 void intel_fbc_choose_crtc(struct drm_i915_private
*dev_priv
,
1465 struct drm_atomic_state
*state
);
1466 bool intel_fbc_is_active(struct drm_i915_private
*dev_priv
);
1467 void intel_fbc_pre_update(struct intel_crtc
*crtc
,
1468 struct intel_crtc_state
*crtc_state
,
1469 struct intel_plane_state
*plane_state
);
1470 void intel_fbc_post_update(struct intel_crtc
*crtc
);
1471 void intel_fbc_init(struct drm_i915_private
*dev_priv
);
1472 void intel_fbc_init_pipe_state(struct drm_i915_private
*dev_priv
);
1473 void intel_fbc_enable(struct intel_crtc
*crtc
,
1474 struct intel_crtc_state
*crtc_state
,
1475 struct intel_plane_state
*plane_state
);
1476 void intel_fbc_disable(struct intel_crtc
*crtc
);
1477 void intel_fbc_global_disable(struct drm_i915_private
*dev_priv
);
1478 void intel_fbc_invalidate(struct drm_i915_private
*dev_priv
,
1479 unsigned int frontbuffer_bits
,
1480 enum fb_op_origin origin
);
1481 void intel_fbc_flush(struct drm_i915_private
*dev_priv
,
1482 unsigned int frontbuffer_bits
, enum fb_op_origin origin
);
1483 void intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
);
1486 void intel_hdmi_init(struct drm_device
*dev
, i915_reg_t hdmi_reg
, enum port port
);
1487 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
1488 struct intel_connector
*intel_connector
);
1489 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
);
1490 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
1491 struct intel_crtc_state
*pipe_config
);
1492 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi
*hdmi
, bool enable
);
1496 void intel_lvds_init(struct drm_device
*dev
);
1497 struct intel_encoder
*intel_get_lvds_encoder(struct drm_device
*dev
);
1498 bool intel_is_dual_link_lvds(struct drm_device
*dev
);
1502 int intel_connector_update_modes(struct drm_connector
*connector
,
1504 int intel_ddc_get_modes(struct drm_connector
*c
, struct i2c_adapter
*adapter
);
1505 void intel_attach_force_audio_property(struct drm_connector
*connector
);
1506 void intel_attach_broadcast_rgb_property(struct drm_connector
*connector
);
1507 void intel_attach_aspect_ratio_property(struct drm_connector
*connector
);
1510 /* intel_overlay.c */
1511 void intel_setup_overlay(struct drm_i915_private
*dev_priv
);
1512 void intel_cleanup_overlay(struct drm_i915_private
*dev_priv
);
1513 int intel_overlay_switch_off(struct intel_overlay
*overlay
);
1514 int intel_overlay_put_image_ioctl(struct drm_device
*dev
, void *data
,
1515 struct drm_file
*file_priv
);
1516 int intel_overlay_attrs_ioctl(struct drm_device
*dev
, void *data
,
1517 struct drm_file
*file_priv
);
1518 void intel_overlay_reset(struct drm_i915_private
*dev_priv
);
1522 int intel_panel_init(struct intel_panel
*panel
,
1523 struct drm_display_mode
*fixed_mode
,
1524 struct drm_display_mode
*downclock_mode
);
1525 void intel_panel_fini(struct intel_panel
*panel
);
1526 void intel_fixed_panel_mode(const struct drm_display_mode
*fixed_mode
,
1527 struct drm_display_mode
*adjusted_mode
);
1528 void intel_pch_panel_fitting(struct intel_crtc
*crtc
,
1529 struct intel_crtc_state
*pipe_config
,
1531 void intel_gmch_panel_fitting(struct intel_crtc
*crtc
,
1532 struct intel_crtc_state
*pipe_config
,
1534 void intel_panel_set_backlight_acpi(struct intel_connector
*connector
,
1535 u32 level
, u32 max
);
1536 int intel_panel_setup_backlight(struct drm_connector
*connector
,
1538 void intel_panel_enable_backlight(struct intel_connector
*connector
);
1539 void intel_panel_disable_backlight(struct intel_connector
*connector
);
1540 void intel_panel_destroy_backlight(struct drm_connector
*connector
);
1541 enum drm_connector_status
intel_panel_detect(struct drm_device
*dev
);
1542 extern struct drm_display_mode
*intel_find_panel_downclock(
1543 struct drm_device
*dev
,
1544 struct drm_display_mode
*fixed_mode
,
1545 struct drm_connector
*connector
);
1547 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1548 int intel_backlight_device_register(struct intel_connector
*connector
);
1549 void intel_backlight_device_unregister(struct intel_connector
*connector
);
1550 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1551 static int intel_backlight_device_register(struct intel_connector
*connector
)
1555 static inline void intel_backlight_device_unregister(struct intel_connector
*connector
)
1558 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1562 void intel_psr_enable(struct intel_dp
*intel_dp
);
1563 void intel_psr_disable(struct intel_dp
*intel_dp
);
1564 void intel_psr_invalidate(struct drm_device
*dev
,
1565 unsigned frontbuffer_bits
);
1566 void intel_psr_flush(struct drm_device
*dev
,
1567 unsigned frontbuffer_bits
,
1568 enum fb_op_origin origin
);
1569 void intel_psr_init(struct drm_device
*dev
);
1570 void intel_psr_single_frame_update(struct drm_device
*dev
,
1571 unsigned frontbuffer_bits
);
1573 /* intel_runtime_pm.c */
1574 int intel_power_domains_init(struct drm_i915_private
*);
1575 void intel_power_domains_fini(struct drm_i915_private
*);
1576 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
, bool resume
);
1577 void intel_power_domains_suspend(struct drm_i915_private
*dev_priv
);
1578 void bxt_display_core_init(struct drm_i915_private
*dev_priv
, bool resume
);
1579 void bxt_display_core_uninit(struct drm_i915_private
*dev_priv
);
1580 void intel_runtime_pm_enable(struct drm_i915_private
*dev_priv
);
1582 intel_display_power_domain_str(enum intel_display_power_domain domain
);
1584 bool intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1585 enum intel_display_power_domain domain
);
1586 bool __intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1587 enum intel_display_power_domain domain
);
1588 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
1589 enum intel_display_power_domain domain
);
1590 bool intel_display_power_get_if_enabled(struct drm_i915_private
*dev_priv
,
1591 enum intel_display_power_domain domain
);
1592 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
1593 enum intel_display_power_domain domain
);
1596 assert_rpm_device_not_suspended(struct drm_i915_private
*dev_priv
)
1598 WARN_ONCE(dev_priv
->pm
.suspended
,
1599 "Device suspended during HW access\n");
1603 assert_rpm_wakelock_held(struct drm_i915_private
*dev_priv
)
1605 assert_rpm_device_not_suspended(dev_priv
);
1606 /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1607 * too much noise. */
1608 if (!atomic_read(&dev_priv
->pm
.wakeref_count
))
1609 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1613 assert_rpm_atomic_begin(struct drm_i915_private
*dev_priv
)
1615 int seq
= atomic_read(&dev_priv
->pm
.atomic_seq
);
1617 assert_rpm_wakelock_held(dev_priv
);
1623 assert_rpm_atomic_end(struct drm_i915_private
*dev_priv
, int begin_seq
)
1625 WARN_ONCE(atomic_read(&dev_priv
->pm
.atomic_seq
) != begin_seq
,
1626 "HW access outside of RPM atomic section\n");
1630 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1631 * @dev_priv: i915 device instance
1633 * This function disable asserts that check if we hold an RPM wakelock
1634 * reference, while keeping the device-not-suspended checks still enabled.
1635 * It's meant to be used only in special circumstances where our rule about
1636 * the wakelock refcount wrt. the device power state doesn't hold. According
1637 * to this rule at any point where we access the HW or want to keep the HW in
1638 * an active state we must hold an RPM wakelock reference acquired via one of
1639 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1640 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1641 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1642 * users should avoid using this function.
1644 * Any calls to this function must have a symmetric call to
1645 * enable_rpm_wakeref_asserts().
1648 disable_rpm_wakeref_asserts(struct drm_i915_private
*dev_priv
)
1650 atomic_inc(&dev_priv
->pm
.wakeref_count
);
1654 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1655 * @dev_priv: i915 device instance
1657 * This function re-enables the RPM assert checks after disabling them with
1658 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1659 * circumstances otherwise its use should be avoided.
1661 * Any calls to this function must have a symmetric call to
1662 * disable_rpm_wakeref_asserts().
1665 enable_rpm_wakeref_asserts(struct drm_i915_private
*dev_priv
)
1667 atomic_dec(&dev_priv
->pm
.wakeref_count
);
1670 /* TODO: convert users of these to rely instead on proper RPM refcounting */
1671 #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1672 disable_rpm_wakeref_asserts(dev_priv)
1674 #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1675 enable_rpm_wakeref_asserts(dev_priv)
1677 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
);
1678 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private
*dev_priv
);
1679 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
);
1680 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
);
1682 void intel_display_set_init_power(struct drm_i915_private
*dev
, bool enable
);
1684 void chv_phy_powergate_lanes(struct intel_encoder
*encoder
,
1685 bool override
, unsigned int mask
);
1686 bool chv_phy_powergate_ch(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
,
1687 enum dpio_channel ch
, bool override
);
1691 void intel_init_clock_gating(struct drm_device
*dev
);
1692 void intel_suspend_hw(struct drm_device
*dev
);
1693 int ilk_wm_max_level(const struct drm_device
*dev
);
1694 void intel_update_watermarks(struct drm_crtc
*crtc
);
1695 void intel_init_pm(struct drm_device
*dev
);
1696 void intel_init_clock_gating_hooks(struct drm_i915_private
*dev_priv
);
1697 void intel_pm_setup(struct drm_device
*dev
);
1698 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
1699 void intel_gpu_ips_teardown(void);
1700 void intel_init_gt_powersave(struct drm_i915_private
*dev_priv
);
1701 void intel_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
);
1702 void intel_enable_gt_powersave(struct drm_i915_private
*dev_priv
);
1703 void intel_disable_gt_powersave(struct drm_i915_private
*dev_priv
);
1704 void intel_suspend_gt_powersave(struct drm_i915_private
*dev_priv
);
1705 void intel_reset_gt_powersave(struct drm_i915_private
*dev_priv
);
1706 void gen6_update_ring_freq(struct drm_i915_private
*dev_priv
);
1707 void gen6_rps_busy(struct drm_i915_private
*dev_priv
);
1708 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
);
1709 void gen6_rps_idle(struct drm_i915_private
*dev_priv
);
1710 void gen6_rps_boost(struct drm_i915_private
*dev_priv
,
1711 struct intel_rps_client
*rps
,
1712 unsigned long submitted
);
1713 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request
*req
);
1714 void vlv_wm_get_hw_state(struct drm_device
*dev
);
1715 void ilk_wm_get_hw_state(struct drm_device
*dev
);
1716 void skl_wm_get_hw_state(struct drm_device
*dev
);
1717 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
1718 struct skl_ddb_allocation
*ddb
/* out */);
1719 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
*pipe_config
);
1720 bool ilk_disable_lp_wm(struct drm_device
*dev
);
1721 int sanitize_rc6_option(struct drm_i915_private
*dev_priv
, int enable_rc6
);
1722 static inline int intel_enable_rc6(void)
1724 return i915
.enable_rc6
;
1728 bool intel_sdvo_init(struct drm_device
*dev
,
1729 i915_reg_t reg
, enum port port
);
1732 /* intel_sprite.c */
1733 int intel_usecs_to_scanlines(const struct drm_display_mode
*adjusted_mode
,
1735 int intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
);
1736 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
1737 struct drm_file
*file_priv
);
1738 void intel_pipe_update_start(struct intel_crtc
*crtc
);
1739 void intel_pipe_update_end(struct intel_crtc
*crtc
, struct intel_flip_work
*work
);
1742 void intel_tv_init(struct drm_device
*dev
);
1744 /* intel_atomic.c */
1745 int intel_connector_atomic_get_property(struct drm_connector
*connector
,
1746 const struct drm_connector_state
*state
,
1747 struct drm_property
*property
,
1749 struct drm_crtc_state
*intel_crtc_duplicate_state(struct drm_crtc
*crtc
);
1750 void intel_crtc_destroy_state(struct drm_crtc
*crtc
,
1751 struct drm_crtc_state
*state
);
1752 struct drm_atomic_state
*intel_atomic_state_alloc(struct drm_device
*dev
);
1753 void intel_atomic_state_clear(struct drm_atomic_state
*);
1754 struct intel_shared_dpll_config
*
1755 intel_atomic_get_shared_dpll_state(struct drm_atomic_state
*s
);
1757 static inline struct intel_crtc_state
*
1758 intel_atomic_get_crtc_state(struct drm_atomic_state
*state
,
1759 struct intel_crtc
*crtc
)
1761 struct drm_crtc_state
*crtc_state
;
1762 crtc_state
= drm_atomic_get_crtc_state(state
, &crtc
->base
);
1763 if (IS_ERR(crtc_state
))
1764 return ERR_CAST(crtc_state
);
1766 return to_intel_crtc_state(crtc_state
);
1769 static inline struct intel_plane_state
*
1770 intel_atomic_get_existing_plane_state(struct drm_atomic_state
*state
,
1771 struct intel_plane
*plane
)
1773 struct drm_plane_state
*plane_state
;
1775 plane_state
= drm_atomic_get_existing_plane_state(state
, &plane
->base
);
1777 return to_intel_plane_state(plane_state
);
1780 int intel_atomic_setup_scalers(struct drm_device
*dev
,
1781 struct intel_crtc
*intel_crtc
,
1782 struct intel_crtc_state
*crtc_state
);
1784 /* intel_atomic_plane.c */
1785 struct intel_plane_state
*intel_create_plane_state(struct drm_plane
*plane
);
1786 struct drm_plane_state
*intel_plane_duplicate_state(struct drm_plane
*plane
);
1787 void intel_plane_destroy_state(struct drm_plane
*plane
,
1788 struct drm_plane_state
*state
);
1789 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs
;
1792 void intel_color_init(struct drm_crtc
*crtc
);
1793 int intel_color_check(struct drm_crtc
*crtc
, struct drm_crtc_state
*state
);
1794 void intel_color_set_csc(struct drm_crtc_state
*crtc_state
);
1795 void intel_color_load_luts(struct drm_crtc_state
*crtc_state
);
1797 #endif /* __INTEL_DRV_H__ */