2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
38 #include <drm/drm_atomic.h>
41 * _wait_for - magic (register) wait macro
43 * Does the right thing for modeset paths when run under kdgb or similar atomic
44 * contexts. Note that it's important that we check the condition again after
45 * having timed out, since the timeout could be due to preemption or similar and
46 * we've never had a chance to check the condition before the timeout.
48 #define _wait_for(COND, MS, W) ({ \
49 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
52 if (time_after(jiffies, timeout__)) { \
57 if ((W) && drm_can_sleep()) { \
58 usleep_range((W)*1000, (W)*2000); \
66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
69 DIV_ROUND_UP((US), 1000), 0)
71 #define KHz(x) (1000 * (x))
72 #define MHz(x) KHz(1000 * (x))
75 * Display related stuff
78 /* store information about an Ixxx DVO */
79 /* The i830->i865 use multiple DVOs with multiple i2cs */
80 /* the i915, i945 have a single sDVO i2c bus - which is different */
82 /* maximum connectors per crtcs in the mode set */
84 /* Maximum cursor sizes */
85 #define GEN2_CURSOR_WIDTH 64
86 #define GEN2_CURSOR_HEIGHT 64
87 #define MAX_CURSOR_WIDTH 256
88 #define MAX_CURSOR_HEIGHT 256
90 #define INTEL_I2C_BUS_DVO 1
91 #define INTEL_I2C_BUS_SDVO 2
93 /* these are outputs from the chip - integrated only
94 external chips are via DVO or SDVO output */
95 enum intel_output_type
{
96 INTEL_OUTPUT_UNUSED
= 0,
97 INTEL_OUTPUT_ANALOG
= 1,
99 INTEL_OUTPUT_SDVO
= 3,
100 INTEL_OUTPUT_LVDS
= 4,
101 INTEL_OUTPUT_TVOUT
= 5,
102 INTEL_OUTPUT_HDMI
= 6,
103 INTEL_OUTPUT_DISPLAYPORT
= 7,
104 INTEL_OUTPUT_EDP
= 8,
105 INTEL_OUTPUT_DSI
= 9,
106 INTEL_OUTPUT_UNKNOWN
= 10,
107 INTEL_OUTPUT_DP_MST
= 11,
110 #define INTEL_DVO_CHIP_NONE 0
111 #define INTEL_DVO_CHIP_LVDS 1
112 #define INTEL_DVO_CHIP_TMDS 2
113 #define INTEL_DVO_CHIP_TVOUT 4
115 #define INTEL_DSI_VIDEO_MODE 0
116 #define INTEL_DSI_COMMAND_MODE 1
118 struct intel_framebuffer
{
119 struct drm_framebuffer base
;
120 struct drm_i915_gem_object
*obj
;
124 struct drm_fb_helper helper
;
125 struct intel_framebuffer
*fb
;
126 struct list_head fbdev_list
;
127 struct drm_display_mode
*our_mode
;
131 struct intel_encoder
{
132 struct drm_encoder base
;
134 enum intel_output_type type
;
135 unsigned int cloneable
;
136 bool connectors_active
;
137 void (*hot_plug
)(struct intel_encoder
*);
138 bool (*compute_config
)(struct intel_encoder
*,
139 struct intel_crtc_state
*);
140 void (*pre_pll_enable
)(struct intel_encoder
*);
141 void (*pre_enable
)(struct intel_encoder
*);
142 void (*enable
)(struct intel_encoder
*);
143 void (*mode_set
)(struct intel_encoder
*intel_encoder
);
144 void (*disable
)(struct intel_encoder
*);
145 void (*post_disable
)(struct intel_encoder
*);
146 /* Read out the current hw state of this connector, returning true if
147 * the encoder is active. If the encoder is enabled it also set the pipe
148 * it is connected to in the pipe parameter. */
149 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
150 /* Reconstructs the equivalent mode flags for the current hardware
151 * state. This must be called _after_ display->get_pipe_config has
152 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
153 * be set correctly before calling this function. */
154 void (*get_config
)(struct intel_encoder
*,
155 struct intel_crtc_state
*pipe_config
);
157 * Called during system suspend after all pending requests for the
158 * encoder are flushed (for example for DP AUX transactions) and
159 * device interrupts are disabled.
161 void (*suspend
)(struct intel_encoder
*);
163 enum hpd_pin hpd_pin
;
167 struct drm_display_mode
*fixed_mode
;
168 struct drm_display_mode
*downclock_mode
;
178 bool combination_mode
; /* gen 2/4 only */
182 struct pwm_device
*pwm
;
184 struct backlight_device
*device
;
187 void (*backlight_power
)(struct intel_connector
*, bool enable
);
190 struct intel_connector
{
191 struct drm_connector base
;
193 * The fixed encoder this connector is connected to.
195 struct intel_encoder
*encoder
;
197 /* Reads out the current hw, returning true if the connector is enabled
198 * and active (i.e. dpms ON state). */
199 bool (*get_hw_state
)(struct intel_connector
*);
202 * Removes all interfaces through which the connector is accessible
203 * - like sysfs, debugfs entries -, so that no new operations can be
204 * started on the connector. Also makes sure all currently pending
205 * operations finish before returing.
207 void (*unregister
)(struct intel_connector
*);
209 /* Panel info for eDP and LVDS */
210 struct intel_panel panel
;
212 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
214 struct edid
*detect_edid
;
216 /* since POLL and HPD connectors may use the same HPD line keep the native
217 state of connector->polled in case hotplug storm detection changes it */
220 void *port
; /* store this opaque as its illegal to dereference it */
222 struct intel_dp
*mst_port
;
225 typedef struct dpll
{
237 struct intel_atomic_state
{
238 struct drm_atomic_state base
;
242 struct intel_shared_dpll_config shared_dpll
[I915_NUM_PLLS
];
245 struct intel_plane_state
{
246 struct drm_plane_state base
;
249 struct drm_rect clip
;
254 * = -1 : not using a scaler
255 * >= 0 : using a scalers
257 * plane requiring a scaler:
258 * - During check_plane, its bit is set in
259 * crtc_state->scaler_state.scaler_users by calling helper function
260 * update_scaler_plane.
261 * - scaler_id indicates the scaler it got assigned.
263 * plane doesn't require a scaler:
264 * - this can happen when scaling is no more required or plane simply
266 * - During check_plane, corresponding bit is reset in
267 * crtc_state->scaler_state.scaler_users by calling helper function
268 * update_scaler_plane.
272 struct drm_intel_sprite_colorkey ckey
;
275 struct intel_initial_plane_config
{
276 struct intel_framebuffer
*fb
;
282 #define SKL_MIN_SRC_W 8
283 #define SKL_MAX_SRC_W 4096
284 #define SKL_MIN_SRC_H 8
285 #define SKL_MAX_SRC_H 4096
286 #define SKL_MIN_DST_W 8
287 #define SKL_MAX_DST_W 4096
288 #define SKL_MIN_DST_H 8
289 #define SKL_MAX_DST_H 4096
291 struct intel_scaler
{
296 struct intel_crtc_scaler_state
{
297 #define SKL_NUM_SCALERS 2
298 struct intel_scaler scalers
[SKL_NUM_SCALERS
];
301 * scaler_users: keeps track of users requesting scalers on this crtc.
303 * If a bit is set, a user is using a scaler.
304 * Here user can be a plane or crtc as defined below:
305 * bits 0-30 - plane (bit position is index from drm_plane_index)
308 * Instead of creating a new index to cover planes and crtc, using
309 * existing drm_plane_index for planes which is well less than 31
310 * planes and bit 31 for crtc. This should be fine to cover all
313 * intel_atomic_setup_scalers will setup available scalers to users
314 * requesting scalers. It will gracefully fail if request exceeds
317 #define SKL_CRTC_INDEX 31
318 unsigned scaler_users
;
320 /* scaler used by crtc for panel fitting purpose */
324 /* drm_mode->private_flags */
325 #define I915_MODE_FLAG_INHERITED 1
327 struct intel_crtc_state
{
328 struct drm_crtc_state base
;
331 * quirks - bitfield with hw state readout quirks
333 * For various reasons the hw state readout code might not be able to
334 * completely faithfully read out the current state. These cases are
335 * tracked with quirk flags so that fastboot and state checker can act
338 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
339 unsigned long quirks
;
341 /* Pipe source size (ie. panel fitter input size)
342 * All planes will be positioned inside this space,
343 * and get clipped at the edges. */
344 int pipe_src_w
, pipe_src_h
;
346 /* Whether to set up the PCH/FDI. Note that we never allow sharing
347 * between pch encoders and cpu encoders. */
348 bool has_pch_encoder
;
350 /* Are we sending infoframes on the attached port */
353 /* CPU Transcoder for the pipe. Currently this can only differ from the
354 * pipe on Haswell (where we have a special eDP transcoder). */
355 enum transcoder cpu_transcoder
;
358 * Use reduced/limited/broadcast rbg range, compressing from the full
359 * range fed into the crtcs.
361 bool limited_color_range
;
363 /* DP has a bunch of special case unfortunately, so mark the pipe
367 /* Whether we should send NULL infoframes. Required for audio. */
370 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
371 * has_dp_encoder is set. */
375 * Enable dithering, used when the selected pipe bpp doesn't match the
380 /* Controls for the clock computation, to override various stages. */
383 /* SDVO TV has a bunch of special case. To make multifunction encoders
384 * work correctly, we need to track this at runtime.*/
388 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
389 * required. This is set in the 2nd loop of calling encoder's
390 * ->compute_config if the first pick doesn't work out.
394 /* Settings for the intel dpll used on pretty much everything but
398 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
399 enum intel_dpll_id shared_dpll
;
402 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
403 * - enum skl_dpll on SKL
405 uint32_t ddi_pll_sel
;
407 /* Actual register state of the dpll, for shared dpll cross-checking. */
408 struct intel_dpll_hw_state dpll_hw_state
;
411 struct intel_link_m_n dp_m_n
;
413 /* m2_n2 for eDP downclock */
414 struct intel_link_m_n dp_m2_n2
;
418 * Frequence the dpll for the port should run at. Differs from the
419 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
420 * already multiplied by pixel_multiplier.
424 /* Used by SDVO (and if we ever fix it, HDMI). */
425 unsigned pixel_multiplier
;
427 /* Panel fitter controls for gen2-gen4 + VLV */
431 u32 lvds_border_bits
;
434 /* Panel fitter placement and size for Ironlake+ */
442 /* FDI configuration, only valid if has_pch_encoder is set. */
444 struct intel_link_m_n fdi_m_n
;
450 bool dp_encoder_is_mst
;
453 struct intel_crtc_scaler_state scaler_state
;
455 /* w/a for waiting 2 vblanks during crtc enable */
456 enum pipe hsw_workaround_pipe
;
459 struct vlv_wm_state
{
460 struct vlv_pipe_wm wm
[3];
461 struct vlv_sr_wm sr
[3];
462 uint8_t num_active_planes
;
468 struct intel_pipe_wm
{
469 struct intel_wm_level wm
[5];
473 bool sprites_enabled
;
477 struct intel_mmio_flip
{
478 struct work_struct work
;
479 struct drm_i915_private
*i915
;
480 struct drm_i915_gem_request
*req
;
481 struct intel_crtc
*crtc
;
485 struct skl_wm_level wm
[8];
486 struct skl_wm_level trans_wm
;
491 * Tracking of operations that need to be performed at the beginning/end of an
492 * atomic commit, outside the atomic section where interrupts are disabled.
493 * These are generally operations that grab mutexes or might otherwise sleep
494 * and thus can't be run with interrupts disabled.
496 struct intel_crtc_atomic_commit
{
497 /* Sleepable operations to perform before commit */
502 bool pre_disable_primary
;
503 bool update_wm_pre
, update_wm_post
;
504 unsigned disabled_planes
;
506 /* Sleepable operations to perform after commit */
510 bool post_enable_primary
;
511 unsigned update_sprite_watermarks
;
515 struct drm_crtc base
;
518 u8 lut_r
[256], lut_g
[256], lut_b
[256];
520 * Whether the crtc and the connected output pipeline is active. Implies
521 * that crtc->enabled is set, i.e. the current mode configuration has
522 * some outputs connected to this crtc.
525 unsigned long enabled_power_domains
;
527 struct intel_overlay
*overlay
;
528 struct intel_unpin_work
*unpin_work
;
530 atomic_t unpin_work_count
;
532 /* Display surface base address adjustement for pageflips. Note that on
533 * gen4+ this only adjusts up to a tile, offsets within a tile are
534 * handled in the hw itself (with the TILEOFF register). */
535 unsigned long dspaddr_offset
;
537 struct drm_i915_gem_object
*cursor_bo
;
538 uint32_t cursor_addr
;
539 uint32_t cursor_cntl
;
540 uint32_t cursor_size
;
541 uint32_t cursor_base
;
543 struct intel_crtc_state
*config
;
545 /* reset counter value when the last flip was submitted */
546 unsigned int reset_counter
;
548 /* Access to these should be protected by dev_priv->irq_lock. */
549 bool cpu_fifo_underrun_disabled
;
550 bool pch_fifo_underrun_disabled
;
552 /* per-pipe watermark state */
554 /* watermarks currently being used */
555 struct intel_pipe_wm active
;
556 /* SKL wm values currently in use */
557 struct skl_pipe_wm skl_active
;
558 /* allow CxSR on this pipe */
564 unsigned start_vbl_count
;
565 struct intel_crtc_atomic_commit atomic
;
567 /* scalers available on this crtc */
570 struct vlv_wm_state wm_state
;
573 struct intel_plane_wm_parameters
{
574 uint32_t horiz_pixels
;
575 uint32_t vert_pixels
;
577 * For packed pixel formats:
578 * bytes_per_pixel - holds bytes per pixel
579 * For planar pixel formats:
580 * bytes_per_pixel - holds bytes per pixel for uv-plane
581 * y_bytes_per_pixel - holds bytes per pixel for y-plane
583 uint8_t bytes_per_pixel
;
584 uint8_t y_bytes_per_pixel
;
588 unsigned int rotation
;
593 struct drm_plane base
;
598 uint32_t frontbuffer_bit
;
600 /* Since we need to change the watermarks before/after
601 * enabling/disabling the planes, we need to store the parameters here
602 * as the other pieces of the struct may not reflect the values we want
603 * for the watermark calculations. Currently only Haswell uses this.
605 struct intel_plane_wm_parameters wm
;
608 * NOTE: Do not place new plane state fields here (e.g., when adding
609 * new plane properties). New runtime state should now be placed in
610 * the intel_plane_state structure and accessed via drm_plane->state.
613 void (*update_plane
)(struct drm_plane
*plane
,
614 struct drm_crtc
*crtc
,
615 struct drm_framebuffer
*fb
,
616 int crtc_x
, int crtc_y
,
617 unsigned int crtc_w
, unsigned int crtc_h
,
618 uint32_t x
, uint32_t y
,
619 uint32_t src_w
, uint32_t src_h
);
620 void (*disable_plane
)(struct drm_plane
*plane
,
621 struct drm_crtc
*crtc
);
622 int (*check_plane
)(struct drm_plane
*plane
,
623 struct intel_crtc_state
*crtc_state
,
624 struct intel_plane_state
*state
);
625 void (*commit_plane
)(struct drm_plane
*plane
,
626 struct intel_plane_state
*state
);
629 struct intel_watermark_params
{
630 unsigned long fifo_size
;
631 unsigned long max_wm
;
632 unsigned long default_wm
;
633 unsigned long guard_size
;
634 unsigned long cacheline_size
;
637 struct cxsr_latency
{
640 unsigned long fsb_freq
;
641 unsigned long mem_freq
;
642 unsigned long display_sr
;
643 unsigned long display_hpll_disable
;
644 unsigned long cursor_sr
;
645 unsigned long cursor_hpll_disable
;
648 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
649 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
650 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
651 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
652 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
653 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
654 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
655 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
656 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
661 uint32_t color_range
;
662 bool color_range_auto
;
665 enum hdmi_force_audio force_audio
;
666 bool rgb_quant_range_selectable
;
667 enum hdmi_picture_aspect aspect_ratio
;
668 void (*write_infoframe
)(struct drm_encoder
*encoder
,
669 enum hdmi_infoframe_type type
,
670 const void *frame
, ssize_t len
);
671 void (*set_infoframes
)(struct drm_encoder
*encoder
,
673 struct drm_display_mode
*adjusted_mode
);
674 bool (*infoframe_enabled
)(struct drm_encoder
*encoder
);
677 struct intel_dp_mst_encoder
;
678 #define DP_MAX_DOWNSTREAM_PORTS 0x10
682 * When platform provides two set of M_N registers for dp, we can
683 * program them and switch between them incase of DRRS.
684 * But When only one such register is provided, we have to program the
685 * required divider value on that registers itself based on the DRRS state.
687 * M1_N1 : Program dp_m_n on M1_N1 registers
688 * dp_m2_n2 on M2_N2 registers (If supported)
690 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
691 * M2_N2 registers are not supported
695 /* Sets the m1_n1 and m2_n2 */
702 uint32_t aux_ch_ctl_reg
;
705 enum hdmi_force_audio force_audio
;
706 uint32_t color_range
;
707 bool color_range_auto
;
711 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
712 uint8_t psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
713 uint8_t downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
714 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
715 uint8_t num_sink_rates
;
716 int sink_rates
[DP_MAX_SUPPORTED_RATES
];
717 struct drm_dp_aux aux
;
718 uint8_t train_set
[4];
719 int panel_power_up_delay
;
720 int panel_power_down_delay
;
721 int panel_power_cycle_delay
;
722 int backlight_on_delay
;
723 int backlight_off_delay
;
724 struct delayed_work panel_vdd_work
;
726 unsigned long last_power_cycle
;
727 unsigned long last_power_on
;
728 unsigned long last_backlight_off
;
730 struct notifier_block edp_notifier
;
733 * Pipe whose power sequencer is currently locked into
734 * this port. Only relevant on VLV/CHV.
737 struct edp_power_seq pps_delays
;
740 bool can_mst
; /* this port supports mst */
742 int active_mst_links
;
743 /* connector directly attached - won't be use for modeset in mst world */
744 struct intel_connector
*attached_connector
;
746 /* mst connector list */
747 struct intel_dp_mst_encoder
*mst_encoders
[I915_MAX_PIPES
];
748 struct drm_dp_mst_topology_mgr mst_mgr
;
750 uint32_t (*get_aux_clock_divider
)(struct intel_dp
*dp
, int index
);
752 * This function returns the value we have to program the AUX_CTL
753 * register with to kick off an AUX transaction.
755 uint32_t (*get_aux_send_ctl
)(struct intel_dp
*dp
,
758 uint32_t aux_clock_divider
);
759 bool train_set_valid
;
761 /* Displayport compliance testing */
762 unsigned long compliance_test_type
;
763 unsigned long compliance_test_data
;
764 bool compliance_test_active
;
767 struct intel_digital_port
{
768 struct intel_encoder base
;
772 struct intel_hdmi hdmi
;
773 enum irqreturn (*hpd_pulse
)(struct intel_digital_port
*, bool);
776 struct intel_dp_mst_encoder
{
777 struct intel_encoder base
;
779 struct intel_digital_port
*primary
;
780 void *port
; /* store this opaque as its illegal to dereference it */
784 vlv_dport_to_channel(struct intel_digital_port
*dport
)
786 switch (dport
->port
) {
798 vlv_pipe_to_channel(enum pipe pipe
)
811 static inline struct drm_crtc
*
812 intel_get_crtc_for_pipe(struct drm_device
*dev
, int pipe
)
814 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
815 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
818 static inline struct drm_crtc
*
819 intel_get_crtc_for_plane(struct drm_device
*dev
, int plane
)
821 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
822 return dev_priv
->plane_to_crtc_mapping
[plane
];
825 struct intel_unpin_work
{
826 struct work_struct work
;
827 struct drm_crtc
*crtc
;
828 struct drm_framebuffer
*old_fb
;
829 struct drm_i915_gem_object
*pending_flip_obj
;
830 struct drm_pending_vblank_event
*event
;
832 #define INTEL_FLIP_INACTIVE 0
833 #define INTEL_FLIP_PENDING 1
834 #define INTEL_FLIP_COMPLETE 2
837 struct drm_i915_gem_request
*flip_queued_req
;
838 int flip_queued_vblank
;
839 int flip_ready_vblank
;
840 bool enable_stall_check
;
843 struct intel_load_detect_pipe
{
844 struct drm_framebuffer
*release_fb
;
845 bool load_detect_temp
;
849 static inline struct intel_encoder
*
850 intel_attached_encoder(struct drm_connector
*connector
)
852 return to_intel_connector(connector
)->encoder
;
855 static inline struct intel_digital_port
*
856 enc_to_dig_port(struct drm_encoder
*encoder
)
858 return container_of(encoder
, struct intel_digital_port
, base
.base
);
861 static inline struct intel_dp_mst_encoder
*
862 enc_to_mst(struct drm_encoder
*encoder
)
864 return container_of(encoder
, struct intel_dp_mst_encoder
, base
.base
);
867 static inline struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
869 return &enc_to_dig_port(encoder
)->dp
;
872 static inline struct intel_digital_port
*
873 dp_to_dig_port(struct intel_dp
*intel_dp
)
875 return container_of(intel_dp
, struct intel_digital_port
, dp
);
878 static inline struct intel_digital_port
*
879 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
881 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
885 * Returns the number of planes for this pipe, ie the number of sprites + 1
886 * (primary plane). This doesn't count the cursor plane then.
888 static inline unsigned int intel_num_planes(struct intel_crtc
*crtc
)
890 return INTEL_INFO(crtc
->base
.dev
)->num_sprites
[crtc
->pipe
] + 1;
893 /* intel_fifo_underrun.c */
894 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
895 enum pipe pipe
, bool enable
);
896 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
897 enum transcoder pch_transcoder
,
899 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
901 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
902 enum transcoder pch_transcoder
);
903 void i9xx_check_fifo_underruns(struct drm_i915_private
*dev_priv
);
906 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
907 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
908 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
909 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
910 void gen6_reset_rps_interrupts(struct drm_device
*dev
);
911 void gen6_enable_rps_interrupts(struct drm_device
*dev
);
912 void gen6_disable_rps_interrupts(struct drm_device
*dev
);
913 u32
gen6_sanitize_rps_pm_mask(struct drm_i915_private
*dev_priv
, u32 mask
);
914 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
);
915 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
);
916 static inline bool intel_irqs_enabled(struct drm_i915_private
*dev_priv
)
919 * We only use drm_irq_uninstall() at unload and VT switch, so
920 * this is the only thing we need to check.
922 return dev_priv
->pm
.irqs_enabled
;
925 int intel_get_crtc_scanline(struct intel_crtc
*crtc
);
926 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
927 unsigned int pipe_mask
);
930 void intel_crt_init(struct drm_device
*dev
);
934 void intel_prepare_ddi(struct drm_device
*dev
);
935 void hsw_fdi_link_train(struct drm_crtc
*crtc
);
936 void intel_ddi_init(struct drm_device
*dev
, enum port port
);
937 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
);
938 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
, enum pipe
*pipe
);
939 void intel_ddi_pll_init(struct drm_device
*dev
);
940 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
);
941 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
942 enum transcoder cpu_transcoder
);
943 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
);
944 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
);
945 bool intel_ddi_pll_select(struct intel_crtc
*crtc
,
946 struct intel_crtc_state
*crtc_state
);
947 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
);
948 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
);
949 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
);
950 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
);
951 void intel_ddi_get_config(struct intel_encoder
*encoder
,
952 struct intel_crtc_state
*pipe_config
);
953 struct intel_encoder
*
954 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state
*crtc_state
);
956 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
);
957 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
958 struct intel_crtc_state
*pipe_config
);
959 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
);
960 uint32_t ddi_signal_levels(struct intel_dp
*intel_dp
);
962 /* intel_frontbuffer.c */
963 void intel_fb_obj_invalidate(struct drm_i915_gem_object
*obj
,
964 enum fb_op_origin origin
);
965 void intel_frontbuffer_flip_prepare(struct drm_device
*dev
,
966 unsigned frontbuffer_bits
);
967 void intel_frontbuffer_flip_complete(struct drm_device
*dev
,
968 unsigned frontbuffer_bits
);
969 void intel_frontbuffer_flip(struct drm_device
*dev
,
970 unsigned frontbuffer_bits
);
971 unsigned int intel_fb_align_height(struct drm_device
*dev
,
973 uint32_t pixel_format
,
974 uint64_t fb_format_modifier
);
975 void intel_fb_obj_flush(struct drm_i915_gem_object
*obj
, bool retire
,
976 enum fb_op_origin origin
);
977 u32
intel_fb_stride_alignment(struct drm_device
*dev
, uint64_t fb_modifier
,
978 uint32_t pixel_format
);
981 void intel_init_audio(struct drm_device
*dev
);
982 void intel_audio_codec_enable(struct intel_encoder
*encoder
);
983 void intel_audio_codec_disable(struct intel_encoder
*encoder
);
984 void i915_audio_component_init(struct drm_i915_private
*dev_priv
);
985 void i915_audio_component_cleanup(struct drm_i915_private
*dev_priv
);
987 /* intel_display.c */
988 extern const struct drm_plane_funcs intel_plane_funcs
;
989 bool intel_has_pending_fb_unpin(struct drm_device
*dev
);
990 int intel_pch_rawclk(struct drm_device
*dev
);
991 void intel_mark_busy(struct drm_device
*dev
);
992 void intel_mark_idle(struct drm_device
*dev
);
993 void intel_crtc_restore_mode(struct drm_crtc
*crtc
);
994 int intel_display_suspend(struct drm_device
*dev
);
995 int intel_crtc_control(struct drm_crtc
*crtc
, bool enable
);
996 void intel_crtc_update_dpms(struct drm_crtc
*crtc
);
997 void intel_encoder_destroy(struct drm_encoder
*encoder
);
998 int intel_connector_init(struct intel_connector
*);
999 struct intel_connector
*intel_connector_alloc(void);
1000 int intel_connector_dpms(struct drm_connector
*, int mode
);
1001 bool intel_connector_get_hw_state(struct intel_connector
*connector
);
1002 void intel_modeset_check_state(struct drm_device
*dev
);
1003 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1004 struct intel_digital_port
*port
);
1005 void intel_connector_attach_encoder(struct intel_connector
*connector
,
1006 struct intel_encoder
*encoder
);
1007 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
);
1008 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
1009 struct drm_crtc
*crtc
);
1010 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
);
1011 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
1012 struct drm_file
*file_priv
);
1013 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1015 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
);
1017 intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
1019 drm_wait_one_vblank(dev
, pipe
);
1021 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
);
1022 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1023 struct intel_digital_port
*dport
,
1024 unsigned int expected_mask
);
1025 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
1026 struct drm_display_mode
*mode
,
1027 struct intel_load_detect_pipe
*old
,
1028 struct drm_modeset_acquire_ctx
*ctx
);
1029 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
1030 struct intel_load_detect_pipe
*old
,
1031 struct drm_modeset_acquire_ctx
*ctx
);
1032 int intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
1033 struct drm_framebuffer
*fb
,
1034 const struct drm_plane_state
*plane_state
,
1035 struct intel_engine_cs
*pipelined
,
1036 struct drm_i915_gem_request
**pipelined_request
);
1037 struct drm_framebuffer
*
1038 __intel_framebuffer_create(struct drm_device
*dev
,
1039 struct drm_mode_fb_cmd2
*mode_cmd
,
1040 struct drm_i915_gem_object
*obj
);
1041 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
);
1042 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
);
1043 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
);
1044 void intel_check_page_flip(struct drm_device
*dev
, int pipe
);
1045 int intel_prepare_plane_fb(struct drm_plane
*plane
,
1046 struct drm_framebuffer
*fb
,
1047 const struct drm_plane_state
*new_state
);
1048 void intel_cleanup_plane_fb(struct drm_plane
*plane
,
1049 struct drm_framebuffer
*fb
,
1050 const struct drm_plane_state
*old_state
);
1051 int intel_plane_atomic_get_property(struct drm_plane
*plane
,
1052 const struct drm_plane_state
*state
,
1053 struct drm_property
*property
,
1055 int intel_plane_atomic_set_property(struct drm_plane
*plane
,
1056 struct drm_plane_state
*state
,
1057 struct drm_property
*property
,
1059 int intel_plane_atomic_calc_changes(struct drm_crtc_state
*crtc_state
,
1060 struct drm_plane_state
*plane_state
);
1063 intel_tile_height(struct drm_device
*dev
, uint32_t pixel_format
,
1064 uint64_t fb_format_modifier
);
1067 intel_rotation_90_or_270(unsigned int rotation
)
1069 return rotation
& (BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
));
1072 void intel_create_rotation_property(struct drm_device
*dev
,
1073 struct intel_plane
*plane
);
1075 /* shared dpll functions */
1076 struct intel_shared_dpll
*intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
);
1077 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1078 struct intel_shared_dpll
*pll
,
1080 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1081 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1082 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
,
1083 struct intel_crtc_state
*state
);
1085 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
1086 const struct dpll
*dpll
);
1087 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
);
1089 /* modesetting asserts */
1090 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1092 void assert_pll(struct drm_i915_private
*dev_priv
,
1093 enum pipe pipe
, bool state
);
1094 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1095 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1096 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1097 enum pipe pipe
, bool state
);
1098 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1099 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1100 void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool state
);
1101 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1102 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1103 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private
*dev_priv
,
1105 unsigned int tiling_mode
,
1107 unsigned int pitch
);
1108 void intel_prepare_reset(struct drm_device
*dev
);
1109 void intel_finish_reset(struct drm_device
*dev
);
1110 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
);
1111 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
);
1112 void broxton_init_cdclk(struct drm_device
*dev
);
1113 void broxton_uninit_cdclk(struct drm_device
*dev
);
1114 void broxton_ddi_phy_init(struct drm_device
*dev
);
1115 void broxton_ddi_phy_uninit(struct drm_device
*dev
);
1116 void bxt_enable_dc9(struct drm_i915_private
*dev_priv
);
1117 void bxt_disable_dc9(struct drm_i915_private
*dev_priv
);
1118 void skl_init_cdclk(struct drm_i915_private
*dev_priv
);
1119 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1120 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
1121 struct intel_crtc_state
*pipe_config
);
1122 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
);
1123 int intel_dotclock_calculate(int link_freq
, const struct intel_link_m_n
*m_n
);
1125 ironlake_check_encoder_dotclock(const struct intel_crtc_state
*pipe_config
,
1127 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
1128 intel_clock_t
*best_clock
);
1129 int chv_calc_dpll_params(int refclk
, intel_clock_t
*pll_clock
);
1131 bool intel_crtc_active(struct drm_crtc
*crtc
);
1132 void hsw_enable_ips(struct intel_crtc
*crtc
);
1133 void hsw_disable_ips(struct intel_crtc
*crtc
);
1134 enum intel_display_power_domain
1135 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
);
1136 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
1137 struct intel_crtc_state
*pipe_config
);
1138 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
);
1139 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
);
1141 int skl_update_scaler_crtc(struct intel_crtc_state
*crtc_state
);
1142 int skl_max_scale(struct intel_crtc
*crtc
, struct intel_crtc_state
*crtc_state
);
1144 unsigned long intel_plane_obj_offset(struct intel_plane
*intel_plane
,
1145 struct drm_i915_gem_object
*obj
);
1146 u32
skl_plane_ctl_format(uint32_t pixel_format
);
1147 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
);
1148 u32
skl_plane_ctl_rotation(unsigned int rotation
);
1151 void intel_csr_ucode_init(struct drm_device
*dev
);
1152 enum csr_state
intel_csr_load_status_get(struct drm_i915_private
*dev_priv
);
1153 void intel_csr_load_status_set(struct drm_i915_private
*dev_priv
,
1154 enum csr_state state
);
1155 void intel_csr_load_program(struct drm_device
*dev
);
1156 void intel_csr_ucode_fini(struct drm_device
*dev
);
1157 void assert_csr_loaded(struct drm_i915_private
*dev_priv
);
1160 void intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
);
1161 bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
1162 struct intel_connector
*intel_connector
);
1163 void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
1164 void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
1165 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
);
1166 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
1167 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
);
1168 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
);
1169 bool intel_dp_compute_config(struct intel_encoder
*encoder
,
1170 struct intel_crtc_state
*pipe_config
);
1171 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
);
1172 enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
,
1174 void intel_edp_backlight_on(struct intel_dp
*intel_dp
);
1175 void intel_edp_backlight_off(struct intel_dp
*intel_dp
);
1176 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
1177 void intel_edp_panel_on(struct intel_dp
*intel_dp
);
1178 void intel_edp_panel_off(struct intel_dp
*intel_dp
);
1179 void intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
);
1180 void intel_dp_mst_suspend(struct drm_device
*dev
);
1181 void intel_dp_mst_resume(struct drm_device
*dev
);
1182 int intel_dp_max_link_rate(struct intel_dp
*intel_dp
);
1183 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
);
1184 void intel_dp_hot_plug(struct intel_encoder
*intel_encoder
);
1185 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
);
1186 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
);
1187 void intel_plane_destroy(struct drm_plane
*plane
);
1188 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
);
1189 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
);
1190 void intel_edp_drrs_invalidate(struct drm_device
*dev
,
1191 unsigned frontbuffer_bits
);
1192 void intel_edp_drrs_flush(struct drm_device
*dev
, unsigned frontbuffer_bits
);
1194 /* intel_dp_mst.c */
1195 int intel_dp_mst_encoder_init(struct intel_digital_port
*intel_dig_port
, int conn_id
);
1196 void intel_dp_mst_encoder_cleanup(struct intel_digital_port
*intel_dig_port
);
1198 void intel_dsi_init(struct drm_device
*dev
);
1202 void intel_dvo_init(struct drm_device
*dev
);
1205 /* legacy fbdev emulation in intel_fbdev.c */
1206 #ifdef CONFIG_DRM_I915_FBDEV
1207 extern int intel_fbdev_init(struct drm_device
*dev
);
1208 extern void intel_fbdev_initial_config(void *data
, async_cookie_t cookie
);
1209 extern void intel_fbdev_fini(struct drm_device
*dev
);
1210 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
);
1211 extern void intel_fbdev_output_poll_changed(struct drm_device
*dev
);
1212 extern void intel_fbdev_restore_mode(struct drm_device
*dev
);
1214 static inline int intel_fbdev_init(struct drm_device
*dev
)
1219 static inline void intel_fbdev_initial_config(void *data
, async_cookie_t cookie
)
1223 static inline void intel_fbdev_fini(struct drm_device
*dev
)
1227 static inline void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
)
1231 static inline void intel_fbdev_restore_mode(struct drm_device
*dev
)
1237 bool intel_fbc_enabled(struct drm_i915_private
*dev_priv
);
1238 void intel_fbc_update(struct drm_i915_private
*dev_priv
);
1239 void intel_fbc_init(struct drm_i915_private
*dev_priv
);
1240 void intel_fbc_disable(struct drm_i915_private
*dev_priv
);
1241 void intel_fbc_disable_crtc(struct intel_crtc
*crtc
);
1242 void intel_fbc_invalidate(struct drm_i915_private
*dev_priv
,
1243 unsigned int frontbuffer_bits
,
1244 enum fb_op_origin origin
);
1245 void intel_fbc_flush(struct drm_i915_private
*dev_priv
,
1246 unsigned int frontbuffer_bits
);
1247 const char *intel_no_fbc_reason_str(enum no_fbc_reason reason
);
1248 void intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
);
1251 void intel_hdmi_init(struct drm_device
*dev
, int hdmi_reg
, enum port port
);
1252 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
1253 struct intel_connector
*intel_connector
);
1254 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
);
1255 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
1256 struct intel_crtc_state
*pipe_config
);
1260 void intel_lvds_init(struct drm_device
*dev
);
1261 bool intel_is_dual_link_lvds(struct drm_device
*dev
);
1265 int intel_connector_update_modes(struct drm_connector
*connector
,
1267 int intel_ddc_get_modes(struct drm_connector
*c
, struct i2c_adapter
*adapter
);
1268 void intel_attach_force_audio_property(struct drm_connector
*connector
);
1269 void intel_attach_broadcast_rgb_property(struct drm_connector
*connector
);
1272 /* intel_overlay.c */
1273 void intel_setup_overlay(struct drm_device
*dev
);
1274 void intel_cleanup_overlay(struct drm_device
*dev
);
1275 int intel_overlay_switch_off(struct intel_overlay
*overlay
);
1276 int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
1277 struct drm_file
*file_priv
);
1278 int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
1279 struct drm_file
*file_priv
);
1280 void intel_overlay_reset(struct drm_i915_private
*dev_priv
);
1284 int intel_panel_init(struct intel_panel
*panel
,
1285 struct drm_display_mode
*fixed_mode
,
1286 struct drm_display_mode
*downclock_mode
);
1287 void intel_panel_fini(struct intel_panel
*panel
);
1288 void intel_fixed_panel_mode(const struct drm_display_mode
*fixed_mode
,
1289 struct drm_display_mode
*adjusted_mode
);
1290 void intel_pch_panel_fitting(struct intel_crtc
*crtc
,
1291 struct intel_crtc_state
*pipe_config
,
1293 void intel_gmch_panel_fitting(struct intel_crtc
*crtc
,
1294 struct intel_crtc_state
*pipe_config
,
1296 void intel_panel_set_backlight_acpi(struct intel_connector
*connector
,
1297 u32 level
, u32 max
);
1298 int intel_panel_setup_backlight(struct drm_connector
*connector
, enum pipe pipe
);
1299 void intel_panel_enable_backlight(struct intel_connector
*connector
);
1300 void intel_panel_disable_backlight(struct intel_connector
*connector
);
1301 void intel_panel_destroy_backlight(struct drm_connector
*connector
);
1302 void intel_panel_init_backlight_funcs(struct drm_device
*dev
);
1303 enum drm_connector_status
intel_panel_detect(struct drm_device
*dev
);
1304 extern struct drm_display_mode
*intel_find_panel_downclock(
1305 struct drm_device
*dev
,
1306 struct drm_display_mode
*fixed_mode
,
1307 struct drm_connector
*connector
);
1308 void intel_backlight_register(struct drm_device
*dev
);
1309 void intel_backlight_unregister(struct drm_device
*dev
);
1313 void intel_psr_enable(struct intel_dp
*intel_dp
);
1314 void intel_psr_disable(struct intel_dp
*intel_dp
);
1315 void intel_psr_invalidate(struct drm_device
*dev
,
1316 unsigned frontbuffer_bits
);
1317 void intel_psr_flush(struct drm_device
*dev
,
1318 unsigned frontbuffer_bits
,
1319 enum fb_op_origin origin
);
1320 void intel_psr_init(struct drm_device
*dev
);
1321 void intel_psr_single_frame_update(struct drm_device
*dev
,
1322 unsigned frontbuffer_bits
);
1324 /* intel_runtime_pm.c */
1325 int intel_power_domains_init(struct drm_i915_private
*);
1326 void intel_power_domains_fini(struct drm_i915_private
*);
1327 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
);
1328 void intel_runtime_pm_enable(struct drm_i915_private
*dev_priv
);
1330 bool intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1331 enum intel_display_power_domain domain
);
1332 bool __intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1333 enum intel_display_power_domain domain
);
1334 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
1335 enum intel_display_power_domain domain
);
1336 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
1337 enum intel_display_power_domain domain
);
1338 void intel_aux_display_runtime_get(struct drm_i915_private
*dev_priv
);
1339 void intel_aux_display_runtime_put(struct drm_i915_private
*dev_priv
);
1340 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
);
1341 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
);
1342 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
);
1344 void intel_display_set_init_power(struct drm_i915_private
*dev
, bool enable
);
1347 void intel_init_clock_gating(struct drm_device
*dev
);
1348 void intel_suspend_hw(struct drm_device
*dev
);
1349 int ilk_wm_max_level(const struct drm_device
*dev
);
1350 void intel_update_watermarks(struct drm_crtc
*crtc
);
1351 void intel_update_sprite_watermarks(struct drm_plane
*plane
,
1352 struct drm_crtc
*crtc
,
1353 uint32_t sprite_width
,
1354 uint32_t sprite_height
,
1356 bool enabled
, bool scaled
);
1357 void intel_init_pm(struct drm_device
*dev
);
1358 void intel_pm_setup(struct drm_device
*dev
);
1359 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
1360 void intel_gpu_ips_teardown(void);
1361 void intel_init_gt_powersave(struct drm_device
*dev
);
1362 void intel_cleanup_gt_powersave(struct drm_device
*dev
);
1363 void intel_enable_gt_powersave(struct drm_device
*dev
);
1364 void intel_disable_gt_powersave(struct drm_device
*dev
);
1365 void intel_suspend_gt_powersave(struct drm_device
*dev
);
1366 void intel_reset_gt_powersave(struct drm_device
*dev
);
1367 void gen6_update_ring_freq(struct drm_device
*dev
);
1368 void gen6_rps_busy(struct drm_i915_private
*dev_priv
);
1369 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
);
1370 void gen6_rps_idle(struct drm_i915_private
*dev_priv
);
1371 void gen6_rps_boost(struct drm_i915_private
*dev_priv
,
1372 struct intel_rps_client
*rps
,
1373 unsigned long submitted
);
1374 void intel_queue_rps_boost_for_request(struct drm_device
*dev
,
1375 struct drm_i915_gem_request
*req
);
1376 void vlv_wm_get_hw_state(struct drm_device
*dev
);
1377 void ilk_wm_get_hw_state(struct drm_device
*dev
);
1378 void skl_wm_get_hw_state(struct drm_device
*dev
);
1379 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
1380 struct skl_ddb_allocation
*ddb
/* out */);
1381 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
*pipe_config
);
1384 bool intel_sdvo_init(struct drm_device
*dev
, uint32_t sdvo_reg
, bool is_sdvob
);
1387 /* intel_sprite.c */
1388 int intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
);
1389 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
1390 struct drm_file
*file_priv
);
1391 void intel_pipe_update_start(struct intel_crtc
*crtc
,
1392 uint32_t *start_vbl_count
);
1393 void intel_pipe_update_end(struct intel_crtc
*crtc
, u32 start_vbl_count
);
1396 void intel_tv_init(struct drm_device
*dev
);
1398 /* intel_atomic.c */
1399 int intel_connector_atomic_get_property(struct drm_connector
*connector
,
1400 const struct drm_connector_state
*state
,
1401 struct drm_property
*property
,
1403 struct drm_crtc_state
*intel_crtc_duplicate_state(struct drm_crtc
*crtc
);
1404 void intel_crtc_destroy_state(struct drm_crtc
*crtc
,
1405 struct drm_crtc_state
*state
);
1406 struct drm_atomic_state
*intel_atomic_state_alloc(struct drm_device
*dev
);
1407 void intel_atomic_state_clear(struct drm_atomic_state
*);
1408 struct intel_shared_dpll_config
*
1409 intel_atomic_get_shared_dpll_state(struct drm_atomic_state
*s
);
1411 static inline struct intel_crtc_state
*
1412 intel_atomic_get_crtc_state(struct drm_atomic_state
*state
,
1413 struct intel_crtc
*crtc
)
1415 struct drm_crtc_state
*crtc_state
;
1416 crtc_state
= drm_atomic_get_crtc_state(state
, &crtc
->base
);
1417 if (IS_ERR(crtc_state
))
1418 return ERR_CAST(crtc_state
);
1420 return to_intel_crtc_state(crtc_state
);
1422 int intel_atomic_setup_scalers(struct drm_device
*dev
,
1423 struct intel_crtc
*intel_crtc
,
1424 struct intel_crtc_state
*crtc_state
);
1426 /* intel_atomic_plane.c */
1427 struct intel_plane_state
*intel_create_plane_state(struct drm_plane
*plane
);
1428 struct drm_plane_state
*intel_plane_duplicate_state(struct drm_plane
*plane
);
1429 void intel_plane_destroy_state(struct drm_plane
*plane
,
1430 struct drm_plane_state
*state
);
1431 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs
;
1433 #endif /* __INTEL_DRV_H__ */