2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/i2c.h>
29 #include <drm/i915_drm.h>
31 #include <drm/drm_crtc.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include <drm/drm_dp_helper.h>
37 * _wait_for - magic (register) wait macro
39 * Does the right thing for modeset paths when run under kdgb or similar atomic
40 * contexts. Note that it's important that we check the condition again after
41 * having timed out, since the timeout could be due to preemption or similar and
42 * we've never had a chance to check the condition before the timeout.
44 #define _wait_for(COND, MS, W) ({ \
45 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
48 if (time_after(jiffies, timeout__)) { \
53 if (W && drm_can_sleep()) { \
62 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
63 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
64 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
65 DIV_ROUND_UP((US), 1000), 0)
67 #define KHz(x) (1000*x)
68 #define MHz(x) KHz(1000*x)
71 * Display related stuff
74 /* store information about an Ixxx DVO */
75 /* The i830->i865 use multiple DVOs with multiple i2cs */
76 /* the i915, i945 have a single sDVO i2c bus - which is different */
78 /* maximum connectors per crtcs in the mode set */
79 #define INTELFB_CONN_LIMIT 4
81 #define INTEL_I2C_BUS_DVO 1
82 #define INTEL_I2C_BUS_SDVO 2
84 /* these are outputs from the chip - integrated only
85 external chips are via DVO or SDVO output */
86 #define INTEL_OUTPUT_UNUSED 0
87 #define INTEL_OUTPUT_ANALOG 1
88 #define INTEL_OUTPUT_DVO 2
89 #define INTEL_OUTPUT_SDVO 3
90 #define INTEL_OUTPUT_LVDS 4
91 #define INTEL_OUTPUT_TVOUT 5
92 #define INTEL_OUTPUT_HDMI 6
93 #define INTEL_OUTPUT_DISPLAYPORT 7
94 #define INTEL_OUTPUT_EDP 8
95 #define INTEL_OUTPUT_UNKNOWN 9
97 #define INTEL_DVO_CHIP_NONE 0
98 #define INTEL_DVO_CHIP_LVDS 1
99 #define INTEL_DVO_CHIP_TMDS 2
100 #define INTEL_DVO_CHIP_TVOUT 4
102 struct intel_framebuffer
{
103 struct drm_framebuffer base
;
104 struct drm_i915_gem_object
*obj
;
108 struct drm_fb_helper helper
;
109 struct intel_framebuffer ifb
;
110 struct list_head fbdev_list
;
111 struct drm_display_mode
*our_mode
;
114 struct intel_encoder
{
115 struct drm_encoder base
;
117 * The new crtc this encoder will be driven from. Only differs from
118 * base->crtc while a modeset is in progress.
120 struct intel_crtc
*new_crtc
;
124 * Intel hw has only one MUX where encoders could be clone, hence a
125 * simple flag is enough to compute the possible_clones mask.
128 bool connectors_active
;
129 void (*hot_plug
)(struct intel_encoder
*);
130 bool (*compute_config
)(struct intel_encoder
*,
131 struct intel_crtc_config
*);
132 void (*pre_pll_enable
)(struct intel_encoder
*);
133 void (*pre_enable
)(struct intel_encoder
*);
134 void (*enable
)(struct intel_encoder
*);
135 void (*mode_set
)(struct intel_encoder
*intel_encoder
);
136 void (*disable
)(struct intel_encoder
*);
137 void (*post_disable
)(struct intel_encoder
*);
138 /* Read out the current hw state of this connector, returning true if
139 * the encoder is active. If the encoder is enabled it also set the pipe
140 * it is connected to in the pipe parameter. */
141 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
142 /* Reconstructs the equivalent mode flags for the current hardware
143 * state. This must be called _after_ display->get_pipe_config has
144 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
145 * be set correctly before calling this function. */
146 void (*get_config
)(struct intel_encoder
*,
147 struct intel_crtc_config
*pipe_config
);
149 enum hpd_pin hpd_pin
;
153 struct drm_display_mode
*fixed_mode
;
157 struct intel_connector
{
158 struct drm_connector base
;
160 * The fixed encoder this connector is connected to.
162 struct intel_encoder
*encoder
;
165 * The new encoder this connector will be driven. Only differs from
166 * encoder while a modeset is in progress.
168 struct intel_encoder
*new_encoder
;
170 /* Reads out the current hw, returning true if the connector is enabled
171 * and active (i.e. dpms ON state). */
172 bool (*get_hw_state
)(struct intel_connector
*);
174 /* Panel info for eDP and LVDS */
175 struct intel_panel panel
;
177 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
180 /* since POLL and HPD connectors may use the same HPD line keep the native
181 state of connector->polled in case hotplug storm detection changes it */
185 typedef struct dpll
{
197 struct intel_crtc_config
{
199 * quirks - bitfield with hw state readout quirks
201 * For various reasons the hw state readout code might not be able to
202 * completely faithfully read out the current state. These cases are
203 * tracked with quirk flags so that fastboot and state checker can act
206 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
207 unsigned long quirks
;
209 struct drm_display_mode requested_mode
;
210 struct drm_display_mode adjusted_mode
;
211 /* Whether to set up the PCH/FDI. Note that we never allow sharing
212 * between pch encoders and cpu encoders. */
213 bool has_pch_encoder
;
215 /* CPU Transcoder for the pipe. Currently this can only differ from the
216 * pipe on Haswell (where we have a special eDP transcoder). */
217 enum transcoder cpu_transcoder
;
220 * Use reduced/limited/broadcast rbg range, compressing from the full
221 * range fed into the crtcs.
223 bool limited_color_range
;
225 /* DP has a bunch of special case unfortunately, so mark the pipe
230 * Enable dithering, used when the selected pipe bpp doesn't match the
235 /* Controls for the clock computation, to override various stages. */
238 /* SDVO TV has a bunch of special case. To make multifunction encoders
239 * work correctly, we need to track this at runtime.*/
243 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
244 * required. This is set in the 2nd loop of calling encoder's
245 * ->compute_config if the first pick doesn't work out.
249 /* Settings for the intel dpll used on pretty much everything but
253 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
254 enum intel_dpll_id shared_dpll
;
256 /* Actual register state of the dpll, for shared dpll cross-checking. */
257 struct intel_dpll_hw_state dpll_hw_state
;
260 struct intel_link_m_n dp_m_n
;
263 * Frequence the dpll for the port should run at. Differs from the
264 * adjusted dotclock e.g. for DP or 12bpc hdmi mode.
268 /* Used by SDVO (and if we ever fix it, HDMI). */
269 unsigned pixel_multiplier
;
271 /* Panel fitter controls for gen2-gen4 + VLV */
275 u32 lvds_border_bits
;
278 /* Panel fitter placement and size for Ironlake+ */
284 /* FDI configuration, only valid if has_pch_encoder is set. */
286 struct intel_link_m_n fdi_m_n
;
292 struct drm_crtc base
;
295 u8 lut_r
[256], lut_g
[256], lut_b
[256];
297 * Whether the crtc and the connected output pipeline is active. Implies
298 * that crtc->enabled is set, i.e. the current mode configuration has
299 * some outputs connected to this crtc.
303 bool primary_disabled
; /* is the crtc obscured by a plane? */
305 struct intel_overlay
*overlay
;
306 struct intel_unpin_work
*unpin_work
;
308 atomic_t unpin_work_count
;
310 /* Display surface base address adjustement for pageflips. Note that on
311 * gen4+ this only adjusts up to a tile, offsets within a tile are
312 * handled in the hw itself (with the TILEOFF register). */
313 unsigned long dspaddr_offset
;
315 struct drm_i915_gem_object
*cursor_bo
;
316 uint32_t cursor_addr
;
317 int16_t cursor_x
, cursor_y
;
318 int16_t cursor_width
, cursor_height
;
321 struct intel_crtc_config config
;
323 uint32_t ddi_pll_sel
;
325 /* reset counter value when the last flip was submitted */
326 unsigned int reset_counter
;
328 /* Access to these should be protected by dev_priv->irq_lock. */
329 bool cpu_fifo_underrun_disabled
;
330 bool pch_fifo_underrun_disabled
;
334 struct drm_plane base
;
337 struct drm_i915_gem_object
*obj
;
340 u32 lut_r
[1024], lut_g
[1024], lut_b
[1024];
342 unsigned int crtc_w
, crtc_h
;
343 uint32_t src_x
, src_y
;
344 uint32_t src_w
, src_h
;
346 /* Since we need to change the watermarks before/after
347 * enabling/disabling the planes, we need to store the parameters here
348 * as the other pieces of the struct may not reflect the values we want
349 * for the watermark calculations. Currently only Haswell uses this.
354 uint8_t bytes_per_pixel
;
355 uint32_t horiz_pixels
;
358 void (*update_plane
)(struct drm_plane
*plane
,
359 struct drm_framebuffer
*fb
,
360 struct drm_i915_gem_object
*obj
,
361 int crtc_x
, int crtc_y
,
362 unsigned int crtc_w
, unsigned int crtc_h
,
363 uint32_t x
, uint32_t y
,
364 uint32_t src_w
, uint32_t src_h
);
365 void (*disable_plane
)(struct drm_plane
*plane
);
366 int (*update_colorkey
)(struct drm_plane
*plane
,
367 struct drm_intel_sprite_colorkey
*key
);
368 void (*get_colorkey
)(struct drm_plane
*plane
,
369 struct drm_intel_sprite_colorkey
*key
);
372 struct intel_watermark_params
{
373 unsigned long fifo_size
;
374 unsigned long max_wm
;
375 unsigned long default_wm
;
376 unsigned long guard_size
;
377 unsigned long cacheline_size
;
380 struct cxsr_latency
{
383 unsigned long fsb_freq
;
384 unsigned long mem_freq
;
385 unsigned long display_sr
;
386 unsigned long display_hpll_disable
;
387 unsigned long cursor_sr
;
388 unsigned long cursor_hpll_disable
;
391 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
392 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
393 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
394 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
395 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
397 #define DIP_HEADER_SIZE 5
399 #define DIP_TYPE_AVI 0x82
400 #define DIP_VERSION_AVI 0x2
401 #define DIP_LEN_AVI 13
402 #define DIP_AVI_PR_1 0
403 #define DIP_AVI_PR_2 1
404 #define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
405 #define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
406 #define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2)
408 #define DIP_TYPE_SPD 0x83
409 #define DIP_VERSION_SPD 0x1
410 #define DIP_LEN_SPD 25
411 #define DIP_SPD_UNKNOWN 0
412 #define DIP_SPD_DSTB 0x1
413 #define DIP_SPD_DVDP 0x2
414 #define DIP_SPD_DVHS 0x3
415 #define DIP_SPD_HDDVR 0x4
416 #define DIP_SPD_DVC 0x5
417 #define DIP_SPD_DSC 0x6
418 #define DIP_SPD_VCD 0x7
419 #define DIP_SPD_GAME 0x8
420 #define DIP_SPD_PC 0x9
421 #define DIP_SPD_BD 0xa
422 #define DIP_SPD_SCD 0xb
424 struct dip_infoframe
{
425 uint8_t type
; /* HB0 */
426 uint8_t ver
; /* HB1 */
427 uint8_t len
; /* HB2 - body len, not including checksum */
428 uint8_t ecc
; /* Header ECC */
429 uint8_t checksum
; /* PB0 */
432 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
434 /* PB2 - C 7:6, M 5:4, R 3:0 */
436 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
440 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
443 uint16_t top_bar_end
;
444 uint16_t bottom_bar_start
;
445 uint16_t left_bar_end
;
446 uint16_t right_bar_start
;
447 } __attribute__ ((packed
)) avi
;
452 } __attribute__ ((packed
)) spd
;
454 } __attribute__ ((packed
)) body
;
455 } __attribute__((packed
));
460 uint32_t color_range
;
461 bool color_range_auto
;
464 enum hdmi_force_audio force_audio
;
465 bool rgb_quant_range_selectable
;
466 void (*write_infoframe
)(struct drm_encoder
*encoder
,
467 struct dip_infoframe
*frame
);
468 void (*set_infoframes
)(struct drm_encoder
*encoder
,
469 struct drm_display_mode
*adjusted_mode
);
472 #define DP_MAX_DOWNSTREAM_PORTS 0x10
473 #define DP_LINK_CONFIGURATION_SIZE 9
477 uint32_t aux_ch_ctl_reg
;
479 uint8_t link_configuration
[DP_LINK_CONFIGURATION_SIZE
];
481 enum hdmi_force_audio force_audio
;
482 uint32_t color_range
;
483 bool color_range_auto
;
486 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
487 uint8_t psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
488 uint8_t downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
489 struct i2c_adapter adapter
;
490 struct i2c_algo_dp_aux_data algo
;
491 uint8_t train_set
[4];
492 int panel_power_up_delay
;
493 int panel_power_down_delay
;
494 int panel_power_cycle_delay
;
495 int backlight_on_delay
;
496 int backlight_off_delay
;
497 struct delayed_work panel_vdd_work
;
500 struct intel_connector
*attached_connector
;
503 struct intel_digital_port
{
504 struct intel_encoder base
;
508 struct intel_hdmi hdmi
;
512 vlv_dport_to_channel(struct intel_digital_port
*dport
)
514 switch (dport
->port
) {
524 static inline struct drm_crtc
*
525 intel_get_crtc_for_pipe(struct drm_device
*dev
, int pipe
)
527 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
528 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
531 static inline struct drm_crtc
*
532 intel_get_crtc_for_plane(struct drm_device
*dev
, int plane
)
534 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
535 return dev_priv
->plane_to_crtc_mapping
[plane
];
538 struct intel_unpin_work
{
539 struct work_struct work
;
540 struct drm_crtc
*crtc
;
541 struct drm_i915_gem_object
*old_fb_obj
;
542 struct drm_i915_gem_object
*pending_flip_obj
;
543 struct drm_pending_vblank_event
*event
;
545 #define INTEL_FLIP_INACTIVE 0
546 #define INTEL_FLIP_PENDING 1
547 #define INTEL_FLIP_COMPLETE 2
548 bool enable_stall_check
;
551 int intel_pch_rawclk(struct drm_device
*dev
);
553 int intel_connector_update_modes(struct drm_connector
*connector
,
555 int intel_ddc_get_modes(struct drm_connector
*c
, struct i2c_adapter
*adapter
);
557 extern void intel_attach_force_audio_property(struct drm_connector
*connector
);
558 extern void intel_attach_broadcast_rgb_property(struct drm_connector
*connector
);
560 extern bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
561 extern void intel_crt_init(struct drm_device
*dev
);
562 extern void intel_hdmi_init(struct drm_device
*dev
,
563 int hdmi_reg
, enum port port
);
564 extern void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
565 struct intel_connector
*intel_connector
);
566 extern struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
);
567 extern bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
568 struct intel_crtc_config
*pipe_config
);
569 extern void intel_dip_infoframe_csum(struct dip_infoframe
*avi_if
);
570 extern bool intel_sdvo_init(struct drm_device
*dev
, uint32_t sdvo_reg
,
572 extern void intel_dvo_init(struct drm_device
*dev
);
573 extern void intel_tv_init(struct drm_device
*dev
);
574 extern void intel_mark_busy(struct drm_device
*dev
);
575 extern void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
,
576 struct intel_ring_buffer
*ring
);
577 extern void intel_mark_idle(struct drm_device
*dev
);
578 extern void intel_lvds_init(struct drm_device
*dev
);
579 extern bool intel_is_dual_link_lvds(struct drm_device
*dev
);
580 extern void intel_dp_init(struct drm_device
*dev
, int output_reg
,
582 extern bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
583 struct intel_connector
*intel_connector
);
584 extern void intel_dp_init_link_config(struct intel_dp
*intel_dp
);
585 extern void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
586 extern void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
587 extern void intel_dp_stop_link_train(struct intel_dp
*intel_dp
);
588 extern void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
589 extern void intel_dp_encoder_destroy(struct drm_encoder
*encoder
);
590 extern void intel_dp_check_link_status(struct intel_dp
*intel_dp
);
591 extern bool intel_dp_compute_config(struct intel_encoder
*encoder
,
592 struct intel_crtc_config
*pipe_config
);
593 extern bool intel_dpd_is_edp(struct drm_device
*dev
);
594 extern void ironlake_edp_backlight_on(struct intel_dp
*intel_dp
);
595 extern void ironlake_edp_backlight_off(struct intel_dp
*intel_dp
);
596 extern void ironlake_edp_panel_on(struct intel_dp
*intel_dp
);
597 extern void ironlake_edp_panel_off(struct intel_dp
*intel_dp
);
598 extern void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
599 extern void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
600 extern int intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
);
601 extern void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
605 extern int intel_panel_init(struct intel_panel
*panel
,
606 struct drm_display_mode
*fixed_mode
);
607 extern void intel_panel_fini(struct intel_panel
*panel
);
609 extern void intel_fixed_panel_mode(struct drm_display_mode
*fixed_mode
,
610 struct drm_display_mode
*adjusted_mode
);
611 extern void intel_pch_panel_fitting(struct intel_crtc
*crtc
,
612 struct intel_crtc_config
*pipe_config
,
614 extern void intel_gmch_panel_fitting(struct intel_crtc
*crtc
,
615 struct intel_crtc_config
*pipe_config
,
617 extern void intel_panel_set_backlight(struct drm_device
*dev
,
619 extern int intel_panel_setup_backlight(struct drm_connector
*connector
);
620 extern void intel_panel_enable_backlight(struct drm_device
*dev
,
622 extern void intel_panel_disable_backlight(struct drm_device
*dev
);
623 extern void intel_panel_destroy_backlight(struct drm_device
*dev
);
624 extern enum drm_connector_status
intel_panel_detect(struct drm_device
*dev
);
626 struct intel_set_config
{
627 struct drm_encoder
**save_connector_encoders
;
628 struct drm_crtc
**save_encoder_crtcs
;
634 extern int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
635 int x
, int y
, struct drm_framebuffer
*old_fb
);
636 extern void intel_modeset_disable(struct drm_device
*dev
);
637 extern void intel_crtc_restore_mode(struct drm_crtc
*crtc
);
638 extern void intel_crtc_load_lut(struct drm_crtc
*crtc
);
639 extern void intel_crtc_update_dpms(struct drm_crtc
*crtc
);
640 extern void intel_encoder_destroy(struct drm_encoder
*encoder
);
641 extern void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
);
642 extern void intel_connector_dpms(struct drm_connector
*, int mode
);
643 extern bool intel_connector_get_hw_state(struct intel_connector
*connector
);
644 extern void intel_modeset_check_state(struct drm_device
*dev
);
645 extern void intel_plane_restore(struct drm_plane
*plane
);
646 extern void intel_plane_disable(struct drm_plane
*plane
);
649 static inline struct intel_encoder
*intel_attached_encoder(struct drm_connector
*connector
)
651 return to_intel_connector(connector
)->encoder
;
654 static inline struct intel_digital_port
*
655 enc_to_dig_port(struct drm_encoder
*encoder
)
657 return container_of(encoder
, struct intel_digital_port
, base
.base
);
660 static inline struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
662 return &enc_to_dig_port(encoder
)->dp
;
665 static inline struct intel_digital_port
*
666 dp_to_dig_port(struct intel_dp
*intel_dp
)
668 return container_of(intel_dp
, struct intel_digital_port
, dp
);
671 static inline struct intel_digital_port
*
672 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
674 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
677 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
678 struct intel_digital_port
*port
);
680 extern void intel_connector_attach_encoder(struct intel_connector
*connector
,
681 struct intel_encoder
*encoder
);
682 extern struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
);
684 extern struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
685 struct drm_crtc
*crtc
);
686 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
687 struct drm_file
*file_priv
);
688 extern enum transcoder
689 intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
691 extern void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
);
692 extern void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
);
693 extern int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
);
694 extern void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
, int port
);
696 struct intel_load_detect_pipe
{
697 struct drm_framebuffer
*release_fb
;
698 bool load_detect_temp
;
701 extern bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
702 struct drm_display_mode
*mode
,
703 struct intel_load_detect_pipe
*old
);
704 extern void intel_release_load_detect_pipe(struct drm_connector
*connector
,
705 struct intel_load_detect_pipe
*old
);
707 extern void intelfb_restore(void);
708 extern void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
709 u16 blue
, int regno
);
710 extern void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
711 u16
*blue
, int regno
);
712 extern void intel_enable_clock_gating(struct drm_device
*dev
);
714 extern int intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
715 struct drm_i915_gem_object
*obj
,
716 struct intel_ring_buffer
*pipelined
);
717 extern void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
);
719 extern int intel_framebuffer_init(struct drm_device
*dev
,
720 struct intel_framebuffer
*ifb
,
721 struct drm_mode_fb_cmd2
*mode_cmd
,
722 struct drm_i915_gem_object
*obj
);
723 extern void intel_framebuffer_fini(struct intel_framebuffer
*fb
);
724 extern int intel_fbdev_init(struct drm_device
*dev
);
725 extern void intel_fbdev_initial_config(struct drm_device
*dev
);
726 extern void intel_fbdev_fini(struct drm_device
*dev
);
727 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
);
728 extern void intel_prepare_page_flip(struct drm_device
*dev
, int plane
);
729 extern void intel_finish_page_flip(struct drm_device
*dev
, int pipe
);
730 extern void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
);
732 extern void intel_setup_overlay(struct drm_device
*dev
);
733 extern void intel_cleanup_overlay(struct drm_device
*dev
);
734 extern int intel_overlay_switch_off(struct intel_overlay
*overlay
);
735 extern int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
736 struct drm_file
*file_priv
);
737 extern int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
738 struct drm_file
*file_priv
);
740 extern void intel_fb_output_poll_changed(struct drm_device
*dev
);
741 extern void intel_fb_restore_mode(struct drm_device
*dev
);
743 struct intel_shared_dpll
*
744 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
);
746 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
747 struct intel_shared_dpll
*pll
,
749 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
750 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
751 void assert_pll(struct drm_i915_private
*dev_priv
,
752 enum pipe pipe
, bool state
);
753 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
754 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
755 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
756 enum pipe pipe
, bool state
);
757 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
758 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
759 extern void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
761 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
762 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
764 extern void intel_init_clock_gating(struct drm_device
*dev
);
765 extern void intel_suspend_hw(struct drm_device
*dev
);
766 extern void intel_write_eld(struct drm_encoder
*encoder
,
767 struct drm_display_mode
*mode
);
768 extern void intel_prepare_ddi(struct drm_device
*dev
);
769 extern void hsw_fdi_link_train(struct drm_crtc
*crtc
);
770 extern void intel_ddi_init(struct drm_device
*dev
, enum port port
);
772 /* For use by IVB LP watermark workaround in intel_sprite.c */
773 extern void intel_update_watermarks(struct drm_device
*dev
);
774 extern void intel_update_sprite_watermarks(struct drm_device
*dev
, int pipe
,
775 uint32_t sprite_width
, int pixel_size
,
776 bool enabled
, bool scaled
);
778 extern unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
779 unsigned int tiling_mode
,
783 extern int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
784 struct drm_file
*file_priv
);
785 extern int intel_sprite_get_colorkey(struct drm_device
*dev
, void *data
,
786 struct drm_file
*file_priv
);
788 /* Power-related functions, located in intel_pm.c */
789 extern void intel_init_pm(struct drm_device
*dev
);
791 extern bool intel_fbc_enabled(struct drm_device
*dev
);
792 extern void intel_update_fbc(struct drm_device
*dev
);
794 extern void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
795 extern void intel_gpu_ips_teardown(void);
798 extern int i915_init_power_well(struct drm_device
*dev
);
799 extern void i915_remove_power_well(struct drm_device
*dev
);
801 extern bool intel_display_power_enabled(struct drm_device
*dev
,
802 enum intel_display_power_domain domain
);
803 extern void intel_init_power_well(struct drm_device
*dev
);
804 extern void intel_set_power_well(struct drm_device
*dev
, bool enable
);
805 extern void intel_enable_gt_powersave(struct drm_device
*dev
);
806 extern void intel_disable_gt_powersave(struct drm_device
*dev
);
807 extern void ironlake_teardown_rc6(struct drm_device
*dev
);
809 extern bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
811 extern int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
);
812 extern void intel_ddi_pll_init(struct drm_device
*dev
);
813 extern void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
);
814 extern void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
815 enum transcoder cpu_transcoder
);
816 extern void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
);
817 extern void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
);
818 extern void intel_ddi_setup_hw_pll_state(struct drm_device
*dev
);
819 extern bool intel_ddi_pll_mode_set(struct drm_crtc
*crtc
);
820 extern void intel_ddi_put_crtc_pll(struct drm_crtc
*crtc
);
821 extern void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
);
822 extern void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
);
824 intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
);
825 extern void intel_ddi_fdi_disable(struct drm_crtc
*crtc
);
827 extern void intel_display_handle_reset(struct drm_device
*dev
);
828 extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
831 extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device
*dev
,
832 enum transcoder pch_transcoder
,
835 extern void intel_edp_psr_enable(struct intel_dp
*intel_dp
);
836 extern void intel_edp_psr_disable(struct intel_dp
*intel_dp
);
837 extern void intel_edp_psr_update(struct drm_device
*dev
);
838 extern void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
839 bool switch_to_fclk
, bool allow_power_down
);
840 extern void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
);
842 #endif /* __INTEL_DRV_H__ */