2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_dual_mode_helper.h>
37 #include <drm/drm_dp_mst_helper.h>
38 #include <drm/drm_rect.h>
39 #include <drm/drm_atomic.h>
42 * _wait_for - magic (register) wait macro
44 * Does the right thing for modeset paths when run under kdgb or similar atomic
45 * contexts. Note that it's important that we check the condition again after
46 * having timed out, since the timeout could be due to preemption or similar and
47 * we've never had a chance to check the condition before the timeout.
49 * TODO: When modesetting has fully transitioned to atomic, the below
50 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
53 #define _wait_for(COND, US, W) ({ \
54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
57 if (time_after(jiffies, timeout__)) { \
62 if ((W) && drm_can_sleep()) { \
63 usleep_range((W), (W)*2); \
71 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
73 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
74 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
75 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
77 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
80 #define _wait_for_atomic(COND, US, ATOMIC) \
82 int cpu, ret, timeout = (US) * 1000; \
84 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
85 BUILD_BUG_ON((US) > 50000); \
88 cpu = smp_processor_id(); \
90 base = local_clock(); \
92 u64 now = local_clock(); \
99 if (now - base >= timeout) { \
106 if (unlikely(cpu != smp_processor_id())) { \
107 timeout -= now - base; \
108 cpu = smp_processor_id(); \
109 base = local_clock(); \
116 #define wait_for_us(COND, US) \
119 BUILD_BUG_ON(!__builtin_constant_p(US)); \
121 ret__ = _wait_for((COND), (US), 10); \
123 ret__ = _wait_for_atomic((COND), (US), 0); \
127 #define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000, 1)
128 #define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US), 1)
130 #define KHz(x) (1000 * (x))
131 #define MHz(x) KHz(1000 * (x))
134 * Display related stuff
137 /* store information about an Ixxx DVO */
138 /* The i830->i865 use multiple DVOs with multiple i2cs */
139 /* the i915, i945 have a single sDVO i2c bus - which is different */
140 #define MAX_OUTPUTS 6
141 /* maximum connectors per crtcs in the mode set */
143 /* Maximum cursor sizes */
144 #define GEN2_CURSOR_WIDTH 64
145 #define GEN2_CURSOR_HEIGHT 64
146 #define MAX_CURSOR_WIDTH 256
147 #define MAX_CURSOR_HEIGHT 256
149 #define INTEL_I2C_BUS_DVO 1
150 #define INTEL_I2C_BUS_SDVO 2
152 /* these are outputs from the chip - integrated only
153 external chips are via DVO or SDVO output */
154 enum intel_output_type
{
155 INTEL_OUTPUT_UNUSED
= 0,
156 INTEL_OUTPUT_ANALOG
= 1,
157 INTEL_OUTPUT_DVO
= 2,
158 INTEL_OUTPUT_SDVO
= 3,
159 INTEL_OUTPUT_LVDS
= 4,
160 INTEL_OUTPUT_TVOUT
= 5,
161 INTEL_OUTPUT_HDMI
= 6,
163 INTEL_OUTPUT_EDP
= 8,
164 INTEL_OUTPUT_DSI
= 9,
165 INTEL_OUTPUT_UNKNOWN
= 10,
166 INTEL_OUTPUT_DP_MST
= 11,
169 #define INTEL_DVO_CHIP_NONE 0
170 #define INTEL_DVO_CHIP_LVDS 1
171 #define INTEL_DVO_CHIP_TMDS 2
172 #define INTEL_DVO_CHIP_TVOUT 4
174 #define INTEL_DSI_VIDEO_MODE 0
175 #define INTEL_DSI_COMMAND_MODE 1
177 struct intel_framebuffer
{
178 struct drm_framebuffer base
;
179 struct drm_i915_gem_object
*obj
;
180 struct intel_rotation_info rot_info
;
182 /* for each plane in the normal GTT view */
186 /* for each plane in the rotated GTT view */
189 unsigned int pitch
; /* pixels */
194 struct drm_fb_helper helper
;
195 struct intel_framebuffer
*fb
;
196 async_cookie_t cookie
;
200 struct intel_encoder
{
201 struct drm_encoder base
;
203 enum intel_output_type type
;
204 unsigned int cloneable
;
205 void (*hot_plug
)(struct intel_encoder
*);
206 bool (*compute_config
)(struct intel_encoder
*,
207 struct intel_crtc_state
*);
208 void (*pre_pll_enable
)(struct intel_encoder
*);
209 void (*pre_enable
)(struct intel_encoder
*);
210 void (*enable
)(struct intel_encoder
*);
211 void (*mode_set
)(struct intel_encoder
*intel_encoder
);
212 void (*disable
)(struct intel_encoder
*);
213 void (*post_disable
)(struct intel_encoder
*);
214 void (*post_pll_disable
)(struct intel_encoder
*);
215 /* Read out the current hw state of this connector, returning true if
216 * the encoder is active. If the encoder is enabled it also set the pipe
217 * it is connected to in the pipe parameter. */
218 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
219 /* Reconstructs the equivalent mode flags for the current hardware
220 * state. This must be called _after_ display->get_pipe_config has
221 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
222 * be set correctly before calling this function. */
223 void (*get_config
)(struct intel_encoder
*,
224 struct intel_crtc_state
*pipe_config
);
226 * Called during system suspend after all pending requests for the
227 * encoder are flushed (for example for DP AUX transactions) and
228 * device interrupts are disabled.
230 void (*suspend
)(struct intel_encoder
*);
232 enum hpd_pin hpd_pin
;
236 struct drm_display_mode
*fixed_mode
;
237 struct drm_display_mode
*downclock_mode
;
247 bool combination_mode
; /* gen 2/4 only */
251 bool util_pin_active_low
; /* bxt+ */
252 u8 controller
; /* bxt+ only */
253 struct pwm_device
*pwm
;
255 struct backlight_device
*device
;
257 /* Connector and platform specific backlight functions */
258 int (*setup
)(struct intel_connector
*connector
, enum pipe pipe
);
259 uint32_t (*get
)(struct intel_connector
*connector
);
260 void (*set
)(struct intel_connector
*connector
, uint32_t level
);
261 void (*disable
)(struct intel_connector
*connector
);
262 void (*enable
)(struct intel_connector
*connector
);
263 uint32_t (*hz_to_pwm
)(struct intel_connector
*connector
,
265 void (*power
)(struct intel_connector
*, bool enable
);
269 struct intel_connector
{
270 struct drm_connector base
;
272 * The fixed encoder this connector is connected to.
274 struct intel_encoder
*encoder
;
276 /* Reads out the current hw, returning true if the connector is enabled
277 * and active (i.e. dpms ON state). */
278 bool (*get_hw_state
)(struct intel_connector
*);
280 /* Panel info for eDP and LVDS */
281 struct intel_panel panel
;
283 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
285 struct edid
*detect_edid
;
287 /* since POLL and HPD connectors may use the same HPD line keep the native
288 state of connector->polled in case hotplug storm detection changes it */
291 void *port
; /* store this opaque as its illegal to dereference it */
293 struct intel_dp
*mst_port
;
308 struct intel_atomic_state
{
309 struct drm_atomic_state base
;
314 * Calculated device cdclk, can be different from cdclk
315 * only when all crtc's are DPMS off.
317 unsigned int dev_cdclk
;
319 bool dpll_set
, modeset
;
322 * Does this transaction change the pipes that are active? This mask
323 * tracks which CRTC's have changed their active state at the end of
324 * the transaction (not counting the temporary disable during modesets).
325 * This mask should only be non-zero when intel_state->modeset is true,
326 * but the converse is not necessarily true; simply changing a mode may
327 * not flip the final active status of any CRTC's
329 unsigned int active_pipe_changes
;
331 unsigned int active_crtcs
;
332 unsigned int min_pixclk
[I915_MAX_PIPES
];
335 unsigned int cdclk_pll_vco
;
337 struct intel_shared_dpll_config shared_dpll
[I915_NUM_PLLS
];
340 * Current watermarks can't be trusted during hardware readout, so
341 * don't bother calculating intermediate watermarks.
343 bool skip_intermediate_wm
;
346 struct skl_wm_values wm_results
;
349 struct intel_plane_state
{
350 struct drm_plane_state base
;
353 struct drm_rect clip
;
358 * = -1 : not using a scaler
359 * >= 0 : using a scalers
361 * plane requiring a scaler:
362 * - During check_plane, its bit is set in
363 * crtc_state->scaler_state.scaler_users by calling helper function
364 * update_scaler_plane.
365 * - scaler_id indicates the scaler it got assigned.
367 * plane doesn't require a scaler:
368 * - this can happen when scaling is no more required or plane simply
370 * - During check_plane, corresponding bit is reset in
371 * crtc_state->scaler_state.scaler_users by calling helper function
372 * update_scaler_plane.
376 struct drm_intel_sprite_colorkey ckey
;
378 /* async flip related structures */
379 struct drm_i915_gem_request
*wait_req
;
382 struct intel_initial_plane_config
{
383 struct intel_framebuffer
*fb
;
389 #define SKL_MIN_SRC_W 8
390 #define SKL_MAX_SRC_W 4096
391 #define SKL_MIN_SRC_H 8
392 #define SKL_MAX_SRC_H 4096
393 #define SKL_MIN_DST_W 8
394 #define SKL_MAX_DST_W 4096
395 #define SKL_MIN_DST_H 8
396 #define SKL_MAX_DST_H 4096
398 struct intel_scaler
{
403 struct intel_crtc_scaler_state
{
404 #define SKL_NUM_SCALERS 2
405 struct intel_scaler scalers
[SKL_NUM_SCALERS
];
408 * scaler_users: keeps track of users requesting scalers on this crtc.
410 * If a bit is set, a user is using a scaler.
411 * Here user can be a plane or crtc as defined below:
412 * bits 0-30 - plane (bit position is index from drm_plane_index)
415 * Instead of creating a new index to cover planes and crtc, using
416 * existing drm_plane_index for planes which is well less than 31
417 * planes and bit 31 for crtc. This should be fine to cover all
420 * intel_atomic_setup_scalers will setup available scalers to users
421 * requesting scalers. It will gracefully fail if request exceeds
424 #define SKL_CRTC_INDEX 31
425 unsigned scaler_users
;
427 /* scaler used by crtc for panel fitting purpose */
431 /* drm_mode->private_flags */
432 #define I915_MODE_FLAG_INHERITED 1
434 struct intel_pipe_wm
{
435 struct intel_wm_level wm
[5];
436 struct intel_wm_level raw_wm
[5];
440 bool sprites_enabled
;
445 struct skl_wm_level wm
[8];
446 struct skl_wm_level trans_wm
;
450 struct intel_crtc_wm_state
{
454 * Intermediate watermarks; these can be
455 * programmed immediately since they satisfy
456 * both the current configuration we're
457 * switching away from and the new
458 * configuration we're switching to.
460 struct intel_pipe_wm intermediate
;
463 * Optimal watermarks, programmed post-vblank
464 * when this state is committed.
466 struct intel_pipe_wm optimal
;
470 /* gen9+ only needs 1-step wm programming */
471 struct skl_pipe_wm optimal
;
473 /* cached plane data rate */
474 unsigned plane_data_rate
[I915_MAX_PLANES
];
475 unsigned plane_y_data_rate
[I915_MAX_PLANES
];
477 /* minimum block allocation */
478 uint16_t minimum_blocks
[I915_MAX_PLANES
];
479 uint16_t minimum_y_blocks
[I915_MAX_PLANES
];
484 * Platforms with two-step watermark programming will need to
485 * update watermark programming post-vblank to switch from the
486 * safe intermediate watermarks to the optimal final
489 bool need_postvbl_update
;
492 struct intel_crtc_state
{
493 struct drm_crtc_state base
;
496 * quirks - bitfield with hw state readout quirks
498 * For various reasons the hw state readout code might not be able to
499 * completely faithfully read out the current state. These cases are
500 * tracked with quirk flags so that fastboot and state checker can act
503 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
504 unsigned long quirks
;
506 unsigned fb_bits
; /* framebuffers to flip */
507 bool update_pipe
; /* can a fast modeset be performed? */
509 bool update_wm_pre
, update_wm_post
; /* watermarks are updated */
510 bool fb_changed
; /* fb on any of the planes is changed */
512 /* Pipe source size (ie. panel fitter input size)
513 * All planes will be positioned inside this space,
514 * and get clipped at the edges. */
515 int pipe_src_w
, pipe_src_h
;
517 /* Whether to set up the PCH/FDI. Note that we never allow sharing
518 * between pch encoders and cpu encoders. */
519 bool has_pch_encoder
;
521 /* Are we sending infoframes on the attached port */
524 /* CPU Transcoder for the pipe. Currently this can only differ from the
525 * pipe on Haswell and later (where we have a special eDP transcoder)
526 * and Broxton (where we have special DSI transcoders). */
527 enum transcoder cpu_transcoder
;
530 * Use reduced/limited/broadcast rbg range, compressing from the full
531 * range fed into the crtcs.
533 bool limited_color_range
;
535 /* Bitmask of encoder types (enum intel_output_type)
536 * driven by the pipe.
538 unsigned int output_types
;
540 /* Whether we should send NULL infoframes. Required for audio. */
543 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
544 * has_dp_encoder is set. */
548 * Enable dithering, used when the selected pipe bpp doesn't match the
553 /* Controls for the clock computation, to override various stages. */
556 /* SDVO TV has a bunch of special case. To make multifunction encoders
557 * work correctly, we need to track this at runtime.*/
561 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
562 * required. This is set in the 2nd loop of calling encoder's
563 * ->compute_config if the first pick doesn't work out.
567 /* Settings for the intel dpll used on pretty much everything but
571 /* Selected dpll when shared or NULL. */
572 struct intel_shared_dpll
*shared_dpll
;
575 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
576 * - enum skl_dpll on SKL
578 uint32_t ddi_pll_sel
;
580 /* Actual register state of the dpll, for shared dpll cross-checking. */
581 struct intel_dpll_hw_state dpll_hw_state
;
583 /* DSI PLL registers */
589 struct intel_link_m_n dp_m_n
;
591 /* m2_n2 for eDP downclock */
592 struct intel_link_m_n dp_m2_n2
;
596 * Frequence the dpll for the port should run at. Differs from the
597 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
598 * already multiplied by pixel_multiplier.
602 /* Used by SDVO (and if we ever fix it, HDMI). */
603 unsigned pixel_multiplier
;
608 * Used by platforms having DP/HDMI PHY with programmable lane
609 * latency optimization.
611 uint8_t lane_lat_optim_mask
;
613 /* Panel fitter controls for gen2-gen4 + VLV */
617 u32 lvds_border_bits
;
620 /* Panel fitter placement and size for Ironlake+ */
628 /* FDI configuration, only valid if has_pch_encoder is set. */
630 struct intel_link_m_n fdi_m_n
;
638 bool dp_encoder_is_mst
;
641 struct intel_crtc_scaler_state scaler_state
;
643 /* w/a for waiting 2 vblanks during crtc enable */
644 enum pipe hsw_workaround_pipe
;
646 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
649 struct intel_crtc_wm_state wm
;
651 /* Gamma mode programmed on the pipe */
655 struct vlv_wm_state
{
656 struct vlv_pipe_wm wm
[3];
657 struct vlv_sr_wm sr
[3];
658 uint8_t num_active_planes
;
665 struct drm_crtc base
;
668 u8 lut_r
[256], lut_g
[256], lut_b
[256];
670 * Whether the crtc and the connected output pipeline is active. Implies
671 * that crtc->enabled is set, i.e. the current mode configuration has
672 * some outputs connected to this crtc.
675 unsigned long enabled_power_domains
;
677 struct intel_overlay
*overlay
;
678 struct intel_flip_work
*flip_work
;
680 atomic_t unpin_work_count
;
682 /* Display surface base address adjustement for pageflips. Note that on
683 * gen4+ this only adjusts up to a tile, offsets within a tile are
684 * handled in the hw itself (with the TILEOFF register). */
689 uint32_t cursor_addr
;
690 uint32_t cursor_cntl
;
691 uint32_t cursor_size
;
692 uint32_t cursor_base
;
694 struct intel_crtc_state
*config
;
696 /* reset counter value when the last flip was submitted */
697 unsigned int reset_counter
;
699 /* Access to these should be protected by dev_priv->irq_lock. */
700 bool cpu_fifo_underrun_disabled
;
701 bool pch_fifo_underrun_disabled
;
703 /* per-pipe watermark state */
705 /* watermarks currently being used */
707 struct intel_pipe_wm ilk
;
708 struct skl_pipe_wm skl
;
711 /* allow CxSR on this pipe */
718 unsigned start_vbl_count
;
719 ktime_t start_vbl_time
;
720 int min_vbl
, max_vbl
;
724 /* scalers available on this crtc */
727 struct vlv_wm_state wm_state
;
730 struct intel_plane_wm_parameters
{
731 uint32_t horiz_pixels
;
732 uint32_t vert_pixels
;
734 * For packed pixel formats:
735 * bytes_per_pixel - holds bytes per pixel
736 * For planar pixel formats:
737 * bytes_per_pixel - holds bytes per pixel for uv-plane
738 * y_bytes_per_pixel - holds bytes per pixel for y-plane
740 uint8_t bytes_per_pixel
;
741 uint8_t y_bytes_per_pixel
;
745 unsigned int rotation
;
750 struct drm_plane base
;
755 uint32_t frontbuffer_bit
;
757 /* Since we need to change the watermarks before/after
758 * enabling/disabling the planes, we need to store the parameters here
759 * as the other pieces of the struct may not reflect the values we want
760 * for the watermark calculations. Currently only Haswell uses this.
762 struct intel_plane_wm_parameters wm
;
765 * NOTE: Do not place new plane state fields here (e.g., when adding
766 * new plane properties). New runtime state should now be placed in
767 * the intel_plane_state structure and accessed via plane_state.
770 void (*update_plane
)(struct drm_plane
*plane
,
771 const struct intel_crtc_state
*crtc_state
,
772 const struct intel_plane_state
*plane_state
);
773 void (*disable_plane
)(struct drm_plane
*plane
,
774 struct drm_crtc
*crtc
);
775 int (*check_plane
)(struct drm_plane
*plane
,
776 struct intel_crtc_state
*crtc_state
,
777 struct intel_plane_state
*state
);
780 struct intel_watermark_params
{
781 unsigned long fifo_size
;
782 unsigned long max_wm
;
783 unsigned long default_wm
;
784 unsigned long guard_size
;
785 unsigned long cacheline_size
;
788 struct cxsr_latency
{
791 unsigned long fsb_freq
;
792 unsigned long mem_freq
;
793 unsigned long display_sr
;
794 unsigned long display_hpll_disable
;
795 unsigned long cursor_sr
;
796 unsigned long cursor_hpll_disable
;
799 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
800 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
801 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
802 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
803 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
804 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
805 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
806 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
807 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
813 enum drm_dp_dual_mode_type type
;
816 bool limited_color_range
;
817 bool color_range_auto
;
820 enum hdmi_force_audio force_audio
;
821 bool rgb_quant_range_selectable
;
822 enum hdmi_picture_aspect aspect_ratio
;
823 struct intel_connector
*attached_connector
;
824 void (*write_infoframe
)(struct drm_encoder
*encoder
,
825 enum hdmi_infoframe_type type
,
826 const void *frame
, ssize_t len
);
827 void (*set_infoframes
)(struct drm_encoder
*encoder
,
829 const struct drm_display_mode
*adjusted_mode
);
830 bool (*infoframe_enabled
)(struct drm_encoder
*encoder
,
831 const struct intel_crtc_state
*pipe_config
);
834 struct intel_dp_mst_encoder
;
835 #define DP_MAX_DOWNSTREAM_PORTS 0x10
839 * When platform provides two set of M_N registers for dp, we can
840 * program them and switch between them incase of DRRS.
841 * But When only one such register is provided, we have to program the
842 * required divider value on that registers itself based on the DRRS state.
844 * M1_N1 : Program dp_m_n on M1_N1 registers
845 * dp_m2_n2 on M2_N2 registers (If supported)
847 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
848 * M2_N2 registers are not supported
852 /* Sets the m1_n1 and m2_n2 */
858 i915_reg_t output_reg
;
859 i915_reg_t aux_ch_ctl_reg
;
860 i915_reg_t aux_ch_data_reg
[5];
868 enum hdmi_force_audio force_audio
;
869 bool limited_color_range
;
870 bool color_range_auto
;
871 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
872 uint8_t psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
873 uint8_t downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
874 uint8_t edp_dpcd
[EDP_DISPLAY_CTL_CAP_SIZE
];
875 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
876 uint8_t num_sink_rates
;
877 int sink_rates
[DP_MAX_SUPPORTED_RATES
];
878 struct drm_dp_aux aux
;
879 uint8_t train_set
[4];
880 int panel_power_up_delay
;
881 int panel_power_down_delay
;
882 int panel_power_cycle_delay
;
883 int backlight_on_delay
;
884 int backlight_off_delay
;
885 struct delayed_work panel_vdd_work
;
887 unsigned long last_power_on
;
888 unsigned long last_backlight_off
;
889 ktime_t panel_power_off_time
;
891 struct notifier_block edp_notifier
;
894 * Pipe whose power sequencer is currently locked into
895 * this port. Only relevant on VLV/CHV.
899 * Set if the sequencer may be reset due to a power transition,
900 * requiring a reinitialization. Only relevant on BXT.
903 struct edp_power_seq pps_delays
;
905 bool can_mst
; /* this port supports mst */
907 int active_mst_links
;
908 /* connector directly attached - won't be use for modeset in mst world */
909 struct intel_connector
*attached_connector
;
911 /* mst connector list */
912 struct intel_dp_mst_encoder
*mst_encoders
[I915_MAX_PIPES
];
913 struct drm_dp_mst_topology_mgr mst_mgr
;
915 uint32_t (*get_aux_clock_divider
)(struct intel_dp
*dp
, int index
);
917 * This function returns the value we have to program the AUX_CTL
918 * register with to kick off an AUX transaction.
920 uint32_t (*get_aux_send_ctl
)(struct intel_dp
*dp
,
923 uint32_t aux_clock_divider
);
925 /* This is called before a link training is starterd */
926 void (*prepare_link_retrain
)(struct intel_dp
*intel_dp
);
928 /* Displayport compliance testing */
929 unsigned long compliance_test_type
;
930 unsigned long compliance_test_data
;
931 bool compliance_test_active
;
934 struct intel_digital_port
{
935 struct intel_encoder base
;
939 struct intel_hdmi hdmi
;
940 enum irqreturn (*hpd_pulse
)(struct intel_digital_port
*, bool);
941 bool release_cl2_override
;
943 /* for communication with audio component; protected by av_mutex */
944 const struct drm_connector
*audio_connector
;
947 struct intel_dp_mst_encoder
{
948 struct intel_encoder base
;
950 struct intel_digital_port
*primary
;
951 struct intel_connector
*connector
;
954 static inline enum dpio_channel
955 vlv_dport_to_channel(struct intel_digital_port
*dport
)
957 switch (dport
->port
) {
968 static inline enum dpio_phy
969 vlv_dport_to_phy(struct intel_digital_port
*dport
)
971 switch (dport
->port
) {
982 static inline enum dpio_channel
983 vlv_pipe_to_channel(enum pipe pipe
)
996 static inline struct drm_crtc
*
997 intel_get_crtc_for_pipe(struct drm_device
*dev
, int pipe
)
999 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1000 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
1003 static inline struct drm_crtc
*
1004 intel_get_crtc_for_plane(struct drm_device
*dev
, int plane
)
1006 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1007 return dev_priv
->plane_to_crtc_mapping
[plane
];
1010 struct intel_flip_work
{
1011 struct work_struct unpin_work
;
1012 struct work_struct mmio_work
;
1014 struct drm_crtc
*crtc
;
1015 struct drm_framebuffer
*old_fb
;
1016 struct drm_i915_gem_object
*pending_flip_obj
;
1017 struct drm_pending_vblank_event
*event
;
1021 struct drm_i915_gem_request
*flip_queued_req
;
1022 u32 flip_queued_vblank
;
1023 u32 flip_ready_vblank
;
1024 unsigned int rotation
;
1027 struct intel_load_detect_pipe
{
1028 struct drm_atomic_state
*restore_state
;
1031 static inline struct intel_encoder
*
1032 intel_attached_encoder(struct drm_connector
*connector
)
1034 return to_intel_connector(connector
)->encoder
;
1037 static inline struct intel_digital_port
*
1038 enc_to_dig_port(struct drm_encoder
*encoder
)
1040 return container_of(encoder
, struct intel_digital_port
, base
.base
);
1043 static inline struct intel_dp_mst_encoder
*
1044 enc_to_mst(struct drm_encoder
*encoder
)
1046 return container_of(encoder
, struct intel_dp_mst_encoder
, base
.base
);
1049 static inline struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
1051 return &enc_to_dig_port(encoder
)->dp
;
1054 static inline struct intel_digital_port
*
1055 dp_to_dig_port(struct intel_dp
*intel_dp
)
1057 return container_of(intel_dp
, struct intel_digital_port
, dp
);
1060 static inline struct intel_digital_port
*
1061 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
1063 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
1067 * Returns the number of planes for this pipe, ie the number of sprites + 1
1068 * (primary plane). This doesn't count the cursor plane then.
1070 static inline unsigned int intel_num_planes(struct intel_crtc
*crtc
)
1072 return INTEL_INFO(crtc
->base
.dev
)->num_sprites
[crtc
->pipe
] + 1;
1075 /* intel_fifo_underrun.c */
1076 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
1077 enum pipe pipe
, bool enable
);
1078 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
1079 enum transcoder pch_transcoder
,
1081 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
1083 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
1084 enum transcoder pch_transcoder
);
1085 void intel_check_cpu_fifo_underruns(struct drm_i915_private
*dev_priv
);
1086 void intel_check_pch_fifo_underruns(struct drm_i915_private
*dev_priv
);
1089 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1090 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1091 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1092 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1093 void gen6_reset_rps_interrupts(struct drm_i915_private
*dev_priv
);
1094 void gen6_enable_rps_interrupts(struct drm_i915_private
*dev_priv
);
1095 void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv
);
1096 u32
gen6_sanitize_rps_pm_mask(struct drm_i915_private
*dev_priv
, u32 mask
);
1097 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
);
1098 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
);
1099 static inline bool intel_irqs_enabled(struct drm_i915_private
*dev_priv
)
1102 * We only use drm_irq_uninstall() at unload and VT switch, so
1103 * this is the only thing we need to check.
1105 return dev_priv
->pm
.irqs_enabled
;
1108 int intel_get_crtc_scanline(struct intel_crtc
*crtc
);
1109 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
1110 unsigned int pipe_mask
);
1111 void gen8_irq_power_well_pre_disable(struct drm_i915_private
*dev_priv
,
1112 unsigned int pipe_mask
);
1115 void intel_crt_init(struct drm_device
*dev
);
1116 void intel_crt_reset(struct drm_encoder
*encoder
);
1119 void intel_ddi_clk_select(struct intel_encoder
*encoder
,
1120 const struct intel_crtc_state
*pipe_config
);
1121 void intel_prepare_dp_ddi_buffers(struct intel_encoder
*encoder
);
1122 void hsw_fdi_link_train(struct drm_crtc
*crtc
);
1123 void intel_ddi_init(struct drm_device
*dev
, enum port port
);
1124 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
);
1125 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
, enum pipe
*pipe
);
1126 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
);
1127 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1128 enum transcoder cpu_transcoder
);
1129 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
);
1130 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
);
1131 bool intel_ddi_pll_select(struct intel_crtc
*crtc
,
1132 struct intel_crtc_state
*crtc_state
);
1133 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
);
1134 void intel_ddi_prepare_link_retrain(struct intel_dp
*intel_dp
);
1135 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
);
1136 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
);
1137 void intel_ddi_get_config(struct intel_encoder
*encoder
,
1138 struct intel_crtc_state
*pipe_config
);
1139 struct intel_encoder
*
1140 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state
*crtc_state
);
1142 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
);
1143 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
1144 struct intel_crtc_state
*pipe_config
);
1145 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
);
1146 uint32_t ddi_signal_levels(struct intel_dp
*intel_dp
);
1148 unsigned int intel_fb_align_height(struct drm_device
*dev
,
1149 unsigned int height
,
1150 uint32_t pixel_format
,
1151 uint64_t fb_format_modifier
);
1152 u32
intel_fb_stride_alignment(const struct drm_i915_private
*dev_priv
,
1153 uint64_t fb_modifier
, uint32_t pixel_format
);
1156 void intel_init_audio_hooks(struct drm_i915_private
*dev_priv
);
1157 void intel_audio_codec_enable(struct intel_encoder
*encoder
);
1158 void intel_audio_codec_disable(struct intel_encoder
*encoder
);
1159 void i915_audio_component_init(struct drm_i915_private
*dev_priv
);
1160 void i915_audio_component_cleanup(struct drm_i915_private
*dev_priv
);
1162 /* intel_display.c */
1163 void skl_set_preferred_cdclk_vco(struct drm_i915_private
*dev_priv
, int vco
);
1164 void intel_update_rawclk(struct drm_i915_private
*dev_priv
);
1165 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
1166 const char *name
, u32 reg
, int ref_freq
);
1167 extern const struct drm_plane_funcs intel_plane_funcs
;
1168 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
);
1169 unsigned int intel_fb_xy_to_linear(int x
, int y
,
1170 const struct drm_framebuffer
*fb
, int plane
);
1171 void intel_add_fb_offsets(int *x
, int *y
,
1172 const struct drm_framebuffer
*fb
, int plane
,
1173 unsigned int rotation
);
1174 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
);
1175 bool intel_has_pending_fb_unpin(struct drm_device
*dev
);
1176 void intel_mark_busy(struct drm_i915_private
*dev_priv
);
1177 void intel_mark_idle(struct drm_i915_private
*dev_priv
);
1178 void intel_crtc_restore_mode(struct drm_crtc
*crtc
);
1179 int intel_display_suspend(struct drm_device
*dev
);
1180 void intel_pps_unlock_regs_wa(struct drm_i915_private
*dev_priv
);
1181 void intel_encoder_destroy(struct drm_encoder
*encoder
);
1182 int intel_connector_init(struct intel_connector
*);
1183 struct intel_connector
*intel_connector_alloc(void);
1184 bool intel_connector_get_hw_state(struct intel_connector
*connector
);
1185 void intel_connector_attach_encoder(struct intel_connector
*connector
,
1186 struct intel_encoder
*encoder
);
1187 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
1188 struct drm_crtc
*crtc
);
1189 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
);
1190 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
1191 struct drm_file
*file_priv
);
1192 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1195 intel_crtc_has_type(const struct intel_crtc_state
*crtc_state
,
1196 enum intel_output_type type
)
1198 return crtc_state
->output_types
& (1 << type
);
1201 intel_crtc_has_dp_encoder(const struct intel_crtc_state
*crtc_state
)
1203 return crtc_state
->output_types
&
1204 ((1 << INTEL_OUTPUT_DP
) |
1205 (1 << INTEL_OUTPUT_DP_MST
) |
1206 (1 << INTEL_OUTPUT_EDP
));
1209 intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
1211 drm_wait_one_vblank(dev
, pipe
);
1214 intel_wait_for_vblank_if_active(struct drm_device
*dev
, int pipe
)
1216 const struct intel_crtc
*crtc
=
1217 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
1220 intel_wait_for_vblank(dev
, pipe
);
1223 u32
intel_crtc_get_vblank_counter(struct intel_crtc
*crtc
);
1225 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
);
1226 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1227 struct intel_digital_port
*dport
,
1228 unsigned int expected_mask
);
1229 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
1230 struct drm_display_mode
*mode
,
1231 struct intel_load_detect_pipe
*old
,
1232 struct drm_modeset_acquire_ctx
*ctx
);
1233 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
1234 struct intel_load_detect_pipe
*old
,
1235 struct drm_modeset_acquire_ctx
*ctx
);
1236 int intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
,
1237 unsigned int rotation
);
1238 void intel_unpin_fb_obj(struct drm_framebuffer
*fb
, unsigned int rotation
);
1239 struct drm_framebuffer
*
1240 __intel_framebuffer_create(struct drm_device
*dev
,
1241 struct drm_mode_fb_cmd2
*mode_cmd
,
1242 struct drm_i915_gem_object
*obj
);
1243 void intel_finish_page_flip_cs(struct drm_i915_private
*dev_priv
, int pipe
);
1244 void intel_finish_page_flip_mmio(struct drm_i915_private
*dev_priv
, int pipe
);
1245 void intel_check_page_flip(struct drm_i915_private
*dev_priv
, int pipe
);
1246 int intel_prepare_plane_fb(struct drm_plane
*plane
,
1247 const struct drm_plane_state
*new_state
);
1248 void intel_cleanup_plane_fb(struct drm_plane
*plane
,
1249 const struct drm_plane_state
*old_state
);
1250 int intel_plane_atomic_get_property(struct drm_plane
*plane
,
1251 const struct drm_plane_state
*state
,
1252 struct drm_property
*property
,
1254 int intel_plane_atomic_set_property(struct drm_plane
*plane
,
1255 struct drm_plane_state
*state
,
1256 struct drm_property
*property
,
1258 int intel_plane_atomic_calc_changes(struct drm_crtc_state
*crtc_state
,
1259 struct drm_plane_state
*plane_state
);
1261 unsigned int intel_tile_height(const struct drm_i915_private
*dev_priv
,
1262 uint64_t fb_modifier
, unsigned int cpp
);
1265 intel_rotation_90_or_270(unsigned int rotation
)
1267 return rotation
& (BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
));
1270 void intel_create_rotation_property(struct drm_device
*dev
,
1271 struct intel_plane
*plane
);
1273 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1276 int vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
1277 const struct dpll
*dpll
);
1278 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
);
1279 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
);
1281 /* modesetting asserts */
1282 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1284 void assert_pll(struct drm_i915_private
*dev_priv
,
1285 enum pipe pipe
, bool state
);
1286 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1287 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1288 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
);
1289 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1290 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1291 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1292 enum pipe pipe
, bool state
);
1293 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1294 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1295 void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool state
);
1296 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1297 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1298 u32
intel_compute_tile_offset(int *x
, int *y
,
1299 const struct drm_framebuffer
*fb
, int plane
,
1300 unsigned int rotation
);
1301 void intel_prepare_reset(struct drm_i915_private
*dev_priv
);
1302 void intel_finish_reset(struct drm_i915_private
*dev_priv
);
1303 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
);
1304 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
);
1305 void bxt_init_cdclk(struct drm_i915_private
*dev_priv
);
1306 void bxt_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1307 void bxt_ddi_phy_init(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
1308 void bxt_ddi_phy_uninit(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
1309 bool bxt_ddi_phy_is_enabled(struct drm_i915_private
*dev_priv
,
1311 bool bxt_ddi_phy_verify_state(struct drm_i915_private
*dev_priv
,
1313 void gen9_sanitize_dc_state(struct drm_i915_private
*dev_priv
);
1314 void bxt_enable_dc9(struct drm_i915_private
*dev_priv
);
1315 void bxt_disable_dc9(struct drm_i915_private
*dev_priv
);
1316 void gen9_enable_dc5(struct drm_i915_private
*dev_priv
);
1317 void skl_init_cdclk(struct drm_i915_private
*dev_priv
);
1318 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1319 unsigned int skl_cdclk_get_vco(unsigned int freq
);
1320 void skl_enable_dc6(struct drm_i915_private
*dev_priv
);
1321 void skl_disable_dc6(struct drm_i915_private
*dev_priv
);
1322 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
1323 struct intel_crtc_state
*pipe_config
);
1324 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
);
1325 int intel_dotclock_calculate(int link_freq
, const struct intel_link_m_n
*m_n
);
1326 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
1327 struct dpll
*best_clock
);
1328 int chv_calc_dpll_params(int refclk
, struct dpll
*pll_clock
);
1330 bool intel_crtc_active(struct drm_crtc
*crtc
);
1331 void hsw_enable_ips(struct intel_crtc
*crtc
);
1332 void hsw_disable_ips(struct intel_crtc
*crtc
);
1333 enum intel_display_power_domain
1334 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
);
1335 enum intel_display_power_domain
1336 intel_display_port_aux_power_domain(struct intel_encoder
*intel_encoder
);
1337 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
1338 struct intel_crtc_state
*pipe_config
);
1340 int skl_update_scaler_crtc(struct intel_crtc_state
*crtc_state
);
1341 int skl_max_scale(struct intel_crtc
*crtc
, struct intel_crtc_state
*crtc_state
);
1343 u32
intel_fb_gtt_offset(struct drm_framebuffer
*fb
, unsigned int rotation
);
1345 u32
skl_plane_ctl_format(uint32_t pixel_format
);
1346 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
);
1347 u32
skl_plane_ctl_rotation(unsigned int rotation
);
1350 void intel_csr_ucode_init(struct drm_i915_private
*);
1351 void intel_csr_load_program(struct drm_i915_private
*);
1352 void intel_csr_ucode_fini(struct drm_i915_private
*);
1353 void intel_csr_ucode_suspend(struct drm_i915_private
*);
1354 void intel_csr_ucode_resume(struct drm_i915_private
*);
1357 bool intel_dp_init(struct drm_device
*dev
, i915_reg_t output_reg
, enum port port
);
1358 bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
1359 struct intel_connector
*intel_connector
);
1360 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1361 const struct intel_crtc_state
*pipe_config
);
1362 void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
1363 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
);
1364 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
1365 void intel_dp_encoder_reset(struct drm_encoder
*encoder
);
1366 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
);
1367 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
);
1368 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
);
1369 bool intel_dp_compute_config(struct intel_encoder
*encoder
,
1370 struct intel_crtc_state
*pipe_config
);
1371 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
);
1372 enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
,
1374 void intel_edp_backlight_on(struct intel_dp
*intel_dp
);
1375 void intel_edp_backlight_off(struct intel_dp
*intel_dp
);
1376 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
1377 void intel_edp_panel_on(struct intel_dp
*intel_dp
);
1378 void intel_edp_panel_off(struct intel_dp
*intel_dp
);
1379 void intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
);
1380 void intel_dp_mst_suspend(struct drm_device
*dev
);
1381 void intel_dp_mst_resume(struct drm_device
*dev
);
1382 int intel_dp_max_link_rate(struct intel_dp
*intel_dp
);
1383 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
);
1384 void intel_dp_hot_plug(struct intel_encoder
*intel_encoder
);
1385 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
);
1386 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
);
1387 void intel_plane_destroy(struct drm_plane
*plane
);
1388 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
);
1389 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
);
1390 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
1391 unsigned int frontbuffer_bits
);
1392 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
1393 unsigned int frontbuffer_bits
);
1394 bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
1395 struct intel_digital_port
*port
);
1398 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
1399 uint8_t dp_train_pat
);
1401 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
);
1402 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
);
1404 intel_dp_voltage_max(struct intel_dp
*intel_dp
);
1406 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
);
1407 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1408 uint8_t *link_bw
, uint8_t *rate_select
);
1409 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
);
1411 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
]);
1413 static inline unsigned int intel_dp_unused_lane_mask(int lane_count
)
1415 return ~((1 << lane_count
) - 1) & 0xf;
1418 /* intel_dp_aux_backlight.c */
1419 int intel_dp_aux_init_backlight_funcs(struct intel_connector
*intel_connector
);
1421 /* intel_dp_mst.c */
1422 int intel_dp_mst_encoder_init(struct intel_digital_port
*intel_dig_port
, int conn_id
);
1423 void intel_dp_mst_encoder_cleanup(struct intel_digital_port
*intel_dig_port
);
1425 void intel_dsi_init(struct drm_device
*dev
);
1427 /* intel_dsi_dcs_backlight.c */
1428 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector
*intel_connector
);
1431 void intel_dvo_init(struct drm_device
*dev
);
1432 /* intel_hotplug.c */
1433 void intel_hpd_poll_init(struct drm_i915_private
*dev_priv
);
1436 /* legacy fbdev emulation in intel_fbdev.c */
1437 #ifdef CONFIG_DRM_FBDEV_EMULATION
1438 extern int intel_fbdev_init(struct drm_device
*dev
);
1439 extern void intel_fbdev_initial_config_async(struct drm_device
*dev
);
1440 extern void intel_fbdev_fini(struct drm_device
*dev
);
1441 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
);
1442 extern void intel_fbdev_output_poll_changed(struct drm_device
*dev
);
1443 extern void intel_fbdev_restore_mode(struct drm_device
*dev
);
1445 static inline int intel_fbdev_init(struct drm_device
*dev
)
1450 static inline void intel_fbdev_initial_config_async(struct drm_device
*dev
)
1454 static inline void intel_fbdev_fini(struct drm_device
*dev
)
1458 static inline void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
)
1462 static inline void intel_fbdev_restore_mode(struct drm_device
*dev
)
1468 void intel_fbc_choose_crtc(struct drm_i915_private
*dev_priv
,
1469 struct drm_atomic_state
*state
);
1470 bool intel_fbc_is_active(struct drm_i915_private
*dev_priv
);
1471 void intel_fbc_pre_update(struct intel_crtc
*crtc
,
1472 struct intel_crtc_state
*crtc_state
,
1473 struct intel_plane_state
*plane_state
);
1474 void intel_fbc_post_update(struct intel_crtc
*crtc
);
1475 void intel_fbc_init(struct drm_i915_private
*dev_priv
);
1476 void intel_fbc_init_pipe_state(struct drm_i915_private
*dev_priv
);
1477 void intel_fbc_enable(struct intel_crtc
*crtc
,
1478 struct intel_crtc_state
*crtc_state
,
1479 struct intel_plane_state
*plane_state
);
1480 void intel_fbc_disable(struct intel_crtc
*crtc
);
1481 void intel_fbc_global_disable(struct drm_i915_private
*dev_priv
);
1482 void intel_fbc_invalidate(struct drm_i915_private
*dev_priv
,
1483 unsigned int frontbuffer_bits
,
1484 enum fb_op_origin origin
);
1485 void intel_fbc_flush(struct drm_i915_private
*dev_priv
,
1486 unsigned int frontbuffer_bits
, enum fb_op_origin origin
);
1487 void intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
);
1490 void intel_hdmi_init(struct drm_device
*dev
, i915_reg_t hdmi_reg
, enum port port
);
1491 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
1492 struct intel_connector
*intel_connector
);
1493 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
);
1494 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
1495 struct intel_crtc_state
*pipe_config
);
1496 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi
*hdmi
, bool enable
);
1500 void intel_lvds_init(struct drm_device
*dev
);
1501 struct intel_encoder
*intel_get_lvds_encoder(struct drm_device
*dev
);
1502 bool intel_is_dual_link_lvds(struct drm_device
*dev
);
1506 int intel_connector_update_modes(struct drm_connector
*connector
,
1508 int intel_ddc_get_modes(struct drm_connector
*c
, struct i2c_adapter
*adapter
);
1509 void intel_attach_force_audio_property(struct drm_connector
*connector
);
1510 void intel_attach_broadcast_rgb_property(struct drm_connector
*connector
);
1511 void intel_attach_aspect_ratio_property(struct drm_connector
*connector
);
1514 /* intel_overlay.c */
1515 void intel_setup_overlay(struct drm_i915_private
*dev_priv
);
1516 void intel_cleanup_overlay(struct drm_i915_private
*dev_priv
);
1517 int intel_overlay_switch_off(struct intel_overlay
*overlay
);
1518 int intel_overlay_put_image_ioctl(struct drm_device
*dev
, void *data
,
1519 struct drm_file
*file_priv
);
1520 int intel_overlay_attrs_ioctl(struct drm_device
*dev
, void *data
,
1521 struct drm_file
*file_priv
);
1522 void intel_overlay_reset(struct drm_i915_private
*dev_priv
);
1526 int intel_panel_init(struct intel_panel
*panel
,
1527 struct drm_display_mode
*fixed_mode
,
1528 struct drm_display_mode
*downclock_mode
);
1529 void intel_panel_fini(struct intel_panel
*panel
);
1530 void intel_fixed_panel_mode(const struct drm_display_mode
*fixed_mode
,
1531 struct drm_display_mode
*adjusted_mode
);
1532 void intel_pch_panel_fitting(struct intel_crtc
*crtc
,
1533 struct intel_crtc_state
*pipe_config
,
1535 void intel_gmch_panel_fitting(struct intel_crtc
*crtc
,
1536 struct intel_crtc_state
*pipe_config
,
1538 void intel_panel_set_backlight_acpi(struct intel_connector
*connector
,
1539 u32 level
, u32 max
);
1540 int intel_panel_setup_backlight(struct drm_connector
*connector
,
1542 void intel_panel_enable_backlight(struct intel_connector
*connector
);
1543 void intel_panel_disable_backlight(struct intel_connector
*connector
);
1544 void intel_panel_destroy_backlight(struct drm_connector
*connector
);
1545 enum drm_connector_status
intel_panel_detect(struct drm_device
*dev
);
1546 extern struct drm_display_mode
*intel_find_panel_downclock(
1547 struct drm_device
*dev
,
1548 struct drm_display_mode
*fixed_mode
,
1549 struct drm_connector
*connector
);
1551 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1552 int intel_backlight_device_register(struct intel_connector
*connector
);
1553 void intel_backlight_device_unregister(struct intel_connector
*connector
);
1554 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1555 static int intel_backlight_device_register(struct intel_connector
*connector
)
1559 static inline void intel_backlight_device_unregister(struct intel_connector
*connector
)
1562 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1566 void intel_psr_enable(struct intel_dp
*intel_dp
);
1567 void intel_psr_disable(struct intel_dp
*intel_dp
);
1568 void intel_psr_invalidate(struct drm_i915_private
*dev_priv
,
1569 unsigned frontbuffer_bits
);
1570 void intel_psr_flush(struct drm_i915_private
*dev_priv
,
1571 unsigned frontbuffer_bits
,
1572 enum fb_op_origin origin
);
1573 void intel_psr_init(struct drm_device
*dev
);
1574 void intel_psr_single_frame_update(struct drm_i915_private
*dev_priv
,
1575 unsigned frontbuffer_bits
);
1577 /* intel_runtime_pm.c */
1578 int intel_power_domains_init(struct drm_i915_private
*);
1579 void intel_power_domains_fini(struct drm_i915_private
*);
1580 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
, bool resume
);
1581 void intel_power_domains_suspend(struct drm_i915_private
*dev_priv
);
1582 void bxt_display_core_init(struct drm_i915_private
*dev_priv
, bool resume
);
1583 void bxt_display_core_uninit(struct drm_i915_private
*dev_priv
);
1584 void intel_runtime_pm_enable(struct drm_i915_private
*dev_priv
);
1586 intel_display_power_domain_str(enum intel_display_power_domain domain
);
1588 bool intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1589 enum intel_display_power_domain domain
);
1590 bool __intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1591 enum intel_display_power_domain domain
);
1592 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
1593 enum intel_display_power_domain domain
);
1594 bool intel_display_power_get_if_enabled(struct drm_i915_private
*dev_priv
,
1595 enum intel_display_power_domain domain
);
1596 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
1597 enum intel_display_power_domain domain
);
1600 assert_rpm_device_not_suspended(struct drm_i915_private
*dev_priv
)
1602 WARN_ONCE(dev_priv
->pm
.suspended
,
1603 "Device suspended during HW access\n");
1607 assert_rpm_wakelock_held(struct drm_i915_private
*dev_priv
)
1609 assert_rpm_device_not_suspended(dev_priv
);
1610 /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1611 * too much noise. */
1612 if (!atomic_read(&dev_priv
->pm
.wakeref_count
))
1613 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1617 assert_rpm_atomic_begin(struct drm_i915_private
*dev_priv
)
1619 int seq
= atomic_read(&dev_priv
->pm
.atomic_seq
);
1621 assert_rpm_wakelock_held(dev_priv
);
1627 assert_rpm_atomic_end(struct drm_i915_private
*dev_priv
, int begin_seq
)
1629 WARN_ONCE(atomic_read(&dev_priv
->pm
.atomic_seq
) != begin_seq
,
1630 "HW access outside of RPM atomic section\n");
1634 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1635 * @dev_priv: i915 device instance
1637 * This function disable asserts that check if we hold an RPM wakelock
1638 * reference, while keeping the device-not-suspended checks still enabled.
1639 * It's meant to be used only in special circumstances where our rule about
1640 * the wakelock refcount wrt. the device power state doesn't hold. According
1641 * to this rule at any point where we access the HW or want to keep the HW in
1642 * an active state we must hold an RPM wakelock reference acquired via one of
1643 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1644 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1645 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1646 * users should avoid using this function.
1648 * Any calls to this function must have a symmetric call to
1649 * enable_rpm_wakeref_asserts().
1652 disable_rpm_wakeref_asserts(struct drm_i915_private
*dev_priv
)
1654 atomic_inc(&dev_priv
->pm
.wakeref_count
);
1658 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1659 * @dev_priv: i915 device instance
1661 * This function re-enables the RPM assert checks after disabling them with
1662 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1663 * circumstances otherwise its use should be avoided.
1665 * Any calls to this function must have a symmetric call to
1666 * disable_rpm_wakeref_asserts().
1669 enable_rpm_wakeref_asserts(struct drm_i915_private
*dev_priv
)
1671 atomic_dec(&dev_priv
->pm
.wakeref_count
);
1674 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
);
1675 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private
*dev_priv
);
1676 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
);
1677 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
);
1679 void intel_display_set_init_power(struct drm_i915_private
*dev
, bool enable
);
1681 void chv_phy_powergate_lanes(struct intel_encoder
*encoder
,
1682 bool override
, unsigned int mask
);
1683 bool chv_phy_powergate_ch(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
,
1684 enum dpio_channel ch
, bool override
);
1688 void intel_init_clock_gating(struct drm_device
*dev
);
1689 void intel_suspend_hw(struct drm_device
*dev
);
1690 int ilk_wm_max_level(const struct drm_device
*dev
);
1691 void intel_update_watermarks(struct drm_crtc
*crtc
);
1692 void intel_init_pm(struct drm_device
*dev
);
1693 void intel_init_clock_gating_hooks(struct drm_i915_private
*dev_priv
);
1694 void intel_pm_setup(struct drm_device
*dev
);
1695 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
1696 void intel_gpu_ips_teardown(void);
1697 void intel_init_gt_powersave(struct drm_i915_private
*dev_priv
);
1698 void intel_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
);
1699 void intel_sanitize_gt_powersave(struct drm_i915_private
*dev_priv
);
1700 void intel_enable_gt_powersave(struct drm_i915_private
*dev_priv
);
1701 void intel_autoenable_gt_powersave(struct drm_i915_private
*dev_priv
);
1702 void intel_disable_gt_powersave(struct drm_i915_private
*dev_priv
);
1703 void intel_suspend_gt_powersave(struct drm_i915_private
*dev_priv
);
1704 void gen6_rps_busy(struct drm_i915_private
*dev_priv
);
1705 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
);
1706 void gen6_rps_idle(struct drm_i915_private
*dev_priv
);
1707 void gen6_rps_boost(struct drm_i915_private
*dev_priv
,
1708 struct intel_rps_client
*rps
,
1709 unsigned long submitted
);
1710 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request
*req
);
1711 void vlv_wm_get_hw_state(struct drm_device
*dev
);
1712 void ilk_wm_get_hw_state(struct drm_device
*dev
);
1713 void skl_wm_get_hw_state(struct drm_device
*dev
);
1714 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
1715 struct skl_ddb_allocation
*ddb
/* out */);
1716 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
*pipe_config
);
1717 bool ilk_disable_lp_wm(struct drm_device
*dev
);
1718 int sanitize_rc6_option(struct drm_i915_private
*dev_priv
, int enable_rc6
);
1719 static inline int intel_enable_rc6(void)
1721 return i915
.enable_rc6
;
1725 bool intel_sdvo_init(struct drm_device
*dev
,
1726 i915_reg_t reg
, enum port port
);
1729 /* intel_sprite.c */
1730 int intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
);
1731 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
1732 struct drm_file
*file_priv
);
1733 void intel_pipe_update_start(struct intel_crtc
*crtc
);
1734 void intel_pipe_update_end(struct intel_crtc
*crtc
, struct intel_flip_work
*work
);
1737 void intel_tv_init(struct drm_device
*dev
);
1739 /* intel_atomic.c */
1740 int intel_connector_atomic_get_property(struct drm_connector
*connector
,
1741 const struct drm_connector_state
*state
,
1742 struct drm_property
*property
,
1744 struct drm_crtc_state
*intel_crtc_duplicate_state(struct drm_crtc
*crtc
);
1745 void intel_crtc_destroy_state(struct drm_crtc
*crtc
,
1746 struct drm_crtc_state
*state
);
1747 struct drm_atomic_state
*intel_atomic_state_alloc(struct drm_device
*dev
);
1748 void intel_atomic_state_clear(struct drm_atomic_state
*);
1749 struct intel_shared_dpll_config
*
1750 intel_atomic_get_shared_dpll_state(struct drm_atomic_state
*s
);
1752 static inline struct intel_crtc_state
*
1753 intel_atomic_get_crtc_state(struct drm_atomic_state
*state
,
1754 struct intel_crtc
*crtc
)
1756 struct drm_crtc_state
*crtc_state
;
1757 crtc_state
= drm_atomic_get_crtc_state(state
, &crtc
->base
);
1758 if (IS_ERR(crtc_state
))
1759 return ERR_CAST(crtc_state
);
1761 return to_intel_crtc_state(crtc_state
);
1764 static inline struct intel_plane_state
*
1765 intel_atomic_get_existing_plane_state(struct drm_atomic_state
*state
,
1766 struct intel_plane
*plane
)
1768 struct drm_plane_state
*plane_state
;
1770 plane_state
= drm_atomic_get_existing_plane_state(state
, &plane
->base
);
1772 return to_intel_plane_state(plane_state
);
1775 int intel_atomic_setup_scalers(struct drm_device
*dev
,
1776 struct intel_crtc
*intel_crtc
,
1777 struct intel_crtc_state
*crtc_state
);
1779 /* intel_atomic_plane.c */
1780 struct intel_plane_state
*intel_create_plane_state(struct drm_plane
*plane
);
1781 struct drm_plane_state
*intel_plane_duplicate_state(struct drm_plane
*plane
);
1782 void intel_plane_destroy_state(struct drm_plane
*plane
,
1783 struct drm_plane_state
*state
);
1784 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs
;
1787 void intel_color_init(struct drm_crtc
*crtc
);
1788 int intel_color_check(struct drm_crtc
*crtc
, struct drm_crtc_state
*state
);
1789 void intel_color_set_csc(struct drm_crtc_state
*crtc_state
);
1790 void intel_color_load_luts(struct drm_crtc_state
*crtc_state
);
1792 #endif /* __INTEL_DRV_H__ */