2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_dual_mode_helper.h>
37 #include <drm/drm_dp_mst_helper.h>
38 #include <drm/drm_rect.h>
39 #include <drm/drm_atomic.h>
42 * _wait_for - magic (register) wait macro
44 * Does the right thing for modeset paths when run under kdgb or similar atomic
45 * contexts. Note that it's important that we check the condition again after
46 * having timed out, since the timeout could be due to preemption or similar and
47 * we've never had a chance to check the condition before the timeout.
49 * TODO: When modesetting has fully transitioned to atomic, the below
50 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
53 #define _wait_for(COND, US, W) ({ \
54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
57 bool expired__ = time_after(jiffies, timeout__); \
66 if ((W) && drm_can_sleep()) { \
67 usleep_range((W), (W)*2); \
75 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
77 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
78 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
79 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
84 #define _wait_for_atomic(COND, US, ATOMIC) \
86 int cpu, ret, timeout = (US) * 1000; \
88 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
89 BUILD_BUG_ON((US) > 50000); \
92 cpu = smp_processor_id(); \
94 base = local_clock(); \
96 u64 now = local_clock(); \
103 if (now - base >= timeout) { \
110 if (unlikely(cpu != smp_processor_id())) { \
111 timeout -= now - base; \
112 cpu = smp_processor_id(); \
113 base = local_clock(); \
120 #define wait_for_us(COND, US) \
123 BUILD_BUG_ON(!__builtin_constant_p(US)); \
125 ret__ = _wait_for((COND), (US), 10); \
127 ret__ = _wait_for_atomic((COND), (US), 0); \
131 #define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000, 1)
132 #define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US), 1)
134 #define KHz(x) (1000 * (x))
135 #define MHz(x) KHz(1000 * (x))
138 * Display related stuff
141 /* store information about an Ixxx DVO */
142 /* The i830->i865 use multiple DVOs with multiple i2cs */
143 /* the i915, i945 have a single sDVO i2c bus - which is different */
144 #define MAX_OUTPUTS 6
145 /* maximum connectors per crtcs in the mode set */
147 /* Maximum cursor sizes */
148 #define GEN2_CURSOR_WIDTH 64
149 #define GEN2_CURSOR_HEIGHT 64
150 #define MAX_CURSOR_WIDTH 256
151 #define MAX_CURSOR_HEIGHT 256
153 #define INTEL_I2C_BUS_DVO 1
154 #define INTEL_I2C_BUS_SDVO 2
156 /* these are outputs from the chip - integrated only
157 external chips are via DVO or SDVO output */
158 enum intel_output_type
{
159 INTEL_OUTPUT_UNUSED
= 0,
160 INTEL_OUTPUT_ANALOG
= 1,
161 INTEL_OUTPUT_DVO
= 2,
162 INTEL_OUTPUT_SDVO
= 3,
163 INTEL_OUTPUT_LVDS
= 4,
164 INTEL_OUTPUT_TVOUT
= 5,
165 INTEL_OUTPUT_HDMI
= 6,
167 INTEL_OUTPUT_EDP
= 8,
168 INTEL_OUTPUT_DSI
= 9,
169 INTEL_OUTPUT_UNKNOWN
= 10,
170 INTEL_OUTPUT_DP_MST
= 11,
173 #define INTEL_DVO_CHIP_NONE 0
174 #define INTEL_DVO_CHIP_LVDS 1
175 #define INTEL_DVO_CHIP_TMDS 2
176 #define INTEL_DVO_CHIP_TVOUT 4
178 #define INTEL_DSI_VIDEO_MODE 0
179 #define INTEL_DSI_COMMAND_MODE 1
181 struct intel_framebuffer
{
182 struct drm_framebuffer base
;
183 struct drm_i915_gem_object
*obj
;
184 struct intel_rotation_info rot_info
;
186 /* for each plane in the normal GTT view */
190 /* for each plane in the rotated GTT view */
193 unsigned int pitch
; /* pixels */
198 struct drm_fb_helper helper
;
199 struct intel_framebuffer
*fb
;
200 struct i915_vma
*vma
;
201 async_cookie_t cookie
;
205 struct intel_encoder
{
206 struct drm_encoder base
;
208 enum intel_output_type type
;
210 unsigned int cloneable
;
211 void (*hot_plug
)(struct intel_encoder
*);
212 bool (*compute_config
)(struct intel_encoder
*,
213 struct intel_crtc_state
*,
214 struct drm_connector_state
*);
215 void (*pre_pll_enable
)(struct intel_encoder
*,
216 struct intel_crtc_state
*,
217 struct drm_connector_state
*);
218 void (*pre_enable
)(struct intel_encoder
*,
219 struct intel_crtc_state
*,
220 struct drm_connector_state
*);
221 void (*enable
)(struct intel_encoder
*,
222 struct intel_crtc_state
*,
223 struct drm_connector_state
*);
224 void (*disable
)(struct intel_encoder
*,
225 struct intel_crtc_state
*,
226 struct drm_connector_state
*);
227 void (*post_disable
)(struct intel_encoder
*,
228 struct intel_crtc_state
*,
229 struct drm_connector_state
*);
230 void (*post_pll_disable
)(struct intel_encoder
*,
231 struct intel_crtc_state
*,
232 struct drm_connector_state
*);
233 /* Read out the current hw state of this connector, returning true if
234 * the encoder is active. If the encoder is enabled it also set the pipe
235 * it is connected to in the pipe parameter. */
236 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
237 /* Reconstructs the equivalent mode flags for the current hardware
238 * state. This must be called _after_ display->get_pipe_config has
239 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
240 * be set correctly before calling this function. */
241 void (*get_config
)(struct intel_encoder
*,
242 struct intel_crtc_state
*pipe_config
);
244 * Called during system suspend after all pending requests for the
245 * encoder are flushed (for example for DP AUX transactions) and
246 * device interrupts are disabled.
248 void (*suspend
)(struct intel_encoder
*);
250 enum hpd_pin hpd_pin
;
251 /* for communication with audio component; protected by av_mutex */
252 const struct drm_connector
*audio_connector
;
256 struct drm_display_mode
*fixed_mode
;
257 struct drm_display_mode
*downclock_mode
;
267 bool combination_mode
; /* gen 2/4 only */
269 bool alternate_pwm_increment
; /* lpt+ */
272 bool util_pin_active_low
; /* bxt+ */
273 u8 controller
; /* bxt+ only */
274 struct pwm_device
*pwm
;
276 struct backlight_device
*device
;
278 /* Connector and platform specific backlight functions */
279 int (*setup
)(struct intel_connector
*connector
, enum pipe pipe
);
280 uint32_t (*get
)(struct intel_connector
*connector
);
281 void (*set
)(struct intel_connector
*connector
, uint32_t level
);
282 void (*disable
)(struct intel_connector
*connector
);
283 void (*enable
)(struct intel_connector
*connector
);
284 uint32_t (*hz_to_pwm
)(struct intel_connector
*connector
,
286 void (*power
)(struct intel_connector
*, bool enable
);
290 struct intel_connector
{
291 struct drm_connector base
;
293 * The fixed encoder this connector is connected to.
295 struct intel_encoder
*encoder
;
297 /* ACPI device id for ACPI and driver cooperation */
300 /* Reads out the current hw, returning true if the connector is enabled
301 * and active (i.e. dpms ON state). */
302 bool (*get_hw_state
)(struct intel_connector
*);
304 /* Panel info for eDP and LVDS */
305 struct intel_panel panel
;
307 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
309 struct edid
*detect_edid
;
311 /* since POLL and HPD connectors may use the same HPD line keep the native
312 state of connector->polled in case hotplug storm detection changes it */
315 void *port
; /* store this opaque as its illegal to dereference it */
317 struct intel_dp
*mst_port
;
332 struct intel_atomic_state
{
333 struct drm_atomic_state base
;
338 * Calculated device cdclk, can be different from cdclk
339 * only when all crtc's are DPMS off.
341 unsigned int dev_cdclk
;
343 bool dpll_set
, modeset
;
346 * Does this transaction change the pipes that are active? This mask
347 * tracks which CRTC's have changed their active state at the end of
348 * the transaction (not counting the temporary disable during modesets).
349 * This mask should only be non-zero when intel_state->modeset is true,
350 * but the converse is not necessarily true; simply changing a mode may
351 * not flip the final active status of any CRTC's
353 unsigned int active_pipe_changes
;
355 unsigned int active_crtcs
;
356 unsigned int min_pixclk
[I915_MAX_PIPES
];
359 unsigned int cdclk_pll_vco
;
361 struct intel_shared_dpll_config shared_dpll
[I915_NUM_PLLS
];
364 * Current watermarks can't be trusted during hardware readout, so
365 * don't bother calculating intermediate watermarks.
367 bool skip_intermediate_wm
;
370 struct skl_wm_values wm_results
;
372 struct i915_sw_fence commit_ready
;
374 struct llist_node freed
;
377 struct intel_plane_state
{
378 struct drm_plane_state base
;
379 struct drm_rect clip
;
380 struct i915_vma
*vma
;
393 * = -1 : not using a scaler
394 * >= 0 : using a scalers
396 * plane requiring a scaler:
397 * - During check_plane, its bit is set in
398 * crtc_state->scaler_state.scaler_users by calling helper function
399 * update_scaler_plane.
400 * - scaler_id indicates the scaler it got assigned.
402 * plane doesn't require a scaler:
403 * - this can happen when scaling is no more required or plane simply
405 * - During check_plane, corresponding bit is reset in
406 * crtc_state->scaler_state.scaler_users by calling helper function
407 * update_scaler_plane.
411 struct drm_intel_sprite_colorkey ckey
;
414 struct intel_initial_plane_config
{
415 struct intel_framebuffer
*fb
;
421 #define SKL_MIN_SRC_W 8
422 #define SKL_MAX_SRC_W 4096
423 #define SKL_MIN_SRC_H 8
424 #define SKL_MAX_SRC_H 4096
425 #define SKL_MIN_DST_W 8
426 #define SKL_MAX_DST_W 4096
427 #define SKL_MIN_DST_H 8
428 #define SKL_MAX_DST_H 4096
430 struct intel_scaler
{
435 struct intel_crtc_scaler_state
{
436 #define SKL_NUM_SCALERS 2
437 struct intel_scaler scalers
[SKL_NUM_SCALERS
];
440 * scaler_users: keeps track of users requesting scalers on this crtc.
442 * If a bit is set, a user is using a scaler.
443 * Here user can be a plane or crtc as defined below:
444 * bits 0-30 - plane (bit position is index from drm_plane_index)
447 * Instead of creating a new index to cover planes and crtc, using
448 * existing drm_plane_index for planes which is well less than 31
449 * planes and bit 31 for crtc. This should be fine to cover all
452 * intel_atomic_setup_scalers will setup available scalers to users
453 * requesting scalers. It will gracefully fail if request exceeds
456 #define SKL_CRTC_INDEX 31
457 unsigned scaler_users
;
459 /* scaler used by crtc for panel fitting purpose */
463 /* drm_mode->private_flags */
464 #define I915_MODE_FLAG_INHERITED 1
466 struct intel_pipe_wm
{
467 struct intel_wm_level wm
[5];
468 struct intel_wm_level raw_wm
[5];
472 bool sprites_enabled
;
476 struct skl_plane_wm
{
477 struct skl_wm_level wm
[8];
478 struct skl_wm_level trans_wm
;
482 struct skl_plane_wm planes
[I915_MAX_PLANES
];
486 struct intel_crtc_wm_state
{
490 * Intermediate watermarks; these can be
491 * programmed immediately since they satisfy
492 * both the current configuration we're
493 * switching away from and the new
494 * configuration we're switching to.
496 struct intel_pipe_wm intermediate
;
499 * Optimal watermarks, programmed post-vblank
500 * when this state is committed.
502 struct intel_pipe_wm optimal
;
506 /* gen9+ only needs 1-step wm programming */
507 struct skl_pipe_wm optimal
;
508 struct skl_ddb_entry ddb
;
513 * Platforms with two-step watermark programming will need to
514 * update watermark programming post-vblank to switch from the
515 * safe intermediate watermarks to the optimal final
518 bool need_postvbl_update
;
521 struct intel_crtc_state
{
522 struct drm_crtc_state base
;
525 * quirks - bitfield with hw state readout quirks
527 * For various reasons the hw state readout code might not be able to
528 * completely faithfully read out the current state. These cases are
529 * tracked with quirk flags so that fastboot and state checker can act
532 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
533 unsigned long quirks
;
535 unsigned fb_bits
; /* framebuffers to flip */
536 bool update_pipe
; /* can a fast modeset be performed? */
538 bool update_wm_pre
, update_wm_post
; /* watermarks are updated */
539 bool fb_changed
; /* fb on any of the planes is changed */
541 /* Pipe source size (ie. panel fitter input size)
542 * All planes will be positioned inside this space,
543 * and get clipped at the edges. */
544 int pipe_src_w
, pipe_src_h
;
546 /* Whether to set up the PCH/FDI. Note that we never allow sharing
547 * between pch encoders and cpu encoders. */
548 bool has_pch_encoder
;
550 /* Are we sending infoframes on the attached port */
553 /* CPU Transcoder for the pipe. Currently this can only differ from the
554 * pipe on Haswell and later (where we have a special eDP transcoder)
555 * and Broxton (where we have special DSI transcoders). */
556 enum transcoder cpu_transcoder
;
559 * Use reduced/limited/broadcast rbg range, compressing from the full
560 * range fed into the crtcs.
562 bool limited_color_range
;
564 /* Bitmask of encoder types (enum intel_output_type)
565 * driven by the pipe.
567 unsigned int output_types
;
569 /* Whether we should send NULL infoframes. Required for audio. */
572 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
573 * has_dp_encoder is set. */
577 * Enable dithering, used when the selected pipe bpp doesn't match the
582 /* Controls for the clock computation, to override various stages. */
585 /* SDVO TV has a bunch of special case. To make multifunction encoders
586 * work correctly, we need to track this at runtime.*/
590 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
591 * required. This is set in the 2nd loop of calling encoder's
592 * ->compute_config if the first pick doesn't work out.
596 /* Settings for the intel dpll used on pretty much everything but
600 /* Selected dpll when shared or NULL. */
601 struct intel_shared_dpll
*shared_dpll
;
603 /* Actual register state of the dpll, for shared dpll cross-checking. */
604 struct intel_dpll_hw_state dpll_hw_state
;
606 /* DSI PLL registers */
612 struct intel_link_m_n dp_m_n
;
614 /* m2_n2 for eDP downclock */
615 struct intel_link_m_n dp_m2_n2
;
619 * Frequence the dpll for the port should run at. Differs from the
620 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
621 * already multiplied by pixel_multiplier.
625 /* Used by SDVO (and if we ever fix it, HDMI). */
626 unsigned pixel_multiplier
;
631 * Used by platforms having DP/HDMI PHY with programmable lane
632 * latency optimization.
634 uint8_t lane_lat_optim_mask
;
636 /* Panel fitter controls for gen2-gen4 + VLV */
640 u32 lvds_border_bits
;
643 /* Panel fitter placement and size for Ironlake+ */
651 /* FDI configuration, only valid if has_pch_encoder is set. */
653 struct intel_link_m_n fdi_m_n
;
663 struct intel_crtc_scaler_state scaler_state
;
665 /* w/a for waiting 2 vblanks during crtc enable */
666 enum pipe hsw_workaround_pipe
;
668 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
671 struct intel_crtc_wm_state wm
;
673 /* Gamma mode programmed on the pipe */
677 struct vlv_wm_state
{
678 struct vlv_pipe_wm wm
[3];
679 struct vlv_sr_wm sr
[3];
680 uint8_t num_active_planes
;
687 struct drm_crtc base
;
690 u8 lut_r
[256], lut_g
[256], lut_b
[256];
692 * Whether the crtc and the connected output pipeline is active. Implies
693 * that crtc->enabled is set, i.e. the current mode configuration has
694 * some outputs connected to this crtc.
697 unsigned long enabled_power_domains
;
699 struct intel_overlay
*overlay
;
700 struct intel_flip_work
*flip_work
;
702 atomic_t unpin_work_count
;
704 /* Display surface base address adjustement for pageflips. Note that on
705 * gen4+ this only adjusts up to a tile, offsets within a tile are
706 * handled in the hw itself (with the TILEOFF register). */
711 uint32_t cursor_addr
;
712 uint32_t cursor_cntl
;
713 uint32_t cursor_size
;
714 uint32_t cursor_base
;
716 struct intel_crtc_state
*config
;
718 /* global reset count when the last flip was submitted */
719 unsigned int reset_count
;
721 /* Access to these should be protected by dev_priv->irq_lock. */
722 bool cpu_fifo_underrun_disabled
;
723 bool pch_fifo_underrun_disabled
;
725 /* per-pipe watermark state */
727 /* watermarks currently being used */
729 struct intel_pipe_wm ilk
;
732 /* allow CxSR on this pipe */
739 unsigned start_vbl_count
;
740 ktime_t start_vbl_time
;
741 int min_vbl
, max_vbl
;
745 /* scalers available on this crtc */
748 struct vlv_wm_state wm_state
;
751 struct intel_plane_wm_parameters
{
752 uint32_t horiz_pixels
;
753 uint32_t vert_pixels
;
755 * For packed pixel formats:
756 * bytes_per_pixel - holds bytes per pixel
757 * For planar pixel formats:
758 * bytes_per_pixel - holds bytes per pixel for uv-plane
759 * y_bytes_per_pixel - holds bytes per pixel for y-plane
761 uint8_t bytes_per_pixel
;
762 uint8_t y_bytes_per_pixel
;
766 unsigned int rotation
;
771 struct drm_plane base
;
776 uint32_t frontbuffer_bit
;
778 /* Since we need to change the watermarks before/after
779 * enabling/disabling the planes, we need to store the parameters here
780 * as the other pieces of the struct may not reflect the values we want
781 * for the watermark calculations. Currently only Haswell uses this.
783 struct intel_plane_wm_parameters wm
;
786 * NOTE: Do not place new plane state fields here (e.g., when adding
787 * new plane properties). New runtime state should now be placed in
788 * the intel_plane_state structure and accessed via plane_state.
791 void (*update_plane
)(struct drm_plane
*plane
,
792 const struct intel_crtc_state
*crtc_state
,
793 const struct intel_plane_state
*plane_state
);
794 void (*disable_plane
)(struct drm_plane
*plane
,
795 struct drm_crtc
*crtc
);
796 int (*check_plane
)(struct drm_plane
*plane
,
797 struct intel_crtc_state
*crtc_state
,
798 struct intel_plane_state
*state
);
801 struct intel_watermark_params
{
809 struct cxsr_latency
{
815 u16 display_hpll_disable
;
817 u16 cursor_hpll_disable
;
820 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
821 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
822 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
823 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
824 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
825 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
826 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
827 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
828 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
834 enum drm_dp_dual_mode_type type
;
837 bool limited_color_range
;
838 bool color_range_auto
;
841 enum hdmi_force_audio force_audio
;
842 bool rgb_quant_range_selectable
;
843 enum hdmi_picture_aspect aspect_ratio
;
844 struct intel_connector
*attached_connector
;
845 void (*write_infoframe
)(struct drm_encoder
*encoder
,
846 enum hdmi_infoframe_type type
,
847 const void *frame
, ssize_t len
);
848 void (*set_infoframes
)(struct drm_encoder
*encoder
,
850 const struct drm_display_mode
*adjusted_mode
);
851 bool (*infoframe_enabled
)(struct drm_encoder
*encoder
,
852 const struct intel_crtc_state
*pipe_config
);
855 struct intel_dp_mst_encoder
;
856 #define DP_MAX_DOWNSTREAM_PORTS 0x10
860 * When platform provides two set of M_N registers for dp, we can
861 * program them and switch between them incase of DRRS.
862 * But When only one such register is provided, we have to program the
863 * required divider value on that registers itself based on the DRRS state.
865 * M1_N1 : Program dp_m_n on M1_N1 registers
866 * dp_m2_n2 on M2_N2 registers (If supported)
868 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
869 * M2_N2 registers are not supported
873 /* Sets the m1_n1 and m2_n2 */
878 struct intel_dp_desc
{
887 i915_reg_t output_reg
;
888 i915_reg_t aux_ch_ctl_reg
;
889 i915_reg_t aux_ch_data_reg
[5];
897 bool channel_eq_status
;
898 enum hdmi_force_audio force_audio
;
899 bool limited_color_range
;
900 bool color_range_auto
;
901 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
902 uint8_t psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
903 uint8_t downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
904 uint8_t edp_dpcd
[EDP_DISPLAY_CTL_CAP_SIZE
];
905 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
906 uint8_t num_sink_rates
;
907 int sink_rates
[DP_MAX_SUPPORTED_RATES
];
908 /* sink or branch descriptor */
909 struct intel_dp_desc desc
;
910 struct drm_dp_aux aux
;
911 uint8_t train_set
[4];
912 int panel_power_up_delay
;
913 int panel_power_down_delay
;
914 int panel_power_cycle_delay
;
915 int backlight_on_delay
;
916 int backlight_off_delay
;
917 struct delayed_work panel_vdd_work
;
919 unsigned long last_power_on
;
920 unsigned long last_backlight_off
;
921 ktime_t panel_power_off_time
;
923 struct notifier_block edp_notifier
;
926 * Pipe whose power sequencer is currently locked into
927 * this port. Only relevant on VLV/CHV.
931 * Set if the sequencer may be reset due to a power transition,
932 * requiring a reinitialization. Only relevant on BXT.
935 struct edp_power_seq pps_delays
;
937 bool can_mst
; /* this port supports mst */
939 int active_mst_links
;
940 /* connector directly attached - won't be use for modeset in mst world */
941 struct intel_connector
*attached_connector
;
943 /* mst connector list */
944 struct intel_dp_mst_encoder
*mst_encoders
[I915_MAX_PIPES
];
945 struct drm_dp_mst_topology_mgr mst_mgr
;
947 uint32_t (*get_aux_clock_divider
)(struct intel_dp
*dp
, int index
);
949 * This function returns the value we have to program the AUX_CTL
950 * register with to kick off an AUX transaction.
952 uint32_t (*get_aux_send_ctl
)(struct intel_dp
*dp
,
955 uint32_t aux_clock_divider
);
957 /* This is called before a link training is starterd */
958 void (*prepare_link_retrain
)(struct intel_dp
*intel_dp
);
960 /* Displayport compliance testing */
961 unsigned long compliance_test_type
;
962 unsigned long compliance_test_data
;
963 bool compliance_test_active
;
966 struct intel_lspcon
{
968 enum drm_lspcon_mode mode
;
972 struct intel_digital_port
{
973 struct intel_encoder base
;
977 struct intel_hdmi hdmi
;
978 struct intel_lspcon lspcon
;
979 enum irqreturn (*hpd_pulse
)(struct intel_digital_port
*, bool);
980 bool release_cl2_override
;
984 struct intel_dp_mst_encoder
{
985 struct intel_encoder base
;
987 struct intel_digital_port
*primary
;
988 struct intel_connector
*connector
;
991 static inline enum dpio_channel
992 vlv_dport_to_channel(struct intel_digital_port
*dport
)
994 switch (dport
->port
) {
1005 static inline enum dpio_phy
1006 vlv_dport_to_phy(struct intel_digital_port
*dport
)
1008 switch (dport
->port
) {
1019 static inline enum dpio_channel
1020 vlv_pipe_to_channel(enum pipe pipe
)
1033 static inline struct intel_crtc
*
1034 intel_get_crtc_for_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1036 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
1039 static inline struct intel_crtc
*
1040 intel_get_crtc_for_plane(struct drm_i915_private
*dev_priv
, enum plane plane
)
1042 return dev_priv
->plane_to_crtc_mapping
[plane
];
1045 struct intel_flip_work
{
1046 struct work_struct unpin_work
;
1047 struct work_struct mmio_work
;
1049 struct drm_crtc
*crtc
;
1050 struct i915_vma
*old_vma
;
1051 struct drm_framebuffer
*old_fb
;
1052 struct drm_i915_gem_object
*pending_flip_obj
;
1053 struct drm_pending_vblank_event
*event
;
1057 struct drm_i915_gem_request
*flip_queued_req
;
1058 u32 flip_queued_vblank
;
1059 u32 flip_ready_vblank
;
1060 unsigned int rotation
;
1063 struct intel_load_detect_pipe
{
1064 struct drm_atomic_state
*restore_state
;
1067 static inline struct intel_encoder
*
1068 intel_attached_encoder(struct drm_connector
*connector
)
1070 return to_intel_connector(connector
)->encoder
;
1073 static inline struct intel_digital_port
*
1074 enc_to_dig_port(struct drm_encoder
*encoder
)
1076 return container_of(encoder
, struct intel_digital_port
, base
.base
);
1079 static inline struct intel_dp_mst_encoder
*
1080 enc_to_mst(struct drm_encoder
*encoder
)
1082 return container_of(encoder
, struct intel_dp_mst_encoder
, base
.base
);
1085 static inline struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
1087 return &enc_to_dig_port(encoder
)->dp
;
1090 static inline struct intel_digital_port
*
1091 dp_to_dig_port(struct intel_dp
*intel_dp
)
1093 return container_of(intel_dp
, struct intel_digital_port
, dp
);
1096 static inline struct intel_digital_port
*
1097 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
1099 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
1102 /* intel_fifo_underrun.c */
1103 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
1104 enum pipe pipe
, bool enable
);
1105 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
1106 enum transcoder pch_transcoder
,
1108 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
1110 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
1111 enum transcoder pch_transcoder
);
1112 void intel_check_cpu_fifo_underruns(struct drm_i915_private
*dev_priv
);
1113 void intel_check_pch_fifo_underruns(struct drm_i915_private
*dev_priv
);
1116 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1117 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1118 void gen6_reset_pm_iir(struct drm_i915_private
*dev_priv
, u32 mask
);
1119 void gen6_mask_pm_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
1120 void gen6_unmask_pm_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
1121 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1122 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1123 void gen6_reset_rps_interrupts(struct drm_i915_private
*dev_priv
);
1124 void gen6_enable_rps_interrupts(struct drm_i915_private
*dev_priv
);
1125 void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv
);
1126 u32
gen6_sanitize_rps_pm_mask(struct drm_i915_private
*dev_priv
, u32 mask
);
1127 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
);
1128 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
);
1129 static inline bool intel_irqs_enabled(struct drm_i915_private
*dev_priv
)
1132 * We only use drm_irq_uninstall() at unload and VT switch, so
1133 * this is the only thing we need to check.
1135 return dev_priv
->pm
.irqs_enabled
;
1138 int intel_get_crtc_scanline(struct intel_crtc
*crtc
);
1139 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
1140 unsigned int pipe_mask
);
1141 void gen8_irq_power_well_pre_disable(struct drm_i915_private
*dev_priv
,
1142 unsigned int pipe_mask
);
1143 void gen9_reset_guc_interrupts(struct drm_i915_private
*dev_priv
);
1144 void gen9_enable_guc_interrupts(struct drm_i915_private
*dev_priv
);
1145 void gen9_disable_guc_interrupts(struct drm_i915_private
*dev_priv
);
1148 void intel_crt_init(struct drm_device
*dev
);
1149 void intel_crt_reset(struct drm_encoder
*encoder
);
1152 void intel_ddi_clk_select(struct intel_encoder
*encoder
,
1153 struct intel_shared_dpll
*pll
);
1154 void intel_ddi_fdi_post_disable(struct intel_encoder
*intel_encoder
,
1155 struct intel_crtc_state
*old_crtc_state
,
1156 struct drm_connector_state
*old_conn_state
);
1157 void intel_prepare_dp_ddi_buffers(struct intel_encoder
*encoder
);
1158 void hsw_fdi_link_train(struct drm_crtc
*crtc
);
1159 void intel_ddi_init(struct drm_device
*dev
, enum port port
);
1160 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
);
1161 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
, enum pipe
*pipe
);
1162 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
);
1163 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1164 enum transcoder cpu_transcoder
);
1165 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
);
1166 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
);
1167 bool intel_ddi_pll_select(struct intel_crtc
*crtc
,
1168 struct intel_crtc_state
*crtc_state
);
1169 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
);
1170 void intel_ddi_prepare_link_retrain(struct intel_dp
*intel_dp
);
1171 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
);
1172 void intel_ddi_get_config(struct intel_encoder
*encoder
,
1173 struct intel_crtc_state
*pipe_config
);
1174 struct intel_encoder
*
1175 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state
*crtc_state
);
1177 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
);
1178 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
1179 struct intel_crtc_state
*pipe_config
);
1180 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
);
1181 uint32_t ddi_signal_levels(struct intel_dp
*intel_dp
);
1182 struct intel_shared_dpll
*intel_ddi_get_link_dpll(struct intel_dp
*intel_dp
,
1184 unsigned int intel_fb_align_height(struct drm_device
*dev
,
1185 unsigned int height
,
1186 uint32_t pixel_format
,
1187 uint64_t fb_format_modifier
);
1188 u32
intel_fb_stride_alignment(const struct drm_i915_private
*dev_priv
,
1189 uint64_t fb_modifier
, uint32_t pixel_format
);
1192 void intel_init_audio_hooks(struct drm_i915_private
*dev_priv
);
1193 void intel_audio_codec_enable(struct intel_encoder
*encoder
,
1194 const struct intel_crtc_state
*crtc_state
,
1195 const struct drm_connector_state
*conn_state
);
1196 void intel_audio_codec_disable(struct intel_encoder
*encoder
);
1197 void i915_audio_component_init(struct drm_i915_private
*dev_priv
);
1198 void i915_audio_component_cleanup(struct drm_i915_private
*dev_priv
);
1200 /* intel_display.c */
1201 enum transcoder
intel_crtc_pch_transcoder(struct intel_crtc
*crtc
);
1202 void skl_set_preferred_cdclk_vco(struct drm_i915_private
*dev_priv
, int vco
);
1203 void intel_update_rawclk(struct drm_i915_private
*dev_priv
);
1204 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
1205 const char *name
, u32 reg
, int ref_freq
);
1206 void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
);
1207 void lpt_disable_iclkip(struct drm_i915_private
*dev_priv
);
1208 extern const struct drm_plane_funcs intel_plane_funcs
;
1209 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
);
1210 unsigned int intel_fb_xy_to_linear(int x
, int y
,
1211 const struct intel_plane_state
*state
,
1213 void intel_add_fb_offsets(int *x
, int *y
,
1214 const struct intel_plane_state
*state
, int plane
);
1215 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
);
1216 bool intel_has_pending_fb_unpin(struct drm_device
*dev
);
1217 void intel_mark_busy(struct drm_i915_private
*dev_priv
);
1218 void intel_mark_idle(struct drm_i915_private
*dev_priv
);
1219 void intel_crtc_restore_mode(struct drm_crtc
*crtc
);
1220 int intel_display_suspend(struct drm_device
*dev
);
1221 void intel_pps_unlock_regs_wa(struct drm_i915_private
*dev_priv
);
1222 void intel_encoder_destroy(struct drm_encoder
*encoder
);
1223 int intel_connector_init(struct intel_connector
*);
1224 struct intel_connector
*intel_connector_alloc(void);
1225 bool intel_connector_get_hw_state(struct intel_connector
*connector
);
1226 void intel_connector_attach_encoder(struct intel_connector
*connector
,
1227 struct intel_encoder
*encoder
);
1228 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
1229 struct drm_crtc
*crtc
);
1230 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
);
1231 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
1232 struct drm_file
*file_priv
);
1233 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1236 intel_crtc_has_type(const struct intel_crtc_state
*crtc_state
,
1237 enum intel_output_type type
)
1239 return crtc_state
->output_types
& (1 << type
);
1242 intel_crtc_has_dp_encoder(const struct intel_crtc_state
*crtc_state
)
1244 return crtc_state
->output_types
&
1245 ((1 << INTEL_OUTPUT_DP
) |
1246 (1 << INTEL_OUTPUT_DP_MST
) |
1247 (1 << INTEL_OUTPUT_EDP
));
1250 intel_wait_for_vblank(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1252 drm_wait_one_vblank(&dev_priv
->drm
, pipe
);
1255 intel_wait_for_vblank_if_active(struct drm_i915_private
*dev_priv
, int pipe
)
1257 const struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
1260 intel_wait_for_vblank(dev_priv
, pipe
);
1263 u32
intel_crtc_get_vblank_counter(struct intel_crtc
*crtc
);
1265 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
);
1266 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1267 struct intel_digital_port
*dport
,
1268 unsigned int expected_mask
);
1269 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
1270 struct drm_display_mode
*mode
,
1271 struct intel_load_detect_pipe
*old
,
1272 struct drm_modeset_acquire_ctx
*ctx
);
1273 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
1274 struct intel_load_detect_pipe
*old
,
1275 struct drm_modeset_acquire_ctx
*ctx
);
1277 intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
, unsigned int rotation
);
1278 void intel_unpin_fb_vma(struct i915_vma
*vma
);
1279 struct drm_framebuffer
*
1280 __intel_framebuffer_create(struct drm_device
*dev
,
1281 struct drm_mode_fb_cmd2
*mode_cmd
,
1282 struct drm_i915_gem_object
*obj
);
1283 void intel_finish_page_flip_cs(struct drm_i915_private
*dev_priv
, int pipe
);
1284 void intel_finish_page_flip_mmio(struct drm_i915_private
*dev_priv
, int pipe
);
1285 void intel_check_page_flip(struct drm_i915_private
*dev_priv
, int pipe
);
1286 int intel_prepare_plane_fb(struct drm_plane
*plane
,
1287 struct drm_plane_state
*new_state
);
1288 void intel_cleanup_plane_fb(struct drm_plane
*plane
,
1289 struct drm_plane_state
*old_state
);
1290 int intel_plane_atomic_get_property(struct drm_plane
*plane
,
1291 const struct drm_plane_state
*state
,
1292 struct drm_property
*property
,
1294 int intel_plane_atomic_set_property(struct drm_plane
*plane
,
1295 struct drm_plane_state
*state
,
1296 struct drm_property
*property
,
1298 int intel_plane_atomic_calc_changes(struct drm_crtc_state
*crtc_state
,
1299 struct drm_plane_state
*plane_state
);
1301 unsigned int intel_tile_height(const struct drm_i915_private
*dev_priv
,
1302 uint64_t fb_modifier
, unsigned int cpp
);
1304 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1307 int vlv_force_pll_on(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1308 const struct dpll
*dpll
);
1309 void vlv_force_pll_off(struct drm_i915_private
*dev_priv
, enum pipe pipe
);
1310 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
);
1312 /* modesetting asserts */
1313 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1315 void assert_pll(struct drm_i915_private
*dev_priv
,
1316 enum pipe pipe
, bool state
);
1317 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1318 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1319 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
);
1320 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1321 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1322 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1323 enum pipe pipe
, bool state
);
1324 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1325 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1326 void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool state
);
1327 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1328 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1329 u32
intel_compute_tile_offset(int *x
, int *y
,
1330 const struct intel_plane_state
*state
, int plane
);
1331 void intel_prepare_reset(struct drm_i915_private
*dev_priv
);
1332 void intel_finish_reset(struct drm_i915_private
*dev_priv
);
1333 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
);
1334 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
);
1335 void bxt_init_cdclk(struct drm_i915_private
*dev_priv
);
1336 void bxt_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1337 void gen9_sanitize_dc_state(struct drm_i915_private
*dev_priv
);
1338 void bxt_enable_dc9(struct drm_i915_private
*dev_priv
);
1339 void bxt_disable_dc9(struct drm_i915_private
*dev_priv
);
1340 void gen9_enable_dc5(struct drm_i915_private
*dev_priv
);
1341 void skl_init_cdclk(struct drm_i915_private
*dev_priv
);
1342 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1343 unsigned int skl_cdclk_get_vco(unsigned int freq
);
1344 void skl_enable_dc6(struct drm_i915_private
*dev_priv
);
1345 void skl_disable_dc6(struct drm_i915_private
*dev_priv
);
1346 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
1347 struct intel_crtc_state
*pipe_config
);
1348 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
);
1349 int intel_dotclock_calculate(int link_freq
, const struct intel_link_m_n
*m_n
);
1350 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
1351 struct dpll
*best_clock
);
1352 int chv_calc_dpll_params(int refclk
, struct dpll
*pll_clock
);
1354 bool intel_crtc_active(struct intel_crtc
*crtc
);
1355 void hsw_enable_ips(struct intel_crtc
*crtc
);
1356 void hsw_disable_ips(struct intel_crtc
*crtc
);
1357 enum intel_display_power_domain
1358 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
);
1359 enum intel_display_power_domain
1360 intel_display_port_aux_power_domain(struct intel_encoder
*intel_encoder
);
1361 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
1362 struct intel_crtc_state
*pipe_config
);
1364 int skl_update_scaler_crtc(struct intel_crtc_state
*crtc_state
);
1365 int skl_max_scale(struct intel_crtc
*crtc
, struct intel_crtc_state
*crtc_state
);
1367 static inline u32
intel_plane_ggtt_offset(const struct intel_plane_state
*state
)
1369 return i915_ggtt_offset(state
->vma
);
1372 u32
skl_plane_ctl_format(uint32_t pixel_format
);
1373 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
);
1374 u32
skl_plane_ctl_rotation(unsigned int rotation
);
1375 u32
skl_plane_stride(const struct drm_framebuffer
*fb
, int plane
,
1376 unsigned int rotation
);
1377 int skl_check_plane_surface(struct intel_plane_state
*plane_state
);
1380 void intel_csr_ucode_init(struct drm_i915_private
*);
1381 void intel_csr_load_program(struct drm_i915_private
*);
1382 void intel_csr_ucode_fini(struct drm_i915_private
*);
1383 void intel_csr_ucode_suspend(struct drm_i915_private
*);
1384 void intel_csr_ucode_resume(struct drm_i915_private
*);
1387 bool intel_dp_init(struct drm_device
*dev
, i915_reg_t output_reg
, enum port port
);
1388 bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
1389 struct intel_connector
*intel_connector
);
1390 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1391 int link_rate
, uint8_t lane_count
,
1393 void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
1394 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
);
1395 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
1396 void intel_dp_encoder_reset(struct drm_encoder
*encoder
);
1397 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
);
1398 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
);
1399 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
);
1400 bool intel_dp_compute_config(struct intel_encoder
*encoder
,
1401 struct intel_crtc_state
*pipe_config
,
1402 struct drm_connector_state
*conn_state
);
1403 bool intel_dp_is_edp(struct drm_i915_private
*dev_priv
, enum port port
);
1404 enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
,
1406 void intel_edp_backlight_on(struct intel_dp
*intel_dp
);
1407 void intel_edp_backlight_off(struct intel_dp
*intel_dp
);
1408 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
1409 void intel_edp_panel_on(struct intel_dp
*intel_dp
);
1410 void intel_edp_panel_off(struct intel_dp
*intel_dp
);
1411 void intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
);
1412 void intel_dp_mst_suspend(struct drm_device
*dev
);
1413 void intel_dp_mst_resume(struct drm_device
*dev
);
1414 int intel_dp_max_link_rate(struct intel_dp
*intel_dp
);
1415 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
);
1416 void intel_dp_hot_plug(struct intel_encoder
*intel_encoder
);
1417 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
);
1418 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
);
1419 void intel_plane_destroy(struct drm_plane
*plane
);
1420 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
1421 struct intel_crtc_state
*crtc_state
);
1422 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
1423 struct intel_crtc_state
*crtc_state
);
1424 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
1425 unsigned int frontbuffer_bits
);
1426 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
1427 unsigned int frontbuffer_bits
);
1430 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
1431 uint8_t dp_train_pat
);
1433 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
);
1434 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
);
1436 intel_dp_voltage_max(struct intel_dp
*intel_dp
);
1438 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
);
1439 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1440 uint8_t *link_bw
, uint8_t *rate_select
);
1441 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
);
1443 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
]);
1445 static inline unsigned int intel_dp_unused_lane_mask(int lane_count
)
1447 return ~((1 << lane_count
) - 1) & 0xf;
1450 bool intel_dp_read_dpcd(struct intel_dp
*intel_dp
);
1451 bool __intel_dp_read_desc(struct intel_dp
*intel_dp
,
1452 struct intel_dp_desc
*desc
);
1453 bool intel_dp_read_desc(struct intel_dp
*intel_dp
);
1454 bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
1455 struct intel_digital_port
*port
);
1457 /* intel_dp_aux_backlight.c */
1458 int intel_dp_aux_init_backlight_funcs(struct intel_connector
*intel_connector
);
1460 /* intel_dp_mst.c */
1461 int intel_dp_mst_encoder_init(struct intel_digital_port
*intel_dig_port
, int conn_id
);
1462 void intel_dp_mst_encoder_cleanup(struct intel_digital_port
*intel_dig_port
);
1464 void intel_dsi_init(struct drm_device
*dev
);
1466 /* intel_dsi_dcs_backlight.c */
1467 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector
*intel_connector
);
1470 void intel_dvo_init(struct drm_device
*dev
);
1471 /* intel_hotplug.c */
1472 void intel_hpd_poll_init(struct drm_i915_private
*dev_priv
);
1475 /* legacy fbdev emulation in intel_fbdev.c */
1476 #ifdef CONFIG_DRM_FBDEV_EMULATION
1477 extern int intel_fbdev_init(struct drm_device
*dev
);
1478 extern void intel_fbdev_initial_config_async(struct drm_device
*dev
);
1479 extern void intel_fbdev_fini(struct drm_device
*dev
);
1480 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
);
1481 extern void intel_fbdev_output_poll_changed(struct drm_device
*dev
);
1482 extern void intel_fbdev_restore_mode(struct drm_device
*dev
);
1484 static inline int intel_fbdev_init(struct drm_device
*dev
)
1489 static inline void intel_fbdev_initial_config_async(struct drm_device
*dev
)
1493 static inline void intel_fbdev_fini(struct drm_device
*dev
)
1497 static inline void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
)
1501 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
1505 static inline void intel_fbdev_restore_mode(struct drm_device
*dev
)
1511 void intel_fbc_choose_crtc(struct drm_i915_private
*dev_priv
,
1512 struct drm_atomic_state
*state
);
1513 bool intel_fbc_is_active(struct drm_i915_private
*dev_priv
);
1514 void intel_fbc_pre_update(struct intel_crtc
*crtc
,
1515 struct intel_crtc_state
*crtc_state
,
1516 struct intel_plane_state
*plane_state
);
1517 void intel_fbc_post_update(struct intel_crtc
*crtc
);
1518 void intel_fbc_init(struct drm_i915_private
*dev_priv
);
1519 void intel_fbc_init_pipe_state(struct drm_i915_private
*dev_priv
);
1520 void intel_fbc_enable(struct intel_crtc
*crtc
,
1521 struct intel_crtc_state
*crtc_state
,
1522 struct intel_plane_state
*plane_state
);
1523 void intel_fbc_disable(struct intel_crtc
*crtc
);
1524 void intel_fbc_global_disable(struct drm_i915_private
*dev_priv
);
1525 void intel_fbc_invalidate(struct drm_i915_private
*dev_priv
,
1526 unsigned int frontbuffer_bits
,
1527 enum fb_op_origin origin
);
1528 void intel_fbc_flush(struct drm_i915_private
*dev_priv
,
1529 unsigned int frontbuffer_bits
, enum fb_op_origin origin
);
1530 void intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
);
1531 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private
*dev_priv
);
1534 void intel_hdmi_init(struct drm_device
*dev
, i915_reg_t hdmi_reg
, enum port port
);
1535 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
1536 struct intel_connector
*intel_connector
);
1537 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
);
1538 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
1539 struct intel_crtc_state
*pipe_config
,
1540 struct drm_connector_state
*conn_state
);
1541 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi
*hdmi
, bool enable
);
1545 void intel_lvds_init(struct drm_device
*dev
);
1546 struct intel_encoder
*intel_get_lvds_encoder(struct drm_device
*dev
);
1547 bool intel_is_dual_link_lvds(struct drm_device
*dev
);
1551 int intel_connector_update_modes(struct drm_connector
*connector
,
1553 int intel_ddc_get_modes(struct drm_connector
*c
, struct i2c_adapter
*adapter
);
1554 void intel_attach_force_audio_property(struct drm_connector
*connector
);
1555 void intel_attach_broadcast_rgb_property(struct drm_connector
*connector
);
1556 void intel_attach_aspect_ratio_property(struct drm_connector
*connector
);
1559 /* intel_overlay.c */
1560 void intel_setup_overlay(struct drm_i915_private
*dev_priv
);
1561 void intel_cleanup_overlay(struct drm_i915_private
*dev_priv
);
1562 int intel_overlay_switch_off(struct intel_overlay
*overlay
);
1563 int intel_overlay_put_image_ioctl(struct drm_device
*dev
, void *data
,
1564 struct drm_file
*file_priv
);
1565 int intel_overlay_attrs_ioctl(struct drm_device
*dev
, void *data
,
1566 struct drm_file
*file_priv
);
1567 void intel_overlay_reset(struct drm_i915_private
*dev_priv
);
1571 int intel_panel_init(struct intel_panel
*panel
,
1572 struct drm_display_mode
*fixed_mode
,
1573 struct drm_display_mode
*downclock_mode
);
1574 void intel_panel_fini(struct intel_panel
*panel
);
1575 void intel_fixed_panel_mode(const struct drm_display_mode
*fixed_mode
,
1576 struct drm_display_mode
*adjusted_mode
);
1577 void intel_pch_panel_fitting(struct intel_crtc
*crtc
,
1578 struct intel_crtc_state
*pipe_config
,
1580 void intel_gmch_panel_fitting(struct intel_crtc
*crtc
,
1581 struct intel_crtc_state
*pipe_config
,
1583 void intel_panel_set_backlight_acpi(struct intel_connector
*connector
,
1584 u32 level
, u32 max
);
1585 int intel_panel_setup_backlight(struct drm_connector
*connector
,
1587 void intel_panel_enable_backlight(struct intel_connector
*connector
);
1588 void intel_panel_disable_backlight(struct intel_connector
*connector
);
1589 void intel_panel_destroy_backlight(struct drm_connector
*connector
);
1590 enum drm_connector_status
intel_panel_detect(struct drm_device
*dev
);
1591 extern struct drm_display_mode
*intel_find_panel_downclock(
1592 struct drm_device
*dev
,
1593 struct drm_display_mode
*fixed_mode
,
1594 struct drm_connector
*connector
);
1596 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1597 int intel_backlight_device_register(struct intel_connector
*connector
);
1598 void intel_backlight_device_unregister(struct intel_connector
*connector
);
1599 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1600 static int intel_backlight_device_register(struct intel_connector
*connector
)
1604 static inline void intel_backlight_device_unregister(struct intel_connector
*connector
)
1607 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1611 void intel_psr_enable(struct intel_dp
*intel_dp
);
1612 void intel_psr_disable(struct intel_dp
*intel_dp
);
1613 void intel_psr_invalidate(struct drm_i915_private
*dev_priv
,
1614 unsigned frontbuffer_bits
);
1615 void intel_psr_flush(struct drm_i915_private
*dev_priv
,
1616 unsigned frontbuffer_bits
,
1617 enum fb_op_origin origin
);
1618 void intel_psr_init(struct drm_device
*dev
);
1619 void intel_psr_single_frame_update(struct drm_i915_private
*dev_priv
,
1620 unsigned frontbuffer_bits
);
1622 /* intel_runtime_pm.c */
1623 int intel_power_domains_init(struct drm_i915_private
*);
1624 void intel_power_domains_fini(struct drm_i915_private
*);
1625 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
, bool resume
);
1626 void intel_power_domains_suspend(struct drm_i915_private
*dev_priv
);
1627 void bxt_display_core_init(struct drm_i915_private
*dev_priv
, bool resume
);
1628 void bxt_display_core_uninit(struct drm_i915_private
*dev_priv
);
1629 void intel_runtime_pm_enable(struct drm_i915_private
*dev_priv
);
1631 intel_display_power_domain_str(enum intel_display_power_domain domain
);
1633 bool intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1634 enum intel_display_power_domain domain
);
1635 bool __intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1636 enum intel_display_power_domain domain
);
1637 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
1638 enum intel_display_power_domain domain
);
1639 bool intel_display_power_get_if_enabled(struct drm_i915_private
*dev_priv
,
1640 enum intel_display_power_domain domain
);
1641 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
1642 enum intel_display_power_domain domain
);
1645 assert_rpm_device_not_suspended(struct drm_i915_private
*dev_priv
)
1647 WARN_ONCE(dev_priv
->pm
.suspended
,
1648 "Device suspended during HW access\n");
1652 assert_rpm_wakelock_held(struct drm_i915_private
*dev_priv
)
1654 assert_rpm_device_not_suspended(dev_priv
);
1655 /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1656 * too much noise. */
1657 if (!atomic_read(&dev_priv
->pm
.wakeref_count
))
1658 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1662 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1663 * @dev_priv: i915 device instance
1665 * This function disable asserts that check if we hold an RPM wakelock
1666 * reference, while keeping the device-not-suspended checks still enabled.
1667 * It's meant to be used only in special circumstances where our rule about
1668 * the wakelock refcount wrt. the device power state doesn't hold. According
1669 * to this rule at any point where we access the HW or want to keep the HW in
1670 * an active state we must hold an RPM wakelock reference acquired via one of
1671 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1672 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1673 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1674 * users should avoid using this function.
1676 * Any calls to this function must have a symmetric call to
1677 * enable_rpm_wakeref_asserts().
1680 disable_rpm_wakeref_asserts(struct drm_i915_private
*dev_priv
)
1682 atomic_inc(&dev_priv
->pm
.wakeref_count
);
1686 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1687 * @dev_priv: i915 device instance
1689 * This function re-enables the RPM assert checks after disabling them with
1690 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1691 * circumstances otherwise its use should be avoided.
1693 * Any calls to this function must have a symmetric call to
1694 * disable_rpm_wakeref_asserts().
1697 enable_rpm_wakeref_asserts(struct drm_i915_private
*dev_priv
)
1699 atomic_dec(&dev_priv
->pm
.wakeref_count
);
1702 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
);
1703 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private
*dev_priv
);
1704 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
);
1705 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
);
1707 void intel_display_set_init_power(struct drm_i915_private
*dev
, bool enable
);
1709 void chv_phy_powergate_lanes(struct intel_encoder
*encoder
,
1710 bool override
, unsigned int mask
);
1711 bool chv_phy_powergate_ch(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
,
1712 enum dpio_channel ch
, bool override
);
1716 void intel_init_clock_gating(struct drm_i915_private
*dev_priv
);
1717 void intel_suspend_hw(struct drm_i915_private
*dev_priv
);
1718 int ilk_wm_max_level(const struct drm_i915_private
*dev_priv
);
1719 void intel_update_watermarks(struct intel_crtc
*crtc
);
1720 void intel_init_pm(struct drm_i915_private
*dev_priv
);
1721 void intel_init_clock_gating_hooks(struct drm_i915_private
*dev_priv
);
1722 void intel_pm_setup(struct drm_device
*dev
);
1723 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
1724 void intel_gpu_ips_teardown(void);
1725 void intel_init_gt_powersave(struct drm_i915_private
*dev_priv
);
1726 void intel_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
);
1727 void intel_sanitize_gt_powersave(struct drm_i915_private
*dev_priv
);
1728 void intel_enable_gt_powersave(struct drm_i915_private
*dev_priv
);
1729 void intel_autoenable_gt_powersave(struct drm_i915_private
*dev_priv
);
1730 void intel_disable_gt_powersave(struct drm_i915_private
*dev_priv
);
1731 void intel_suspend_gt_powersave(struct drm_i915_private
*dev_priv
);
1732 void gen6_rps_busy(struct drm_i915_private
*dev_priv
);
1733 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
);
1734 void gen6_rps_idle(struct drm_i915_private
*dev_priv
);
1735 void gen6_rps_boost(struct drm_i915_private
*dev_priv
,
1736 struct intel_rps_client
*rps
,
1737 unsigned long submitted
);
1738 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request
*req
);
1739 void vlv_wm_get_hw_state(struct drm_device
*dev
);
1740 void ilk_wm_get_hw_state(struct drm_device
*dev
);
1741 void skl_wm_get_hw_state(struct drm_device
*dev
);
1742 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
1743 struct skl_ddb_allocation
*ddb
/* out */);
1744 void skl_pipe_wm_get_hw_state(struct drm_crtc
*crtc
,
1745 struct skl_pipe_wm
*out
);
1746 bool intel_can_enable_sagv(struct drm_atomic_state
*state
);
1747 int intel_enable_sagv(struct drm_i915_private
*dev_priv
);
1748 int intel_disable_sagv(struct drm_i915_private
*dev_priv
);
1749 bool skl_wm_level_equals(const struct skl_wm_level
*l1
,
1750 const struct skl_wm_level
*l2
);
1751 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry
**entries
,
1752 const struct skl_ddb_entry
*ddb
,
1754 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
*pipe_config
);
1755 bool ilk_disable_lp_wm(struct drm_device
*dev
);
1756 int sanitize_rc6_option(struct drm_i915_private
*dev_priv
, int enable_rc6
);
1757 static inline int intel_enable_rc6(void)
1759 return i915
.enable_rc6
;
1763 bool intel_sdvo_init(struct drm_device
*dev
,
1764 i915_reg_t reg
, enum port port
);
1767 /* intel_sprite.c */
1768 int intel_usecs_to_scanlines(const struct drm_display_mode
*adjusted_mode
,
1770 struct intel_plane
*intel_sprite_plane_create(struct drm_i915_private
*dev_priv
,
1771 enum pipe pipe
, int plane
);
1772 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
1773 struct drm_file
*file_priv
);
1774 void intel_pipe_update_start(struct intel_crtc
*crtc
);
1775 void intel_pipe_update_end(struct intel_crtc
*crtc
, struct intel_flip_work
*work
);
1778 void intel_tv_init(struct drm_device
*dev
);
1780 /* intel_atomic.c */
1781 int intel_connector_atomic_get_property(struct drm_connector
*connector
,
1782 const struct drm_connector_state
*state
,
1783 struct drm_property
*property
,
1785 struct drm_crtc_state
*intel_crtc_duplicate_state(struct drm_crtc
*crtc
);
1786 void intel_crtc_destroy_state(struct drm_crtc
*crtc
,
1787 struct drm_crtc_state
*state
);
1788 struct drm_atomic_state
*intel_atomic_state_alloc(struct drm_device
*dev
);
1789 void intel_atomic_state_clear(struct drm_atomic_state
*);
1790 struct intel_shared_dpll_config
*
1791 intel_atomic_get_shared_dpll_state(struct drm_atomic_state
*s
);
1793 static inline struct intel_crtc_state
*
1794 intel_atomic_get_crtc_state(struct drm_atomic_state
*state
,
1795 struct intel_crtc
*crtc
)
1797 struct drm_crtc_state
*crtc_state
;
1798 crtc_state
= drm_atomic_get_crtc_state(state
, &crtc
->base
);
1799 if (IS_ERR(crtc_state
))
1800 return ERR_CAST(crtc_state
);
1802 return to_intel_crtc_state(crtc_state
);
1805 static inline struct intel_plane_state
*
1806 intel_atomic_get_existing_plane_state(struct drm_atomic_state
*state
,
1807 struct intel_plane
*plane
)
1809 struct drm_plane_state
*plane_state
;
1811 plane_state
= drm_atomic_get_existing_plane_state(state
, &plane
->base
);
1813 return to_intel_plane_state(plane_state
);
1816 int intel_atomic_setup_scalers(struct drm_device
*dev
,
1817 struct intel_crtc
*intel_crtc
,
1818 struct intel_crtc_state
*crtc_state
);
1820 /* intel_atomic_plane.c */
1821 struct intel_plane_state
*intel_create_plane_state(struct drm_plane
*plane
);
1822 struct drm_plane_state
*intel_plane_duplicate_state(struct drm_plane
*plane
);
1823 void intel_plane_destroy_state(struct drm_plane
*plane
,
1824 struct drm_plane_state
*state
);
1825 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs
;
1828 void intel_color_init(struct drm_crtc
*crtc
);
1829 int intel_color_check(struct drm_crtc
*crtc
, struct drm_crtc_state
*state
);
1830 void intel_color_set_csc(struct drm_crtc_state
*crtc_state
);
1831 void intel_color_load_luts(struct drm_crtc_state
*crtc_state
);
1833 /* intel_lspcon.c */
1834 bool lspcon_init(struct intel_digital_port
*intel_dig_port
);
1835 void lspcon_resume(struct intel_lspcon
*lspcon
);
1836 #endif /* __INTEL_DRV_H__ */