drivers/gpu/drm/i915/intel_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc.h>
  28 #include <drm/drm_edid.h>
  29 #include <drm/i915_drm.h>
  30 #include <linux/slab.h>
  31 #include "i915_drv.h"
  32 #include "intel_drv.h"
  33 #include "intel_dsi.h"
  34 #include "intel_dsi_cmd.h"
  35
  36 /* the sub-encoders aka panel drivers */
  37 static const struct intel_dsi_device intel_dsi_devices[] = {
  38         {
  39                 .panel_id = MIPI_DSI_GENERIC_PANEL_ID,
  40                 .name = "vbt-generic-dsi-vid-mode-display",
  41                 .dev_ops = &vbt_generic_dsi_display_ops,
  42         },
  43 };
  44
  45 static void band_gap_reset(struct drm_i915_private *dev_priv)
  46 {
  47         mutex_lock(&dev_priv->dpio_lock);
  48
  49         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
  50         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
  51         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
  52         udelay(150);
  53         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
  54         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
  55
  56         mutex_unlock(&dev_priv->dpio_lock);
  57 }
  58
  59 static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
  60 {
  61         return container_of(intel_attached_encoder(connector),
  62                             struct intel_dsi, base);
  63 }
  64
  65 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
  66 {
  67         return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
  68 }
  69
  70 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
  71 {
  72         return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
  73 }
  74
  75 static void intel_dsi_hot_plug(struct intel_encoder *encoder)
  76 {
  77         DRM_DEBUG_KMS("\n");
  78 }
  79
  80 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
  81                                      struct intel_crtc_config *config)
  82 {
  83         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
  84                                                    base);
  85         struct intel_connector *intel_connector = intel_dsi->attached_connector;
  86         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
  87         struct drm_display_mode *adjusted_mode = &config->adjusted_mode;
  88         struct drm_display_mode *mode = &config->requested_mode;
  89
  90         DRM_DEBUG_KMS("\n");
  91
  92         if (fixed_mode)
  93                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
  94
  95         if (intel_dsi->dev.dev_ops->mode_fixup)
  96                 return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev,
  97                                                           mode, adjusted_mode);
  98
  99         return true;
 100 }
 101
 102 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 103 {
 104         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 105         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 106         int pipe = intel_crtc->pipe;
 107         u32 val;
 108
 109         DRM_DEBUG_KMS("\n");
 110
 111         mutex_lock(&dev_priv->dpio_lock);
 112         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 113          * needed everytime after power gate */
 114         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 115         mutex_unlock(&dev_priv->dpio_lock);
 116
 117         /* bandgap reset is needed after everytime we do power gate */
 118         band_gap_reset(dev_priv);
 119
 120         val = I915_READ(MIPI_PORT_CTRL(pipe));
 121         I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD);
 122         usleep_range(1000, 1500);
 123         I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT);
 124         usleep_range(2000, 2500);
 125         I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
 126         usleep_range(2000, 2500);
 127         I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
 128         usleep_range(2000, 2500);
 129         I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
 130         usleep_range(2000, 2500);
 131 }
 132
 133 static void intel_dsi_enable(struct intel_encoder *encoder)
 134 {
 135         struct drm_device *dev = encoder->base.dev;
 136         struct drm_i915_private *dev_priv = dev->dev_private;
 137         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 138         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 139         int pipe = intel_crtc->pipe;
 140         u32 temp;
 141
 142         DRM_DEBUG_KMS("\n");
 143
 144         if (is_cmd_mode(intel_dsi))
 145                 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
 146         else {
 147                 msleep(20); /* XXX */
 148                 dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN);
 149                 msleep(100);
 150
 151                 if (intel_dsi->dev.dev_ops->enable)
 152                         intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
 153
 154                 /* assert ip_tg_enable signal */
 155                 temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK;
 156                 temp = temp | intel_dsi->port_bits;
 157                 I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
 158                 POSTING_READ(MIPI_PORT_CTRL(pipe));
 159         }
 160 }
 161
 162 static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 163 {
 164         struct drm_device *dev = encoder->base.dev;
 165         struct drm_i915_private *dev_priv = dev->dev_private;
 166         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 167         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 168         enum pipe pipe = intel_crtc->pipe;
 169         u32 tmp;
 170
 171         DRM_DEBUG_KMS("\n");
 172
 173         /* Disable DPOunit clock gating, can stall pipe
 174          * and we need DPLL REFA always enabled */
 175         tmp = I915_READ(DPLL(pipe));
 176         tmp |= DPLL_REFA_CLK_ENABLE_VLV;
 177         I915_WRITE(DPLL(pipe), tmp);
 178
 179         tmp = I915_READ(DSPCLK_GATE_D);
 180         tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
 181         I915_WRITE(DSPCLK_GATE_D, tmp);
 182
 183         /* put device in ready state */
 184         intel_dsi_device_ready(encoder);
 185
 186         msleep(intel_dsi->panel_on_delay);
 187
 188         if (intel_dsi->dev.dev_ops->panel_reset)
 189                 intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
 190
 191         if (intel_dsi->dev.dev_ops->send_otp_cmds)
 192                 intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev);
 193
 194         /* Enable port in pre-enable phase itself because as per hw team
 195          * recommendation, port should be enabled befor plane & pipe */
 196         intel_dsi_enable(encoder);
 197 }
 198
 199 static void intel_dsi_enable_nop(struct intel_encoder *encoder)
 200 {
 201         DRM_DEBUG_KMS("\n");
 202
 203         /* for DSI port enable has to be done before pipe
 204          * and plane enable, so port enable is done in
 205          * pre_enable phase itself unlike other encoders
 206          */
 207 }
 208
 209 static void intel_dsi_pre_disable(struct intel_encoder *encoder)
 210 {
 211         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 212
 213         DRM_DEBUG_KMS("\n");
 214
 215         if (is_vid_mode(intel_dsi)) {
 216                 /* Send Shutdown command to the panel in LP mode */
 217                 dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN);
 218                 msleep(10);
 219         }
 220 }
 221
 222 static void intel_dsi_disable(struct intel_encoder *encoder)
 223 {
 224         struct drm_device *dev = encoder->base.dev;
 225         struct drm_i915_private *dev_priv = dev->dev_private;
 226         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 227         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 228         int pipe = intel_crtc->pipe;
 229         u32 temp;
 230
 231         DRM_DEBUG_KMS("\n");
 232
 233         if (is_vid_mode(intel_dsi)) {
 234                 /* de-assert ip_tg_enable signal */
 235                 temp = I915_READ(MIPI_PORT_CTRL(pipe));
 236                 I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
 237                 POSTING_READ(MIPI_PORT_CTRL(pipe));
 238
 239                 msleep(2);
 240         }
 241
 242         /* Panel commands can be sent when clock is in LP11 */
 243         I915_WRITE(MIPI_DEVICE_READY(pipe), 0x0);
 244
 245         temp = I915_READ(MIPI_CTRL(pipe));
 246         temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 247         I915_WRITE(MIPI_CTRL(pipe), temp |
 248                         intel_dsi->escape_clk_div <<
 249                         ESCAPE_CLOCK_DIVIDER_SHIFT);
 250
 251         I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP);
 252
 253         temp = I915_READ(MIPI_DSI_FUNC_PRG(pipe));
 254         temp &= ~VID_MODE_FORMAT_MASK;
 255         I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), temp);
 256
 257         I915_WRITE(MIPI_DEVICE_READY(pipe), 0x1);
 258
 259         /* if disable packets are sent before sending shutdown packet then in
 260          * some next enable sequence send turn on packet error is observed */
 261         if (intel_dsi->dev.dev_ops->disable)
 262                 intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
 263 }
 264
 265 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 266 {
 267         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 268         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 269         int pipe = intel_crtc->pipe;
 270         u32 val;
 271
 272         DRM_DEBUG_KMS("\n");
 273
 274         I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
 275         usleep_range(2000, 2500);
 276
 277         I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
 278         usleep_range(2000, 2500);
 279
 280         I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
 281         usleep_range(2000, 2500);
 282
 283         val = I915_READ(MIPI_PORT_CTRL(pipe));
 284         I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD);
 285         usleep_range(1000, 1500);
 286
 287         if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT)
 288                                         == 0x00000), 30))
 289                 DRM_ERROR("DSI LP not going Low\n");
 290
 291         I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
 292         usleep_range(2000, 2500);
 293
 294         vlv_disable_dsi_pll(encoder);
 295 }
 296
 297 static void intel_dsi_post_disable(struct intel_encoder *encoder)
 298 {
 299         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 300         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 301         u32 val;
 302
 303         DRM_DEBUG_KMS("\n");
 304
 305         intel_dsi_disable(encoder);
 306
 307         intel_dsi_clear_device_ready(encoder);
 308
 309         val = I915_READ(DSPCLK_GATE_D);
 310         val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 311         I915_WRITE(DSPCLK_GATE_D, val);
 312
 313         if (intel_dsi->dev.dev_ops->disable_panel_power)
 314                 intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev);
 315
 316         msleep(intel_dsi->panel_off_delay);
 317         msleep(intel_dsi->panel_pwr_cycle_delay);
 318 }
 319
 320 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 321                                    enum pipe *pipe)
 322 {
 323         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 324         enum intel_display_power_domain power_domain;
 325         u32 port, func;
 326         enum pipe p;
 327
 328         DRM_DEBUG_KMS("\n");
 329
 330         power_domain = intel_display_port_power_domain(encoder);
 331         if (!intel_display_power_enabled(dev_priv, power_domain))
 332                 return false;
 333
 334         /* XXX: this only works for one DSI output */
 335         for (p = PIPE_A; p <= PIPE_B; p++) {
 336                 port = I915_READ(MIPI_PORT_CTRL(p));
 337                 func = I915_READ(MIPI_DSI_FUNC_PRG(p));
 338
 339                 if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
 340                         if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) {
 341                                 *pipe = p;
 342                                 return true;
 343                         }
 344                 }
 345         }
 346
 347         return false;
 348 }
 349
 350 static void intel_dsi_get_config(struct intel_encoder *encoder,
 351                                  struct intel_crtc_config *pipe_config)
 352 {
 353         DRM_DEBUG_KMS("\n");
 354
 355         /* XXX: read flags, set to adjusted_mode */
 356 }
 357
 358 static enum drm_mode_status
 359 intel_dsi_mode_valid(struct drm_connector *connector,
 360                      struct drm_display_mode *mode)
 361 {
 362         struct intel_connector *intel_connector = to_intel_connector(connector);
 363         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 364         struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
 365
 366         DRM_DEBUG_KMS("\n");
 367
 368         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 369                 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
 370                 return MODE_NO_DBLESCAN;
 371         }
 372
 373         if (fixed_mode) {
 374                 if (mode->hdisplay > fixed_mode->hdisplay)
 375                         return MODE_PANEL;
 376                 if (mode->vdisplay > fixed_mode->vdisplay)
 377                         return MODE_PANEL;
 378         }
 379
 380         return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode);
 381 }
 382
 383 /* return txclkesc cycles in terms of divider and duration in us */
 384 static u16 txclkesc(u32 divider, unsigned int us)
 385 {
 386         switch (divider) {
 387         case ESCAPE_CLOCK_DIVIDER_1:
 388         default:
 389                 return 20 * us;
 390         case ESCAPE_CLOCK_DIVIDER_2:
 391                 return 10 * us;
 392         case ESCAPE_CLOCK_DIVIDER_4:
 393                 return 5 * us;
 394         }
 395 }
 396
 397 /* return pixels in terms of txbyteclkhs */
 398 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count)
 399 {
 400         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count);
 401 }
 402
 403 static void set_dsi_timings(struct drm_encoder *encoder,
 404                             const struct drm_display_mode *mode)
 405 {
 406         struct drm_device *dev = encoder->dev;
 407         struct drm_i915_private *dev_priv = dev->dev_private;
 408         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 409         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 410         int pipe = intel_crtc->pipe;
 411         unsigned int bpp = intel_crtc->config.pipe_bpp;
 412         unsigned int lane_count = intel_dsi->lane_count;
 413
 414         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
 415
 416         hactive = mode->hdisplay;
 417         hfp = mode->hsync_start - mode->hdisplay;
 418         hsync = mode->hsync_end - mode->hsync_start;
 419         hbp = mode->htotal - mode->hsync_end;
 420
 421         vfp = mode->vsync_start - mode->vdisplay;
 422         vsync = mode->vsync_end - mode->vsync_start;
 423         vbp = mode->vtotal - mode->vsync_end;
 424
 425         /* horizontal values are in terms of high speed byte clock */
 426         hactive = txbyteclkhs(hactive, bpp, lane_count);
 427         hfp = txbyteclkhs(hfp, bpp, lane_count);
 428         hsync = txbyteclkhs(hsync, bpp, lane_count);
 429         hbp = txbyteclkhs(hbp, bpp, lane_count);
 430
 431         I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
 432         I915_WRITE(MIPI_HFP_COUNT(pipe), hfp);
 433
 434         /* meaningful for video mode non-burst sync pulse mode only, can be zero
 435          * for non-burst sync events and burst modes */
 436         I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync);
 437         I915_WRITE(MIPI_HBP_COUNT(pipe), hbp);
 438
 439         /* vertical values are in terms of lines */
 440         I915_WRITE(MIPI_VFP_COUNT(pipe), vfp);
 441         I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync);
 442         I915_WRITE(MIPI_VBP_COUNT(pipe), vbp);
 443 }
 444
 445 static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 446 {
 447         struct drm_encoder *encoder = &intel_encoder->base;
 448         struct drm_device *dev = encoder->dev;
 449         struct drm_i915_private *dev_priv = dev->dev_private;
 450         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 451         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 452         struct drm_display_mode *adjusted_mode =
 453                 &intel_crtc->config.adjusted_mode;
 454         int pipe = intel_crtc->pipe;
 455         unsigned int bpp = intel_crtc->config.pipe_bpp;
 456         u32 val, tmp;
 457
 458         DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
 459
 460         /* escape clock divider, 20MHz, shared for A and C. device ready must be
 461          * off when doing this! txclkesc? */
 462         tmp = I915_READ(MIPI_CTRL(0));
 463         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 464         I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1);
 465
 466         /* read request priority is per pipe */
 467         tmp = I915_READ(MIPI_CTRL(pipe));
 468         tmp &= ~READ_REQUEST_PRIORITY_MASK;
 469         I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH);
 470
 471         /* XXX: why here, why like this? handling in irq handler?! */
 472         I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff);
 473         I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff);
 474
 475         I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg);
 476
 477         I915_WRITE(MIPI_DPI_RESOLUTION(pipe),
 478                    adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
 479                    adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
 480
 481         set_dsi_timings(encoder, adjusted_mode);
 482
 483         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
 484         if (is_cmd_mode(intel_dsi)) {
 485                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
 486                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
 487         } else {
 488                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
 489
 490                 /* XXX: cross-check bpp vs. pixel format? */
 491                 val |= intel_dsi->pixel_format;
 492         }
 493         I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val);
 494
 495         /* timeouts for recovery. one frame IIUC. if counter expires, EOT and
 496          * stop state. */
 497
 498         /*
 499          * In burst mode, value greater than one DPI line Time in byte clock
 500          * (txbyteclkhs) To timeout this timer 1+ of the above said value is
 501          * recommended.
 502          *
 503          * In non-burst mode, Value greater than one DPI frame time in byte
 504          * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
 505          * is recommended.
 506          *
 507          * In DBI only mode, value greater than one DBI frame time in byte
 508          * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
 509          * is recommended.
 510          */
 511
 512         if (is_vid_mode(intel_dsi) &&
 513             intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 514                 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
 515                            txbyteclkhs(adjusted_mode->htotal, bpp,
 516                                        intel_dsi->lane_count) + 1);
 517         } else {
 518                 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
 519                            txbyteclkhs(adjusted_mode->vtotal *
 520                                        adjusted_mode->htotal,
 521                                        bpp, intel_dsi->lane_count) + 1);
 522         }
 523         I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout);
 524         I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val);
 525         I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val);
 526
 527         /* dphy stuff */
 528
 529         /* in terms of low power clock */
 530         I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(intel_dsi->escape_clk_div, 100));
 531
 532         val = 0;
 533         if (intel_dsi->eotp_pkt == 0)
 534                 val |= EOT_DISABLE;
 535
 536         if (intel_dsi->clock_stop)
 537                 val |= CLOCKSTOP;
 538
 539         /* recovery disables */
 540         I915_WRITE(MIPI_EOT_DISABLE(pipe), val);
 541
 542         /* in terms of low power clock */
 543         I915_WRITE(MIPI_INIT_COUNT(pipe), intel_dsi->init_count);
 544
 545         /* in terms of txbyteclkhs. actual high to low switch +
 546          * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
 547          *
 548          * XXX: write MIPI_STOP_STATE_STALL?
 549          */
 550         I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe),
 551                                                 intel_dsi->hs_to_lp_count);
 552
 553         /* XXX: low power clock equivalence in terms of byte clock. the number
 554          * of byte clocks occupied in one low power clock. based on txbyteclkhs
 555          * and txclkesc. txclkesc time / txbyteclk time * (105 +
 556          * MIPI_STOP_STATE_STALL) / 105.???
 557          */
 558         I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk);
 559
 560         /* the bw essential for transmitting 16 long packets containing 252
 561          * bytes meant for dcs write memory command is programmed in this
 562          * register in terms of byte clocks. based on dsi transfer rate and the
 563          * number of lanes configured the time taken to transmit 16 long packets
 564          * in a dsi stream varies. */
 565         I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer);
 566
 567         I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe),
 568                    intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
 569                    intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
 570
 571         if (is_vid_mode(intel_dsi))
 572                 /* Some panels might have resolution which is not a multiple of
 573                  * 64 like 1366 x 768. Enable RANDOM resolution support for such
 574                  * panels by default */
 575                 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
 576                                 intel_dsi->video_frmt_cfg_bits |
 577                                 intel_dsi->video_mode_format |
 578                                 IP_TG_CONFIG |
 579                                 RANDOM_DPI_DISPLAY_RESOLUTION);
 580 }
 581
 582 static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
 583 {
 584         DRM_DEBUG_KMS("\n");
 585
 586         intel_dsi_prepare(encoder);
 587
 588         vlv_enable_dsi_pll(encoder);
 589 }
 590
 591 static enum drm_connector_status
 592 intel_dsi_detect(struct drm_connector *connector, bool force)
 593 {
 594         struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
 595         struct intel_encoder *intel_encoder = &intel_dsi->base;
 596         enum intel_display_power_domain power_domain;
 597         enum drm_connector_status connector_status;
 598         struct drm_i915_private *dev_priv = intel_encoder->base.dev->dev_private;
 599
 600         DRM_DEBUG_KMS("\n");
 601         power_domain = intel_display_port_power_domain(intel_encoder);
 602
 603         intel_display_power_get(dev_priv, power_domain);
 604         connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
 605         intel_display_power_put(dev_priv, power_domain);
 606
 607         return connector_status;
 608 }
 609
 610 static int intel_dsi_get_modes(struct drm_connector *connector)
 611 {
 612         struct intel_connector *intel_connector = to_intel_connector(connector);
 613         struct drm_display_mode *mode;
 614
 615         DRM_DEBUG_KMS("\n");
 616
 617         if (!intel_connector->panel.fixed_mode) {
 618                 DRM_DEBUG_KMS("no fixed mode\n");
 619                 return 0;
 620         }
 621
 622         mode = drm_mode_duplicate(connector->dev,
 623                                   intel_connector->panel.fixed_mode);
 624         if (!mode) {
 625                 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
 626                 return 0;
 627         }
 628
 629         drm_mode_probed_add(connector, mode);
 630         return 1;
 631 }
 632
 633 static void intel_dsi_destroy(struct drm_connector *connector)
 634 {
 635         struct intel_connector *intel_connector = to_intel_connector(connector);
 636
 637         DRM_DEBUG_KMS("\n");
 638         intel_panel_fini(&intel_connector->panel);
 639         drm_connector_cleanup(connector);
 640         kfree(connector);
 641 }
 642
 643 static const struct drm_encoder_funcs intel_dsi_funcs = {
 644         .destroy = intel_encoder_destroy,
 645 };
 646
 647 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
 648         .get_modes = intel_dsi_get_modes,
 649         .mode_valid = intel_dsi_mode_valid,
 650         .best_encoder = intel_best_encoder,
 651 };
 652
 653 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
 654         .dpms = intel_connector_dpms,
 655         .detect = intel_dsi_detect,
 656         .destroy = intel_dsi_destroy,
 657         .fill_modes = drm_helper_probe_single_connector_modes,
 658 };
 659
 660 void intel_dsi_init(struct drm_device *dev)
 661 {
 662         struct intel_dsi *intel_dsi;
 663         struct intel_encoder *intel_encoder;
 664         struct drm_encoder *encoder;
 665         struct intel_connector *intel_connector;
 666         struct drm_connector *connector;
 667         struct drm_display_mode *fixed_mode = NULL;
 668         struct drm_i915_private *dev_priv = dev->dev_private;
 669         const struct intel_dsi_device *dsi;
 670         unsigned int i;
 671
 672         DRM_DEBUG_KMS("\n");
 673
 674         /* There is no detection method for MIPI so rely on VBT */
 675         if (!dev_priv->vbt.has_mipi)
 676                 return;
 677
 678         if (IS_VALLEYVIEW(dev)) {
 679                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
 680         } else {
 681                 DRM_ERROR("Unsupported Mipi device to reg base");
 682                 return;
 683         }
 684
 685         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
 686         if (!intel_dsi)
 687                 return;
 688
 689         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
 690         if (!intel_connector) {
 691                 kfree(intel_dsi);
 692                 return;
 693         }
 694
 695         intel_encoder = &intel_dsi->base;
 696         encoder = &intel_encoder->base;
 697         intel_dsi->attached_connector = intel_connector;
 698
 699         connector = &intel_connector->base;
 700
 701         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
 702
 703         /* XXX: very likely not all of these are needed */
 704         intel_encoder->hot_plug = intel_dsi_hot_plug;
 705         intel_encoder->compute_config = intel_dsi_compute_config;
 706         intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
 707         intel_encoder->pre_enable = intel_dsi_pre_enable;
 708         intel_encoder->enable = intel_dsi_enable_nop;
 709         intel_encoder->disable = intel_dsi_pre_disable;
 710         intel_encoder->post_disable = intel_dsi_post_disable;
 711         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
 712         intel_encoder->get_config = intel_dsi_get_config;
 713
 714         intel_connector->get_hw_state = intel_connector_get_hw_state;
 715         intel_connector->unregister = intel_connector_unregister;
 716
 717         for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) {
 718                 dsi = &intel_dsi_devices[i];
 719                 intel_dsi->dev = *dsi;
 720
 721                 if (dsi->dev_ops->init(&intel_dsi->dev))
 722                         break;
 723         }
 724
 725         if (i == ARRAY_SIZE(intel_dsi_devices)) {
 726                 DRM_DEBUG_KMS("no device found\n");
 727                 goto err;
 728         }
 729
 730         intel_encoder->type = INTEL_OUTPUT_DSI;
 731         intel_encoder->crtc_mask = (1 << 0); /* XXX */
 732
 733         intel_encoder->cloneable = 0;
 734         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
 735                            DRM_MODE_CONNECTOR_DSI);
 736
 737         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
 738
 739         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
 740         connector->interlace_allowed = false;
 741         connector->doublescan_allowed = false;
 742
 743         intel_connector_attach_encoder(intel_connector, intel_encoder);
 744
 745         drm_connector_register(connector);
 746
 747         fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev);
 748         if (!fixed_mode) {
 749                 DRM_DEBUG_KMS("no fixed mode\n");
 750                 goto err;
 751         }
 752
 753         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
 754         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
 755
 756         return;
 757
 758 err:
 759         drm_encoder_cleanup(&intel_encoder->base);
 760         kfree(intel_dsi);
 761         kfree(intel_connector);
 762 }