2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
23 * Author: Jani Nikula <jani.nikula@intel.com>
27 #include <drm/drm_crtc.h>
28 #include <drm/drm_edid.h>
29 #include <drm/i915_drm.h>
30 #include <linux/slab.h>
32 #include "intel_drv.h"
33 #include "intel_dsi.h"
34 #include "intel_dsi_cmd.h"
36 /* the sub-encoders aka panel drivers */
37 static const struct intel_dsi_device intel_dsi_devices
[] = {
40 static void band_gap_reset(struct drm_i915_private
*dev_priv
)
42 mutex_lock(&dev_priv
->dpio_lock
);
44 vlv_flisdsi_write(dev_priv
, 0x08, 0x0001);
45 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0005);
46 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0025);
48 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0000);
49 vlv_flisdsi_write(dev_priv
, 0x08, 0x0000);
51 mutex_unlock(&dev_priv
->dpio_lock
);
54 static struct intel_dsi
*intel_attached_dsi(struct drm_connector
*connector
)
56 return container_of(intel_attached_encoder(connector
),
57 struct intel_dsi
, base
);
60 static inline bool is_vid_mode(struct intel_dsi
*intel_dsi
)
62 return intel_dsi
->dev
.type
== INTEL_DSI_VIDEO_MODE
;
65 static inline bool is_cmd_mode(struct intel_dsi
*intel_dsi
)
67 return intel_dsi
->dev
.type
== INTEL_DSI_COMMAND_MODE
;
70 static void intel_dsi_hot_plug(struct intel_encoder
*encoder
)
75 static bool intel_dsi_compute_config(struct intel_encoder
*encoder
,
76 struct intel_crtc_config
*config
)
78 struct intel_dsi
*intel_dsi
= container_of(encoder
, struct intel_dsi
,
80 struct intel_connector
*intel_connector
= intel_dsi
->attached_connector
;
81 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
82 struct drm_display_mode
*adjusted_mode
= &config
->adjusted_mode
;
83 struct drm_display_mode
*mode
= &config
->requested_mode
;
88 intel_fixed_panel_mode(fixed_mode
, adjusted_mode
);
90 if (intel_dsi
->dev
.dev_ops
->mode_fixup
)
91 return intel_dsi
->dev
.dev_ops
->mode_fixup(&intel_dsi
->dev
,
97 static void intel_dsi_pre_pll_enable(struct intel_encoder
*encoder
)
101 vlv_enable_dsi_pll(encoder
);
104 static void intel_dsi_device_ready(struct intel_encoder
*encoder
)
106 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
107 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
108 int pipe
= intel_crtc
->pipe
;
113 val
= I915_READ(MIPI_PORT_CTRL(pipe
));
114 I915_WRITE(MIPI_PORT_CTRL(pipe
), val
| LP_OUTPUT_HOLD
);
115 usleep_range(1000, 1500);
116 I915_WRITE(MIPI_DEVICE_READY(pipe
), DEVICE_READY
| ULPS_STATE_EXIT
);
117 usleep_range(2000, 2500);
118 I915_WRITE(MIPI_DEVICE_READY(pipe
), DEVICE_READY
);
119 usleep_range(2000, 2500);
120 I915_WRITE(MIPI_DEVICE_READY(pipe
), 0x00);
121 usleep_range(2000, 2500);
122 I915_WRITE(MIPI_DEVICE_READY(pipe
), DEVICE_READY
);
123 usleep_range(2000, 2500);
125 static void intel_dsi_pre_enable(struct intel_encoder
*encoder
)
127 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
131 if (intel_dsi
->dev
.dev_ops
->panel_reset
)
132 intel_dsi
->dev
.dev_ops
->panel_reset(&intel_dsi
->dev
);
134 /* put device in ready state */
135 intel_dsi_device_ready(encoder
);
137 if (intel_dsi
->dev
.dev_ops
->send_otp_cmds
)
138 intel_dsi
->dev
.dev_ops
->send_otp_cmds(&intel_dsi
->dev
);
141 static void intel_dsi_enable(struct intel_encoder
*encoder
)
143 struct drm_device
*dev
= encoder
->base
.dev
;
144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
145 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
146 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
147 int pipe
= intel_crtc
->pipe
;
152 if (is_cmd_mode(intel_dsi
))
153 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe
), 8 * 4);
155 msleep(20); /* XXX */
156 dpi_send_cmd(intel_dsi
, TURN_ON
);
159 /* assert ip_tg_enable signal */
160 temp
= I915_READ(MIPI_PORT_CTRL(pipe
)) & ~LANE_CONFIGURATION_MASK
;
161 temp
= temp
| intel_dsi
->port_bits
;
162 I915_WRITE(MIPI_PORT_CTRL(pipe
), temp
| DPI_ENABLE
);
163 POSTING_READ(MIPI_PORT_CTRL(pipe
));
166 if (intel_dsi
->dev
.dev_ops
->enable
)
167 intel_dsi
->dev
.dev_ops
->enable(&intel_dsi
->dev
);
170 static void intel_dsi_disable(struct intel_encoder
*encoder
)
172 struct drm_device
*dev
= encoder
->base
.dev
;
173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
174 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
175 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
176 int pipe
= intel_crtc
->pipe
;
181 if (is_vid_mode(intel_dsi
)) {
182 dpi_send_cmd(intel_dsi
, SHUTDOWN
);
185 /* de-assert ip_tg_enable signal */
186 temp
= I915_READ(MIPI_PORT_CTRL(pipe
));
187 I915_WRITE(MIPI_PORT_CTRL(pipe
), temp
& ~DPI_ENABLE
);
188 POSTING_READ(MIPI_PORT_CTRL(pipe
));
193 /* if disable packets are sent before sending shutdown packet then in
194 * some next enable sequence send turn on packet error is observed */
195 if (intel_dsi
->dev
.dev_ops
->disable
)
196 intel_dsi
->dev
.dev_ops
->disable(&intel_dsi
->dev
);
199 static void intel_dsi_clear_device_ready(struct intel_encoder
*encoder
)
201 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
202 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
203 int pipe
= intel_crtc
->pipe
;
208 I915_WRITE(MIPI_DEVICE_READY(pipe
), ULPS_STATE_ENTER
);
209 usleep_range(2000, 2500);
211 I915_WRITE(MIPI_DEVICE_READY(pipe
), ULPS_STATE_EXIT
);
212 usleep_range(2000, 2500);
214 I915_WRITE(MIPI_DEVICE_READY(pipe
), ULPS_STATE_ENTER
);
215 usleep_range(2000, 2500);
217 val
= I915_READ(MIPI_PORT_CTRL(pipe
));
218 I915_WRITE(MIPI_PORT_CTRL(pipe
), val
& ~LP_OUTPUT_HOLD
);
219 usleep_range(1000, 1500);
221 if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe
)) & AFE_LATCHOUT
)
223 DRM_ERROR("DSI LP not going Low\n");
225 I915_WRITE(MIPI_DEVICE_READY(pipe
), 0x00);
226 usleep_range(2000, 2500);
228 vlv_disable_dsi_pll(encoder
);
230 static void intel_dsi_post_disable(struct intel_encoder
*encoder
)
232 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
236 intel_dsi_clear_device_ready(encoder
);
238 if (intel_dsi
->dev
.dev_ops
->disable_panel_power
)
239 intel_dsi
->dev
.dev_ops
->disable_panel_power(&intel_dsi
->dev
);
242 static bool intel_dsi_get_hw_state(struct intel_encoder
*encoder
,
245 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
246 enum intel_display_power_domain power_domain
;
252 power_domain
= intel_display_port_power_domain(encoder
);
253 if (!intel_display_power_enabled(dev_priv
, power_domain
))
256 /* XXX: this only works for one DSI output */
257 for (p
= PIPE_A
; p
<= PIPE_B
; p
++) {
258 port
= I915_READ(MIPI_PORT_CTRL(p
));
259 func
= I915_READ(MIPI_DSI_FUNC_PRG(p
));
261 if ((port
& DPI_ENABLE
) || (func
& CMD_MODE_DATA_WIDTH_MASK
)) {
262 if (I915_READ(MIPI_DEVICE_READY(p
)) & DEVICE_READY
) {
272 static void intel_dsi_get_config(struct intel_encoder
*encoder
,
273 struct intel_crtc_config
*pipe_config
)
277 /* XXX: read flags, set to adjusted_mode */
280 static enum drm_mode_status
281 intel_dsi_mode_valid(struct drm_connector
*connector
,
282 struct drm_display_mode
*mode
)
284 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
285 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
286 struct intel_dsi
*intel_dsi
= intel_attached_dsi(connector
);
290 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
) {
291 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
292 return MODE_NO_DBLESCAN
;
296 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
298 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
302 return intel_dsi
->dev
.dev_ops
->mode_valid(&intel_dsi
->dev
, mode
);
305 /* return txclkesc cycles in terms of divider and duration in us */
306 static u16
txclkesc(u32 divider
, unsigned int us
)
309 case ESCAPE_CLOCK_DIVIDER_1
:
312 case ESCAPE_CLOCK_DIVIDER_2
:
314 case ESCAPE_CLOCK_DIVIDER_4
:
319 /* return pixels in terms of txbyteclkhs */
320 static u16
txbyteclkhs(u16 pixels
, int bpp
, int lane_count
)
322 return DIV_ROUND_UP(DIV_ROUND_UP(pixels
* bpp
, 8), lane_count
);
325 static void set_dsi_timings(struct drm_encoder
*encoder
,
326 const struct drm_display_mode
*mode
)
328 struct drm_device
*dev
= encoder
->dev
;
329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
330 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
331 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
332 int pipe
= intel_crtc
->pipe
;
333 unsigned int bpp
= intel_crtc
->config
.pipe_bpp
;
334 unsigned int lane_count
= intel_dsi
->lane_count
;
336 u16 hactive
, hfp
, hsync
, hbp
, vfp
, vsync
, vbp
;
338 hactive
= mode
->hdisplay
;
339 hfp
= mode
->hsync_start
- mode
->hdisplay
;
340 hsync
= mode
->hsync_end
- mode
->hsync_start
;
341 hbp
= mode
->htotal
- mode
->hsync_end
;
343 vfp
= mode
->vsync_start
- mode
->vdisplay
;
344 vsync
= mode
->vsync_end
- mode
->vsync_start
;
345 vbp
= mode
->vtotal
- mode
->vsync_end
;
347 /* horizontal values are in terms of high speed byte clock */
348 hactive
= txbyteclkhs(hactive
, bpp
, lane_count
);
349 hfp
= txbyteclkhs(hfp
, bpp
, lane_count
);
350 hsync
= txbyteclkhs(hsync
, bpp
, lane_count
);
351 hbp
= txbyteclkhs(hbp
, bpp
, lane_count
);
353 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe
), hactive
);
354 I915_WRITE(MIPI_HFP_COUNT(pipe
), hfp
);
356 /* meaningful for video mode non-burst sync pulse mode only, can be zero
357 * for non-burst sync events and burst modes */
358 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe
), hsync
);
359 I915_WRITE(MIPI_HBP_COUNT(pipe
), hbp
);
361 /* vertical values are in terms of lines */
362 I915_WRITE(MIPI_VFP_COUNT(pipe
), vfp
);
363 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe
), vsync
);
364 I915_WRITE(MIPI_VBP_COUNT(pipe
), vbp
);
367 static void intel_dsi_mode_set(struct intel_encoder
*intel_encoder
)
369 struct drm_encoder
*encoder
= &intel_encoder
->base
;
370 struct drm_device
*dev
= encoder
->dev
;
371 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
372 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
373 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
374 struct drm_display_mode
*adjusted_mode
=
375 &intel_crtc
->config
.adjusted_mode
;
376 int pipe
= intel_crtc
->pipe
;
377 unsigned int bpp
= intel_crtc
->config
.pipe_bpp
;
380 DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe
));
382 /* XXX: Location of the call */
383 band_gap_reset(dev_priv
);
385 /* escape clock divider, 20MHz, shared for A and C. device ready must be
386 * off when doing this! txclkesc? */
387 tmp
= I915_READ(MIPI_CTRL(0));
388 tmp
&= ~ESCAPE_CLOCK_DIVIDER_MASK
;
389 I915_WRITE(MIPI_CTRL(0), tmp
| ESCAPE_CLOCK_DIVIDER_1
);
391 /* read request priority is per pipe */
392 tmp
= I915_READ(MIPI_CTRL(pipe
));
393 tmp
&= ~READ_REQUEST_PRIORITY_MASK
;
394 I915_WRITE(MIPI_CTRL(pipe
), tmp
| READ_REQUEST_PRIORITY_HIGH
);
396 /* XXX: why here, why like this? handling in irq handler?! */
397 I915_WRITE(MIPI_INTR_STAT(pipe
), 0xffffffff);
398 I915_WRITE(MIPI_INTR_EN(pipe
), 0xffffffff);
400 I915_WRITE(MIPI_DPHY_PARAM(pipe
), intel_dsi
->dphy_reg
);
402 I915_WRITE(MIPI_DPI_RESOLUTION(pipe
),
403 adjusted_mode
->vdisplay
<< VERTICAL_ADDRESS_SHIFT
|
404 adjusted_mode
->hdisplay
<< HORIZONTAL_ADDRESS_SHIFT
);
406 set_dsi_timings(encoder
, adjusted_mode
);
408 val
= intel_dsi
->lane_count
<< DATA_LANES_PRG_REG_SHIFT
;
409 if (is_cmd_mode(intel_dsi
)) {
410 val
|= intel_dsi
->channel
<< CMD_MODE_CHANNEL_NUMBER_SHIFT
;
411 val
|= CMD_MODE_DATA_WIDTH_8_BIT
; /* XXX */
413 val
|= intel_dsi
->channel
<< VID_MODE_CHANNEL_NUMBER_SHIFT
;
415 /* XXX: cross-check bpp vs. pixel format? */
416 val
|= intel_dsi
->pixel_format
;
418 I915_WRITE(MIPI_DSI_FUNC_PRG(pipe
), val
);
420 /* timeouts for recovery. one frame IIUC. if counter expires, EOT and
424 * In burst mode, value greater than one DPI line Time in byte clock
425 * (txbyteclkhs) To timeout this timer 1+ of the above said value is
428 * In non-burst mode, Value greater than one DPI frame time in byte
429 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
432 * In DBI only mode, value greater than one DBI frame time in byte
433 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
437 if (is_vid_mode(intel_dsi
) &&
438 intel_dsi
->video_mode_format
== VIDEO_MODE_BURST
) {
439 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe
),
440 txbyteclkhs(adjusted_mode
->htotal
, bpp
,
441 intel_dsi
->lane_count
) + 1);
443 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe
),
444 txbyteclkhs(adjusted_mode
->vtotal
*
445 adjusted_mode
->htotal
,
446 bpp
, intel_dsi
->lane_count
) + 1);
448 I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe
), intel_dsi
->lp_rx_timeout
);
449 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe
), intel_dsi
->turn_arnd_val
);
450 I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe
), intel_dsi
->rst_timer_val
);
454 /* in terms of low power clock */
455 I915_WRITE(MIPI_INIT_COUNT(pipe
), txclkesc(ESCAPE_CLOCK_DIVIDER_1
, 100));
457 /* recovery disables */
458 I915_WRITE(MIPI_EOT_DISABLE(pipe
), intel_dsi
->eot_disable
);
460 /* in terms of txbyteclkhs. actual high to low switch +
461 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
463 * XXX: write MIPI_STOP_STATE_STALL?
465 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe
),
466 intel_dsi
->hs_to_lp_count
);
468 /* XXX: low power clock equivalence in terms of byte clock. the number
469 * of byte clocks occupied in one low power clock. based on txbyteclkhs
470 * and txclkesc. txclkesc time / txbyteclk time * (105 +
471 * MIPI_STOP_STATE_STALL) / 105.???
473 I915_WRITE(MIPI_LP_BYTECLK(pipe
), intel_dsi
->lp_byte_clk
);
475 /* the bw essential for transmitting 16 long packets containing 252
476 * bytes meant for dcs write memory command is programmed in this
477 * register in terms of byte clocks. based on dsi transfer rate and the
478 * number of lanes configured the time taken to transmit 16 long packets
479 * in a dsi stream varies. */
480 I915_WRITE(MIPI_DBI_BW_CTRL(pipe
), intel_dsi
->bw_timer
);
482 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe
),
483 intel_dsi
->clk_lp_to_hs_count
<< LP_HS_SSW_CNT_SHIFT
|
484 intel_dsi
->clk_hs_to_lp_count
<< HS_LP_PWR_SW_CNT_SHIFT
);
486 if (is_vid_mode(intel_dsi
))
487 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe
),
488 intel_dsi
->video_frmt_cfg_bits
|
489 intel_dsi
->video_mode_format
);
492 static enum drm_connector_status
493 intel_dsi_detect(struct drm_connector
*connector
, bool force
)
495 struct intel_dsi
*intel_dsi
= intel_attached_dsi(connector
);
496 struct intel_encoder
*intel_encoder
= &intel_dsi
->base
;
497 enum intel_display_power_domain power_domain
;
498 enum drm_connector_status connector_status
;
499 struct drm_i915_private
*dev_priv
= intel_encoder
->base
.dev
->dev_private
;
502 power_domain
= intel_display_port_power_domain(intel_encoder
);
504 intel_display_power_get(dev_priv
, power_domain
);
505 connector_status
= intel_dsi
->dev
.dev_ops
->detect(&intel_dsi
->dev
);
506 intel_display_power_put(dev_priv
, power_domain
);
508 return connector_status
;
511 static int intel_dsi_get_modes(struct drm_connector
*connector
)
513 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
514 struct drm_display_mode
*mode
;
518 if (!intel_connector
->panel
.fixed_mode
) {
519 DRM_DEBUG_KMS("no fixed mode\n");
523 mode
= drm_mode_duplicate(connector
->dev
,
524 intel_connector
->panel
.fixed_mode
);
526 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
530 drm_mode_probed_add(connector
, mode
);
534 static void intel_dsi_destroy(struct drm_connector
*connector
)
536 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
539 intel_panel_fini(&intel_connector
->panel
);
540 drm_connector_cleanup(connector
);
544 static const struct drm_encoder_funcs intel_dsi_funcs
= {
545 .destroy
= intel_encoder_destroy
,
548 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs
= {
549 .get_modes
= intel_dsi_get_modes
,
550 .mode_valid
= intel_dsi_mode_valid
,
551 .best_encoder
= intel_best_encoder
,
554 static const struct drm_connector_funcs intel_dsi_connector_funcs
= {
555 .dpms
= intel_connector_dpms
,
556 .detect
= intel_dsi_detect
,
557 .destroy
= intel_dsi_destroy
,
558 .fill_modes
= drm_helper_probe_single_connector_modes
,
561 bool intel_dsi_init(struct drm_device
*dev
)
563 struct intel_dsi
*intel_dsi
;
564 struct intel_encoder
*intel_encoder
;
565 struct drm_encoder
*encoder
;
566 struct intel_connector
*intel_connector
;
567 struct drm_connector
*connector
;
568 struct drm_display_mode
*fixed_mode
= NULL
;
569 const struct intel_dsi_device
*dsi
;
574 intel_dsi
= kzalloc(sizeof(*intel_dsi
), GFP_KERNEL
);
578 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
579 if (!intel_connector
) {
584 intel_encoder
= &intel_dsi
->base
;
585 encoder
= &intel_encoder
->base
;
586 intel_dsi
->attached_connector
= intel_connector
;
588 connector
= &intel_connector
->base
;
590 drm_encoder_init(dev
, encoder
, &intel_dsi_funcs
, DRM_MODE_ENCODER_DSI
);
592 /* XXX: very likely not all of these are needed */
593 intel_encoder
->hot_plug
= intel_dsi_hot_plug
;
594 intel_encoder
->compute_config
= intel_dsi_compute_config
;
595 intel_encoder
->pre_pll_enable
= intel_dsi_pre_pll_enable
;
596 intel_encoder
->pre_enable
= intel_dsi_pre_enable
;
597 intel_encoder
->enable
= intel_dsi_enable
;
598 intel_encoder
->mode_set
= intel_dsi_mode_set
;
599 intel_encoder
->disable
= intel_dsi_disable
;
600 intel_encoder
->post_disable
= intel_dsi_post_disable
;
601 intel_encoder
->get_hw_state
= intel_dsi_get_hw_state
;
602 intel_encoder
->get_config
= intel_dsi_get_config
;
604 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
605 intel_connector
->unregister
= intel_connector_unregister
;
607 for (i
= 0; i
< ARRAY_SIZE(intel_dsi_devices
); i
++) {
608 dsi
= &intel_dsi_devices
[i
];
609 intel_dsi
->dev
= *dsi
;
611 if (dsi
->dev_ops
->init(&intel_dsi
->dev
))
615 if (i
== ARRAY_SIZE(intel_dsi_devices
)) {
616 DRM_DEBUG_KMS("no device found\n");
620 intel_encoder
->type
= INTEL_OUTPUT_DSI
;
621 intel_encoder
->crtc_mask
= (1 << 0); /* XXX */
623 intel_encoder
->cloneable
= 0;
624 drm_connector_init(dev
, connector
, &intel_dsi_connector_funcs
,
625 DRM_MODE_CONNECTOR_DSI
);
627 drm_connector_helper_add(connector
, &intel_dsi_connector_helper_funcs
);
629 connector
->display_info
.subpixel_order
= SubPixelHorizontalRGB
; /*XXX*/
630 connector
->interlace_allowed
= false;
631 connector
->doublescan_allowed
= false;
633 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
635 drm_sysfs_connector_add(connector
);
637 fixed_mode
= dsi
->dev_ops
->get_modes(&intel_dsi
->dev
);
639 DRM_DEBUG_KMS("no fixed mode\n");
643 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
644 intel_panel_init(&intel_connector
->panel
, fixed_mode
, NULL
);
649 drm_encoder_cleanup(&intel_encoder
->base
);
651 kfree(intel_connector
);