drivers/gpu/drm/i915/intel_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc.h>
  28 #include <drm/drm_edid.h>
  29 #include <drm/i915_drm.h>
  30 #include <linux/slab.h>
  31 #include "i915_drv.h"
  32 #include "intel_drv.h"
  33 #include "intel_dsi.h"
  34 #include "intel_dsi_cmd.h"
  35
  36 /* the sub-encoders aka panel drivers */
  37 static const struct intel_dsi_device intel_dsi_devices[] = {
  38 };
  39
  40
  41 static void vlv_cck_modify(struct drm_i915_private *dev_priv, u32 reg, u32 val,
  42                            u32 mask)
  43 {
  44         u32 tmp = vlv_cck_read(dev_priv, reg);
  45         tmp &= ~mask;
  46         tmp |= val;
  47         vlv_cck_write(dev_priv, reg, tmp);
  48 }
  49
  50 static void band_gap_wa(struct drm_i915_private *dev_priv)
  51 {
  52         mutex_lock(&dev_priv->dpio_lock);
  53
  54         /* Enable bandgap fix in GOP driver */
  55         vlv_cck_modify(dev_priv, 0x6D, 0x00010000, 0x00030000);
  56         msleep(20);
  57         vlv_cck_modify(dev_priv, 0x6E, 0x00010000, 0x00030000);
  58         msleep(20);
  59         vlv_cck_modify(dev_priv, 0x6F, 0x00010000, 0x00030000);
  60         msleep(20);
  61         vlv_cck_modify(dev_priv, 0x00, 0x00008000, 0x00008000);
  62         msleep(20);
  63         vlv_cck_modify(dev_priv, 0x00, 0x00000000, 0x00008000);
  64         msleep(20);
  65
  66         /* Turn Display Trunk on */
  67         vlv_cck_modify(dev_priv, 0x6B, 0x00020000, 0x00030000);
  68         msleep(20);
  69
  70         vlv_cck_modify(dev_priv, 0x6C, 0x00020000, 0x00030000);
  71         msleep(20);
  72
  73         vlv_cck_modify(dev_priv, 0x6D, 0x00020000, 0x00030000);
  74         msleep(20);
  75         vlv_cck_modify(dev_priv, 0x6E, 0x00020000, 0x00030000);
  76         msleep(20);
  77         vlv_cck_modify(dev_priv, 0x6F, 0x00020000, 0x00030000);
  78
  79         mutex_unlock(&dev_priv->dpio_lock);
  80
  81         /* Need huge delay, otherwise clock is not stable */
  82         msleep(100);
  83 }
  84
  85 static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
  86 {
  87         return container_of(intel_attached_encoder(connector),
  88                             struct intel_dsi, base);
  89 }
  90
  91 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
  92 {
  93         return intel_dsi->dev.type == INTEL_DSI_VIDEO_MODE;
  94 }
  95
  96 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
  97 {
  98         return intel_dsi->dev.type == INTEL_DSI_COMMAND_MODE;
  99 }
 100
 101 static void intel_dsi_hot_plug(struct intel_encoder *encoder)
 102 {
 103         DRM_DEBUG_KMS("\n");
 104 }
 105
 106 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 107                                      struct intel_crtc_config *config)
 108 {
 109         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 110                                                    base);
 111         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 112         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 113         struct drm_display_mode *adjusted_mode = &config->adjusted_mode;
 114         struct drm_display_mode *mode = &config->requested_mode;
 115
 116         DRM_DEBUG_KMS("\n");
 117
 118         if (fixed_mode)
 119                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 120
 121         if (intel_dsi->dev.dev_ops->mode_fixup)
 122                 return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev,
 123                                                           mode, adjusted_mode);
 124
 125         return true;
 126 }
 127
 128 static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
 129 {
 130         DRM_DEBUG_KMS("\n");
 131
 132         vlv_enable_dsi_pll(encoder);
 133 }
 134
 135 static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 136 {
 137         DRM_DEBUG_KMS("\n");
 138 }
 139
 140 static void intel_dsi_enable(struct intel_encoder *encoder)
 141 {
 142         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 143         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 144         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 145         int pipe = intel_crtc->pipe;
 146         u32 temp;
 147
 148         DRM_DEBUG_KMS("\n");
 149
 150         if (intel_dsi->dev.dev_ops->panel_reset)
 151                 intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
 152
 153         temp = I915_READ(MIPI_DEVICE_READY(pipe));
 154         if ((temp & DEVICE_READY) == 0) {
 155                 temp &= ~ULPS_STATE_MASK;
 156                 I915_WRITE(MIPI_DEVICE_READY(pipe), temp | DEVICE_READY);
 157         } else if (temp & ULPS_STATE_MASK) {
 158                 temp &= ~ULPS_STATE_MASK;
 159                 I915_WRITE(MIPI_DEVICE_READY(pipe), temp | ULPS_STATE_EXIT);
 160                 /*
 161                  * We need to ensure that there is a minimum of 1 ms time
 162                  * available before clearing the UPLS exit state.
 163                  */
 164                 msleep(2);
 165                 I915_WRITE(MIPI_DEVICE_READY(pipe), temp);
 166         }
 167
 168         if (intel_dsi->dev.dev_ops->send_otp_cmds)
 169                 intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev);
 170
 171         if (is_cmd_mode(intel_dsi))
 172                 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
 173
 174         if (is_vid_mode(intel_dsi)) {
 175                 msleep(20); /* XXX */
 176                 dpi_send_cmd(intel_dsi, TURN_ON);
 177                 msleep(100);
 178
 179                 /* assert ip_tg_enable signal */
 180                 temp = I915_READ(MIPI_PORT_CTRL(pipe));
 181                 I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
 182                 POSTING_READ(MIPI_PORT_CTRL(pipe));
 183         }
 184
 185         if (intel_dsi->dev.dev_ops->enable)
 186                 intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
 187 }
 188
 189 static void intel_dsi_disable(struct intel_encoder *encoder)
 190 {
 191         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 192         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 193         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 194         int pipe = intel_crtc->pipe;
 195         u32 temp;
 196
 197         DRM_DEBUG_KMS("\n");
 198
 199         intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
 200
 201         if (is_vid_mode(intel_dsi)) {
 202                 dpi_send_cmd(intel_dsi, SHUTDOWN);
 203                 msleep(10);
 204
 205                 /* de-assert ip_tg_enable signal */
 206                 temp = I915_READ(MIPI_PORT_CTRL(pipe));
 207                 I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
 208                 POSTING_READ(MIPI_PORT_CTRL(pipe));
 209
 210                 msleep(2);
 211         }
 212
 213         temp = I915_READ(MIPI_DEVICE_READY(pipe));
 214         if (temp & DEVICE_READY) {
 215                 temp &= ~DEVICE_READY;
 216                 temp &= ~ULPS_STATE_MASK;
 217                 I915_WRITE(MIPI_DEVICE_READY(pipe), temp);
 218         }
 219 }
 220
 221 static void intel_dsi_post_disable(struct intel_encoder *encoder)
 222 {
 223         DRM_DEBUG_KMS("\n");
 224
 225         vlv_disable_dsi_pll(encoder);
 226 }
 227
 228 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 229                                    enum pipe *pipe)
 230 {
 231         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 232         u32 port, func;
 233         enum pipe p;
 234
 235         DRM_DEBUG_KMS("\n");
 236
 237         /* XXX: this only works for one DSI output */
 238         for (p = PIPE_A; p <= PIPE_B; p++) {
 239                 port = I915_READ(MIPI_PORT_CTRL(p));
 240                 func = I915_READ(MIPI_DSI_FUNC_PRG(p));
 241
 242                 if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
 243                         if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) {
 244                                 *pipe = p;
 245                                 return true;
 246                         }
 247                 }
 248         }
 249
 250         return false;
 251 }
 252
 253 static void intel_dsi_get_config(struct intel_encoder *encoder,
 254                                  struct intel_crtc_config *pipe_config)
 255 {
 256         DRM_DEBUG_KMS("\n");
 257
 258         /* XXX: read flags, set to adjusted_mode */
 259 }
 260
 261 static enum drm_mode_status
 262 intel_dsi_mode_valid(struct drm_connector *connector,
 263                      struct drm_display_mode *mode)
 264 {
 265         struct intel_connector *intel_connector = to_intel_connector(connector);
 266         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 267         struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
 268
 269         DRM_DEBUG_KMS("\n");
 270
 271         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 272                 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
 273                 return MODE_NO_DBLESCAN;
 274         }
 275
 276         if (fixed_mode) {
 277                 if (mode->hdisplay > fixed_mode->hdisplay)
 278                         return MODE_PANEL;
 279                 if (mode->vdisplay > fixed_mode->vdisplay)
 280                         return MODE_PANEL;
 281         }
 282
 283         return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode);
 284 }
 285
 286 /* return txclkesc cycles in terms of divider and duration in us */
 287 static u16 txclkesc(u32 divider, unsigned int us)
 288 {
 289         switch (divider) {
 290         case ESCAPE_CLOCK_DIVIDER_1:
 291         default:
 292                 return 20 * us;
 293         case ESCAPE_CLOCK_DIVIDER_2:
 294                 return 10 * us;
 295         case ESCAPE_CLOCK_DIVIDER_4:
 296                 return 5 * us;
 297         }
 298 }
 299
 300 /* return pixels in terms of txbyteclkhs */
 301 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count)
 302 {
 303         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count);
 304 }
 305
 306 static void set_dsi_timings(struct drm_encoder *encoder,
 307                             const struct drm_display_mode *mode)
 308 {
 309         struct drm_device *dev = encoder->dev;
 310         struct drm_i915_private *dev_priv = dev->dev_private;
 311         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 312         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 313         int pipe = intel_crtc->pipe;
 314         unsigned int bpp = intel_crtc->config.pipe_bpp;
 315         unsigned int lane_count = intel_dsi->lane_count;
 316
 317         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
 318
 319         hactive = mode->hdisplay;
 320         hfp = mode->hsync_start - mode->hdisplay;
 321         hsync = mode->hsync_end - mode->hsync_start;
 322         hbp = mode->htotal - mode->hsync_end;
 323
 324         vfp = mode->vsync_start - mode->vdisplay;
 325         vsync = mode->vsync_end - mode->vsync_start;
 326         vbp = mode->vtotal - mode->vsync_end;
 327
 328         /* horizontal values are in terms of high speed byte clock */
 329         hactive = txbyteclkhs(hactive, bpp, lane_count);
 330         hfp = txbyteclkhs(hfp, bpp, lane_count);
 331         hsync = txbyteclkhs(hsync, bpp, lane_count);
 332         hbp = txbyteclkhs(hbp, bpp, lane_count);
 333
 334         I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
 335         I915_WRITE(MIPI_HFP_COUNT(pipe), hfp);
 336
 337         /* meaningful for video mode non-burst sync pulse mode only, can be zero
 338          * for non-burst sync events and burst modes */
 339         I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync);
 340         I915_WRITE(MIPI_HBP_COUNT(pipe), hbp);
 341
 342         /* vertical values are in terms of lines */
 343         I915_WRITE(MIPI_VFP_COUNT(pipe), vfp);
 344         I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync);
 345         I915_WRITE(MIPI_VBP_COUNT(pipe), vbp);
 346 }
 347
 348 static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
 349 {
 350         struct drm_encoder *encoder = &intel_encoder->base;
 351         struct drm_device *dev = encoder->dev;
 352         struct drm_i915_private *dev_priv = dev->dev_private;
 353         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 354         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 355         struct drm_display_mode *adjusted_mode =
 356                 &intel_crtc->config.adjusted_mode;
 357         int pipe = intel_crtc->pipe;
 358         unsigned int bpp = intel_crtc->config.pipe_bpp;
 359         u32 val, tmp;
 360
 361         DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
 362
 363         /* Update the DSI PLL */
 364         vlv_enable_dsi_pll(intel_encoder);
 365
 366         /* XXX: Location of the call */
 367         band_gap_wa(dev_priv);
 368
 369         /* escape clock divider, 20MHz, shared for A and C. device ready must be
 370          * off when doing this! txclkesc? */
 371         tmp = I915_READ(MIPI_CTRL(0));
 372         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 373         I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1);
 374
 375         /* read request priority is per pipe */
 376         tmp = I915_READ(MIPI_CTRL(pipe));
 377         tmp &= ~READ_REQUEST_PRIORITY_MASK;
 378         I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH);
 379
 380         /* XXX: why here, why like this? handling in irq handler?! */
 381         I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff);
 382         I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff);
 383
 384         I915_WRITE(MIPI_DPHY_PARAM(pipe),
 385                    0x3c << EXIT_ZERO_COUNT_SHIFT |
 386                    0x1f << TRAIL_COUNT_SHIFT |
 387                    0xc5 << CLK_ZERO_COUNT_SHIFT |
 388                    0x1f << PREPARE_COUNT_SHIFT);
 389
 390         I915_WRITE(MIPI_DPI_RESOLUTION(pipe),
 391                    adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
 392                    adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
 393
 394         set_dsi_timings(encoder, adjusted_mode);
 395
 396         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
 397         if (is_cmd_mode(intel_dsi)) {
 398                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
 399                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
 400         } else {
 401                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
 402
 403                 /* XXX: cross-check bpp vs. pixel format? */
 404                 val |= intel_dsi->pixel_format;
 405         }
 406         I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val);
 407
 408         /* timeouts for recovery. one frame IIUC. if counter expires, EOT and
 409          * stop state. */
 410
 411         /*
 412          * In burst mode, value greater than one DPI line Time in byte clock
 413          * (txbyteclkhs) To timeout this timer 1+ of the above said value is
 414          * recommended.
 415          *
 416          * In non-burst mode, Value greater than one DPI frame time in byte
 417          * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
 418          * is recommended.
 419          *
 420          * In DBI only mode, value greater than one DBI frame time in byte
 421          * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
 422          * is recommended.
 423          */
 424
 425         if (is_vid_mode(intel_dsi) &&
 426             intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 427                 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
 428                            txbyteclkhs(adjusted_mode->htotal, bpp,
 429                                        intel_dsi->lane_count) + 1);
 430         } else {
 431                 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
 432                            txbyteclkhs(adjusted_mode->vtotal *
 433                                        adjusted_mode->htotal,
 434                                        bpp, intel_dsi->lane_count) + 1);
 435         }
 436         I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), 8309); /* max */
 437         I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), 0x14); /* max */
 438         I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), 0xffff); /* max */
 439
 440         /* dphy stuff */
 441
 442         /* in terms of low power clock */
 443         I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(ESCAPE_CLOCK_DIVIDER_1, 100));
 444
 445         /* recovery disables */
 446         I915_WRITE(MIPI_EOT_DISABLE(pipe), intel_dsi->eot_disable);
 447
 448         /* in terms of txbyteclkhs. actual high to low switch +
 449          * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
 450          *
 451          * XXX: write MIPI_STOP_STATE_STALL?
 452          */
 453         I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), 0x46);
 454
 455         /* XXX: low power clock equivalence in terms of byte clock. the number
 456          * of byte clocks occupied in one low power clock. based on txbyteclkhs
 457          * and txclkesc. txclkesc time / txbyteclk time * (105 +
 458          * MIPI_STOP_STATE_STALL) / 105.???
 459          */
 460         I915_WRITE(MIPI_LP_BYTECLK(pipe), 4);
 461
 462         /* the bw essential for transmitting 16 long packets containing 252
 463          * bytes meant for dcs write memory command is programmed in this
 464          * register in terms of byte clocks. based on dsi transfer rate and the
 465          * number of lanes configured the time taken to transmit 16 long packets
 466          * in a dsi stream varies. */
 467         I915_WRITE(MIPI_DBI_BW_CTRL(pipe), 0x820);
 468
 469         I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe),
 470                    0xa << LP_HS_SSW_CNT_SHIFT |
 471                    0x14 << HS_LP_PWR_SW_CNT_SHIFT);
 472
 473         if (is_vid_mode(intel_dsi))
 474                 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
 475                            intel_dsi->video_mode_format);
 476 }
 477
 478 static enum drm_connector_status
 479 intel_dsi_detect(struct drm_connector *connector, bool force)
 480 {
 481         struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
 482         DRM_DEBUG_KMS("\n");
 483         return intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
 484 }
 485
 486 static int intel_dsi_get_modes(struct drm_connector *connector)
 487 {
 488         struct intel_connector *intel_connector = to_intel_connector(connector);
 489         struct drm_display_mode *mode;
 490
 491         DRM_DEBUG_KMS("\n");
 492
 493         if (!intel_connector->panel.fixed_mode) {
 494                 DRM_DEBUG_KMS("no fixed mode\n");
 495                 return 0;
 496         }
 497
 498         mode = drm_mode_duplicate(connector->dev,
 499                                   intel_connector->panel.fixed_mode);
 500         if (!mode) {
 501                 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
 502                 return 0;
 503         }
 504
 505         drm_mode_probed_add(connector, mode);
 506         return 1;
 507 }
 508
 509 static void intel_dsi_destroy(struct drm_connector *connector)
 510 {
 511         struct intel_connector *intel_connector = to_intel_connector(connector);
 512
 513         DRM_DEBUG_KMS("\n");
 514         intel_panel_fini(&intel_connector->panel);
 515         drm_connector_cleanup(connector);
 516         kfree(connector);
 517 }
 518
 519 static const struct drm_encoder_funcs intel_dsi_funcs = {
 520         .destroy = intel_encoder_destroy,
 521 };
 522
 523 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
 524         .get_modes = intel_dsi_get_modes,
 525         .mode_valid = intel_dsi_mode_valid,
 526         .best_encoder = intel_best_encoder,
 527 };
 528
 529 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
 530         .dpms = intel_connector_dpms,
 531         .detect = intel_dsi_detect,
 532         .destroy = intel_dsi_destroy,
 533         .fill_modes = drm_helper_probe_single_connector_modes,
 534 };
 535
 536 bool intel_dsi_init(struct drm_device *dev)
 537 {
 538         struct intel_dsi *intel_dsi;
 539         struct intel_encoder *intel_encoder;
 540         struct drm_encoder *encoder;
 541         struct intel_connector *intel_connector;
 542         struct drm_connector *connector;
 543         struct drm_display_mode *fixed_mode = NULL;
 544         const struct intel_dsi_device *dsi;
 545         unsigned int i;
 546
 547         DRM_DEBUG_KMS("\n");
 548
 549         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
 550         if (!intel_dsi)
 551                 return false;
 552
 553         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
 554         if (!intel_connector) {
 555                 kfree(intel_dsi);
 556                 return false;
 557         }
 558
 559         intel_encoder = &intel_dsi->base;
 560         encoder = &intel_encoder->base;
 561         intel_dsi->attached_connector = intel_connector;
 562
 563         connector = &intel_connector->base;
 564
 565         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
 566
 567         /* XXX: very likely not all of these are needed */
 568         intel_encoder->hot_plug = intel_dsi_hot_plug;
 569         intel_encoder->compute_config = intel_dsi_compute_config;
 570         intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
 571         intel_encoder->pre_enable = intel_dsi_pre_enable;
 572         intel_encoder->enable = intel_dsi_enable;
 573         intel_encoder->mode_set = intel_dsi_mode_set;
 574         intel_encoder->disable = intel_dsi_disable;
 575         intel_encoder->post_disable = intel_dsi_post_disable;
 576         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
 577         intel_encoder->get_config = intel_dsi_get_config;
 578
 579         intel_connector->get_hw_state = intel_connector_get_hw_state;
 580
 581         for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) {
 582                 dsi = &intel_dsi_devices[i];
 583                 intel_dsi->dev = *dsi;
 584
 585                 if (dsi->dev_ops->init(&intel_dsi->dev))
 586                         break;
 587         }
 588
 589         if (i == ARRAY_SIZE(intel_dsi_devices)) {
 590                 DRM_DEBUG_KMS("no device found\n");
 591                 goto err;
 592         }
 593
 594         intel_encoder->type = INTEL_OUTPUT_DSI;
 595         intel_encoder->crtc_mask = (1 << 0); /* XXX */
 596
 597         intel_encoder->cloneable = false;
 598         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
 599                            DRM_MODE_CONNECTOR_DSI);
 600
 601         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
 602
 603         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
 604         connector->interlace_allowed = false;
 605         connector->doublescan_allowed = false;
 606
 607         intel_connector_attach_encoder(intel_connector, intel_encoder);
 608
 609         drm_sysfs_connector_add(connector);
 610
 611         fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev);
 612         if (!fixed_mode) {
 613                 DRM_DEBUG_KMS("no fixed mode\n");
 614                 goto err;
 615         }
 616
 617         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
 618         intel_panel_init(&intel_connector->panel, fixed_mode);
 619
 620         return true;
 621
 622 err:
 623         drm_encoder_cleanup(&intel_encoder->base);
 624         kfree(intel_dsi);
 625         kfree(intel_connector);
 626
 627         return false;
 628 }