drivers/gpu/drm/i915/intel_dsi_cmd.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <linux/export.h>
  27 #include <drm/drmP.h>
  28 #include <drm/drm_crtc.h>
  29 #include <video/mipi_display.h>
  30 #include "i915_drv.h"
  31 #include "intel_drv.h"
  32 #include "intel_dsi.h"
  33 #include "intel_dsi_cmd.h"
  34
  35 /*
  36  * XXX: MIPI_DATA_ADDRESS, MIPI_DATA_LENGTH, MIPI_COMMAND_LENGTH, and
  37  * MIPI_COMMAND_ADDRESS registers.
  38  *
  39  * Apparently these registers provide a MIPI adapter level way to send (lots of)
  40  * commands and data to the receiver, without having to write the commands and
  41  * data to MIPI_{HS,LP}_GEN_{CTRL,DATA} registers word by word.
  42  *
  43  * Presumably for anything other than MIPI_DCS_WRITE_MEMORY_START and
  44  * MIPI_DCS_WRITE_MEMORY_CONTINUE (which are used to update the external
  45  * framebuffer in command mode displays) these are just an optimization that can
  46  * come later.
  47  *
  48  * For memory writes, these should probably be used for performance.
  49  */
  50
  51 static void print_stat(struct intel_dsi *intel_dsi, enum port port)
  52 {
  53         struct drm_encoder *encoder = &intel_dsi->base.base;
  54         struct drm_device *dev = encoder->dev;
  55         struct drm_i915_private *dev_priv = dev->dev_private;
  56         u32 val;
  57
  58         val = I915_READ(MIPI_INTR_STAT(port));
  59
  60 #define STAT_BIT(val, bit) (val) & (bit) ? " " #bit : ""
  61         DRM_DEBUG_KMS("MIPI_INTR_STAT(%c) = %08x"
  62                       "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s"
  63                       "\n", port_name(port), val,
  64                       STAT_BIT(val, TEARING_EFFECT),
  65                       STAT_BIT(val, SPL_PKT_SENT_INTERRUPT),
  66                       STAT_BIT(val, GEN_READ_DATA_AVAIL),
  67                       STAT_BIT(val, LP_GENERIC_WR_FIFO_FULL),
  68                       STAT_BIT(val, HS_GENERIC_WR_FIFO_FULL),
  69                       STAT_BIT(val, RX_PROT_VIOLATION),
  70                       STAT_BIT(val, RX_INVALID_TX_LENGTH),
  71                       STAT_BIT(val, ACK_WITH_NO_ERROR),
  72                       STAT_BIT(val, TURN_AROUND_ACK_TIMEOUT),
  73                       STAT_BIT(val, LP_RX_TIMEOUT),
  74                       STAT_BIT(val, HS_TX_TIMEOUT),
  75                       STAT_BIT(val, DPI_FIFO_UNDERRUN),
  76                       STAT_BIT(val, LOW_CONTENTION),
  77                       STAT_BIT(val, HIGH_CONTENTION),
  78                       STAT_BIT(val, TXDSI_VC_ID_INVALID),
  79                       STAT_BIT(val, TXDSI_DATA_TYPE_NOT_RECOGNISED),
  80                       STAT_BIT(val, TXCHECKSUM_ERROR),
  81                       STAT_BIT(val, TXECC_MULTIBIT_ERROR),
  82                       STAT_BIT(val, TXECC_SINGLE_BIT_ERROR),
  83                       STAT_BIT(val, TXFALSE_CONTROL_ERROR),
  84                       STAT_BIT(val, RXDSI_VC_ID_INVALID),
  85                       STAT_BIT(val, RXDSI_DATA_TYPE_NOT_REGOGNISED),
  86                       STAT_BIT(val, RXCHECKSUM_ERROR),
  87                       STAT_BIT(val, RXECC_MULTIBIT_ERROR),
  88                       STAT_BIT(val, RXECC_SINGLE_BIT_ERROR),
  89                       STAT_BIT(val, RXFALSE_CONTROL_ERROR),
  90                       STAT_BIT(val, RXHS_RECEIVE_TIMEOUT_ERROR),
  91                       STAT_BIT(val, RX_LP_TX_SYNC_ERROR),
  92                       STAT_BIT(val, RXEXCAPE_MODE_ENTRY_ERROR),
  93                       STAT_BIT(val, RXEOT_SYNC_ERROR),
  94                       STAT_BIT(val, RXSOT_SYNC_ERROR),
  95                       STAT_BIT(val, RXSOT_ERROR));
  96 #undef STAT_BIT
  97 }
  98
  99 enum dsi_type {
 100         DSI_DCS,
 101         DSI_GENERIC,
 102 };
 103
 104 /* enable or disable command mode hs transmissions */
 105 void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable,
 106                                                 enum port port)
 107 {
 108         struct drm_encoder *encoder = &intel_dsi->base.base;
 109         struct drm_device *dev = encoder->dev;
 110         struct drm_i915_private *dev_priv = dev->dev_private;
 111         u32 temp;
 112         u32 mask = DBI_FIFO_EMPTY;
 113
 114         if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 50))
 115                 DRM_ERROR("Timeout waiting for DBI FIFO empty\n");
 116
 117         temp = I915_READ(MIPI_HS_LP_DBI_ENABLE(port));
 118         temp &= DBI_HS_LP_MODE_MASK;
 119         I915_WRITE(MIPI_HS_LP_DBI_ENABLE(port), enable ? DBI_HS_MODE : DBI_LP_MODE);
 120
 121         intel_dsi->hs = enable;
 122 }
 123
 124 static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
 125                              u8 data_type, u16 data, enum port port)
 126 {
 127         struct drm_encoder *encoder = &intel_dsi->base.base;
 128         struct drm_device *dev = encoder->dev;
 129         struct drm_i915_private *dev_priv = dev->dev_private;
 130         u32 ctrl_reg;
 131         u32 ctrl;
 132         u32 mask;
 133
 134         DRM_DEBUG_KMS("channel %d, data_type %d, data %04x\n",
 135                       channel, data_type, data);
 136
 137         if (intel_dsi->hs) {
 138                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 139                 mask = HS_CTRL_FIFO_FULL;
 140         } else {
 141                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 142                 mask = LP_CTRL_FIFO_FULL;
 143         }
 144
 145         if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == 0, 50)) {
 146                 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
 147                 print_stat(intel_dsi, port);
 148         }
 149
 150         /*
 151          * Note: This function is also used for long packets, with length passed
 152          * as data, since SHORT_PACKET_PARAM_SHIFT ==
 153          * LONG_PACKET_WORD_COUNT_SHIFT.
 154          */
 155         ctrl = data << SHORT_PACKET_PARAM_SHIFT |
 156                 channel << VIRTUAL_CHANNEL_SHIFT |
 157                 data_type << DATA_TYPE_SHIFT;
 158
 159         I915_WRITE(ctrl_reg, ctrl);
 160
 161         return 0;
 162 }
 163
 164 static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel,
 165                 u8 data_type, const u8 *data, int len, enum port port)
 166 {
 167         struct drm_encoder *encoder = &intel_dsi->base.base;
 168         struct drm_device *dev = encoder->dev;
 169         struct drm_i915_private *dev_priv = dev->dev_private;
 170         u32 data_reg;
 171         int i, j, n;
 172         u32 mask;
 173
 174         DRM_DEBUG_KMS("channel %d, data_type %d, len %04x\n",
 175                       channel, data_type, len);
 176
 177         if (intel_dsi->hs) {
 178                 data_reg = MIPI_HS_GEN_DATA(port);
 179                 mask = HS_DATA_FIFO_FULL;
 180         } else {
 181                 data_reg = MIPI_LP_GEN_DATA(port);
 182                 mask = LP_DATA_FIFO_FULL;
 183         }
 184
 185         if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == 0, 50))
 186                 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
 187
 188         for (i = 0; i < len; i += n) {
 189                 u32 val = 0;
 190                 n = min_t(int, len - i, 4);
 191
 192                 for (j = 0; j < n; j++)
 193                         val |= *data++ << 8 * j;
 194
 195                 I915_WRITE(data_reg, val);
 196                 /* XXX: check for data fifo full, once that is set, write 4
 197                  * dwords, then wait for not set, then continue. */
 198         }
 199
 200         return dsi_vc_send_short(intel_dsi, channel, data_type, len, port);
 201 }
 202
 203 static int dsi_vc_write_common(struct intel_dsi *intel_dsi,
 204                                int channel, const u8 *data, int len,
 205                                enum dsi_type type, enum port port)
 206 {
 207         int ret;
 208
 209         if (len == 0) {
 210                 BUG_ON(type == DSI_GENERIC);
 211                 ret = dsi_vc_send_short(intel_dsi, channel,
 212                                         MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM,
 213                                         0, port);
 214         } else if (len == 1) {
 215                 ret = dsi_vc_send_short(intel_dsi, channel,
 216                                         type == DSI_GENERIC ?
 217                                         MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
 218                                         MIPI_DSI_DCS_SHORT_WRITE, data[0],
 219                                         port);
 220         } else if (len == 2) {
 221                 ret = dsi_vc_send_short(intel_dsi, channel,
 222                                         type == DSI_GENERIC ?
 223                                         MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
 224                                         MIPI_DSI_DCS_SHORT_WRITE_PARAM,
 225                                         (data[1] << 8) | data[0], port);
 226         } else {
 227                 ret = dsi_vc_send_long(intel_dsi, channel,
 228                                         type == DSI_GENERIC ?
 229                                         MIPI_DSI_GENERIC_LONG_WRITE :
 230                                         MIPI_DSI_DCS_LONG_WRITE, data, len,
 231                                         port);
 232         }
 233
 234         return ret;
 235 }
 236
 237 int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
 238                      const u8 *data, int len, enum port port)
 239 {
 240         return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_DCS,
 241                                                                         port);
 242 }
 243
 244 int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
 245                          const u8 *data, int len, enum port port)
 246 {
 247         return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_GENERIC,
 248                                                                         port);
 249 }
 250
 251 static int dsi_vc_dcs_send_read_request(struct intel_dsi *intel_dsi,
 252                                 int channel, u8 dcs_cmd, enum port port)
 253 {
 254         return dsi_vc_send_short(intel_dsi, channel, MIPI_DSI_DCS_READ,
 255                                  dcs_cmd, port);
 256 }
 257
 258 static int dsi_vc_generic_send_read_request(struct intel_dsi *intel_dsi,
 259                                             int channel, u8 *reqdata,
 260                                             int reqlen, enum port port)
 261 {
 262         u16 data;
 263         u8 data_type;
 264
 265         switch (reqlen) {
 266         case 0:
 267                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
 268                 data = 0;
 269                 break;
 270         case 1:
 271                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
 272                 data = reqdata[0];
 273                 break;
 274         case 2:
 275                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
 276                 data = (reqdata[1] << 8) | reqdata[0];
 277                 break;
 278         default:
 279                 BUG();
 280         }
 281
 282         return dsi_vc_send_short(intel_dsi, channel, data_type, data, port);
 283 }
 284
 285 static int dsi_read_data_return(struct intel_dsi *intel_dsi,
 286                                 u8 *buf, int buflen, enum port port)
 287 {
 288         struct drm_encoder *encoder = &intel_dsi->base.base;
 289         struct drm_device *dev = encoder->dev;
 290         struct drm_i915_private *dev_priv = dev->dev_private;
 291         int i, len = 0;
 292         u32 data_reg, val;
 293
 294         if (intel_dsi->hs) {
 295                 data_reg = MIPI_HS_GEN_DATA(port);
 296         } else {
 297                 data_reg = MIPI_LP_GEN_DATA(port);
 298         }
 299
 300         while (len < buflen) {
 301                 val = I915_READ(data_reg);
 302                 for (i = 0; i < 4 && len < buflen; i++, len++)
 303                         buf[len] = val >> 8 * i;
 304         }
 305
 306         return len;
 307 }
 308
 309 int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
 310                     u8 *buf, int buflen, enum port port)
 311 {
 312         struct drm_encoder *encoder = &intel_dsi->base.base;
 313         struct drm_device *dev = encoder->dev;
 314         struct drm_i915_private *dev_priv = dev->dev_private;
 315         u32 mask;
 316         int ret;
 317
 318         /*
 319          * XXX: should issue multiple read requests and reads if request is
 320          * longer than MIPI_MAX_RETURN_PKT_SIZE
 321          */
 322
 323         I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 324
 325         ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd, port);
 326         if (ret)
 327                 return ret;
 328
 329         mask = GEN_READ_DATA_AVAIL;
 330         if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50))
 331                 DRM_ERROR("Timeout waiting for read data.\n");
 332
 333         ret = dsi_read_data_return(intel_dsi, buf, buflen, port);
 334         if (ret < 0)
 335                 return ret;
 336
 337         if (ret != buflen)
 338                 return -EIO;
 339
 340         return 0;
 341 }
 342
 343 int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
 344                 u8 *reqdata, int reqlen, u8 *buf, int buflen, enum port port)
 345 {
 346         struct drm_encoder *encoder = &intel_dsi->base.base;
 347         struct drm_device *dev = encoder->dev;
 348         struct drm_i915_private *dev_priv = dev->dev_private;
 349         u32 mask;
 350         int ret;
 351
 352         /*
 353          * XXX: should issue multiple read requests and reads if request is
 354          * longer than MIPI_MAX_RETURN_PKT_SIZE
 355          */
 356
 357         I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 358
 359         ret = dsi_vc_generic_send_read_request(intel_dsi, channel, reqdata,
 360                                                reqlen, port);
 361         if (ret)
 362                 return ret;
 363
 364         mask = GEN_READ_DATA_AVAIL;
 365         if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50))
 366                 DRM_ERROR("Timeout waiting for read data.\n");
 367
 368         ret = dsi_read_data_return(intel_dsi, buf, buflen, port);
 369         if (ret < 0)
 370                 return ret;
 371
 372         if (ret != buflen)
 373                 return -EIO;
 374
 375         return 0;
 376 }
 377
 378 /*
 379  * send a video mode command
 380  *
 381  * XXX: commands with data in MIPI_DPI_DATA?
 382  */
 383 int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, enum port port)
 384 {
 385         struct drm_encoder *encoder = &intel_dsi->base.base;
 386         struct drm_device *dev = encoder->dev;
 387         struct drm_i915_private *dev_priv = dev->dev_private;
 388         u32 mask;
 389
 390         /* XXX: pipe, hs */
 391         if (hs)
 392                 cmd &= ~DPI_LP_MODE;
 393         else
 394                 cmd |= DPI_LP_MODE;
 395
 396         /* clear bit */
 397         I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 398
 399         /* XXX: old code skips write if control unchanged */
 400         if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
 401                 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
 402
 403         I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 404
 405         mask = SPL_PKT_SENT_INTERRUPT;
 406         if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100))
 407                 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
 408
 409         return 0;
 410 }
 411
 412 void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi)
 413 {
 414         struct drm_encoder *encoder = &intel_dsi->base.base;
 415         struct drm_device *dev = encoder->dev;
 416         struct drm_i915_private *dev_priv = dev->dev_private;
 417         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 418         enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
 419         u32 mask;
 420
 421         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
 422                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
 423
 424         if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100))
 425                 DRM_ERROR("DPI FIFOs are not empty\n");
 426 }