drivers/gpu/drm/i915/intel_dsi_vbt.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Shobhit Kumar <shobhit.kumar@intel.com>
  24  *
  25  */
  26
  27 #include <drm/drmP.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/i915_drm.h>
  31 #include <linux/gpio/consumer.h>
  32 #include <linux/slab.h>
  33 #include <video/mipi_display.h>
  34 #include <asm/intel-mid.h>
  35 #include <video/mipi_display.h>
  36 #include "i915_drv.h"
  37 #include "intel_drv.h"
  38 #include "intel_dsi.h"
  39
  40 #define MIPI_TRANSFER_MODE_SHIFT        0
  41 #define MIPI_VIRTUAL_CHANNEL_SHIFT      1
  42 #define MIPI_PORT_SHIFT                 3
  43
  44 #define PREPARE_CNT_MAX         0x3F
  45 #define EXIT_ZERO_CNT_MAX       0x3F
  46 #define CLK_ZERO_CNT_MAX        0xFF
  47 #define TRAIL_CNT_MAX           0x1F
  48
  49 #define NS_KHZ_RATIO 1000000
  50
  51 /* base offsets for gpio pads */
  52 #define VLV_GPIO_NC_0_HV_DDI0_HPD       0x4130
  53 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA   0x4120
  54 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL   0x4110
  55 #define VLV_GPIO_NC_3_PANEL0_VDDEN      0x4140
  56 #define VLV_GPIO_NC_4_PANEL0_BKLTEN     0x4150
  57 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL    0x4160
  58 #define VLV_GPIO_NC_6_HV_DDI1_HPD       0x4180
  59 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA   0x4190
  60 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL   0x4170
  61 #define VLV_GPIO_NC_9_PANEL1_VDDEN      0x4100
  62 #define VLV_GPIO_NC_10_PANEL1_BKLTEN    0x40E0
  63 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL   0x40F0
  64
  65 #define VLV_GPIO_PCONF0(base_offset)    (base_offset)
  66 #define VLV_GPIO_PAD_VAL(base_offset)   ((base_offset) + 8)
  67
  68 struct gpio_map {
  69         u16 base_offset;
  70         bool init;
  71 };
  72
  73 static struct gpio_map vlv_gpio_table[] = {
  74         { VLV_GPIO_NC_0_HV_DDI0_HPD },
  75         { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA },
  76         { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL },
  77         { VLV_GPIO_NC_3_PANEL0_VDDEN },
  78         { VLV_GPIO_NC_4_PANEL0_BKLTEN },
  79         { VLV_GPIO_NC_5_PANEL0_BKLTCTL },
  80         { VLV_GPIO_NC_6_HV_DDI1_HPD },
  81         { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA },
  82         { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL },
  83         { VLV_GPIO_NC_9_PANEL1_VDDEN },
  84         { VLV_GPIO_NC_10_PANEL1_BKLTEN },
  85         { VLV_GPIO_NC_11_PANEL1_BKLTCTL },
  86 };
  87
  88 #define CHV_GPIO_IDX_START_N            0
  89 #define CHV_GPIO_IDX_START_E            73
  90 #define CHV_GPIO_IDX_START_SW           100
  91 #define CHV_GPIO_IDX_START_SE           198
  92
  93 #define CHV_VBT_MAX_PINS_PER_FMLY       15
  94
  95 #define CHV_GPIO_PAD_CFG0(f, i)         (0x4400 + (f) * 0x400 + (i) * 8)
  96 #define  CHV_GPIO_GPIOEN                (1 << 15)
  97 #define  CHV_GPIO_GPIOCFG_GPIO          (0 << 8)
  98 #define  CHV_GPIO_GPIOCFG_GPO           (1 << 8)
  99 #define  CHV_GPIO_GPIOCFG_GPI           (2 << 8)
 100 #define  CHV_GPIO_GPIOCFG_HIZ           (3 << 8)
 101 #define  CHV_GPIO_GPIOTXSTATE(state)    ((!!(state)) << 1)
 102
 103 #define CHV_GPIO_PAD_CFG1(f, i)         (0x4400 + (f) * 0x400 + (i) * 8 + 4)
 104 #define  CHV_GPIO_CFGLOCK               (1 << 31)
 105
 106 static inline enum port intel_dsi_seq_port_to_port(u8 port)
 107 {
 108         return port ? PORT_C : PORT_A;
 109 }
 110
 111 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
 112                                        const u8 *data)
 113 {
 114         struct mipi_dsi_device *dsi_device;
 115         u8 type, flags, seq_port;
 116         u16 len;
 117         enum port port;
 118
 119         DRM_DEBUG_KMS("\n");
 120
 121         flags = *data++;
 122         type = *data++;
 123
 124         len = *((u16 *) data);
 125         data += 2;
 126
 127         seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
 128
 129         /* For DSI single link on Port A & C, the seq_port value which is
 130          * parsed from Sequence Block#53 of VBT has been set to 0
 131          * Now, read/write of packets for the DSI single link on Port A and
 132          * Port C will based on the DVO port from VBT block 2.
 133          */
 134         if (intel_dsi->ports == (1 << PORT_C))
 135                 port = PORT_C;
 136         else
 137                 port = intel_dsi_seq_port_to_port(seq_port);
 138
 139         dsi_device = intel_dsi->dsi_hosts[port]->device;
 140         if (!dsi_device) {
 141                 DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port));
 142                 goto out;
 143         }
 144
 145         if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
 146                 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
 147         else
 148                 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
 149
 150         dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
 151
 152         switch (type) {
 153         case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
 154                 mipi_dsi_generic_write(dsi_device, NULL, 0);
 155                 break;
 156         case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
 157                 mipi_dsi_generic_write(dsi_device, data, 1);
 158                 break;
 159         case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
 160                 mipi_dsi_generic_write(dsi_device, data, 2);
 161                 break;
 162         case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
 163         case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
 164         case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
 165                 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
 166                 break;
 167         case MIPI_DSI_GENERIC_LONG_WRITE:
 168                 mipi_dsi_generic_write(dsi_device, data, len);
 169                 break;
 170         case MIPI_DSI_DCS_SHORT_WRITE:
 171                 mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
 172                 break;
 173         case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 174                 mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
 175                 break;
 176         case MIPI_DSI_DCS_READ:
 177                 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
 178                 break;
 179         case MIPI_DSI_DCS_LONG_WRITE:
 180                 mipi_dsi_dcs_write_buffer(dsi_device, data, len);
 181                 break;
 182         }
 183
 184         wait_for_dsi_fifo_empty(intel_dsi, port);
 185
 186 out:
 187         data += len;
 188
 189         return data;
 190 }
 191
 192 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
 193 {
 194         u32 delay = *((const u32 *) data);
 195
 196         DRM_DEBUG_KMS("\n");
 197
 198         usleep_range(delay, delay + 10);
 199         data += 4;
 200
 201         return data;
 202 }
 203
 204 static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
 205                           u8 gpio_source, u8 gpio_index, bool value)
 206 {
 207         struct gpio_map *map;
 208         u16 pconf0, padval;
 209         u32 tmp;
 210         u8 port;
 211
 212         if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) {
 213                 DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index);
 214                 return;
 215         }
 216
 217         map = &vlv_gpio_table[gpio_index];
 218
 219         if (dev_priv->vbt.dsi.seq_version >= 3) {
 220                 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
 221                 port = IOSF_PORT_GPIO_NC;
 222         } else {
 223                 if (gpio_source == 0) {
 224                         port = IOSF_PORT_GPIO_NC;
 225                 } else if (gpio_source == 1) {
 226                         DRM_DEBUG_KMS("SC gpio not supported\n");
 227                         return;
 228                 } else {
 229                         DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
 230                         return;
 231                 }
 232         }
 233
 234         pconf0 = VLV_GPIO_PCONF0(map->base_offset);
 235         padval = VLV_GPIO_PAD_VAL(map->base_offset);
 236
 237         mutex_lock(&dev_priv->sb_lock);
 238         if (!map->init) {
 239                 /* FIXME: remove constant below */
 240                 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);
 241                 map->init = true;
 242         }
 243
 244         tmp = 0x4 | value;
 245         vlv_iosf_sb_write(dev_priv, port, padval, tmp);
 246         mutex_unlock(&dev_priv->sb_lock);
 247 }
 248
 249 static void chv_exec_gpio(struct drm_i915_private *dev_priv,
 250                           u8 gpio_source, u8 gpio_index, bool value)
 251 {
 252         u16 cfg0, cfg1;
 253         u16 family_num;
 254         u8 port;
 255
 256         if (dev_priv->vbt.dsi.seq_version >= 3) {
 257                 if (gpio_index >= CHV_GPIO_IDX_START_SE) {
 258                         /* XXX: it's unclear whether 255->57 is part of SE. */
 259                         gpio_index -= CHV_GPIO_IDX_START_SE;
 260                         port = CHV_IOSF_PORT_GPIO_SE;
 261                 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) {
 262                         gpio_index -= CHV_GPIO_IDX_START_SW;
 263                         port = CHV_IOSF_PORT_GPIO_SW;
 264                 } else if (gpio_index >= CHV_GPIO_IDX_START_E) {
 265                         gpio_index -= CHV_GPIO_IDX_START_E;
 266                         port = CHV_IOSF_PORT_GPIO_E;
 267                 } else {
 268                         port = CHV_IOSF_PORT_GPIO_N;
 269                 }
 270         } else {
 271                 /* XXX: The spec is unclear about CHV GPIO on seq v2 */
 272                 if (gpio_source != 0) {
 273                         DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
 274                         return;
 275                 }
 276
 277                 if (gpio_index >= CHV_GPIO_IDX_START_E) {
 278                         DRM_DEBUG_KMS("invalid gpio index %u for GPIO N\n",
 279                                       gpio_index);
 280                         return;
 281                 }
 282
 283                 port = CHV_IOSF_PORT_GPIO_N;
 284         }
 285
 286         family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY;
 287         gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY;
 288
 289         cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index);
 290         cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);
 291
 292         mutex_lock(&dev_priv->sb_lock);
 293         vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
 294         vlv_iosf_sb_write(dev_priv, port, cfg0,
 295                           CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO |
 296                           CHV_GPIO_GPIOTXSTATE(value));
 297         mutex_unlock(&dev_priv->sb_lock);
 298 }
 299
 300 static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
 301                           u8 gpio_source, u8 gpio_index, bool value)
 302 {
 303         /* XXX: this table is a quick ugly hack. */
 304         static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
 305         struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
 306
 307         if (!gpio_desc) {
 308                 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
 309                                                  NULL, gpio_index,
 310                                                  value ? GPIOD_OUT_LOW :
 311                                                  GPIOD_OUT_HIGH);
 312
 313                 if (IS_ERR_OR_NULL(gpio_desc)) {
 314                         DRM_ERROR("GPIO index %u request failed (%ld)\n",
 315                                   gpio_index, PTR_ERR(gpio_desc));
 316                         return;
 317                 }
 318
 319                 bxt_gpio_table[gpio_index] = gpio_desc;
 320         }
 321
 322         gpiod_set_value(gpio_desc, value);
 323 }
 324
 325 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 326 {
 327         struct drm_device *dev = intel_dsi->base.base.dev;
 328         struct drm_i915_private *dev_priv = to_i915(dev);
 329         u8 gpio_source, gpio_index = 0, gpio_number;
 330         bool value;
 331
 332         DRM_DEBUG_KMS("\n");
 333
 334         if (dev_priv->vbt.dsi.seq_version >= 3)
 335                 gpio_index = *data++;
 336
 337         gpio_number = *data++;
 338
 339         /* gpio source in sequence v2 only */
 340         if (dev_priv->vbt.dsi.seq_version == 2)
 341                 gpio_source = (*data >> 1) & 3;
 342         else
 343                 gpio_source = 0;
 344
 345         /* pull up/down */
 346         value = *data++ & 1;
 347
 348         if (IS_VALLEYVIEW(dev_priv))
 349                 vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
 350         else if (IS_CHERRYVIEW(dev_priv))
 351                 chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
 352         else
 353                 bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value);
 354
 355         return data;
 356 }
 357
 358 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
 359 {
 360         DRM_DEBUG_KMS("Skipping I2C element execution\n");
 361
 362         return data + *(data + 6) + 7;
 363 }
 364
 365 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data)
 366 {
 367         DRM_DEBUG_KMS("Skipping SPI element execution\n");
 368
 369         return data + *(data + 5) + 6;
 370 }
 371
 372 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data)
 373 {
 374         DRM_DEBUG_KMS("Skipping PMIC element execution\n");
 375
 376         return data + 15;
 377 }
 378
 379 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
 380                                         const u8 *data);
 381 static const fn_mipi_elem_exec exec_elem[] = {
 382         [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
 383         [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
 384         [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
 385         [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
 386         [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi,
 387         [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic,
 388 };
 389
 390 /*
 391  * MIPI Sequence from VBT #53 parsing logic
 392  * We have already separated each seqence during bios parsing
 393  * Following is generic execution function for any sequence
 394  */
 395
 396 static const char * const seq_name[] = {
 397         [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
 398         [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
 399         [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
 400         [MIPI_SEQ_DISPLAY_OFF]  = "MIPI_SEQ_DISPLAY_OFF",
 401         [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
 402         [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
 403         [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
 404         [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
 405         [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF",
 406         [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON",
 407         [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF",
 408 };
 409
 410 static const char *sequence_name(enum mipi_seq seq_id)
 411 {
 412         if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])
 413                 return seq_name[seq_id];
 414         else
 415                 return "(unknown)";
 416 }
 417
 418 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
 419                                  enum mipi_seq seq_id)
 420 {
 421         struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 422         const u8 *data;
 423         fn_mipi_elem_exec mipi_elem_exec;
 424
 425         if (WARN_ON(seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence)))
 426                 return;
 427
 428         data = dev_priv->vbt.dsi.sequence[seq_id];
 429         if (!data)
 430                 return;
 431
 432         WARN_ON(*data != seq_id);
 433
 434         DRM_DEBUG_KMS("Starting MIPI sequence %d - %s\n",
 435                       seq_id, sequence_name(seq_id));
 436
 437         /* Skip Sequence Byte. */
 438         data++;
 439
 440         /* Skip Size of Sequence. */
 441         if (dev_priv->vbt.dsi.seq_version >= 3)
 442                 data += 4;
 443
 444         while (1) {
 445                 u8 operation_byte = *data++;
 446                 u8 operation_size = 0;
 447
 448                 if (operation_byte == MIPI_SEQ_ELEM_END)
 449                         break;
 450
 451                 if (operation_byte < ARRAY_SIZE(exec_elem))
 452                         mipi_elem_exec = exec_elem[operation_byte];
 453                 else
 454                         mipi_elem_exec = NULL;
 455
 456                 /* Size of Operation. */
 457                 if (dev_priv->vbt.dsi.seq_version >= 3)
 458                         operation_size = *data++;
 459
 460                 if (mipi_elem_exec) {
 461                         const u8 *next = data + operation_size;
 462
 463                         data = mipi_elem_exec(intel_dsi, data);
 464
 465                         /* Consistency check if we have size. */
 466                         if (operation_size && data != next) {
 467                                 DRM_ERROR("Inconsistent operation size\n");
 468                                 return;
 469                         }
 470                 } else if (operation_size) {
 471                         /* We have size, skip. */
 472                         DRM_DEBUG_KMS("Unsupported MIPI operation byte %u\n",
 473                                       operation_byte);
 474                         data += operation_size;
 475                 } else {
 476                         /* No size, can't skip without parsing. */
 477                         DRM_ERROR("Unsupported MIPI operation byte %u\n",
 478                                   operation_byte);
 479                         return;
 480                 }
 481         }
 482 }
 483
 484 int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi)
 485 {
 486         struct intel_connector *connector = intel_dsi->attached_connector;
 487         struct drm_device *dev = intel_dsi->base.base.dev;
 488         struct drm_i915_private *dev_priv = to_i915(dev);
 489         struct drm_display_mode *mode;
 490
 491         mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
 492         if (!mode)
 493                 return 0;
 494
 495         mode->type |= DRM_MODE_TYPE_PREFERRED;
 496
 497         drm_mode_probed_add(&connector->base, mode);
 498
 499         return 1;
 500 }
 501
 502 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 503 {
 504         struct drm_device *dev = intel_dsi->base.base.dev;
 505         struct drm_i915_private *dev_priv = to_i915(dev);
 506         struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
 507         struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
 508         struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
 509         u32 bpp;
 510         u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
 511         u32 ui_num, ui_den;
 512         u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
 513         u32 ths_prepare_ns, tclk_trail_ns;
 514         u32 tclk_prepare_clkzero, ths_prepare_hszero;
 515         u32 lp_to_hs_switch, hs_to_lp_switch;
 516         u32 pclk, computed_ddr;
 517         u32 mul;
 518         u16 burst_mode_ratio;
 519         enum port port;
 520
 521         DRM_DEBUG_KMS("\n");
 522
 523         intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
 524         intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
 525         intel_dsi->lane_count = mipi_config->lane_cnt + 1;
 526         intel_dsi->pixel_format =
 527                         pixel_format_from_register_bits(
 528                                 mipi_config->videomode_color_format << 7);
 529         bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 530
 531         intel_dsi->dual_link = mipi_config->dual_link;
 532         intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
 533         intel_dsi->operation_mode = mipi_config->is_cmd_mode;
 534         intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
 535         intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
 536         intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
 537         intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
 538         intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
 539         intel_dsi->init_count = mipi_config->master_init_timer;
 540         intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
 541         intel_dsi->video_frmt_cfg_bits =
 542                 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
 543
 544         pclk = mode->clock;
 545
 546         /* In dual link mode each port needs half of pixel clock */
 547         if (intel_dsi->dual_link) {
 548                 pclk = pclk / 2;
 549
 550                 /* we can enable pixel_overlap if needed by panel. In this
 551                  * case we need to increase the pixelclock for extra pixels
 552                  */
 553                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 554                         pclk += DIV_ROUND_UP(mode->vtotal *
 555                                                 intel_dsi->pixel_overlap *
 556                                                 60, 1000);
 557                 }
 558         }
 559
 560         /* Burst Mode Ratio
 561          * Target ddr frequency from VBT / non burst ddr freq
 562          * multiply by 100 to preserve remainder
 563          */
 564         if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 565                 if (mipi_config->target_burst_mode_freq) {
 566                         computed_ddr = (pclk * bpp) / intel_dsi->lane_count;
 567
 568                         if (mipi_config->target_burst_mode_freq <
 569                                                                 computed_ddr) {
 570                                 DRM_ERROR("Burst mode freq is less than computed\n");
 571                                 return false;
 572                         }
 573
 574                         burst_mode_ratio = DIV_ROUND_UP(
 575                                 mipi_config->target_burst_mode_freq * 100,
 576                                 computed_ddr);
 577
 578                         pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100);
 579                 } else {
 580                         DRM_ERROR("Burst mode target is not set\n");
 581                         return false;
 582                 }
 583         } else
 584                 burst_mode_ratio = 100;
 585
 586         intel_dsi->burst_mode_ratio = burst_mode_ratio;
 587         intel_dsi->pclk = pclk;
 588
 589         bitrate = (pclk * bpp) / intel_dsi->lane_count;
 590
 591         switch (intel_dsi->escape_clk_div) {
 592         case 0:
 593                 tlpx_ns = 50;
 594                 break;
 595         case 1:
 596                 tlpx_ns = 100;
 597                 break;
 598
 599         case 2:
 600                 tlpx_ns = 200;
 601                 break;
 602         default:
 603                 tlpx_ns = 50;
 604                 break;
 605         }
 606
 607         switch (intel_dsi->lane_count) {
 608         case 1:
 609         case 2:
 610                 extra_byte_count = 2;
 611                 break;
 612         case 3:
 613                 extra_byte_count = 4;
 614                 break;
 615         case 4:
 616         default:
 617                 extra_byte_count = 3;
 618                 break;
 619         }
 620
 621         /* in Kbps */
 622         ui_num = NS_KHZ_RATIO;
 623         ui_den = bitrate;
 624
 625         tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
 626         ths_prepare_hszero = mipi_config->ths_prepare_hszero;
 627
 628         /*
 629          * B060
 630          * LP byte clock = TLPX/ (8UI)
 631          */
 632         intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
 633
 634         /* DDR clock period = 2 * UI
 635          * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
 636          * UI(nsec) = 10^6 / bitrate
 637          * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
 638          * DDR clock count  = ns_value / DDR clock period
 639          *
 640          * For GEMINILAKE dphy_param_reg will be programmed in terms of
 641          * HS byte clock count for other platform in HS ddr clock count
 642          */
 643         mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
 644         ths_prepare_ns = max(mipi_config->ths_prepare,
 645                              mipi_config->tclk_prepare);
 646
 647         /* prepare count */
 648         prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
 649
 650         /* exit zero count */
 651         exit_zero_cnt = DIV_ROUND_UP(
 652                                 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
 653                                 ui_num * mul
 654                                 );
 655
 656         /*
 657          * Exit zero is unified val ths_zero and ths_exit
 658          * minimum value for ths_exit = 110ns
 659          * min (exit_zero_cnt * 2) = 110/UI
 660          * exit_zero_cnt = 55/UI
 661          */
 662         if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
 663                 exit_zero_cnt += 1;
 664
 665         /* clk zero count */
 666         clk_zero_cnt = DIV_ROUND_UP(
 667                                 (tclk_prepare_clkzero - ths_prepare_ns)
 668                                 * ui_den, ui_num * mul);
 669
 670         /* trail count */
 671         tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
 672         trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
 673
 674         if (prepare_cnt > PREPARE_CNT_MAX ||
 675                 exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
 676                 clk_zero_cnt > CLK_ZERO_CNT_MAX ||
 677                 trail_cnt > TRAIL_CNT_MAX)
 678                 DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n");
 679
 680         if (prepare_cnt > PREPARE_CNT_MAX)
 681                 prepare_cnt = PREPARE_CNT_MAX;
 682
 683         if (exit_zero_cnt > EXIT_ZERO_CNT_MAX)
 684                 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
 685
 686         if (clk_zero_cnt > CLK_ZERO_CNT_MAX)
 687                 clk_zero_cnt = CLK_ZERO_CNT_MAX;
 688
 689         if (trail_cnt > TRAIL_CNT_MAX)
 690                 trail_cnt = TRAIL_CNT_MAX;
 691
 692         /* B080 */
 693         intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
 694                                                 clk_zero_cnt << 8 | prepare_cnt;
 695
 696         /*
 697          * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
 698          *                                      mul + 10UI + Extra Byte Count
 699          *
 700          * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
 701          * Extra Byte Count is calculated according to number of lanes.
 702          * High Low Switch Count is the Max of LP to HS and
 703          * HS to LP switch count
 704          *
 705          */
 706         tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
 707
 708         /* B044 */
 709         /* FIXME:
 710          * The comment above does not match with the code */
 711         lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
 712                                                 exit_zero_cnt * mul + 10, 8);
 713
 714         hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
 715
 716         intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
 717         intel_dsi->hs_to_lp_count += extra_byte_count;
 718
 719         /* B088 */
 720         /* LP -> HS for clock lanes
 721          * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
 722          *                                              extra byte count
 723          * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
 724          *                                      2(in UI) + extra byte count
 725          * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
 726          *                                      8 + extra byte count
 727          */
 728         intel_dsi->clk_lp_to_hs_count =
 729                 DIV_ROUND_UP(
 730                         4 * tlpx_ui + prepare_cnt * 2 +
 731                         clk_zero_cnt * 2,
 732                         8);
 733
 734         intel_dsi->clk_lp_to_hs_count += extra_byte_count;
 735
 736         /* HS->LP for Clock Lanes
 737          * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
 738          *                                              Extra byte count
 739          * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
 740          * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
 741          *                                              Extra byte count
 742          */
 743         intel_dsi->clk_hs_to_lp_count =
 744                 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
 745                         8);
 746         intel_dsi->clk_hs_to_lp_count += extra_byte_count;
 747
 748         DRM_DEBUG_KMS("Pclk %d\n", intel_dsi->pclk);
 749         DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi->pixel_overlap);
 750         DRM_DEBUG_KMS("Lane count %d\n", intel_dsi->lane_count);
 751         DRM_DEBUG_KMS("DPHY param reg 0x%x\n", intel_dsi->dphy_reg);
 752         DRM_DEBUG_KMS("Video mode format %s\n",
 753                       intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ?
 754                       "non-burst with sync pulse" :
 755                       intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ?
 756                       "non-burst with sync events" :
 757                       intel_dsi->video_mode_format == VIDEO_MODE_BURST ?
 758                       "burst" : "<unknown>");
 759         DRM_DEBUG_KMS("Burst mode ratio %d\n", intel_dsi->burst_mode_ratio);
 760         DRM_DEBUG_KMS("Reset timer %d\n", intel_dsi->rst_timer_val);
 761         DRM_DEBUG_KMS("Eot %s\n", enableddisabled(intel_dsi->eotp_pkt));
 762         DRM_DEBUG_KMS("Clockstop %s\n", enableddisabled(!intel_dsi->clock_stop));
 763         DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
 764         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 765                 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
 766         else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
 767                 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
 768         else
 769                 DRM_DEBUG_KMS("Dual link: NONE\n");
 770         DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
 771         DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
 772         DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
 773         DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
 774         DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
 775         DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
 776         DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
 777         DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
 778         DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
 779         DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
 780         DRM_DEBUG_KMS("BTA %s\n",
 781                         enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
 782
 783         /* delays in VBT are in unit of 100us, so need to convert
 784          * here in ms
 785          * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
 786         intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
 787         intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
 788         intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
 789         intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
 790         intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
 791
 792         /* a regular driver would get the device in probe */
 793         for_each_dsi_port(port, intel_dsi->ports) {
 794                 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
 795         }
 796
 797         return true;
 798 }