drivers/gpu/drm/i915/intel_engine_cs.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "i915_drv.h"
  26 #include "intel_ringbuffer.h"
  27 #include "intel_lrc.h"
  28
  29 static const struct engine_info {
  30         const char *name;
  31         unsigned exec_id;
  32         enum intel_engine_hw_id hw_id;
  33         u32 mmio_base;
  34         unsigned irq_shift;
  35         int (*init_legacy)(struct intel_engine_cs *engine);
  36         int (*init_execlists)(struct intel_engine_cs *engine);
  37 } intel_engines[] = {
  38         [RCS] = {
  39                 .name = "render ring",
  40                 .exec_id = I915_EXEC_RENDER,
  41                 .hw_id = RCS_HW,
  42                 .mmio_base = RENDER_RING_BASE,
  43                 .irq_shift = GEN8_RCS_IRQ_SHIFT,
  44                 .init_execlists = logical_render_ring_init,
  45                 .init_legacy = intel_init_render_ring_buffer,
  46         },
  47         [BCS] = {
  48                 .name = "blitter ring",
  49                 .exec_id = I915_EXEC_BLT,
  50                 .hw_id = BCS_HW,
  51                 .mmio_base = BLT_RING_BASE,
  52                 .irq_shift = GEN8_BCS_IRQ_SHIFT,
  53                 .init_execlists = logical_xcs_ring_init,
  54                 .init_legacy = intel_init_blt_ring_buffer,
  55         },
  56         [VCS] = {
  57                 .name = "bsd ring",
  58                 .exec_id = I915_EXEC_BSD,
  59                 .hw_id = VCS_HW,
  60                 .mmio_base = GEN6_BSD_RING_BASE,
  61                 .irq_shift = GEN8_VCS1_IRQ_SHIFT,
  62                 .init_execlists = logical_xcs_ring_init,
  63                 .init_legacy = intel_init_bsd_ring_buffer,
  64         },
  65         [VCS2] = {
  66                 .name = "bsd2 ring",
  67                 .exec_id = I915_EXEC_BSD,
  68                 .hw_id = VCS2_HW,
  69                 .mmio_base = GEN8_BSD2_RING_BASE,
  70                 .irq_shift = GEN8_VCS2_IRQ_SHIFT,
  71                 .init_execlists = logical_xcs_ring_init,
  72                 .init_legacy = intel_init_bsd2_ring_buffer,
  73         },
  74         [VECS] = {
  75                 .name = "video enhancement ring",
  76                 .exec_id = I915_EXEC_VEBOX,
  77                 .hw_id = VECS_HW,
  78                 .mmio_base = VEBOX_RING_BASE,
  79                 .irq_shift = GEN8_VECS_IRQ_SHIFT,
  80                 .init_execlists = logical_xcs_ring_init,
  81                 .init_legacy = intel_init_vebox_ring_buffer,
  82         },
  83 };
  84
  85 static int
  86 intel_engine_setup(struct drm_i915_private *dev_priv,
  87                    enum intel_engine_id id)
  88 {
  89         const struct engine_info *info = &intel_engines[id];
  90         struct intel_engine_cs *engine;
  91
  92         GEM_BUG_ON(dev_priv->engine[id]);
  93         engine = kzalloc(sizeof(*engine), GFP_KERNEL);
  94         if (!engine)
  95                 return -ENOMEM;
  96
  97         engine->id = id;
  98         engine->i915 = dev_priv;
  99         engine->name = info->name;
 100         engine->exec_id = info->exec_id;
 101         engine->hw_id = engine->guc_id = info->hw_id;
 102         engine->mmio_base = info->mmio_base;
 103         engine->irq_shift = info->irq_shift;
 104
 105         /* Nothing to do here, execute in order of dependencies */
 106         engine->schedule = NULL;
 107
 108         dev_priv->engine[id] = engine;
 109         return 0;
 110 }
 111
 112 /**
 113  * intel_engines_init_early() - allocate the Engine Command Streamers
 114  * @dev_priv: i915 device private
 115  *
 116  * Return: non-zero if the initialization failed.
 117  */
 118 int intel_engines_init_early(struct drm_i915_private *dev_priv)
 119 {
 120         struct intel_device_info *device_info = mkwrite_device_info(dev_priv);
 121         unsigned int ring_mask = INTEL_INFO(dev_priv)->ring_mask;
 122         unsigned int mask = 0;
 123         struct intel_engine_cs *engine;
 124         enum intel_engine_id id;
 125         unsigned int i;
 126         int err;
 127
 128         WARN_ON(ring_mask == 0);
 129         WARN_ON(ring_mask &
 130                 GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES));
 131
 132         for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
 133                 if (!HAS_ENGINE(dev_priv, i))
 134                         continue;
 135
 136                 err = intel_engine_setup(dev_priv, i);
 137                 if (err)
 138                         goto cleanup;
 139
 140                 mask |= ENGINE_MASK(i);
 141         }
 142
 143         /*
 144          * Catch failures to update intel_engines table when the new engines
 145          * are added to the driver by a warning and disabling the forgotten
 146          * engines.
 147          */
 148         if (WARN_ON(mask != ring_mask))
 149                 device_info->ring_mask = mask;
 150
 151         device_info->num_rings = hweight32(mask);
 152
 153         return 0;
 154
 155 cleanup:
 156         for_each_engine(engine, dev_priv, id)
 157                 kfree(engine);
 158         return err;
 159 }
 160
 161 /**
 162  * intel_engines_init() - allocate, populate and init the Engine Command Streamers
 163  * @dev_priv: i915 device private
 164  *
 165  * Return: non-zero if the initialization failed.
 166  */
 167 int intel_engines_init(struct drm_i915_private *dev_priv)
 168 {
 169         struct intel_device_info *device_info = mkwrite_device_info(dev_priv);
 170         struct intel_engine_cs *engine;
 171         enum intel_engine_id id, err_id;
 172         unsigned int mask = 0;
 173         int err = 0;
 174
 175         for_each_engine(engine, dev_priv, id) {
 176                 int (*init)(struct intel_engine_cs *engine);
 177
 178                 if (i915.enable_execlists)
 179                         init = intel_engines[id].init_execlists;
 180                 else
 181                         init = intel_engines[id].init_legacy;
 182                 if (!init) {
 183                         kfree(engine);
 184                         dev_priv->engine[id] = NULL;
 185                         continue;
 186                 }
 187
 188                 err = init(engine);
 189                 if (err) {
 190                         err_id = id;
 191                         goto cleanup;
 192                 }
 193
 194                 mask |= ENGINE_MASK(id);
 195         }
 196
 197         /*
 198          * Catch failures to update intel_engines table when the new engines
 199          * are added to the driver by a warning and disabling the forgotten
 200          * engines.
 201          */
 202         if (WARN_ON(mask != INTEL_INFO(dev_priv)->ring_mask))
 203                 device_info->ring_mask = mask;
 204
 205         device_info->num_rings = hweight32(mask);
 206
 207         return 0;
 208
 209 cleanup:
 210         for_each_engine(engine, dev_priv, id) {
 211                 if (id >= err_id)
 212                         kfree(engine);
 213                 else
 214                         dev_priv->gt.cleanup_engine(engine);
 215         }
 216         return err;
 217 }
 218
 219 void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno)
 220 {
 221         struct drm_i915_private *dev_priv = engine->i915;
 222
 223         /* Our semaphore implementation is strictly monotonic (i.e. we proceed
 224          * so long as the semaphore value in the register/page is greater
 225          * than the sync value), so whenever we reset the seqno,
 226          * so long as we reset the tracking semaphore value to 0, it will
 227          * always be before the next request's seqno. If we don't reset
 228          * the semaphore value, then when the seqno moves backwards all
 229          * future waits will complete instantly (causing rendering corruption).
 230          */
 231         if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
 232                 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
 233                 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
 234                 if (HAS_VEBOX(dev_priv))
 235                         I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
 236         }
 237         if (dev_priv->semaphore) {
 238                 struct page *page = i915_vma_first_page(dev_priv->semaphore);
 239                 void *semaphores;
 240
 241                 /* Semaphores are in noncoherent memory, flush to be safe */
 242                 semaphores = kmap(page);
 243                 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
 244                        0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
 245                 drm_clflush_virt_range(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
 246                                        I915_NUM_ENGINES * gen8_semaphore_seqno_size);
 247                 kunmap(page);
 248         }
 249
 250         intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
 251         if (engine->irq_seqno_barrier)
 252                 engine->irq_seqno_barrier(engine);
 253
 254         GEM_BUG_ON(i915_gem_active_isset(&engine->timeline->last_request));
 255         engine->timeline->last_submitted_seqno = seqno;
 256
 257         engine->hangcheck.seqno = seqno;
 258
 259         /* After manually advancing the seqno, fake the interrupt in case
 260          * there are any waiters for that seqno.
 261          */
 262         intel_engine_wakeup(engine);
 263 }
 264
 265 static void intel_engine_init_timeline(struct intel_engine_cs *engine)
 266 {
 267         engine->timeline = &engine->i915->gt.global_timeline.engine[engine->id];
 268 }
 269
 270 /**
 271  * intel_engines_setup_common - setup engine state not requiring hw access
 272  * @engine: Engine to setup.
 273  *
 274  * Initializes @engine@ structure members shared between legacy and execlists
 275  * submission modes which do not require hardware access.
 276  *
 277  * Typically done early in the submission mode specific engine setup stage.
 278  */
 279 void intel_engine_setup_common(struct intel_engine_cs *engine)
 280 {
 281         engine->execlist_queue = RB_ROOT;
 282         engine->execlist_first = NULL;
 283
 284         intel_engine_init_timeline(engine);
 285         intel_engine_init_hangcheck(engine);
 286         i915_gem_batch_pool_init(engine, &engine->batch_pool);
 287
 288         intel_engine_init_cmd_parser(engine);
 289 }
 290
 291 int intel_engine_create_scratch(struct intel_engine_cs *engine, int size)
 292 {
 293         struct drm_i915_gem_object *obj;
 294         struct i915_vma *vma;
 295         int ret;
 296
 297         WARN_ON(engine->scratch);
 298
 299         obj = i915_gem_object_create_stolen(engine->i915, size);
 300         if (!obj)
 301                 obj = i915_gem_object_create_internal(engine->i915, size);
 302         if (IS_ERR(obj)) {
 303                 DRM_ERROR("Failed to allocate scratch page\n");
 304                 return PTR_ERR(obj);
 305         }
 306
 307         vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
 308         if (IS_ERR(vma)) {
 309                 ret = PTR_ERR(vma);
 310                 goto err_unref;
 311         }
 312
 313         ret = i915_vma_pin(vma, 0, 4096, PIN_GLOBAL | PIN_HIGH);
 314         if (ret)
 315                 goto err_unref;
 316
 317         engine->scratch = vma;
 318         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 319                          engine->name, i915_ggtt_offset(vma));
 320         return 0;
 321
 322 err_unref:
 323         i915_gem_object_put(obj);
 324         return ret;
 325 }
 326
 327 static void intel_engine_cleanup_scratch(struct intel_engine_cs *engine)
 328 {
 329         i915_vma_unpin_and_release(&engine->scratch);
 330 }
 331
 332 /**
 333  * intel_engines_init_common - initialize cengine state which might require hw access
 334  * @engine: Engine to initialize.
 335  *
 336  * Initializes @engine@ structure members shared between legacy and execlists
 337  * submission modes which do require hardware access.
 338  *
 339  * Typcally done at later stages of submission mode specific engine setup.
 340  *
 341  * Returns zero on success or an error code on failure.
 342  */
 343 int intel_engine_init_common(struct intel_engine_cs *engine)
 344 {
 345         int ret;
 346
 347         /* We may need to do things with the shrinker which
 348          * require us to immediately switch back to the default
 349          * context. This can cause a problem as pinning the
 350          * default context also requires GTT space which may not
 351          * be available. To avoid this we always pin the default
 352          * context.
 353          */
 354         ret = engine->context_pin(engine, engine->i915->kernel_context);
 355         if (ret)
 356                 return ret;
 357
 358         ret = intel_engine_init_breadcrumbs(engine);
 359         if (ret)
 360                 goto err_unpin;
 361
 362         ret = i915_gem_render_state_init(engine);
 363         if (ret)
 364                 goto err_unpin;
 365
 366         return 0;
 367
 368 err_unpin:
 369         engine->context_unpin(engine, engine->i915->kernel_context);
 370         return ret;
 371 }
 372
 373 /**
 374  * intel_engines_cleanup_common - cleans up the engine state created by
 375  *                                the common initiailizers.
 376  * @engine: Engine to cleanup.
 377  *
 378  * This cleans up everything created by the common helpers.
 379  */
 380 void intel_engine_cleanup_common(struct intel_engine_cs *engine)
 381 {
 382         intel_engine_cleanup_scratch(engine);
 383
 384         i915_gem_render_state_fini(engine);
 385         intel_engine_fini_breadcrumbs(engine);
 386         intel_engine_cleanup_cmd_parser(engine);
 387         i915_gem_batch_pool_fini(&engine->batch_pool);
 388
 389         engine->context_unpin(engine, engine->i915->kernel_context);
 390 }
 391
 392 u64 intel_engine_get_active_head(struct intel_engine_cs *engine)
 393 {
 394         struct drm_i915_private *dev_priv = engine->i915;
 395         u64 acthd;
 396
 397         if (INTEL_GEN(dev_priv) >= 8)
 398                 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
 399                                          RING_ACTHD_UDW(engine->mmio_base));
 400         else if (INTEL_GEN(dev_priv) >= 4)
 401                 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
 402         else
 403                 acthd = I915_READ(ACTHD);
 404
 405         return acthd;
 406 }
 407
 408 u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine)
 409 {
 410         struct drm_i915_private *dev_priv = engine->i915;
 411         u64 bbaddr;
 412
 413         if (INTEL_GEN(dev_priv) >= 8)
 414                 bbaddr = I915_READ64_2x32(RING_BBADDR(engine->mmio_base),
 415                                           RING_BBADDR_UDW(engine->mmio_base));
 416         else
 417                 bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
 418
 419         return bbaddr;
 420 }
 421
 422 const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
 423 {
 424         switch (type) {
 425         case I915_CACHE_NONE: return " uncached";
 426         case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
 427         case I915_CACHE_L3_LLC: return " L3+LLC";
 428         case I915_CACHE_WT: return " WT";
 429         default: return "";
 430         }
 431 }
 432
 433 static inline uint32_t
 434 read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 435                   int subslice, i915_reg_t reg)
 436 {
 437         uint32_t mcr;
 438         uint32_t ret;
 439         enum forcewake_domains fw_domains;
 440
 441         fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,
 442                                                     FW_REG_READ);
 443         fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
 444                                                      GEN8_MCR_SELECTOR,
 445                                                      FW_REG_READ | FW_REG_WRITE);
 446
 447         spin_lock_irq(&dev_priv->uncore.lock);
 448         intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
 449
 450         mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
 451         /*
 452          * The HW expects the slice and sublice selectors to be reset to 0
 453          * after reading out the registers.
 454          */
 455         WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK));
 456         mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
 457         mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
 458         I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 459
 460         ret = I915_READ_FW(reg);
 461
 462         mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
 463         I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 464
 465         intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
 466         spin_unlock_irq(&dev_priv->uncore.lock);
 467
 468         return ret;
 469 }
 470
 471 /* NB: please notice the memset */
 472 void intel_engine_get_instdone(struct intel_engine_cs *engine,
 473                                struct intel_instdone *instdone)
 474 {
 475         struct drm_i915_private *dev_priv = engine->i915;
 476         u32 mmio_base = engine->mmio_base;
 477         int slice;
 478         int subslice;
 479
 480         memset(instdone, 0, sizeof(*instdone));
 481
 482         switch (INTEL_GEN(dev_priv)) {
 483         default:
 484                 instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
 485
 486                 if (engine->id != RCS)
 487                         break;
 488
 489                 instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
 490                 for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
 491                         instdone->sampler[slice][subslice] =
 492                                 read_subslice_reg(dev_priv, slice, subslice,
 493                                                   GEN7_SAMPLER_INSTDONE);
 494                         instdone->row[slice][subslice] =
 495                                 read_subslice_reg(dev_priv, slice, subslice,
 496                                                   GEN7_ROW_INSTDONE);
 497                 }
 498                 break;
 499         case 7:
 500                 instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
 501
 502                 if (engine->id != RCS)
 503                         break;
 504
 505                 instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
 506                 instdone->sampler[0][0] = I915_READ(GEN7_SAMPLER_INSTDONE);
 507                 instdone->row[0][0] = I915_READ(GEN7_ROW_INSTDONE);
 508
 509                 break;
 510         case 6:
 511         case 5:
 512         case 4:
 513                 instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
 514
 515                 if (engine->id == RCS)
 516                         /* HACK: Using the wrong struct member */
 517                         instdone->slice_common = I915_READ(GEN4_INSTDONE1);
 518                 break;
 519         case 3:
 520         case 2:
 521                 instdone->instdone = I915_READ(GEN2_INSTDONE);
 522                 break;
 523         }
 524 }
 525
 526 static int wa_add(struct drm_i915_private *dev_priv,
 527                   i915_reg_t addr,
 528                   const u32 mask, const u32 val)
 529 {
 530         const u32 idx = dev_priv->workarounds.count;
 531
 532         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 533                 return -ENOSPC;
 534
 535         dev_priv->workarounds.reg[idx].addr = addr;
 536         dev_priv->workarounds.reg[idx].value = val;
 537         dev_priv->workarounds.reg[idx].mask = mask;
 538
 539         dev_priv->workarounds.count++;
 540
 541         return 0;
 542 }
 543
 544 #define WA_REG(addr, mask, val) do { \
 545                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 546                 if (r) \
 547                         return r; \
 548         } while (0)
 549
 550 #define WA_SET_BIT_MASKED(addr, mask) \
 551         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 552
 553 #define WA_CLR_BIT_MASKED(addr, mask) \
 554         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 555
 556 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 557         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 558
 559 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 560 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 561
 562 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 563
 564 static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
 565                                  i915_reg_t reg)
 566 {
 567         struct drm_i915_private *dev_priv = engine->i915;
 568         struct i915_workarounds *wa = &dev_priv->workarounds;
 569         const uint32_t index = wa->hw_whitelist_count[engine->id];
 570
 571         if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
 572                 return -EINVAL;
 573
 574         WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
 575                  i915_mmio_reg_offset(reg));
 576         wa->hw_whitelist_count[engine->id]++;
 577
 578         return 0;
 579 }
 580
 581 static int gen8_init_workarounds(struct intel_engine_cs *engine)
 582 {
 583         struct drm_i915_private *dev_priv = engine->i915;
 584
 585         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 586
 587         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 588         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 589
 590         /* WaDisablePartialInstShootdown:bdw,chv */
 591         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 592                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 593
 594         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 595          * workaround for for a possible hang in the unlikely event a TLB
 596          * invalidation occurs during a PSD flush.
 597          */
 598         /* WaForceEnableNonCoherent:bdw,chv */
 599         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 600         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 601                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 602                           HDC_FORCE_NON_COHERENT);
 603
 604         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 605          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 606          *  polygons in the same 8x4 pixel/sample area to be processed without
 607          *  stalling waiting for the earlier ones to write to Hierarchical Z
 608          *  buffer."
 609          *
 610          * This optimization is off by default for BDW and CHV; turn it on.
 611          */
 612         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 613
 614         /* Wa4x4STCOptimizationDisable:bdw,chv */
 615         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 616
 617         /*
 618          * BSpec recommends 8x4 when MSAA is used,
 619          * however in practice 16x4 seems fastest.
 620          *
 621          * Note that PS/WM thread counts depend on the WIZ hashing
 622          * disable bit, which we don't touch here, but it's good
 623          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 624          */
 625         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 626                             GEN6_WIZ_HASHING_MASK,
 627                             GEN6_WIZ_HASHING_16x4);
 628
 629         return 0;
 630 }
 631
 632 static int bdw_init_workarounds(struct intel_engine_cs *engine)
 633 {
 634         struct drm_i915_private *dev_priv = engine->i915;
 635         int ret;
 636
 637         ret = gen8_init_workarounds(engine);
 638         if (ret)
 639                 return ret;
 640
 641         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 642         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 643
 644         /* WaDisableDopClockGating:bdw
 645          *
 646          * Also see the related UCGTCL1 write in broadwell_init_clock_gating()
 647          * to disable EUTC clock gating.
 648          */
 649         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 650                           DOP_CLOCK_GATING_DISABLE);
 651
 652         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 653                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 654
 655         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 656                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 657                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 658                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 659                           (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 660
 661         return 0;
 662 }
 663
 664 static int chv_init_workarounds(struct intel_engine_cs *engine)
 665 {
 666         struct drm_i915_private *dev_priv = engine->i915;
 667         int ret;
 668
 669         ret = gen8_init_workarounds(engine);
 670         if (ret)
 671                 return ret;
 672
 673         /* WaDisableThreadStallDopClockGating:chv */
 674         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 675
 676         /* Improve HiZ throughput on CHV. */
 677         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 678
 679         return 0;
 680 }
 681
 682 static int gen9_init_workarounds(struct intel_engine_cs *engine)
 683 {
 684         struct drm_i915_private *dev_priv = engine->i915;
 685         int ret;
 686
 687         /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk */
 688         I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
 689
 690         /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk */
 691         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 692                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 693
 694         /* WaDisableKillLogic:bxt,skl,kbl */
 695         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 696                    ECOCHK_DIS_TLB);
 697
 698         /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk */
 699         /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk */
 700         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 701                           FLOW_CONTROL_ENABLE |
 702                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 703
 704         /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
 705         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 706                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 707
 708         /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
 709         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
 710                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 711                                   GEN9_DG_MIRROR_FIX_ENABLE);
 712
 713         /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
 714         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
 715                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 716                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 717                 /*
 718                  * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
 719                  * but we do that in per ctx batchbuffer as there is an issue
 720                  * with this register not getting restored on ctx restore
 721                  */
 722         }
 723
 724         /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
 725         WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 726                           GEN9_ENABLE_GPGPU_PREEMPTION);
 727
 728         /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk */
 729         /* WaDisablePartialResolveInVc:skl,bxt,kbl */
 730         WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 731                                          GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 732
 733         /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk */
 734         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 735                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 736
 737         /* WaDisableMaskBasedCammingInRCC:bxt */
 738         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
 739                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 740                                   PIXEL_MASK_CAMMING_DISABLE);
 741
 742         /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
 743         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 744                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 745                           HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
 746
 747         /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
 748          * both tied to WaForceContextSaveRestoreNonCoherent
 749          * in some hsds for skl. We keep the tie for all gen9. The
 750          * documentation is a bit hazy and so we want to get common behaviour,
 751          * even though there is no clear evidence we would need both on kbl/bxt.
 752          * This area has been source of system hangs so we play it safe
 753          * and mimic the skl regardless of what bspec says.
 754          *
 755          * Use Force Non-Coherent whenever executing a 3D context. This
 756          * is a workaround for a possible hang in the unlikely event
 757          * a TLB invalidation occurs during a PSD flush.
 758          */
 759
 760         /* WaForceEnableNonCoherent:skl,bxt,kbl */
 761         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 762                           HDC_FORCE_NON_COHERENT);
 763
 764         /* WaDisableHDCInvalidation:skl,bxt,kbl */
 765         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 766                    BDW_DISABLE_HDC_INVALIDATION);
 767
 768         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
 769         if (IS_SKYLAKE(dev_priv) ||
 770             IS_KABYLAKE(dev_priv) ||
 771             IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
 772                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 773                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
 774
 775         /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk */
 776         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 777
 778         /* WaOCLCoherentLineFlush:skl,bxt,kbl */
 779         I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 780                                     GEN8_LQSC_FLUSH_COHERENT_LINES));
 781
 782         /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk */
 783         ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
 784         if (ret)
 785                 return ret;
 786
 787         /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
 788         ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
 789         if (ret)
 790                 return ret;
 791
 792         /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk */
 793         ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
 794         if (ret)
 795                 return ret;
 796
 797         return 0;
 798 }
 799
 800 static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
 801 {
 802         struct drm_i915_private *dev_priv = engine->i915;
 803         u8 vals[3] = { 0, 0, 0 };
 804         unsigned int i;
 805
 806         for (i = 0; i < 3; i++) {
 807                 u8 ss;
 808
 809                 /*
 810                  * Only consider slices where one, and only one, subslice has 7
 811                  * EUs
 812                  */
 813                 if (!is_power_of_2(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]))
 814                         continue;
 815
 816                 /*
 817                  * subslice_7eu[i] != 0 (because of the check above) and
 818                  * ss_max == 4 (maximum number of subslices possible per slice)
 819                  *
 820                  * ->    0 <= ss <= 3;
 821                  */
 822                 ss = ffs(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1;
 823                 vals[i] = 3 - ss;
 824         }
 825
 826         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
 827                 return 0;
 828
 829         /* Tune IZ hashing. See intel_device_info_runtime_init() */
 830         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 831                             GEN9_IZ_HASHING_MASK(2) |
 832                             GEN9_IZ_HASHING_MASK(1) |
 833                             GEN9_IZ_HASHING_MASK(0),
 834                             GEN9_IZ_HASHING(2, vals[2]) |
 835                             GEN9_IZ_HASHING(1, vals[1]) |
 836                             GEN9_IZ_HASHING(0, vals[0]));
 837
 838         return 0;
 839 }
 840
 841 static int skl_init_workarounds(struct intel_engine_cs *engine)
 842 {
 843         struct drm_i915_private *dev_priv = engine->i915;
 844         int ret;
 845
 846         ret = gen9_init_workarounds(engine);
 847         if (ret)
 848                 return ret;
 849
 850         /*
 851          * Actual WA is to disable percontext preemption granularity control
 852          * until D0 which is the default case so this is equivalent to
 853          * !WaDisablePerCtxtPreemptionGranularityControl:skl
 854          */
 855         I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
 856                    _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
 857
 858         /* WaEnableGapsTsvCreditFix:skl */
 859         I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
 860                                    GEN9_GAPS_TSV_CREDIT_DISABLE));
 861
 862         /* WaDisableGafsUnitClkGating:skl */
 863         WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 864
 865         /* WaInPlaceDecompressionHang:skl */
 866         if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
 867                 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
 868                            GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 869
 870         /* WaDisableLSQCROPERFforOCL:skl */
 871         ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
 872         if (ret)
 873                 return ret;
 874
 875         return skl_tune_iz_hashing(engine);
 876 }
 877
 878 static int bxt_init_workarounds(struct intel_engine_cs *engine)
 879 {
 880         struct drm_i915_private *dev_priv = engine->i915;
 881         int ret;
 882
 883         ret = gen9_init_workarounds(engine);
 884         if (ret)
 885                 return ret;
 886
 887         /* WaStoreMultiplePTEenable:bxt */
 888         /* This is a requirement according to Hardware specification */
 889         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
 890                 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
 891
 892         /* WaSetClckGatingDisableMedia:bxt */
 893         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
 894                 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
 895                                             ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
 896         }
 897
 898         /* WaDisableThreadStallDopClockGating:bxt */
 899         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 900                           STALL_DOP_GATING_DISABLE);
 901
 902         /* WaDisablePooledEuLoadBalancingFix:bxt */
 903         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
 904                 WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2,
 905                                   GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
 906         }
 907
 908         /* WaDisableSbeCacheDispatchPortSharing:bxt */
 909         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
 910                 WA_SET_BIT_MASKED(
 911                         GEN7_HALF_SLICE_CHICKEN1,
 912                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 913         }
 914
 915         /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
 916         /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
 917         /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
 918         /* WaDisableLSQCROPERFforOCL:bxt */
 919         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
 920                 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
 921                 if (ret)
 922                         return ret;
 923
 924                 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
 925                 if (ret)
 926                         return ret;
 927         }
 928
 929         /* WaProgramL3SqcReg1DefaultForPerf:bxt */
 930         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
 931                 I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
 932                                            L3_HIGH_PRIO_CREDITS(2));
 933
 934         /* WaToEnableHwFixForPushConstHWBug:bxt */
 935         if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
 936                 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 937                                   GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 938
 939         /* WaInPlaceDecompressionHang:bxt */
 940         if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
 941                 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
 942                            GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 943
 944         return 0;
 945 }
 946
 947 static int kbl_init_workarounds(struct intel_engine_cs *engine)
 948 {
 949         struct drm_i915_private *dev_priv = engine->i915;
 950         int ret;
 951
 952         ret = gen9_init_workarounds(engine);
 953         if (ret)
 954                 return ret;
 955
 956         /* WaEnableGapsTsvCreditFix:kbl */
 957         I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
 958                                    GEN9_GAPS_TSV_CREDIT_DISABLE));
 959
 960         /* WaDisableDynamicCreditSharing:kbl */
 961         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
 962                 WA_SET_BIT(GAMT_CHKN_BIT_REG,
 963                            GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
 964
 965         /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
 966         if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
 967                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
 968                                   HDC_FENCE_DEST_SLM_DISABLE);
 969
 970         /* WaToEnableHwFixForPushConstHWBug:kbl */
 971         if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER))
 972                 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 973                                   GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 974
 975         /* WaDisableGafsUnitClkGating:kbl */
 976         WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 977
 978         /* WaDisableSbeCacheDispatchPortSharing:kbl */
 979         WA_SET_BIT_MASKED(
 980                 GEN7_HALF_SLICE_CHICKEN1,
 981                 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 982
 983         /* WaInPlaceDecompressionHang:kbl */
 984         WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
 985                    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
 986
 987         /* WaDisableLSQCROPERFforOCL:kbl */
 988         ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
 989         if (ret)
 990                 return ret;
 991
 992         return 0;
 993 }
 994
 995 static int glk_init_workarounds(struct intel_engine_cs *engine)
 996 {
 997         struct drm_i915_private *dev_priv = engine->i915;
 998         int ret;
 999
1000         ret = gen9_init_workarounds(engine);
1001         if (ret)
1002                 return ret;
1003
1004         /* WaToEnableHwFixForPushConstHWBug:glk */
1005         WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1006                           GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1007
1008         return 0;
1009 }
1010
1011 int init_workarounds_ring(struct intel_engine_cs *engine)
1012 {
1013         struct drm_i915_private *dev_priv = engine->i915;
1014
1015         WARN_ON(engine->id != RCS);
1016
1017         dev_priv->workarounds.count = 0;
1018         dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1019
1020         if (IS_BROADWELL(dev_priv))
1021                 return bdw_init_workarounds(engine);
1022
1023         if (IS_CHERRYVIEW(dev_priv))
1024                 return chv_init_workarounds(engine);
1025
1026         if (IS_SKYLAKE(dev_priv))
1027                 return skl_init_workarounds(engine);
1028
1029         if (IS_BROXTON(dev_priv))
1030                 return bxt_init_workarounds(engine);
1031
1032         if (IS_KABYLAKE(dev_priv))
1033                 return kbl_init_workarounds(engine);
1034
1035         if (IS_GEMINILAKE(dev_priv))
1036                 return glk_init_workarounds(engine);
1037
1038         return 0;
1039 }
1040
1041 int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
1042 {
1043         struct i915_workarounds *w = &req->i915->workarounds;
1044         u32 *cs;
1045         int ret, i;
1046
1047         if (w->count == 0)
1048                 return 0;
1049
1050         ret = req->engine->emit_flush(req, EMIT_BARRIER);
1051         if (ret)
1052                 return ret;
1053
1054         cs = intel_ring_begin(req, (w->count * 2 + 2));
1055         if (IS_ERR(cs))
1056                 return PTR_ERR(cs);
1057
1058         *cs++ = MI_LOAD_REGISTER_IMM(w->count);
1059         for (i = 0; i < w->count; i++) {
1060                 *cs++ = i915_mmio_reg_offset(w->reg[i].addr);
1061                 *cs++ = w->reg[i].value;
1062         }
1063         *cs++ = MI_NOOP;
1064
1065         intel_ring_advance(req, cs);
1066
1067         ret = req->engine->emit_flush(req, EMIT_BARRIER);
1068         if (ret)
1069                 return ret;
1070
1071         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
1072
1073         return 0;
1074 }
1075
1076 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1077 #include "selftests/mock_engine.c"
1078 #endif