2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "intel_ringbuffer.h"
27 #include "intel_lrc.h"
29 /* Haswell does have the CXT_SIZE register however it does not appear to be
30 * valid. Now, docs explain in dwords what is in the context object. The full
31 * size is 70720 bytes, however, the power context and execlist context will
32 * never be saved (power context is stored elsewhere, and execlists don't work
33 * on HSW) - so the final size, including the extra state required for the
34 * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
36 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
37 /* Same as Haswell, but 72064 bytes now. */
38 #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE)
40 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
41 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
43 #define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE)
45 struct engine_class_info
{
47 int (*init_legacy
)(struct intel_engine_cs
*engine
);
48 int (*init_execlists
)(struct intel_engine_cs
*engine
);
51 static const struct engine_class_info intel_engine_classes
[] = {
54 .init_execlists
= logical_render_ring_init
,
55 .init_legacy
= intel_init_render_ring_buffer
,
57 [COPY_ENGINE_CLASS
] = {
59 .init_execlists
= logical_xcs_ring_init
,
60 .init_legacy
= intel_init_blt_ring_buffer
,
62 [VIDEO_DECODE_CLASS
] = {
64 .init_execlists
= logical_xcs_ring_init
,
65 .init_legacy
= intel_init_bsd_ring_buffer
,
67 [VIDEO_ENHANCEMENT_CLASS
] = {
69 .init_execlists
= logical_xcs_ring_init
,
70 .init_legacy
= intel_init_vebox_ring_buffer
,
83 static const struct engine_info intel_engines
[] = {
86 .uabi_id
= I915_EXEC_RENDER
,
87 .class = RENDER_CLASS
,
89 .mmio_base
= RENDER_RING_BASE
,
90 .irq_shift
= GEN8_RCS_IRQ_SHIFT
,
94 .uabi_id
= I915_EXEC_BLT
,
95 .class = COPY_ENGINE_CLASS
,
97 .mmio_base
= BLT_RING_BASE
,
98 .irq_shift
= GEN8_BCS_IRQ_SHIFT
,
102 .uabi_id
= I915_EXEC_BSD
,
103 .class = VIDEO_DECODE_CLASS
,
105 .mmio_base
= GEN6_BSD_RING_BASE
,
106 .irq_shift
= GEN8_VCS1_IRQ_SHIFT
,
110 .uabi_id
= I915_EXEC_BSD
,
111 .class = VIDEO_DECODE_CLASS
,
113 .mmio_base
= GEN8_BSD2_RING_BASE
,
114 .irq_shift
= GEN8_VCS2_IRQ_SHIFT
,
118 .uabi_id
= I915_EXEC_VEBOX
,
119 .class = VIDEO_ENHANCEMENT_CLASS
,
121 .mmio_base
= VEBOX_RING_BASE
,
122 .irq_shift
= GEN8_VECS_IRQ_SHIFT
,
127 * ___intel_engine_context_size() - return the size of the context for an engine
128 * @dev_priv: i915 device private
129 * @class: engine class
131 * Each engine class may require a different amount of space for a context
134 * Return: size (in bytes) of an engine class specific context image
136 * Note: this size includes the HWSP, which is part of the context image
137 * in LRC mode, but does not include the "shared data page" used with
138 * GuC submission. The caller should account for this if using the GuC.
141 __intel_engine_context_size(struct drm_i915_private
*dev_priv
, u8
class)
145 BUILD_BUG_ON(I915_GTT_PAGE_SIZE
!= PAGE_SIZE
);
149 switch (INTEL_GEN(dev_priv
)) {
151 MISSING_CASE(INTEL_GEN(dev_priv
));
154 return GEN9_LR_CONTEXT_RENDER_SIZE
;
156 return i915
.enable_execlists
?
157 GEN8_LR_CONTEXT_RENDER_SIZE
:
160 if (IS_HASWELL(dev_priv
))
161 return HSW_CXT_TOTAL_SIZE
;
163 cxt_size
= I915_READ(GEN7_CXT_SIZE
);
164 return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size
) * 64,
167 cxt_size
= I915_READ(CXT_SIZE
);
168 return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size
) * 64,
174 /* For the special day when i810 gets merged. */
181 case VIDEO_DECODE_CLASS
:
182 case VIDEO_ENHANCEMENT_CLASS
:
183 case COPY_ENGINE_CLASS
:
184 if (INTEL_GEN(dev_priv
) < 8)
186 return GEN8_LR_CONTEXT_OTHER_SIZE
;
191 intel_engine_setup(struct drm_i915_private
*dev_priv
,
192 enum intel_engine_id id
)
194 const struct engine_info
*info
= &intel_engines
[id
];
195 const struct engine_class_info
*class_info
;
196 struct intel_engine_cs
*engine
;
198 GEM_BUG_ON(info
->class >= ARRAY_SIZE(intel_engine_classes
));
199 class_info
= &intel_engine_classes
[info
->class];
201 GEM_BUG_ON(dev_priv
->engine
[id
]);
202 engine
= kzalloc(sizeof(*engine
), GFP_KERNEL
);
207 engine
->i915
= dev_priv
;
208 WARN_ON(snprintf(engine
->name
, sizeof(engine
->name
), "%s%u",
209 class_info
->name
, info
->instance
) >=
210 sizeof(engine
->name
));
211 engine
->uabi_id
= info
->uabi_id
;
212 engine
->hw_id
= engine
->guc_id
= info
->hw_id
;
213 engine
->mmio_base
= info
->mmio_base
;
214 engine
->irq_shift
= info
->irq_shift
;
215 engine
->class = info
->class;
216 engine
->instance
= info
->instance
;
218 engine
->context_size
= __intel_engine_context_size(dev_priv
,
220 if (WARN_ON(engine
->context_size
> BIT(20)))
221 engine
->context_size
= 0;
223 /* Nothing to do here, execute in order of dependencies */
224 engine
->schedule
= NULL
;
226 ATOMIC_INIT_NOTIFIER_HEAD(&engine
->context_status_notifier
);
228 dev_priv
->engine
[id
] = engine
;
233 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
234 * @dev_priv: i915 device private
236 * Return: non-zero if the initialization failed.
238 int intel_engines_init_mmio(struct drm_i915_private
*dev_priv
)
240 struct intel_device_info
*device_info
= mkwrite_device_info(dev_priv
);
241 const unsigned int ring_mask
= INTEL_INFO(dev_priv
)->ring_mask
;
242 struct intel_engine_cs
*engine
;
243 enum intel_engine_id id
;
244 unsigned int mask
= 0;
248 WARN_ON(ring_mask
== 0);
250 GENMASK(sizeof(mask
) * BITS_PER_BYTE
- 1, I915_NUM_ENGINES
));
252 for (i
= 0; i
< ARRAY_SIZE(intel_engines
); i
++) {
253 if (!HAS_ENGINE(dev_priv
, i
))
256 err
= intel_engine_setup(dev_priv
, i
);
260 mask
|= ENGINE_MASK(i
);
264 * Catch failures to update intel_engines table when the new engines
265 * are added to the driver by a warning and disabling the forgotten
268 if (WARN_ON(mask
!= ring_mask
))
269 device_info
->ring_mask
= mask
;
271 /* We always presume we have at least RCS available for later probing */
272 if (WARN_ON(!HAS_ENGINE(dev_priv
, RCS
))) {
277 device_info
->num_rings
= hweight32(mask
);
282 for_each_engine(engine
, dev_priv
, id
)
288 * intel_engines_init() - init the Engine Command Streamers
289 * @dev_priv: i915 device private
291 * Return: non-zero if the initialization failed.
293 int intel_engines_init(struct drm_i915_private
*dev_priv
)
295 struct intel_engine_cs
*engine
;
296 enum intel_engine_id id
, err_id
;
299 for_each_engine(engine
, dev_priv
, id
) {
300 const struct engine_class_info
*class_info
=
301 &intel_engine_classes
[engine
->class];
302 int (*init
)(struct intel_engine_cs
*engine
);
304 if (i915
.enable_execlists
)
305 init
= class_info
->init_execlists
;
307 init
= class_info
->init_legacy
;
312 if (GEM_WARN_ON(!init
))
319 GEM_BUG_ON(!engine
->submit_request
);
325 for_each_engine(engine
, dev_priv
, id
) {
328 dev_priv
->engine
[id
] = NULL
;
330 dev_priv
->gt
.cleanup_engine(engine
);
336 void intel_engine_init_global_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
338 struct drm_i915_private
*dev_priv
= engine
->i915
;
340 /* Our semaphore implementation is strictly monotonic (i.e. we proceed
341 * so long as the semaphore value in the register/page is greater
342 * than the sync value), so whenever we reset the seqno,
343 * so long as we reset the tracking semaphore value to 0, it will
344 * always be before the next request's seqno. If we don't reset
345 * the semaphore value, then when the seqno moves backwards all
346 * future waits will complete instantly (causing rendering corruption).
348 if (IS_GEN6(dev_priv
) || IS_GEN7(dev_priv
)) {
349 I915_WRITE(RING_SYNC_0(engine
->mmio_base
), 0);
350 I915_WRITE(RING_SYNC_1(engine
->mmio_base
), 0);
351 if (HAS_VEBOX(dev_priv
))
352 I915_WRITE(RING_SYNC_2(engine
->mmio_base
), 0);
354 if (dev_priv
->semaphore
) {
355 struct page
*page
= i915_vma_first_page(dev_priv
->semaphore
);
358 /* Semaphores are in noncoherent memory, flush to be safe */
359 semaphores
= kmap_atomic(page
);
360 memset(semaphores
+ GEN8_SEMAPHORE_OFFSET(engine
->id
, 0),
361 0, I915_NUM_ENGINES
* gen8_semaphore_seqno_size
);
362 drm_clflush_virt_range(semaphores
+ GEN8_SEMAPHORE_OFFSET(engine
->id
, 0),
363 I915_NUM_ENGINES
* gen8_semaphore_seqno_size
);
364 kunmap_atomic(semaphores
);
367 intel_write_status_page(engine
, I915_GEM_HWS_INDEX
, seqno
);
368 clear_bit(ENGINE_IRQ_BREADCRUMB
, &engine
->irq_posted
);
370 /* After manually advancing the seqno, fake the interrupt in case
371 * there are any waiters for that seqno.
373 intel_engine_wakeup(engine
);
375 GEM_BUG_ON(intel_engine_get_seqno(engine
) != seqno
);
378 static void intel_engine_init_timeline(struct intel_engine_cs
*engine
)
380 engine
->timeline
= &engine
->i915
->gt
.global_timeline
.engine
[engine
->id
];
384 * intel_engines_setup_common - setup engine state not requiring hw access
385 * @engine: Engine to setup.
387 * Initializes @engine@ structure members shared between legacy and execlists
388 * submission modes which do not require hardware access.
390 * Typically done early in the submission mode specific engine setup stage.
392 void intel_engine_setup_common(struct intel_engine_cs
*engine
)
394 engine
->execlist_queue
= RB_ROOT
;
395 engine
->execlist_first
= NULL
;
397 intel_engine_init_timeline(engine
);
398 intel_engine_init_hangcheck(engine
);
399 i915_gem_batch_pool_init(engine
, &engine
->batch_pool
);
401 intel_engine_init_cmd_parser(engine
);
404 int intel_engine_create_scratch(struct intel_engine_cs
*engine
, int size
)
406 struct drm_i915_gem_object
*obj
;
407 struct i915_vma
*vma
;
410 WARN_ON(engine
->scratch
);
412 obj
= i915_gem_object_create_stolen(engine
->i915
, size
);
414 obj
= i915_gem_object_create_internal(engine
->i915
, size
);
416 DRM_ERROR("Failed to allocate scratch page\n");
420 vma
= i915_vma_instance(obj
, &engine
->i915
->ggtt
.base
, NULL
);
426 ret
= i915_vma_pin(vma
, 0, 4096, PIN_GLOBAL
| PIN_HIGH
);
430 engine
->scratch
= vma
;
431 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
432 engine
->name
, i915_ggtt_offset(vma
));
436 i915_gem_object_put(obj
);
440 static void intel_engine_cleanup_scratch(struct intel_engine_cs
*engine
)
442 i915_vma_unpin_and_release(&engine
->scratch
);
446 * intel_engines_init_common - initialize cengine state which might require hw access
447 * @engine: Engine to initialize.
449 * Initializes @engine@ structure members shared between legacy and execlists
450 * submission modes which do require hardware access.
452 * Typcally done at later stages of submission mode specific engine setup.
454 * Returns zero on success or an error code on failure.
456 int intel_engine_init_common(struct intel_engine_cs
*engine
)
458 struct intel_ring
*ring
;
461 engine
->set_default_submission(engine
);
463 /* We may need to do things with the shrinker which
464 * require us to immediately switch back to the default
465 * context. This can cause a problem as pinning the
466 * default context also requires GTT space which may not
467 * be available. To avoid this we always pin the default
470 ring
= engine
->context_pin(engine
, engine
->i915
->kernel_context
);
472 return PTR_ERR(ring
);
474 ret
= intel_engine_init_breadcrumbs(engine
);
478 ret
= i915_gem_render_state_init(engine
);
485 engine
->context_unpin(engine
, engine
->i915
->kernel_context
);
490 * intel_engines_cleanup_common - cleans up the engine state created by
491 * the common initiailizers.
492 * @engine: Engine to cleanup.
494 * This cleans up everything created by the common helpers.
496 void intel_engine_cleanup_common(struct intel_engine_cs
*engine
)
498 intel_engine_cleanup_scratch(engine
);
500 i915_gem_render_state_fini(engine
);
501 intel_engine_fini_breadcrumbs(engine
);
502 intel_engine_cleanup_cmd_parser(engine
);
503 i915_gem_batch_pool_fini(&engine
->batch_pool
);
505 engine
->context_unpin(engine
, engine
->i915
->kernel_context
);
508 u64
intel_engine_get_active_head(struct intel_engine_cs
*engine
)
510 struct drm_i915_private
*dev_priv
= engine
->i915
;
513 if (INTEL_GEN(dev_priv
) >= 8)
514 acthd
= I915_READ64_2x32(RING_ACTHD(engine
->mmio_base
),
515 RING_ACTHD_UDW(engine
->mmio_base
));
516 else if (INTEL_GEN(dev_priv
) >= 4)
517 acthd
= I915_READ(RING_ACTHD(engine
->mmio_base
));
519 acthd
= I915_READ(ACTHD
);
524 u64
intel_engine_get_last_batch_head(struct intel_engine_cs
*engine
)
526 struct drm_i915_private
*dev_priv
= engine
->i915
;
529 if (INTEL_GEN(dev_priv
) >= 8)
530 bbaddr
= I915_READ64_2x32(RING_BBADDR(engine
->mmio_base
),
531 RING_BBADDR_UDW(engine
->mmio_base
));
533 bbaddr
= I915_READ(RING_BBADDR(engine
->mmio_base
));
538 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
)
541 case I915_CACHE_NONE
: return " uncached";
542 case I915_CACHE_LLC
: return HAS_LLC(i915
) ? " LLC" : " snooped";
543 case I915_CACHE_L3_LLC
: return " L3+LLC";
544 case I915_CACHE_WT
: return " WT";
549 static inline uint32_t
550 read_subslice_reg(struct drm_i915_private
*dev_priv
, int slice
,
551 int subslice
, i915_reg_t reg
)
555 enum forcewake_domains fw_domains
;
557 fw_domains
= intel_uncore_forcewake_for_reg(dev_priv
, reg
,
559 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
561 FW_REG_READ
| FW_REG_WRITE
);
563 spin_lock_irq(&dev_priv
->uncore
.lock
);
564 intel_uncore_forcewake_get__locked(dev_priv
, fw_domains
);
566 mcr
= I915_READ_FW(GEN8_MCR_SELECTOR
);
568 * The HW expects the slice and sublice selectors to be reset to 0
569 * after reading out the registers.
571 WARN_ON_ONCE(mcr
& (GEN8_MCR_SLICE_MASK
| GEN8_MCR_SUBSLICE_MASK
));
572 mcr
&= ~(GEN8_MCR_SLICE_MASK
| GEN8_MCR_SUBSLICE_MASK
);
573 mcr
|= GEN8_MCR_SLICE(slice
) | GEN8_MCR_SUBSLICE(subslice
);
574 I915_WRITE_FW(GEN8_MCR_SELECTOR
, mcr
);
576 ret
= I915_READ_FW(reg
);
578 mcr
&= ~(GEN8_MCR_SLICE_MASK
| GEN8_MCR_SUBSLICE_MASK
);
579 I915_WRITE_FW(GEN8_MCR_SELECTOR
, mcr
);
581 intel_uncore_forcewake_put__locked(dev_priv
, fw_domains
);
582 spin_unlock_irq(&dev_priv
->uncore
.lock
);
587 /* NB: please notice the memset */
588 void intel_engine_get_instdone(struct intel_engine_cs
*engine
,
589 struct intel_instdone
*instdone
)
591 struct drm_i915_private
*dev_priv
= engine
->i915
;
592 u32 mmio_base
= engine
->mmio_base
;
596 memset(instdone
, 0, sizeof(*instdone
));
598 switch (INTEL_GEN(dev_priv
)) {
600 instdone
->instdone
= I915_READ(RING_INSTDONE(mmio_base
));
602 if (engine
->id
!= RCS
)
605 instdone
->slice_common
= I915_READ(GEN7_SC_INSTDONE
);
606 for_each_instdone_slice_subslice(dev_priv
, slice
, subslice
) {
607 instdone
->sampler
[slice
][subslice
] =
608 read_subslice_reg(dev_priv
, slice
, subslice
,
609 GEN7_SAMPLER_INSTDONE
);
610 instdone
->row
[slice
][subslice
] =
611 read_subslice_reg(dev_priv
, slice
, subslice
,
616 instdone
->instdone
= I915_READ(RING_INSTDONE(mmio_base
));
618 if (engine
->id
!= RCS
)
621 instdone
->slice_common
= I915_READ(GEN7_SC_INSTDONE
);
622 instdone
->sampler
[0][0] = I915_READ(GEN7_SAMPLER_INSTDONE
);
623 instdone
->row
[0][0] = I915_READ(GEN7_ROW_INSTDONE
);
629 instdone
->instdone
= I915_READ(RING_INSTDONE(mmio_base
));
631 if (engine
->id
== RCS
)
632 /* HACK: Using the wrong struct member */
633 instdone
->slice_common
= I915_READ(GEN4_INSTDONE1
);
637 instdone
->instdone
= I915_READ(GEN2_INSTDONE
);
642 static int wa_add(struct drm_i915_private
*dev_priv
,
644 const u32 mask
, const u32 val
)
646 const u32 idx
= dev_priv
->workarounds
.count
;
648 if (WARN_ON(idx
>= I915_MAX_WA_REGS
))
651 dev_priv
->workarounds
.reg
[idx
].addr
= addr
;
652 dev_priv
->workarounds
.reg
[idx
].value
= val
;
653 dev_priv
->workarounds
.reg
[idx
].mask
= mask
;
655 dev_priv
->workarounds
.count
++;
660 #define WA_REG(addr, mask, val) do { \
661 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
666 #define WA_SET_BIT_MASKED(addr, mask) \
667 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
669 #define WA_CLR_BIT_MASKED(addr, mask) \
670 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
672 #define WA_SET_FIELD_MASKED(addr, mask, value) \
673 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
675 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
676 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
678 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
680 static int wa_ring_whitelist_reg(struct intel_engine_cs
*engine
,
683 struct drm_i915_private
*dev_priv
= engine
->i915
;
684 struct i915_workarounds
*wa
= &dev_priv
->workarounds
;
685 const uint32_t index
= wa
->hw_whitelist_count
[engine
->id
];
687 if (WARN_ON(index
>= RING_MAX_NONPRIV_SLOTS
))
690 WA_WRITE(RING_FORCE_TO_NONPRIV(engine
->mmio_base
, index
),
691 i915_mmio_reg_offset(reg
));
692 wa
->hw_whitelist_count
[engine
->id
]++;
697 static int gen8_init_workarounds(struct intel_engine_cs
*engine
)
699 struct drm_i915_private
*dev_priv
= engine
->i915
;
701 WA_SET_BIT_MASKED(INSTPM
, INSTPM_FORCE_ORDERING
);
703 /* WaDisableAsyncFlipPerfMode:bdw,chv */
704 WA_SET_BIT_MASKED(MI_MODE
, ASYNC_FLIP_PERF_DISABLE
);
706 /* WaDisablePartialInstShootdown:bdw,chv */
707 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
708 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
710 /* Use Force Non-Coherent whenever executing a 3D context. This is a
711 * workaround for for a possible hang in the unlikely event a TLB
712 * invalidation occurs during a PSD flush.
714 /* WaForceEnableNonCoherent:bdw,chv */
715 /* WaHdcDisableFetchWhenMasked:bdw,chv */
716 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
717 HDC_DONOT_FETCH_MEM_WHEN_MASKED
|
718 HDC_FORCE_NON_COHERENT
);
720 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
721 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
722 * polygons in the same 8x4 pixel/sample area to be processed without
723 * stalling waiting for the earlier ones to write to Hierarchical Z
726 * This optimization is off by default for BDW and CHV; turn it on.
728 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7
, HIZ_RAW_STALL_OPT_DISABLE
);
730 /* Wa4x4STCOptimizationDisable:bdw,chv */
731 WA_SET_BIT_MASKED(CACHE_MODE_1
, GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
734 * BSpec recommends 8x4 when MSAA is used,
735 * however in practice 16x4 seems fastest.
737 * Note that PS/WM thread counts depend on the WIZ hashing
738 * disable bit, which we don't touch here, but it's good
739 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
741 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
742 GEN6_WIZ_HASHING_MASK
,
743 GEN6_WIZ_HASHING_16x4
);
748 static int bdw_init_workarounds(struct intel_engine_cs
*engine
)
750 struct drm_i915_private
*dev_priv
= engine
->i915
;
753 ret
= gen8_init_workarounds(engine
);
757 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
758 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
760 /* WaDisableDopClockGating:bdw
762 * Also see the related UCGTCL1 write in broadwell_init_clock_gating()
763 * to disable EUTC clock gating.
765 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2
,
766 DOP_CLOCK_GATING_DISABLE
);
768 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
769 GEN8_SAMPLER_POWER_BYPASS_DIS
);
771 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
772 /* WaForceContextSaveRestoreNonCoherent:bdw */
773 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
774 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
775 (IS_BDW_GT3(dev_priv
) ? HDC_FENCE_DEST_SLM_DISABLE
: 0));
780 static int chv_init_workarounds(struct intel_engine_cs
*engine
)
782 struct drm_i915_private
*dev_priv
= engine
->i915
;
785 ret
= gen8_init_workarounds(engine
);
789 /* WaDisableThreadStallDopClockGating:chv */
790 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
792 /* Improve HiZ throughput on CHV. */
793 WA_SET_BIT_MASKED(HIZ_CHICKEN
, CHV_HZ_8X8_MODE_IN_1X
);
798 static int gen9_init_workarounds(struct intel_engine_cs
*engine
)
800 struct drm_i915_private
*dev_priv
= engine
->i915
;
803 /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
804 I915_WRITE(GEN9_CSFE_CHICKEN1_RCS
, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE
));
806 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
807 I915_WRITE(BDW_SCRATCH1
, I915_READ(BDW_SCRATCH1
) |
808 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE
);
810 /* WaDisableKillLogic:bxt,skl,kbl */
811 if (!IS_COFFEELAKE(dev_priv
))
812 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
815 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
816 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
817 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
818 FLOW_CONTROL_ENABLE
|
819 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
821 /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
822 if (!IS_COFFEELAKE(dev_priv
))
823 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
824 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC
);
826 /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
827 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
828 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
829 GEN9_DG_MIRROR_FIX_ENABLE
);
831 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
832 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
833 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1
,
834 GEN9_RHWO_OPTIMIZATION_DISABLE
);
836 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
837 * but we do that in per ctx batchbuffer as there is an issue
838 * with this register not getting restored on ctx restore
842 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
843 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
844 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7
,
845 GEN9_ENABLE_YV12_BUGFIX
|
846 GEN9_ENABLE_GPGPU_PREEMPTION
);
848 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */
849 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */
850 WA_SET_BIT_MASKED(CACHE_MODE_1
, (GEN8_4x4_STC_OPTIMIZATION_DISABLE
|
851 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE
));
853 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */
854 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
855 GEN9_CCS_TLB_PREFETCH_ENABLE
);
857 /* WaDisableMaskBasedCammingInRCC:bxt */
858 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
859 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0
,
860 PIXEL_MASK_CAMMING_DISABLE
);
862 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
863 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
864 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
865 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE
);
867 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
868 * both tied to WaForceContextSaveRestoreNonCoherent
869 * in some hsds for skl. We keep the tie for all gen9. The
870 * documentation is a bit hazy and so we want to get common behaviour,
871 * even though there is no clear evidence we would need both on kbl/bxt.
872 * This area has been source of system hangs so we play it safe
873 * and mimic the skl regardless of what bspec says.
875 * Use Force Non-Coherent whenever executing a 3D context. This
876 * is a workaround for a possible hang in the unlikely event
877 * a TLB invalidation occurs during a PSD flush.
880 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */
881 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
882 HDC_FORCE_NON_COHERENT
);
884 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
885 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
886 BDW_DISABLE_HDC_INVALIDATION
);
888 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
889 if (IS_SKYLAKE(dev_priv
) ||
890 IS_KABYLAKE(dev_priv
) ||
891 IS_COFFEELAKE(dev_priv
) ||
892 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B0
))
893 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
894 GEN8_SAMPLER_POWER_BYPASS_DIS
);
896 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
897 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2
, GEN8_ST_PO_DISABLE
);
899 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
900 I915_WRITE(GEN8_L3SQCREG4
, (I915_READ(GEN8_L3SQCREG4
) |
901 GEN8_LQSC_FLUSH_COHERENT_LINES
));
903 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
904 ret
= wa_ring_whitelist_reg(engine
, GEN9_CTX_PREEMPT_REG
);
908 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl */
909 ret
= wa_ring_whitelist_reg(engine
, GEN8_CS_CHICKEN1
);
913 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */
914 ret
= wa_ring_whitelist_reg(engine
, GEN8_HDC_CHICKEN1
);
921 static int skl_tune_iz_hashing(struct intel_engine_cs
*engine
)
923 struct drm_i915_private
*dev_priv
= engine
->i915
;
924 u8 vals
[3] = { 0, 0, 0 };
927 for (i
= 0; i
< 3; i
++) {
931 * Only consider slices where one, and only one, subslice has 7
934 if (!is_power_of_2(INTEL_INFO(dev_priv
)->sseu
.subslice_7eu
[i
]))
938 * subslice_7eu[i] != 0 (because of the check above) and
939 * ss_max == 4 (maximum number of subslices possible per slice)
943 ss
= ffs(INTEL_INFO(dev_priv
)->sseu
.subslice_7eu
[i
]) - 1;
947 if (vals
[0] == 0 && vals
[1] == 0 && vals
[2] == 0)
950 /* Tune IZ hashing. See intel_device_info_runtime_init() */
951 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
952 GEN9_IZ_HASHING_MASK(2) |
953 GEN9_IZ_HASHING_MASK(1) |
954 GEN9_IZ_HASHING_MASK(0),
955 GEN9_IZ_HASHING(2, vals
[2]) |
956 GEN9_IZ_HASHING(1, vals
[1]) |
957 GEN9_IZ_HASHING(0, vals
[0]));
962 static int skl_init_workarounds(struct intel_engine_cs
*engine
)
964 struct drm_i915_private
*dev_priv
= engine
->i915
;
967 ret
= gen9_init_workarounds(engine
);
972 * Actual WA is to disable percontext preemption granularity control
973 * until D0 which is the default case so this is equivalent to
974 * !WaDisablePerCtxtPreemptionGranularityControl:skl
976 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1
,
977 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL
));
979 /* WaEnableGapsTsvCreditFix:skl */
980 I915_WRITE(GEN8_GARBCNTL
, (I915_READ(GEN8_GARBCNTL
) |
981 GEN9_GAPS_TSV_CREDIT_DISABLE
));
983 /* WaDisableGafsUnitClkGating:skl */
984 WA_SET_BIT(GEN7_UCGCTL4
, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE
);
986 /* WaInPlaceDecompressionHang:skl */
987 if (IS_SKL_REVID(dev_priv
, SKL_REVID_H0
, REVID_FOREVER
))
988 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA
,
989 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS
);
991 /* WaDisableLSQCROPERFforOCL:skl */
992 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
996 return skl_tune_iz_hashing(engine
);
999 static int bxt_init_workarounds(struct intel_engine_cs
*engine
)
1001 struct drm_i915_private
*dev_priv
= engine
->i915
;
1004 ret
= gen9_init_workarounds(engine
);
1008 /* WaStoreMultiplePTEenable:bxt */
1009 /* This is a requirement according to Hardware specification */
1010 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
1011 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_TLBPF
);
1013 /* WaSetClckGatingDisableMedia:bxt */
1014 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
1015 I915_WRITE(GEN7_MISCCPCTL
, (I915_READ(GEN7_MISCCPCTL
) &
1016 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE
));
1019 /* WaDisableThreadStallDopClockGating:bxt */
1020 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
1021 STALL_DOP_GATING_DISABLE
);
1023 /* WaDisablePooledEuLoadBalancingFix:bxt */
1024 if (IS_BXT_REVID(dev_priv
, BXT_REVID_B0
, REVID_FOREVER
)) {
1025 WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2
,
1026 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE
);
1029 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1030 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B0
)) {
1032 GEN7_HALF_SLICE_CHICKEN1
,
1033 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1036 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1037 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1038 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1039 /* WaDisableLSQCROPERFforOCL:bxt */
1040 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
1041 ret
= wa_ring_whitelist_reg(engine
, GEN9_CS_DEBUG_MODE1
);
1045 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1050 /* WaProgramL3SqcReg1DefaultForPerf:bxt */
1051 if (IS_BXT_REVID(dev_priv
, BXT_REVID_B0
, REVID_FOREVER
)) {
1052 u32 val
= I915_READ(GEN8_L3SQCREG1
);
1053 val
&= ~L3_PRIO_CREDITS_MASK
;
1054 val
|= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);
1055 I915_WRITE(GEN8_L3SQCREG1
, val
);
1058 /* WaToEnableHwFixForPushConstHWBug:bxt */
1059 if (IS_BXT_REVID(dev_priv
, BXT_REVID_C0
, REVID_FOREVER
))
1060 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2
,
1061 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION
);
1063 /* WaInPlaceDecompressionHang:bxt */
1064 if (IS_BXT_REVID(dev_priv
, BXT_REVID_C0
, REVID_FOREVER
))
1065 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA
,
1066 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS
);
1071 static int kbl_init_workarounds(struct intel_engine_cs
*engine
)
1073 struct drm_i915_private
*dev_priv
= engine
->i915
;
1076 ret
= gen9_init_workarounds(engine
);
1080 /* WaEnableGapsTsvCreditFix:kbl */
1081 I915_WRITE(GEN8_GARBCNTL
, (I915_READ(GEN8_GARBCNTL
) |
1082 GEN9_GAPS_TSV_CREDIT_DISABLE
));
1084 /* WaDisableDynamicCreditSharing:kbl */
1085 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
1086 WA_SET_BIT(GAMT_CHKN_BIT_REG
,
1087 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING
);
1089 /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
1090 if (IS_KBL_REVID(dev_priv
, KBL_REVID_A0
, KBL_REVID_A0
))
1091 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1092 HDC_FENCE_DEST_SLM_DISABLE
);
1094 /* WaToEnableHwFixForPushConstHWBug:kbl */
1095 if (IS_KBL_REVID(dev_priv
, KBL_REVID_C0
, REVID_FOREVER
))
1096 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2
,
1097 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION
);
1099 /* WaDisableGafsUnitClkGating:kbl */
1100 WA_SET_BIT(GEN7_UCGCTL4
, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE
);
1102 /* WaDisableSbeCacheDispatchPortSharing:kbl */
1104 GEN7_HALF_SLICE_CHICKEN1
,
1105 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1107 /* WaInPlaceDecompressionHang:kbl */
1108 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA
,
1109 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS
);
1111 /* WaDisableLSQCROPERFforOCL:kbl */
1112 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1119 static int glk_init_workarounds(struct intel_engine_cs
*engine
)
1121 struct drm_i915_private
*dev_priv
= engine
->i915
;
1124 ret
= gen9_init_workarounds(engine
);
1128 /* WaToEnableHwFixForPushConstHWBug:glk */
1129 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2
,
1130 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION
);
1135 static int cfl_init_workarounds(struct intel_engine_cs
*engine
)
1137 struct drm_i915_private
*dev_priv
= engine
->i915
;
1140 ret
= gen9_init_workarounds(engine
);
1144 /* WaEnableGapsTsvCreditFix:cfl */
1145 I915_WRITE(GEN8_GARBCNTL
, (I915_READ(GEN8_GARBCNTL
) |
1146 GEN9_GAPS_TSV_CREDIT_DISABLE
));
1148 /* WaToEnableHwFixForPushConstHWBug:cfl */
1149 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2
,
1150 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION
);
1152 /* WaDisableGafsUnitClkGating:cfl */
1153 WA_SET_BIT(GEN7_UCGCTL4
, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE
);
1155 /* WaDisableSbeCacheDispatchPortSharing:cfl */
1157 GEN7_HALF_SLICE_CHICKEN1
,
1158 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1160 /* WaInPlaceDecompressionHang:cfl */
1161 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA
,
1162 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS
);
1167 int init_workarounds_ring(struct intel_engine_cs
*engine
)
1169 struct drm_i915_private
*dev_priv
= engine
->i915
;
1172 WARN_ON(engine
->id
!= RCS
);
1174 dev_priv
->workarounds
.count
= 0;
1175 dev_priv
->workarounds
.hw_whitelist_count
[engine
->id
] = 0;
1177 if (IS_BROADWELL(dev_priv
))
1178 err
= bdw_init_workarounds(engine
);
1179 else if (IS_CHERRYVIEW(dev_priv
))
1180 err
= chv_init_workarounds(engine
);
1181 else if (IS_SKYLAKE(dev_priv
))
1182 err
= skl_init_workarounds(engine
);
1183 else if (IS_BROXTON(dev_priv
))
1184 err
= bxt_init_workarounds(engine
);
1185 else if (IS_KABYLAKE(dev_priv
))
1186 err
= kbl_init_workarounds(engine
);
1187 else if (IS_GEMINILAKE(dev_priv
))
1188 err
= glk_init_workarounds(engine
);
1189 else if (IS_COFFEELAKE(dev_priv
))
1190 err
= cfl_init_workarounds(engine
);
1196 DRM_DEBUG_DRIVER("%s: Number of context specific w/a: %d\n",
1197 engine
->name
, dev_priv
->workarounds
.count
);
1201 int intel_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
1203 struct i915_workarounds
*w
= &req
->i915
->workarounds
;
1210 ret
= req
->engine
->emit_flush(req
, EMIT_BARRIER
);
1214 cs
= intel_ring_begin(req
, (w
->count
* 2 + 2));
1218 *cs
++ = MI_LOAD_REGISTER_IMM(w
->count
);
1219 for (i
= 0; i
< w
->count
; i
++) {
1220 *cs
++ = i915_mmio_reg_offset(w
->reg
[i
].addr
);
1221 *cs
++ = w
->reg
[i
].value
;
1225 intel_ring_advance(req
, cs
);
1227 ret
= req
->engine
->emit_flush(req
, EMIT_BARRIER
);
1234 static bool ring_is_idle(struct intel_engine_cs
*engine
)
1236 struct drm_i915_private
*dev_priv
= engine
->i915
;
1239 intel_runtime_pm_get(dev_priv
);
1241 /* First check that no commands are left in the ring */
1242 if ((I915_READ_HEAD(engine
) & HEAD_ADDR
) !=
1243 (I915_READ_TAIL(engine
) & TAIL_ADDR
))
1246 /* No bit for gen2, so assume the CS parser is idle */
1247 if (INTEL_GEN(dev_priv
) > 2 && !(I915_READ_MODE(engine
) & MODE_IDLE
))
1250 intel_runtime_pm_put(dev_priv
);
1256 * intel_engine_is_idle() - Report if the engine has finished process all work
1257 * @engine: the intel_engine_cs
1259 * Return true if there are no requests pending, nothing left to be submitted
1260 * to hardware, and that the engine is idle.
1262 bool intel_engine_is_idle(struct intel_engine_cs
*engine
)
1264 struct drm_i915_private
*dev_priv
= engine
->i915
;
1266 /* More white lies, if wedged, hw state is inconsistent */
1267 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
1270 /* Any inflight/incomplete requests? */
1271 if (!i915_seqno_passed(intel_engine_get_seqno(engine
),
1272 intel_engine_last_submit(engine
)))
1275 if (I915_SELFTEST_ONLY(engine
->breadcrumbs
.mock
))
1278 /* Interrupt/tasklet pending? */
1279 if (test_bit(ENGINE_IRQ_EXECLIST
, &engine
->irq_posted
))
1282 /* Both ports drained, no more ELSP submission? */
1283 if (port_request(&engine
->execlist_port
[0]))
1286 /* ELSP is empty, but there are ready requests? */
1287 if (READ_ONCE(engine
->execlist_first
))
1291 if (!ring_is_idle(engine
))
1297 bool intel_engines_are_idle(struct drm_i915_private
*dev_priv
)
1299 struct intel_engine_cs
*engine
;
1300 enum intel_engine_id id
;
1302 if (READ_ONCE(dev_priv
->gt
.active_requests
))
1305 /* If the driver is wedged, HW state may be very inconsistent and
1306 * report that it is still busy, even though we have stopped using it.
1308 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
1311 for_each_engine(engine
, dev_priv
, id
) {
1312 if (!intel_engine_is_idle(engine
))
1319 void intel_engines_reset_default_submission(struct drm_i915_private
*i915
)
1321 struct intel_engine_cs
*engine
;
1322 enum intel_engine_id id
;
1324 for_each_engine(engine
, i915
, id
)
1325 engine
->set_default_submission(engine
);
1328 void intel_engines_mark_idle(struct drm_i915_private
*i915
)
1330 struct intel_engine_cs
*engine
;
1331 enum intel_engine_id id
;
1333 for_each_engine(engine
, i915
, id
) {
1334 intel_engine_disarm_breadcrumbs(engine
);
1335 i915_gem_batch_pool_fini(&engine
->batch_pool
);
1336 tasklet_kill(&engine
->irq_tasklet
);
1337 engine
->no_priolist
= false;
1341 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1342 #include "selftests/mock_engine.c"