2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
25 * DOC: Frame Buffer Compression (FBC)
27 * FBC tries to save memory bandwidth (and so power consumption) by
28 * compressing the amount of memory used by the display. It is total
29 * transparent to user space and completely handled in the kernel.
31 * The benefits of FBC are mostly visible with solid backgrounds and
32 * variation-less patterns. It comes from keeping the memory footprint small
33 * and having fewer memory pages opened and accessed for refreshing the display.
35 * i915 is responsible to reserve stolen memory for FBC and configure its
36 * offset on proper registers. The hardware takes care of all
37 * compress/decompress. However there are many known cases where we have to
38 * forcibly disable it to allow proper screen updates.
41 #include "intel_drv.h"
44 static void i8xx_fbc_disable(struct drm_i915_private
*dev_priv
)
48 dev_priv
->fbc
.enabled
= false;
50 /* Disable compression */
51 fbc_ctl
= I915_READ(FBC_CONTROL
);
52 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
55 fbc_ctl
&= ~FBC_CTL_EN
;
56 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
58 /* Wait for compressing bit to clear */
59 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
60 DRM_DEBUG_KMS("FBC idle timed out\n");
64 DRM_DEBUG_KMS("disabled FBC\n");
67 static void i8xx_fbc_enable(struct intel_crtc
*crtc
)
69 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
70 struct drm_framebuffer
*fb
= crtc
->base
.primary
->fb
;
71 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
76 dev_priv
->fbc
.enabled
= true;
78 /* Note: fbc.threshold == 1 for i8xx */
79 cfb_pitch
= dev_priv
->fbc
.uncompressed_size
/ FBC_LL_SIZE
;
80 if (fb
->pitches
[0] < cfb_pitch
)
81 cfb_pitch
= fb
->pitches
[0];
83 /* FBC_CTL wants 32B or 64B units */
84 if (IS_GEN2(dev_priv
))
85 cfb_pitch
= (cfb_pitch
/ 32) - 1;
87 cfb_pitch
= (cfb_pitch
/ 64) - 1;
90 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
91 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
93 if (IS_GEN4(dev_priv
)) {
97 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| FBC_CTL_CPU_FENCE
;
98 fbc_ctl2
|= FBC_CTL_PLANE(crtc
->plane
);
99 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
100 I915_WRITE(FBC_FENCE_OFF
, crtc
->base
.y
);
104 fbc_ctl
= I915_READ(FBC_CONTROL
);
105 fbc_ctl
&= 0x3fff << FBC_CTL_INTERVAL_SHIFT
;
106 fbc_ctl
|= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
107 if (IS_I945GM(dev_priv
))
108 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
109 fbc_ctl
|= (cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
110 fbc_ctl
|= obj
->fence_reg
;
111 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
113 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
114 cfb_pitch
, crtc
->base
.y
, plane_name(crtc
->plane
));
117 static bool i8xx_fbc_enabled(struct drm_i915_private
*dev_priv
)
119 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
122 static void g4x_fbc_enable(struct intel_crtc
*crtc
)
124 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
125 struct drm_framebuffer
*fb
= crtc
->base
.primary
->fb
;
126 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
129 dev_priv
->fbc
.enabled
= true;
131 dpfc_ctl
= DPFC_CTL_PLANE(crtc
->plane
) | DPFC_SR_EN
;
132 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
133 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
135 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
136 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| obj
->fence_reg
;
138 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->base
.y
);
141 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
143 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc
->plane
));
146 static void g4x_fbc_disable(struct drm_i915_private
*dev_priv
)
150 dev_priv
->fbc
.enabled
= false;
152 /* Disable compression */
153 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
154 if (dpfc_ctl
& DPFC_CTL_EN
) {
155 dpfc_ctl
&= ~DPFC_CTL_EN
;
156 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
158 DRM_DEBUG_KMS("disabled FBC\n");
162 static bool g4x_fbc_enabled(struct drm_i915_private
*dev_priv
)
164 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
167 static void intel_fbc_nuke(struct drm_i915_private
*dev_priv
)
169 I915_WRITE(MSG_FBC_REND_STATE
, FBC_REND_NUKE
);
170 POSTING_READ(MSG_FBC_REND_STATE
);
173 static void ilk_fbc_enable(struct intel_crtc
*crtc
)
175 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
176 struct drm_framebuffer
*fb
= crtc
->base
.primary
->fb
;
177 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
179 int threshold
= dev_priv
->fbc
.threshold
;
181 dev_priv
->fbc
.enabled
= true;
183 dpfc_ctl
= DPFC_CTL_PLANE(crtc
->plane
);
184 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
190 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
193 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
196 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
199 dpfc_ctl
|= DPFC_CTL_FENCE_EN
;
200 if (IS_GEN5(dev_priv
))
201 dpfc_ctl
|= obj
->fence_reg
;
203 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->base
.y
);
204 I915_WRITE(ILK_FBC_RT_BASE
, i915_gem_obj_ggtt_offset(obj
) | ILK_FBC_RT_VALID
);
206 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
208 if (IS_GEN6(dev_priv
)) {
209 I915_WRITE(SNB_DPFC_CTL_SA
,
210 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
211 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->base
.y
);
214 intel_fbc_nuke(dev_priv
);
216 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc
->plane
));
219 static void ilk_fbc_disable(struct drm_i915_private
*dev_priv
)
223 dev_priv
->fbc
.enabled
= false;
225 /* Disable compression */
226 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
227 if (dpfc_ctl
& DPFC_CTL_EN
) {
228 dpfc_ctl
&= ~DPFC_CTL_EN
;
229 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
231 DRM_DEBUG_KMS("disabled FBC\n");
235 static bool ilk_fbc_enabled(struct drm_i915_private
*dev_priv
)
237 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
240 static void gen7_fbc_enable(struct intel_crtc
*crtc
)
242 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
243 struct drm_framebuffer
*fb
= crtc
->base
.primary
->fb
;
244 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
246 int threshold
= dev_priv
->fbc
.threshold
;
248 dev_priv
->fbc
.enabled
= true;
251 if (IS_IVYBRIDGE(dev_priv
))
252 dpfc_ctl
|= IVB_DPFC_CTL_PLANE(crtc
->plane
);
254 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
260 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
263 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
266 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
270 dpfc_ctl
|= IVB_DPFC_CTL_FENCE_EN
;
272 if (dev_priv
->fbc
.false_color
)
273 dpfc_ctl
|= FBC_CTL_FALSE_COLOR
;
275 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
277 if (IS_IVYBRIDGE(dev_priv
)) {
278 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
279 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
280 I915_READ(ILK_DISPLAY_CHICKEN1
) |
283 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
284 I915_WRITE(CHICKEN_PIPESL_1(crtc
->pipe
),
285 I915_READ(CHICKEN_PIPESL_1(crtc
->pipe
)) |
289 I915_WRITE(SNB_DPFC_CTL_SA
,
290 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
291 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->base
.y
);
293 intel_fbc_nuke(dev_priv
);
295 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc
->plane
));
299 * intel_fbc_enabled - Is FBC enabled?
300 * @dev_priv: i915 device instance
302 * This function is used to verify the current state of FBC.
303 * FIXME: This should be tracked in the plane config eventually
304 * instead of queried at runtime for most callers.
306 bool intel_fbc_enabled(struct drm_i915_private
*dev_priv
)
308 return dev_priv
->fbc
.enabled
;
311 static void intel_fbc_work_fn(struct work_struct
*__work
)
313 struct intel_fbc_work
*work
=
314 container_of(to_delayed_work(__work
),
315 struct intel_fbc_work
, work
);
316 struct drm_i915_private
*dev_priv
= work
->crtc
->base
.dev
->dev_private
;
317 struct drm_framebuffer
*crtc_fb
= work
->crtc
->base
.primary
->fb
;
319 mutex_lock(&dev_priv
->fbc
.lock
);
320 if (work
== dev_priv
->fbc
.fbc_work
) {
321 /* Double check that we haven't switched fb without cancelling
324 if (crtc_fb
== work
->fb
) {
325 dev_priv
->fbc
.enable_fbc(work
->crtc
);
327 dev_priv
->fbc
.crtc
= work
->crtc
;
328 dev_priv
->fbc
.fb_id
= crtc_fb
->base
.id
;
329 dev_priv
->fbc
.y
= work
->crtc
->base
.y
;
332 dev_priv
->fbc
.fbc_work
= NULL
;
334 mutex_unlock(&dev_priv
->fbc
.lock
);
339 static void intel_fbc_cancel_work(struct drm_i915_private
*dev_priv
)
341 WARN_ON(!mutex_is_locked(&dev_priv
->fbc
.lock
));
343 if (dev_priv
->fbc
.fbc_work
== NULL
)
346 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
348 /* Synchronisation is provided by struct_mutex and checking of
349 * dev_priv->fbc.fbc_work, so we can perform the cancellation
350 * entirely asynchronously.
352 if (cancel_delayed_work(&dev_priv
->fbc
.fbc_work
->work
))
353 /* tasklet was killed before being run, clean up */
354 kfree(dev_priv
->fbc
.fbc_work
);
356 /* Mark the work as no longer wanted so that if it does
357 * wake-up (because the work was already running and waiting
358 * for our mutex), it will discover that is no longer
361 dev_priv
->fbc
.fbc_work
= NULL
;
364 static void intel_fbc_enable(struct intel_crtc
*crtc
)
366 struct intel_fbc_work
*work
;
367 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
369 WARN_ON(!mutex_is_locked(&dev_priv
->fbc
.lock
));
371 intel_fbc_cancel_work(dev_priv
);
373 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
375 DRM_ERROR("Failed to allocate FBC work structure\n");
376 dev_priv
->fbc
.enable_fbc(crtc
);
381 work
->fb
= crtc
->base
.primary
->fb
;
382 INIT_DELAYED_WORK(&work
->work
, intel_fbc_work_fn
);
384 dev_priv
->fbc
.fbc_work
= work
;
386 /* Delay the actual enabling to let pageflipping cease and the
387 * display to settle before starting the compression. Note that
388 * this delay also serves a second purpose: it allows for a
389 * vblank to pass after disabling the FBC before we attempt
390 * to modify the control registers.
392 * A more complicated solution would involve tracking vblanks
393 * following the termination of the page-flipping sequence
394 * and indeed performing the enable as a co-routine and not
395 * waiting synchronously upon the vblank.
397 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
399 schedule_delayed_work(&work
->work
, msecs_to_jiffies(50));
402 static void __intel_fbc_disable(struct drm_i915_private
*dev_priv
)
404 WARN_ON(!mutex_is_locked(&dev_priv
->fbc
.lock
));
406 intel_fbc_cancel_work(dev_priv
);
408 dev_priv
->fbc
.disable_fbc(dev_priv
);
409 dev_priv
->fbc
.crtc
= NULL
;
413 * intel_fbc_disable - disable FBC
414 * @dev_priv: i915 device instance
416 * This function disables FBC.
418 void intel_fbc_disable(struct drm_i915_private
*dev_priv
)
420 if (!dev_priv
->fbc
.enable_fbc
)
423 mutex_lock(&dev_priv
->fbc
.lock
);
424 __intel_fbc_disable(dev_priv
);
425 mutex_unlock(&dev_priv
->fbc
.lock
);
429 * intel_fbc_disable_crtc - disable FBC if it's associated with crtc
432 * This function disables FBC if it's associated with the provided CRTC.
434 void intel_fbc_disable_crtc(struct intel_crtc
*crtc
)
436 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
438 if (!dev_priv
->fbc
.enable_fbc
)
441 mutex_lock(&dev_priv
->fbc
.lock
);
442 if (dev_priv
->fbc
.crtc
== crtc
)
443 __intel_fbc_disable(dev_priv
);
444 mutex_unlock(&dev_priv
->fbc
.lock
);
447 const char *intel_no_fbc_reason_str(enum no_fbc_reason reason
)
451 return "FBC enabled but currently disabled in hardware";
452 case FBC_UNSUPPORTED
:
453 return "unsupported by this chipset";
456 case FBC_STOLEN_TOO_SMALL
:
457 return "not enough stolen memory";
458 case FBC_UNSUPPORTED_MODE
:
459 return "mode incompatible with compression";
460 case FBC_MODE_TOO_LARGE
:
461 return "mode too large for compression";
463 return "FBC unsupported on plane";
465 return "framebuffer not tiled or fenced";
466 case FBC_MULTIPLE_PIPES
:
467 return "more than one pipe active";
468 case FBC_MODULE_PARAM
:
469 return "disabled per module param";
470 case FBC_CHIP_DEFAULT
:
471 return "disabled per chip default";
473 return "rotation unsupported";
474 case FBC_IN_DBG_MASTER
:
475 return "Kernel debugger is active";
477 MISSING_CASE(reason
);
478 return "unknown reason";
482 static void set_no_fbc_reason(struct drm_i915_private
*dev_priv
,
483 enum no_fbc_reason reason
)
485 if (dev_priv
->fbc
.no_fbc_reason
== reason
)
488 dev_priv
->fbc
.no_fbc_reason
= reason
;
489 DRM_DEBUG_KMS("Disabling FBC: %s\n", intel_no_fbc_reason_str(reason
));
492 static struct drm_crtc
*intel_fbc_find_crtc(struct drm_i915_private
*dev_priv
)
494 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
496 bool pipe_a_only
= false;
498 if (IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8)
501 for_each_pipe(dev_priv
, pipe
) {
502 tmp_crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
504 if (intel_crtc_active(tmp_crtc
) &&
505 to_intel_plane_state(tmp_crtc
->primary
->state
)->visible
)
512 if (!crtc
|| crtc
->primary
->fb
== NULL
)
518 static bool multiple_pipes_ok(struct drm_i915_private
*dev_priv
)
522 struct drm_crtc
*crtc
;
524 if (INTEL_INFO(dev_priv
)->gen
> 4)
527 for_each_pipe(dev_priv
, pipe
) {
528 crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
530 if (intel_crtc_active(crtc
) &&
531 to_intel_plane_state(crtc
->primary
->state
)->visible
)
535 return (n_pipes
< 2);
538 static int find_compression_threshold(struct drm_i915_private
*dev_priv
,
539 struct drm_mm_node
*node
,
543 int compression_threshold
= 1;
546 /* HACK: This code depends on what we will do in *_enable_fbc. If that
547 * code changes, this code needs to change as well.
549 * The enable_fbc code will attempt to use one of our 2 compression
550 * thresholds, therefore, in that case, we only have 1 resort.
553 /* Try to over-allocate to reduce reallocations and fragmentation. */
554 ret
= i915_gem_stolen_insert_node(dev_priv
, node
, size
<<= 1, 4096);
556 return compression_threshold
;
559 /* HW's ability to limit the CFB is 1:4 */
560 if (compression_threshold
> 4 ||
561 (fb_cpp
== 2 && compression_threshold
== 2))
564 ret
= i915_gem_stolen_insert_node(dev_priv
, node
, size
>>= 1, 4096);
565 if (ret
&& INTEL_INFO(dev_priv
)->gen
<= 4) {
568 compression_threshold
<<= 1;
571 return compression_threshold
;
575 static int intel_fbc_alloc_cfb(struct drm_i915_private
*dev_priv
, int size
,
578 struct drm_mm_node
*uninitialized_var(compressed_llb
);
581 ret
= find_compression_threshold(dev_priv
, &dev_priv
->fbc
.compressed_fb
,
586 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
590 dev_priv
->fbc
.threshold
= ret
;
592 if (INTEL_INFO(dev_priv
)->gen
>= 5)
593 I915_WRITE(ILK_DPFC_CB_BASE
, dev_priv
->fbc
.compressed_fb
.start
);
594 else if (IS_GM45(dev_priv
)) {
595 I915_WRITE(DPFC_CB_BASE
, dev_priv
->fbc
.compressed_fb
.start
);
597 compressed_llb
= kzalloc(sizeof(*compressed_llb
), GFP_KERNEL
);
601 ret
= i915_gem_stolen_insert_node(dev_priv
, compressed_llb
,
606 dev_priv
->fbc
.compressed_llb
= compressed_llb
;
608 I915_WRITE(FBC_CFB_BASE
,
609 dev_priv
->mm
.stolen_base
+ dev_priv
->fbc
.compressed_fb
.start
);
610 I915_WRITE(FBC_LL_BASE
,
611 dev_priv
->mm
.stolen_base
+ compressed_llb
->start
);
614 dev_priv
->fbc
.uncompressed_size
= size
;
616 DRM_DEBUG_KMS("reserved %d bytes of contiguous stolen space for FBC\n",
622 kfree(compressed_llb
);
623 i915_gem_stolen_remove_node(dev_priv
, &dev_priv
->fbc
.compressed_fb
);
625 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size
);
629 static void __intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
)
631 if (dev_priv
->fbc
.uncompressed_size
== 0)
634 i915_gem_stolen_remove_node(dev_priv
, &dev_priv
->fbc
.compressed_fb
);
636 if (dev_priv
->fbc
.compressed_llb
) {
637 i915_gem_stolen_remove_node(dev_priv
,
638 dev_priv
->fbc
.compressed_llb
);
639 kfree(dev_priv
->fbc
.compressed_llb
);
642 dev_priv
->fbc
.uncompressed_size
= 0;
645 void intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
)
647 if (!dev_priv
->fbc
.enable_fbc
)
650 mutex_lock(&dev_priv
->fbc
.lock
);
651 __intel_fbc_cleanup_cfb(dev_priv
);
652 mutex_unlock(&dev_priv
->fbc
.lock
);
655 static int intel_fbc_setup_cfb(struct drm_i915_private
*dev_priv
, int size
,
658 if (size
<= dev_priv
->fbc
.uncompressed_size
)
661 /* Release any current block */
662 __intel_fbc_cleanup_cfb(dev_priv
);
664 return intel_fbc_alloc_cfb(dev_priv
, size
, fb_cpp
);
668 * __intel_fbc_update - enable/disable FBC as needed, unlocked
669 * @dev_priv: i915 device instance
671 * Set up the framebuffer compression hardware at mode set time. We
672 * enable it if possible:
673 * - plane A only (on pre-965)
674 * - no pixel mulitply/line duplication
675 * - no alpha buffer discard
677 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
679 * We can't assume that any compression will take place (worst case),
680 * so the compressed buffer has to be the same size as the uncompressed
681 * one. It also must reside (along with the line length buffer) in
684 * We need to enable/disable FBC on a global basis.
686 static void __intel_fbc_update(struct drm_i915_private
*dev_priv
)
688 struct drm_crtc
*crtc
= NULL
;
689 struct intel_crtc
*intel_crtc
;
690 struct drm_framebuffer
*fb
;
691 struct drm_i915_gem_object
*obj
;
692 const struct drm_display_mode
*adjusted_mode
;
693 unsigned int max_width
, max_height
;
695 WARN_ON(!mutex_is_locked(&dev_priv
->fbc
.lock
));
697 /* disable framebuffer compression in vGPU */
698 if (intel_vgpu_active(dev_priv
->dev
))
701 if (i915
.enable_fbc
< 0) {
702 set_no_fbc_reason(dev_priv
, FBC_CHIP_DEFAULT
);
706 if (!i915
.enable_fbc
) {
707 set_no_fbc_reason(dev_priv
, FBC_MODULE_PARAM
);
712 * If FBC is already on, we just have to verify that we can
713 * keep it that way...
714 * Need to disable if:
715 * - more than one pipe is active
716 * - changing FBC params (stride, fence, mode)
717 * - new fb is too large to fit in compressed buffer
718 * - going to an unsupported config (interlace, pixel multiply, etc.)
720 crtc
= intel_fbc_find_crtc(dev_priv
);
722 set_no_fbc_reason(dev_priv
, FBC_NO_OUTPUT
);
726 if (!multiple_pipes_ok(dev_priv
)) {
727 set_no_fbc_reason(dev_priv
, FBC_MULTIPLE_PIPES
);
731 intel_crtc
= to_intel_crtc(crtc
);
732 fb
= crtc
->primary
->fb
;
733 obj
= intel_fb_obj(fb
);
734 adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
736 if ((adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ||
737 (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)) {
738 set_no_fbc_reason(dev_priv
, FBC_UNSUPPORTED_MODE
);
742 if (INTEL_INFO(dev_priv
)->gen
>= 8 || IS_HASWELL(dev_priv
)) {
745 } else if (IS_G4X(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 5) {
752 if (intel_crtc
->config
->pipe_src_w
> max_width
||
753 intel_crtc
->config
->pipe_src_h
> max_height
) {
754 set_no_fbc_reason(dev_priv
, FBC_MODE_TOO_LARGE
);
757 if ((INTEL_INFO(dev_priv
)->gen
< 4 || HAS_DDI(dev_priv
)) &&
758 intel_crtc
->plane
!= PLANE_A
) {
759 set_no_fbc_reason(dev_priv
, FBC_BAD_PLANE
);
763 /* The use of a CPU fence is mandatory in order to detect writes
764 * by the CPU to the scanout and trigger updates to the FBC.
766 if (obj
->tiling_mode
!= I915_TILING_X
||
767 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
768 set_no_fbc_reason(dev_priv
, FBC_NOT_TILED
);
771 if (INTEL_INFO(dev_priv
)->gen
<= 4 && !IS_G4X(dev_priv
) &&
772 crtc
->primary
->state
->rotation
!= BIT(DRM_ROTATE_0
)) {
773 set_no_fbc_reason(dev_priv
, FBC_ROTATION
);
777 /* If the kernel debugger is active, always disable compression */
778 if (in_dbg_master()) {
779 set_no_fbc_reason(dev_priv
, FBC_IN_DBG_MASTER
);
783 if (intel_fbc_setup_cfb(dev_priv
, obj
->base
.size
,
784 drm_format_plane_cpp(fb
->pixel_format
, 0))) {
785 set_no_fbc_reason(dev_priv
, FBC_STOLEN_TOO_SMALL
);
789 /* If the scanout has not changed, don't modify the FBC settings.
790 * Note that we make the fundamental assumption that the fb->obj
791 * cannot be unpinned (and have its GTT offset and fence revoked)
792 * without first being decoupled from the scanout and FBC disabled.
794 if (dev_priv
->fbc
.crtc
== intel_crtc
&&
795 dev_priv
->fbc
.fb_id
== fb
->base
.id
&&
796 dev_priv
->fbc
.y
== crtc
->y
)
799 if (intel_fbc_enabled(dev_priv
)) {
800 /* We update FBC along two paths, after changing fb/crtc
801 * configuration (modeswitching) and after page-flipping
802 * finishes. For the latter, we know that not only did
803 * we disable the FBC at the start of the page-flip
804 * sequence, but also more than one vblank has passed.
806 * For the former case of modeswitching, it is possible
807 * to switch between two FBC valid configurations
808 * instantaneously so we do need to disable the FBC
809 * before we can modify its control registers. We also
810 * have to wait for the next vblank for that to take
811 * effect. However, since we delay enabling FBC we can
812 * assume that a vblank has passed since disabling and
813 * that we can safely alter the registers in the deferred
816 * In the scenario that we go from a valid to invalid
817 * and then back to valid FBC configuration we have
818 * no strict enforcement that a vblank occurred since
819 * disabling the FBC. However, along all current pipe
820 * disabling paths we do need to wait for a vblank at
821 * some point. And we wait before enabling FBC anyway.
823 DRM_DEBUG_KMS("disabling active FBC for update\n");
824 __intel_fbc_disable(dev_priv
);
827 intel_fbc_enable(intel_crtc
);
828 dev_priv
->fbc
.no_fbc_reason
= FBC_OK
;
832 /* Multiple disables should be harmless */
833 if (intel_fbc_enabled(dev_priv
)) {
834 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
835 __intel_fbc_disable(dev_priv
);
837 __intel_fbc_cleanup_cfb(dev_priv
);
841 * intel_fbc_update - enable/disable FBC as needed
842 * @dev_priv: i915 device instance
844 * This function reevaluates the overall state and enables or disables FBC.
846 void intel_fbc_update(struct drm_i915_private
*dev_priv
)
848 if (!dev_priv
->fbc
.enable_fbc
)
851 mutex_lock(&dev_priv
->fbc
.lock
);
852 __intel_fbc_update(dev_priv
);
853 mutex_unlock(&dev_priv
->fbc
.lock
);
856 void intel_fbc_invalidate(struct drm_i915_private
*dev_priv
,
857 unsigned int frontbuffer_bits
,
858 enum fb_op_origin origin
)
860 unsigned int fbc_bits
;
862 if (!dev_priv
->fbc
.enable_fbc
)
865 if (origin
== ORIGIN_GTT
)
868 mutex_lock(&dev_priv
->fbc
.lock
);
870 if (dev_priv
->fbc
.enabled
)
871 fbc_bits
= INTEL_FRONTBUFFER_PRIMARY(dev_priv
->fbc
.crtc
->pipe
);
872 else if (dev_priv
->fbc
.fbc_work
)
873 fbc_bits
= INTEL_FRONTBUFFER_PRIMARY(
874 dev_priv
->fbc
.fbc_work
->crtc
->pipe
);
876 fbc_bits
= dev_priv
->fbc
.possible_framebuffer_bits
;
878 dev_priv
->fbc
.busy_bits
|= (fbc_bits
& frontbuffer_bits
);
880 if (dev_priv
->fbc
.busy_bits
)
881 __intel_fbc_disable(dev_priv
);
883 mutex_unlock(&dev_priv
->fbc
.lock
);
886 void intel_fbc_flush(struct drm_i915_private
*dev_priv
,
887 unsigned int frontbuffer_bits
, enum fb_op_origin origin
)
889 if (!dev_priv
->fbc
.enable_fbc
)
892 if (origin
== ORIGIN_GTT
)
895 mutex_lock(&dev_priv
->fbc
.lock
);
897 dev_priv
->fbc
.busy_bits
&= ~frontbuffer_bits
;
899 if (!dev_priv
->fbc
.busy_bits
) {
900 __intel_fbc_disable(dev_priv
);
901 __intel_fbc_update(dev_priv
);
904 mutex_unlock(&dev_priv
->fbc
.lock
);
908 * intel_fbc_init - Initialize FBC
909 * @dev_priv: the i915 device
911 * This function might be called during PM init process.
913 void intel_fbc_init(struct drm_i915_private
*dev_priv
)
917 mutex_init(&dev_priv
->fbc
.lock
);
919 if (!HAS_FBC(dev_priv
)) {
920 dev_priv
->fbc
.enabled
= false;
921 dev_priv
->fbc
.no_fbc_reason
= FBC_UNSUPPORTED
;
925 for_each_pipe(dev_priv
, pipe
) {
926 dev_priv
->fbc
.possible_framebuffer_bits
|=
927 INTEL_FRONTBUFFER_PRIMARY(pipe
);
929 if (IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8)
933 if (INTEL_INFO(dev_priv
)->gen
>= 7) {
934 dev_priv
->fbc
.fbc_enabled
= ilk_fbc_enabled
;
935 dev_priv
->fbc
.enable_fbc
= gen7_fbc_enable
;
936 dev_priv
->fbc
.disable_fbc
= ilk_fbc_disable
;
937 } else if (INTEL_INFO(dev_priv
)->gen
>= 5) {
938 dev_priv
->fbc
.fbc_enabled
= ilk_fbc_enabled
;
939 dev_priv
->fbc
.enable_fbc
= ilk_fbc_enable
;
940 dev_priv
->fbc
.disable_fbc
= ilk_fbc_disable
;
941 } else if (IS_GM45(dev_priv
)) {
942 dev_priv
->fbc
.fbc_enabled
= g4x_fbc_enabled
;
943 dev_priv
->fbc
.enable_fbc
= g4x_fbc_enable
;
944 dev_priv
->fbc
.disable_fbc
= g4x_fbc_disable
;
946 dev_priv
->fbc
.fbc_enabled
= i8xx_fbc_enabled
;
947 dev_priv
->fbc
.enable_fbc
= i8xx_fbc_enable
;
948 dev_priv
->fbc
.disable_fbc
= i8xx_fbc_disable
;
950 /* This value was pulled out of someone's hat */
951 I915_WRITE(FBC_CONTROL
, 500 << FBC_CTL_INTERVAL_SHIFT
);
954 dev_priv
->fbc
.enabled
= dev_priv
->fbc
.fbc_enabled(dev_priv
);