2 * Copyright © 2014 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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27 #include "intel_guc_fwif.h"
28 #include "i915_guc_reg.h"
29 #include "intel_ringbuffer.h"
31 struct drm_i915_gem_request
;
34 * This structure primarily describes the GEM object shared with the GuC.
35 * The GEM object is held for the entire lifetime of our interaction with
36 * the GuC, being allocated before the GuC is loaded with its firmware.
37 * Because there's no way to update the address used by the GuC after
38 * initialisation, the shared object must stay pinned into the GGTT as
39 * long as the GuC is in use. We also keep the first page (only) mapped
40 * into kernel address space, as it includes shared data that must be
41 * updated on every request submission.
43 * The single GEM object described here is actually made up of several
44 * separate areas, as far as the GuC is concerned. The first page (kept
45 * kmap'd) includes the "process decriptor" which holds sequence data for
46 * the doorbell, and one cacheline which actually *is* the doorbell; a
47 * write to this will "ring the doorbell" (i.e. send an interrupt to the
48 * GuC). The subsequent pages of the client object constitute the work
49 * queue (a circular array of work items), again described in the process
50 * descriptor. Work queue pages are mapped momentarily as required.
52 * We also keep a few statistics on failures. Ideally, these should all
54 * no_wq_space: times that the submission pre-check found no space was
55 * available in the work queue (note, the queue is shared,
56 * not per-engine). It is OK for this to be nonzero, but
57 * it should not be huge!
58 * q_fail: failed to enqueue a work item. This should never happen,
59 * because we check for space beforehand.
60 * b_fail: failed to ring the doorbell. This should never happen, unless
61 * somehow the hardware misbehaves, or maybe if the GuC firmware
62 * crashes? We probably need to reset the GPU to recover.
63 * retcode: errno from last guc_submit()
65 struct i915_guc_client
{
66 struct drm_i915_gem_object
*client_obj
;
67 void *client_base
; /* first page (only) of above */
68 struct i915_gem_context
*owner
;
69 struct intel_guc
*guc
;
73 uint32_t proc_desc_offset
;
74 uint32_t doorbell_offset
;
77 uint16_t padding
; /* Maintain alignment */
82 uint32_t unused
; /* Was 'wq_head' */
85 uint32_t q_fail
; /* No longer used */
89 /* Per-engine counts of GuC submissions */
90 uint64_t submissions
[I915_NUM_ENGINES
];
93 enum intel_guc_fw_status
{
94 GUC_FIRMWARE_FAIL
= -1,
95 GUC_FIRMWARE_NONE
= 0,
101 * This structure encapsulates all the data needed during the process
102 * of fetching, caching, and loading the firmware image into the GuC.
104 struct intel_guc_fw
{
105 struct drm_device
* guc_dev
;
106 const char * guc_fw_path
;
108 struct drm_i915_gem_object
* guc_fw_obj
;
109 enum intel_guc_fw_status guc_fw_fetch_status
;
110 enum intel_guc_fw_status guc_fw_load_status
;
112 uint16_t guc_fw_major_wanted
;
113 uint16_t guc_fw_minor_wanted
;
114 uint16_t guc_fw_major_found
;
115 uint16_t guc_fw_minor_found
;
117 uint32_t header_size
;
118 uint32_t header_offset
;
122 uint32_t ucode_offset
;
126 struct intel_guc_fw guc_fw
;
128 struct drm_i915_gem_object
*log_obj
;
130 struct drm_i915_gem_object
*ads_obj
;
132 struct drm_i915_gem_object
*ctx_pool_obj
;
135 struct i915_guc_client
*execbuf_client
;
137 DECLARE_BITMAP(doorbell_bitmap
, GUC_MAX_DOORBELLS
);
138 uint32_t db_cacheline
; /* Cyclic counter mod pagesize */
140 /* Action status & statistics */
141 uint64_t action_count
; /* Total commands issued */
142 uint32_t action_cmd
; /* Last command word */
143 uint32_t action_status
; /* Last return status */
144 uint32_t action_fail
; /* Total number of failures */
145 int32_t action_err
; /* Last error code */
147 uint64_t submissions
[I915_NUM_ENGINES
];
148 uint32_t last_seqno
[I915_NUM_ENGINES
];
151 /* intel_guc_loader.c */
152 extern void intel_guc_init(struct drm_device
*dev
);
153 extern int intel_guc_setup(struct drm_device
*dev
);
154 extern void intel_guc_fini(struct drm_device
*dev
);
155 extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status
);
156 extern int intel_guc_suspend(struct drm_device
*dev
);
157 extern int intel_guc_resume(struct drm_device
*dev
);
159 /* i915_guc_submission.c */
160 int i915_guc_submission_init(struct drm_i915_private
*dev_priv
);
161 int i915_guc_submission_enable(struct drm_i915_private
*dev_priv
);
162 int i915_guc_wq_check_space(struct drm_i915_gem_request
*rq
);
163 void i915_guc_submission_disable(struct drm_i915_private
*dev_priv
);
164 void i915_guc_submission_fini(struct drm_i915_private
*dev_priv
);