2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
40 static struct drm_device
*intel_hdmi_to_dev(struct intel_hdmi
*intel_hdmi
)
42 return hdmi_to_dig_port(intel_hdmi
)->base
.base
.dev
;
46 assert_hdmi_port_disabled(struct intel_hdmi
*intel_hdmi
)
48 struct drm_device
*dev
= intel_hdmi_to_dev(intel_hdmi
);
49 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
50 uint32_t enabled_bits
;
52 enabled_bits
= HAS_DDI(dev
) ? DDI_BUF_CTL_ENABLE
: SDVO_ENABLE
;
54 WARN(I915_READ(intel_hdmi
->hdmi_reg
) & enabled_bits
,
55 "HDMI port enabled, expecting disabled\n");
58 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
)
60 struct intel_digital_port
*intel_dig_port
=
61 container_of(encoder
, struct intel_digital_port
, base
.base
);
62 return &intel_dig_port
->hdmi
;
65 static struct intel_hdmi
*intel_attached_hdmi(struct drm_connector
*connector
)
67 return enc_to_intel_hdmi(&intel_attached_encoder(connector
)->base
);
70 static u32
g4x_infoframe_index(enum hdmi_infoframe_type type
)
73 case HDMI_INFOFRAME_TYPE_AVI
:
74 return VIDEO_DIP_SELECT_AVI
;
75 case HDMI_INFOFRAME_TYPE_SPD
:
76 return VIDEO_DIP_SELECT_SPD
;
77 case HDMI_INFOFRAME_TYPE_VENDOR
:
78 return VIDEO_DIP_SELECT_VENDOR
;
80 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type
);
85 static u32
g4x_infoframe_enable(enum hdmi_infoframe_type type
)
88 case HDMI_INFOFRAME_TYPE_AVI
:
89 return VIDEO_DIP_ENABLE_AVI
;
90 case HDMI_INFOFRAME_TYPE_SPD
:
91 return VIDEO_DIP_ENABLE_SPD
;
92 case HDMI_INFOFRAME_TYPE_VENDOR
:
93 return VIDEO_DIP_ENABLE_VENDOR
;
95 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type
);
100 static u32
hsw_infoframe_enable(enum hdmi_infoframe_type type
)
103 case HDMI_INFOFRAME_TYPE_AVI
:
104 return VIDEO_DIP_ENABLE_AVI_HSW
;
105 case HDMI_INFOFRAME_TYPE_SPD
:
106 return VIDEO_DIP_ENABLE_SPD_HSW
;
107 case HDMI_INFOFRAME_TYPE_VENDOR
:
108 return VIDEO_DIP_ENABLE_VS_HSW
;
110 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type
);
115 static u32
hsw_infoframe_data_reg(enum hdmi_infoframe_type type
,
116 enum transcoder cpu_transcoder
,
117 struct drm_i915_private
*dev_priv
)
120 case HDMI_INFOFRAME_TYPE_AVI
:
121 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder
);
122 case HDMI_INFOFRAME_TYPE_SPD
:
123 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder
);
124 case HDMI_INFOFRAME_TYPE_VENDOR
:
125 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder
);
127 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type
);
132 static void g4x_write_infoframe(struct drm_encoder
*encoder
,
133 enum hdmi_infoframe_type type
,
134 const void *frame
, ssize_t len
)
136 const uint32_t *data
= frame
;
137 struct drm_device
*dev
= encoder
->dev
;
138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
139 u32 val
= I915_READ(VIDEO_DIP_CTL
);
142 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
144 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
145 val
|= g4x_infoframe_index(type
);
147 val
&= ~g4x_infoframe_enable(type
);
149 I915_WRITE(VIDEO_DIP_CTL
, val
);
152 for (i
= 0; i
< len
; i
+= 4) {
153 I915_WRITE(VIDEO_DIP_DATA
, *data
);
156 /* Write every possible data byte to force correct ECC calculation. */
157 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
158 I915_WRITE(VIDEO_DIP_DATA
, 0);
161 val
|= g4x_infoframe_enable(type
);
162 val
&= ~VIDEO_DIP_FREQ_MASK
;
163 val
|= VIDEO_DIP_FREQ_VSYNC
;
165 I915_WRITE(VIDEO_DIP_CTL
, val
);
166 POSTING_READ(VIDEO_DIP_CTL
);
169 static void ibx_write_infoframe(struct drm_encoder
*encoder
,
170 enum hdmi_infoframe_type type
,
171 const void *frame
, ssize_t len
)
173 const uint32_t *data
= frame
;
174 struct drm_device
*dev
= encoder
->dev
;
175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
176 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
177 int i
, reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
178 u32 val
= I915_READ(reg
);
180 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
182 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
183 val
|= g4x_infoframe_index(type
);
185 val
&= ~g4x_infoframe_enable(type
);
187 I915_WRITE(reg
, val
);
190 for (i
= 0; i
< len
; i
+= 4) {
191 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
194 /* Write every possible data byte to force correct ECC calculation. */
195 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
196 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
199 val
|= g4x_infoframe_enable(type
);
200 val
&= ~VIDEO_DIP_FREQ_MASK
;
201 val
|= VIDEO_DIP_FREQ_VSYNC
;
203 I915_WRITE(reg
, val
);
207 static void cpt_write_infoframe(struct drm_encoder
*encoder
,
208 enum hdmi_infoframe_type type
,
209 const void *frame
, ssize_t len
)
211 const uint32_t *data
= frame
;
212 struct drm_device
*dev
= encoder
->dev
;
213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
214 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
215 int i
, reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
216 u32 val
= I915_READ(reg
);
218 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
220 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
221 val
|= g4x_infoframe_index(type
);
223 /* The DIP control register spec says that we need to update the AVI
224 * infoframe without clearing its enable bit */
225 if (type
!= HDMI_INFOFRAME_TYPE_AVI
)
226 val
&= ~g4x_infoframe_enable(type
);
228 I915_WRITE(reg
, val
);
231 for (i
= 0; i
< len
; i
+= 4) {
232 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
235 /* Write every possible data byte to force correct ECC calculation. */
236 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
237 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
240 val
|= g4x_infoframe_enable(type
);
241 val
&= ~VIDEO_DIP_FREQ_MASK
;
242 val
|= VIDEO_DIP_FREQ_VSYNC
;
244 I915_WRITE(reg
, val
);
248 static void vlv_write_infoframe(struct drm_encoder
*encoder
,
249 enum hdmi_infoframe_type type
,
250 const void *frame
, ssize_t len
)
252 const uint32_t *data
= frame
;
253 struct drm_device
*dev
= encoder
->dev
;
254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
255 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
256 int i
, reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
257 u32 val
= I915_READ(reg
);
259 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
261 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
262 val
|= g4x_infoframe_index(type
);
264 val
&= ~g4x_infoframe_enable(type
);
266 I915_WRITE(reg
, val
);
269 for (i
= 0; i
< len
; i
+= 4) {
270 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
273 /* Write every possible data byte to force correct ECC calculation. */
274 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
275 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
278 val
|= g4x_infoframe_enable(type
);
279 val
&= ~VIDEO_DIP_FREQ_MASK
;
280 val
|= VIDEO_DIP_FREQ_VSYNC
;
282 I915_WRITE(reg
, val
);
286 static void hsw_write_infoframe(struct drm_encoder
*encoder
,
287 enum hdmi_infoframe_type type
,
288 const void *frame
, ssize_t len
)
290 const uint32_t *data
= frame
;
291 struct drm_device
*dev
= encoder
->dev
;
292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
293 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
294 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(intel_crtc
->config
.cpu_transcoder
);
297 u32 val
= I915_READ(ctl_reg
);
299 data_reg
= hsw_infoframe_data_reg(type
,
300 intel_crtc
->config
.cpu_transcoder
,
305 val
&= ~hsw_infoframe_enable(type
);
306 I915_WRITE(ctl_reg
, val
);
309 for (i
= 0; i
< len
; i
+= 4) {
310 I915_WRITE(data_reg
+ i
, *data
);
313 /* Write every possible data byte to force correct ECC calculation. */
314 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
315 I915_WRITE(data_reg
+ i
, 0);
318 val
|= hsw_infoframe_enable(type
);
319 I915_WRITE(ctl_reg
, val
);
320 POSTING_READ(ctl_reg
);
324 * The data we write to the DIP data buffer registers is 1 byte bigger than the
325 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
326 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
327 * used for both technologies.
329 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
330 * DW1: DB3 | DB2 | DB1 | DB0
331 * DW2: DB7 | DB6 | DB5 | DB4
334 * (HB is Header Byte, DB is Data Byte)
336 * The hdmi pack() functions don't know about that hardware specific hole so we
337 * trick them by giving an offset into the buffer and moving back the header
340 static void intel_write_infoframe(struct drm_encoder
*encoder
,
341 union hdmi_infoframe
*frame
)
343 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
344 uint8_t buffer
[VIDEO_DIP_DATA_SIZE
];
347 /* see comment above for the reason for this offset */
348 len
= hdmi_infoframe_pack(frame
, buffer
+ 1, sizeof(buffer
) - 1);
352 /* Insert the 'hole' (see big comment above) at position 3 */
353 buffer
[0] = buffer
[1];
354 buffer
[1] = buffer
[2];
355 buffer
[2] = buffer
[3];
359 intel_hdmi
->write_infoframe(encoder
, frame
->any
.type
, buffer
, len
);
362 static void intel_hdmi_set_avi_infoframe(struct drm_encoder
*encoder
,
363 struct drm_display_mode
*adjusted_mode
)
365 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
366 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
367 union hdmi_infoframe frame
;
370 /* Set user selected PAR to incoming mode's member */
371 adjusted_mode
->picture_aspect_ratio
= intel_hdmi
->aspect_ratio
;
373 ret
= drm_hdmi_avi_infoframe_from_display_mode(&frame
.avi
,
376 DRM_ERROR("couldn't fill AVI infoframe\n");
380 if (intel_hdmi
->rgb_quant_range_selectable
) {
381 if (intel_crtc
->config
.limited_color_range
)
382 frame
.avi
.quantization_range
=
383 HDMI_QUANTIZATION_RANGE_LIMITED
;
385 frame
.avi
.quantization_range
=
386 HDMI_QUANTIZATION_RANGE_FULL
;
389 intel_write_infoframe(encoder
, &frame
);
392 static void intel_hdmi_set_spd_infoframe(struct drm_encoder
*encoder
)
394 union hdmi_infoframe frame
;
397 ret
= hdmi_spd_infoframe_init(&frame
.spd
, "Intel", "Integrated gfx");
399 DRM_ERROR("couldn't fill SPD infoframe\n");
403 frame
.spd
.sdi
= HDMI_SPD_SDI_PC
;
405 intel_write_infoframe(encoder
, &frame
);
409 intel_hdmi_set_hdmi_infoframe(struct drm_encoder
*encoder
,
410 struct drm_display_mode
*adjusted_mode
)
412 union hdmi_infoframe frame
;
415 ret
= drm_hdmi_vendor_infoframe_from_display_mode(&frame
.vendor
.hdmi
,
420 intel_write_infoframe(encoder
, &frame
);
423 static void g4x_set_infoframes(struct drm_encoder
*encoder
,
425 struct drm_display_mode
*adjusted_mode
)
427 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
428 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
429 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
430 u32 reg
= VIDEO_DIP_CTL
;
431 u32 val
= I915_READ(reg
);
432 u32 port
= VIDEO_DIP_PORT(intel_dig_port
->port
);
434 assert_hdmi_port_disabled(intel_hdmi
);
436 /* If the registers were not initialized yet, they might be zeroes,
437 * which means we're selecting the AVI DIP and we're setting its
438 * frequency to once. This seems to really confuse the HW and make
439 * things stop working (the register spec says the AVI always needs to
440 * be sent every VSync). So here we avoid writing to the register more
441 * than we need and also explicitly select the AVI DIP and explicitly
442 * set its frequency to every VSync. Avoiding to write it twice seems to
443 * be enough to solve the problem, but being defensive shouldn't hurt us
445 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
448 if (!(val
& VIDEO_DIP_ENABLE
))
450 val
&= ~VIDEO_DIP_ENABLE
;
451 I915_WRITE(reg
, val
);
456 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
457 if (val
& VIDEO_DIP_ENABLE
) {
458 val
&= ~VIDEO_DIP_ENABLE
;
459 I915_WRITE(reg
, val
);
462 val
&= ~VIDEO_DIP_PORT_MASK
;
466 val
|= VIDEO_DIP_ENABLE
;
467 val
&= ~VIDEO_DIP_ENABLE_VENDOR
;
469 I915_WRITE(reg
, val
);
472 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
473 intel_hdmi_set_spd_infoframe(encoder
);
474 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
477 static void ibx_set_infoframes(struct drm_encoder
*encoder
,
479 struct drm_display_mode
*adjusted_mode
)
481 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
482 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
483 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
484 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
485 u32 reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
486 u32 val
= I915_READ(reg
);
487 u32 port
= VIDEO_DIP_PORT(intel_dig_port
->port
);
489 assert_hdmi_port_disabled(intel_hdmi
);
491 /* See the big comment in g4x_set_infoframes() */
492 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
495 if (!(val
& VIDEO_DIP_ENABLE
))
497 val
&= ~VIDEO_DIP_ENABLE
;
498 I915_WRITE(reg
, val
);
503 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
504 if (val
& VIDEO_DIP_ENABLE
) {
505 val
&= ~VIDEO_DIP_ENABLE
;
506 I915_WRITE(reg
, val
);
509 val
&= ~VIDEO_DIP_PORT_MASK
;
513 val
|= VIDEO_DIP_ENABLE
;
514 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
515 VIDEO_DIP_ENABLE_GCP
);
517 I915_WRITE(reg
, val
);
520 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
521 intel_hdmi_set_spd_infoframe(encoder
);
522 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
525 static void cpt_set_infoframes(struct drm_encoder
*encoder
,
527 struct drm_display_mode
*adjusted_mode
)
529 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
530 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
531 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
532 u32 reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
533 u32 val
= I915_READ(reg
);
535 assert_hdmi_port_disabled(intel_hdmi
);
537 /* See the big comment in g4x_set_infoframes() */
538 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
541 if (!(val
& VIDEO_DIP_ENABLE
))
543 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
);
544 I915_WRITE(reg
, val
);
549 /* Set both together, unset both together: see the spec. */
550 val
|= VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
;
551 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
552 VIDEO_DIP_ENABLE_GCP
);
554 I915_WRITE(reg
, val
);
557 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
558 intel_hdmi_set_spd_infoframe(encoder
);
559 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
562 static void vlv_set_infoframes(struct drm_encoder
*encoder
,
564 struct drm_display_mode
*adjusted_mode
)
566 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
567 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
568 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
569 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
570 u32 reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
571 u32 val
= I915_READ(reg
);
572 u32 port
= VIDEO_DIP_PORT(intel_dig_port
->port
);
574 assert_hdmi_port_disabled(intel_hdmi
);
576 /* See the big comment in g4x_set_infoframes() */
577 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
580 if (!(val
& VIDEO_DIP_ENABLE
))
582 val
&= ~VIDEO_DIP_ENABLE
;
583 I915_WRITE(reg
, val
);
588 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
589 if (val
& VIDEO_DIP_ENABLE
) {
590 val
&= ~VIDEO_DIP_ENABLE
;
591 I915_WRITE(reg
, val
);
594 val
&= ~VIDEO_DIP_PORT_MASK
;
598 val
|= VIDEO_DIP_ENABLE
;
599 val
&= ~(VIDEO_DIP_ENABLE_AVI
| VIDEO_DIP_ENABLE_VENDOR
|
600 VIDEO_DIP_ENABLE_GAMUT
| VIDEO_DIP_ENABLE_GCP
);
602 I915_WRITE(reg
, val
);
605 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
606 intel_hdmi_set_spd_infoframe(encoder
);
607 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
610 static void hsw_set_infoframes(struct drm_encoder
*encoder
,
612 struct drm_display_mode
*adjusted_mode
)
614 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
615 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
616 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
617 u32 reg
= HSW_TVIDEO_DIP_CTL(intel_crtc
->config
.cpu_transcoder
);
618 u32 val
= I915_READ(reg
);
620 assert_hdmi_port_disabled(intel_hdmi
);
628 val
&= ~(VIDEO_DIP_ENABLE_VSC_HSW
| VIDEO_DIP_ENABLE_GCP_HSW
|
629 VIDEO_DIP_ENABLE_VS_HSW
| VIDEO_DIP_ENABLE_GMP_HSW
);
631 I915_WRITE(reg
, val
);
634 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
635 intel_hdmi_set_spd_infoframe(encoder
);
636 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
639 static void intel_hdmi_prepare(struct intel_encoder
*encoder
)
641 struct drm_device
*dev
= encoder
->base
.dev
;
642 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
643 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
644 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
645 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
648 hdmi_val
= SDVO_ENCODING_HDMI
;
649 if (!HAS_PCH_SPLIT(dev
))
650 hdmi_val
|= intel_hdmi
->color_range
;
651 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
652 hdmi_val
|= SDVO_VSYNC_ACTIVE_HIGH
;
653 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
654 hdmi_val
|= SDVO_HSYNC_ACTIVE_HIGH
;
656 if (crtc
->config
.pipe_bpp
> 24)
657 hdmi_val
|= HDMI_COLOR_FORMAT_12bpc
;
659 hdmi_val
|= SDVO_COLOR_FORMAT_8bpc
;
661 if (crtc
->config
.has_hdmi_sink
)
662 hdmi_val
|= HDMI_MODE_SELECT_HDMI
;
664 if (crtc
->config
.has_audio
) {
665 WARN_ON(!crtc
->config
.has_hdmi_sink
);
666 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
667 pipe_name(crtc
->pipe
));
668 hdmi_val
|= SDVO_AUDIO_ENABLE
;
669 intel_write_eld(&encoder
->base
, adjusted_mode
);
672 if (HAS_PCH_CPT(dev
))
673 hdmi_val
|= SDVO_PIPE_SEL_CPT(crtc
->pipe
);
674 else if (IS_CHERRYVIEW(dev
))
675 hdmi_val
|= SDVO_PIPE_SEL_CHV(crtc
->pipe
);
677 hdmi_val
|= SDVO_PIPE_SEL(crtc
->pipe
);
679 I915_WRITE(intel_hdmi
->hdmi_reg
, hdmi_val
);
680 POSTING_READ(intel_hdmi
->hdmi_reg
);
683 static bool intel_hdmi_get_hw_state(struct intel_encoder
*encoder
,
686 struct drm_device
*dev
= encoder
->base
.dev
;
687 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
688 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
689 enum intel_display_power_domain power_domain
;
692 power_domain
= intel_display_port_power_domain(encoder
);
693 if (!intel_display_power_enabled(dev_priv
, power_domain
))
696 tmp
= I915_READ(intel_hdmi
->hdmi_reg
);
698 if (!(tmp
& SDVO_ENABLE
))
701 if (HAS_PCH_CPT(dev
))
702 *pipe
= PORT_TO_PIPE_CPT(tmp
);
703 else if (IS_CHERRYVIEW(dev
))
704 *pipe
= SDVO_PORT_TO_PIPE_CHV(tmp
);
706 *pipe
= PORT_TO_PIPE(tmp
);
711 static void intel_hdmi_get_config(struct intel_encoder
*encoder
,
712 struct intel_crtc_config
*pipe_config
)
714 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
715 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
719 tmp
= I915_READ(intel_hdmi
->hdmi_reg
);
721 if (tmp
& SDVO_HSYNC_ACTIVE_HIGH
)
722 flags
|= DRM_MODE_FLAG_PHSYNC
;
724 flags
|= DRM_MODE_FLAG_NHSYNC
;
726 if (tmp
& SDVO_VSYNC_ACTIVE_HIGH
)
727 flags
|= DRM_MODE_FLAG_PVSYNC
;
729 flags
|= DRM_MODE_FLAG_NVSYNC
;
731 if (tmp
& HDMI_MODE_SELECT_HDMI
)
732 pipe_config
->has_hdmi_sink
= true;
734 if (tmp
& HDMI_MODE_SELECT_HDMI
)
735 pipe_config
->has_audio
= true;
737 pipe_config
->adjusted_mode
.flags
|= flags
;
739 if ((tmp
& SDVO_COLOR_FORMAT_MASK
) == HDMI_COLOR_FORMAT_12bpc
)
740 dotclock
= pipe_config
->port_clock
* 2 / 3;
742 dotclock
= pipe_config
->port_clock
;
744 if (HAS_PCH_SPLIT(dev_priv
->dev
))
745 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
747 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
750 static void intel_enable_hdmi(struct intel_encoder
*encoder
)
752 struct drm_device
*dev
= encoder
->base
.dev
;
753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
754 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
755 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
757 u32 enable_bits
= SDVO_ENABLE
;
759 if (intel_crtc
->config
.has_audio
)
760 enable_bits
|= SDVO_AUDIO_ENABLE
;
762 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
764 /* HW workaround for IBX, we need to move the port to transcoder A
765 * before disabling it, so restore the transcoder select bit here. */
766 if (HAS_PCH_IBX(dev
))
767 enable_bits
|= SDVO_PIPE_SEL(intel_crtc
->pipe
);
769 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
770 * we do this anyway which shows more stable in testing.
772 if (HAS_PCH_SPLIT(dev
)) {
773 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
& ~SDVO_ENABLE
);
774 POSTING_READ(intel_hdmi
->hdmi_reg
);
779 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
780 POSTING_READ(intel_hdmi
->hdmi_reg
);
782 /* HW workaround, need to write this twice for issue that may result
783 * in first write getting masked.
785 if (HAS_PCH_SPLIT(dev
)) {
786 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
787 POSTING_READ(intel_hdmi
->hdmi_reg
);
791 static void vlv_enable_hdmi(struct intel_encoder
*encoder
)
795 static void intel_disable_hdmi(struct intel_encoder
*encoder
)
797 struct drm_device
*dev
= encoder
->base
.dev
;
798 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
799 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
801 u32 enable_bits
= SDVO_ENABLE
| SDVO_AUDIO_ENABLE
;
803 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
805 /* HW workaround for IBX, we need to move the port to transcoder A
806 * before disabling it. */
807 if (HAS_PCH_IBX(dev
)) {
808 struct drm_crtc
*crtc
= encoder
->base
.crtc
;
809 int pipe
= crtc
? to_intel_crtc(crtc
)->pipe
: -1;
811 if (temp
& SDVO_PIPE_B_SELECT
) {
812 temp
&= ~SDVO_PIPE_B_SELECT
;
813 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
814 POSTING_READ(intel_hdmi
->hdmi_reg
);
816 /* Again we need to write this twice. */
817 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
818 POSTING_READ(intel_hdmi
->hdmi_reg
);
820 /* Transcoder selection bits only update
821 * effectively on vblank. */
823 intel_wait_for_vblank(dev
, pipe
);
829 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
830 * we do this anyway which shows more stable in testing.
832 if (HAS_PCH_SPLIT(dev
)) {
833 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
& ~SDVO_ENABLE
);
834 POSTING_READ(intel_hdmi
->hdmi_reg
);
837 temp
&= ~enable_bits
;
839 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
840 POSTING_READ(intel_hdmi
->hdmi_reg
);
842 /* HW workaround, need to write this twice for issue that may result
843 * in first write getting masked.
845 if (HAS_PCH_SPLIT(dev
)) {
846 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
847 POSTING_READ(intel_hdmi
->hdmi_reg
);
851 static int hdmi_portclock_limit(struct intel_hdmi
*hdmi
, bool respect_dvi_limit
)
853 struct drm_device
*dev
= intel_hdmi_to_dev(hdmi
);
855 if ((respect_dvi_limit
&& !hdmi
->has_hdmi_sink
) || IS_G4X(dev
))
857 else if (IS_HASWELL(dev
) || INTEL_INFO(dev
)->gen
>= 8)
863 static enum drm_mode_status
864 intel_hdmi_mode_valid(struct drm_connector
*connector
,
865 struct drm_display_mode
*mode
)
867 if (mode
->clock
> hdmi_portclock_limit(intel_attached_hdmi(connector
),
869 return MODE_CLOCK_HIGH
;
870 if (mode
->clock
< 20000)
871 return MODE_CLOCK_LOW
;
873 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
874 return MODE_NO_DBLESCAN
;
879 static bool hdmi_12bpc_possible(struct intel_crtc
*crtc
)
881 struct drm_device
*dev
= crtc
->base
.dev
;
882 struct intel_encoder
*encoder
;
883 int count
= 0, count_hdmi
= 0;
885 if (!HAS_PCH_SPLIT(dev
))
888 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
889 if (encoder
->new_crtc
!= crtc
)
892 count_hdmi
+= encoder
->type
== INTEL_OUTPUT_HDMI
;
897 * HDMI 12bpc affects the clocks, so it's only possible
898 * when not cloning with other encoder types.
900 return count_hdmi
> 0 && count_hdmi
== count
;
903 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
904 struct intel_crtc_config
*pipe_config
)
906 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
907 struct drm_device
*dev
= encoder
->base
.dev
;
908 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
909 int clock_12bpc
= pipe_config
->adjusted_mode
.crtc_clock
* 3 / 2;
910 int portclock_limit
= hdmi_portclock_limit(intel_hdmi
, false);
913 pipe_config
->has_hdmi_sink
= intel_hdmi
->has_hdmi_sink
;
915 if (intel_hdmi
->color_range_auto
) {
916 /* See CEA-861-E - 5.1 Default Encoding Parameters */
917 if (pipe_config
->has_hdmi_sink
&&
918 drm_match_cea_mode(adjusted_mode
) > 1)
919 intel_hdmi
->color_range
= HDMI_COLOR_RANGE_16_235
;
921 intel_hdmi
->color_range
= 0;
924 if (intel_hdmi
->color_range
)
925 pipe_config
->limited_color_range
= true;
927 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
))
928 pipe_config
->has_pch_encoder
= true;
930 if (pipe_config
->has_hdmi_sink
&& intel_hdmi
->has_audio
)
931 pipe_config
->has_audio
= true;
934 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
935 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
936 * outputs. We also need to check that the higher clock still fits
939 if (pipe_config
->pipe_bpp
> 8*3 && pipe_config
->has_hdmi_sink
&&
940 clock_12bpc
<= portclock_limit
&&
941 hdmi_12bpc_possible(encoder
->new_crtc
)) {
942 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
945 /* Need to adjust the port link by 1.5x for 12bpc. */
946 pipe_config
->port_clock
= clock_12bpc
;
948 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
952 if (!pipe_config
->bw_constrained
) {
953 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp
);
954 pipe_config
->pipe_bpp
= desired_bpp
;
957 if (adjusted_mode
->crtc_clock
> portclock_limit
) {
958 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
965 static enum drm_connector_status
966 intel_hdmi_detect(struct drm_connector
*connector
, bool force
)
968 struct drm_device
*dev
= connector
->dev
;
969 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
970 struct intel_digital_port
*intel_dig_port
=
971 hdmi_to_dig_port(intel_hdmi
);
972 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
975 enum intel_display_power_domain power_domain
;
976 enum drm_connector_status status
= connector_status_disconnected
;
978 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
979 connector
->base
.id
, connector
->name
);
981 power_domain
= intel_display_port_power_domain(intel_encoder
);
982 intel_display_power_get(dev_priv
, power_domain
);
984 intel_hdmi
->has_hdmi_sink
= false;
985 intel_hdmi
->has_audio
= false;
986 intel_hdmi
->rgb_quant_range_selectable
= false;
987 edid
= drm_get_edid(connector
,
988 intel_gmbus_get_adapter(dev_priv
,
989 intel_hdmi
->ddc_bus
));
992 if (edid
->input
& DRM_EDID_INPUT_DIGITAL
) {
993 status
= connector_status_connected
;
994 if (intel_hdmi
->force_audio
!= HDMI_AUDIO_OFF_DVI
)
995 intel_hdmi
->has_hdmi_sink
=
996 drm_detect_hdmi_monitor(edid
);
997 intel_hdmi
->has_audio
= drm_detect_monitor_audio(edid
);
998 intel_hdmi
->rgb_quant_range_selectable
=
999 drm_rgb_quant_range_selectable(edid
);
1004 if (status
== connector_status_connected
) {
1005 if (intel_hdmi
->force_audio
!= HDMI_AUDIO_AUTO
)
1006 intel_hdmi
->has_audio
=
1007 (intel_hdmi
->force_audio
== HDMI_AUDIO_ON
);
1008 intel_encoder
->type
= INTEL_OUTPUT_HDMI
;
1011 intel_display_power_put(dev_priv
, power_domain
);
1016 static int intel_hdmi_get_modes(struct drm_connector
*connector
)
1018 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
1019 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
1020 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
1021 enum intel_display_power_domain power_domain
;
1024 /* We should parse the EDID data and find out if it's an HDMI sink so
1025 * we can send audio to it.
1028 power_domain
= intel_display_port_power_domain(intel_encoder
);
1029 intel_display_power_get(dev_priv
, power_domain
);
1031 ret
= intel_ddc_get_modes(connector
,
1032 intel_gmbus_get_adapter(dev_priv
,
1033 intel_hdmi
->ddc_bus
));
1035 intel_display_power_put(dev_priv
, power_domain
);
1041 intel_hdmi_detect_audio(struct drm_connector
*connector
)
1043 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
1044 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
1045 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
1046 enum intel_display_power_domain power_domain
;
1048 bool has_audio
= false;
1050 power_domain
= intel_display_port_power_domain(intel_encoder
);
1051 intel_display_power_get(dev_priv
, power_domain
);
1053 edid
= drm_get_edid(connector
,
1054 intel_gmbus_get_adapter(dev_priv
,
1055 intel_hdmi
->ddc_bus
));
1057 if (edid
->input
& DRM_EDID_INPUT_DIGITAL
)
1058 has_audio
= drm_detect_monitor_audio(edid
);
1062 intel_display_power_put(dev_priv
, power_domain
);
1068 intel_hdmi_set_property(struct drm_connector
*connector
,
1069 struct drm_property
*property
,
1072 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
1073 struct intel_digital_port
*intel_dig_port
=
1074 hdmi_to_dig_port(intel_hdmi
);
1075 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
1078 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
1082 if (property
== dev_priv
->force_audio_property
) {
1083 enum hdmi_force_audio i
= val
;
1086 if (i
== intel_hdmi
->force_audio
)
1089 intel_hdmi
->force_audio
= i
;
1091 if (i
== HDMI_AUDIO_AUTO
)
1092 has_audio
= intel_hdmi_detect_audio(connector
);
1094 has_audio
= (i
== HDMI_AUDIO_ON
);
1096 if (i
== HDMI_AUDIO_OFF_DVI
)
1097 intel_hdmi
->has_hdmi_sink
= 0;
1099 intel_hdmi
->has_audio
= has_audio
;
1103 if (property
== dev_priv
->broadcast_rgb_property
) {
1104 bool old_auto
= intel_hdmi
->color_range_auto
;
1105 uint32_t old_range
= intel_hdmi
->color_range
;
1108 case INTEL_BROADCAST_RGB_AUTO
:
1109 intel_hdmi
->color_range_auto
= true;
1111 case INTEL_BROADCAST_RGB_FULL
:
1112 intel_hdmi
->color_range_auto
= false;
1113 intel_hdmi
->color_range
= 0;
1115 case INTEL_BROADCAST_RGB_LIMITED
:
1116 intel_hdmi
->color_range_auto
= false;
1117 intel_hdmi
->color_range
= HDMI_COLOR_RANGE_16_235
;
1123 if (old_auto
== intel_hdmi
->color_range_auto
&&
1124 old_range
== intel_hdmi
->color_range
)
1130 if (property
== connector
->dev
->mode_config
.aspect_ratio_property
) {
1132 case DRM_MODE_PICTURE_ASPECT_NONE
:
1133 intel_hdmi
->aspect_ratio
= HDMI_PICTURE_ASPECT_NONE
;
1135 case DRM_MODE_PICTURE_ASPECT_4_3
:
1136 intel_hdmi
->aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
;
1138 case DRM_MODE_PICTURE_ASPECT_16_9
:
1139 intel_hdmi
->aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
;
1150 if (intel_dig_port
->base
.base
.crtc
)
1151 intel_crtc_restore_mode(intel_dig_port
->base
.base
.crtc
);
1156 static void intel_hdmi_pre_enable(struct intel_encoder
*encoder
)
1158 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1159 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
1160 struct drm_display_mode
*adjusted_mode
=
1161 &intel_crtc
->config
.adjusted_mode
;
1163 intel_hdmi_prepare(encoder
);
1165 intel_hdmi
->set_infoframes(&encoder
->base
,
1166 intel_crtc
->config
.has_hdmi_sink
,
1170 static void vlv_hdmi_pre_enable(struct intel_encoder
*encoder
)
1172 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1173 struct intel_hdmi
*intel_hdmi
= &dport
->hdmi
;
1174 struct drm_device
*dev
= encoder
->base
.dev
;
1175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1176 struct intel_crtc
*intel_crtc
=
1177 to_intel_crtc(encoder
->base
.crtc
);
1178 struct drm_display_mode
*adjusted_mode
=
1179 &intel_crtc
->config
.adjusted_mode
;
1180 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1181 int pipe
= intel_crtc
->pipe
;
1184 /* Enable clock channels for this port */
1185 mutex_lock(&dev_priv
->dpio_lock
);
1186 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
1193 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
1196 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0);
1197 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), 0x2b245f5f);
1198 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
), 0x5578b83a);
1199 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0c782040);
1200 vlv_dpio_write(dev_priv
, pipe
, VLV_TX3_DW4(port
), 0x2b247878);
1201 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
1202 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), 0x00002000);
1203 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), DPIO_TX_OCALINIT_EN
);
1205 /* Program lane clock */
1206 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
1207 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
1208 mutex_unlock(&dev_priv
->dpio_lock
);
1210 intel_hdmi
->set_infoframes(&encoder
->base
,
1211 intel_crtc
->config
.has_hdmi_sink
,
1214 intel_enable_hdmi(encoder
);
1216 vlv_wait_port_ready(dev_priv
, dport
);
1219 static void vlv_hdmi_pre_pll_enable(struct intel_encoder
*encoder
)
1221 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1222 struct drm_device
*dev
= encoder
->base
.dev
;
1223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1224 struct intel_crtc
*intel_crtc
=
1225 to_intel_crtc(encoder
->base
.crtc
);
1226 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1227 int pipe
= intel_crtc
->pipe
;
1229 intel_hdmi_prepare(encoder
);
1231 /* Program Tx lane resets to default */
1232 mutex_lock(&dev_priv
->dpio_lock
);
1233 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
1234 DPIO_PCS_TX_LANE2_RESET
|
1235 DPIO_PCS_TX_LANE1_RESET
);
1236 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
1237 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
1238 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
1239 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
1240 DPIO_PCS_CLK_SOFT_RESET
);
1242 /* Fix up inter-pair skew failure */
1243 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
1244 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
1245 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
1247 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), 0x00002000);
1248 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), DPIO_TX_OCALINIT_EN
);
1249 mutex_unlock(&dev_priv
->dpio_lock
);
1252 static void chv_hdmi_pre_pll_enable(struct intel_encoder
*encoder
)
1254 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1255 struct drm_device
*dev
= encoder
->base
.dev
;
1256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1257 struct intel_crtc
*intel_crtc
=
1258 to_intel_crtc(encoder
->base
.crtc
);
1259 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
1260 enum pipe pipe
= intel_crtc
->pipe
;
1263 mutex_lock(&dev_priv
->dpio_lock
);
1265 /* program left/right clock distribution */
1266 if (pipe
!= PIPE_B
) {
1267 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1268 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1270 val
|= CHV_BUFLEFTENA1_FORCE
;
1272 val
|= CHV_BUFRIGHTENA1_FORCE
;
1273 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1275 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1276 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1278 val
|= CHV_BUFLEFTENA2_FORCE
;
1280 val
|= CHV_BUFRIGHTENA2_FORCE
;
1281 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1284 /* program clock channel usage */
1285 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
1286 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
1288 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
1290 val
|= CHV_PCS_USEDCLKCHANNEL
;
1291 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
1293 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
1294 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
1296 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
1298 val
|= CHV_PCS_USEDCLKCHANNEL
;
1299 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
1302 * This a a bit weird since generally CL
1303 * matches the pipe, but here we need to
1304 * pick the CL based on the port.
1306 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
1308 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
1310 val
|= CHV_CMN_USEDCLKCHANNEL
;
1311 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
1313 mutex_unlock(&dev_priv
->dpio_lock
);
1316 static void vlv_hdmi_post_disable(struct intel_encoder
*encoder
)
1318 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1319 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1320 struct intel_crtc
*intel_crtc
=
1321 to_intel_crtc(encoder
->base
.crtc
);
1322 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1323 int pipe
= intel_crtc
->pipe
;
1325 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1326 mutex_lock(&dev_priv
->dpio_lock
);
1327 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
), 0x00000000);
1328 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
), 0x00e00060);
1329 mutex_unlock(&dev_priv
->dpio_lock
);
1332 static void chv_hdmi_post_disable(struct intel_encoder
*encoder
)
1334 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1335 struct drm_device
*dev
= encoder
->base
.dev
;
1336 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1337 struct intel_crtc
*intel_crtc
=
1338 to_intel_crtc(encoder
->base
.crtc
);
1339 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
1340 enum pipe pipe
= intel_crtc
->pipe
;
1343 mutex_lock(&dev_priv
->dpio_lock
);
1345 /* Propagate soft reset to data lane reset */
1346 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
1347 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
1348 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
1350 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
1351 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
1352 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
1354 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
1355 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
1356 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
1358 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
1359 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
1360 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
1362 mutex_unlock(&dev_priv
->dpio_lock
);
1365 static void chv_hdmi_pre_enable(struct intel_encoder
*encoder
)
1367 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1368 struct drm_device
*dev
= encoder
->base
.dev
;
1369 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1370 struct intel_crtc
*intel_crtc
=
1371 to_intel_crtc(encoder
->base
.crtc
);
1372 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
1373 int pipe
= intel_crtc
->pipe
;
1377 mutex_lock(&dev_priv
->dpio_lock
);
1379 /* Deassert soft data lane reset*/
1380 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
1381 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
1382 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
1384 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
1385 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
1386 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
1388 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
1389 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
1390 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
1392 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
1393 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
1394 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
1396 /* Program Tx latency optimal setting */
1397 for (i
= 0; i
< 4; i
++) {
1398 /* Set the latency optimal bit */
1399 data
= (i
== 1) ? 0x0 : 0x6;
1400 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW11(ch
, i
),
1401 data
<< DPIO_FRC_LATENCY_SHFIT
);
1403 /* Set the upar bit */
1404 data
= (i
== 1) ? 0x0 : 0x1;
1405 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
1406 data
<< DPIO_UPAR_SHIFT
);
1409 /* Data lane stagger programming */
1410 /* FIXME: Fix up value only after power analysis */
1412 /* Clear calc init */
1413 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
1414 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
1415 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
1417 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
1418 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
1419 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
1421 /* FIXME: Program the support xxx V-dB */
1423 for (i
= 0; i
< 4; i
++) {
1424 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
1425 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
1426 val
|= 128 << DPIO_SWING_DEEMPH9P5_SHIFT
;
1427 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
1430 for (i
= 0; i
< 4; i
++) {
1431 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
1432 val
&= ~DPIO_SWING_MARGIN_MASK
;
1433 val
|= 102 << DPIO_SWING_MARGIN_SHIFT
;
1434 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
1437 /* Disable unique transition scale */
1438 for (i
= 0; i
< 4; i
++) {
1439 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
1440 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
1441 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
1444 /* Additional steps for 1200mV-0dB */
1446 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_TX_DW3(ch
));
1448 val
|= DPIO_TX_UNIQ_TRANS_SCALE_CH1
;
1450 val
|= DPIO_TX_UNIQ_TRANS_SCALE_CH0
;
1451 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(ch
), val
);
1453 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(ch
),
1454 vlv_dpio_read(dev_priv
, pipe
, VLV_TX_DW2(ch
)) |
1455 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
));
1457 /* Start swing calculation */
1458 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
1459 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
1460 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
1462 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
1463 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
1464 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
1467 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
1468 val
|= DPIO_LRC_BYPASS
;
1469 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
1471 mutex_unlock(&dev_priv
->dpio_lock
);
1473 intel_enable_hdmi(encoder
);
1475 vlv_wait_port_ready(dev_priv
, dport
);
1478 static void intel_hdmi_destroy(struct drm_connector
*connector
)
1480 drm_connector_cleanup(connector
);
1484 static const struct drm_connector_funcs intel_hdmi_connector_funcs
= {
1485 .dpms
= intel_connector_dpms
,
1486 .detect
= intel_hdmi_detect
,
1487 .fill_modes
= drm_helper_probe_single_connector_modes
,
1488 .set_property
= intel_hdmi_set_property
,
1489 .destroy
= intel_hdmi_destroy
,
1492 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs
= {
1493 .get_modes
= intel_hdmi_get_modes
,
1494 .mode_valid
= intel_hdmi_mode_valid
,
1495 .best_encoder
= intel_best_encoder
,
1498 static const struct drm_encoder_funcs intel_hdmi_enc_funcs
= {
1499 .destroy
= intel_encoder_destroy
,
1503 intel_attach_aspect_ratio_property(struct drm_connector
*connector
)
1505 if (!drm_mode_create_aspect_ratio_property(connector
->dev
))
1506 drm_object_attach_property(&connector
->base
,
1507 connector
->dev
->mode_config
.aspect_ratio_property
,
1508 DRM_MODE_PICTURE_ASPECT_NONE
);
1512 intel_hdmi_add_properties(struct intel_hdmi
*intel_hdmi
, struct drm_connector
*connector
)
1514 intel_attach_force_audio_property(connector
);
1515 intel_attach_broadcast_rgb_property(connector
);
1516 intel_hdmi
->color_range_auto
= true;
1517 intel_attach_aspect_ratio_property(connector
);
1518 intel_hdmi
->aspect_ratio
= HDMI_PICTURE_ASPECT_NONE
;
1521 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
1522 struct intel_connector
*intel_connector
)
1524 struct drm_connector
*connector
= &intel_connector
->base
;
1525 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
1526 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1527 struct drm_device
*dev
= intel_encoder
->base
.dev
;
1528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1529 enum port port
= intel_dig_port
->port
;
1531 drm_connector_init(dev
, connector
, &intel_hdmi_connector_funcs
,
1532 DRM_MODE_CONNECTOR_HDMIA
);
1533 drm_connector_helper_add(connector
, &intel_hdmi_connector_helper_funcs
);
1535 connector
->interlace_allowed
= 1;
1536 connector
->doublescan_allowed
= 0;
1537 connector
->stereo_allowed
= 1;
1541 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPB
;
1542 intel_encoder
->hpd_pin
= HPD_PORT_B
;
1545 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPC
;
1546 intel_encoder
->hpd_pin
= HPD_PORT_C
;
1549 if (IS_CHERRYVIEW(dev
))
1550 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPD_CHV
;
1552 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPD
;
1553 intel_encoder
->hpd_pin
= HPD_PORT_D
;
1556 intel_encoder
->hpd_pin
= HPD_PORT_A
;
1557 /* Internal port only for eDP. */
1562 if (IS_VALLEYVIEW(dev
)) {
1563 intel_hdmi
->write_infoframe
= vlv_write_infoframe
;
1564 intel_hdmi
->set_infoframes
= vlv_set_infoframes
;
1565 } else if (!HAS_PCH_SPLIT(dev
)) {
1566 intel_hdmi
->write_infoframe
= g4x_write_infoframe
;
1567 intel_hdmi
->set_infoframes
= g4x_set_infoframes
;
1568 } else if (HAS_DDI(dev
)) {
1569 intel_hdmi
->write_infoframe
= hsw_write_infoframe
;
1570 intel_hdmi
->set_infoframes
= hsw_set_infoframes
;
1571 } else if (HAS_PCH_IBX(dev
)) {
1572 intel_hdmi
->write_infoframe
= ibx_write_infoframe
;
1573 intel_hdmi
->set_infoframes
= ibx_set_infoframes
;
1575 intel_hdmi
->write_infoframe
= cpt_write_infoframe
;
1576 intel_hdmi
->set_infoframes
= cpt_set_infoframes
;
1580 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
1582 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
1583 intel_connector
->unregister
= intel_connector_unregister
;
1585 intel_hdmi_add_properties(intel_hdmi
, connector
);
1587 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
1588 drm_sysfs_connector_add(connector
);
1590 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1591 * 0xd. Failure to do so will result in spurious interrupts being
1592 * generated on the port when a cable is not attached.
1594 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
1595 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
1596 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
1600 void intel_hdmi_init(struct drm_device
*dev
, int hdmi_reg
, enum port port
)
1602 struct intel_digital_port
*intel_dig_port
;
1603 struct intel_encoder
*intel_encoder
;
1604 struct intel_connector
*intel_connector
;
1606 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
1607 if (!intel_dig_port
)
1610 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
1611 if (!intel_connector
) {
1612 kfree(intel_dig_port
);
1616 intel_encoder
= &intel_dig_port
->base
;
1618 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_hdmi_enc_funcs
,
1619 DRM_MODE_ENCODER_TMDS
);
1621 intel_encoder
->compute_config
= intel_hdmi_compute_config
;
1622 intel_encoder
->disable
= intel_disable_hdmi
;
1623 intel_encoder
->get_hw_state
= intel_hdmi_get_hw_state
;
1624 intel_encoder
->get_config
= intel_hdmi_get_config
;
1625 if (IS_CHERRYVIEW(dev
)) {
1626 intel_encoder
->pre_pll_enable
= chv_hdmi_pre_pll_enable
;
1627 intel_encoder
->pre_enable
= chv_hdmi_pre_enable
;
1628 intel_encoder
->enable
= vlv_enable_hdmi
;
1629 intel_encoder
->post_disable
= chv_hdmi_post_disable
;
1630 } else if (IS_VALLEYVIEW(dev
)) {
1631 intel_encoder
->pre_pll_enable
= vlv_hdmi_pre_pll_enable
;
1632 intel_encoder
->pre_enable
= vlv_hdmi_pre_enable
;
1633 intel_encoder
->enable
= vlv_enable_hdmi
;
1634 intel_encoder
->post_disable
= vlv_hdmi_post_disable
;
1636 intel_encoder
->pre_enable
= intel_hdmi_pre_enable
;
1637 intel_encoder
->enable
= intel_enable_hdmi
;
1640 intel_encoder
->type
= INTEL_OUTPUT_HDMI
;
1641 if (IS_CHERRYVIEW(dev
)) {
1643 intel_encoder
->crtc_mask
= 1 << 2;
1645 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
1647 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
1649 intel_encoder
->cloneable
= 1 << INTEL_OUTPUT_ANALOG
;
1651 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1652 * to work on real hardware. And since g4x can send infoframes to
1653 * only one port anyway, nothing is lost by allowing it.
1656 intel_encoder
->cloneable
|= 1 << INTEL_OUTPUT_HDMI
;
1658 intel_dig_port
->port
= port
;
1659 intel_dig_port
->hdmi
.hdmi_reg
= hdmi_reg
;
1660 intel_dig_port
->dp
.output_reg
= 0;
1662 intel_hdmi_init_connector(intel_dig_port
, intel_connector
);