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Merge tag 'drm-for-v4.9' into drm-intel-next-queued
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_hdmi.c
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
33 #include <drm/drmP.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40
41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
42 {
43 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
44 }
45
46 static void
47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
48 {
49 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
50 struct drm_i915_private *dev_priv = to_i915(dev);
51 uint32_t enabled_bits;
52
53 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
54
55 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
56 "HDMI port enabled, expecting disabled\n");
57 }
58
59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
60 {
61 struct intel_digital_port *intel_dig_port =
62 container_of(encoder, struct intel_digital_port, base.base);
63 return &intel_dig_port->hdmi;
64 }
65
66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
67 {
68 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
69 }
70
71 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
72 {
73 switch (type) {
74 case HDMI_INFOFRAME_TYPE_AVI:
75 return VIDEO_DIP_SELECT_AVI;
76 case HDMI_INFOFRAME_TYPE_SPD:
77 return VIDEO_DIP_SELECT_SPD;
78 case HDMI_INFOFRAME_TYPE_VENDOR:
79 return VIDEO_DIP_SELECT_VENDOR;
80 default:
81 MISSING_CASE(type);
82 return 0;
83 }
84 }
85
86 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
87 {
88 switch (type) {
89 case HDMI_INFOFRAME_TYPE_AVI:
90 return VIDEO_DIP_ENABLE_AVI;
91 case HDMI_INFOFRAME_TYPE_SPD:
92 return VIDEO_DIP_ENABLE_SPD;
93 case HDMI_INFOFRAME_TYPE_VENDOR:
94 return VIDEO_DIP_ENABLE_VENDOR;
95 default:
96 MISSING_CASE(type);
97 return 0;
98 }
99 }
100
101 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
102 {
103 switch (type) {
104 case HDMI_INFOFRAME_TYPE_AVI:
105 return VIDEO_DIP_ENABLE_AVI_HSW;
106 case HDMI_INFOFRAME_TYPE_SPD:
107 return VIDEO_DIP_ENABLE_SPD_HSW;
108 case HDMI_INFOFRAME_TYPE_VENDOR:
109 return VIDEO_DIP_ENABLE_VS_HSW;
110 default:
111 MISSING_CASE(type);
112 return 0;
113 }
114 }
115
116 static i915_reg_t
117 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
118 enum transcoder cpu_transcoder,
119 enum hdmi_infoframe_type type,
120 int i)
121 {
122 switch (type) {
123 case HDMI_INFOFRAME_TYPE_AVI:
124 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
125 case HDMI_INFOFRAME_TYPE_SPD:
126 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
127 case HDMI_INFOFRAME_TYPE_VENDOR:
128 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
129 default:
130 MISSING_CASE(type);
131 return INVALID_MMIO_REG;
132 }
133 }
134
135 static void g4x_write_infoframe(struct drm_encoder *encoder,
136 enum hdmi_infoframe_type type,
137 const void *frame, ssize_t len)
138 {
139 const uint32_t *data = frame;
140 struct drm_device *dev = encoder->dev;
141 struct drm_i915_private *dev_priv = to_i915(dev);
142 u32 val = I915_READ(VIDEO_DIP_CTL);
143 int i;
144
145 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
146
147 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
148 val |= g4x_infoframe_index(type);
149
150 val &= ~g4x_infoframe_enable(type);
151
152 I915_WRITE(VIDEO_DIP_CTL, val);
153
154 mmiowb();
155 for (i = 0; i < len; i += 4) {
156 I915_WRITE(VIDEO_DIP_DATA, *data);
157 data++;
158 }
159 /* Write every possible data byte to force correct ECC calculation. */
160 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
161 I915_WRITE(VIDEO_DIP_DATA, 0);
162 mmiowb();
163
164 val |= g4x_infoframe_enable(type);
165 val &= ~VIDEO_DIP_FREQ_MASK;
166 val |= VIDEO_DIP_FREQ_VSYNC;
167
168 I915_WRITE(VIDEO_DIP_CTL, val);
169 POSTING_READ(VIDEO_DIP_CTL);
170 }
171
172 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
173 const struct intel_crtc_state *pipe_config)
174 {
175 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
176 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
177 u32 val = I915_READ(VIDEO_DIP_CTL);
178
179 if ((val & VIDEO_DIP_ENABLE) == 0)
180 return false;
181
182 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
183 return false;
184
185 return val & (VIDEO_DIP_ENABLE_AVI |
186 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
187 }
188
189 static void ibx_write_infoframe(struct drm_encoder *encoder,
190 enum hdmi_infoframe_type type,
191 const void *frame, ssize_t len)
192 {
193 const uint32_t *data = frame;
194 struct drm_device *dev = encoder->dev;
195 struct drm_i915_private *dev_priv = to_i915(dev);
196 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
197 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
198 u32 val = I915_READ(reg);
199 int i;
200
201 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
202
203 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
204 val |= g4x_infoframe_index(type);
205
206 val &= ~g4x_infoframe_enable(type);
207
208 I915_WRITE(reg, val);
209
210 mmiowb();
211 for (i = 0; i < len; i += 4) {
212 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
213 data++;
214 }
215 /* Write every possible data byte to force correct ECC calculation. */
216 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
217 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
218 mmiowb();
219
220 val |= g4x_infoframe_enable(type);
221 val &= ~VIDEO_DIP_FREQ_MASK;
222 val |= VIDEO_DIP_FREQ_VSYNC;
223
224 I915_WRITE(reg, val);
225 POSTING_READ(reg);
226 }
227
228 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
229 const struct intel_crtc_state *pipe_config)
230 {
231 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
232 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
233 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
234 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
235 u32 val = I915_READ(reg);
236
237 if ((val & VIDEO_DIP_ENABLE) == 0)
238 return false;
239
240 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
241 return false;
242
243 return val & (VIDEO_DIP_ENABLE_AVI |
244 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
245 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
246 }
247
248 static void cpt_write_infoframe(struct drm_encoder *encoder,
249 enum hdmi_infoframe_type type,
250 const void *frame, ssize_t len)
251 {
252 const uint32_t *data = frame;
253 struct drm_device *dev = encoder->dev;
254 struct drm_i915_private *dev_priv = to_i915(dev);
255 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
256 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
257 u32 val = I915_READ(reg);
258 int i;
259
260 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
261
262 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
263 val |= g4x_infoframe_index(type);
264
265 /* The DIP control register spec says that we need to update the AVI
266 * infoframe without clearing its enable bit */
267 if (type != HDMI_INFOFRAME_TYPE_AVI)
268 val &= ~g4x_infoframe_enable(type);
269
270 I915_WRITE(reg, val);
271
272 mmiowb();
273 for (i = 0; i < len; i += 4) {
274 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
275 data++;
276 }
277 /* Write every possible data byte to force correct ECC calculation. */
278 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
279 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
280 mmiowb();
281
282 val |= g4x_infoframe_enable(type);
283 val &= ~VIDEO_DIP_FREQ_MASK;
284 val |= VIDEO_DIP_FREQ_VSYNC;
285
286 I915_WRITE(reg, val);
287 POSTING_READ(reg);
288 }
289
290 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
291 const struct intel_crtc_state *pipe_config)
292 {
293 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
294 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
295 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
296
297 if ((val & VIDEO_DIP_ENABLE) == 0)
298 return false;
299
300 return val & (VIDEO_DIP_ENABLE_AVI |
301 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
302 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
303 }
304
305 static void vlv_write_infoframe(struct drm_encoder *encoder,
306 enum hdmi_infoframe_type type,
307 const void *frame, ssize_t len)
308 {
309 const uint32_t *data = frame;
310 struct drm_device *dev = encoder->dev;
311 struct drm_i915_private *dev_priv = to_i915(dev);
312 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
313 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
314 u32 val = I915_READ(reg);
315 int i;
316
317 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
318
319 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
320 val |= g4x_infoframe_index(type);
321
322 val &= ~g4x_infoframe_enable(type);
323
324 I915_WRITE(reg, val);
325
326 mmiowb();
327 for (i = 0; i < len; i += 4) {
328 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
329 data++;
330 }
331 /* Write every possible data byte to force correct ECC calculation. */
332 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
333 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
334 mmiowb();
335
336 val |= g4x_infoframe_enable(type);
337 val &= ~VIDEO_DIP_FREQ_MASK;
338 val |= VIDEO_DIP_FREQ_VSYNC;
339
340 I915_WRITE(reg, val);
341 POSTING_READ(reg);
342 }
343
344 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
345 const struct intel_crtc_state *pipe_config)
346 {
347 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
348 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
349 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
350 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
351
352 if ((val & VIDEO_DIP_ENABLE) == 0)
353 return false;
354
355 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
356 return false;
357
358 return val & (VIDEO_DIP_ENABLE_AVI |
359 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
360 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
361 }
362
363 static void hsw_write_infoframe(struct drm_encoder *encoder,
364 enum hdmi_infoframe_type type,
365 const void *frame, ssize_t len)
366 {
367 const uint32_t *data = frame;
368 struct drm_device *dev = encoder->dev;
369 struct drm_i915_private *dev_priv = to_i915(dev);
370 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
371 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
372 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
373 i915_reg_t data_reg;
374 int i;
375 u32 val = I915_READ(ctl_reg);
376
377 data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
378
379 val &= ~hsw_infoframe_enable(type);
380 I915_WRITE(ctl_reg, val);
381
382 mmiowb();
383 for (i = 0; i < len; i += 4) {
384 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
385 type, i >> 2), *data);
386 data++;
387 }
388 /* Write every possible data byte to force correct ECC calculation. */
389 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
390 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
391 type, i >> 2), 0);
392 mmiowb();
393
394 val |= hsw_infoframe_enable(type);
395 I915_WRITE(ctl_reg, val);
396 POSTING_READ(ctl_reg);
397 }
398
399 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
400 const struct intel_crtc_state *pipe_config)
401 {
402 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
403 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
404
405 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
406 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
407 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
408 }
409
410 /*
411 * The data we write to the DIP data buffer registers is 1 byte bigger than the
412 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
413 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
414 * used for both technologies.
415 *
416 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
417 * DW1: DB3 | DB2 | DB1 | DB0
418 * DW2: DB7 | DB6 | DB5 | DB4
419 * DW3: ...
420 *
421 * (HB is Header Byte, DB is Data Byte)
422 *
423 * The hdmi pack() functions don't know about that hardware specific hole so we
424 * trick them by giving an offset into the buffer and moving back the header
425 * bytes by one.
426 */
427 static void intel_write_infoframe(struct drm_encoder *encoder,
428 union hdmi_infoframe *frame)
429 {
430 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
431 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
432 ssize_t len;
433
434 /* see comment above for the reason for this offset */
435 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
436 if (len < 0)
437 return;
438
439 /* Insert the 'hole' (see big comment above) at position 3 */
440 buffer[0] = buffer[1];
441 buffer[1] = buffer[2];
442 buffer[2] = buffer[3];
443 buffer[3] = 0;
444 len++;
445
446 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
447 }
448
449 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
450 const struct drm_display_mode *adjusted_mode)
451 {
452 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
453 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
454 union hdmi_infoframe frame;
455 int ret;
456
457 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
458 adjusted_mode);
459 if (ret < 0) {
460 DRM_ERROR("couldn't fill AVI infoframe\n");
461 return;
462 }
463
464 if (intel_hdmi->rgb_quant_range_selectable) {
465 if (intel_crtc->config->limited_color_range)
466 frame.avi.quantization_range =
467 HDMI_QUANTIZATION_RANGE_LIMITED;
468 else
469 frame.avi.quantization_range =
470 HDMI_QUANTIZATION_RANGE_FULL;
471 }
472
473 intel_write_infoframe(encoder, &frame);
474 }
475
476 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
477 {
478 union hdmi_infoframe frame;
479 int ret;
480
481 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
482 if (ret < 0) {
483 DRM_ERROR("couldn't fill SPD infoframe\n");
484 return;
485 }
486
487 frame.spd.sdi = HDMI_SPD_SDI_PC;
488
489 intel_write_infoframe(encoder, &frame);
490 }
491
492 static void
493 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
494 const struct drm_display_mode *adjusted_mode)
495 {
496 union hdmi_infoframe frame;
497 int ret;
498
499 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
500 adjusted_mode);
501 if (ret < 0)
502 return;
503
504 intel_write_infoframe(encoder, &frame);
505 }
506
507 static void g4x_set_infoframes(struct drm_encoder *encoder,
508 bool enable,
509 const struct drm_display_mode *adjusted_mode)
510 {
511 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
512 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
513 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
514 i915_reg_t reg = VIDEO_DIP_CTL;
515 u32 val = I915_READ(reg);
516 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
517
518 assert_hdmi_port_disabled(intel_hdmi);
519
520 /* If the registers were not initialized yet, they might be zeroes,
521 * which means we're selecting the AVI DIP and we're setting its
522 * frequency to once. This seems to really confuse the HW and make
523 * things stop working (the register spec says the AVI always needs to
524 * be sent every VSync). So here we avoid writing to the register more
525 * than we need and also explicitly select the AVI DIP and explicitly
526 * set its frequency to every VSync. Avoiding to write it twice seems to
527 * be enough to solve the problem, but being defensive shouldn't hurt us
528 * either. */
529 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
530
531 if (!enable) {
532 if (!(val & VIDEO_DIP_ENABLE))
533 return;
534 if (port != (val & VIDEO_DIP_PORT_MASK)) {
535 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
536 (val & VIDEO_DIP_PORT_MASK) >> 29);
537 return;
538 }
539 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
540 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
541 I915_WRITE(reg, val);
542 POSTING_READ(reg);
543 return;
544 }
545
546 if (port != (val & VIDEO_DIP_PORT_MASK)) {
547 if (val & VIDEO_DIP_ENABLE) {
548 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
549 (val & VIDEO_DIP_PORT_MASK) >> 29);
550 return;
551 }
552 val &= ~VIDEO_DIP_PORT_MASK;
553 val |= port;
554 }
555
556 val |= VIDEO_DIP_ENABLE;
557 val &= ~(VIDEO_DIP_ENABLE_AVI |
558 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
559
560 I915_WRITE(reg, val);
561 POSTING_READ(reg);
562
563 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
564 intel_hdmi_set_spd_infoframe(encoder);
565 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
566 }
567
568 static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
569 {
570 struct drm_device *dev = encoder->dev;
571 struct drm_connector *connector;
572
573 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
574
575 /*
576 * HDMI cloning is only supported on g4x which doesn't
577 * support deep color or GCP infoframes anyway so no
578 * need to worry about multiple HDMI sinks here.
579 */
580 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
581 if (connector->encoder == encoder)
582 return connector->display_info.bpc > 8;
583
584 return false;
585 }
586
587 /*
588 * Determine if default_phase=1 can be indicated in the GCP infoframe.
589 *
590 * From HDMI specification 1.4a:
591 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
592 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
593 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
594 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
595 * phase of 0
596 */
597 static bool gcp_default_phase_possible(int pipe_bpp,
598 const struct drm_display_mode *mode)
599 {
600 unsigned int pixels_per_group;
601
602 switch (pipe_bpp) {
603 case 30:
604 /* 4 pixels in 5 clocks */
605 pixels_per_group = 4;
606 break;
607 case 36:
608 /* 2 pixels in 3 clocks */
609 pixels_per_group = 2;
610 break;
611 case 48:
612 /* 1 pixel in 2 clocks */
613 pixels_per_group = 1;
614 break;
615 default:
616 /* phase information not relevant for 8bpc */
617 return false;
618 }
619
620 return mode->crtc_hdisplay % pixels_per_group == 0 &&
621 mode->crtc_htotal % pixels_per_group == 0 &&
622 mode->crtc_hblank_start % pixels_per_group == 0 &&
623 mode->crtc_hblank_end % pixels_per_group == 0 &&
624 mode->crtc_hsync_start % pixels_per_group == 0 &&
625 mode->crtc_hsync_end % pixels_per_group == 0 &&
626 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
627 mode->crtc_htotal/2 % pixels_per_group == 0);
628 }
629
630 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
631 {
632 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
633 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
634 i915_reg_t reg;
635 u32 val = 0;
636
637 if (HAS_DDI(dev_priv))
638 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
639 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
640 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
641 else if (HAS_PCH_SPLIT(dev_priv))
642 reg = TVIDEO_DIP_GCP(crtc->pipe);
643 else
644 return false;
645
646 /* Indicate color depth whenever the sink supports deep color */
647 if (hdmi_sink_is_deep_color(encoder))
648 val |= GCP_COLOR_INDICATION;
649
650 /* Enable default_phase whenever the display mode is suitably aligned */
651 if (gcp_default_phase_possible(crtc->config->pipe_bpp,
652 &crtc->config->base.adjusted_mode))
653 val |= GCP_DEFAULT_PHASE_ENABLE;
654
655 I915_WRITE(reg, val);
656
657 return val != 0;
658 }
659
660 static void ibx_set_infoframes(struct drm_encoder *encoder,
661 bool enable,
662 const struct drm_display_mode *adjusted_mode)
663 {
664 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
665 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
666 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
667 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
668 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
669 u32 val = I915_READ(reg);
670 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
671
672 assert_hdmi_port_disabled(intel_hdmi);
673
674 /* See the big comment in g4x_set_infoframes() */
675 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
676
677 if (!enable) {
678 if (!(val & VIDEO_DIP_ENABLE))
679 return;
680 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
681 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
682 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
683 I915_WRITE(reg, val);
684 POSTING_READ(reg);
685 return;
686 }
687
688 if (port != (val & VIDEO_DIP_PORT_MASK)) {
689 WARN(val & VIDEO_DIP_ENABLE,
690 "DIP already enabled on port %c\n",
691 (val & VIDEO_DIP_PORT_MASK) >> 29);
692 val &= ~VIDEO_DIP_PORT_MASK;
693 val |= port;
694 }
695
696 val |= VIDEO_DIP_ENABLE;
697 val &= ~(VIDEO_DIP_ENABLE_AVI |
698 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
699 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
700
701 if (intel_hdmi_set_gcp_infoframe(encoder))
702 val |= VIDEO_DIP_ENABLE_GCP;
703
704 I915_WRITE(reg, val);
705 POSTING_READ(reg);
706
707 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
708 intel_hdmi_set_spd_infoframe(encoder);
709 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
710 }
711
712 static void cpt_set_infoframes(struct drm_encoder *encoder,
713 bool enable,
714 const struct drm_display_mode *adjusted_mode)
715 {
716 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
717 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
718 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
719 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
720 u32 val = I915_READ(reg);
721
722 assert_hdmi_port_disabled(intel_hdmi);
723
724 /* See the big comment in g4x_set_infoframes() */
725 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
726
727 if (!enable) {
728 if (!(val & VIDEO_DIP_ENABLE))
729 return;
730 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
731 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
732 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
733 I915_WRITE(reg, val);
734 POSTING_READ(reg);
735 return;
736 }
737
738 /* Set both together, unset both together: see the spec. */
739 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
740 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
741 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
742
743 if (intel_hdmi_set_gcp_infoframe(encoder))
744 val |= VIDEO_DIP_ENABLE_GCP;
745
746 I915_WRITE(reg, val);
747 POSTING_READ(reg);
748
749 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
750 intel_hdmi_set_spd_infoframe(encoder);
751 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
752 }
753
754 static void vlv_set_infoframes(struct drm_encoder *encoder,
755 bool enable,
756 const struct drm_display_mode *adjusted_mode)
757 {
758 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
759 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
760 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
761 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
762 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
763 u32 val = I915_READ(reg);
764 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
765
766 assert_hdmi_port_disabled(intel_hdmi);
767
768 /* See the big comment in g4x_set_infoframes() */
769 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
770
771 if (!enable) {
772 if (!(val & VIDEO_DIP_ENABLE))
773 return;
774 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
775 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
776 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
777 I915_WRITE(reg, val);
778 POSTING_READ(reg);
779 return;
780 }
781
782 if (port != (val & VIDEO_DIP_PORT_MASK)) {
783 WARN(val & VIDEO_DIP_ENABLE,
784 "DIP already enabled on port %c\n",
785 (val & VIDEO_DIP_PORT_MASK) >> 29);
786 val &= ~VIDEO_DIP_PORT_MASK;
787 val |= port;
788 }
789
790 val |= VIDEO_DIP_ENABLE;
791 val &= ~(VIDEO_DIP_ENABLE_AVI |
792 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
793 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
794
795 if (intel_hdmi_set_gcp_infoframe(encoder))
796 val |= VIDEO_DIP_ENABLE_GCP;
797
798 I915_WRITE(reg, val);
799 POSTING_READ(reg);
800
801 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
802 intel_hdmi_set_spd_infoframe(encoder);
803 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
804 }
805
806 static void hsw_set_infoframes(struct drm_encoder *encoder,
807 bool enable,
808 const struct drm_display_mode *adjusted_mode)
809 {
810 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
811 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
812 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
813 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
814 u32 val = I915_READ(reg);
815
816 assert_hdmi_port_disabled(intel_hdmi);
817
818 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
819 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
820 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
821
822 if (!enable) {
823 I915_WRITE(reg, val);
824 POSTING_READ(reg);
825 return;
826 }
827
828 if (intel_hdmi_set_gcp_infoframe(encoder))
829 val |= VIDEO_DIP_ENABLE_GCP_HSW;
830
831 I915_WRITE(reg, val);
832 POSTING_READ(reg);
833
834 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
835 intel_hdmi_set_spd_infoframe(encoder);
836 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
837 }
838
839 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
840 {
841 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
842 struct i2c_adapter *adapter =
843 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
844
845 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
846 return;
847
848 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
849 enable ? "Enabling" : "Disabling");
850
851 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
852 adapter, enable);
853 }
854
855 static void intel_hdmi_prepare(struct intel_encoder *encoder)
856 {
857 struct drm_device *dev = encoder->base.dev;
858 struct drm_i915_private *dev_priv = to_i915(dev);
859 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
860 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
861 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
862 u32 hdmi_val;
863
864 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
865
866 hdmi_val = SDVO_ENCODING_HDMI;
867 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
868 hdmi_val |= HDMI_COLOR_RANGE_16_235;
869 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
870 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
871 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
872 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
873
874 if (crtc->config->pipe_bpp > 24)
875 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
876 else
877 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
878
879 if (crtc->config->has_hdmi_sink)
880 hdmi_val |= HDMI_MODE_SELECT_HDMI;
881
882 if (HAS_PCH_CPT(dev))
883 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
884 else if (IS_CHERRYVIEW(dev))
885 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
886 else
887 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
888
889 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
890 POSTING_READ(intel_hdmi->hdmi_reg);
891 }
892
893 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
894 enum pipe *pipe)
895 {
896 struct drm_device *dev = encoder->base.dev;
897 struct drm_i915_private *dev_priv = to_i915(dev);
898 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
899 enum intel_display_power_domain power_domain;
900 u32 tmp;
901 bool ret;
902
903 power_domain = intel_display_port_power_domain(encoder);
904 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
905 return false;
906
907 ret = false;
908
909 tmp = I915_READ(intel_hdmi->hdmi_reg);
910
911 if (!(tmp & SDVO_ENABLE))
912 goto out;
913
914 if (HAS_PCH_CPT(dev))
915 *pipe = PORT_TO_PIPE_CPT(tmp);
916 else if (IS_CHERRYVIEW(dev))
917 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
918 else
919 *pipe = PORT_TO_PIPE(tmp);
920
921 ret = true;
922
923 out:
924 intel_display_power_put(dev_priv, power_domain);
925
926 return ret;
927 }
928
929 static void intel_hdmi_get_config(struct intel_encoder *encoder,
930 struct intel_crtc_state *pipe_config)
931 {
932 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
933 struct drm_device *dev = encoder->base.dev;
934 struct drm_i915_private *dev_priv = to_i915(dev);
935 u32 tmp, flags = 0;
936 int dotclock;
937
938 tmp = I915_READ(intel_hdmi->hdmi_reg);
939
940 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
941 flags |= DRM_MODE_FLAG_PHSYNC;
942 else
943 flags |= DRM_MODE_FLAG_NHSYNC;
944
945 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
946 flags |= DRM_MODE_FLAG_PVSYNC;
947 else
948 flags |= DRM_MODE_FLAG_NVSYNC;
949
950 if (tmp & HDMI_MODE_SELECT_HDMI)
951 pipe_config->has_hdmi_sink = true;
952
953 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
954 pipe_config->has_infoframe = true;
955
956 if (tmp & SDVO_AUDIO_ENABLE)
957 pipe_config->has_audio = true;
958
959 if (!HAS_PCH_SPLIT(dev) &&
960 tmp & HDMI_COLOR_RANGE_16_235)
961 pipe_config->limited_color_range = true;
962
963 pipe_config->base.adjusted_mode.flags |= flags;
964
965 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
966 dotclock = pipe_config->port_clock * 2 / 3;
967 else
968 dotclock = pipe_config->port_clock;
969
970 if (pipe_config->pixel_multiplier)
971 dotclock /= pipe_config->pixel_multiplier;
972
973 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
974
975 pipe_config->lane_count = 4;
976 }
977
978 static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
979 {
980 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
981
982 WARN_ON(!crtc->config->has_hdmi_sink);
983 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
984 pipe_name(crtc->pipe));
985 intel_audio_codec_enable(encoder);
986 }
987
988 static void g4x_enable_hdmi(struct intel_encoder *encoder,
989 struct intel_crtc_state *pipe_config,
990 struct drm_connector_state *conn_state)
991 {
992 struct drm_device *dev = encoder->base.dev;
993 struct drm_i915_private *dev_priv = to_i915(dev);
994 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
995 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
996 u32 temp;
997
998 temp = I915_READ(intel_hdmi->hdmi_reg);
999
1000 temp |= SDVO_ENABLE;
1001 if (crtc->config->has_audio)
1002 temp |= SDVO_AUDIO_ENABLE;
1003
1004 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1005 POSTING_READ(intel_hdmi->hdmi_reg);
1006
1007 if (crtc->config->has_audio)
1008 intel_enable_hdmi_audio(encoder);
1009 }
1010
1011 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1012 struct intel_crtc_state *pipe_config,
1013 struct drm_connector_state *conn_state)
1014 {
1015 struct drm_device *dev = encoder->base.dev;
1016 struct drm_i915_private *dev_priv = to_i915(dev);
1017 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1018 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1019 u32 temp;
1020
1021 temp = I915_READ(intel_hdmi->hdmi_reg);
1022
1023 temp |= SDVO_ENABLE;
1024 if (crtc->config->has_audio)
1025 temp |= SDVO_AUDIO_ENABLE;
1026
1027 /*
1028 * HW workaround, need to write this twice for issue
1029 * that may result in first write getting masked.
1030 */
1031 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1032 POSTING_READ(intel_hdmi->hdmi_reg);
1033 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1034 POSTING_READ(intel_hdmi->hdmi_reg);
1035
1036 /*
1037 * HW workaround, need to toggle enable bit off and on
1038 * for 12bpc with pixel repeat.
1039 *
1040 * FIXME: BSpec says this should be done at the end of
1041 * of the modeset sequence, so not sure if this isn't too soon.
1042 */
1043 if (crtc->config->pipe_bpp > 24 &&
1044 crtc->config->pixel_multiplier > 1) {
1045 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1046 POSTING_READ(intel_hdmi->hdmi_reg);
1047
1048 /*
1049 * HW workaround, need to write this twice for issue
1050 * that may result in first write getting masked.
1051 */
1052 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1053 POSTING_READ(intel_hdmi->hdmi_reg);
1054 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1055 POSTING_READ(intel_hdmi->hdmi_reg);
1056 }
1057
1058 if (crtc->config->has_audio)
1059 intel_enable_hdmi_audio(encoder);
1060 }
1061
1062 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1063 struct intel_crtc_state *pipe_config,
1064 struct drm_connector_state *conn_state)
1065 {
1066 struct drm_device *dev = encoder->base.dev;
1067 struct drm_i915_private *dev_priv = to_i915(dev);
1068 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1069 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1070 enum pipe pipe = crtc->pipe;
1071 u32 temp;
1072
1073 temp = I915_READ(intel_hdmi->hdmi_reg);
1074
1075 temp |= SDVO_ENABLE;
1076 if (crtc->config->has_audio)
1077 temp |= SDVO_AUDIO_ENABLE;
1078
1079 /*
1080 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1081 *
1082 * The procedure for 12bpc is as follows:
1083 * 1. disable HDMI clock gating
1084 * 2. enable HDMI with 8bpc
1085 * 3. enable HDMI with 12bpc
1086 * 4. enable HDMI clock gating
1087 */
1088
1089 if (crtc->config->pipe_bpp > 24) {
1090 I915_WRITE(TRANS_CHICKEN1(pipe),
1091 I915_READ(TRANS_CHICKEN1(pipe)) |
1092 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1093
1094 temp &= ~SDVO_COLOR_FORMAT_MASK;
1095 temp |= SDVO_COLOR_FORMAT_8bpc;
1096 }
1097
1098 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1099 POSTING_READ(intel_hdmi->hdmi_reg);
1100
1101 if (crtc->config->pipe_bpp > 24) {
1102 temp &= ~SDVO_COLOR_FORMAT_MASK;
1103 temp |= HDMI_COLOR_FORMAT_12bpc;
1104
1105 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1106 POSTING_READ(intel_hdmi->hdmi_reg);
1107
1108 I915_WRITE(TRANS_CHICKEN1(pipe),
1109 I915_READ(TRANS_CHICKEN1(pipe)) &
1110 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1111 }
1112
1113 if (crtc->config->has_audio)
1114 intel_enable_hdmi_audio(encoder);
1115 }
1116
1117 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1118 struct intel_crtc_state *pipe_config,
1119 struct drm_connector_state *conn_state)
1120 {
1121 }
1122
1123 static void intel_disable_hdmi(struct intel_encoder *encoder,
1124 struct intel_crtc_state *old_crtc_state,
1125 struct drm_connector_state *old_conn_state)
1126 {
1127 struct drm_device *dev = encoder->base.dev;
1128 struct drm_i915_private *dev_priv = to_i915(dev);
1129 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1130 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1131 u32 temp;
1132
1133 temp = I915_READ(intel_hdmi->hdmi_reg);
1134
1135 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1136 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1137 POSTING_READ(intel_hdmi->hdmi_reg);
1138
1139 /*
1140 * HW workaround for IBX, we need to move the port
1141 * to transcoder A after disabling it to allow the
1142 * matching DP port to be enabled on transcoder A.
1143 */
1144 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
1145 /*
1146 * We get CPU/PCH FIFO underruns on the other pipe when
1147 * doing the workaround. Sweep them under the rug.
1148 */
1149 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1150 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1151
1152 temp &= ~SDVO_PIPE_B_SELECT;
1153 temp |= SDVO_ENABLE;
1154 /*
1155 * HW workaround, need to write this twice for issue
1156 * that may result in first write getting masked.
1157 */
1158 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1159 POSTING_READ(intel_hdmi->hdmi_reg);
1160 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1161 POSTING_READ(intel_hdmi->hdmi_reg);
1162
1163 temp &= ~SDVO_ENABLE;
1164 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1165 POSTING_READ(intel_hdmi->hdmi_reg);
1166
1167 intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A);
1168 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1169 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1170 }
1171
1172 intel_hdmi->set_infoframes(&encoder->base, false, NULL);
1173
1174 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1175 }
1176
1177 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1178 struct intel_crtc_state *old_crtc_state,
1179 struct drm_connector_state *old_conn_state)
1180 {
1181 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1182
1183 if (crtc->config->has_audio)
1184 intel_audio_codec_disable(encoder);
1185
1186 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1187 }
1188
1189 static void pch_disable_hdmi(struct intel_encoder *encoder,
1190 struct intel_crtc_state *old_crtc_state,
1191 struct drm_connector_state *old_conn_state)
1192 {
1193 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1194
1195 if (crtc->config->has_audio)
1196 intel_audio_codec_disable(encoder);
1197 }
1198
1199 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1200 struct intel_crtc_state *old_crtc_state,
1201 struct drm_connector_state *old_conn_state)
1202 {
1203 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1204 }
1205
1206 static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv)
1207 {
1208 if (IS_G4X(dev_priv))
1209 return 165000;
1210 else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
1211 return 300000;
1212 else
1213 return 225000;
1214 }
1215
1216 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1217 bool respect_downstream_limits)
1218 {
1219 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1220 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));
1221
1222 if (respect_downstream_limits) {
1223 struct intel_connector *connector = hdmi->attached_connector;
1224 const struct drm_display_info *info = &connector->base.display_info;
1225
1226 if (hdmi->dp_dual_mode.max_tmds_clock)
1227 max_tmds_clock = min(max_tmds_clock,
1228 hdmi->dp_dual_mode.max_tmds_clock);
1229
1230 if (info->max_tmds_clock)
1231 max_tmds_clock = min(max_tmds_clock,
1232 info->max_tmds_clock);
1233 else if (!hdmi->has_hdmi_sink)
1234 max_tmds_clock = min(max_tmds_clock, 165000);
1235 }
1236
1237 return max_tmds_clock;
1238 }
1239
1240 static enum drm_mode_status
1241 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1242 int clock, bool respect_downstream_limits)
1243 {
1244 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1245
1246 if (clock < 25000)
1247 return MODE_CLOCK_LOW;
1248 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits))
1249 return MODE_CLOCK_HIGH;
1250
1251 /* BXT DPLL can't generate 223-240 MHz */
1252 if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
1253 return MODE_CLOCK_RANGE;
1254
1255 /* CHV DPLL can't generate 216-240 MHz */
1256 if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
1257 return MODE_CLOCK_RANGE;
1258
1259 return MODE_OK;
1260 }
1261
1262 static enum drm_mode_status
1263 intel_hdmi_mode_valid(struct drm_connector *connector,
1264 struct drm_display_mode *mode)
1265 {
1266 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1267 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1268 enum drm_mode_status status;
1269 int clock;
1270 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1271
1272 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1273 return MODE_NO_DBLESCAN;
1274
1275 clock = mode->clock;
1276
1277 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1278 clock *= 2;
1279
1280 if (clock > max_dotclk)
1281 return MODE_CLOCK_HIGH;
1282
1283 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1284 clock *= 2;
1285
1286 /* check if we can do 8bpc */
1287 status = hdmi_port_clock_valid(hdmi, clock, true);
1288
1289 /* if we can't do 8bpc we may still be able to do 12bpc */
1290 if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
1291 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
1292
1293 return status;
1294 }
1295
1296 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1297 {
1298 struct drm_device *dev = crtc_state->base.crtc->dev;
1299
1300 if (HAS_GMCH_DISPLAY(dev))
1301 return false;
1302
1303 /*
1304 * HDMI 12bpc affects the clocks, so it's only possible
1305 * when not cloning with other encoder types.
1306 */
1307 return crtc_state->output_types == 1 << INTEL_OUTPUT_HDMI;
1308 }
1309
1310 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1311 struct intel_crtc_state *pipe_config,
1312 struct drm_connector_state *conn_state)
1313 {
1314 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1315 struct drm_device *dev = encoder->base.dev;
1316 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1317 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1318 int clock_12bpc = clock_8bpc * 3 / 2;
1319 int desired_bpp;
1320
1321 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1322
1323 if (pipe_config->has_hdmi_sink)
1324 pipe_config->has_infoframe = true;
1325
1326 if (intel_hdmi->color_range_auto) {
1327 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1328 pipe_config->limited_color_range =
1329 pipe_config->has_hdmi_sink &&
1330 drm_match_cea_mode(adjusted_mode) > 1;
1331 } else {
1332 pipe_config->limited_color_range =
1333 intel_hdmi->limited_color_range;
1334 }
1335
1336 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1337 pipe_config->pixel_multiplier = 2;
1338 clock_8bpc *= 2;
1339 clock_12bpc *= 2;
1340 }
1341
1342 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1343 pipe_config->has_pch_encoder = true;
1344
1345 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1346 pipe_config->has_audio = true;
1347
1348 /*
1349 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1350 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1351 * outputs. We also need to check that the higher clock still fits
1352 * within limits.
1353 */
1354 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1355 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true) == MODE_OK &&
1356 hdmi_12bpc_possible(pipe_config)) {
1357 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1358 desired_bpp = 12*3;
1359
1360 /* Need to adjust the port link by 1.5x for 12bpc. */
1361 pipe_config->port_clock = clock_12bpc;
1362 } else {
1363 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1364 desired_bpp = 8*3;
1365
1366 pipe_config->port_clock = clock_8bpc;
1367 }
1368
1369 if (!pipe_config->bw_constrained) {
1370 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1371 pipe_config->pipe_bpp = desired_bpp;
1372 }
1373
1374 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1375 false) != MODE_OK) {
1376 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1377 return false;
1378 }
1379
1380 /* Set user selected PAR to incoming mode's member */
1381 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
1382
1383 pipe_config->lane_count = 4;
1384
1385 return true;
1386 }
1387
1388 static void
1389 intel_hdmi_unset_edid(struct drm_connector *connector)
1390 {
1391 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1392
1393 intel_hdmi->has_hdmi_sink = false;
1394 intel_hdmi->has_audio = false;
1395 intel_hdmi->rgb_quant_range_selectable = false;
1396
1397 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1398 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1399
1400 kfree(to_intel_connector(connector)->detect_edid);
1401 to_intel_connector(connector)->detect_edid = NULL;
1402 }
1403
1404 static void
1405 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1406 {
1407 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1408 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1409 enum port port = hdmi_to_dig_port(hdmi)->port;
1410 struct i2c_adapter *adapter =
1411 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1412 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1413
1414 /*
1415 * Type 1 DVI adaptors are not required to implement any
1416 * registers, so we can't always detect their presence.
1417 * Ideally we should be able to check the state of the
1418 * CONFIG1 pin, but no such luck on our hardware.
1419 *
1420 * The only method left to us is to check the VBT to see
1421 * if the port is a dual mode capable DP port. But let's
1422 * only do that when we sucesfully read the EDID, to avoid
1423 * confusing log messages about DP dual mode adaptors when
1424 * there's nothing connected to the port.
1425 */
1426 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1427 if (has_edid &&
1428 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1429 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1430 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1431 } else {
1432 type = DRM_DP_DUAL_MODE_NONE;
1433 }
1434 }
1435
1436 if (type == DRM_DP_DUAL_MODE_NONE)
1437 return;
1438
1439 hdmi->dp_dual_mode.type = type;
1440 hdmi->dp_dual_mode.max_tmds_clock =
1441 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1442
1443 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1444 drm_dp_get_dual_mode_type_name(type),
1445 hdmi->dp_dual_mode.max_tmds_clock);
1446 }
1447
1448 static bool
1449 intel_hdmi_set_edid(struct drm_connector *connector)
1450 {
1451 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1452 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1453 struct edid *edid;
1454 bool connected = false;
1455
1456 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1457
1458 edid = drm_get_edid(connector,
1459 intel_gmbus_get_adapter(dev_priv,
1460 intel_hdmi->ddc_bus));
1461
1462 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1463
1464 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1465
1466 to_intel_connector(connector)->detect_edid = edid;
1467 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1468 intel_hdmi->rgb_quant_range_selectable =
1469 drm_rgb_quant_range_selectable(edid);
1470
1471 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1472 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1473 intel_hdmi->has_audio =
1474 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1475
1476 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1477 intel_hdmi->has_hdmi_sink =
1478 drm_detect_hdmi_monitor(edid);
1479
1480 connected = true;
1481 }
1482
1483 return connected;
1484 }
1485
1486 static enum drm_connector_status
1487 intel_hdmi_detect(struct drm_connector *connector, bool force)
1488 {
1489 enum drm_connector_status status;
1490 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1491
1492 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1493 connector->base.id, connector->name);
1494
1495 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1496
1497 intel_hdmi_unset_edid(connector);
1498
1499 if (intel_hdmi_set_edid(connector)) {
1500 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1501
1502 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1503 status = connector_status_connected;
1504 } else
1505 status = connector_status_disconnected;
1506
1507 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1508
1509 return status;
1510 }
1511
1512 static void
1513 intel_hdmi_force(struct drm_connector *connector)
1514 {
1515 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1516
1517 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1518 connector->base.id, connector->name);
1519
1520 intel_hdmi_unset_edid(connector);
1521
1522 if (connector->status != connector_status_connected)
1523 return;
1524
1525 intel_hdmi_set_edid(connector);
1526 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1527 }
1528
1529 static int intel_hdmi_get_modes(struct drm_connector *connector)
1530 {
1531 struct edid *edid;
1532
1533 edid = to_intel_connector(connector)->detect_edid;
1534 if (edid == NULL)
1535 return 0;
1536
1537 return intel_connector_update_modes(connector, edid);
1538 }
1539
1540 static bool
1541 intel_hdmi_detect_audio(struct drm_connector *connector)
1542 {
1543 bool has_audio = false;
1544 struct edid *edid;
1545
1546 edid = to_intel_connector(connector)->detect_edid;
1547 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1548 has_audio = drm_detect_monitor_audio(edid);
1549
1550 return has_audio;
1551 }
1552
1553 static int
1554 intel_hdmi_set_property(struct drm_connector *connector,
1555 struct drm_property *property,
1556 uint64_t val)
1557 {
1558 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1559 struct intel_digital_port *intel_dig_port =
1560 hdmi_to_dig_port(intel_hdmi);
1561 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1562 int ret;
1563
1564 ret = drm_object_property_set_value(&connector->base, property, val);
1565 if (ret)
1566 return ret;
1567
1568 if (property == dev_priv->force_audio_property) {
1569 enum hdmi_force_audio i = val;
1570 bool has_audio;
1571
1572 if (i == intel_hdmi->force_audio)
1573 return 0;
1574
1575 intel_hdmi->force_audio = i;
1576
1577 if (i == HDMI_AUDIO_AUTO)
1578 has_audio = intel_hdmi_detect_audio(connector);
1579 else
1580 has_audio = (i == HDMI_AUDIO_ON);
1581
1582 if (i == HDMI_AUDIO_OFF_DVI)
1583 intel_hdmi->has_hdmi_sink = 0;
1584
1585 intel_hdmi->has_audio = has_audio;
1586 goto done;
1587 }
1588
1589 if (property == dev_priv->broadcast_rgb_property) {
1590 bool old_auto = intel_hdmi->color_range_auto;
1591 bool old_range = intel_hdmi->limited_color_range;
1592
1593 switch (val) {
1594 case INTEL_BROADCAST_RGB_AUTO:
1595 intel_hdmi->color_range_auto = true;
1596 break;
1597 case INTEL_BROADCAST_RGB_FULL:
1598 intel_hdmi->color_range_auto = false;
1599 intel_hdmi->limited_color_range = false;
1600 break;
1601 case INTEL_BROADCAST_RGB_LIMITED:
1602 intel_hdmi->color_range_auto = false;
1603 intel_hdmi->limited_color_range = true;
1604 break;
1605 default:
1606 return -EINVAL;
1607 }
1608
1609 if (old_auto == intel_hdmi->color_range_auto &&
1610 old_range == intel_hdmi->limited_color_range)
1611 return 0;
1612
1613 goto done;
1614 }
1615
1616 if (property == connector->dev->mode_config.aspect_ratio_property) {
1617 switch (val) {
1618 case DRM_MODE_PICTURE_ASPECT_NONE:
1619 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1620 break;
1621 case DRM_MODE_PICTURE_ASPECT_4_3:
1622 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1623 break;
1624 case DRM_MODE_PICTURE_ASPECT_16_9:
1625 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1626 break;
1627 default:
1628 return -EINVAL;
1629 }
1630 goto done;
1631 }
1632
1633 return -EINVAL;
1634
1635 done:
1636 if (intel_dig_port->base.base.crtc)
1637 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1638
1639 return 0;
1640 }
1641
1642 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1643 struct intel_crtc_state *pipe_config,
1644 struct drm_connector_state *conn_state)
1645 {
1646 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1647 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1648 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1649
1650 intel_hdmi_prepare(encoder);
1651
1652 intel_hdmi->set_infoframes(&encoder->base,
1653 intel_crtc->config->has_hdmi_sink,
1654 adjusted_mode);
1655 }
1656
1657 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1658 struct intel_crtc_state *pipe_config,
1659 struct drm_connector_state *conn_state)
1660 {
1661 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1662 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1663 struct drm_device *dev = encoder->base.dev;
1664 struct drm_i915_private *dev_priv = to_i915(dev);
1665 struct intel_crtc *intel_crtc =
1666 to_intel_crtc(encoder->base.crtc);
1667 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1668
1669 vlv_phy_pre_encoder_enable(encoder);
1670
1671 /* HDMI 1.0V-2dB */
1672 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
1673 0x2b247878);
1674
1675 intel_hdmi->set_infoframes(&encoder->base,
1676 intel_crtc->config->has_hdmi_sink,
1677 adjusted_mode);
1678
1679 g4x_enable_hdmi(encoder, pipe_config, conn_state);
1680
1681 vlv_wait_port_ready(dev_priv, dport, 0x0);
1682 }
1683
1684 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1685 struct intel_crtc_state *pipe_config,
1686 struct drm_connector_state *conn_state)
1687 {
1688 intel_hdmi_prepare(encoder);
1689
1690 vlv_phy_pre_pll_enable(encoder);
1691 }
1692
1693 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1694 struct intel_crtc_state *pipe_config,
1695 struct drm_connector_state *conn_state)
1696 {
1697 intel_hdmi_prepare(encoder);
1698
1699 chv_phy_pre_pll_enable(encoder);
1700 }
1701
1702 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
1703 struct intel_crtc_state *old_crtc_state,
1704 struct drm_connector_state *old_conn_state)
1705 {
1706 chv_phy_post_pll_disable(encoder);
1707 }
1708
1709 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
1710 struct intel_crtc_state *old_crtc_state,
1711 struct drm_connector_state *old_conn_state)
1712 {
1713 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1714 vlv_phy_reset_lanes(encoder);
1715 }
1716
1717 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
1718 struct intel_crtc_state *old_crtc_state,
1719 struct drm_connector_state *old_conn_state)
1720 {
1721 struct drm_device *dev = encoder->base.dev;
1722 struct drm_i915_private *dev_priv = to_i915(dev);
1723
1724 mutex_lock(&dev_priv->sb_lock);
1725
1726 /* Assert data lane reset */
1727 chv_data_lane_soft_reset(encoder, true);
1728
1729 mutex_unlock(&dev_priv->sb_lock);
1730 }
1731
1732 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
1733 struct intel_crtc_state *pipe_config,
1734 struct drm_connector_state *conn_state)
1735 {
1736 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1737 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1738 struct drm_device *dev = encoder->base.dev;
1739 struct drm_i915_private *dev_priv = to_i915(dev);
1740 struct intel_crtc *intel_crtc =
1741 to_intel_crtc(encoder->base.crtc);
1742 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1743
1744 chv_phy_pre_encoder_enable(encoder);
1745
1746 /* FIXME: Program the support xxx V-dB */
1747 /* Use 800mV-0dB */
1748 chv_set_phy_signal_level(encoder, 128, 102, false);
1749
1750 intel_hdmi->set_infoframes(&encoder->base,
1751 intel_crtc->config->has_hdmi_sink,
1752 adjusted_mode);
1753
1754 g4x_enable_hdmi(encoder, pipe_config, conn_state);
1755
1756 vlv_wait_port_ready(dev_priv, dport, 0x0);
1757
1758 /* Second common lane will stay alive on its own now */
1759 chv_phy_release_cl2_override(encoder);
1760 }
1761
1762 static void intel_hdmi_destroy(struct drm_connector *connector)
1763 {
1764 kfree(to_intel_connector(connector)->detect_edid);
1765 drm_connector_cleanup(connector);
1766 kfree(connector);
1767 }
1768
1769 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1770 .dpms = drm_atomic_helper_connector_dpms,
1771 .detect = intel_hdmi_detect,
1772 .force = intel_hdmi_force,
1773 .fill_modes = drm_helper_probe_single_connector_modes,
1774 .set_property = intel_hdmi_set_property,
1775 .atomic_get_property = intel_connector_atomic_get_property,
1776 .late_register = intel_connector_register,
1777 .early_unregister = intel_connector_unregister,
1778 .destroy = intel_hdmi_destroy,
1779 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1780 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1781 };
1782
1783 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1784 .get_modes = intel_hdmi_get_modes,
1785 .mode_valid = intel_hdmi_mode_valid,
1786 };
1787
1788 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1789 .destroy = intel_encoder_destroy,
1790 };
1791
1792 static void
1793 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1794 {
1795 intel_attach_force_audio_property(connector);
1796 intel_attach_broadcast_rgb_property(connector);
1797 intel_hdmi->color_range_auto = true;
1798 intel_attach_aspect_ratio_property(connector);
1799 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1800 }
1801
1802 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1803 struct intel_connector *intel_connector)
1804 {
1805 struct drm_connector *connector = &intel_connector->base;
1806 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1807 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1808 struct drm_device *dev = intel_encoder->base.dev;
1809 struct drm_i915_private *dev_priv = to_i915(dev);
1810 enum port port = intel_dig_port->port;
1811 uint8_t alternate_ddc_pin;
1812
1813 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
1814 port_name(port));
1815
1816 if (WARN(intel_dig_port->max_lanes < 4,
1817 "Not enough lanes (%d) for HDMI on port %c\n",
1818 intel_dig_port->max_lanes, port_name(port)))
1819 return;
1820
1821 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1822 DRM_MODE_CONNECTOR_HDMIA);
1823 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1824
1825 connector->interlace_allowed = 1;
1826 connector->doublescan_allowed = 0;
1827 connector->stereo_allowed = 1;
1828
1829 switch (port) {
1830 case PORT_B:
1831 if (IS_BROXTON(dev_priv))
1832 intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
1833 else
1834 intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
1835 /*
1836 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
1837 * interrupts to check the external panel connection.
1838 */
1839 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
1840 intel_encoder->hpd_pin = HPD_PORT_A;
1841 else
1842 intel_encoder->hpd_pin = HPD_PORT_B;
1843 break;
1844 case PORT_C:
1845 if (IS_BROXTON(dev_priv))
1846 intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
1847 else
1848 intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
1849 intel_encoder->hpd_pin = HPD_PORT_C;
1850 break;
1851 case PORT_D:
1852 if (WARN_ON(IS_BROXTON(dev_priv)))
1853 intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
1854 else if (IS_CHERRYVIEW(dev_priv))
1855 intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
1856 else
1857 intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
1858 intel_encoder->hpd_pin = HPD_PORT_D;
1859 break;
1860 case PORT_E:
1861 /* On SKL PORT E doesn't have seperate GMBUS pin
1862 * We rely on VBT to set a proper alternate GMBUS pin. */
1863 alternate_ddc_pin =
1864 dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin;
1865 switch (alternate_ddc_pin) {
1866 case DDC_PIN_B:
1867 intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
1868 break;
1869 case DDC_PIN_C:
1870 intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
1871 break;
1872 case DDC_PIN_D:
1873 intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
1874 break;
1875 default:
1876 MISSING_CASE(alternate_ddc_pin);
1877 }
1878 intel_encoder->hpd_pin = HPD_PORT_E;
1879 break;
1880 case PORT_A:
1881 intel_encoder->hpd_pin = HPD_PORT_A;
1882 /* Internal port only for eDP. */
1883 default:
1884 BUG();
1885 }
1886
1887 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1888 intel_hdmi->write_infoframe = vlv_write_infoframe;
1889 intel_hdmi->set_infoframes = vlv_set_infoframes;
1890 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
1891 } else if (IS_G4X(dev)) {
1892 intel_hdmi->write_infoframe = g4x_write_infoframe;
1893 intel_hdmi->set_infoframes = g4x_set_infoframes;
1894 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
1895 } else if (HAS_DDI(dev)) {
1896 intel_hdmi->write_infoframe = hsw_write_infoframe;
1897 intel_hdmi->set_infoframes = hsw_set_infoframes;
1898 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
1899 } else if (HAS_PCH_IBX(dev)) {
1900 intel_hdmi->write_infoframe = ibx_write_infoframe;
1901 intel_hdmi->set_infoframes = ibx_set_infoframes;
1902 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
1903 } else {
1904 intel_hdmi->write_infoframe = cpt_write_infoframe;
1905 intel_hdmi->set_infoframes = cpt_set_infoframes;
1906 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
1907 }
1908
1909 if (HAS_DDI(dev))
1910 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1911 else
1912 intel_connector->get_hw_state = intel_connector_get_hw_state;
1913
1914 intel_hdmi_add_properties(intel_hdmi, connector);
1915
1916 intel_connector_attach_encoder(intel_connector, intel_encoder);
1917 intel_hdmi->attached_connector = intel_connector;
1918
1919 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1920 * 0xd. Failure to do so will result in spurious interrupts being
1921 * generated on the port when a cable is not attached.
1922 */
1923 if (IS_G4X(dev) && !IS_GM45(dev)) {
1924 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1925 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1926 }
1927 }
1928
1929 void intel_hdmi_init(struct drm_device *dev,
1930 i915_reg_t hdmi_reg, enum port port)
1931 {
1932 struct intel_digital_port *intel_dig_port;
1933 struct intel_encoder *intel_encoder;
1934 struct intel_connector *intel_connector;
1935
1936 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1937 if (!intel_dig_port)
1938 return;
1939
1940 intel_connector = intel_connector_alloc();
1941 if (!intel_connector) {
1942 kfree(intel_dig_port);
1943 return;
1944 }
1945
1946 intel_encoder = &intel_dig_port->base;
1947
1948 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1949 DRM_MODE_ENCODER_TMDS, "HDMI %c", port_name(port));
1950
1951 intel_encoder->compute_config = intel_hdmi_compute_config;
1952 if (HAS_PCH_SPLIT(dev)) {
1953 intel_encoder->disable = pch_disable_hdmi;
1954 intel_encoder->post_disable = pch_post_disable_hdmi;
1955 } else {
1956 intel_encoder->disable = g4x_disable_hdmi;
1957 }
1958 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1959 intel_encoder->get_config = intel_hdmi_get_config;
1960 if (IS_CHERRYVIEW(dev)) {
1961 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
1962 intel_encoder->pre_enable = chv_hdmi_pre_enable;
1963 intel_encoder->enable = vlv_enable_hdmi;
1964 intel_encoder->post_disable = chv_hdmi_post_disable;
1965 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
1966 } else if (IS_VALLEYVIEW(dev)) {
1967 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1968 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1969 intel_encoder->enable = vlv_enable_hdmi;
1970 intel_encoder->post_disable = vlv_hdmi_post_disable;
1971 } else {
1972 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1973 if (HAS_PCH_CPT(dev))
1974 intel_encoder->enable = cpt_enable_hdmi;
1975 else if (HAS_PCH_IBX(dev))
1976 intel_encoder->enable = ibx_enable_hdmi;
1977 else
1978 intel_encoder->enable = g4x_enable_hdmi;
1979 }
1980
1981 intel_encoder->type = INTEL_OUTPUT_HDMI;
1982 intel_encoder->port = port;
1983 if (IS_CHERRYVIEW(dev)) {
1984 if (port == PORT_D)
1985 intel_encoder->crtc_mask = 1 << 2;
1986 else
1987 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1988 } else {
1989 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1990 }
1991 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
1992 /*
1993 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1994 * to work on real hardware. And since g4x can send infoframes to
1995 * only one port anyway, nothing is lost by allowing it.
1996 */
1997 if (IS_G4X(dev))
1998 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
1999
2000 intel_dig_port->port = port;
2001 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2002 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2003 intel_dig_port->max_lanes = 4;
2004
2005 intel_hdmi_init_connector(intel_dig_port, intel_connector);
2006 }
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