2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/delay.h>
30 #include <linux/hdmi.h>
31 #include <linux/i2c.h>
32 #include <linux/slab.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_hdcp.h>
38 #include <drm/drm_scdc_helper.h>
39 #include <drm/i915_drm.h>
40 #include <drm/intel_lpe_audio.h>
42 #include "i915_debugfs.h"
44 #include "intel_atomic.h"
45 #include "intel_audio.h"
46 #include "intel_connector.h"
47 #include "intel_ddi.h"
49 #include "intel_dpio_phy.h"
50 #include "intel_drv.h"
51 #include "intel_fifo_underrun.h"
52 #include "intel_gmbus.h"
53 #include "intel_hdcp.h"
54 #include "intel_hdmi.h"
55 #include "intel_hotplug.h"
56 #include "intel_lspcon.h"
57 #include "intel_sdvo.h"
58 #include "intel_panel.h"
59 #include "intel_sideband.h"
61 static struct drm_device
*intel_hdmi_to_dev(struct intel_hdmi
*intel_hdmi
)
63 return hdmi_to_dig_port(intel_hdmi
)->base
.base
.dev
;
67 assert_hdmi_port_disabled(struct intel_hdmi
*intel_hdmi
)
69 struct drm_device
*dev
= intel_hdmi_to_dev(intel_hdmi
);
70 struct drm_i915_private
*dev_priv
= to_i915(dev
);
73 enabled_bits
= HAS_DDI(dev_priv
) ? DDI_BUF_CTL_ENABLE
: SDVO_ENABLE
;
75 WARN(I915_READ(intel_hdmi
->hdmi_reg
) & enabled_bits
,
76 "HDMI port enabled, expecting disabled\n");
80 assert_hdmi_transcoder_func_disabled(struct drm_i915_private
*dev_priv
,
81 enum transcoder cpu_transcoder
)
83 WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
)) &
84 TRANS_DDI_FUNC_ENABLE
,
85 "HDMI transcoder function enabled, expecting disabled\n");
88 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
)
90 struct intel_digital_port
*intel_dig_port
=
91 container_of(encoder
, struct intel_digital_port
, base
.base
);
92 return &intel_dig_port
->hdmi
;
95 static struct intel_hdmi
*intel_attached_hdmi(struct drm_connector
*connector
)
97 return enc_to_intel_hdmi(&intel_attached_encoder(connector
)->base
);
100 static u32
g4x_infoframe_index(unsigned int type
)
103 case HDMI_PACKET_TYPE_GAMUT_METADATA
:
104 return VIDEO_DIP_SELECT_GAMUT
;
105 case HDMI_INFOFRAME_TYPE_AVI
:
106 return VIDEO_DIP_SELECT_AVI
;
107 case HDMI_INFOFRAME_TYPE_SPD
:
108 return VIDEO_DIP_SELECT_SPD
;
109 case HDMI_INFOFRAME_TYPE_VENDOR
:
110 return VIDEO_DIP_SELECT_VENDOR
;
117 static u32
g4x_infoframe_enable(unsigned int type
)
120 case HDMI_PACKET_TYPE_GENERAL_CONTROL
:
121 return VIDEO_DIP_ENABLE_GCP
;
122 case HDMI_PACKET_TYPE_GAMUT_METADATA
:
123 return VIDEO_DIP_ENABLE_GAMUT
;
126 case HDMI_INFOFRAME_TYPE_AVI
:
127 return VIDEO_DIP_ENABLE_AVI
;
128 case HDMI_INFOFRAME_TYPE_SPD
:
129 return VIDEO_DIP_ENABLE_SPD
;
130 case HDMI_INFOFRAME_TYPE_VENDOR
:
131 return VIDEO_DIP_ENABLE_VENDOR
;
138 static u32
hsw_infoframe_enable(unsigned int type
)
141 case HDMI_PACKET_TYPE_GENERAL_CONTROL
:
142 return VIDEO_DIP_ENABLE_GCP_HSW
;
143 case HDMI_PACKET_TYPE_GAMUT_METADATA
:
144 return VIDEO_DIP_ENABLE_GMP_HSW
;
146 return VIDEO_DIP_ENABLE_VSC_HSW
;
148 return VDIP_ENABLE_PPS
;
149 case HDMI_INFOFRAME_TYPE_AVI
:
150 return VIDEO_DIP_ENABLE_AVI_HSW
;
151 case HDMI_INFOFRAME_TYPE_SPD
:
152 return VIDEO_DIP_ENABLE_SPD_HSW
;
153 case HDMI_INFOFRAME_TYPE_VENDOR
:
154 return VIDEO_DIP_ENABLE_VS_HSW
;
162 hsw_dip_data_reg(struct drm_i915_private
*dev_priv
,
163 enum transcoder cpu_transcoder
,
168 case HDMI_PACKET_TYPE_GAMUT_METADATA
:
169 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder
, i
);
171 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder
, i
);
173 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder
, i
);
174 case HDMI_INFOFRAME_TYPE_AVI
:
175 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder
, i
);
176 case HDMI_INFOFRAME_TYPE_SPD
:
177 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder
, i
);
178 case HDMI_INFOFRAME_TYPE_VENDOR
:
179 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder
, i
);
182 return INVALID_MMIO_REG
;
186 static int hsw_dip_data_size(unsigned int type
)
190 return VIDEO_DIP_VSC_DATA_SIZE
;
192 return VIDEO_DIP_PPS_DATA_SIZE
;
194 return VIDEO_DIP_DATA_SIZE
;
198 static void g4x_write_infoframe(struct intel_encoder
*encoder
,
199 const struct intel_crtc_state
*crtc_state
,
201 const void *frame
, ssize_t len
)
203 const u32
*data
= frame
;
204 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
205 u32 val
= I915_READ(VIDEO_DIP_CTL
);
208 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
210 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
211 val
|= g4x_infoframe_index(type
);
213 val
&= ~g4x_infoframe_enable(type
);
215 I915_WRITE(VIDEO_DIP_CTL
, val
);
217 for (i
= 0; i
< len
; i
+= 4) {
218 I915_WRITE(VIDEO_DIP_DATA
, *data
);
221 /* Write every possible data byte to force correct ECC calculation. */
222 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
223 I915_WRITE(VIDEO_DIP_DATA
, 0);
225 val
|= g4x_infoframe_enable(type
);
226 val
&= ~VIDEO_DIP_FREQ_MASK
;
227 val
|= VIDEO_DIP_FREQ_VSYNC
;
229 I915_WRITE(VIDEO_DIP_CTL
, val
);
230 POSTING_READ(VIDEO_DIP_CTL
);
233 static void g4x_read_infoframe(struct intel_encoder
*encoder
,
234 const struct intel_crtc_state
*crtc_state
,
236 void *frame
, ssize_t len
)
238 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
239 u32 val
, *data
= frame
;
242 val
= I915_READ(VIDEO_DIP_CTL
);
244 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
245 val
|= g4x_infoframe_index(type
);
247 I915_WRITE(VIDEO_DIP_CTL
, val
);
249 for (i
= 0; i
< len
; i
+= 4)
250 *data
++ = I915_READ(VIDEO_DIP_DATA
);
253 static u32
g4x_infoframes_enabled(struct intel_encoder
*encoder
,
254 const struct intel_crtc_state
*pipe_config
)
256 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
257 u32 val
= I915_READ(VIDEO_DIP_CTL
);
259 if ((val
& VIDEO_DIP_ENABLE
) == 0)
262 if ((val
& VIDEO_DIP_PORT_MASK
) != VIDEO_DIP_PORT(encoder
->port
))
265 return val
& (VIDEO_DIP_ENABLE_AVI
|
266 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_SPD
);
269 static void ibx_write_infoframe(struct intel_encoder
*encoder
,
270 const struct intel_crtc_state
*crtc_state
,
272 const void *frame
, ssize_t len
)
274 const u32
*data
= frame
;
275 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
276 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
277 i915_reg_t reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
278 u32 val
= I915_READ(reg
);
281 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
283 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
284 val
|= g4x_infoframe_index(type
);
286 val
&= ~g4x_infoframe_enable(type
);
288 I915_WRITE(reg
, val
);
290 for (i
= 0; i
< len
; i
+= 4) {
291 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
294 /* Write every possible data byte to force correct ECC calculation. */
295 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
296 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
298 val
|= g4x_infoframe_enable(type
);
299 val
&= ~VIDEO_DIP_FREQ_MASK
;
300 val
|= VIDEO_DIP_FREQ_VSYNC
;
302 I915_WRITE(reg
, val
);
306 static void ibx_read_infoframe(struct intel_encoder
*encoder
,
307 const struct intel_crtc_state
*crtc_state
,
309 void *frame
, ssize_t len
)
311 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
312 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
313 u32 val
, *data
= frame
;
316 val
= I915_READ(TVIDEO_DIP_CTL(crtc
->pipe
));
318 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
319 val
|= g4x_infoframe_index(type
);
321 I915_WRITE(TVIDEO_DIP_CTL(crtc
->pipe
), val
);
323 for (i
= 0; i
< len
; i
+= 4)
324 *data
++ = I915_READ(TVIDEO_DIP_DATA(crtc
->pipe
));
327 static u32
ibx_infoframes_enabled(struct intel_encoder
*encoder
,
328 const struct intel_crtc_state
*pipe_config
)
330 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
331 enum pipe pipe
= to_intel_crtc(pipe_config
->base
.crtc
)->pipe
;
332 i915_reg_t reg
= TVIDEO_DIP_CTL(pipe
);
333 u32 val
= I915_READ(reg
);
335 if ((val
& VIDEO_DIP_ENABLE
) == 0)
338 if ((val
& VIDEO_DIP_PORT_MASK
) != VIDEO_DIP_PORT(encoder
->port
))
341 return val
& (VIDEO_DIP_ENABLE_AVI
|
342 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
343 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
346 static void cpt_write_infoframe(struct intel_encoder
*encoder
,
347 const struct intel_crtc_state
*crtc_state
,
349 const void *frame
, ssize_t len
)
351 const u32
*data
= frame
;
352 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
353 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
354 i915_reg_t reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
355 u32 val
= I915_READ(reg
);
358 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
360 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
361 val
|= g4x_infoframe_index(type
);
363 /* The DIP control register spec says that we need to update the AVI
364 * infoframe without clearing its enable bit */
365 if (type
!= HDMI_INFOFRAME_TYPE_AVI
)
366 val
&= ~g4x_infoframe_enable(type
);
368 I915_WRITE(reg
, val
);
370 for (i
= 0; i
< len
; i
+= 4) {
371 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
374 /* Write every possible data byte to force correct ECC calculation. */
375 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
376 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
378 val
|= g4x_infoframe_enable(type
);
379 val
&= ~VIDEO_DIP_FREQ_MASK
;
380 val
|= VIDEO_DIP_FREQ_VSYNC
;
382 I915_WRITE(reg
, val
);
386 static void cpt_read_infoframe(struct intel_encoder
*encoder
,
387 const struct intel_crtc_state
*crtc_state
,
389 void *frame
, ssize_t len
)
391 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
392 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
393 u32 val
, *data
= frame
;
396 val
= I915_READ(TVIDEO_DIP_CTL(crtc
->pipe
));
398 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
399 val
|= g4x_infoframe_index(type
);
401 I915_WRITE(TVIDEO_DIP_CTL(crtc
->pipe
), val
);
403 for (i
= 0; i
< len
; i
+= 4)
404 *data
++ = I915_READ(TVIDEO_DIP_DATA(crtc
->pipe
));
407 static u32
cpt_infoframes_enabled(struct intel_encoder
*encoder
,
408 const struct intel_crtc_state
*pipe_config
)
410 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
411 enum pipe pipe
= to_intel_crtc(pipe_config
->base
.crtc
)->pipe
;
412 u32 val
= I915_READ(TVIDEO_DIP_CTL(pipe
));
414 if ((val
& VIDEO_DIP_ENABLE
) == 0)
417 return val
& (VIDEO_DIP_ENABLE_AVI
|
418 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
419 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
422 static void vlv_write_infoframe(struct intel_encoder
*encoder
,
423 const struct intel_crtc_state
*crtc_state
,
425 const void *frame
, ssize_t len
)
427 const u32
*data
= frame
;
428 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
429 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
430 i915_reg_t reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
431 u32 val
= I915_READ(reg
);
434 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
436 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
437 val
|= g4x_infoframe_index(type
);
439 val
&= ~g4x_infoframe_enable(type
);
441 I915_WRITE(reg
, val
);
443 for (i
= 0; i
< len
; i
+= 4) {
444 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
447 /* Write every possible data byte to force correct ECC calculation. */
448 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
449 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
451 val
|= g4x_infoframe_enable(type
);
452 val
&= ~VIDEO_DIP_FREQ_MASK
;
453 val
|= VIDEO_DIP_FREQ_VSYNC
;
455 I915_WRITE(reg
, val
);
459 static void vlv_read_infoframe(struct intel_encoder
*encoder
,
460 const struct intel_crtc_state
*crtc_state
,
462 void *frame
, ssize_t len
)
464 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
465 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
466 u32 val
, *data
= frame
;
469 val
= I915_READ(VLV_TVIDEO_DIP_CTL(crtc
->pipe
));
471 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
472 val
|= g4x_infoframe_index(type
);
474 I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc
->pipe
), val
);
476 for (i
= 0; i
< len
; i
+= 4)
477 *data
++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc
->pipe
));
480 static u32
vlv_infoframes_enabled(struct intel_encoder
*encoder
,
481 const struct intel_crtc_state
*pipe_config
)
483 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
484 enum pipe pipe
= to_intel_crtc(pipe_config
->base
.crtc
)->pipe
;
485 u32 val
= I915_READ(VLV_TVIDEO_DIP_CTL(pipe
));
487 if ((val
& VIDEO_DIP_ENABLE
) == 0)
490 if ((val
& VIDEO_DIP_PORT_MASK
) != VIDEO_DIP_PORT(encoder
->port
))
493 return val
& (VIDEO_DIP_ENABLE_AVI
|
494 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
495 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
498 static void hsw_write_infoframe(struct intel_encoder
*encoder
,
499 const struct intel_crtc_state
*crtc_state
,
501 const void *frame
, ssize_t len
)
503 const u32
*data
= frame
;
504 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
505 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
506 i915_reg_t ctl_reg
= HSW_TVIDEO_DIP_CTL(cpu_transcoder
);
509 u32 val
= I915_READ(ctl_reg
);
511 data_size
= hsw_dip_data_size(type
);
513 val
&= ~hsw_infoframe_enable(type
);
514 I915_WRITE(ctl_reg
, val
);
516 for (i
= 0; i
< len
; i
+= 4) {
517 I915_WRITE(hsw_dip_data_reg(dev_priv
, cpu_transcoder
,
518 type
, i
>> 2), *data
);
521 /* Write every possible data byte to force correct ECC calculation. */
522 for (; i
< data_size
; i
+= 4)
523 I915_WRITE(hsw_dip_data_reg(dev_priv
, cpu_transcoder
,
526 val
|= hsw_infoframe_enable(type
);
527 I915_WRITE(ctl_reg
, val
);
528 POSTING_READ(ctl_reg
);
531 static void hsw_read_infoframe(struct intel_encoder
*encoder
,
532 const struct intel_crtc_state
*crtc_state
,
534 void *frame
, ssize_t len
)
536 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
537 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
538 u32 val
, *data
= frame
;
541 val
= I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder
));
543 for (i
= 0; i
< len
; i
+= 4)
544 *data
++ = I915_READ(hsw_dip_data_reg(dev_priv
, cpu_transcoder
,
548 static u32
hsw_infoframes_enabled(struct intel_encoder
*encoder
,
549 const struct intel_crtc_state
*pipe_config
)
551 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
552 u32 val
= I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config
->cpu_transcoder
));
554 return val
& (VIDEO_DIP_ENABLE_VSC_HSW
| VIDEO_DIP_ENABLE_AVI_HSW
|
555 VIDEO_DIP_ENABLE_GCP_HSW
| VIDEO_DIP_ENABLE_VS_HSW
|
556 VIDEO_DIP_ENABLE_GMP_HSW
| VIDEO_DIP_ENABLE_SPD_HSW
);
559 static const u8 infoframe_type_to_idx
[] = {
560 HDMI_PACKET_TYPE_GENERAL_CONTROL
,
561 HDMI_PACKET_TYPE_GAMUT_METADATA
,
563 HDMI_INFOFRAME_TYPE_AVI
,
564 HDMI_INFOFRAME_TYPE_SPD
,
565 HDMI_INFOFRAME_TYPE_VENDOR
,
568 u32
intel_hdmi_infoframe_enable(unsigned int type
)
572 for (i
= 0; i
< ARRAY_SIZE(infoframe_type_to_idx
); i
++) {
573 if (infoframe_type_to_idx
[i
] == type
)
580 u32
intel_hdmi_infoframes_enabled(struct intel_encoder
*encoder
,
581 const struct intel_crtc_state
*crtc_state
)
583 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
584 struct intel_digital_port
*dig_port
= enc_to_dig_port(&encoder
->base
);
588 val
= dig_port
->infoframes_enabled(encoder
, crtc_state
);
590 /* map from hardware bits to dip idx */
591 for (i
= 0; i
< ARRAY_SIZE(infoframe_type_to_idx
); i
++) {
592 unsigned int type
= infoframe_type_to_idx
[i
];
594 if (HAS_DDI(dev_priv
)) {
595 if (val
& hsw_infoframe_enable(type
))
598 if (val
& g4x_infoframe_enable(type
))
607 * The data we write to the DIP data buffer registers is 1 byte bigger than the
608 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
609 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
610 * used for both technologies.
612 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
613 * DW1: DB3 | DB2 | DB1 | DB0
614 * DW2: DB7 | DB6 | DB5 | DB4
617 * (HB is Header Byte, DB is Data Byte)
619 * The hdmi pack() functions don't know about that hardware specific hole so we
620 * trick them by giving an offset into the buffer and moving back the header
623 static void intel_write_infoframe(struct intel_encoder
*encoder
,
624 const struct intel_crtc_state
*crtc_state
,
625 enum hdmi_infoframe_type type
,
626 const union hdmi_infoframe
*frame
)
628 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(&encoder
->base
);
629 u8 buffer
[VIDEO_DIP_DATA_SIZE
];
632 if ((crtc_state
->infoframes
.enable
&
633 intel_hdmi_infoframe_enable(type
)) == 0)
636 if (WARN_ON(frame
->any
.type
!= type
))
639 /* see comment above for the reason for this offset */
640 len
= hdmi_infoframe_pack_only(frame
, buffer
+ 1, sizeof(buffer
) - 1);
641 if (WARN_ON(len
< 0))
644 /* Insert the 'hole' (see big comment above) at position 3 */
645 memmove(&buffer
[0], &buffer
[1], 3);
649 intel_dig_port
->write_infoframe(encoder
, crtc_state
, type
, buffer
, len
);
652 void intel_read_infoframe(struct intel_encoder
*encoder
,
653 const struct intel_crtc_state
*crtc_state
,
654 enum hdmi_infoframe_type type
,
655 union hdmi_infoframe
*frame
)
657 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(&encoder
->base
);
658 u8 buffer
[VIDEO_DIP_DATA_SIZE
];
661 if ((crtc_state
->infoframes
.enable
&
662 intel_hdmi_infoframe_enable(type
)) == 0)
665 intel_dig_port
->read_infoframe(encoder
, crtc_state
,
666 type
, buffer
, sizeof(buffer
));
668 /* Fill the 'hole' (see big comment above) at position 3 */
669 memmove(&buffer
[1], &buffer
[0], 3);
671 /* see comment above for the reason for this offset */
672 ret
= hdmi_infoframe_unpack(frame
, buffer
+ 1, sizeof(buffer
) - 1);
674 DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type
);
678 if (frame
->any
.type
!= type
)
679 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
680 frame
->any
.type
, type
);
684 intel_hdmi_compute_avi_infoframe(struct intel_encoder
*encoder
,
685 struct intel_crtc_state
*crtc_state
,
686 struct drm_connector_state
*conn_state
)
688 struct hdmi_avi_infoframe
*frame
= &crtc_state
->infoframes
.avi
.avi
;
689 const struct drm_display_mode
*adjusted_mode
=
690 &crtc_state
->base
.adjusted_mode
;
691 struct drm_connector
*connector
= conn_state
->connector
;
694 if (!crtc_state
->has_infoframe
)
697 crtc_state
->infoframes
.enable
|=
698 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI
);
700 ret
= drm_hdmi_avi_infoframe_from_display_mode(frame
, connector
,
705 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
)
706 frame
->colorspace
= HDMI_COLORSPACE_YUV420
;
707 else if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR444
)
708 frame
->colorspace
= HDMI_COLORSPACE_YUV444
;
710 frame
->colorspace
= HDMI_COLORSPACE_RGB
;
712 drm_hdmi_avi_infoframe_colorspace(frame
, conn_state
);
714 drm_hdmi_avi_infoframe_quant_range(frame
, connector
,
716 crtc_state
->limited_color_range
?
717 HDMI_QUANTIZATION_RANGE_LIMITED
:
718 HDMI_QUANTIZATION_RANGE_FULL
);
720 drm_hdmi_avi_infoframe_content_type(frame
, conn_state
);
722 /* TODO: handle pixel repetition for YCBCR420 outputs */
724 ret
= hdmi_avi_infoframe_check(frame
);
732 intel_hdmi_compute_spd_infoframe(struct intel_encoder
*encoder
,
733 struct intel_crtc_state
*crtc_state
,
734 struct drm_connector_state
*conn_state
)
736 struct hdmi_spd_infoframe
*frame
= &crtc_state
->infoframes
.spd
.spd
;
739 if (!crtc_state
->has_infoframe
)
742 crtc_state
->infoframes
.enable
|=
743 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD
);
745 ret
= hdmi_spd_infoframe_init(frame
, "Intel", "Integrated gfx");
749 frame
->sdi
= HDMI_SPD_SDI_PC
;
751 ret
= hdmi_spd_infoframe_check(frame
);
759 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder
*encoder
,
760 struct intel_crtc_state
*crtc_state
,
761 struct drm_connector_state
*conn_state
)
763 struct hdmi_vendor_infoframe
*frame
=
764 &crtc_state
->infoframes
.hdmi
.vendor
.hdmi
;
765 const struct drm_display_info
*info
=
766 &conn_state
->connector
->display_info
;
769 if (!crtc_state
->has_infoframe
|| !info
->has_hdmi_infoframe
)
772 crtc_state
->infoframes
.enable
|=
773 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR
);
775 ret
= drm_hdmi_vendor_infoframe_from_display_mode(frame
,
776 conn_state
->connector
,
777 &crtc_state
->base
.adjusted_mode
);
781 ret
= hdmi_vendor_infoframe_check(frame
);
788 static void g4x_set_infoframes(struct intel_encoder
*encoder
,
790 const struct intel_crtc_state
*crtc_state
,
791 const struct drm_connector_state
*conn_state
)
793 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
794 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(&encoder
->base
);
795 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
796 i915_reg_t reg
= VIDEO_DIP_CTL
;
797 u32 val
= I915_READ(reg
);
798 u32 port
= VIDEO_DIP_PORT(encoder
->port
);
800 assert_hdmi_port_disabled(intel_hdmi
);
802 /* If the registers were not initialized yet, they might be zeroes,
803 * which means we're selecting the AVI DIP and we're setting its
804 * frequency to once. This seems to really confuse the HW and make
805 * things stop working (the register spec says the AVI always needs to
806 * be sent every VSync). So here we avoid writing to the register more
807 * than we need and also explicitly select the AVI DIP and explicitly
808 * set its frequency to every VSync. Avoiding to write it twice seems to
809 * be enough to solve the problem, but being defensive shouldn't hurt us
811 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
814 if (!(val
& VIDEO_DIP_ENABLE
))
816 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
817 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
818 (val
& VIDEO_DIP_PORT_MASK
) >> 29);
821 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
|
822 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_SPD
);
823 I915_WRITE(reg
, val
);
828 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
829 if (val
& VIDEO_DIP_ENABLE
) {
830 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
831 (val
& VIDEO_DIP_PORT_MASK
) >> 29);
834 val
&= ~VIDEO_DIP_PORT_MASK
;
838 val
|= VIDEO_DIP_ENABLE
;
839 val
&= ~(VIDEO_DIP_ENABLE_AVI
|
840 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_SPD
);
842 I915_WRITE(reg
, val
);
845 intel_write_infoframe(encoder
, crtc_state
,
846 HDMI_INFOFRAME_TYPE_AVI
,
847 &crtc_state
->infoframes
.avi
);
848 intel_write_infoframe(encoder
, crtc_state
,
849 HDMI_INFOFRAME_TYPE_SPD
,
850 &crtc_state
->infoframes
.spd
);
851 intel_write_infoframe(encoder
, crtc_state
,
852 HDMI_INFOFRAME_TYPE_VENDOR
,
853 &crtc_state
->infoframes
.hdmi
);
857 * Determine if default_phase=1 can be indicated in the GCP infoframe.
859 * From HDMI specification 1.4a:
860 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
861 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
862 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
863 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
866 static bool gcp_default_phase_possible(int pipe_bpp
,
867 const struct drm_display_mode
*mode
)
869 unsigned int pixels_per_group
;
873 /* 4 pixels in 5 clocks */
874 pixels_per_group
= 4;
877 /* 2 pixels in 3 clocks */
878 pixels_per_group
= 2;
881 /* 1 pixel in 2 clocks */
882 pixels_per_group
= 1;
885 /* phase information not relevant for 8bpc */
889 return mode
->crtc_hdisplay
% pixels_per_group
== 0 &&
890 mode
->crtc_htotal
% pixels_per_group
== 0 &&
891 mode
->crtc_hblank_start
% pixels_per_group
== 0 &&
892 mode
->crtc_hblank_end
% pixels_per_group
== 0 &&
893 mode
->crtc_hsync_start
% pixels_per_group
== 0 &&
894 mode
->crtc_hsync_end
% pixels_per_group
== 0 &&
895 ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
) == 0 ||
896 mode
->crtc_htotal
/2 % pixels_per_group
== 0);
899 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder
*encoder
,
900 const struct intel_crtc_state
*crtc_state
,
901 const struct drm_connector_state
*conn_state
)
903 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
904 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
907 if ((crtc_state
->infoframes
.enable
&
908 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL
)) == 0)
911 if (HAS_DDI(dev_priv
))
912 reg
= HSW_TVIDEO_DIP_GCP(crtc_state
->cpu_transcoder
);
913 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
914 reg
= VLV_TVIDEO_DIP_GCP(crtc
->pipe
);
915 else if (HAS_PCH_SPLIT(dev_priv
))
916 reg
= TVIDEO_DIP_GCP(crtc
->pipe
);
920 I915_WRITE(reg
, crtc_state
->infoframes
.gcp
);
925 void intel_hdmi_read_gcp_infoframe(struct intel_encoder
*encoder
,
926 struct intel_crtc_state
*crtc_state
)
928 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
929 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
932 if ((crtc_state
->infoframes
.enable
&
933 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL
)) == 0)
936 if (HAS_DDI(dev_priv
))
937 reg
= HSW_TVIDEO_DIP_GCP(crtc_state
->cpu_transcoder
);
938 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
939 reg
= VLV_TVIDEO_DIP_GCP(crtc
->pipe
);
940 else if (HAS_PCH_SPLIT(dev_priv
))
941 reg
= TVIDEO_DIP_GCP(crtc
->pipe
);
945 crtc_state
->infoframes
.gcp
= I915_READ(reg
);
948 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder
*encoder
,
949 struct intel_crtc_state
*crtc_state
,
950 struct drm_connector_state
*conn_state
)
952 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
954 if (IS_G4X(dev_priv
) || !crtc_state
->has_infoframe
)
957 crtc_state
->infoframes
.enable
|=
958 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL
);
960 /* Indicate color indication for deep color mode */
961 if (crtc_state
->pipe_bpp
> 24)
962 crtc_state
->infoframes
.gcp
|= GCP_COLOR_INDICATION
;
964 /* Enable default_phase whenever the display mode is suitably aligned */
965 if (gcp_default_phase_possible(crtc_state
->pipe_bpp
,
966 &crtc_state
->base
.adjusted_mode
))
967 crtc_state
->infoframes
.gcp
|= GCP_DEFAULT_PHASE_ENABLE
;
970 static void ibx_set_infoframes(struct intel_encoder
*encoder
,
972 const struct intel_crtc_state
*crtc_state
,
973 const struct drm_connector_state
*conn_state
)
975 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
976 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
977 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(&encoder
->base
);
978 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
979 i915_reg_t reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
980 u32 val
= I915_READ(reg
);
981 u32 port
= VIDEO_DIP_PORT(encoder
->port
);
983 assert_hdmi_port_disabled(intel_hdmi
);
985 /* See the big comment in g4x_set_infoframes() */
986 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
989 if (!(val
& VIDEO_DIP_ENABLE
))
991 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
|
992 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
993 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
994 I915_WRITE(reg
, val
);
999 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
1000 WARN(val
& VIDEO_DIP_ENABLE
,
1001 "DIP already enabled on port %c\n",
1002 (val
& VIDEO_DIP_PORT_MASK
) >> 29);
1003 val
&= ~VIDEO_DIP_PORT_MASK
;
1007 val
|= VIDEO_DIP_ENABLE
;
1008 val
&= ~(VIDEO_DIP_ENABLE_AVI
|
1009 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
1010 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
1012 if (intel_hdmi_set_gcp_infoframe(encoder
, crtc_state
, conn_state
))
1013 val
|= VIDEO_DIP_ENABLE_GCP
;
1015 I915_WRITE(reg
, val
);
1018 intel_write_infoframe(encoder
, crtc_state
,
1019 HDMI_INFOFRAME_TYPE_AVI
,
1020 &crtc_state
->infoframes
.avi
);
1021 intel_write_infoframe(encoder
, crtc_state
,
1022 HDMI_INFOFRAME_TYPE_SPD
,
1023 &crtc_state
->infoframes
.spd
);
1024 intel_write_infoframe(encoder
, crtc_state
,
1025 HDMI_INFOFRAME_TYPE_VENDOR
,
1026 &crtc_state
->infoframes
.hdmi
);
1029 static void cpt_set_infoframes(struct intel_encoder
*encoder
,
1031 const struct intel_crtc_state
*crtc_state
,
1032 const struct drm_connector_state
*conn_state
)
1034 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1035 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1036 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1037 i915_reg_t reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
1038 u32 val
= I915_READ(reg
);
1040 assert_hdmi_port_disabled(intel_hdmi
);
1042 /* See the big comment in g4x_set_infoframes() */
1043 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
1046 if (!(val
& VIDEO_DIP_ENABLE
))
1048 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
|
1049 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
1050 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
1051 I915_WRITE(reg
, val
);
1056 /* Set both together, unset both together: see the spec. */
1057 val
|= VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
;
1058 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
1059 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
1061 if (intel_hdmi_set_gcp_infoframe(encoder
, crtc_state
, conn_state
))
1062 val
|= VIDEO_DIP_ENABLE_GCP
;
1064 I915_WRITE(reg
, val
);
1067 intel_write_infoframe(encoder
, crtc_state
,
1068 HDMI_INFOFRAME_TYPE_AVI
,
1069 &crtc_state
->infoframes
.avi
);
1070 intel_write_infoframe(encoder
, crtc_state
,
1071 HDMI_INFOFRAME_TYPE_SPD
,
1072 &crtc_state
->infoframes
.spd
);
1073 intel_write_infoframe(encoder
, crtc_state
,
1074 HDMI_INFOFRAME_TYPE_VENDOR
,
1075 &crtc_state
->infoframes
.hdmi
);
1078 static void vlv_set_infoframes(struct intel_encoder
*encoder
,
1080 const struct intel_crtc_state
*crtc_state
,
1081 const struct drm_connector_state
*conn_state
)
1083 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1084 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1085 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1086 i915_reg_t reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
1087 u32 val
= I915_READ(reg
);
1088 u32 port
= VIDEO_DIP_PORT(encoder
->port
);
1090 assert_hdmi_port_disabled(intel_hdmi
);
1092 /* See the big comment in g4x_set_infoframes() */
1093 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
1096 if (!(val
& VIDEO_DIP_ENABLE
))
1098 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
|
1099 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
1100 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
1101 I915_WRITE(reg
, val
);
1106 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
1107 WARN(val
& VIDEO_DIP_ENABLE
,
1108 "DIP already enabled on port %c\n",
1109 (val
& VIDEO_DIP_PORT_MASK
) >> 29);
1110 val
&= ~VIDEO_DIP_PORT_MASK
;
1114 val
|= VIDEO_DIP_ENABLE
;
1115 val
&= ~(VIDEO_DIP_ENABLE_AVI
|
1116 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
1117 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
1119 if (intel_hdmi_set_gcp_infoframe(encoder
, crtc_state
, conn_state
))
1120 val
|= VIDEO_DIP_ENABLE_GCP
;
1122 I915_WRITE(reg
, val
);
1125 intel_write_infoframe(encoder
, crtc_state
,
1126 HDMI_INFOFRAME_TYPE_AVI
,
1127 &crtc_state
->infoframes
.avi
);
1128 intel_write_infoframe(encoder
, crtc_state
,
1129 HDMI_INFOFRAME_TYPE_SPD
,
1130 &crtc_state
->infoframes
.spd
);
1131 intel_write_infoframe(encoder
, crtc_state
,
1132 HDMI_INFOFRAME_TYPE_VENDOR
,
1133 &crtc_state
->infoframes
.hdmi
);
1136 static void hsw_set_infoframes(struct intel_encoder
*encoder
,
1138 const struct intel_crtc_state
*crtc_state
,
1139 const struct drm_connector_state
*conn_state
)
1141 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1142 i915_reg_t reg
= HSW_TVIDEO_DIP_CTL(crtc_state
->cpu_transcoder
);
1143 u32 val
= I915_READ(reg
);
1145 assert_hdmi_transcoder_func_disabled(dev_priv
,
1146 crtc_state
->cpu_transcoder
);
1148 val
&= ~(VIDEO_DIP_ENABLE_VSC_HSW
| VIDEO_DIP_ENABLE_AVI_HSW
|
1149 VIDEO_DIP_ENABLE_GCP_HSW
| VIDEO_DIP_ENABLE_VS_HSW
|
1150 VIDEO_DIP_ENABLE_GMP_HSW
| VIDEO_DIP_ENABLE_SPD_HSW
);
1153 I915_WRITE(reg
, val
);
1158 if (intel_hdmi_set_gcp_infoframe(encoder
, crtc_state
, conn_state
))
1159 val
|= VIDEO_DIP_ENABLE_GCP_HSW
;
1161 I915_WRITE(reg
, val
);
1164 intel_write_infoframe(encoder
, crtc_state
,
1165 HDMI_INFOFRAME_TYPE_AVI
,
1166 &crtc_state
->infoframes
.avi
);
1167 intel_write_infoframe(encoder
, crtc_state
,
1168 HDMI_INFOFRAME_TYPE_SPD
,
1169 &crtc_state
->infoframes
.spd
);
1170 intel_write_infoframe(encoder
, crtc_state
,
1171 HDMI_INFOFRAME_TYPE_VENDOR
,
1172 &crtc_state
->infoframes
.hdmi
);
1175 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi
*hdmi
, bool enable
)
1177 struct drm_i915_private
*dev_priv
= to_i915(intel_hdmi_to_dev(hdmi
));
1178 struct i2c_adapter
*adapter
=
1179 intel_gmbus_get_adapter(dev_priv
, hdmi
->ddc_bus
);
1181 if (hdmi
->dp_dual_mode
.type
< DRM_DP_DUAL_MODE_TYPE2_DVI
)
1184 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
1185 enable
? "Enabling" : "Disabling");
1187 drm_dp_dual_mode_set_tmds_output(hdmi
->dp_dual_mode
.type
,
1191 static int intel_hdmi_hdcp_read(struct intel_digital_port
*intel_dig_port
,
1192 unsigned int offset
, void *buffer
, size_t size
)
1194 struct intel_hdmi
*hdmi
= &intel_dig_port
->hdmi
;
1195 struct drm_i915_private
*dev_priv
=
1196 intel_dig_port
->base
.base
.dev
->dev_private
;
1197 struct i2c_adapter
*adapter
= intel_gmbus_get_adapter(dev_priv
,
1200 u8 start
= offset
& 0xff;
1201 struct i2c_msg msgs
[] = {
1203 .addr
= DRM_HDCP_DDC_ADDR
,
1209 .addr
= DRM_HDCP_DDC_ADDR
,
1215 ret
= i2c_transfer(adapter
, msgs
, ARRAY_SIZE(msgs
));
1216 if (ret
== ARRAY_SIZE(msgs
))
1218 return ret
>= 0 ? -EIO
: ret
;
1221 static int intel_hdmi_hdcp_write(struct intel_digital_port
*intel_dig_port
,
1222 unsigned int offset
, void *buffer
, size_t size
)
1224 struct intel_hdmi
*hdmi
= &intel_dig_port
->hdmi
;
1225 struct drm_i915_private
*dev_priv
=
1226 intel_dig_port
->base
.base
.dev
->dev_private
;
1227 struct i2c_adapter
*adapter
= intel_gmbus_get_adapter(dev_priv
,
1233 write_buf
= kzalloc(size
+ 1, GFP_KERNEL
);
1237 write_buf
[0] = offset
& 0xff;
1238 memcpy(&write_buf
[1], buffer
, size
);
1240 msg
.addr
= DRM_HDCP_DDC_ADDR
;
1243 msg
.buf
= write_buf
;
1245 ret
= i2c_transfer(adapter
, &msg
, 1);
1256 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port
*intel_dig_port
,
1259 struct intel_hdmi
*hdmi
= &intel_dig_port
->hdmi
;
1260 struct drm_i915_private
*dev_priv
=
1261 intel_dig_port
->base
.base
.dev
->dev_private
;
1262 struct i2c_adapter
*adapter
= intel_gmbus_get_adapter(dev_priv
,
1266 ret
= intel_hdmi_hdcp_write(intel_dig_port
, DRM_HDCP_DDC_AN
, an
,
1269 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret
);
1273 ret
= intel_gmbus_output_aksv(adapter
);
1275 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret
);
1281 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port
*intel_dig_port
,
1285 ret
= intel_hdmi_hdcp_read(intel_dig_port
, DRM_HDCP_DDC_BKSV
, bksv
,
1288 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret
);
1293 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port
*intel_dig_port
,
1297 ret
= intel_hdmi_hdcp_read(intel_dig_port
, DRM_HDCP_DDC_BSTATUS
,
1298 bstatus
, DRM_HDCP_BSTATUS_LEN
);
1300 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret
);
1305 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port
*intel_dig_port
,
1306 bool *repeater_present
)
1311 ret
= intel_hdmi_hdcp_read(intel_dig_port
, DRM_HDCP_DDC_BCAPS
, &val
, 1);
1313 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret
);
1316 *repeater_present
= val
& DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT
;
1321 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port
*intel_dig_port
,
1325 ret
= intel_hdmi_hdcp_read(intel_dig_port
, DRM_HDCP_DDC_RI_PRIME
,
1326 ri_prime
, DRM_HDCP_RI_LEN
);
1328 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret
);
1333 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port
*intel_dig_port
,
1339 ret
= intel_hdmi_hdcp_read(intel_dig_port
, DRM_HDCP_DDC_BCAPS
, &val
, 1);
1341 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret
);
1344 *ksv_ready
= val
& DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY
;
1349 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port
*intel_dig_port
,
1350 int num_downstream
, u8
*ksv_fifo
)
1353 ret
= intel_hdmi_hdcp_read(intel_dig_port
, DRM_HDCP_DDC_KSV_FIFO
,
1354 ksv_fifo
, num_downstream
* DRM_HDCP_KSV_LEN
);
1356 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret
);
1363 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port
*intel_dig_port
,
1368 if (i
>= DRM_HDCP_V_PRIME_NUM_PARTS
)
1371 ret
= intel_hdmi_hdcp_read(intel_dig_port
, DRM_HDCP_DDC_V_PRIME(i
),
1372 part
, DRM_HDCP_V_PRIME_PART_LEN
);
1374 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i
, ret
);
1378 static int kbl_repositioning_enc_en_signal(struct intel_connector
*connector
)
1380 struct drm_i915_private
*dev_priv
= to_i915(connector
->base
.dev
);
1381 struct intel_digital_port
*intel_dig_port
= conn_to_dig_port(connector
);
1382 struct drm_crtc
*crtc
= connector
->base
.state
->crtc
;
1383 struct intel_crtc
*intel_crtc
= container_of(crtc
,
1384 struct intel_crtc
, base
);
1389 scanline
= I915_READ(PIPEDSL(intel_crtc
->pipe
));
1390 if (scanline
> 100 && scanline
< 200)
1392 usleep_range(25, 50);
1395 ret
= intel_ddi_toggle_hdcp_signalling(&intel_dig_port
->base
, false);
1397 DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret
);
1400 ret
= intel_ddi_toggle_hdcp_signalling(&intel_dig_port
->base
, true);
1402 DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret
);
1410 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port
*intel_dig_port
,
1413 struct intel_hdmi
*hdmi
= &intel_dig_port
->hdmi
;
1414 struct intel_connector
*connector
= hdmi
->attached_connector
;
1415 struct drm_i915_private
*dev_priv
= to_i915(connector
->base
.dev
);
1419 usleep_range(6, 60); /* Bspec says >= 6us */
1421 ret
= intel_ddi_toggle_hdcp_signalling(&intel_dig_port
->base
, enable
);
1423 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1424 enable
? "Enable" : "Disable", ret
);
1429 * WA: To fix incorrect positioning of the window of
1430 * opportunity and enc_en signalling in KABYLAKE.
1432 if (IS_KABYLAKE(dev_priv
) && enable
)
1433 return kbl_repositioning_enc_en_signal(connector
);
1439 bool intel_hdmi_hdcp_check_link(struct intel_digital_port
*intel_dig_port
)
1441 struct drm_i915_private
*dev_priv
=
1442 intel_dig_port
->base
.base
.dev
->dev_private
;
1443 enum port port
= intel_dig_port
->base
.port
;
1447 u8 shim
[DRM_HDCP_RI_LEN
];
1450 ret
= intel_hdmi_hdcp_read_ri_prime(intel_dig_port
, ri
.shim
);
1454 I915_WRITE(PORT_HDCP_RPRIME(port
), ri
.reg
);
1456 /* Wait for Ri prime match */
1457 if (wait_for(I915_READ(PORT_HDCP_STATUS(port
)) &
1458 (HDCP_STATUS_RI_MATCH
| HDCP_STATUS_ENC
), 1)) {
1459 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1460 I915_READ(PORT_HDCP_STATUS(port
)));
1466 static struct hdcp2_hdmi_msg_data
{
1470 } hdcp2_msg_data
[] = {
1471 {HDCP_2_2_AKE_INIT
, 0, 0},
1472 {HDCP_2_2_AKE_SEND_CERT
, HDCP_2_2_CERT_TIMEOUT_MS
, 0},
1473 {HDCP_2_2_AKE_NO_STORED_KM
, 0, 0},
1474 {HDCP_2_2_AKE_STORED_KM
, 0, 0},
1475 {HDCP_2_2_AKE_SEND_HPRIME
, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS
,
1476 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS
},
1477 {HDCP_2_2_AKE_SEND_PAIRING_INFO
, HDCP_2_2_PAIRING_TIMEOUT_MS
,
1479 {HDCP_2_2_LC_INIT
, 0, 0},
1480 {HDCP_2_2_LC_SEND_LPRIME
, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS
, 0},
1481 {HDCP_2_2_SKE_SEND_EKS
, 0, 0},
1482 {HDCP_2_2_REP_SEND_RECVID_LIST
,
1483 HDCP_2_2_RECVID_LIST_TIMEOUT_MS
, 0},
1484 {HDCP_2_2_REP_SEND_ACK
, 0, 0},
1485 {HDCP_2_2_REP_STREAM_MANAGE
, 0, 0},
1486 {HDCP_2_2_REP_STREAM_READY
, HDCP_2_2_STREAM_READY_TIMEOUT_MS
,
1491 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port
*intel_dig_port
,
1494 return intel_hdmi_hdcp_read(intel_dig_port
,
1495 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET
,
1497 HDCP_2_2_HDMI_RXSTATUS_LEN
);
1500 static int get_hdcp2_msg_timeout(u8 msg_id
, bool is_paired
)
1504 for (i
= 0; i
< ARRAY_SIZE(hdcp2_msg_data
); i
++)
1505 if (hdcp2_msg_data
[i
].msg_id
== msg_id
&&
1506 (msg_id
!= HDCP_2_2_AKE_SEND_HPRIME
|| is_paired
))
1507 return hdcp2_msg_data
[i
].timeout
;
1508 else if (hdcp2_msg_data
[i
].msg_id
== msg_id
)
1509 return hdcp2_msg_data
[i
].timeout2
;
1515 int hdcp2_detect_msg_availability(struct intel_digital_port
*intel_digital_port
,
1516 u8 msg_id
, bool *msg_ready
,
1519 u8 rx_status
[HDCP_2_2_HDMI_RXSTATUS_LEN
];
1522 ret
= intel_hdmi_hdcp2_read_rx_status(intel_digital_port
, rx_status
);
1524 DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret
);
1528 *msg_sz
= ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status
[1]) << 8) |
1531 if (msg_id
== HDCP_2_2_REP_SEND_RECVID_LIST
)
1532 *msg_ready
= (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status
[1]) &&
1535 *msg_ready
= *msg_sz
;
1541 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port
*intel_dig_port
,
1542 u8 msg_id
, bool paired
)
1544 bool msg_ready
= false;
1548 timeout
= get_hdcp2_msg_timeout(msg_id
, paired
);
1552 ret
= __wait_for(ret
= hdcp2_detect_msg_availability(intel_dig_port
,
1555 !ret
&& msg_ready
&& msg_sz
, timeout
* 1000,
1558 DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n",
1559 msg_id
, ret
, timeout
);
1561 return ret
? ret
: msg_sz
;
1565 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port
*intel_dig_port
,
1566 void *buf
, size_t size
)
1568 unsigned int offset
;
1570 offset
= HDCP_2_2_HDMI_REG_WR_MSG_OFFSET
;
1571 return intel_hdmi_hdcp_write(intel_dig_port
, offset
, buf
, size
);
1575 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port
*intel_dig_port
,
1576 u8 msg_id
, void *buf
, size_t size
)
1578 struct intel_hdmi
*hdmi
= &intel_dig_port
->hdmi
;
1579 struct intel_hdcp
*hdcp
= &hdmi
->attached_connector
->hdcp
;
1580 unsigned int offset
;
1583 ret
= intel_hdmi_hdcp2_wait_for_msg(intel_dig_port
, msg_id
,
1589 * Available msg size should be equal to or lesser than the
1593 DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n",
1598 offset
= HDCP_2_2_HDMI_REG_RD_MSG_OFFSET
;
1599 ret
= intel_hdmi_hdcp_read(intel_dig_port
, offset
, buf
, ret
);
1601 DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id
, ret
);
1607 int intel_hdmi_hdcp2_check_link(struct intel_digital_port
*intel_dig_port
)
1609 u8 rx_status
[HDCP_2_2_HDMI_RXSTATUS_LEN
];
1612 ret
= intel_hdmi_hdcp2_read_rx_status(intel_dig_port
, rx_status
);
1617 * Re-auth request and Link Integrity Failures are represented by
1618 * same bit. i.e reauth_req.
1620 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status
[1]))
1621 ret
= HDCP_REAUTH_REQUEST
;
1622 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status
[1]))
1623 ret
= HDCP_TOPOLOGY_CHANGE
;
1629 int intel_hdmi_hdcp2_capable(struct intel_digital_port
*intel_dig_port
,
1636 ret
= intel_hdmi_hdcp_read(intel_dig_port
, HDCP_2_2_HDMI_REG_VER_OFFSET
,
1637 &hdcp2_version
, sizeof(hdcp2_version
));
1638 if (!ret
&& hdcp2_version
& HDCP_2_2_HDMI_SUPPORT_MASK
)
1645 enum hdcp_wired_protocol
intel_hdmi_hdcp2_protocol(void)
1647 return HDCP_PROTOCOL_HDMI
;
1650 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim
= {
1651 .write_an_aksv
= intel_hdmi_hdcp_write_an_aksv
,
1652 .read_bksv
= intel_hdmi_hdcp_read_bksv
,
1653 .read_bstatus
= intel_hdmi_hdcp_read_bstatus
,
1654 .repeater_present
= intel_hdmi_hdcp_repeater_present
,
1655 .read_ri_prime
= intel_hdmi_hdcp_read_ri_prime
,
1656 .read_ksv_ready
= intel_hdmi_hdcp_read_ksv_ready
,
1657 .read_ksv_fifo
= intel_hdmi_hdcp_read_ksv_fifo
,
1658 .read_v_prime_part
= intel_hdmi_hdcp_read_v_prime_part
,
1659 .toggle_signalling
= intel_hdmi_hdcp_toggle_signalling
,
1660 .check_link
= intel_hdmi_hdcp_check_link
,
1661 .write_2_2_msg
= intel_hdmi_hdcp2_write_msg
,
1662 .read_2_2_msg
= intel_hdmi_hdcp2_read_msg
,
1663 .check_2_2_link
= intel_hdmi_hdcp2_check_link
,
1664 .hdcp_2_2_capable
= intel_hdmi_hdcp2_capable
,
1665 .protocol
= HDCP_PROTOCOL_HDMI
,
1668 static void intel_hdmi_prepare(struct intel_encoder
*encoder
,
1669 const struct intel_crtc_state
*crtc_state
)
1671 struct drm_device
*dev
= encoder
->base
.dev
;
1672 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1673 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1674 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1675 const struct drm_display_mode
*adjusted_mode
= &crtc_state
->base
.adjusted_mode
;
1678 intel_dp_dual_mode_set_tmds_output(intel_hdmi
, true);
1680 hdmi_val
= SDVO_ENCODING_HDMI
;
1681 if (!HAS_PCH_SPLIT(dev_priv
) && crtc_state
->limited_color_range
)
1682 hdmi_val
|= HDMI_COLOR_RANGE_16_235
;
1683 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1684 hdmi_val
|= SDVO_VSYNC_ACTIVE_HIGH
;
1685 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1686 hdmi_val
|= SDVO_HSYNC_ACTIVE_HIGH
;
1688 if (crtc_state
->pipe_bpp
> 24)
1689 hdmi_val
|= HDMI_COLOR_FORMAT_12bpc
;
1691 hdmi_val
|= SDVO_COLOR_FORMAT_8bpc
;
1693 if (crtc_state
->has_hdmi_sink
)
1694 hdmi_val
|= HDMI_MODE_SELECT_HDMI
;
1696 if (HAS_PCH_CPT(dev_priv
))
1697 hdmi_val
|= SDVO_PIPE_SEL_CPT(crtc
->pipe
);
1698 else if (IS_CHERRYVIEW(dev_priv
))
1699 hdmi_val
|= SDVO_PIPE_SEL_CHV(crtc
->pipe
);
1701 hdmi_val
|= SDVO_PIPE_SEL(crtc
->pipe
);
1703 I915_WRITE(intel_hdmi
->hdmi_reg
, hdmi_val
);
1704 POSTING_READ(intel_hdmi
->hdmi_reg
);
1707 static bool intel_hdmi_get_hw_state(struct intel_encoder
*encoder
,
1710 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1711 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1712 intel_wakeref_t wakeref
;
1715 wakeref
= intel_display_power_get_if_enabled(dev_priv
,
1716 encoder
->power_domain
);
1720 ret
= intel_sdvo_port_enabled(dev_priv
, intel_hdmi
->hdmi_reg
, pipe
);
1722 intel_display_power_put(dev_priv
, encoder
->power_domain
, wakeref
);
1727 static void intel_hdmi_get_config(struct intel_encoder
*encoder
,
1728 struct intel_crtc_state
*pipe_config
)
1730 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1731 struct drm_device
*dev
= encoder
->base
.dev
;
1732 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1736 pipe_config
->output_types
|= BIT(INTEL_OUTPUT_HDMI
);
1738 tmp
= I915_READ(intel_hdmi
->hdmi_reg
);
1740 if (tmp
& SDVO_HSYNC_ACTIVE_HIGH
)
1741 flags
|= DRM_MODE_FLAG_PHSYNC
;
1743 flags
|= DRM_MODE_FLAG_NHSYNC
;
1745 if (tmp
& SDVO_VSYNC_ACTIVE_HIGH
)
1746 flags
|= DRM_MODE_FLAG_PVSYNC
;
1748 flags
|= DRM_MODE_FLAG_NVSYNC
;
1750 if (tmp
& HDMI_MODE_SELECT_HDMI
)
1751 pipe_config
->has_hdmi_sink
= true;
1753 pipe_config
->infoframes
.enable
|=
1754 intel_hdmi_infoframes_enabled(encoder
, pipe_config
);
1756 if (pipe_config
->infoframes
.enable
)
1757 pipe_config
->has_infoframe
= true;
1759 if (tmp
& SDVO_AUDIO_ENABLE
)
1760 pipe_config
->has_audio
= true;
1762 if (!HAS_PCH_SPLIT(dev_priv
) &&
1763 tmp
& HDMI_COLOR_RANGE_16_235
)
1764 pipe_config
->limited_color_range
= true;
1766 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
1768 if ((tmp
& SDVO_COLOR_FORMAT_MASK
) == HDMI_COLOR_FORMAT_12bpc
)
1769 dotclock
= pipe_config
->port_clock
* 2 / 3;
1771 dotclock
= pipe_config
->port_clock
;
1773 if (pipe_config
->pixel_multiplier
)
1774 dotclock
/= pipe_config
->pixel_multiplier
;
1776 pipe_config
->base
.adjusted_mode
.crtc_clock
= dotclock
;
1778 pipe_config
->lane_count
= 4;
1780 intel_hdmi_read_gcp_infoframe(encoder
, pipe_config
);
1782 intel_read_infoframe(encoder
, pipe_config
,
1783 HDMI_INFOFRAME_TYPE_AVI
,
1784 &pipe_config
->infoframes
.avi
);
1785 intel_read_infoframe(encoder
, pipe_config
,
1786 HDMI_INFOFRAME_TYPE_SPD
,
1787 &pipe_config
->infoframes
.spd
);
1788 intel_read_infoframe(encoder
, pipe_config
,
1789 HDMI_INFOFRAME_TYPE_VENDOR
,
1790 &pipe_config
->infoframes
.hdmi
);
1793 static void intel_enable_hdmi_audio(struct intel_encoder
*encoder
,
1794 const struct intel_crtc_state
*pipe_config
,
1795 const struct drm_connector_state
*conn_state
)
1797 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1799 WARN_ON(!pipe_config
->has_hdmi_sink
);
1800 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1801 pipe_name(crtc
->pipe
));
1802 intel_audio_codec_enable(encoder
, pipe_config
, conn_state
);
1805 static void g4x_enable_hdmi(struct intel_encoder
*encoder
,
1806 const struct intel_crtc_state
*pipe_config
,
1807 const struct drm_connector_state
*conn_state
)
1809 struct drm_device
*dev
= encoder
->base
.dev
;
1810 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1811 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1814 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
1816 temp
|= SDVO_ENABLE
;
1817 if (pipe_config
->has_audio
)
1818 temp
|= SDVO_AUDIO_ENABLE
;
1820 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1821 POSTING_READ(intel_hdmi
->hdmi_reg
);
1823 if (pipe_config
->has_audio
)
1824 intel_enable_hdmi_audio(encoder
, pipe_config
, conn_state
);
1827 static void ibx_enable_hdmi(struct intel_encoder
*encoder
,
1828 const struct intel_crtc_state
*pipe_config
,
1829 const struct drm_connector_state
*conn_state
)
1831 struct drm_device
*dev
= encoder
->base
.dev
;
1832 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1833 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1836 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
1838 temp
|= SDVO_ENABLE
;
1839 if (pipe_config
->has_audio
)
1840 temp
|= SDVO_AUDIO_ENABLE
;
1843 * HW workaround, need to write this twice for issue
1844 * that may result in first write getting masked.
1846 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1847 POSTING_READ(intel_hdmi
->hdmi_reg
);
1848 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1849 POSTING_READ(intel_hdmi
->hdmi_reg
);
1852 * HW workaround, need to toggle enable bit off and on
1853 * for 12bpc with pixel repeat.
1855 * FIXME: BSpec says this should be done at the end of
1856 * of the modeset sequence, so not sure if this isn't too soon.
1858 if (pipe_config
->pipe_bpp
> 24 &&
1859 pipe_config
->pixel_multiplier
> 1) {
1860 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
& ~SDVO_ENABLE
);
1861 POSTING_READ(intel_hdmi
->hdmi_reg
);
1864 * HW workaround, need to write this twice for issue
1865 * that may result in first write getting masked.
1867 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1868 POSTING_READ(intel_hdmi
->hdmi_reg
);
1869 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1870 POSTING_READ(intel_hdmi
->hdmi_reg
);
1873 if (pipe_config
->has_audio
)
1874 intel_enable_hdmi_audio(encoder
, pipe_config
, conn_state
);
1877 static void cpt_enable_hdmi(struct intel_encoder
*encoder
,
1878 const struct intel_crtc_state
*pipe_config
,
1879 const struct drm_connector_state
*conn_state
)
1881 struct drm_device
*dev
= encoder
->base
.dev
;
1882 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1883 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1884 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1885 enum pipe pipe
= crtc
->pipe
;
1888 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
1890 temp
|= SDVO_ENABLE
;
1891 if (pipe_config
->has_audio
)
1892 temp
|= SDVO_AUDIO_ENABLE
;
1895 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1897 * The procedure for 12bpc is as follows:
1898 * 1. disable HDMI clock gating
1899 * 2. enable HDMI with 8bpc
1900 * 3. enable HDMI with 12bpc
1901 * 4. enable HDMI clock gating
1904 if (pipe_config
->pipe_bpp
> 24) {
1905 I915_WRITE(TRANS_CHICKEN1(pipe
),
1906 I915_READ(TRANS_CHICKEN1(pipe
)) |
1907 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE
);
1909 temp
&= ~SDVO_COLOR_FORMAT_MASK
;
1910 temp
|= SDVO_COLOR_FORMAT_8bpc
;
1913 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1914 POSTING_READ(intel_hdmi
->hdmi_reg
);
1916 if (pipe_config
->pipe_bpp
> 24) {
1917 temp
&= ~SDVO_COLOR_FORMAT_MASK
;
1918 temp
|= HDMI_COLOR_FORMAT_12bpc
;
1920 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1921 POSTING_READ(intel_hdmi
->hdmi_reg
);
1923 I915_WRITE(TRANS_CHICKEN1(pipe
),
1924 I915_READ(TRANS_CHICKEN1(pipe
)) &
1925 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE
);
1928 if (pipe_config
->has_audio
)
1929 intel_enable_hdmi_audio(encoder
, pipe_config
, conn_state
);
1932 static void vlv_enable_hdmi(struct intel_encoder
*encoder
,
1933 const struct intel_crtc_state
*pipe_config
,
1934 const struct drm_connector_state
*conn_state
)
1938 static void intel_disable_hdmi(struct intel_encoder
*encoder
,
1939 const struct intel_crtc_state
*old_crtc_state
,
1940 const struct drm_connector_state
*old_conn_state
)
1942 struct drm_device
*dev
= encoder
->base
.dev
;
1943 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1944 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1945 struct intel_digital_port
*intel_dig_port
=
1946 hdmi_to_dig_port(intel_hdmi
);
1947 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
1950 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
1952 temp
&= ~(SDVO_ENABLE
| SDVO_AUDIO_ENABLE
);
1953 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1954 POSTING_READ(intel_hdmi
->hdmi_reg
);
1957 * HW workaround for IBX, we need to move the port
1958 * to transcoder A after disabling it to allow the
1959 * matching DP port to be enabled on transcoder A.
1961 if (HAS_PCH_IBX(dev_priv
) && crtc
->pipe
== PIPE_B
) {
1963 * We get CPU/PCH FIFO underruns on the other pipe when
1964 * doing the workaround. Sweep them under the rug.
1966 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
1967 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
1969 temp
&= ~SDVO_PIPE_SEL_MASK
;
1970 temp
|= SDVO_ENABLE
| SDVO_PIPE_SEL(PIPE_A
);
1972 * HW workaround, need to write this twice for issue
1973 * that may result in first write getting masked.
1975 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1976 POSTING_READ(intel_hdmi
->hdmi_reg
);
1977 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1978 POSTING_READ(intel_hdmi
->hdmi_reg
);
1980 temp
&= ~SDVO_ENABLE
;
1981 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1982 POSTING_READ(intel_hdmi
->hdmi_reg
);
1984 intel_wait_for_vblank_if_active(dev_priv
, PIPE_A
);
1985 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
1986 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
1989 intel_dig_port
->set_infoframes(encoder
,
1991 old_crtc_state
, old_conn_state
);
1993 intel_dp_dual_mode_set_tmds_output(intel_hdmi
, false);
1996 static void g4x_disable_hdmi(struct intel_encoder
*encoder
,
1997 const struct intel_crtc_state
*old_crtc_state
,
1998 const struct drm_connector_state
*old_conn_state
)
2000 if (old_crtc_state
->has_audio
)
2001 intel_audio_codec_disable(encoder
,
2002 old_crtc_state
, old_conn_state
);
2004 intel_disable_hdmi(encoder
, old_crtc_state
, old_conn_state
);
2007 static void pch_disable_hdmi(struct intel_encoder
*encoder
,
2008 const struct intel_crtc_state
*old_crtc_state
,
2009 const struct drm_connector_state
*old_conn_state
)
2011 if (old_crtc_state
->has_audio
)
2012 intel_audio_codec_disable(encoder
,
2013 old_crtc_state
, old_conn_state
);
2016 static void pch_post_disable_hdmi(struct intel_encoder
*encoder
,
2017 const struct intel_crtc_state
*old_crtc_state
,
2018 const struct drm_connector_state
*old_conn_state
)
2020 intel_disable_hdmi(encoder
, old_crtc_state
, old_conn_state
);
2023 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder
*encoder
)
2025 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2026 const struct ddi_vbt_port_info
*info
=
2027 &dev_priv
->vbt
.ddi_port_info
[encoder
->port
];
2030 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
))
2031 max_tmds_clock
= 594000;
2032 else if (INTEL_GEN(dev_priv
) >= 8 || IS_HASWELL(dev_priv
))
2033 max_tmds_clock
= 300000;
2034 else if (INTEL_GEN(dev_priv
) >= 5)
2035 max_tmds_clock
= 225000;
2037 max_tmds_clock
= 165000;
2039 if (info
->max_tmds_clock
)
2040 max_tmds_clock
= min(max_tmds_clock
, info
->max_tmds_clock
);
2042 return max_tmds_clock
;
2045 static int hdmi_port_clock_limit(struct intel_hdmi
*hdmi
,
2046 bool respect_downstream_limits
,
2049 struct intel_encoder
*encoder
= &hdmi_to_dig_port(hdmi
)->base
;
2050 int max_tmds_clock
= intel_hdmi_source_max_tmds_clock(encoder
);
2052 if (respect_downstream_limits
) {
2053 struct intel_connector
*connector
= hdmi
->attached_connector
;
2054 const struct drm_display_info
*info
= &connector
->base
.display_info
;
2056 if (hdmi
->dp_dual_mode
.max_tmds_clock
)
2057 max_tmds_clock
= min(max_tmds_clock
,
2058 hdmi
->dp_dual_mode
.max_tmds_clock
);
2060 if (info
->max_tmds_clock
)
2061 max_tmds_clock
= min(max_tmds_clock
,
2062 info
->max_tmds_clock
);
2063 else if (!hdmi
->has_hdmi_sink
|| force_dvi
)
2064 max_tmds_clock
= min(max_tmds_clock
, 165000);
2067 return max_tmds_clock
;
2070 static enum drm_mode_status
2071 hdmi_port_clock_valid(struct intel_hdmi
*hdmi
,
2072 int clock
, bool respect_downstream_limits
,
2075 struct drm_i915_private
*dev_priv
= to_i915(intel_hdmi_to_dev(hdmi
));
2078 return MODE_CLOCK_LOW
;
2079 if (clock
> hdmi_port_clock_limit(hdmi
, respect_downstream_limits
, force_dvi
))
2080 return MODE_CLOCK_HIGH
;
2082 /* BXT DPLL can't generate 223-240 MHz */
2083 if (IS_GEN9_LP(dev_priv
) && clock
> 223333 && clock
< 240000)
2084 return MODE_CLOCK_RANGE
;
2086 /* CHV DPLL can't generate 216-240 MHz */
2087 if (IS_CHERRYVIEW(dev_priv
) && clock
> 216000 && clock
< 240000)
2088 return MODE_CLOCK_RANGE
;
2093 static enum drm_mode_status
2094 intel_hdmi_mode_valid(struct drm_connector
*connector
,
2095 struct drm_display_mode
*mode
)
2097 struct intel_hdmi
*hdmi
= intel_attached_hdmi(connector
);
2098 struct drm_device
*dev
= intel_hdmi_to_dev(hdmi
);
2099 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2100 enum drm_mode_status status
;
2102 int max_dotclk
= to_i915(connector
->dev
)->max_dotclk_freq
;
2104 READ_ONCE(to_intel_digital_connector_state(connector
->state
)->force_audio
) == HDMI_AUDIO_OFF_DVI
;
2106 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
2107 return MODE_NO_DBLESCAN
;
2109 clock
= mode
->clock
;
2111 if ((mode
->flags
& DRM_MODE_FLAG_3D_MASK
) == DRM_MODE_FLAG_3D_FRAME_PACKING
)
2114 if (clock
> max_dotclk
)
2115 return MODE_CLOCK_HIGH
;
2117 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
2120 if (drm_mode_is_420_only(&connector
->display_info
, mode
))
2123 /* check if we can do 8bpc */
2124 status
= hdmi_port_clock_valid(hdmi
, clock
, true, force_dvi
);
2126 if (hdmi
->has_hdmi_sink
&& !force_dvi
) {
2127 /* if we can't do 8bpc we may still be able to do 12bpc */
2128 if (status
!= MODE_OK
&& !HAS_GMCH(dev_priv
))
2129 status
= hdmi_port_clock_valid(hdmi
, clock
* 3 / 2,
2132 /* if we can't do 8,12bpc we may still be able to do 10bpc */
2133 if (status
!= MODE_OK
&& INTEL_GEN(dev_priv
) >= 11)
2134 status
= hdmi_port_clock_valid(hdmi
, clock
* 5 / 4,
2141 static bool hdmi_deep_color_possible(const struct intel_crtc_state
*crtc_state
,
2144 struct drm_i915_private
*dev_priv
=
2145 to_i915(crtc_state
->base
.crtc
->dev
);
2146 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
2147 struct drm_connector_state
*connector_state
;
2148 struct drm_connector
*connector
;
2149 const struct drm_display_mode
*adjusted_mode
=
2150 &crtc_state
->base
.adjusted_mode
;
2153 if (HAS_GMCH(dev_priv
))
2156 if (bpc
== 10 && INTEL_GEN(dev_priv
) < 11)
2159 if (crtc_state
->pipe_bpp
< bpc
* 3)
2162 if (!crtc_state
->has_hdmi_sink
)
2166 * HDMI deep color affects the clocks, so it's only possible
2167 * when not cloning with other encoder types.
2169 if (crtc_state
->output_types
!= 1 << INTEL_OUTPUT_HDMI
)
2172 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
2173 const struct drm_display_info
*info
= &connector
->display_info
;
2175 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
2178 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
) {
2179 const struct drm_hdmi_info
*hdmi
= &info
->hdmi
;
2181 if (bpc
== 12 && !(hdmi
->y420_dc_modes
&
2182 DRM_EDID_YCBCR420_DC_36
))
2184 else if (bpc
== 10 && !(hdmi
->y420_dc_modes
&
2185 DRM_EDID_YCBCR420_DC_30
))
2188 if (bpc
== 12 && !(info
->edid_hdmi_dc_modes
&
2189 DRM_EDID_HDMI_DC_36
))
2191 else if (bpc
== 10 && !(info
->edid_hdmi_dc_modes
&
2192 DRM_EDID_HDMI_DC_30
))
2197 /* Display WA #1139: glk */
2198 if (bpc
== 12 && IS_GLK_REVID(dev_priv
, 0, GLK_REVID_A1
) &&
2199 adjusted_mode
->htotal
> 5460)
2202 /* Display Wa_1405510057:icl */
2203 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
&&
2204 bpc
== 10 && INTEL_GEN(dev_priv
) >= 11 &&
2205 (adjusted_mode
->crtc_hblank_end
-
2206 adjusted_mode
->crtc_hblank_start
) % 8 == 2)
2213 intel_hdmi_ycbcr420_config(struct drm_connector
*connector
,
2214 struct intel_crtc_state
*config
,
2215 int *clock_12bpc
, int *clock_10bpc
,
2218 struct intel_crtc
*intel_crtc
= to_intel_crtc(config
->base
.crtc
);
2220 if (!connector
->ycbcr_420_allowed
) {
2221 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
2225 /* YCBCR420 TMDS rate requirement is half the pixel clock */
2226 config
->port_clock
/= 2;
2230 config
->output_format
= INTEL_OUTPUT_FORMAT_YCBCR420
;
2232 /* YCBCR 420 output conversion needs a scaler */
2233 if (skl_update_scaler_crtc(config
)) {
2234 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2238 intel_pch_panel_fitting(intel_crtc
, config
,
2239 DRM_MODE_SCALE_FULLSCREEN
);
2244 int intel_hdmi_compute_config(struct intel_encoder
*encoder
,
2245 struct intel_crtc_state
*pipe_config
,
2246 struct drm_connector_state
*conn_state
)
2248 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
2249 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2250 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
2251 struct drm_connector
*connector
= conn_state
->connector
;
2252 struct drm_scdc
*scdc
= &connector
->display_info
.hdmi
.scdc
;
2253 struct intel_digital_connector_state
*intel_conn_state
=
2254 to_intel_digital_connector_state(conn_state
);
2255 int clock_8bpc
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
2256 int clock_10bpc
= clock_8bpc
* 5 / 4;
2257 int clock_12bpc
= clock_8bpc
* 3 / 2;
2259 bool force_dvi
= intel_conn_state
->force_audio
== HDMI_AUDIO_OFF_DVI
;
2261 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
2264 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
2265 pipe_config
->has_hdmi_sink
= !force_dvi
&& intel_hdmi
->has_hdmi_sink
;
2267 if (pipe_config
->has_hdmi_sink
)
2268 pipe_config
->has_infoframe
= true;
2270 if (intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_AUTO
) {
2271 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2272 pipe_config
->limited_color_range
=
2273 pipe_config
->has_hdmi_sink
&&
2274 drm_default_rgb_quant_range(adjusted_mode
) ==
2275 HDMI_QUANTIZATION_RANGE_LIMITED
;
2277 pipe_config
->limited_color_range
=
2278 intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_LIMITED
;
2281 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
) {
2282 pipe_config
->pixel_multiplier
= 2;
2288 if (drm_mode_is_420_only(&connector
->display_info
, adjusted_mode
)) {
2289 if (!intel_hdmi_ycbcr420_config(connector
, pipe_config
,
2290 &clock_12bpc
, &clock_10bpc
,
2292 DRM_ERROR("Can't support YCBCR420 output\n");
2297 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_DDI(dev_priv
))
2298 pipe_config
->has_pch_encoder
= true;
2300 if (pipe_config
->has_hdmi_sink
) {
2301 if (intel_conn_state
->force_audio
== HDMI_AUDIO_AUTO
)
2302 pipe_config
->has_audio
= intel_hdmi
->has_audio
;
2304 pipe_config
->has_audio
=
2305 intel_conn_state
->force_audio
== HDMI_AUDIO_ON
;
2309 * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need
2310 * to check that the higher clock still fits within limits.
2312 if (hdmi_deep_color_possible(pipe_config
, 12) &&
2313 hdmi_port_clock_valid(intel_hdmi
, clock_12bpc
,
2314 true, force_dvi
) == MODE_OK
) {
2315 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
2318 /* Need to adjust the port link by 1.5x for 12bpc. */
2319 pipe_config
->port_clock
= clock_12bpc
;
2320 } else if (hdmi_deep_color_possible(pipe_config
, 10) &&
2321 hdmi_port_clock_valid(intel_hdmi
, clock_10bpc
,
2322 true, force_dvi
) == MODE_OK
) {
2323 DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n");
2324 desired_bpp
= 10 * 3;
2326 /* Need to adjust the port link by 1.25x for 10bpc. */
2327 pipe_config
->port_clock
= clock_10bpc
;
2329 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
2332 pipe_config
->port_clock
= clock_8bpc
;
2335 if (!pipe_config
->bw_constrained
) {
2336 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp
);
2337 pipe_config
->pipe_bpp
= desired_bpp
;
2340 if (hdmi_port_clock_valid(intel_hdmi
, pipe_config
->port_clock
,
2341 false, force_dvi
) != MODE_OK
) {
2342 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
2346 /* Set user selected PAR to incoming mode's member */
2347 adjusted_mode
->picture_aspect_ratio
= conn_state
->picture_aspect_ratio
;
2349 pipe_config
->lane_count
= 4;
2351 if (scdc
->scrambling
.supported
&& (INTEL_GEN(dev_priv
) >= 10 ||
2352 IS_GEMINILAKE(dev_priv
))) {
2353 if (scdc
->scrambling
.low_rates
)
2354 pipe_config
->hdmi_scrambling
= true;
2356 if (pipe_config
->port_clock
> 340000) {
2357 pipe_config
->hdmi_scrambling
= true;
2358 pipe_config
->hdmi_high_tmds_clock_ratio
= true;
2362 intel_hdmi_compute_gcp_infoframe(encoder
, pipe_config
, conn_state
);
2364 if (!intel_hdmi_compute_avi_infoframe(encoder
, pipe_config
, conn_state
)) {
2365 DRM_DEBUG_KMS("bad AVI infoframe\n");
2369 if (!intel_hdmi_compute_spd_infoframe(encoder
, pipe_config
, conn_state
)) {
2370 DRM_DEBUG_KMS("bad SPD infoframe\n");
2374 if (!intel_hdmi_compute_hdmi_infoframe(encoder
, pipe_config
, conn_state
)) {
2375 DRM_DEBUG_KMS("bad HDMI infoframe\n");
2383 intel_hdmi_unset_edid(struct drm_connector
*connector
)
2385 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
2387 intel_hdmi
->has_hdmi_sink
= false;
2388 intel_hdmi
->has_audio
= false;
2390 intel_hdmi
->dp_dual_mode
.type
= DRM_DP_DUAL_MODE_NONE
;
2391 intel_hdmi
->dp_dual_mode
.max_tmds_clock
= 0;
2393 kfree(to_intel_connector(connector
)->detect_edid
);
2394 to_intel_connector(connector
)->detect_edid
= NULL
;
2398 intel_hdmi_dp_dual_mode_detect(struct drm_connector
*connector
, bool has_edid
)
2400 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
2401 struct intel_hdmi
*hdmi
= intel_attached_hdmi(connector
);
2402 enum port port
= hdmi_to_dig_port(hdmi
)->base
.port
;
2403 struct i2c_adapter
*adapter
=
2404 intel_gmbus_get_adapter(dev_priv
, hdmi
->ddc_bus
);
2405 enum drm_dp_dual_mode_type type
= drm_dp_dual_mode_detect(adapter
);
2408 * Type 1 DVI adaptors are not required to implement any
2409 * registers, so we can't always detect their presence.
2410 * Ideally we should be able to check the state of the
2411 * CONFIG1 pin, but no such luck on our hardware.
2413 * The only method left to us is to check the VBT to see
2414 * if the port is a dual mode capable DP port. But let's
2415 * only do that when we sucesfully read the EDID, to avoid
2416 * confusing log messages about DP dual mode adaptors when
2417 * there's nothing connected to the port.
2419 if (type
== DRM_DP_DUAL_MODE_UNKNOWN
) {
2420 /* An overridden EDID imply that we want this port for testing.
2421 * Make sure not to set limits for that port.
2423 if (has_edid
&& !connector
->override_edid
&&
2424 intel_bios_is_port_dp_dual_mode(dev_priv
, port
)) {
2425 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
2426 type
= DRM_DP_DUAL_MODE_TYPE1_DVI
;
2428 type
= DRM_DP_DUAL_MODE_NONE
;
2432 if (type
== DRM_DP_DUAL_MODE_NONE
)
2435 hdmi
->dp_dual_mode
.type
= type
;
2436 hdmi
->dp_dual_mode
.max_tmds_clock
=
2437 drm_dp_dual_mode_max_tmds_clock(type
, adapter
);
2439 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2440 drm_dp_get_dual_mode_type_name(type
),
2441 hdmi
->dp_dual_mode
.max_tmds_clock
);
2445 intel_hdmi_set_edid(struct drm_connector
*connector
)
2447 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
2448 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
2449 intel_wakeref_t wakeref
;
2451 bool connected
= false;
2452 struct i2c_adapter
*i2c
;
2454 wakeref
= intel_display_power_get(dev_priv
, POWER_DOMAIN_GMBUS
);
2456 i2c
= intel_gmbus_get_adapter(dev_priv
, intel_hdmi
->ddc_bus
);
2458 edid
= drm_get_edid(connector
, i2c
);
2460 if (!edid
&& !intel_gmbus_is_forced_bit(i2c
)) {
2461 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2462 intel_gmbus_force_bit(i2c
, true);
2463 edid
= drm_get_edid(connector
, i2c
);
2464 intel_gmbus_force_bit(i2c
, false);
2467 intel_hdmi_dp_dual_mode_detect(connector
, edid
!= NULL
);
2469 intel_display_power_put(dev_priv
, POWER_DOMAIN_GMBUS
, wakeref
);
2471 to_intel_connector(connector
)->detect_edid
= edid
;
2472 if (edid
&& edid
->input
& DRM_EDID_INPUT_DIGITAL
) {
2473 intel_hdmi
->has_audio
= drm_detect_monitor_audio(edid
);
2474 intel_hdmi
->has_hdmi_sink
= drm_detect_hdmi_monitor(edid
);
2479 cec_notifier_set_phys_addr_from_edid(intel_hdmi
->cec_notifier
, edid
);
2484 static enum drm_connector_status
2485 intel_hdmi_detect(struct drm_connector
*connector
, bool force
)
2487 enum drm_connector_status status
= connector_status_disconnected
;
2488 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
2489 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
2490 struct intel_encoder
*encoder
= &hdmi_to_dig_port(intel_hdmi
)->base
;
2491 intel_wakeref_t wakeref
;
2493 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2494 connector
->base
.id
, connector
->name
);
2496 wakeref
= intel_display_power_get(dev_priv
, POWER_DOMAIN_GMBUS
);
2498 if (INTEL_GEN(dev_priv
) >= 11 &&
2499 !intel_digital_port_connected(encoder
))
2502 intel_hdmi_unset_edid(connector
);
2504 if (intel_hdmi_set_edid(connector
))
2505 status
= connector_status_connected
;
2508 intel_display_power_put(dev_priv
, POWER_DOMAIN_GMBUS
, wakeref
);
2510 if (status
!= connector_status_connected
)
2511 cec_notifier_phys_addr_invalidate(intel_hdmi
->cec_notifier
);
2517 intel_hdmi_force(struct drm_connector
*connector
)
2519 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2520 connector
->base
.id
, connector
->name
);
2522 intel_hdmi_unset_edid(connector
);
2524 if (connector
->status
!= connector_status_connected
)
2527 intel_hdmi_set_edid(connector
);
2530 static int intel_hdmi_get_modes(struct drm_connector
*connector
)
2534 edid
= to_intel_connector(connector
)->detect_edid
;
2538 return intel_connector_update_modes(connector
, edid
);
2541 static void intel_hdmi_pre_enable(struct intel_encoder
*encoder
,
2542 const struct intel_crtc_state
*pipe_config
,
2543 const struct drm_connector_state
*conn_state
)
2545 struct intel_digital_port
*intel_dig_port
=
2546 enc_to_dig_port(&encoder
->base
);
2548 intel_hdmi_prepare(encoder
, pipe_config
);
2550 intel_dig_port
->set_infoframes(encoder
,
2551 pipe_config
->has_infoframe
,
2552 pipe_config
, conn_state
);
2555 static void vlv_hdmi_pre_enable(struct intel_encoder
*encoder
,
2556 const struct intel_crtc_state
*pipe_config
,
2557 const struct drm_connector_state
*conn_state
)
2559 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2560 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2562 vlv_phy_pre_encoder_enable(encoder
, pipe_config
);
2565 vlv_set_phy_signal_level(encoder
, 0x2b245f5f, 0x00002000, 0x5578b83a,
2568 dport
->set_infoframes(encoder
,
2569 pipe_config
->has_infoframe
,
2570 pipe_config
, conn_state
);
2572 g4x_enable_hdmi(encoder
, pipe_config
, conn_state
);
2574 vlv_wait_port_ready(dev_priv
, dport
, 0x0);
2577 static void vlv_hdmi_pre_pll_enable(struct intel_encoder
*encoder
,
2578 const struct intel_crtc_state
*pipe_config
,
2579 const struct drm_connector_state
*conn_state
)
2581 intel_hdmi_prepare(encoder
, pipe_config
);
2583 vlv_phy_pre_pll_enable(encoder
, pipe_config
);
2586 static void chv_hdmi_pre_pll_enable(struct intel_encoder
*encoder
,
2587 const struct intel_crtc_state
*pipe_config
,
2588 const struct drm_connector_state
*conn_state
)
2590 intel_hdmi_prepare(encoder
, pipe_config
);
2592 chv_phy_pre_pll_enable(encoder
, pipe_config
);
2595 static void chv_hdmi_post_pll_disable(struct intel_encoder
*encoder
,
2596 const struct intel_crtc_state
*old_crtc_state
,
2597 const struct drm_connector_state
*old_conn_state
)
2599 chv_phy_post_pll_disable(encoder
, old_crtc_state
);
2602 static void vlv_hdmi_post_disable(struct intel_encoder
*encoder
,
2603 const struct intel_crtc_state
*old_crtc_state
,
2604 const struct drm_connector_state
*old_conn_state
)
2606 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2607 vlv_phy_reset_lanes(encoder
, old_crtc_state
);
2610 static void chv_hdmi_post_disable(struct intel_encoder
*encoder
,
2611 const struct intel_crtc_state
*old_crtc_state
,
2612 const struct drm_connector_state
*old_conn_state
)
2614 struct drm_device
*dev
= encoder
->base
.dev
;
2615 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2617 vlv_dpio_get(dev_priv
);
2619 /* Assert data lane reset */
2620 chv_data_lane_soft_reset(encoder
, old_crtc_state
, true);
2622 vlv_dpio_put(dev_priv
);
2625 static void chv_hdmi_pre_enable(struct intel_encoder
*encoder
,
2626 const struct intel_crtc_state
*pipe_config
,
2627 const struct drm_connector_state
*conn_state
)
2629 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2630 struct drm_device
*dev
= encoder
->base
.dev
;
2631 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2633 chv_phy_pre_encoder_enable(encoder
, pipe_config
);
2635 /* FIXME: Program the support xxx V-dB */
2637 chv_set_phy_signal_level(encoder
, 128, 102, false);
2639 dport
->set_infoframes(encoder
,
2640 pipe_config
->has_infoframe
,
2641 pipe_config
, conn_state
);
2643 g4x_enable_hdmi(encoder
, pipe_config
, conn_state
);
2645 vlv_wait_port_ready(dev_priv
, dport
, 0x0);
2647 /* Second common lane will stay alive on its own now */
2648 chv_phy_release_cl2_override(encoder
);
2652 intel_hdmi_connector_register(struct drm_connector
*connector
)
2656 ret
= intel_connector_register(connector
);
2660 i915_debugfs_connector_add(connector
);
2665 static void intel_hdmi_destroy(struct drm_connector
*connector
)
2667 if (intel_attached_hdmi(connector
)->cec_notifier
)
2668 cec_notifier_put(intel_attached_hdmi(connector
)->cec_notifier
);
2670 intel_connector_destroy(connector
);
2673 static const struct drm_connector_funcs intel_hdmi_connector_funcs
= {
2674 .detect
= intel_hdmi_detect
,
2675 .force
= intel_hdmi_force
,
2676 .fill_modes
= drm_helper_probe_single_connector_modes
,
2677 .atomic_get_property
= intel_digital_connector_atomic_get_property
,
2678 .atomic_set_property
= intel_digital_connector_atomic_set_property
,
2679 .late_register
= intel_hdmi_connector_register
,
2680 .early_unregister
= intel_connector_unregister
,
2681 .destroy
= intel_hdmi_destroy
,
2682 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
2683 .atomic_duplicate_state
= intel_digital_connector_duplicate_state
,
2686 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs
= {
2687 .get_modes
= intel_hdmi_get_modes
,
2688 .mode_valid
= intel_hdmi_mode_valid
,
2689 .atomic_check
= intel_digital_connector_atomic_check
,
2692 static const struct drm_encoder_funcs intel_hdmi_enc_funcs
= {
2693 .destroy
= intel_encoder_destroy
,
2697 intel_hdmi_add_properties(struct intel_hdmi
*intel_hdmi
, struct drm_connector
*connector
)
2699 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
2700 struct intel_digital_port
*intel_dig_port
=
2701 hdmi_to_dig_port(intel_hdmi
);
2703 intel_attach_force_audio_property(connector
);
2704 intel_attach_broadcast_rgb_property(connector
);
2705 intel_attach_aspect_ratio_property(connector
);
2708 * Attach Colorspace property for Non LSPCON based device
2709 * ToDo: This needs to be extended for LSPCON implementation
2710 * as well. Will be implemented separately.
2712 if (!intel_dig_port
->lspcon
.active
)
2713 intel_attach_colorspace_property(connector
);
2715 drm_connector_attach_content_type_property(connector
);
2716 connector
->state
->picture_aspect_ratio
= HDMI_PICTURE_ASPECT_NONE
;
2718 if (!HAS_GMCH(dev_priv
))
2719 drm_connector_attach_max_bpc_property(connector
, 8, 12);
2723 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2724 * @encoder: intel_encoder
2725 * @connector: drm_connector
2726 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2727 * or reset the high tmds clock ratio for scrambling
2728 * @scrambling: bool to Indicate if the function needs to set or reset
2731 * This function handles scrambling on HDMI 2.0 capable sinks.
2732 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2733 * it enables scrambling. This should be called before enabling the HDMI
2734 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2735 * detect a scrambled clock within 100 ms.
2738 * True on success, false on failure.
2740 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder
*encoder
,
2741 struct drm_connector
*connector
,
2742 bool high_tmds_clock_ratio
,
2745 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2746 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
2747 struct drm_scrambling
*sink_scrambling
=
2748 &connector
->display_info
.hdmi
.scdc
.scrambling
;
2749 struct i2c_adapter
*adapter
=
2750 intel_gmbus_get_adapter(dev_priv
, intel_hdmi
->ddc_bus
);
2752 if (!sink_scrambling
->supported
)
2755 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2756 connector
->base
.id
, connector
->name
,
2757 yesno(scrambling
), high_tmds_clock_ratio
? 40 : 10);
2759 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2760 return drm_scdc_set_high_tmds_clock_ratio(adapter
,
2761 high_tmds_clock_ratio
) &&
2762 drm_scdc_set_scrambling(adapter
, scrambling
);
2765 static u8
chv_port_to_ddc_pin(struct drm_i915_private
*dev_priv
, enum port port
)
2771 ddc_pin
= GMBUS_PIN_DPB
;
2774 ddc_pin
= GMBUS_PIN_DPC
;
2777 ddc_pin
= GMBUS_PIN_DPD_CHV
;
2781 ddc_pin
= GMBUS_PIN_DPB
;
2787 static u8
bxt_port_to_ddc_pin(struct drm_i915_private
*dev_priv
, enum port port
)
2793 ddc_pin
= GMBUS_PIN_1_BXT
;
2796 ddc_pin
= GMBUS_PIN_2_BXT
;
2800 ddc_pin
= GMBUS_PIN_1_BXT
;
2806 static u8
cnp_port_to_ddc_pin(struct drm_i915_private
*dev_priv
,
2813 ddc_pin
= GMBUS_PIN_1_BXT
;
2816 ddc_pin
= GMBUS_PIN_2_BXT
;
2819 ddc_pin
= GMBUS_PIN_4_CNP
;
2822 ddc_pin
= GMBUS_PIN_3_BXT
;
2826 ddc_pin
= GMBUS_PIN_1_BXT
;
2832 static u8
icl_port_to_ddc_pin(struct drm_i915_private
*dev_priv
, enum port port
)
2838 ddc_pin
= GMBUS_PIN_1_BXT
;
2841 ddc_pin
= GMBUS_PIN_2_BXT
;
2844 ddc_pin
= GMBUS_PIN_9_TC1_ICP
;
2847 ddc_pin
= GMBUS_PIN_10_TC2_ICP
;
2850 ddc_pin
= GMBUS_PIN_11_TC3_ICP
;
2853 ddc_pin
= GMBUS_PIN_12_TC4_ICP
;
2857 ddc_pin
= GMBUS_PIN_2_BXT
;
2863 static u8
g4x_port_to_ddc_pin(struct drm_i915_private
*dev_priv
,
2870 ddc_pin
= GMBUS_PIN_DPB
;
2873 ddc_pin
= GMBUS_PIN_DPC
;
2876 ddc_pin
= GMBUS_PIN_DPD
;
2880 ddc_pin
= GMBUS_PIN_DPB
;
2886 static u8
intel_hdmi_ddc_pin(struct drm_i915_private
*dev_priv
,
2889 const struct ddi_vbt_port_info
*info
=
2890 &dev_priv
->vbt
.ddi_port_info
[port
];
2893 if (info
->alternate_ddc_pin
) {
2894 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
2895 info
->alternate_ddc_pin
, port_name(port
));
2896 return info
->alternate_ddc_pin
;
2899 if (HAS_PCH_ICP(dev_priv
))
2900 ddc_pin
= icl_port_to_ddc_pin(dev_priv
, port
);
2901 else if (HAS_PCH_CNP(dev_priv
))
2902 ddc_pin
= cnp_port_to_ddc_pin(dev_priv
, port
);
2903 else if (IS_GEN9_LP(dev_priv
))
2904 ddc_pin
= bxt_port_to_ddc_pin(dev_priv
, port
);
2905 else if (IS_CHERRYVIEW(dev_priv
))
2906 ddc_pin
= chv_port_to_ddc_pin(dev_priv
, port
);
2908 ddc_pin
= g4x_port_to_ddc_pin(dev_priv
, port
);
2910 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
2911 ddc_pin
, port_name(port
));
2916 void intel_infoframe_init(struct intel_digital_port
*intel_dig_port
)
2918 struct drm_i915_private
*dev_priv
=
2919 to_i915(intel_dig_port
->base
.base
.dev
);
2921 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2922 intel_dig_port
->write_infoframe
= vlv_write_infoframe
;
2923 intel_dig_port
->read_infoframe
= vlv_read_infoframe
;
2924 intel_dig_port
->set_infoframes
= vlv_set_infoframes
;
2925 intel_dig_port
->infoframes_enabled
= vlv_infoframes_enabled
;
2926 } else if (IS_G4X(dev_priv
)) {
2927 intel_dig_port
->write_infoframe
= g4x_write_infoframe
;
2928 intel_dig_port
->read_infoframe
= g4x_read_infoframe
;
2929 intel_dig_port
->set_infoframes
= g4x_set_infoframes
;
2930 intel_dig_port
->infoframes_enabled
= g4x_infoframes_enabled
;
2931 } else if (HAS_DDI(dev_priv
)) {
2932 if (intel_dig_port
->lspcon
.active
) {
2933 intel_dig_port
->write_infoframe
= lspcon_write_infoframe
;
2934 intel_dig_port
->read_infoframe
= lspcon_read_infoframe
;
2935 intel_dig_port
->set_infoframes
= lspcon_set_infoframes
;
2936 intel_dig_port
->infoframes_enabled
= lspcon_infoframes_enabled
;
2938 intel_dig_port
->write_infoframe
= hsw_write_infoframe
;
2939 intel_dig_port
->read_infoframe
= hsw_read_infoframe
;
2940 intel_dig_port
->set_infoframes
= hsw_set_infoframes
;
2941 intel_dig_port
->infoframes_enabled
= hsw_infoframes_enabled
;
2943 } else if (HAS_PCH_IBX(dev_priv
)) {
2944 intel_dig_port
->write_infoframe
= ibx_write_infoframe
;
2945 intel_dig_port
->read_infoframe
= ibx_read_infoframe
;
2946 intel_dig_port
->set_infoframes
= ibx_set_infoframes
;
2947 intel_dig_port
->infoframes_enabled
= ibx_infoframes_enabled
;
2949 intel_dig_port
->write_infoframe
= cpt_write_infoframe
;
2950 intel_dig_port
->read_infoframe
= cpt_read_infoframe
;
2951 intel_dig_port
->set_infoframes
= cpt_set_infoframes
;
2952 intel_dig_port
->infoframes_enabled
= cpt_infoframes_enabled
;
2956 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
2957 struct intel_connector
*intel_connector
)
2959 struct drm_connector
*connector
= &intel_connector
->base
;
2960 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
2961 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2962 struct drm_device
*dev
= intel_encoder
->base
.dev
;
2963 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2964 enum port port
= intel_encoder
->port
;
2966 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2969 if (WARN(intel_dig_port
->max_lanes
< 4,
2970 "Not enough lanes (%d) for HDMI on port %c\n",
2971 intel_dig_port
->max_lanes
, port_name(port
)))
2974 drm_connector_init(dev
, connector
, &intel_hdmi_connector_funcs
,
2975 DRM_MODE_CONNECTOR_HDMIA
);
2976 drm_connector_helper_add(connector
, &intel_hdmi_connector_helper_funcs
);
2978 connector
->interlace_allowed
= 1;
2979 connector
->doublescan_allowed
= 0;
2980 connector
->stereo_allowed
= 1;
2982 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
))
2983 connector
->ycbcr_420_allowed
= true;
2985 intel_hdmi
->ddc_bus
= intel_hdmi_ddc_pin(dev_priv
, port
);
2987 if (WARN_ON(port
== PORT_A
))
2989 intel_encoder
->hpd_pin
= intel_hpd_pin_default(dev_priv
, port
);
2991 if (HAS_DDI(dev_priv
))
2992 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
2994 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
2996 intel_hdmi_add_properties(intel_hdmi
, connector
);
2998 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
2999 intel_hdmi
->attached_connector
= intel_connector
;
3001 if (is_hdcp_supported(dev_priv
, port
)) {
3002 int ret
= intel_hdcp_init(intel_connector
,
3003 &intel_hdmi_hdcp_shim
);
3005 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
3008 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3009 * 0xd. Failure to do so will result in spurious interrupts being
3010 * generated on the port when a cable is not attached.
3012 if (IS_G45(dev_priv
)) {
3013 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
3014 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
3017 intel_hdmi
->cec_notifier
= cec_notifier_get_conn(dev
->dev
,
3018 port_identifier(port
));
3019 if (!intel_hdmi
->cec_notifier
)
3020 DRM_DEBUG_KMS("CEC notifier get failed\n");
3023 void intel_hdmi_init(struct drm_i915_private
*dev_priv
,
3024 i915_reg_t hdmi_reg
, enum port port
)
3026 struct intel_digital_port
*intel_dig_port
;
3027 struct intel_encoder
*intel_encoder
;
3028 struct intel_connector
*intel_connector
;
3030 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
3031 if (!intel_dig_port
)
3034 intel_connector
= intel_connector_alloc();
3035 if (!intel_connector
) {
3036 kfree(intel_dig_port
);
3040 intel_encoder
= &intel_dig_port
->base
;
3042 drm_encoder_init(&dev_priv
->drm
, &intel_encoder
->base
,
3043 &intel_hdmi_enc_funcs
, DRM_MODE_ENCODER_TMDS
,
3044 "HDMI %c", port_name(port
));
3046 intel_encoder
->hotplug
= intel_encoder_hotplug
;
3047 intel_encoder
->compute_config
= intel_hdmi_compute_config
;
3048 if (HAS_PCH_SPLIT(dev_priv
)) {
3049 intel_encoder
->disable
= pch_disable_hdmi
;
3050 intel_encoder
->post_disable
= pch_post_disable_hdmi
;
3052 intel_encoder
->disable
= g4x_disable_hdmi
;
3054 intel_encoder
->get_hw_state
= intel_hdmi_get_hw_state
;
3055 intel_encoder
->get_config
= intel_hdmi_get_config
;
3056 if (IS_CHERRYVIEW(dev_priv
)) {
3057 intel_encoder
->pre_pll_enable
= chv_hdmi_pre_pll_enable
;
3058 intel_encoder
->pre_enable
= chv_hdmi_pre_enable
;
3059 intel_encoder
->enable
= vlv_enable_hdmi
;
3060 intel_encoder
->post_disable
= chv_hdmi_post_disable
;
3061 intel_encoder
->post_pll_disable
= chv_hdmi_post_pll_disable
;
3062 } else if (IS_VALLEYVIEW(dev_priv
)) {
3063 intel_encoder
->pre_pll_enable
= vlv_hdmi_pre_pll_enable
;
3064 intel_encoder
->pre_enable
= vlv_hdmi_pre_enable
;
3065 intel_encoder
->enable
= vlv_enable_hdmi
;
3066 intel_encoder
->post_disable
= vlv_hdmi_post_disable
;
3068 intel_encoder
->pre_enable
= intel_hdmi_pre_enable
;
3069 if (HAS_PCH_CPT(dev_priv
))
3070 intel_encoder
->enable
= cpt_enable_hdmi
;
3071 else if (HAS_PCH_IBX(dev_priv
))
3072 intel_encoder
->enable
= ibx_enable_hdmi
;
3074 intel_encoder
->enable
= g4x_enable_hdmi
;
3077 intel_encoder
->type
= INTEL_OUTPUT_HDMI
;
3078 intel_encoder
->power_domain
= intel_port_to_power_domain(port
);
3079 intel_encoder
->port
= port
;
3080 if (IS_CHERRYVIEW(dev_priv
)) {
3082 intel_encoder
->crtc_mask
= 1 << 2;
3084 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
3086 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
3088 intel_encoder
->cloneable
= 1 << INTEL_OUTPUT_ANALOG
;
3090 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
3091 * to work on real hardware. And since g4x can send infoframes to
3092 * only one port anyway, nothing is lost by allowing it.
3094 if (IS_G4X(dev_priv
))
3095 intel_encoder
->cloneable
|= 1 << INTEL_OUTPUT_HDMI
;
3097 intel_dig_port
->hdmi
.hdmi_reg
= hdmi_reg
;
3098 intel_dig_port
->dp
.output_reg
= INVALID_MMIO_REG
;
3099 intel_dig_port
->max_lanes
= 4;
3101 intel_infoframe_init(intel_dig_port
);
3103 intel_dig_port
->aux_ch
= intel_bios_port_aux_ch(dev_priv
, port
);
3104 intel_hdmi_init_connector(intel_dig_port
, intel_connector
);