drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_edid.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39
  40 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  41 {
  42         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  43 }
  44
  45 static void
  46 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  47 {
  48         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  49         struct drm_i915_private *dev_priv = dev->dev_private;
  50         uint32_t enabled_bits;
  51
  52         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  53
  54         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  55              "HDMI port enabled, expecting disabled\n");
  56 }
  57
  58 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  59 {
  60         struct intel_digital_port *intel_dig_port =
  61                 container_of(encoder, struct intel_digital_port, base.base);
  62         return &intel_dig_port->hdmi;
  63 }
  64
  65 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  66 {
  67         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  68 }
  69
  70 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  71 {
  72         switch (type) {
  73         case HDMI_INFOFRAME_TYPE_AVI:
  74                 return VIDEO_DIP_SELECT_AVI;
  75         case HDMI_INFOFRAME_TYPE_SPD:
  76                 return VIDEO_DIP_SELECT_SPD;
  77         case HDMI_INFOFRAME_TYPE_VENDOR:
  78                 return VIDEO_DIP_SELECT_VENDOR;
  79         default:
  80                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  81                 return 0;
  82         }
  83 }
  84
  85 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  86 {
  87         switch (type) {
  88         case HDMI_INFOFRAME_TYPE_AVI:
  89                 return VIDEO_DIP_ENABLE_AVI;
  90         case HDMI_INFOFRAME_TYPE_SPD:
  91                 return VIDEO_DIP_ENABLE_SPD;
  92         case HDMI_INFOFRAME_TYPE_VENDOR:
  93                 return VIDEO_DIP_ENABLE_VENDOR;
  94         default:
  95                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  96                 return 0;
  97         }
  98 }
  99
 100 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 101 {
 102         switch (type) {
 103         case HDMI_INFOFRAME_TYPE_AVI:
 104                 return VIDEO_DIP_ENABLE_AVI_HSW;
 105         case HDMI_INFOFRAME_TYPE_SPD:
 106                 return VIDEO_DIP_ENABLE_SPD_HSW;
 107         case HDMI_INFOFRAME_TYPE_VENDOR:
 108                 return VIDEO_DIP_ENABLE_VS_HSW;
 109         default:
 110                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 111                 return 0;
 112         }
 113 }
 114
 115 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
 116                                   enum transcoder cpu_transcoder,
 117                                   struct drm_i915_private *dev_priv)
 118 {
 119         switch (type) {
 120         case HDMI_INFOFRAME_TYPE_AVI:
 121                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
 122         case HDMI_INFOFRAME_TYPE_SPD:
 123                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
 124         case HDMI_INFOFRAME_TYPE_VENDOR:
 125                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
 126         default:
 127                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 128                 return 0;
 129         }
 130 }
 131
 132 static void g4x_write_infoframe(struct drm_encoder *encoder,
 133                                 enum hdmi_infoframe_type type,
 134                                 const void *frame, ssize_t len)
 135 {
 136         const uint32_t *data = frame;
 137         struct drm_device *dev = encoder->dev;
 138         struct drm_i915_private *dev_priv = dev->dev_private;
 139         u32 val = I915_READ(VIDEO_DIP_CTL);
 140         int i;
 141
 142         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 143
 144         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 145         val |= g4x_infoframe_index(type);
 146
 147         val &= ~g4x_infoframe_enable(type);
 148
 149         I915_WRITE(VIDEO_DIP_CTL, val);
 150
 151         mmiowb();
 152         for (i = 0; i < len; i += 4) {
 153                 I915_WRITE(VIDEO_DIP_DATA, *data);
 154                 data++;
 155         }
 156         /* Write every possible data byte to force correct ECC calculation. */
 157         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 158                 I915_WRITE(VIDEO_DIP_DATA, 0);
 159         mmiowb();
 160
 161         val |= g4x_infoframe_enable(type);
 162         val &= ~VIDEO_DIP_FREQ_MASK;
 163         val |= VIDEO_DIP_FREQ_VSYNC;
 164
 165         I915_WRITE(VIDEO_DIP_CTL, val);
 166         POSTING_READ(VIDEO_DIP_CTL);
 167 }
 168
 169 static void ibx_write_infoframe(struct drm_encoder *encoder,
 170                                 enum hdmi_infoframe_type type,
 171                                 const void *frame, ssize_t len)
 172 {
 173         const uint32_t *data = frame;
 174         struct drm_device *dev = encoder->dev;
 175         struct drm_i915_private *dev_priv = dev->dev_private;
 176         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 177         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 178         u32 val = I915_READ(reg);
 179
 180         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 181
 182         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 183         val |= g4x_infoframe_index(type);
 184
 185         val &= ~g4x_infoframe_enable(type);
 186
 187         I915_WRITE(reg, val);
 188
 189         mmiowb();
 190         for (i = 0; i < len; i += 4) {
 191                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 192                 data++;
 193         }
 194         /* Write every possible data byte to force correct ECC calculation. */
 195         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 196                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 197         mmiowb();
 198
 199         val |= g4x_infoframe_enable(type);
 200         val &= ~VIDEO_DIP_FREQ_MASK;
 201         val |= VIDEO_DIP_FREQ_VSYNC;
 202
 203         I915_WRITE(reg, val);
 204         POSTING_READ(reg);
 205 }
 206
 207 static void cpt_write_infoframe(struct drm_encoder *encoder,
 208                                 enum hdmi_infoframe_type type,
 209                                 const void *frame, ssize_t len)
 210 {
 211         const uint32_t *data = frame;
 212         struct drm_device *dev = encoder->dev;
 213         struct drm_i915_private *dev_priv = dev->dev_private;
 214         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 215         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 216         u32 val = I915_READ(reg);
 217
 218         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 219
 220         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 221         val |= g4x_infoframe_index(type);
 222
 223         /* The DIP control register spec says that we need to update the AVI
 224          * infoframe without clearing its enable bit */
 225         if (type != HDMI_INFOFRAME_TYPE_AVI)
 226                 val &= ~g4x_infoframe_enable(type);
 227
 228         I915_WRITE(reg, val);
 229
 230         mmiowb();
 231         for (i = 0; i < len; i += 4) {
 232                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 233                 data++;
 234         }
 235         /* Write every possible data byte to force correct ECC calculation. */
 236         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 237                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 238         mmiowb();
 239
 240         val |= g4x_infoframe_enable(type);
 241         val &= ~VIDEO_DIP_FREQ_MASK;
 242         val |= VIDEO_DIP_FREQ_VSYNC;
 243
 244         I915_WRITE(reg, val);
 245         POSTING_READ(reg);
 246 }
 247
 248 static void vlv_write_infoframe(struct drm_encoder *encoder,
 249                                 enum hdmi_infoframe_type type,
 250                                 const void *frame, ssize_t len)
 251 {
 252         const uint32_t *data = frame;
 253         struct drm_device *dev = encoder->dev;
 254         struct drm_i915_private *dev_priv = dev->dev_private;
 255         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 256         int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 257         u32 val = I915_READ(reg);
 258
 259         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 260
 261         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 262         val |= g4x_infoframe_index(type);
 263
 264         val &= ~g4x_infoframe_enable(type);
 265
 266         I915_WRITE(reg, val);
 267
 268         mmiowb();
 269         for (i = 0; i < len; i += 4) {
 270                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 271                 data++;
 272         }
 273         /* Write every possible data byte to force correct ECC calculation. */
 274         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 275                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 276         mmiowb();
 277
 278         val |= g4x_infoframe_enable(type);
 279         val &= ~VIDEO_DIP_FREQ_MASK;
 280         val |= VIDEO_DIP_FREQ_VSYNC;
 281
 282         I915_WRITE(reg, val);
 283         POSTING_READ(reg);
 284 }
 285
 286 static void hsw_write_infoframe(struct drm_encoder *encoder,
 287                                 enum hdmi_infoframe_type type,
 288                                 const void *frame, ssize_t len)
 289 {
 290         const uint32_t *data = frame;
 291         struct drm_device *dev = encoder->dev;
 292         struct drm_i915_private *dev_priv = dev->dev_private;
 293         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 294         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 295         u32 data_reg;
 296         int i;
 297         u32 val = I915_READ(ctl_reg);
 298
 299         data_reg = hsw_infoframe_data_reg(type,
 300                                           intel_crtc->config.cpu_transcoder,
 301                                           dev_priv);
 302         if (data_reg == 0)
 303                 return;
 304
 305         val &= ~hsw_infoframe_enable(type);
 306         I915_WRITE(ctl_reg, val);
 307
 308         mmiowb();
 309         for (i = 0; i < len; i += 4) {
 310                 I915_WRITE(data_reg + i, *data);
 311                 data++;
 312         }
 313         /* Write every possible data byte to force correct ECC calculation. */
 314         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 315                 I915_WRITE(data_reg + i, 0);
 316         mmiowb();
 317
 318         val |= hsw_infoframe_enable(type);
 319         I915_WRITE(ctl_reg, val);
 320         POSTING_READ(ctl_reg);
 321 }
 322
 323 /*
 324  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 325  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 326  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 327  * used for both technologies.
 328  *
 329  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 330  * DW1:       DB3       | DB2 | DB1 | DB0
 331  * DW2:       DB7       | DB6 | DB5 | DB4
 332  * DW3: ...
 333  *
 334  * (HB is Header Byte, DB is Data Byte)
 335  *
 336  * The hdmi pack() functions don't know about that hardware specific hole so we
 337  * trick them by giving an offset into the buffer and moving back the header
 338  * bytes by one.
 339  */
 340 static void intel_write_infoframe(struct drm_encoder *encoder,
 341                                   union hdmi_infoframe *frame)
 342 {
 343         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 344         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 345         ssize_t len;
 346
 347         /* see comment above for the reason for this offset */
 348         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 349         if (len < 0)
 350                 return;
 351
 352         /* Insert the 'hole' (see big comment above) at position 3 */
 353         buffer[0] = buffer[1];
 354         buffer[1] = buffer[2];
 355         buffer[2] = buffer[3];
 356         buffer[3] = 0;
 357         len++;
 358
 359         intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
 360 }
 361
 362 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 363                                          struct drm_display_mode *adjusted_mode)
 364 {
 365         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 366         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 367         union hdmi_infoframe frame;
 368         int ret;
 369
 370         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 371                                                        adjusted_mode);
 372         if (ret < 0) {
 373                 DRM_ERROR("couldn't fill AVI infoframe\n");
 374                 return;
 375         }
 376
 377         if (intel_hdmi->rgb_quant_range_selectable) {
 378                 if (intel_crtc->config.limited_color_range)
 379                         frame.avi.quantization_range =
 380                                 HDMI_QUANTIZATION_RANGE_LIMITED;
 381                 else
 382                         frame.avi.quantization_range =
 383                                 HDMI_QUANTIZATION_RANGE_FULL;
 384         }
 385
 386         intel_write_infoframe(encoder, &frame);
 387 }
 388
 389 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 390 {
 391         union hdmi_infoframe frame;
 392         int ret;
 393
 394         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 395         if (ret < 0) {
 396                 DRM_ERROR("couldn't fill SPD infoframe\n");
 397                 return;
 398         }
 399
 400         frame.spd.sdi = HDMI_SPD_SDI_PC;
 401
 402         intel_write_infoframe(encoder, &frame);
 403 }
 404
 405 static void
 406 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 407                               struct drm_display_mode *adjusted_mode)
 408 {
 409         union hdmi_infoframe frame;
 410         int ret;
 411
 412         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 413                                                           adjusted_mode);
 414         if (ret < 0)
 415                 return;
 416
 417         intel_write_infoframe(encoder, &frame);
 418 }
 419
 420 static void g4x_set_infoframes(struct drm_encoder *encoder,
 421                                struct drm_display_mode *adjusted_mode)
 422 {
 423         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 424         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 425         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 426         u32 reg = VIDEO_DIP_CTL;
 427         u32 val = I915_READ(reg);
 428         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 429
 430         assert_hdmi_port_disabled(intel_hdmi);
 431
 432         /* If the registers were not initialized yet, they might be zeroes,
 433          * which means we're selecting the AVI DIP and we're setting its
 434          * frequency to once. This seems to really confuse the HW and make
 435          * things stop working (the register spec says the AVI always needs to
 436          * be sent every VSync). So here we avoid writing to the register more
 437          * than we need and also explicitly select the AVI DIP and explicitly
 438          * set its frequency to every VSync. Avoiding to write it twice seems to
 439          * be enough to solve the problem, but being defensive shouldn't hurt us
 440          * either. */
 441         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 442
 443         if (!intel_hdmi->has_hdmi_sink) {
 444                 if (!(val & VIDEO_DIP_ENABLE))
 445                         return;
 446                 val &= ~VIDEO_DIP_ENABLE;
 447                 I915_WRITE(reg, val);
 448                 POSTING_READ(reg);
 449                 return;
 450         }
 451
 452         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 453                 if (val & VIDEO_DIP_ENABLE) {
 454                         val &= ~VIDEO_DIP_ENABLE;
 455                         I915_WRITE(reg, val);
 456                         POSTING_READ(reg);
 457                 }
 458                 val &= ~VIDEO_DIP_PORT_MASK;
 459                 val |= port;
 460         }
 461
 462         val |= VIDEO_DIP_ENABLE;
 463         val &= ~VIDEO_DIP_ENABLE_VENDOR;
 464
 465         I915_WRITE(reg, val);
 466         POSTING_READ(reg);
 467
 468         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 469         intel_hdmi_set_spd_infoframe(encoder);
 470         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 471 }
 472
 473 static void ibx_set_infoframes(struct drm_encoder *encoder,
 474                                struct drm_display_mode *adjusted_mode)
 475 {
 476         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 477         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 478         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 479         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 480         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 481         u32 val = I915_READ(reg);
 482         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 483
 484         assert_hdmi_port_disabled(intel_hdmi);
 485
 486         /* See the big comment in g4x_set_infoframes() */
 487         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 488
 489         if (!intel_hdmi->has_hdmi_sink) {
 490                 if (!(val & VIDEO_DIP_ENABLE))
 491                         return;
 492                 val &= ~VIDEO_DIP_ENABLE;
 493                 I915_WRITE(reg, val);
 494                 POSTING_READ(reg);
 495                 return;
 496         }
 497
 498         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 499                 if (val & VIDEO_DIP_ENABLE) {
 500                         val &= ~VIDEO_DIP_ENABLE;
 501                         I915_WRITE(reg, val);
 502                         POSTING_READ(reg);
 503                 }
 504                 val &= ~VIDEO_DIP_PORT_MASK;
 505                 val |= port;
 506         }
 507
 508         val |= VIDEO_DIP_ENABLE;
 509         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 510                  VIDEO_DIP_ENABLE_GCP);
 511
 512         I915_WRITE(reg, val);
 513         POSTING_READ(reg);
 514
 515         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 516         intel_hdmi_set_spd_infoframe(encoder);
 517         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 518 }
 519
 520 static void cpt_set_infoframes(struct drm_encoder *encoder,
 521                                struct drm_display_mode *adjusted_mode)
 522 {
 523         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 524         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 525         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 526         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 527         u32 val = I915_READ(reg);
 528
 529         assert_hdmi_port_disabled(intel_hdmi);
 530
 531         /* See the big comment in g4x_set_infoframes() */
 532         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 533
 534         if (!intel_hdmi->has_hdmi_sink) {
 535                 if (!(val & VIDEO_DIP_ENABLE))
 536                         return;
 537                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
 538                 I915_WRITE(reg, val);
 539                 POSTING_READ(reg);
 540                 return;
 541         }
 542
 543         /* Set both together, unset both together: see the spec. */
 544         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 545         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 546                  VIDEO_DIP_ENABLE_GCP);
 547
 548         I915_WRITE(reg, val);
 549         POSTING_READ(reg);
 550
 551         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 552         intel_hdmi_set_spd_infoframe(encoder);
 553         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 554 }
 555
 556 static void vlv_set_infoframes(struct drm_encoder *encoder,
 557                                struct drm_display_mode *adjusted_mode)
 558 {
 559         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 560         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 561         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 562         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 563         u32 val = I915_READ(reg);
 564
 565         assert_hdmi_port_disabled(intel_hdmi);
 566
 567         /* See the big comment in g4x_set_infoframes() */
 568         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 569
 570         if (!intel_hdmi->has_hdmi_sink) {
 571                 if (!(val & VIDEO_DIP_ENABLE))
 572                         return;
 573                 val &= ~VIDEO_DIP_ENABLE;
 574                 I915_WRITE(reg, val);
 575                 POSTING_READ(reg);
 576                 return;
 577         }
 578
 579         val |= VIDEO_DIP_ENABLE;
 580         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 581                  VIDEO_DIP_ENABLE_GCP);
 582
 583         I915_WRITE(reg, val);
 584         POSTING_READ(reg);
 585
 586         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 587         intel_hdmi_set_spd_infoframe(encoder);
 588         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 589 }
 590
 591 static void hsw_set_infoframes(struct drm_encoder *encoder,
 592                                struct drm_display_mode *adjusted_mode)
 593 {
 594         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 595         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 596         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 597         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 598         u32 val = I915_READ(reg);
 599
 600         assert_hdmi_port_disabled(intel_hdmi);
 601
 602         if (!intel_hdmi->has_hdmi_sink) {
 603                 I915_WRITE(reg, 0);
 604                 POSTING_READ(reg);
 605                 return;
 606         }
 607
 608         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 609                  VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
 610
 611         I915_WRITE(reg, val);
 612         POSTING_READ(reg);
 613
 614         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 615         intel_hdmi_set_spd_infoframe(encoder);
 616         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 617 }
 618
 619 static void intel_hdmi_mode_set(struct intel_encoder *encoder)
 620 {
 621         struct drm_device *dev = encoder->base.dev;
 622         struct drm_i915_private *dev_priv = dev->dev_private;
 623         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 624         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 625         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 626         u32 hdmi_val;
 627
 628         hdmi_val = SDVO_ENCODING_HDMI;
 629         if (!HAS_PCH_SPLIT(dev))
 630                 hdmi_val |= intel_hdmi->color_range;
 631         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 632                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 633         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 634                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 635
 636         if (crtc->config.pipe_bpp > 24)
 637                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 638         else
 639                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 640
 641         /* Required on CPT */
 642         if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
 643                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 644
 645         if (intel_hdmi->has_audio) {
 646                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 647                                  pipe_name(crtc->pipe));
 648                 hdmi_val |= SDVO_AUDIO_ENABLE;
 649                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 650                 intel_write_eld(&encoder->base, adjusted_mode);
 651         }
 652
 653         if (HAS_PCH_CPT(dev))
 654                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 655         else
 656                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 657
 658         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 659         POSTING_READ(intel_hdmi->hdmi_reg);
 660
 661         intel_hdmi->set_infoframes(&encoder->base, adjusted_mode);
 662 }
 663
 664 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 665                                     enum pipe *pipe)
 666 {
 667         struct drm_device *dev = encoder->base.dev;
 668         struct drm_i915_private *dev_priv = dev->dev_private;
 669         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 670         enum intel_display_power_domain power_domain;
 671         u32 tmp;
 672
 673         power_domain = intel_display_port_power_domain(encoder);
 674         if (!intel_display_power_enabled(dev_priv, power_domain))
 675                 return false;
 676
 677         tmp = I915_READ(intel_hdmi->hdmi_reg);
 678
 679         if (!(tmp & SDVO_ENABLE))
 680                 return false;
 681
 682         if (HAS_PCH_CPT(dev))
 683                 *pipe = PORT_TO_PIPE_CPT(tmp);
 684         else
 685                 *pipe = PORT_TO_PIPE(tmp);
 686
 687         return true;
 688 }
 689
 690 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 691                                   struct intel_crtc_config *pipe_config)
 692 {
 693         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 694         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 695         u32 tmp, flags = 0;
 696         int dotclock;
 697
 698         tmp = I915_READ(intel_hdmi->hdmi_reg);
 699
 700         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 701                 flags |= DRM_MODE_FLAG_PHSYNC;
 702         else
 703                 flags |= DRM_MODE_FLAG_NHSYNC;
 704
 705         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 706                 flags |= DRM_MODE_FLAG_PVSYNC;
 707         else
 708                 flags |= DRM_MODE_FLAG_NVSYNC;
 709
 710         pipe_config->adjusted_mode.flags |= flags;
 711
 712         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 713                 dotclock = pipe_config->port_clock * 2 / 3;
 714         else
 715                 dotclock = pipe_config->port_clock;
 716
 717         if (HAS_PCH_SPLIT(dev_priv->dev))
 718                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
 719
 720         pipe_config->adjusted_mode.crtc_clock = dotclock;
 721 }
 722
 723 static void intel_enable_hdmi(struct intel_encoder *encoder)
 724 {
 725         struct drm_device *dev = encoder->base.dev;
 726         struct drm_i915_private *dev_priv = dev->dev_private;
 727         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 728         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 729         u32 temp;
 730         u32 enable_bits = SDVO_ENABLE;
 731
 732         if (intel_hdmi->has_audio)
 733                 enable_bits |= SDVO_AUDIO_ENABLE;
 734
 735         temp = I915_READ(intel_hdmi->hdmi_reg);
 736
 737         /* HW workaround for IBX, we need to move the port to transcoder A
 738          * before disabling it, so restore the transcoder select bit here. */
 739         if (HAS_PCH_IBX(dev))
 740                 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
 741
 742         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 743          * we do this anyway which shows more stable in testing.
 744          */
 745         if (HAS_PCH_SPLIT(dev)) {
 746                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 747                 POSTING_READ(intel_hdmi->hdmi_reg);
 748         }
 749
 750         temp |= enable_bits;
 751
 752         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 753         POSTING_READ(intel_hdmi->hdmi_reg);
 754
 755         /* HW workaround, need to write this twice for issue that may result
 756          * in first write getting masked.
 757          */
 758         if (HAS_PCH_SPLIT(dev)) {
 759                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 760                 POSTING_READ(intel_hdmi->hdmi_reg);
 761         }
 762 }
 763
 764 static void vlv_enable_hdmi(struct intel_encoder *encoder)
 765 {
 766 }
 767
 768 static void intel_disable_hdmi(struct intel_encoder *encoder)
 769 {
 770         struct drm_device *dev = encoder->base.dev;
 771         struct drm_i915_private *dev_priv = dev->dev_private;
 772         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 773         u32 temp;
 774         u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
 775
 776         temp = I915_READ(intel_hdmi->hdmi_reg);
 777
 778         /* HW workaround for IBX, we need to move the port to transcoder A
 779          * before disabling it. */
 780         if (HAS_PCH_IBX(dev)) {
 781                 struct drm_crtc *crtc = encoder->base.crtc;
 782                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 783
 784                 if (temp & SDVO_PIPE_B_SELECT) {
 785                         temp &= ~SDVO_PIPE_B_SELECT;
 786                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 787                         POSTING_READ(intel_hdmi->hdmi_reg);
 788
 789                         /* Again we need to write this twice. */
 790                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 791                         POSTING_READ(intel_hdmi->hdmi_reg);
 792
 793                         /* Transcoder selection bits only update
 794                          * effectively on vblank. */
 795                         if (crtc)
 796                                 intel_wait_for_vblank(dev, pipe);
 797                         else
 798                                 msleep(50);
 799                 }
 800         }
 801
 802         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 803          * we do this anyway which shows more stable in testing.
 804          */
 805         if (HAS_PCH_SPLIT(dev)) {
 806                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 807                 POSTING_READ(intel_hdmi->hdmi_reg);
 808         }
 809
 810         temp &= ~enable_bits;
 811
 812         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 813         POSTING_READ(intel_hdmi->hdmi_reg);
 814
 815         /* HW workaround, need to write this twice for issue that may result
 816          * in first write getting masked.
 817          */
 818         if (HAS_PCH_SPLIT(dev)) {
 819                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 820                 POSTING_READ(intel_hdmi->hdmi_reg);
 821         }
 822 }
 823
 824 static int hdmi_portclock_limit(struct intel_hdmi *hdmi)
 825 {
 826         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
 827
 828         if (!hdmi->has_hdmi_sink || IS_G4X(dev))
 829                 return 165000;
 830         else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
 831                 return 300000;
 832         else
 833                 return 225000;
 834 }
 835
 836 static enum drm_mode_status
 837 intel_hdmi_mode_valid(struct drm_connector *connector,
 838                       struct drm_display_mode *mode)
 839 {
 840         if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector)))
 841                 return MODE_CLOCK_HIGH;
 842         if (mode->clock < 20000)
 843                 return MODE_CLOCK_LOW;
 844
 845         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 846                 return MODE_NO_DBLESCAN;
 847
 848         return MODE_OK;
 849 }
 850
 851 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 852                                struct intel_crtc_config *pipe_config)
 853 {
 854         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 855         struct drm_device *dev = encoder->base.dev;
 856         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 857         int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;
 858         int portclock_limit = hdmi_portclock_limit(intel_hdmi);
 859         int desired_bpp;
 860
 861         if (intel_hdmi->color_range_auto) {
 862                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
 863                 if (intel_hdmi->has_hdmi_sink &&
 864                     drm_match_cea_mode(adjusted_mode) > 1)
 865                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
 866                 else
 867                         intel_hdmi->color_range = 0;
 868         }
 869
 870         if (intel_hdmi->color_range)
 871                 pipe_config->limited_color_range = true;
 872
 873         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
 874                 pipe_config->has_pch_encoder = true;
 875
 876         /*
 877          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
 878          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
 879          * outputs. We also need to check that the higher clock still fits
 880          * within limits.
 881          */
 882         if (pipe_config->pipe_bpp > 8*3 && intel_hdmi->has_hdmi_sink &&
 883             clock_12bpc <= portclock_limit && HAS_PCH_SPLIT(dev)) {
 884                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
 885                 desired_bpp = 12*3;
 886
 887                 /* Need to adjust the port link by 1.5x for 12bpc. */
 888                 pipe_config->port_clock = clock_12bpc;
 889         } else {
 890                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
 891                 desired_bpp = 8*3;
 892         }
 893
 894         if (!pipe_config->bw_constrained) {
 895                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
 896                 pipe_config->pipe_bpp = desired_bpp;
 897         }
 898
 899         if (adjusted_mode->crtc_clock > portclock_limit) {
 900                 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
 901                 return false;
 902         }
 903
 904         return true;
 905 }
 906
 907 static enum drm_connector_status
 908 intel_hdmi_detect(struct drm_connector *connector, bool force)
 909 {
 910         struct drm_device *dev = connector->dev;
 911         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 912         struct intel_digital_port *intel_dig_port =
 913                 hdmi_to_dig_port(intel_hdmi);
 914         struct intel_encoder *intel_encoder = &intel_dig_port->base;
 915         struct drm_i915_private *dev_priv = dev->dev_private;
 916         struct edid *edid;
 917         enum intel_display_power_domain power_domain;
 918         enum drm_connector_status status = connector_status_disconnected;
 919
 920         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
 921                       connector->base.id, drm_get_connector_name(connector));
 922
 923         power_domain = intel_display_port_power_domain(intel_encoder);
 924         intel_display_power_get(dev_priv, power_domain);
 925
 926         intel_hdmi->has_hdmi_sink = false;
 927         intel_hdmi->has_audio = false;
 928         intel_hdmi->rgb_quant_range_selectable = false;
 929         edid = drm_get_edid(connector,
 930                             intel_gmbus_get_adapter(dev_priv,
 931                                                     intel_hdmi->ddc_bus));
 932
 933         if (edid) {
 934                 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
 935                         status = connector_status_connected;
 936                         if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
 937                                 intel_hdmi->has_hdmi_sink =
 938                                                 drm_detect_hdmi_monitor(edid);
 939                         intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
 940                         intel_hdmi->rgb_quant_range_selectable =
 941                                 drm_rgb_quant_range_selectable(edid);
 942                 }
 943                 kfree(edid);
 944         }
 945
 946         if (status == connector_status_connected) {
 947                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
 948                         intel_hdmi->has_audio =
 949                                 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
 950                 intel_encoder->type = INTEL_OUTPUT_HDMI;
 951         }
 952
 953         intel_display_power_put(dev_priv, power_domain);
 954
 955         return status;
 956 }
 957
 958 static int intel_hdmi_get_modes(struct drm_connector *connector)
 959 {
 960         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
 961         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
 962         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 963         enum intel_display_power_domain power_domain;
 964         int ret;
 965
 966         /* We should parse the EDID data and find out if it's an HDMI sink so
 967          * we can send audio to it.
 968          */
 969
 970         power_domain = intel_display_port_power_domain(intel_encoder);
 971         intel_display_power_get(dev_priv, power_domain);
 972
 973         ret = intel_ddc_get_modes(connector,
 974                                    intel_gmbus_get_adapter(dev_priv,
 975                                                            intel_hdmi->ddc_bus));
 976
 977         intel_display_power_put(dev_priv, power_domain);
 978
 979         return ret;
 980 }
 981
 982 static bool
 983 intel_hdmi_detect_audio(struct drm_connector *connector)
 984 {
 985         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
 986         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
 987         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 988         enum intel_display_power_domain power_domain;
 989         struct edid *edid;
 990         bool has_audio = false;
 991
 992         power_domain = intel_display_port_power_domain(intel_encoder);
 993         intel_display_power_get(dev_priv, power_domain);
 994
 995         edid = drm_get_edid(connector,
 996                             intel_gmbus_get_adapter(dev_priv,
 997                                                     intel_hdmi->ddc_bus));
 998         if (edid) {
 999                 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1000                         has_audio = drm_detect_monitor_audio(edid);
1001                 kfree(edid);
1002         }
1003
1004         intel_display_power_put(dev_priv, power_domain);
1005
1006         return has_audio;
1007 }
1008
1009 static int
1010 intel_hdmi_set_property(struct drm_connector *connector,
1011                         struct drm_property *property,
1012                         uint64_t val)
1013 {
1014         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1015         struct intel_digital_port *intel_dig_port =
1016                 hdmi_to_dig_port(intel_hdmi);
1017         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1018         int ret;
1019
1020         ret = drm_object_property_set_value(&connector->base, property, val);
1021         if (ret)
1022                 return ret;
1023
1024         if (property == dev_priv->force_audio_property) {
1025                 enum hdmi_force_audio i = val;
1026                 bool has_audio;
1027
1028                 if (i == intel_hdmi->force_audio)
1029                         return 0;
1030
1031                 intel_hdmi->force_audio = i;
1032
1033                 if (i == HDMI_AUDIO_AUTO)
1034                         has_audio = intel_hdmi_detect_audio(connector);
1035                 else
1036                         has_audio = (i == HDMI_AUDIO_ON);
1037
1038                 if (i == HDMI_AUDIO_OFF_DVI)
1039                         intel_hdmi->has_hdmi_sink = 0;
1040
1041                 intel_hdmi->has_audio = has_audio;
1042                 goto done;
1043         }
1044
1045         if (property == dev_priv->broadcast_rgb_property) {
1046                 bool old_auto = intel_hdmi->color_range_auto;
1047                 uint32_t old_range = intel_hdmi->color_range;
1048
1049                 switch (val) {
1050                 case INTEL_BROADCAST_RGB_AUTO:
1051                         intel_hdmi->color_range_auto = true;
1052                         break;
1053                 case INTEL_BROADCAST_RGB_FULL:
1054                         intel_hdmi->color_range_auto = false;
1055                         intel_hdmi->color_range = 0;
1056                         break;
1057                 case INTEL_BROADCAST_RGB_LIMITED:
1058                         intel_hdmi->color_range_auto = false;
1059                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1060                         break;
1061                 default:
1062                         return -EINVAL;
1063                 }
1064
1065                 if (old_auto == intel_hdmi->color_range_auto &&
1066                     old_range == intel_hdmi->color_range)
1067                         return 0;
1068
1069                 goto done;
1070         }
1071
1072         return -EINVAL;
1073
1074 done:
1075         if (intel_dig_port->base.base.crtc)
1076                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1077
1078         return 0;
1079 }
1080
1081 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1082 {
1083         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1084         struct drm_device *dev = encoder->base.dev;
1085         struct drm_i915_private *dev_priv = dev->dev_private;
1086         struct intel_crtc *intel_crtc =
1087                 to_intel_crtc(encoder->base.crtc);
1088         enum dpio_channel port = vlv_dport_to_channel(dport);
1089         int pipe = intel_crtc->pipe;
1090         u32 val;
1091
1092         if (!IS_VALLEYVIEW(dev))
1093                 return;
1094
1095         /* Enable clock channels for this port */
1096         mutex_lock(&dev_priv->dpio_lock);
1097         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1098         val = 0;
1099         if (pipe)
1100                 val |= (1<<21);
1101         else
1102                 val &= ~(1<<21);
1103         val |= 0x001000c4;
1104         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1105
1106         /* HDMI 1.0V-2dB */
1107         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1108         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1109         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1110         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1111         vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1112         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1113         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1114         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1115
1116         /* Program lane clock */
1117         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1118         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1119         mutex_unlock(&dev_priv->dpio_lock);
1120
1121         intel_enable_hdmi(encoder);
1122
1123         vlv_wait_port_ready(dev_priv, dport);
1124 }
1125
1126 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1127 {
1128         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1129         struct drm_device *dev = encoder->base.dev;
1130         struct drm_i915_private *dev_priv = dev->dev_private;
1131         struct intel_crtc *intel_crtc =
1132                 to_intel_crtc(encoder->base.crtc);
1133         enum dpio_channel port = vlv_dport_to_channel(dport);
1134         int pipe = intel_crtc->pipe;
1135
1136         if (!IS_VALLEYVIEW(dev))
1137                 return;
1138
1139         /* Program Tx lane resets to default */
1140         mutex_lock(&dev_priv->dpio_lock);
1141         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1142                          DPIO_PCS_TX_LANE2_RESET |
1143                          DPIO_PCS_TX_LANE1_RESET);
1144         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1145                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1146                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1147                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1148                          DPIO_PCS_CLK_SOFT_RESET);
1149
1150         /* Fix up inter-pair skew failure */
1151         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1152         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1153         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1154
1155         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1156         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1157         mutex_unlock(&dev_priv->dpio_lock);
1158 }
1159
1160 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1161 {
1162         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1163         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1164         struct intel_crtc *intel_crtc =
1165                 to_intel_crtc(encoder->base.crtc);
1166         enum dpio_channel port = vlv_dport_to_channel(dport);
1167         int pipe = intel_crtc->pipe;
1168
1169         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1170         mutex_lock(&dev_priv->dpio_lock);
1171         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1172         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1173         mutex_unlock(&dev_priv->dpio_lock);
1174 }
1175
1176 static void intel_hdmi_destroy(struct drm_connector *connector)
1177 {
1178         drm_connector_cleanup(connector);
1179         kfree(connector);
1180 }
1181
1182 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1183         .dpms = intel_connector_dpms,
1184         .detect = intel_hdmi_detect,
1185         .fill_modes = drm_helper_probe_single_connector_modes,
1186         .set_property = intel_hdmi_set_property,
1187         .destroy = intel_hdmi_destroy,
1188 };
1189
1190 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1191         .get_modes = intel_hdmi_get_modes,
1192         .mode_valid = intel_hdmi_mode_valid,
1193         .best_encoder = intel_best_encoder,
1194 };
1195
1196 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1197         .destroy = intel_encoder_destroy,
1198 };
1199
1200 static void
1201 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1202 {
1203         intel_attach_force_audio_property(connector);
1204         intel_attach_broadcast_rgb_property(connector);
1205         intel_hdmi->color_range_auto = true;
1206 }
1207
1208 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1209                                struct intel_connector *intel_connector)
1210 {
1211         struct drm_connector *connector = &intel_connector->base;
1212         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1213         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1214         struct drm_device *dev = intel_encoder->base.dev;
1215         struct drm_i915_private *dev_priv = dev->dev_private;
1216         enum port port = intel_dig_port->port;
1217
1218         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1219                            DRM_MODE_CONNECTOR_HDMIA);
1220         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1221
1222         connector->interlace_allowed = 1;
1223         connector->doublescan_allowed = 0;
1224         connector->stereo_allowed = 1;
1225
1226         switch (port) {
1227         case PORT_B:
1228                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
1229                 intel_encoder->hpd_pin = HPD_PORT_B;
1230                 break;
1231         case PORT_C:
1232                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
1233                 intel_encoder->hpd_pin = HPD_PORT_C;
1234                 break;
1235         case PORT_D:
1236                 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
1237                 intel_encoder->hpd_pin = HPD_PORT_D;
1238                 break;
1239         case PORT_A:
1240                 intel_encoder->hpd_pin = HPD_PORT_A;
1241                 /* Internal port only for eDP. */
1242         default:
1243                 BUG();
1244         }
1245
1246         if (IS_VALLEYVIEW(dev)) {
1247                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1248                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1249         } else if (!HAS_PCH_SPLIT(dev)) {
1250                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1251                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1252         } else if (HAS_DDI(dev)) {
1253                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1254                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1255         } else if (HAS_PCH_IBX(dev)) {
1256                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1257                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1258         } else {
1259                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1260                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1261         }
1262
1263         if (HAS_DDI(dev))
1264                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1265         else
1266                 intel_connector->get_hw_state = intel_connector_get_hw_state;
1267         intel_connector->unregister = intel_connector_unregister;
1268
1269         intel_hdmi_add_properties(intel_hdmi, connector);
1270
1271         intel_connector_attach_encoder(intel_connector, intel_encoder);
1272         drm_sysfs_connector_add(connector);
1273
1274         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1275          * 0xd.  Failure to do so will result in spurious interrupts being
1276          * generated on the port when a cable is not attached.
1277          */
1278         if (IS_G4X(dev) && !IS_GM45(dev)) {
1279                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1280                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1281         }
1282 }
1283
1284 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1285 {
1286         struct intel_digital_port *intel_dig_port;
1287         struct intel_encoder *intel_encoder;
1288         struct intel_connector *intel_connector;
1289
1290         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1291         if (!intel_dig_port)
1292                 return;
1293
1294         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
1295         if (!intel_connector) {
1296                 kfree(intel_dig_port);
1297                 return;
1298         }
1299
1300         intel_encoder = &intel_dig_port->base;
1301
1302         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1303                          DRM_MODE_ENCODER_TMDS);
1304
1305         intel_encoder->compute_config = intel_hdmi_compute_config;
1306         intel_encoder->mode_set = intel_hdmi_mode_set;
1307         intel_encoder->disable = intel_disable_hdmi;
1308         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1309         intel_encoder->get_config = intel_hdmi_get_config;
1310         if (IS_VALLEYVIEW(dev)) {
1311                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1312                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1313                 intel_encoder->enable = vlv_enable_hdmi;
1314                 intel_encoder->post_disable = vlv_hdmi_post_disable;
1315         } else {
1316                 intel_encoder->enable = intel_enable_hdmi;
1317         }
1318
1319         intel_encoder->type = INTEL_OUTPUT_HDMI;
1320         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1321         intel_encoder->cloneable = 0;
1322
1323         intel_dig_port->port = port;
1324         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1325         intel_dig_port->dp.output_reg = 0;
1326
1327         intel_hdmi_init_connector(intel_dig_port, intel_connector);
1328 }