drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_scdc_helper.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include <drm/intel_lpe_audio.h>
  41 #include "i915_drv.h"
  42
  43 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  44 {
  45         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  46 }
  47
  48 static void
  49 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  50 {
  51         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  52         struct drm_i915_private *dev_priv = to_i915(dev);
  53         uint32_t enabled_bits;
  54
  55         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  56
  57         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  58              "HDMI port enabled, expecting disabled\n");
  59 }
  60
  61 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  62 {
  63         struct intel_digital_port *intel_dig_port =
  64                 container_of(encoder, struct intel_digital_port, base.base);
  65         return &intel_dig_port->hdmi;
  66 }
  67
  68 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  69 {
  70         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  71 }
  72
  73 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  74 {
  75         switch (type) {
  76         case HDMI_INFOFRAME_TYPE_AVI:
  77                 return VIDEO_DIP_SELECT_AVI;
  78         case HDMI_INFOFRAME_TYPE_SPD:
  79                 return VIDEO_DIP_SELECT_SPD;
  80         case HDMI_INFOFRAME_TYPE_VENDOR:
  81                 return VIDEO_DIP_SELECT_VENDOR;
  82         default:
  83                 MISSING_CASE(type);
  84                 return 0;
  85         }
  86 }
  87
  88 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  89 {
  90         switch (type) {
  91         case HDMI_INFOFRAME_TYPE_AVI:
  92                 return VIDEO_DIP_ENABLE_AVI;
  93         case HDMI_INFOFRAME_TYPE_SPD:
  94                 return VIDEO_DIP_ENABLE_SPD;
  95         case HDMI_INFOFRAME_TYPE_VENDOR:
  96                 return VIDEO_DIP_ENABLE_VENDOR;
  97         default:
  98                 MISSING_CASE(type);
  99                 return 0;
 100         }
 101 }
 102
 103 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 104 {
 105         switch (type) {
 106         case HDMI_INFOFRAME_TYPE_AVI:
 107                 return VIDEO_DIP_ENABLE_AVI_HSW;
 108         case HDMI_INFOFRAME_TYPE_SPD:
 109                 return VIDEO_DIP_ENABLE_SPD_HSW;
 110         case HDMI_INFOFRAME_TYPE_VENDOR:
 111                 return VIDEO_DIP_ENABLE_VS_HSW;
 112         default:
 113                 MISSING_CASE(type);
 114                 return 0;
 115         }
 116 }
 117
 118 static i915_reg_t
 119 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 120                  enum transcoder cpu_transcoder,
 121                  enum hdmi_infoframe_type type,
 122                  int i)
 123 {
 124         switch (type) {
 125         case HDMI_INFOFRAME_TYPE_AVI:
 126                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 127         case HDMI_INFOFRAME_TYPE_SPD:
 128                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 129         case HDMI_INFOFRAME_TYPE_VENDOR:
 130                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 131         default:
 132                 MISSING_CASE(type);
 133                 return INVALID_MMIO_REG;
 134         }
 135 }
 136
 137 static void g4x_write_infoframe(struct drm_encoder *encoder,
 138                                 const struct intel_crtc_state *crtc_state,
 139                                 enum hdmi_infoframe_type type,
 140                                 const void *frame, ssize_t len)
 141 {
 142         const uint32_t *data = frame;
 143         struct drm_device *dev = encoder->dev;
 144         struct drm_i915_private *dev_priv = to_i915(dev);
 145         u32 val = I915_READ(VIDEO_DIP_CTL);
 146         int i;
 147
 148         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 149
 150         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 151         val |= g4x_infoframe_index(type);
 152
 153         val &= ~g4x_infoframe_enable(type);
 154
 155         I915_WRITE(VIDEO_DIP_CTL, val);
 156
 157         mmiowb();
 158         for (i = 0; i < len; i += 4) {
 159                 I915_WRITE(VIDEO_DIP_DATA, *data);
 160                 data++;
 161         }
 162         /* Write every possible data byte to force correct ECC calculation. */
 163         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 164                 I915_WRITE(VIDEO_DIP_DATA, 0);
 165         mmiowb();
 166
 167         val |= g4x_infoframe_enable(type);
 168         val &= ~VIDEO_DIP_FREQ_MASK;
 169         val |= VIDEO_DIP_FREQ_VSYNC;
 170
 171         I915_WRITE(VIDEO_DIP_CTL, val);
 172         POSTING_READ(VIDEO_DIP_CTL);
 173 }
 174
 175 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
 176                                   const struct intel_crtc_state *pipe_config)
 177 {
 178         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 179         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 180         u32 val = I915_READ(VIDEO_DIP_CTL);
 181
 182         if ((val & VIDEO_DIP_ENABLE) == 0)
 183                 return false;
 184
 185         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 186                 return false;
 187
 188         return val & (VIDEO_DIP_ENABLE_AVI |
 189                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 190 }
 191
 192 static void ibx_write_infoframe(struct drm_encoder *encoder,
 193                                 const struct intel_crtc_state *crtc_state,
 194                                 enum hdmi_infoframe_type type,
 195                                 const void *frame, ssize_t len)
 196 {
 197         const uint32_t *data = frame;
 198         struct drm_device *dev = encoder->dev;
 199         struct drm_i915_private *dev_priv = to_i915(dev);
 200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 201         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 202         u32 val = I915_READ(reg);
 203         int i;
 204
 205         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 206
 207         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 208         val |= g4x_infoframe_index(type);
 209
 210         val &= ~g4x_infoframe_enable(type);
 211
 212         I915_WRITE(reg, val);
 213
 214         mmiowb();
 215         for (i = 0; i < len; i += 4) {
 216                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 217                 data++;
 218         }
 219         /* Write every possible data byte to force correct ECC calculation. */
 220         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 221                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 222         mmiowb();
 223
 224         val |= g4x_infoframe_enable(type);
 225         val &= ~VIDEO_DIP_FREQ_MASK;
 226         val |= VIDEO_DIP_FREQ_VSYNC;
 227
 228         I915_WRITE(reg, val);
 229         POSTING_READ(reg);
 230 }
 231
 232 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
 233                                   const struct intel_crtc_state *pipe_config)
 234 {
 235         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 236         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 237         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 238         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 239         u32 val = I915_READ(reg);
 240
 241         if ((val & VIDEO_DIP_ENABLE) == 0)
 242                 return false;
 243
 244         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 245                 return false;
 246
 247         return val & (VIDEO_DIP_ENABLE_AVI |
 248                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 249                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 250 }
 251
 252 static void cpt_write_infoframe(struct drm_encoder *encoder,
 253                                 const struct intel_crtc_state *crtc_state,
 254                                 enum hdmi_infoframe_type type,
 255                                 const void *frame, ssize_t len)
 256 {
 257         const uint32_t *data = frame;
 258         struct drm_device *dev = encoder->dev;
 259         struct drm_i915_private *dev_priv = to_i915(dev);
 260         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 261         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 262         u32 val = I915_READ(reg);
 263         int i;
 264
 265         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 266
 267         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 268         val |= g4x_infoframe_index(type);
 269
 270         /* The DIP control register spec says that we need to update the AVI
 271          * infoframe without clearing its enable bit */
 272         if (type != HDMI_INFOFRAME_TYPE_AVI)
 273                 val &= ~g4x_infoframe_enable(type);
 274
 275         I915_WRITE(reg, val);
 276
 277         mmiowb();
 278         for (i = 0; i < len; i += 4) {
 279                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 280                 data++;
 281         }
 282         /* Write every possible data byte to force correct ECC calculation. */
 283         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 284                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 285         mmiowb();
 286
 287         val |= g4x_infoframe_enable(type);
 288         val &= ~VIDEO_DIP_FREQ_MASK;
 289         val |= VIDEO_DIP_FREQ_VSYNC;
 290
 291         I915_WRITE(reg, val);
 292         POSTING_READ(reg);
 293 }
 294
 295 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
 296                                   const struct intel_crtc_state *pipe_config)
 297 {
 298         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 299         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 300         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
 301
 302         if ((val & VIDEO_DIP_ENABLE) == 0)
 303                 return false;
 304
 305         return val & (VIDEO_DIP_ENABLE_AVI |
 306                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 307                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 308 }
 309
 310 static void vlv_write_infoframe(struct drm_encoder *encoder,
 311                                 const struct intel_crtc_state *crtc_state,
 312                                 enum hdmi_infoframe_type type,
 313                                 const void *frame, ssize_t len)
 314 {
 315         const uint32_t *data = frame;
 316         struct drm_device *dev = encoder->dev;
 317         struct drm_i915_private *dev_priv = to_i915(dev);
 318         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 319         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 320         u32 val = I915_READ(reg);
 321         int i;
 322
 323         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 324
 325         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 326         val |= g4x_infoframe_index(type);
 327
 328         val &= ~g4x_infoframe_enable(type);
 329
 330         I915_WRITE(reg, val);
 331
 332         mmiowb();
 333         for (i = 0; i < len; i += 4) {
 334                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 335                 data++;
 336         }
 337         /* Write every possible data byte to force correct ECC calculation. */
 338         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 339                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 340         mmiowb();
 341
 342         val |= g4x_infoframe_enable(type);
 343         val &= ~VIDEO_DIP_FREQ_MASK;
 344         val |= VIDEO_DIP_FREQ_VSYNC;
 345
 346         I915_WRITE(reg, val);
 347         POSTING_READ(reg);
 348 }
 349
 350 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
 351                                   const struct intel_crtc_state *pipe_config)
 352 {
 353         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 354         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 355         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 356         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
 357
 358         if ((val & VIDEO_DIP_ENABLE) == 0)
 359                 return false;
 360
 361         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 362                 return false;
 363
 364         return val & (VIDEO_DIP_ENABLE_AVI |
 365                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 366                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 367 }
 368
 369 static void hsw_write_infoframe(struct drm_encoder *encoder,
 370                                 const struct intel_crtc_state *crtc_state,
 371                                 enum hdmi_infoframe_type type,
 372                                 const void *frame, ssize_t len)
 373 {
 374         const uint32_t *data = frame;
 375         struct drm_device *dev = encoder->dev;
 376         struct drm_i915_private *dev_priv = to_i915(dev);
 377         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 378         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 379         i915_reg_t data_reg;
 380         int i;
 381         u32 val = I915_READ(ctl_reg);
 382
 383         data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
 384
 385         val &= ~hsw_infoframe_enable(type);
 386         I915_WRITE(ctl_reg, val);
 387
 388         mmiowb();
 389         for (i = 0; i < len; i += 4) {
 390                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 391                                             type, i >> 2), *data);
 392                 data++;
 393         }
 394         /* Write every possible data byte to force correct ECC calculation. */
 395         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 396                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 397                                             type, i >> 2), 0);
 398         mmiowb();
 399
 400         val |= hsw_infoframe_enable(type);
 401         I915_WRITE(ctl_reg, val);
 402         POSTING_READ(ctl_reg);
 403 }
 404
 405 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
 406                                   const struct intel_crtc_state *pipe_config)
 407 {
 408         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 409         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 410
 411         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 412                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 413                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 414 }
 415
 416 /*
 417  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 418  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 419  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 420  * used for both technologies.
 421  *
 422  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 423  * DW1:       DB3       | DB2 | DB1 | DB0
 424  * DW2:       DB7       | DB6 | DB5 | DB4
 425  * DW3: ...
 426  *
 427  * (HB is Header Byte, DB is Data Byte)
 428  *
 429  * The hdmi pack() functions don't know about that hardware specific hole so we
 430  * trick them by giving an offset into the buffer and moving back the header
 431  * bytes by one.
 432  */
 433 static void intel_write_infoframe(struct drm_encoder *encoder,
 434                                   const struct intel_crtc_state *crtc_state,
 435                                   union hdmi_infoframe *frame)
 436 {
 437         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 438         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 439         ssize_t len;
 440
 441         /* see comment above for the reason for this offset */
 442         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 443         if (len < 0)
 444                 return;
 445
 446         /* Insert the 'hole' (see big comment above) at position 3 */
 447         buffer[0] = buffer[1];
 448         buffer[1] = buffer[2];
 449         buffer[2] = buffer[3];
 450         buffer[3] = 0;
 451         len++;
 452
 453         intel_hdmi->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len);
 454 }
 455
 456 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 457                                          const struct intel_crtc_state *crtc_state)
 458 {
 459         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 460         const struct drm_display_mode *adjusted_mode =
 461                 &crtc_state->base.adjusted_mode;
 462         struct drm_connector *connector = &intel_hdmi->attached_connector->base;
 463         bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported;
 464         union hdmi_infoframe frame;
 465         int ret;
 466
 467         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 468                                                        adjusted_mode,
 469                                                        is_hdmi2_sink);
 470         if (ret < 0) {
 471                 DRM_ERROR("couldn't fill AVI infoframe\n");
 472                 return;
 473         }
 474
 475         drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode,
 476                                            crtc_state->limited_color_range ?
 477                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 478                                            HDMI_QUANTIZATION_RANGE_FULL,
 479                                            intel_hdmi->rgb_quant_range_selectable);
 480
 481         intel_write_infoframe(encoder, crtc_state, &frame);
 482 }
 483
 484 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder,
 485                                          const struct intel_crtc_state *crtc_state)
 486 {
 487         union hdmi_infoframe frame;
 488         int ret;
 489
 490         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 491         if (ret < 0) {
 492                 DRM_ERROR("couldn't fill SPD infoframe\n");
 493                 return;
 494         }
 495
 496         frame.spd.sdi = HDMI_SPD_SDI_PC;
 497
 498         intel_write_infoframe(encoder, crtc_state, &frame);
 499 }
 500
 501 static void
 502 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 503                               const struct intel_crtc_state *crtc_state)
 504 {
 505         union hdmi_infoframe frame;
 506         int ret;
 507
 508         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 509                                                           &crtc_state->base.adjusted_mode);
 510         if (ret < 0)
 511                 return;
 512
 513         intel_write_infoframe(encoder, crtc_state, &frame);
 514 }
 515
 516 static void g4x_set_infoframes(struct drm_encoder *encoder,
 517                                bool enable,
 518                                const struct intel_crtc_state *crtc_state,
 519                                const struct drm_connector_state *conn_state)
 520 {
 521         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 522         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 523         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 524         i915_reg_t reg = VIDEO_DIP_CTL;
 525         u32 val = I915_READ(reg);
 526         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 527
 528         assert_hdmi_port_disabled(intel_hdmi);
 529
 530         /* If the registers were not initialized yet, they might be zeroes,
 531          * which means we're selecting the AVI DIP and we're setting its
 532          * frequency to once. This seems to really confuse the HW and make
 533          * things stop working (the register spec says the AVI always needs to
 534          * be sent every VSync). So here we avoid writing to the register more
 535          * than we need and also explicitly select the AVI DIP and explicitly
 536          * set its frequency to every VSync. Avoiding to write it twice seems to
 537          * be enough to solve the problem, but being defensive shouldn't hurt us
 538          * either. */
 539         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 540
 541         if (!enable) {
 542                 if (!(val & VIDEO_DIP_ENABLE))
 543                         return;
 544                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 545                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 546                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 547                         return;
 548                 }
 549                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 550                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 551                 I915_WRITE(reg, val);
 552                 POSTING_READ(reg);
 553                 return;
 554         }
 555
 556         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 557                 if (val & VIDEO_DIP_ENABLE) {
 558                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 559                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 560                         return;
 561                 }
 562                 val &= ~VIDEO_DIP_PORT_MASK;
 563                 val |= port;
 564         }
 565
 566         val |= VIDEO_DIP_ENABLE;
 567         val &= ~(VIDEO_DIP_ENABLE_AVI |
 568                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 569
 570         I915_WRITE(reg, val);
 571         POSTING_READ(reg);
 572
 573         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 574         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 575         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
 576 }
 577
 578 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
 579 {
 580         struct drm_connector *connector = conn_state->connector;
 581
 582         /*
 583          * HDMI cloning is only supported on g4x which doesn't
 584          * support deep color or GCP infoframes anyway so no
 585          * need to worry about multiple HDMI sinks here.
 586          */
 587
 588         return connector->display_info.bpc > 8;
 589 }
 590
 591 /*
 592  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 593  *
 594  * From HDMI specification 1.4a:
 595  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 596  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 597  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 598  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 599  *   phase of 0
 600  */
 601 static bool gcp_default_phase_possible(int pipe_bpp,
 602                                        const struct drm_display_mode *mode)
 603 {
 604         unsigned int pixels_per_group;
 605
 606         switch (pipe_bpp) {
 607         case 30:
 608                 /* 4 pixels in 5 clocks */
 609                 pixels_per_group = 4;
 610                 break;
 611         case 36:
 612                 /* 2 pixels in 3 clocks */
 613                 pixels_per_group = 2;
 614                 break;
 615         case 48:
 616                 /* 1 pixel in 2 clocks */
 617                 pixels_per_group = 1;
 618                 break;
 619         default:
 620                 /* phase information not relevant for 8bpc */
 621                 return false;
 622         }
 623
 624         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 625                 mode->crtc_htotal % pixels_per_group == 0 &&
 626                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 627                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 628                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 629                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 630                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 631                  mode->crtc_htotal/2 % pixels_per_group == 0);
 632 }
 633
 634 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder,
 635                                          const struct intel_crtc_state *crtc_state,
 636                                          const struct drm_connector_state *conn_state)
 637 {
 638         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 639         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 640         i915_reg_t reg;
 641         u32 val = 0;
 642
 643         if (HAS_DDI(dev_priv))
 644                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 645         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 646                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 647         else if (HAS_PCH_SPLIT(dev_priv))
 648                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 649         else
 650                 return false;
 651
 652         /* Indicate color depth whenever the sink supports deep color */
 653         if (hdmi_sink_is_deep_color(conn_state))
 654                 val |= GCP_COLOR_INDICATION;
 655
 656         /* Enable default_phase whenever the display mode is suitably aligned */
 657         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
 658                                        &crtc_state->base.adjusted_mode))
 659                 val |= GCP_DEFAULT_PHASE_ENABLE;
 660
 661         I915_WRITE(reg, val);
 662
 663         return val != 0;
 664 }
 665
 666 static void ibx_set_infoframes(struct drm_encoder *encoder,
 667                                bool enable,
 668                                const struct intel_crtc_state *crtc_state,
 669                                const struct drm_connector_state *conn_state)
 670 {
 671         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 672         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 673         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 674         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 675         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 676         u32 val = I915_READ(reg);
 677         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 678
 679         assert_hdmi_port_disabled(intel_hdmi);
 680
 681         /* See the big comment in g4x_set_infoframes() */
 682         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 683
 684         if (!enable) {
 685                 if (!(val & VIDEO_DIP_ENABLE))
 686                         return;
 687                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 688                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 689                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 690                 I915_WRITE(reg, val);
 691                 POSTING_READ(reg);
 692                 return;
 693         }
 694
 695         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 696                 WARN(val & VIDEO_DIP_ENABLE,
 697                      "DIP already enabled on port %c\n",
 698                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 699                 val &= ~VIDEO_DIP_PORT_MASK;
 700                 val |= port;
 701         }
 702
 703         val |= VIDEO_DIP_ENABLE;
 704         val &= ~(VIDEO_DIP_ENABLE_AVI |
 705                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 706                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 707
 708         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 709                 val |= VIDEO_DIP_ENABLE_GCP;
 710
 711         I915_WRITE(reg, val);
 712         POSTING_READ(reg);
 713
 714         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 715         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 716         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
 717 }
 718
 719 static void cpt_set_infoframes(struct drm_encoder *encoder,
 720                                bool enable,
 721                                const struct intel_crtc_state *crtc_state,
 722                                const struct drm_connector_state *conn_state)
 723 {
 724         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 725         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 726         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 727         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 728         u32 val = I915_READ(reg);
 729
 730         assert_hdmi_port_disabled(intel_hdmi);
 731
 732         /* See the big comment in g4x_set_infoframes() */
 733         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 734
 735         if (!enable) {
 736                 if (!(val & VIDEO_DIP_ENABLE))
 737                         return;
 738                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 739                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 740                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 741                 I915_WRITE(reg, val);
 742                 POSTING_READ(reg);
 743                 return;
 744         }
 745
 746         /* Set both together, unset both together: see the spec. */
 747         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 748         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 749                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 750
 751         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 752                 val |= VIDEO_DIP_ENABLE_GCP;
 753
 754         I915_WRITE(reg, val);
 755         POSTING_READ(reg);
 756
 757         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 758         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 759         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
 760 }
 761
 762 static void vlv_set_infoframes(struct drm_encoder *encoder,
 763                                bool enable,
 764                                const struct intel_crtc_state *crtc_state,
 765                                const struct drm_connector_state *conn_state)
 766 {
 767         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 768         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 770         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 771         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 772         u32 val = I915_READ(reg);
 773         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 774
 775         assert_hdmi_port_disabled(intel_hdmi);
 776
 777         /* See the big comment in g4x_set_infoframes() */
 778         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 779
 780         if (!enable) {
 781                 if (!(val & VIDEO_DIP_ENABLE))
 782                         return;
 783                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 784                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 785                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 786                 I915_WRITE(reg, val);
 787                 POSTING_READ(reg);
 788                 return;
 789         }
 790
 791         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 792                 WARN(val & VIDEO_DIP_ENABLE,
 793                      "DIP already enabled on port %c\n",
 794                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 795                 val &= ~VIDEO_DIP_PORT_MASK;
 796                 val |= port;
 797         }
 798
 799         val |= VIDEO_DIP_ENABLE;
 800         val &= ~(VIDEO_DIP_ENABLE_AVI |
 801                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 802                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 803
 804         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 805                 val |= VIDEO_DIP_ENABLE_GCP;
 806
 807         I915_WRITE(reg, val);
 808         POSTING_READ(reg);
 809
 810         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 811         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 812         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
 813 }
 814
 815 static void hsw_set_infoframes(struct drm_encoder *encoder,
 816                                bool enable,
 817                                const struct intel_crtc_state *crtc_state,
 818                                const struct drm_connector_state *conn_state)
 819 {
 820         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 821         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 822         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
 823         u32 val = I915_READ(reg);
 824
 825         assert_hdmi_port_disabled(intel_hdmi);
 826
 827         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 828                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 829                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 830
 831         if (!enable) {
 832                 I915_WRITE(reg, val);
 833                 POSTING_READ(reg);
 834                 return;
 835         }
 836
 837         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 838                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
 839
 840         I915_WRITE(reg, val);
 841         POSTING_READ(reg);
 842
 843         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 844         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 845         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
 846 }
 847
 848 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
 849 {
 850         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
 851         struct i2c_adapter *adapter =
 852                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
 853
 854         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
 855                 return;
 856
 857         DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
 858                       enable ? "Enabling" : "Disabling");
 859
 860         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
 861                                          adapter, enable);
 862 }
 863
 864 static void intel_hdmi_prepare(struct intel_encoder *encoder,
 865                                const struct intel_crtc_state *crtc_state)
 866 {
 867         struct drm_device *dev = encoder->base.dev;
 868         struct drm_i915_private *dev_priv = to_i915(dev);
 869         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 870         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 871         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
 872         u32 hdmi_val;
 873
 874         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
 875
 876         hdmi_val = SDVO_ENCODING_HDMI;
 877         if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
 878                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
 879         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 880                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 881         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 882                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 883
 884         if (crtc_state->pipe_bpp > 24)
 885                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 886         else
 887                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 888
 889         if (crtc_state->has_hdmi_sink)
 890                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 891
 892         if (HAS_PCH_CPT(dev_priv))
 893                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 894         else if (IS_CHERRYVIEW(dev_priv))
 895                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 896         else
 897                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 898
 899         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 900         POSTING_READ(intel_hdmi->hdmi_reg);
 901 }
 902
 903 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 904                                     enum pipe *pipe)
 905 {
 906         struct drm_device *dev = encoder->base.dev;
 907         struct drm_i915_private *dev_priv = to_i915(dev);
 908         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 909         u32 tmp;
 910         bool ret;
 911
 912         if (!intel_display_power_get_if_enabled(dev_priv,
 913                                                 encoder->power_domain))
 914                 return false;
 915
 916         ret = false;
 917
 918         tmp = I915_READ(intel_hdmi->hdmi_reg);
 919
 920         if (!(tmp & SDVO_ENABLE))
 921                 goto out;
 922
 923         if (HAS_PCH_CPT(dev_priv))
 924                 *pipe = PORT_TO_PIPE_CPT(tmp);
 925         else if (IS_CHERRYVIEW(dev_priv))
 926                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
 927         else
 928                 *pipe = PORT_TO_PIPE(tmp);
 929
 930         ret = true;
 931
 932 out:
 933         intel_display_power_put(dev_priv, encoder->power_domain);
 934
 935         return ret;
 936 }
 937
 938 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 939                                   struct intel_crtc_state *pipe_config)
 940 {
 941         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 942         struct drm_device *dev = encoder->base.dev;
 943         struct drm_i915_private *dev_priv = to_i915(dev);
 944         u32 tmp, flags = 0;
 945         int dotclock;
 946
 947         tmp = I915_READ(intel_hdmi->hdmi_reg);
 948
 949         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 950                 flags |= DRM_MODE_FLAG_PHSYNC;
 951         else
 952                 flags |= DRM_MODE_FLAG_NHSYNC;
 953
 954         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 955                 flags |= DRM_MODE_FLAG_PVSYNC;
 956         else
 957                 flags |= DRM_MODE_FLAG_NVSYNC;
 958
 959         if (tmp & HDMI_MODE_SELECT_HDMI)
 960                 pipe_config->has_hdmi_sink = true;
 961
 962         if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
 963                 pipe_config->has_infoframe = true;
 964
 965         if (tmp & SDVO_AUDIO_ENABLE)
 966                 pipe_config->has_audio = true;
 967
 968         if (!HAS_PCH_SPLIT(dev_priv) &&
 969             tmp & HDMI_COLOR_RANGE_16_235)
 970                 pipe_config->limited_color_range = true;
 971
 972         pipe_config->base.adjusted_mode.flags |= flags;
 973
 974         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 975                 dotclock = pipe_config->port_clock * 2 / 3;
 976         else
 977                 dotclock = pipe_config->port_clock;
 978
 979         if (pipe_config->pixel_multiplier)
 980                 dotclock /= pipe_config->pixel_multiplier;
 981
 982         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 983
 984         pipe_config->lane_count = 4;
 985 }
 986
 987 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
 988                                     struct intel_crtc_state *pipe_config,
 989                                     struct drm_connector_state *conn_state)
 990 {
 991         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 992
 993         WARN_ON(!pipe_config->has_hdmi_sink);
 994         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 995                          pipe_name(crtc->pipe));
 996         intel_audio_codec_enable(encoder, pipe_config, conn_state);
 997 }
 998
 999 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1000                             struct intel_crtc_state *pipe_config,
1001                             struct drm_connector_state *conn_state)
1002 {
1003         struct drm_device *dev = encoder->base.dev;
1004         struct drm_i915_private *dev_priv = to_i915(dev);
1005         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1006         u32 temp;
1007
1008         temp = I915_READ(intel_hdmi->hdmi_reg);
1009
1010         temp |= SDVO_ENABLE;
1011         if (pipe_config->has_audio)
1012                 temp |= SDVO_AUDIO_ENABLE;
1013
1014         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1015         POSTING_READ(intel_hdmi->hdmi_reg);
1016
1017         if (pipe_config->has_audio)
1018                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1019 }
1020
1021 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1022                             struct intel_crtc_state *pipe_config,
1023                             struct drm_connector_state *conn_state)
1024 {
1025         struct drm_device *dev = encoder->base.dev;
1026         struct drm_i915_private *dev_priv = to_i915(dev);
1027         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1028         u32 temp;
1029
1030         temp = I915_READ(intel_hdmi->hdmi_reg);
1031
1032         temp |= SDVO_ENABLE;
1033         if (pipe_config->has_audio)
1034                 temp |= SDVO_AUDIO_ENABLE;
1035
1036         /*
1037          * HW workaround, need to write this twice for issue
1038          * that may result in first write getting masked.
1039          */
1040         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1041         POSTING_READ(intel_hdmi->hdmi_reg);
1042         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1043         POSTING_READ(intel_hdmi->hdmi_reg);
1044
1045         /*
1046          * HW workaround, need to toggle enable bit off and on
1047          * for 12bpc with pixel repeat.
1048          *
1049          * FIXME: BSpec says this should be done at the end of
1050          * of the modeset sequence, so not sure if this isn't too soon.
1051          */
1052         if (pipe_config->pipe_bpp > 24 &&
1053             pipe_config->pixel_multiplier > 1) {
1054                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1055                 POSTING_READ(intel_hdmi->hdmi_reg);
1056
1057                 /*
1058                  * HW workaround, need to write this twice for issue
1059                  * that may result in first write getting masked.
1060                  */
1061                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1062                 POSTING_READ(intel_hdmi->hdmi_reg);
1063                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1064                 POSTING_READ(intel_hdmi->hdmi_reg);
1065         }
1066
1067         if (pipe_config->has_audio)
1068                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1069 }
1070
1071 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1072                             struct intel_crtc_state *pipe_config,
1073                             struct drm_connector_state *conn_state)
1074 {
1075         struct drm_device *dev = encoder->base.dev;
1076         struct drm_i915_private *dev_priv = to_i915(dev);
1077         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1078         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1079         enum pipe pipe = crtc->pipe;
1080         u32 temp;
1081
1082         temp = I915_READ(intel_hdmi->hdmi_reg);
1083
1084         temp |= SDVO_ENABLE;
1085         if (pipe_config->has_audio)
1086                 temp |= SDVO_AUDIO_ENABLE;
1087
1088         /*
1089          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1090          *
1091          * The procedure for 12bpc is as follows:
1092          * 1. disable HDMI clock gating
1093          * 2. enable HDMI with 8bpc
1094          * 3. enable HDMI with 12bpc
1095          * 4. enable HDMI clock gating
1096          */
1097
1098         if (pipe_config->pipe_bpp > 24) {
1099                 I915_WRITE(TRANS_CHICKEN1(pipe),
1100                            I915_READ(TRANS_CHICKEN1(pipe)) |
1101                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1102
1103                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1104                 temp |= SDVO_COLOR_FORMAT_8bpc;
1105         }
1106
1107         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1108         POSTING_READ(intel_hdmi->hdmi_reg);
1109
1110         if (pipe_config->pipe_bpp > 24) {
1111                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1112                 temp |= HDMI_COLOR_FORMAT_12bpc;
1113
1114                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1115                 POSTING_READ(intel_hdmi->hdmi_reg);
1116
1117                 I915_WRITE(TRANS_CHICKEN1(pipe),
1118                            I915_READ(TRANS_CHICKEN1(pipe)) &
1119                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1120         }
1121
1122         if (pipe_config->has_audio)
1123                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1124 }
1125
1126 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1127                             struct intel_crtc_state *pipe_config,
1128                             struct drm_connector_state *conn_state)
1129 {
1130 }
1131
1132 static void intel_disable_hdmi(struct intel_encoder *encoder,
1133                                struct intel_crtc_state *old_crtc_state,
1134                                struct drm_connector_state *old_conn_state)
1135 {
1136         struct drm_device *dev = encoder->base.dev;
1137         struct drm_i915_private *dev_priv = to_i915(dev);
1138         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1139         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1140         u32 temp;
1141
1142         temp = I915_READ(intel_hdmi->hdmi_reg);
1143
1144         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1145         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1146         POSTING_READ(intel_hdmi->hdmi_reg);
1147
1148         /*
1149          * HW workaround for IBX, we need to move the port
1150          * to transcoder A after disabling it to allow the
1151          * matching DP port to be enabled on transcoder A.
1152          */
1153         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1154                 /*
1155                  * We get CPU/PCH FIFO underruns on the other pipe when
1156                  * doing the workaround. Sweep them under the rug.
1157                  */
1158                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1159                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1160
1161                 temp &= ~SDVO_PIPE_B_SELECT;
1162                 temp |= SDVO_ENABLE;
1163                 /*
1164                  * HW workaround, need to write this twice for issue
1165                  * that may result in first write getting masked.
1166                  */
1167                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1168                 POSTING_READ(intel_hdmi->hdmi_reg);
1169                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1170                 POSTING_READ(intel_hdmi->hdmi_reg);
1171
1172                 temp &= ~SDVO_ENABLE;
1173                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1174                 POSTING_READ(intel_hdmi->hdmi_reg);
1175
1176                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1177                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1178                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1179         }
1180
1181         intel_hdmi->set_infoframes(&encoder->base, false, old_crtc_state, old_conn_state);
1182
1183         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1184 }
1185
1186 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1187                              struct intel_crtc_state *old_crtc_state,
1188                              struct drm_connector_state *old_conn_state)
1189 {
1190         if (old_crtc_state->has_audio)
1191                 intel_audio_codec_disable(encoder);
1192
1193         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1194 }
1195
1196 static void pch_disable_hdmi(struct intel_encoder *encoder,
1197                              struct intel_crtc_state *old_crtc_state,
1198                              struct drm_connector_state *old_conn_state)
1199 {
1200         if (old_crtc_state->has_audio)
1201                 intel_audio_codec_disable(encoder);
1202 }
1203
1204 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1205                                   struct intel_crtc_state *old_crtc_state,
1206                                   struct drm_connector_state *old_conn_state)
1207 {
1208         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1209 }
1210
1211 static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv)
1212 {
1213         if (IS_G4X(dev_priv))
1214                 return 165000;
1215         else if (IS_GEMINILAKE(dev_priv))
1216                 return 594000;
1217         else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
1218                 return 300000;
1219         else
1220                 return 225000;
1221 }
1222
1223 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1224                                  bool respect_downstream_limits,
1225                                  bool force_dvi)
1226 {
1227         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1228         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));
1229
1230         if (respect_downstream_limits) {
1231                 struct intel_connector *connector = hdmi->attached_connector;
1232                 const struct drm_display_info *info = &connector->base.display_info;
1233
1234                 if (hdmi->dp_dual_mode.max_tmds_clock)
1235                         max_tmds_clock = min(max_tmds_clock,
1236                                              hdmi->dp_dual_mode.max_tmds_clock);
1237
1238                 if (info->max_tmds_clock)
1239                         max_tmds_clock = min(max_tmds_clock,
1240                                              info->max_tmds_clock);
1241                 else if (!hdmi->has_hdmi_sink || force_dvi)
1242                         max_tmds_clock = min(max_tmds_clock, 165000);
1243         }
1244
1245         return max_tmds_clock;
1246 }
1247
1248 static enum drm_mode_status
1249 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1250                       int clock, bool respect_downstream_limits,
1251                       bool force_dvi)
1252 {
1253         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1254
1255         if (clock < 25000)
1256                 return MODE_CLOCK_LOW;
1257         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
1258                 return MODE_CLOCK_HIGH;
1259
1260         /* BXT DPLL can't generate 223-240 MHz */
1261         if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1262                 return MODE_CLOCK_RANGE;
1263
1264         /* CHV DPLL can't generate 216-240 MHz */
1265         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1266                 return MODE_CLOCK_RANGE;
1267
1268         return MODE_OK;
1269 }
1270
1271 static enum drm_mode_status
1272 intel_hdmi_mode_valid(struct drm_connector *connector,
1273                       struct drm_display_mode *mode)
1274 {
1275         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1276         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1277         struct drm_i915_private *dev_priv = to_i915(dev);
1278         enum drm_mode_status status;
1279         int clock;
1280         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1281         bool force_dvi =
1282                 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
1283
1284         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1285                 return MODE_NO_DBLESCAN;
1286
1287         clock = mode->clock;
1288
1289         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1290                 clock *= 2;
1291
1292         if (clock > max_dotclk)
1293                 return MODE_CLOCK_HIGH;
1294
1295         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1296                 clock *= 2;
1297
1298         /* check if we can do 8bpc */
1299         status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
1300
1301         /* if we can't do 8bpc we may still be able to do 12bpc */
1302         if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK && hdmi->has_hdmi_sink && !force_dvi)
1303                 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true, force_dvi);
1304
1305         return status;
1306 }
1307
1308 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1309 {
1310         struct drm_i915_private *dev_priv =
1311                 to_i915(crtc_state->base.crtc->dev);
1312         struct drm_atomic_state *state = crtc_state->base.state;
1313         struct drm_connector_state *connector_state;
1314         struct drm_connector *connector;
1315         int i;
1316
1317         if (HAS_GMCH_DISPLAY(dev_priv))
1318                 return false;
1319
1320         /*
1321          * HDMI 12bpc affects the clocks, so it's only possible
1322          * when not cloning with other encoder types.
1323          */
1324         if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
1325                 return false;
1326
1327         for_each_new_connector_in_state(state, connector, connector_state, i) {
1328                 const struct drm_display_info *info = &connector->display_info;
1329
1330                 if (connector_state->crtc != crtc_state->base.crtc)
1331                         continue;
1332
1333                 if ((info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36) == 0)
1334                         return false;
1335         }
1336
1337         /* Display Wa #1139 */
1338         if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
1339             crtc_state->base.adjusted_mode.htotal > 5460)
1340                 return false;
1341
1342         return true;
1343 }
1344
1345 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1346                                struct intel_crtc_state *pipe_config,
1347                                struct drm_connector_state *conn_state)
1348 {
1349         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1350         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1351         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1352         struct drm_scdc *scdc = &conn_state->connector->display_info.hdmi.scdc;
1353         struct intel_digital_connector_state *intel_conn_state =
1354                 to_intel_digital_connector_state(conn_state);
1355         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1356         int clock_12bpc = clock_8bpc * 3 / 2;
1357         int desired_bpp;
1358         bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
1359
1360         pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
1361
1362         if (pipe_config->has_hdmi_sink)
1363                 pipe_config->has_infoframe = true;
1364
1365         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1366                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1367                 pipe_config->limited_color_range =
1368                         pipe_config->has_hdmi_sink &&
1369                         drm_default_rgb_quant_range(adjusted_mode) ==
1370                         HDMI_QUANTIZATION_RANGE_LIMITED;
1371         } else {
1372                 pipe_config->limited_color_range =
1373                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1374         }
1375
1376         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1377                 pipe_config->pixel_multiplier = 2;
1378                 clock_8bpc *= 2;
1379                 clock_12bpc *= 2;
1380         }
1381
1382         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1383                 pipe_config->has_pch_encoder = true;
1384
1385         if (pipe_config->has_hdmi_sink) {
1386                 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1387                         pipe_config->has_audio = intel_hdmi->has_audio;
1388                 else
1389                         pipe_config->has_audio =
1390                                 intel_conn_state->force_audio == HDMI_AUDIO_ON;
1391         }
1392
1393         /*
1394          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1395          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1396          * outputs. We also need to check that the higher clock still fits
1397          * within limits.
1398          */
1399         if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && !force_dvi &&
1400             hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true, force_dvi) == MODE_OK &&
1401             hdmi_12bpc_possible(pipe_config)) {
1402                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1403                 desired_bpp = 12*3;
1404
1405                 /* Need to adjust the port link by 1.5x for 12bpc. */
1406                 pipe_config->port_clock = clock_12bpc;
1407         } else {
1408                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1409                 desired_bpp = 8*3;
1410
1411                 pipe_config->port_clock = clock_8bpc;
1412         }
1413
1414         if (!pipe_config->bw_constrained) {
1415                 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
1416                 pipe_config->pipe_bpp = desired_bpp;
1417         }
1418
1419         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1420                                   false, force_dvi) != MODE_OK) {
1421                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1422                 return false;
1423         }
1424
1425         /* Set user selected PAR to incoming mode's member */
1426         adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1427
1428         pipe_config->lane_count = 4;
1429
1430         if (scdc->scrambling.supported && IS_GEMINILAKE(dev_priv)) {
1431                 if (scdc->scrambling.low_rates)
1432                         pipe_config->hdmi_scrambling = true;
1433
1434                 if (pipe_config->port_clock > 340000) {
1435                         pipe_config->hdmi_scrambling = true;
1436                         pipe_config->hdmi_high_tmds_clock_ratio = true;
1437                 }
1438         }
1439
1440         return true;
1441 }
1442
1443 static void
1444 intel_hdmi_unset_edid(struct drm_connector *connector)
1445 {
1446         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1447
1448         intel_hdmi->has_hdmi_sink = false;
1449         intel_hdmi->has_audio = false;
1450         intel_hdmi->rgb_quant_range_selectable = false;
1451
1452         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1453         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1454
1455         kfree(to_intel_connector(connector)->detect_edid);
1456         to_intel_connector(connector)->detect_edid = NULL;
1457 }
1458
1459 static void
1460 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1461 {
1462         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1463         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1464         enum port port = hdmi_to_dig_port(hdmi)->port;
1465         struct i2c_adapter *adapter =
1466                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1467         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1468
1469         /*
1470          * Type 1 DVI adaptors are not required to implement any
1471          * registers, so we can't always detect their presence.
1472          * Ideally we should be able to check the state of the
1473          * CONFIG1 pin, but no such luck on our hardware.
1474          *
1475          * The only method left to us is to check the VBT to see
1476          * if the port is a dual mode capable DP port. But let's
1477          * only do that when we sucesfully read the EDID, to avoid
1478          * confusing log messages about DP dual mode adaptors when
1479          * there's nothing connected to the port.
1480          */
1481         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1482                 if (has_edid &&
1483                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1484                         DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1485                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1486                 } else {
1487                         type = DRM_DP_DUAL_MODE_NONE;
1488                 }
1489         }
1490
1491         if (type == DRM_DP_DUAL_MODE_NONE)
1492                 return;
1493
1494         hdmi->dp_dual_mode.type = type;
1495         hdmi->dp_dual_mode.max_tmds_clock =
1496                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1497
1498         DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1499                       drm_dp_get_dual_mode_type_name(type),
1500                       hdmi->dp_dual_mode.max_tmds_clock);
1501 }
1502
1503 static bool
1504 intel_hdmi_set_edid(struct drm_connector *connector)
1505 {
1506         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1507         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1508         struct edid *edid;
1509         bool connected = false;
1510
1511         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1512
1513         edid = drm_get_edid(connector,
1514                             intel_gmbus_get_adapter(dev_priv,
1515                             intel_hdmi->ddc_bus));
1516
1517         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1518
1519         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1520
1521         to_intel_connector(connector)->detect_edid = edid;
1522         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1523                 intel_hdmi->rgb_quant_range_selectable =
1524                         drm_rgb_quant_range_selectable(edid);
1525
1526                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1527                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
1528
1529                 connected = true;
1530         }
1531
1532         return connected;
1533 }
1534
1535 static enum drm_connector_status
1536 intel_hdmi_detect(struct drm_connector *connector, bool force)
1537 {
1538         enum drm_connector_status status;
1539         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1540
1541         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1542                       connector->base.id, connector->name);
1543
1544         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1545
1546         intel_hdmi_unset_edid(connector);
1547
1548         if (intel_hdmi_set_edid(connector)) {
1549                 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1550
1551                 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1552                 status = connector_status_connected;
1553         } else
1554                 status = connector_status_disconnected;
1555
1556         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1557
1558         return status;
1559 }
1560
1561 static void
1562 intel_hdmi_force(struct drm_connector *connector)
1563 {
1564         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1565
1566         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1567                       connector->base.id, connector->name);
1568
1569         intel_hdmi_unset_edid(connector);
1570
1571         if (connector->status != connector_status_connected)
1572                 return;
1573
1574         intel_hdmi_set_edid(connector);
1575         hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1576 }
1577
1578 static int intel_hdmi_get_modes(struct drm_connector *connector)
1579 {
1580         struct edid *edid;
1581
1582         edid = to_intel_connector(connector)->detect_edid;
1583         if (edid == NULL)
1584                 return 0;
1585
1586         return intel_connector_update_modes(connector, edid);
1587 }
1588
1589 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1590                                   struct intel_crtc_state *pipe_config,
1591                                   struct drm_connector_state *conn_state)
1592 {
1593         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1594
1595         intel_hdmi_prepare(encoder, pipe_config);
1596
1597         intel_hdmi->set_infoframes(&encoder->base,
1598                                    pipe_config->has_hdmi_sink,
1599                                    pipe_config, conn_state);
1600 }
1601
1602 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1603                                 struct intel_crtc_state *pipe_config,
1604                                 struct drm_connector_state *conn_state)
1605 {
1606         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1607         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1608         struct drm_device *dev = encoder->base.dev;
1609         struct drm_i915_private *dev_priv = to_i915(dev);
1610
1611         vlv_phy_pre_encoder_enable(encoder);
1612
1613         /* HDMI 1.0V-2dB */
1614         vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
1615                                  0x2b247878);
1616
1617         intel_hdmi->set_infoframes(&encoder->base,
1618                                    pipe_config->has_hdmi_sink,
1619                                    pipe_config, conn_state);
1620
1621         g4x_enable_hdmi(encoder, pipe_config, conn_state);
1622
1623         vlv_wait_port_ready(dev_priv, dport, 0x0);
1624 }
1625
1626 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1627                                     struct intel_crtc_state *pipe_config,
1628                                     struct drm_connector_state *conn_state)
1629 {
1630         intel_hdmi_prepare(encoder, pipe_config);
1631
1632         vlv_phy_pre_pll_enable(encoder);
1633 }
1634
1635 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1636                                     struct intel_crtc_state *pipe_config,
1637                                     struct drm_connector_state *conn_state)
1638 {
1639         intel_hdmi_prepare(encoder, pipe_config);
1640
1641         chv_phy_pre_pll_enable(encoder);
1642 }
1643
1644 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
1645                                       struct intel_crtc_state *old_crtc_state,
1646                                       struct drm_connector_state *old_conn_state)
1647 {
1648         chv_phy_post_pll_disable(encoder);
1649 }
1650
1651 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
1652                                   struct intel_crtc_state *old_crtc_state,
1653                                   struct drm_connector_state *old_conn_state)
1654 {
1655         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1656         vlv_phy_reset_lanes(encoder);
1657 }
1658
1659 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
1660                                   struct intel_crtc_state *old_crtc_state,
1661                                   struct drm_connector_state *old_conn_state)
1662 {
1663         struct drm_device *dev = encoder->base.dev;
1664         struct drm_i915_private *dev_priv = to_i915(dev);
1665
1666         mutex_lock(&dev_priv->sb_lock);
1667
1668         /* Assert data lane reset */
1669         chv_data_lane_soft_reset(encoder, true);
1670
1671         mutex_unlock(&dev_priv->sb_lock);
1672 }
1673
1674 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
1675                                 struct intel_crtc_state *pipe_config,
1676                                 struct drm_connector_state *conn_state)
1677 {
1678         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1679         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1680         struct drm_device *dev = encoder->base.dev;
1681         struct drm_i915_private *dev_priv = to_i915(dev);
1682
1683         chv_phy_pre_encoder_enable(encoder);
1684
1685         /* FIXME: Program the support xxx V-dB */
1686         /* Use 800mV-0dB */
1687         chv_set_phy_signal_level(encoder, 128, 102, false);
1688
1689         intel_hdmi->set_infoframes(&encoder->base,
1690                                    pipe_config->has_hdmi_sink,
1691                                    pipe_config, conn_state);
1692
1693         g4x_enable_hdmi(encoder, pipe_config, conn_state);
1694
1695         vlv_wait_port_ready(dev_priv, dport, 0x0);
1696
1697         /* Second common lane will stay alive on its own now */
1698         chv_phy_release_cl2_override(encoder);
1699 }
1700
1701 static void intel_hdmi_destroy(struct drm_connector *connector)
1702 {
1703         kfree(to_intel_connector(connector)->detect_edid);
1704         drm_connector_cleanup(connector);
1705         kfree(connector);
1706 }
1707
1708 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1709         .detect = intel_hdmi_detect,
1710         .force = intel_hdmi_force,
1711         .fill_modes = drm_helper_probe_single_connector_modes,
1712         .atomic_get_property = intel_digital_connector_atomic_get_property,
1713         .atomic_set_property = intel_digital_connector_atomic_set_property,
1714         .late_register = intel_connector_register,
1715         .early_unregister = intel_connector_unregister,
1716         .destroy = intel_hdmi_destroy,
1717         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1718         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1719 };
1720
1721 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1722         .get_modes = intel_hdmi_get_modes,
1723         .mode_valid = intel_hdmi_mode_valid,
1724         .atomic_check = intel_digital_connector_atomic_check,
1725 };
1726
1727 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1728         .destroy = intel_encoder_destroy,
1729 };
1730
1731 static void
1732 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1733 {
1734         intel_attach_force_audio_property(connector);
1735         intel_attach_broadcast_rgb_property(connector);
1736         intel_attach_aspect_ratio_property(connector);
1737         connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1738 }
1739
1740 /*
1741  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
1742  * @encoder: intel_encoder
1743  * @connector: drm_connector
1744  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
1745  *  or reset the high tmds clock ratio for scrambling
1746  * @scrambling: bool to Indicate if the function needs to set or reset
1747  *  sink scrambling
1748  *
1749  * This function handles scrambling on HDMI 2.0 capable sinks.
1750  * If required clock rate is > 340 Mhz && scrambling is supported by sink
1751  * it enables scrambling. This should be called before enabling the HDMI
1752  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
1753  * detect a scrambled clock within 100 ms.
1754  */
1755 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1756                                        struct drm_connector *connector,
1757                                        bool high_tmds_clock_ratio,
1758                                        bool scrambling)
1759 {
1760         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1761         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1762         struct drm_scrambling *sink_scrambling =
1763                                 &connector->display_info.hdmi.scdc.scrambling;
1764         struct i2c_adapter *adptr = intel_gmbus_get_adapter(dev_priv,
1765                                                            intel_hdmi->ddc_bus);
1766         bool ret;
1767
1768         if (!sink_scrambling->supported)
1769                 return;
1770
1771         DRM_DEBUG_KMS("Setting sink scrambling for enc:%s connector:%s\n",
1772                       encoder->base.name, connector->name);
1773
1774         /* Set TMDS bit clock ratio to 1/40 or 1/10 */
1775         ret = drm_scdc_set_high_tmds_clock_ratio(adptr, high_tmds_clock_ratio);
1776         if (!ret) {
1777                 DRM_ERROR("Set TMDS ratio failed\n");
1778                 return;
1779         }
1780
1781         /* Enable/disable sink scrambling */
1782         ret = drm_scdc_set_scrambling(adptr, scrambling);
1783         if (!ret) {
1784                 DRM_ERROR("Set sink scrambling failed\n");
1785                 return;
1786         }
1787
1788         DRM_DEBUG_KMS("sink scrambling handled\n");
1789 }
1790
1791 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
1792                              enum port port)
1793 {
1794         const struct ddi_vbt_port_info *info =
1795                 &dev_priv->vbt.ddi_port_info[port];
1796         u8 ddc_pin;
1797
1798         if (info->alternate_ddc_pin) {
1799                 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
1800                               info->alternate_ddc_pin, port_name(port));
1801                 return info->alternate_ddc_pin;
1802         }
1803
1804         switch (port) {
1805         case PORT_B:
1806                 if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
1807                         ddc_pin = GMBUS_PIN_1_BXT;
1808                 else
1809                         ddc_pin = GMBUS_PIN_DPB;
1810                 break;
1811         case PORT_C:
1812                 if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
1813                         ddc_pin = GMBUS_PIN_2_BXT;
1814                 else
1815                         ddc_pin = GMBUS_PIN_DPC;
1816                 break;
1817         case PORT_D:
1818                 if (HAS_PCH_CNP(dev_priv))
1819                         ddc_pin = GMBUS_PIN_4_CNP;
1820                 else if (IS_CHERRYVIEW(dev_priv))
1821                         ddc_pin = GMBUS_PIN_DPD_CHV;
1822                 else
1823                         ddc_pin = GMBUS_PIN_DPD;
1824                 break;
1825         default:
1826                 MISSING_CASE(port);
1827                 ddc_pin = GMBUS_PIN_DPB;
1828                 break;
1829         }
1830
1831         DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
1832                       ddc_pin, port_name(port));
1833
1834         return ddc_pin;
1835 }
1836
1837 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1838                                struct intel_connector *intel_connector)
1839 {
1840         struct drm_connector *connector = &intel_connector->base;
1841         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1842         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1843         struct drm_device *dev = intel_encoder->base.dev;
1844         struct drm_i915_private *dev_priv = to_i915(dev);
1845         enum port port = intel_dig_port->port;
1846
1847         DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
1848                       port_name(port));
1849
1850         if (WARN(intel_dig_port->max_lanes < 4,
1851                  "Not enough lanes (%d) for HDMI on port %c\n",
1852                  intel_dig_port->max_lanes, port_name(port)))
1853                 return;
1854
1855         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1856                            DRM_MODE_CONNECTOR_HDMIA);
1857         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1858
1859         connector->interlace_allowed = 1;
1860         connector->doublescan_allowed = 0;
1861         connector->stereo_allowed = 1;
1862
1863         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
1864
1865         switch (port) {
1866         case PORT_B:
1867                 intel_encoder->hpd_pin = HPD_PORT_B;
1868                 break;
1869         case PORT_C:
1870                 intel_encoder->hpd_pin = HPD_PORT_C;
1871                 break;
1872         case PORT_D:
1873                 intel_encoder->hpd_pin = HPD_PORT_D;
1874                 break;
1875         case PORT_E:
1876                 intel_encoder->hpd_pin = HPD_PORT_E;
1877                 break;
1878         default:
1879                 MISSING_CASE(port);
1880                 return;
1881         }
1882
1883         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1884                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1885                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1886                 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
1887         } else if (IS_G4X(dev_priv)) {
1888                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1889                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1890                 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
1891         } else if (HAS_DDI(dev_priv)) {
1892                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1893                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1894                 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
1895         } else if (HAS_PCH_IBX(dev_priv)) {
1896                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1897                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1898                 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
1899         } else {
1900                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1901                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1902                 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
1903         }
1904
1905         if (HAS_DDI(dev_priv))
1906                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1907         else
1908                 intel_connector->get_hw_state = intel_connector_get_hw_state;
1909
1910         intel_hdmi_add_properties(intel_hdmi, connector);
1911
1912         intel_connector_attach_encoder(intel_connector, intel_encoder);
1913         intel_hdmi->attached_connector = intel_connector;
1914
1915         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1916          * 0xd.  Failure to do so will result in spurious interrupts being
1917          * generated on the port when a cable is not attached.
1918          */
1919         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
1920                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1921                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1922         }
1923 }
1924
1925 void intel_hdmi_init(struct drm_i915_private *dev_priv,
1926                      i915_reg_t hdmi_reg, enum port port)
1927 {
1928         struct intel_digital_port *intel_dig_port;
1929         struct intel_encoder *intel_encoder;
1930         struct intel_connector *intel_connector;
1931
1932         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1933         if (!intel_dig_port)
1934                 return;
1935
1936         intel_connector = intel_connector_alloc();
1937         if (!intel_connector) {
1938                 kfree(intel_dig_port);
1939                 return;
1940         }
1941
1942         intel_encoder = &intel_dig_port->base;
1943
1944         drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
1945                          &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
1946                          "HDMI %c", port_name(port));
1947
1948         intel_encoder->compute_config = intel_hdmi_compute_config;
1949         if (HAS_PCH_SPLIT(dev_priv)) {
1950                 intel_encoder->disable = pch_disable_hdmi;
1951                 intel_encoder->post_disable = pch_post_disable_hdmi;
1952         } else {
1953                 intel_encoder->disable = g4x_disable_hdmi;
1954         }
1955         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1956         intel_encoder->get_config = intel_hdmi_get_config;
1957         if (IS_CHERRYVIEW(dev_priv)) {
1958                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
1959                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
1960                 intel_encoder->enable = vlv_enable_hdmi;
1961                 intel_encoder->post_disable = chv_hdmi_post_disable;
1962                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
1963         } else if (IS_VALLEYVIEW(dev_priv)) {
1964                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1965                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1966                 intel_encoder->enable = vlv_enable_hdmi;
1967                 intel_encoder->post_disable = vlv_hdmi_post_disable;
1968         } else {
1969                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1970                 if (HAS_PCH_CPT(dev_priv))
1971                         intel_encoder->enable = cpt_enable_hdmi;
1972                 else if (HAS_PCH_IBX(dev_priv))
1973                         intel_encoder->enable = ibx_enable_hdmi;
1974                 else
1975                         intel_encoder->enable = g4x_enable_hdmi;
1976         }
1977
1978         intel_encoder->type = INTEL_OUTPUT_HDMI;
1979         intel_encoder->power_domain = intel_port_to_power_domain(port);
1980         intel_encoder->port = port;
1981         if (IS_CHERRYVIEW(dev_priv)) {
1982                 if (port == PORT_D)
1983                         intel_encoder->crtc_mask = 1 << 2;
1984                 else
1985                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1986         } else {
1987                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1988         }
1989         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
1990         /*
1991          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1992          * to work on real hardware. And since g4x can send infoframes to
1993          * only one port anyway, nothing is lost by allowing it.
1994          */
1995         if (IS_G4X(dev_priv))
1996                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
1997
1998         intel_dig_port->port = port;
1999         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2000         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2001         intel_dig_port->max_lanes = 4;
2002
2003         intel_hdmi_init_connector(intel_dig_port, intel_connector);
2004 }