2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
35 #include "intel_drv.h"
40 assert_hdmi_port_disabled(struct intel_hdmi
*intel_hdmi
)
42 struct drm_device
*dev
= intel_hdmi
->base
.base
.dev
;
43 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
44 uint32_t enabled_bits
;
46 enabled_bits
= IS_HASWELL(dev
) ? DDI_BUF_CTL_ENABLE
: SDVO_ENABLE
;
48 WARN(I915_READ(intel_hdmi
->sdvox_reg
) & enabled_bits
,
49 "HDMI port enabled, expecting disabled\n");
52 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
)
54 return container_of(encoder
, struct intel_hdmi
, base
.base
);
57 static struct intel_hdmi
*intel_attached_hdmi(struct drm_connector
*connector
)
59 return container_of(intel_attached_encoder(connector
),
60 struct intel_hdmi
, base
);
63 void intel_dip_infoframe_csum(struct dip_infoframe
*frame
)
65 uint8_t *data
= (uint8_t *)frame
;
72 for (i
= 0; i
< frame
->len
+ DIP_HEADER_SIZE
; i
++)
75 frame
->checksum
= 0x100 - sum
;
78 static u32
g4x_infoframe_index(struct dip_infoframe
*frame
)
80 switch (frame
->type
) {
82 return VIDEO_DIP_SELECT_AVI
;
84 return VIDEO_DIP_SELECT_SPD
;
86 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame
->type
);
91 static u32
g4x_infoframe_enable(struct dip_infoframe
*frame
)
93 switch (frame
->type
) {
95 return VIDEO_DIP_ENABLE_AVI
;
97 return VIDEO_DIP_ENABLE_SPD
;
99 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame
->type
);
104 static u32
hsw_infoframe_enable(struct dip_infoframe
*frame
)
106 switch (frame
->type
) {
108 return VIDEO_DIP_ENABLE_AVI_HSW
;
110 return VIDEO_DIP_ENABLE_SPD_HSW
;
112 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame
->type
);
117 static u32
hsw_infoframe_data_reg(struct dip_infoframe
*frame
, enum pipe pipe
)
119 switch (frame
->type
) {
121 return HSW_TVIDEO_DIP_AVI_DATA(pipe
);
123 return HSW_TVIDEO_DIP_SPD_DATA(pipe
);
125 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame
->type
);
130 static void g4x_write_infoframe(struct drm_encoder
*encoder
,
131 struct dip_infoframe
*frame
)
133 uint32_t *data
= (uint32_t *)frame
;
134 struct drm_device
*dev
= encoder
->dev
;
135 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
136 u32 val
= I915_READ(VIDEO_DIP_CTL
);
137 unsigned i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
139 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
141 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
142 val
|= g4x_infoframe_index(frame
);
144 val
&= ~g4x_infoframe_enable(frame
);
146 I915_WRITE(VIDEO_DIP_CTL
, val
);
149 for (i
= 0; i
< len
; i
+= 4) {
150 I915_WRITE(VIDEO_DIP_DATA
, *data
);
155 val
|= g4x_infoframe_enable(frame
);
156 val
&= ~VIDEO_DIP_FREQ_MASK
;
157 val
|= VIDEO_DIP_FREQ_VSYNC
;
159 I915_WRITE(VIDEO_DIP_CTL
, val
);
160 POSTING_READ(VIDEO_DIP_CTL
);
163 static void ibx_write_infoframe(struct drm_encoder
*encoder
,
164 struct dip_infoframe
*frame
)
166 uint32_t *data
= (uint32_t *)frame
;
167 struct drm_device
*dev
= encoder
->dev
;
168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
169 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
170 int reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
171 unsigned i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
172 u32 val
= I915_READ(reg
);
174 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
176 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
177 val
|= g4x_infoframe_index(frame
);
179 val
&= ~g4x_infoframe_enable(frame
);
181 I915_WRITE(reg
, val
);
184 for (i
= 0; i
< len
; i
+= 4) {
185 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
190 val
|= g4x_infoframe_enable(frame
);
191 val
&= ~VIDEO_DIP_FREQ_MASK
;
192 val
|= VIDEO_DIP_FREQ_VSYNC
;
194 I915_WRITE(reg
, val
);
198 static void cpt_write_infoframe(struct drm_encoder
*encoder
,
199 struct dip_infoframe
*frame
)
201 uint32_t *data
= (uint32_t *)frame
;
202 struct drm_device
*dev
= encoder
->dev
;
203 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
204 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
205 int reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
206 unsigned i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
207 u32 val
= I915_READ(reg
);
209 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
211 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
212 val
|= g4x_infoframe_index(frame
);
214 /* The DIP control register spec says that we need to update the AVI
215 * infoframe without clearing its enable bit */
216 if (frame
->type
!= DIP_TYPE_AVI
)
217 val
&= ~g4x_infoframe_enable(frame
);
219 I915_WRITE(reg
, val
);
222 for (i
= 0; i
< len
; i
+= 4) {
223 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
228 val
|= g4x_infoframe_enable(frame
);
229 val
&= ~VIDEO_DIP_FREQ_MASK
;
230 val
|= VIDEO_DIP_FREQ_VSYNC
;
232 I915_WRITE(reg
, val
);
236 static void vlv_write_infoframe(struct drm_encoder
*encoder
,
237 struct dip_infoframe
*frame
)
239 uint32_t *data
= (uint32_t *)frame
;
240 struct drm_device
*dev
= encoder
->dev
;
241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
242 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
243 int reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
244 unsigned i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
245 u32 val
= I915_READ(reg
);
247 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
249 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
250 val
|= g4x_infoframe_index(frame
);
252 val
&= ~g4x_infoframe_enable(frame
);
254 I915_WRITE(reg
, val
);
257 for (i
= 0; i
< len
; i
+= 4) {
258 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
263 val
|= g4x_infoframe_enable(frame
);
264 val
&= ~VIDEO_DIP_FREQ_MASK
;
265 val
|= VIDEO_DIP_FREQ_VSYNC
;
267 I915_WRITE(reg
, val
);
271 static void hsw_write_infoframe(struct drm_encoder
*encoder
,
272 struct dip_infoframe
*frame
)
274 uint32_t *data
= (uint32_t *)frame
;
275 struct drm_device
*dev
= encoder
->dev
;
276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
277 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
278 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
279 u32 data_reg
= hsw_infoframe_data_reg(frame
, intel_crtc
->pipe
);
280 unsigned int i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
281 u32 val
= I915_READ(ctl_reg
);
286 val
&= ~hsw_infoframe_enable(frame
);
287 I915_WRITE(ctl_reg
, val
);
290 for (i
= 0; i
< len
; i
+= 4) {
291 I915_WRITE(data_reg
+ i
, *data
);
296 val
|= hsw_infoframe_enable(frame
);
297 I915_WRITE(ctl_reg
, val
);
298 POSTING_READ(ctl_reg
);
301 static void intel_set_infoframe(struct drm_encoder
*encoder
,
302 struct dip_infoframe
*frame
)
304 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
306 intel_dip_infoframe_csum(frame
);
307 intel_hdmi
->write_infoframe(encoder
, frame
);
310 static void intel_hdmi_set_avi_infoframe(struct drm_encoder
*encoder
,
311 struct drm_display_mode
*adjusted_mode
)
313 struct dip_infoframe avi_if
= {
314 .type
= DIP_TYPE_AVI
,
315 .ver
= DIP_VERSION_AVI
,
319 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
320 avi_if
.body
.avi
.YQ_CN_PR
|= DIP_AVI_PR_2
;
322 intel_set_infoframe(encoder
, &avi_if
);
325 static void intel_hdmi_set_spd_infoframe(struct drm_encoder
*encoder
)
327 struct dip_infoframe spd_if
;
329 memset(&spd_if
, 0, sizeof(spd_if
));
330 spd_if
.type
= DIP_TYPE_SPD
;
331 spd_if
.ver
= DIP_VERSION_SPD
;
332 spd_if
.len
= DIP_LEN_SPD
;
333 strcpy(spd_if
.body
.spd
.vn
, "Intel");
334 strcpy(spd_if
.body
.spd
.pd
, "Integrated gfx");
335 spd_if
.body
.spd
.sdi
= DIP_SPD_PC
;
337 intel_set_infoframe(encoder
, &spd_if
);
340 static void g4x_set_infoframes(struct drm_encoder
*encoder
,
341 struct drm_display_mode
*adjusted_mode
)
343 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
344 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
345 u32 reg
= VIDEO_DIP_CTL
;
346 u32 val
= I915_READ(reg
);
349 assert_hdmi_port_disabled(intel_hdmi
);
351 /* If the registers were not initialized yet, they might be zeroes,
352 * which means we're selecting the AVI DIP and we're setting its
353 * frequency to once. This seems to really confuse the HW and make
354 * things stop working (the register spec says the AVI always needs to
355 * be sent every VSync). So here we avoid writing to the register more
356 * than we need and also explicitly select the AVI DIP and explicitly
357 * set its frequency to every VSync. Avoiding to write it twice seems to
358 * be enough to solve the problem, but being defensive shouldn't hurt us
360 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
362 if (!intel_hdmi
->has_hdmi_sink
) {
363 if (!(val
& VIDEO_DIP_ENABLE
))
365 val
&= ~VIDEO_DIP_ENABLE
;
366 I915_WRITE(reg
, val
);
371 switch (intel_hdmi
->sdvox_reg
) {
373 port
= VIDEO_DIP_PORT_B
;
376 port
= VIDEO_DIP_PORT_C
;
382 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
383 if (val
& VIDEO_DIP_ENABLE
) {
384 val
&= ~VIDEO_DIP_ENABLE
;
385 I915_WRITE(reg
, val
);
388 val
&= ~VIDEO_DIP_PORT_MASK
;
392 val
|= VIDEO_DIP_ENABLE
;
393 val
&= ~VIDEO_DIP_ENABLE_VENDOR
;
395 I915_WRITE(reg
, val
);
398 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
399 intel_hdmi_set_spd_infoframe(encoder
);
402 static void ibx_set_infoframes(struct drm_encoder
*encoder
,
403 struct drm_display_mode
*adjusted_mode
)
405 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
406 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
407 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
408 u32 reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
409 u32 val
= I915_READ(reg
);
412 assert_hdmi_port_disabled(intel_hdmi
);
414 /* See the big comment in g4x_set_infoframes() */
415 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
417 if (!intel_hdmi
->has_hdmi_sink
) {
418 if (!(val
& VIDEO_DIP_ENABLE
))
420 val
&= ~VIDEO_DIP_ENABLE
;
421 I915_WRITE(reg
, val
);
426 switch (intel_hdmi
->sdvox_reg
) {
428 port
= VIDEO_DIP_PORT_B
;
431 port
= VIDEO_DIP_PORT_C
;
434 port
= VIDEO_DIP_PORT_D
;
440 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
441 if (val
& VIDEO_DIP_ENABLE
) {
442 val
&= ~VIDEO_DIP_ENABLE
;
443 I915_WRITE(reg
, val
);
446 val
&= ~VIDEO_DIP_PORT_MASK
;
450 val
|= VIDEO_DIP_ENABLE
;
451 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
452 VIDEO_DIP_ENABLE_GCP
);
454 I915_WRITE(reg
, val
);
457 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
458 intel_hdmi_set_spd_infoframe(encoder
);
461 static void cpt_set_infoframes(struct drm_encoder
*encoder
,
462 struct drm_display_mode
*adjusted_mode
)
464 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
465 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
466 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
467 u32 reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
468 u32 val
= I915_READ(reg
);
470 assert_hdmi_port_disabled(intel_hdmi
);
472 /* See the big comment in g4x_set_infoframes() */
473 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
475 if (!intel_hdmi
->has_hdmi_sink
) {
476 if (!(val
& VIDEO_DIP_ENABLE
))
478 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
);
479 I915_WRITE(reg
, val
);
484 /* Set both together, unset both together: see the spec. */
485 val
|= VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
;
486 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
487 VIDEO_DIP_ENABLE_GCP
);
489 I915_WRITE(reg
, val
);
492 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
493 intel_hdmi_set_spd_infoframe(encoder
);
496 static void vlv_set_infoframes(struct drm_encoder
*encoder
,
497 struct drm_display_mode
*adjusted_mode
)
499 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
500 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
501 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
502 u32 reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
503 u32 val
= I915_READ(reg
);
505 assert_hdmi_port_disabled(intel_hdmi
);
507 /* See the big comment in g4x_set_infoframes() */
508 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
510 if (!intel_hdmi
->has_hdmi_sink
) {
511 if (!(val
& VIDEO_DIP_ENABLE
))
513 val
&= ~VIDEO_DIP_ENABLE
;
514 I915_WRITE(reg
, val
);
519 val
|= VIDEO_DIP_ENABLE
;
520 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
521 VIDEO_DIP_ENABLE_GCP
);
523 I915_WRITE(reg
, val
);
526 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
527 intel_hdmi_set_spd_infoframe(encoder
);
530 static void hsw_set_infoframes(struct drm_encoder
*encoder
,
531 struct drm_display_mode
*adjusted_mode
)
533 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
534 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
535 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
536 u32 reg
= HSW_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
537 u32 val
= I915_READ(reg
);
539 assert_hdmi_port_disabled(intel_hdmi
);
541 if (!intel_hdmi
->has_hdmi_sink
) {
547 val
&= ~(VIDEO_DIP_ENABLE_VSC_HSW
| VIDEO_DIP_ENABLE_GCP_HSW
|
548 VIDEO_DIP_ENABLE_VS_HSW
| VIDEO_DIP_ENABLE_GMP_HSW
);
550 I915_WRITE(reg
, val
);
553 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
554 intel_hdmi_set_spd_infoframe(encoder
);
557 static void intel_hdmi_mode_set(struct drm_encoder
*encoder
,
558 struct drm_display_mode
*mode
,
559 struct drm_display_mode
*adjusted_mode
)
561 struct drm_device
*dev
= encoder
->dev
;
562 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
563 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
564 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
567 sdvox
= SDVO_ENCODING_HDMI
;
568 if (!HAS_PCH_SPLIT(dev
))
569 sdvox
|= intel_hdmi
->color_range
;
570 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
571 sdvox
|= SDVO_VSYNC_ACTIVE_HIGH
;
572 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
573 sdvox
|= SDVO_HSYNC_ACTIVE_HIGH
;
575 if (intel_crtc
->bpp
> 24)
576 sdvox
|= COLOR_FORMAT_12bpc
;
578 sdvox
|= COLOR_FORMAT_8bpc
;
580 /* Required on CPT */
581 if (intel_hdmi
->has_hdmi_sink
&& HAS_PCH_CPT(dev
))
582 sdvox
|= HDMI_MODE_SELECT
;
584 if (intel_hdmi
->has_audio
) {
585 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
586 pipe_name(intel_crtc
->pipe
));
587 sdvox
|= SDVO_AUDIO_ENABLE
;
588 sdvox
|= SDVO_NULL_PACKETS_DURING_VSYNC
;
589 intel_write_eld(encoder
, adjusted_mode
);
592 if (HAS_PCH_CPT(dev
))
593 sdvox
|= PORT_TRANS_SEL_CPT(intel_crtc
->pipe
);
594 else if (intel_crtc
->pipe
== PIPE_B
)
595 sdvox
|= SDVO_PIPE_B_SELECT
;
597 I915_WRITE(intel_hdmi
->sdvox_reg
, sdvox
);
598 POSTING_READ(intel_hdmi
->sdvox_reg
);
600 intel_hdmi
->set_infoframes(encoder
, adjusted_mode
);
603 static void intel_hdmi_dpms(struct drm_encoder
*encoder
, int mode
)
605 struct drm_device
*dev
= encoder
->dev
;
606 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
607 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
609 u32 enable_bits
= SDVO_ENABLE
;
611 if (intel_hdmi
->has_audio
|| mode
!= DRM_MODE_DPMS_ON
)
612 enable_bits
|= SDVO_AUDIO_ENABLE
;
614 temp
= I915_READ(intel_hdmi
->sdvox_reg
);
616 /* HW workaround for IBX, we need to move the port to transcoder A
617 * before disabling it. */
618 if (HAS_PCH_IBX(dev
)) {
619 struct drm_crtc
*crtc
= encoder
->crtc
;
620 int pipe
= crtc
? to_intel_crtc(crtc
)->pipe
: -1;
622 if (mode
!= DRM_MODE_DPMS_ON
) {
623 if (temp
& SDVO_PIPE_B_SELECT
) {
624 temp
&= ~SDVO_PIPE_B_SELECT
;
625 I915_WRITE(intel_hdmi
->sdvox_reg
, temp
);
626 POSTING_READ(intel_hdmi
->sdvox_reg
);
628 /* Again we need to write this twice. */
629 I915_WRITE(intel_hdmi
->sdvox_reg
, temp
);
630 POSTING_READ(intel_hdmi
->sdvox_reg
);
632 /* Transcoder selection bits only update
633 * effectively on vblank. */
635 intel_wait_for_vblank(dev
, pipe
);
640 /* Restore the transcoder select bit. */
642 enable_bits
|= SDVO_PIPE_B_SELECT
;
646 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
647 * we do this anyway which shows more stable in testing.
649 if (HAS_PCH_SPLIT(dev
)) {
650 I915_WRITE(intel_hdmi
->sdvox_reg
, temp
& ~SDVO_ENABLE
);
651 POSTING_READ(intel_hdmi
->sdvox_reg
);
654 if (mode
!= DRM_MODE_DPMS_ON
) {
655 temp
&= ~enable_bits
;
660 I915_WRITE(intel_hdmi
->sdvox_reg
, temp
);
661 POSTING_READ(intel_hdmi
->sdvox_reg
);
663 /* HW workaround, need to write this twice for issue that may result
664 * in first write getting masked.
666 if (HAS_PCH_SPLIT(dev
)) {
667 I915_WRITE(intel_hdmi
->sdvox_reg
, temp
);
668 POSTING_READ(intel_hdmi
->sdvox_reg
);
672 static int intel_hdmi_mode_valid(struct drm_connector
*connector
,
673 struct drm_display_mode
*mode
)
675 if (mode
->clock
> 165000)
676 return MODE_CLOCK_HIGH
;
677 if (mode
->clock
< 20000)
678 return MODE_CLOCK_LOW
;
680 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
681 return MODE_NO_DBLESCAN
;
686 static bool intel_hdmi_mode_fixup(struct drm_encoder
*encoder
,
687 const struct drm_display_mode
*mode
,
688 struct drm_display_mode
*adjusted_mode
)
693 static bool g4x_hdmi_connected(struct intel_hdmi
*intel_hdmi
)
695 struct drm_device
*dev
= intel_hdmi
->base
.base
.dev
;
696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
699 switch (intel_hdmi
->sdvox_reg
) {
701 bit
= HDMIB_HOTPLUG_LIVE_STATUS
;
704 bit
= HDMIC_HOTPLUG_LIVE_STATUS
;
711 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
714 static enum drm_connector_status
715 intel_hdmi_detect(struct drm_connector
*connector
, bool force
)
717 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
718 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
720 enum drm_connector_status status
= connector_status_disconnected
;
722 if (IS_G4X(connector
->dev
) && !g4x_hdmi_connected(intel_hdmi
))
725 intel_hdmi
->has_hdmi_sink
= false;
726 intel_hdmi
->has_audio
= false;
727 edid
= drm_get_edid(connector
,
728 intel_gmbus_get_adapter(dev_priv
,
729 intel_hdmi
->ddc_bus
));
732 if (edid
->input
& DRM_EDID_INPUT_DIGITAL
) {
733 status
= connector_status_connected
;
734 if (intel_hdmi
->force_audio
!= HDMI_AUDIO_OFF_DVI
)
735 intel_hdmi
->has_hdmi_sink
=
736 drm_detect_hdmi_monitor(edid
);
737 intel_hdmi
->has_audio
= drm_detect_monitor_audio(edid
);
739 connector
->display_info
.raw_edid
= NULL
;
743 if (status
== connector_status_connected
) {
744 if (intel_hdmi
->force_audio
!= HDMI_AUDIO_AUTO
)
745 intel_hdmi
->has_audio
=
746 (intel_hdmi
->force_audio
== HDMI_AUDIO_ON
);
752 static int intel_hdmi_get_modes(struct drm_connector
*connector
)
754 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
755 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
757 /* We should parse the EDID data and find out if it's an HDMI sink so
758 * we can send audio to it.
761 return intel_ddc_get_modes(connector
,
762 intel_gmbus_get_adapter(dev_priv
,
763 intel_hdmi
->ddc_bus
));
767 intel_hdmi_detect_audio(struct drm_connector
*connector
)
769 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
770 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
772 bool has_audio
= false;
774 edid
= drm_get_edid(connector
,
775 intel_gmbus_get_adapter(dev_priv
,
776 intel_hdmi
->ddc_bus
));
778 if (edid
->input
& DRM_EDID_INPUT_DIGITAL
)
779 has_audio
= drm_detect_monitor_audio(edid
);
781 connector
->display_info
.raw_edid
= NULL
;
789 intel_hdmi_set_property(struct drm_connector
*connector
,
790 struct drm_property
*property
,
793 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
794 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
797 ret
= drm_connector_property_set_value(connector
, property
, val
);
801 if (property
== dev_priv
->force_audio_property
) {
802 enum hdmi_force_audio i
= val
;
805 if (i
== intel_hdmi
->force_audio
)
808 intel_hdmi
->force_audio
= i
;
810 if (i
== HDMI_AUDIO_AUTO
)
811 has_audio
= intel_hdmi_detect_audio(connector
);
813 has_audio
= (i
== HDMI_AUDIO_ON
);
815 if (i
== HDMI_AUDIO_OFF_DVI
)
816 intel_hdmi
->has_hdmi_sink
= 0;
818 intel_hdmi
->has_audio
= has_audio
;
822 if (property
== dev_priv
->broadcast_rgb_property
) {
823 if (val
== !!intel_hdmi
->color_range
)
826 intel_hdmi
->color_range
= val
? SDVO_COLOR_RANGE_16_235
: 0;
833 if (intel_hdmi
->base
.base
.crtc
) {
834 struct drm_crtc
*crtc
= intel_hdmi
->base
.base
.crtc
;
835 drm_crtc_helper_set_mode(crtc
, &crtc
->mode
,
843 static void intel_hdmi_destroy(struct drm_connector
*connector
)
845 drm_sysfs_connector_remove(connector
);
846 drm_connector_cleanup(connector
);
850 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw
= {
851 .dpms
= intel_ddi_dpms
,
852 .mode_fixup
= intel_hdmi_mode_fixup
,
853 .prepare
= intel_encoder_prepare
,
854 .mode_set
= intel_ddi_mode_set
,
855 .commit
= intel_encoder_commit
,
858 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs
= {
859 .dpms
= intel_hdmi_dpms
,
860 .mode_fixup
= intel_hdmi_mode_fixup
,
861 .prepare
= intel_encoder_prepare
,
862 .mode_set
= intel_hdmi_mode_set
,
863 .commit
= intel_encoder_commit
,
866 static const struct drm_connector_funcs intel_hdmi_connector_funcs
= {
867 .dpms
= drm_helper_connector_dpms
,
868 .detect
= intel_hdmi_detect
,
869 .fill_modes
= drm_helper_probe_single_connector_modes
,
870 .set_property
= intel_hdmi_set_property
,
871 .destroy
= intel_hdmi_destroy
,
874 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs
= {
875 .get_modes
= intel_hdmi_get_modes
,
876 .mode_valid
= intel_hdmi_mode_valid
,
877 .best_encoder
= intel_best_encoder
,
880 static const struct drm_encoder_funcs intel_hdmi_enc_funcs
= {
881 .destroy
= intel_encoder_destroy
,
885 intel_hdmi_add_properties(struct intel_hdmi
*intel_hdmi
, struct drm_connector
*connector
)
887 intel_attach_force_audio_property(connector
);
888 intel_attach_broadcast_rgb_property(connector
);
891 void intel_hdmi_init(struct drm_device
*dev
, int sdvox_reg
)
893 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
894 struct drm_connector
*connector
;
895 struct intel_encoder
*intel_encoder
;
896 struct intel_connector
*intel_connector
;
897 struct intel_hdmi
*intel_hdmi
;
899 intel_hdmi
= kzalloc(sizeof(struct intel_hdmi
), GFP_KERNEL
);
903 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
904 if (!intel_connector
) {
909 intel_encoder
= &intel_hdmi
->base
;
910 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_hdmi_enc_funcs
,
911 DRM_MODE_ENCODER_TMDS
);
913 connector
= &intel_connector
->base
;
914 drm_connector_init(dev
, connector
, &intel_hdmi_connector_funcs
,
915 DRM_MODE_CONNECTOR_HDMIA
);
916 drm_connector_helper_add(connector
, &intel_hdmi_connector_helper_funcs
);
918 intel_encoder
->type
= INTEL_OUTPUT_HDMI
;
920 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
921 connector
->interlace_allowed
= 1;
922 connector
->doublescan_allowed
= 0;
923 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
925 /* Set up the DDC bus. */
926 if (sdvox_reg
== SDVOB
) {
927 intel_encoder
->clone_mask
= (1 << INTEL_HDMIB_CLONE_BIT
);
928 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPB
;
929 dev_priv
->hotplug_supported_mask
|= HDMIB_HOTPLUG_INT_STATUS
;
930 } else if (sdvox_reg
== SDVOC
) {
931 intel_encoder
->clone_mask
= (1 << INTEL_HDMIC_CLONE_BIT
);
932 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPC
;
933 dev_priv
->hotplug_supported_mask
|= HDMIC_HOTPLUG_INT_STATUS
;
934 } else if (sdvox_reg
== HDMIB
) {
935 intel_encoder
->clone_mask
= (1 << INTEL_HDMID_CLONE_BIT
);
936 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPB
;
937 dev_priv
->hotplug_supported_mask
|= HDMIB_HOTPLUG_INT_STATUS
;
938 } else if (sdvox_reg
== HDMIC
) {
939 intel_encoder
->clone_mask
= (1 << INTEL_HDMIE_CLONE_BIT
);
940 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPC
;
941 dev_priv
->hotplug_supported_mask
|= HDMIC_HOTPLUG_INT_STATUS
;
942 } else if (sdvox_reg
== HDMID
) {
943 intel_encoder
->clone_mask
= (1 << INTEL_HDMIF_CLONE_BIT
);
944 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPD
;
945 dev_priv
->hotplug_supported_mask
|= HDMID_HOTPLUG_INT_STATUS
;
946 } else if (sdvox_reg
== DDI_BUF_CTL(PORT_B
)) {
947 DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n");
948 intel_encoder
->clone_mask
= (1 << INTEL_HDMIB_CLONE_BIT
);
949 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPB
;
950 intel_hdmi
->ddi_port
= PORT_B
;
951 dev_priv
->hotplug_supported_mask
|= HDMIB_HOTPLUG_INT_STATUS
;
952 } else if (sdvox_reg
== DDI_BUF_CTL(PORT_C
)) {
953 DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n");
954 intel_encoder
->clone_mask
= (1 << INTEL_HDMIC_CLONE_BIT
);
955 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPC
;
956 intel_hdmi
->ddi_port
= PORT_C
;
957 dev_priv
->hotplug_supported_mask
|= HDMIC_HOTPLUG_INT_STATUS
;
958 } else if (sdvox_reg
== DDI_BUF_CTL(PORT_D
)) {
959 DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n");
960 intel_encoder
->clone_mask
= (1 << INTEL_HDMID_CLONE_BIT
);
961 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPD
;
962 intel_hdmi
->ddi_port
= PORT_D
;
963 dev_priv
->hotplug_supported_mask
|= HDMID_HOTPLUG_INT_STATUS
;
965 /* If we got an unknown sdvox_reg, things are pretty much broken
966 * in a way that we should let the kernel know about it */
970 intel_hdmi
->sdvox_reg
= sdvox_reg
;
972 if (!HAS_PCH_SPLIT(dev
)) {
973 intel_hdmi
->write_infoframe
= g4x_write_infoframe
;
974 intel_hdmi
->set_infoframes
= g4x_set_infoframes
;
975 } else if (IS_VALLEYVIEW(dev
)) {
976 intel_hdmi
->write_infoframe
= vlv_write_infoframe
;
977 intel_hdmi
->set_infoframes
= vlv_set_infoframes
;
978 } else if (IS_HASWELL(dev
)) {
979 intel_hdmi
->write_infoframe
= hsw_write_infoframe
;
980 intel_hdmi
->set_infoframes
= hsw_set_infoframes
;
981 } else if (HAS_PCH_IBX(dev
)) {
982 intel_hdmi
->write_infoframe
= ibx_write_infoframe
;
983 intel_hdmi
->set_infoframes
= ibx_set_infoframes
;
985 intel_hdmi
->write_infoframe
= cpt_write_infoframe
;
986 intel_hdmi
->set_infoframes
= cpt_set_infoframes
;
990 drm_encoder_helper_add(&intel_encoder
->base
, &intel_hdmi_helper_funcs_hsw
);
992 drm_encoder_helper_add(&intel_encoder
->base
, &intel_hdmi_helper_funcs
);
994 intel_hdmi_add_properties(intel_hdmi
, connector
);
996 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
997 drm_sysfs_connector_add(connector
);
999 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1000 * 0xd. Failure to do so will result in spurious interrupts being
1001 * generated on the port when a cable is not attached.
1003 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
1004 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
1005 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);