2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
40 static struct drm_device
*intel_hdmi_to_dev(struct intel_hdmi
*intel_hdmi
)
42 return hdmi_to_dig_port(intel_hdmi
)->base
.base
.dev
;
46 assert_hdmi_port_disabled(struct intel_hdmi
*intel_hdmi
)
48 struct drm_device
*dev
= intel_hdmi_to_dev(intel_hdmi
);
49 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
50 uint32_t enabled_bits
;
52 enabled_bits
= HAS_DDI(dev
) ? DDI_BUF_CTL_ENABLE
: SDVO_ENABLE
;
54 WARN(I915_READ(intel_hdmi
->hdmi_reg
) & enabled_bits
,
55 "HDMI port enabled, expecting disabled\n");
58 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
)
60 struct intel_digital_port
*intel_dig_port
=
61 container_of(encoder
, struct intel_digital_port
, base
.base
);
62 return &intel_dig_port
->hdmi
;
65 static struct intel_hdmi
*intel_attached_hdmi(struct drm_connector
*connector
)
67 return enc_to_intel_hdmi(&intel_attached_encoder(connector
)->base
);
70 static u32
g4x_infoframe_index(enum hdmi_infoframe_type type
)
73 case HDMI_INFOFRAME_TYPE_AVI
:
74 return VIDEO_DIP_SELECT_AVI
;
75 case HDMI_INFOFRAME_TYPE_SPD
:
76 return VIDEO_DIP_SELECT_SPD
;
77 case HDMI_INFOFRAME_TYPE_VENDOR
:
78 return VIDEO_DIP_SELECT_VENDOR
;
80 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type
);
85 static u32
g4x_infoframe_enable(enum hdmi_infoframe_type type
)
88 case HDMI_INFOFRAME_TYPE_AVI
:
89 return VIDEO_DIP_ENABLE_AVI
;
90 case HDMI_INFOFRAME_TYPE_SPD
:
91 return VIDEO_DIP_ENABLE_SPD
;
92 case HDMI_INFOFRAME_TYPE_VENDOR
:
93 return VIDEO_DIP_ENABLE_VENDOR
;
95 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type
);
100 static u32
hsw_infoframe_enable(enum hdmi_infoframe_type type
)
103 case HDMI_INFOFRAME_TYPE_AVI
:
104 return VIDEO_DIP_ENABLE_AVI_HSW
;
105 case HDMI_INFOFRAME_TYPE_SPD
:
106 return VIDEO_DIP_ENABLE_SPD_HSW
;
107 case HDMI_INFOFRAME_TYPE_VENDOR
:
108 return VIDEO_DIP_ENABLE_VS_HSW
;
110 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type
);
115 static u32
hsw_infoframe_data_reg(enum hdmi_infoframe_type type
,
116 enum transcoder cpu_transcoder
,
117 struct drm_i915_private
*dev_priv
)
120 case HDMI_INFOFRAME_TYPE_AVI
:
121 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder
);
122 case HDMI_INFOFRAME_TYPE_SPD
:
123 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder
);
124 case HDMI_INFOFRAME_TYPE_VENDOR
:
125 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder
);
127 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type
);
132 static void g4x_write_infoframe(struct drm_encoder
*encoder
,
133 enum hdmi_infoframe_type type
,
134 const void *frame
, ssize_t len
)
136 const uint32_t *data
= frame
;
137 struct drm_device
*dev
= encoder
->dev
;
138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
139 u32 val
= I915_READ(VIDEO_DIP_CTL
);
142 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
144 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
145 val
|= g4x_infoframe_index(type
);
147 val
&= ~g4x_infoframe_enable(type
);
149 I915_WRITE(VIDEO_DIP_CTL
, val
);
152 for (i
= 0; i
< len
; i
+= 4) {
153 I915_WRITE(VIDEO_DIP_DATA
, *data
);
156 /* Write every possible data byte to force correct ECC calculation. */
157 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
158 I915_WRITE(VIDEO_DIP_DATA
, 0);
161 val
|= g4x_infoframe_enable(type
);
162 val
&= ~VIDEO_DIP_FREQ_MASK
;
163 val
|= VIDEO_DIP_FREQ_VSYNC
;
165 I915_WRITE(VIDEO_DIP_CTL
, val
);
166 POSTING_READ(VIDEO_DIP_CTL
);
169 static void ibx_write_infoframe(struct drm_encoder
*encoder
,
170 enum hdmi_infoframe_type type
,
171 const void *frame
, ssize_t len
)
173 const uint32_t *data
= frame
;
174 struct drm_device
*dev
= encoder
->dev
;
175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
176 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
177 int i
, reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
178 u32 val
= I915_READ(reg
);
180 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
182 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
183 val
|= g4x_infoframe_index(type
);
185 val
&= ~g4x_infoframe_enable(type
);
187 I915_WRITE(reg
, val
);
190 for (i
= 0; i
< len
; i
+= 4) {
191 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
194 /* Write every possible data byte to force correct ECC calculation. */
195 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
196 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
199 val
|= g4x_infoframe_enable(type
);
200 val
&= ~VIDEO_DIP_FREQ_MASK
;
201 val
|= VIDEO_DIP_FREQ_VSYNC
;
203 I915_WRITE(reg
, val
);
207 static void cpt_write_infoframe(struct drm_encoder
*encoder
,
208 enum hdmi_infoframe_type type
,
209 const void *frame
, ssize_t len
)
211 const uint32_t *data
= frame
;
212 struct drm_device
*dev
= encoder
->dev
;
213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
214 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
215 int i
, reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
216 u32 val
= I915_READ(reg
);
218 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
220 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
221 val
|= g4x_infoframe_index(type
);
223 /* The DIP control register spec says that we need to update the AVI
224 * infoframe without clearing its enable bit */
225 if (type
!= HDMI_INFOFRAME_TYPE_AVI
)
226 val
&= ~g4x_infoframe_enable(type
);
228 I915_WRITE(reg
, val
);
231 for (i
= 0; i
< len
; i
+= 4) {
232 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
235 /* Write every possible data byte to force correct ECC calculation. */
236 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
237 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
240 val
|= g4x_infoframe_enable(type
);
241 val
&= ~VIDEO_DIP_FREQ_MASK
;
242 val
|= VIDEO_DIP_FREQ_VSYNC
;
244 I915_WRITE(reg
, val
);
248 static void vlv_write_infoframe(struct drm_encoder
*encoder
,
249 enum hdmi_infoframe_type type
,
250 const void *frame
, ssize_t len
)
252 const uint32_t *data
= frame
;
253 struct drm_device
*dev
= encoder
->dev
;
254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
255 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
256 int i
, reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
257 u32 val
= I915_READ(reg
);
259 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
261 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
262 val
|= g4x_infoframe_index(type
);
264 val
&= ~g4x_infoframe_enable(type
);
266 I915_WRITE(reg
, val
);
269 for (i
= 0; i
< len
; i
+= 4) {
270 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
273 /* Write every possible data byte to force correct ECC calculation. */
274 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
275 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
278 val
|= g4x_infoframe_enable(type
);
279 val
&= ~VIDEO_DIP_FREQ_MASK
;
280 val
|= VIDEO_DIP_FREQ_VSYNC
;
282 I915_WRITE(reg
, val
);
286 static void hsw_write_infoframe(struct drm_encoder
*encoder
,
287 enum hdmi_infoframe_type type
,
288 const void *frame
, ssize_t len
)
290 const uint32_t *data
= frame
;
291 struct drm_device
*dev
= encoder
->dev
;
292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
293 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
294 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(intel_crtc
->config
.cpu_transcoder
);
297 u32 val
= I915_READ(ctl_reg
);
299 data_reg
= hsw_infoframe_data_reg(type
,
300 intel_crtc
->config
.cpu_transcoder
,
305 val
&= ~hsw_infoframe_enable(type
);
306 I915_WRITE(ctl_reg
, val
);
309 for (i
= 0; i
< len
; i
+= 4) {
310 I915_WRITE(data_reg
+ i
, *data
);
313 /* Write every possible data byte to force correct ECC calculation. */
314 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
315 I915_WRITE(data_reg
+ i
, 0);
318 val
|= hsw_infoframe_enable(type
);
319 I915_WRITE(ctl_reg
, val
);
320 POSTING_READ(ctl_reg
);
324 * The data we write to the DIP data buffer registers is 1 byte bigger than the
325 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
326 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
327 * used for both technologies.
329 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
330 * DW1: DB3 | DB2 | DB1 | DB0
331 * DW2: DB7 | DB6 | DB5 | DB4
334 * (HB is Header Byte, DB is Data Byte)
336 * The hdmi pack() functions don't know about that hardware specific hole so we
337 * trick them by giving an offset into the buffer and moving back the header
340 static void intel_write_infoframe(struct drm_encoder
*encoder
,
341 union hdmi_infoframe
*frame
)
343 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
344 uint8_t buffer
[VIDEO_DIP_DATA_SIZE
];
347 /* see comment above for the reason for this offset */
348 len
= hdmi_infoframe_pack(frame
, buffer
+ 1, sizeof(buffer
) - 1);
352 /* Insert the 'hole' (see big comment above) at position 3 */
353 buffer
[0] = buffer
[1];
354 buffer
[1] = buffer
[2];
355 buffer
[2] = buffer
[3];
359 intel_hdmi
->write_infoframe(encoder
, frame
->any
.type
, buffer
, len
);
362 static void intel_hdmi_set_avi_infoframe(struct drm_encoder
*encoder
,
363 struct drm_display_mode
*adjusted_mode
)
365 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
366 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
367 union hdmi_infoframe frame
;
370 ret
= drm_hdmi_avi_infoframe_from_display_mode(&frame
.avi
,
373 DRM_ERROR("couldn't fill AVI infoframe\n");
377 if (intel_hdmi
->rgb_quant_range_selectable
) {
378 if (intel_crtc
->config
.limited_color_range
)
379 frame
.avi
.quantization_range
=
380 HDMI_QUANTIZATION_RANGE_LIMITED
;
382 frame
.avi
.quantization_range
=
383 HDMI_QUANTIZATION_RANGE_FULL
;
386 intel_write_infoframe(encoder
, &frame
);
389 static void intel_hdmi_set_spd_infoframe(struct drm_encoder
*encoder
)
391 union hdmi_infoframe frame
;
394 ret
= hdmi_spd_infoframe_init(&frame
.spd
, "Intel", "Integrated gfx");
396 DRM_ERROR("couldn't fill SPD infoframe\n");
400 frame
.spd
.sdi
= HDMI_SPD_SDI_PC
;
402 intel_write_infoframe(encoder
, &frame
);
406 intel_hdmi_set_hdmi_infoframe(struct drm_encoder
*encoder
,
407 struct drm_display_mode
*adjusted_mode
)
409 union hdmi_infoframe frame
;
412 ret
= drm_hdmi_vendor_infoframe_from_display_mode(&frame
.vendor
.hdmi
,
417 intel_write_infoframe(encoder
, &frame
);
420 static void g4x_set_infoframes(struct drm_encoder
*encoder
,
421 struct drm_display_mode
*adjusted_mode
)
423 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
424 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
425 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
426 u32 reg
= VIDEO_DIP_CTL
;
427 u32 val
= I915_READ(reg
);
428 u32 port
= VIDEO_DIP_PORT(intel_dig_port
->port
);
430 assert_hdmi_port_disabled(intel_hdmi
);
432 /* If the registers were not initialized yet, they might be zeroes,
433 * which means we're selecting the AVI DIP and we're setting its
434 * frequency to once. This seems to really confuse the HW and make
435 * things stop working (the register spec says the AVI always needs to
436 * be sent every VSync). So here we avoid writing to the register more
437 * than we need and also explicitly select the AVI DIP and explicitly
438 * set its frequency to every VSync. Avoiding to write it twice seems to
439 * be enough to solve the problem, but being defensive shouldn't hurt us
441 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
443 if (!intel_hdmi
->has_hdmi_sink
) {
444 if (!(val
& VIDEO_DIP_ENABLE
))
446 val
&= ~VIDEO_DIP_ENABLE
;
447 I915_WRITE(reg
, val
);
452 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
453 if (val
& VIDEO_DIP_ENABLE
) {
454 val
&= ~VIDEO_DIP_ENABLE
;
455 I915_WRITE(reg
, val
);
458 val
&= ~VIDEO_DIP_PORT_MASK
;
462 val
|= VIDEO_DIP_ENABLE
;
463 val
&= ~VIDEO_DIP_ENABLE_VENDOR
;
465 I915_WRITE(reg
, val
);
468 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
469 intel_hdmi_set_spd_infoframe(encoder
);
470 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
473 static void ibx_set_infoframes(struct drm_encoder
*encoder
,
474 struct drm_display_mode
*adjusted_mode
)
476 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
477 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
478 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
479 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
480 u32 reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
481 u32 val
= I915_READ(reg
);
482 u32 port
= VIDEO_DIP_PORT(intel_dig_port
->port
);
484 assert_hdmi_port_disabled(intel_hdmi
);
486 /* See the big comment in g4x_set_infoframes() */
487 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
489 if (!intel_hdmi
->has_hdmi_sink
) {
490 if (!(val
& VIDEO_DIP_ENABLE
))
492 val
&= ~VIDEO_DIP_ENABLE
;
493 I915_WRITE(reg
, val
);
498 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
499 if (val
& VIDEO_DIP_ENABLE
) {
500 val
&= ~VIDEO_DIP_ENABLE
;
501 I915_WRITE(reg
, val
);
504 val
&= ~VIDEO_DIP_PORT_MASK
;
508 val
|= VIDEO_DIP_ENABLE
;
509 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
510 VIDEO_DIP_ENABLE_GCP
);
512 I915_WRITE(reg
, val
);
515 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
516 intel_hdmi_set_spd_infoframe(encoder
);
517 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
520 static void cpt_set_infoframes(struct drm_encoder
*encoder
,
521 struct drm_display_mode
*adjusted_mode
)
523 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
524 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
525 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
526 u32 reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
527 u32 val
= I915_READ(reg
);
529 assert_hdmi_port_disabled(intel_hdmi
);
531 /* See the big comment in g4x_set_infoframes() */
532 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
534 if (!intel_hdmi
->has_hdmi_sink
) {
535 if (!(val
& VIDEO_DIP_ENABLE
))
537 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
);
538 I915_WRITE(reg
, val
);
543 /* Set both together, unset both together: see the spec. */
544 val
|= VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
;
545 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
546 VIDEO_DIP_ENABLE_GCP
);
548 I915_WRITE(reg
, val
);
551 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
552 intel_hdmi_set_spd_infoframe(encoder
);
553 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
556 static void vlv_set_infoframes(struct drm_encoder
*encoder
,
557 struct drm_display_mode
*adjusted_mode
)
559 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
560 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
561 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
562 u32 reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
563 u32 val
= I915_READ(reg
);
565 assert_hdmi_port_disabled(intel_hdmi
);
567 /* See the big comment in g4x_set_infoframes() */
568 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
570 if (!intel_hdmi
->has_hdmi_sink
) {
571 if (!(val
& VIDEO_DIP_ENABLE
))
573 val
&= ~VIDEO_DIP_ENABLE
;
574 I915_WRITE(reg
, val
);
579 val
|= VIDEO_DIP_ENABLE
;
580 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
581 VIDEO_DIP_ENABLE_GCP
);
583 I915_WRITE(reg
, val
);
586 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
587 intel_hdmi_set_spd_infoframe(encoder
);
588 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
591 static void hsw_set_infoframes(struct drm_encoder
*encoder
,
592 struct drm_display_mode
*adjusted_mode
)
594 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
595 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
596 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
597 u32 reg
= HSW_TVIDEO_DIP_CTL(intel_crtc
->config
.cpu_transcoder
);
598 u32 val
= I915_READ(reg
);
600 assert_hdmi_port_disabled(intel_hdmi
);
602 if (!intel_hdmi
->has_hdmi_sink
) {
608 val
&= ~(VIDEO_DIP_ENABLE_VSC_HSW
| VIDEO_DIP_ENABLE_GCP_HSW
|
609 VIDEO_DIP_ENABLE_VS_HSW
| VIDEO_DIP_ENABLE_GMP_HSW
);
611 I915_WRITE(reg
, val
);
614 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
615 intel_hdmi_set_spd_infoframe(encoder
);
616 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
619 static void intel_hdmi_mode_set(struct intel_encoder
*encoder
)
621 struct drm_device
*dev
= encoder
->base
.dev
;
622 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
623 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
624 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
625 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
628 hdmi_val
= SDVO_ENCODING_HDMI
;
629 if (!HAS_PCH_SPLIT(dev
))
630 hdmi_val
|= intel_hdmi
->color_range
;
631 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
632 hdmi_val
|= SDVO_VSYNC_ACTIVE_HIGH
;
633 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
634 hdmi_val
|= SDVO_HSYNC_ACTIVE_HIGH
;
636 if (crtc
->config
.pipe_bpp
> 24)
637 hdmi_val
|= HDMI_COLOR_FORMAT_12bpc
;
639 hdmi_val
|= SDVO_COLOR_FORMAT_8bpc
;
641 /* Required on CPT */
642 if (intel_hdmi
->has_hdmi_sink
&& HAS_PCH_CPT(dev
))
643 hdmi_val
|= HDMI_MODE_SELECT_HDMI
;
645 if (intel_hdmi
->has_audio
) {
646 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
647 pipe_name(crtc
->pipe
));
648 hdmi_val
|= SDVO_AUDIO_ENABLE
;
649 hdmi_val
|= HDMI_MODE_SELECT_HDMI
;
650 intel_write_eld(&encoder
->base
, adjusted_mode
);
653 if (HAS_PCH_CPT(dev
))
654 hdmi_val
|= SDVO_PIPE_SEL_CPT(crtc
->pipe
);
656 hdmi_val
|= SDVO_PIPE_SEL(crtc
->pipe
);
658 I915_WRITE(intel_hdmi
->hdmi_reg
, hdmi_val
);
659 POSTING_READ(intel_hdmi
->hdmi_reg
);
661 intel_hdmi
->set_infoframes(&encoder
->base
, adjusted_mode
);
664 static bool intel_hdmi_get_hw_state(struct intel_encoder
*encoder
,
667 struct drm_device
*dev
= encoder
->base
.dev
;
668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
669 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
670 enum intel_display_power_domain power_domain
;
673 power_domain
= intel_display_port_power_domain(encoder
);
674 if (!intel_display_power_enabled(dev_priv
, power_domain
))
677 tmp
= I915_READ(intel_hdmi
->hdmi_reg
);
679 if (!(tmp
& SDVO_ENABLE
))
682 if (HAS_PCH_CPT(dev
))
683 *pipe
= PORT_TO_PIPE_CPT(tmp
);
685 *pipe
= PORT_TO_PIPE(tmp
);
690 static void intel_hdmi_get_config(struct intel_encoder
*encoder
,
691 struct intel_crtc_config
*pipe_config
)
693 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
694 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
698 tmp
= I915_READ(intel_hdmi
->hdmi_reg
);
700 if (tmp
& SDVO_HSYNC_ACTIVE_HIGH
)
701 flags
|= DRM_MODE_FLAG_PHSYNC
;
703 flags
|= DRM_MODE_FLAG_NHSYNC
;
705 if (tmp
& SDVO_VSYNC_ACTIVE_HIGH
)
706 flags
|= DRM_MODE_FLAG_PVSYNC
;
708 flags
|= DRM_MODE_FLAG_NVSYNC
;
710 pipe_config
->adjusted_mode
.flags
|= flags
;
712 if ((tmp
& SDVO_COLOR_FORMAT_MASK
) == HDMI_COLOR_FORMAT_12bpc
)
713 dotclock
= pipe_config
->port_clock
* 2 / 3;
715 dotclock
= pipe_config
->port_clock
;
717 if (HAS_PCH_SPLIT(dev_priv
->dev
))
718 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
720 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
723 static void intel_enable_hdmi(struct intel_encoder
*encoder
)
725 struct drm_device
*dev
= encoder
->base
.dev
;
726 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
727 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
728 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
730 u32 enable_bits
= SDVO_ENABLE
;
732 if (intel_hdmi
->has_audio
)
733 enable_bits
|= SDVO_AUDIO_ENABLE
;
735 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
737 /* HW workaround for IBX, we need to move the port to transcoder A
738 * before disabling it, so restore the transcoder select bit here. */
739 if (HAS_PCH_IBX(dev
))
740 enable_bits
|= SDVO_PIPE_SEL(intel_crtc
->pipe
);
742 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
743 * we do this anyway which shows more stable in testing.
745 if (HAS_PCH_SPLIT(dev
)) {
746 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
& ~SDVO_ENABLE
);
747 POSTING_READ(intel_hdmi
->hdmi_reg
);
752 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
753 POSTING_READ(intel_hdmi
->hdmi_reg
);
755 /* HW workaround, need to write this twice for issue that may result
756 * in first write getting masked.
758 if (HAS_PCH_SPLIT(dev
)) {
759 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
760 POSTING_READ(intel_hdmi
->hdmi_reg
);
764 static void vlv_enable_hdmi(struct intel_encoder
*encoder
)
768 static void intel_disable_hdmi(struct intel_encoder
*encoder
)
770 struct drm_device
*dev
= encoder
->base
.dev
;
771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
772 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
774 u32 enable_bits
= SDVO_ENABLE
| SDVO_AUDIO_ENABLE
;
776 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
778 /* HW workaround for IBX, we need to move the port to transcoder A
779 * before disabling it. */
780 if (HAS_PCH_IBX(dev
)) {
781 struct drm_crtc
*crtc
= encoder
->base
.crtc
;
782 int pipe
= crtc
? to_intel_crtc(crtc
)->pipe
: -1;
784 if (temp
& SDVO_PIPE_B_SELECT
) {
785 temp
&= ~SDVO_PIPE_B_SELECT
;
786 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
787 POSTING_READ(intel_hdmi
->hdmi_reg
);
789 /* Again we need to write this twice. */
790 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
791 POSTING_READ(intel_hdmi
->hdmi_reg
);
793 /* Transcoder selection bits only update
794 * effectively on vblank. */
796 intel_wait_for_vblank(dev
, pipe
);
802 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
803 * we do this anyway which shows more stable in testing.
805 if (HAS_PCH_SPLIT(dev
)) {
806 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
& ~SDVO_ENABLE
);
807 POSTING_READ(intel_hdmi
->hdmi_reg
);
810 temp
&= ~enable_bits
;
812 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
813 POSTING_READ(intel_hdmi
->hdmi_reg
);
815 /* HW workaround, need to write this twice for issue that may result
816 * in first write getting masked.
818 if (HAS_PCH_SPLIT(dev
)) {
819 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
820 POSTING_READ(intel_hdmi
->hdmi_reg
);
824 static int hdmi_portclock_limit(struct intel_hdmi
*hdmi
)
826 struct drm_device
*dev
= intel_hdmi_to_dev(hdmi
);
828 if (!hdmi
->has_hdmi_sink
|| IS_G4X(dev
))
830 else if (IS_HASWELL(dev
) || INTEL_INFO(dev
)->gen
>= 8)
836 static enum drm_mode_status
837 intel_hdmi_mode_valid(struct drm_connector
*connector
,
838 struct drm_display_mode
*mode
)
840 if (mode
->clock
> hdmi_portclock_limit(intel_attached_hdmi(connector
)))
841 return MODE_CLOCK_HIGH
;
842 if (mode
->clock
< 20000)
843 return MODE_CLOCK_LOW
;
845 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
846 return MODE_NO_DBLESCAN
;
851 static bool hdmi_12bpc_possible(struct intel_crtc
*crtc
)
853 struct drm_device
*dev
= crtc
->base
.dev
;
854 struct intel_encoder
*encoder
;
855 int count
= 0, count_hdmi
= 0;
857 if (!HAS_PCH_SPLIT(dev
))
860 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
861 if (encoder
->new_crtc
!= crtc
)
864 count_hdmi
+= encoder
->type
== INTEL_OUTPUT_HDMI
;
869 * HDMI 12bpc affects the clocks, so it's only possible
870 * when not cloning with other encoder types.
872 return count_hdmi
> 0 && count_hdmi
== count
;
875 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
876 struct intel_crtc_config
*pipe_config
)
878 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
879 struct drm_device
*dev
= encoder
->base
.dev
;
880 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
881 int clock_12bpc
= pipe_config
->adjusted_mode
.crtc_clock
* 3 / 2;
882 int portclock_limit
= hdmi_portclock_limit(intel_hdmi
);
885 if (intel_hdmi
->color_range_auto
) {
886 /* See CEA-861-E - 5.1 Default Encoding Parameters */
887 if (intel_hdmi
->has_hdmi_sink
&&
888 drm_match_cea_mode(adjusted_mode
) > 1)
889 intel_hdmi
->color_range
= HDMI_COLOR_RANGE_16_235
;
891 intel_hdmi
->color_range
= 0;
894 if (intel_hdmi
->color_range
)
895 pipe_config
->limited_color_range
= true;
897 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
))
898 pipe_config
->has_pch_encoder
= true;
901 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
902 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
903 * outputs. We also need to check that the higher clock still fits
906 if (pipe_config
->pipe_bpp
> 8*3 && intel_hdmi
->has_hdmi_sink
&&
907 clock_12bpc
<= portclock_limit
&&
908 hdmi_12bpc_possible(encoder
->new_crtc
)) {
909 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
912 /* Need to adjust the port link by 1.5x for 12bpc. */
913 pipe_config
->port_clock
= clock_12bpc
;
915 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
919 if (!pipe_config
->bw_constrained
) {
920 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp
);
921 pipe_config
->pipe_bpp
= desired_bpp
;
924 if (adjusted_mode
->crtc_clock
> portclock_limit
) {
925 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
932 static enum drm_connector_status
933 intel_hdmi_detect(struct drm_connector
*connector
, bool force
)
935 struct drm_device
*dev
= connector
->dev
;
936 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
937 struct intel_digital_port
*intel_dig_port
=
938 hdmi_to_dig_port(intel_hdmi
);
939 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
940 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
942 enum intel_display_power_domain power_domain
;
943 enum drm_connector_status status
= connector_status_disconnected
;
945 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
946 connector
->base
.id
, drm_get_connector_name(connector
));
948 power_domain
= intel_display_port_power_domain(intel_encoder
);
949 intel_display_power_get(dev_priv
, power_domain
);
951 intel_hdmi
->has_hdmi_sink
= false;
952 intel_hdmi
->has_audio
= false;
953 intel_hdmi
->rgb_quant_range_selectable
= false;
954 edid
= drm_get_edid(connector
,
955 intel_gmbus_get_adapter(dev_priv
,
956 intel_hdmi
->ddc_bus
));
959 if (edid
->input
& DRM_EDID_INPUT_DIGITAL
) {
960 status
= connector_status_connected
;
961 if (intel_hdmi
->force_audio
!= HDMI_AUDIO_OFF_DVI
)
962 intel_hdmi
->has_hdmi_sink
=
963 drm_detect_hdmi_monitor(edid
);
964 intel_hdmi
->has_audio
= drm_detect_monitor_audio(edid
);
965 intel_hdmi
->rgb_quant_range_selectable
=
966 drm_rgb_quant_range_selectable(edid
);
971 if (status
== connector_status_connected
) {
972 if (intel_hdmi
->force_audio
!= HDMI_AUDIO_AUTO
)
973 intel_hdmi
->has_audio
=
974 (intel_hdmi
->force_audio
== HDMI_AUDIO_ON
);
975 intel_encoder
->type
= INTEL_OUTPUT_HDMI
;
978 intel_display_power_put(dev_priv
, power_domain
);
983 static int intel_hdmi_get_modes(struct drm_connector
*connector
)
985 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
986 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
987 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
988 enum intel_display_power_domain power_domain
;
991 /* We should parse the EDID data and find out if it's an HDMI sink so
992 * we can send audio to it.
995 power_domain
= intel_display_port_power_domain(intel_encoder
);
996 intel_display_power_get(dev_priv
, power_domain
);
998 ret
= intel_ddc_get_modes(connector
,
999 intel_gmbus_get_adapter(dev_priv
,
1000 intel_hdmi
->ddc_bus
));
1002 intel_display_power_put(dev_priv
, power_domain
);
1008 intel_hdmi_detect_audio(struct drm_connector
*connector
)
1010 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
1011 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
1012 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
1013 enum intel_display_power_domain power_domain
;
1015 bool has_audio
= false;
1017 power_domain
= intel_display_port_power_domain(intel_encoder
);
1018 intel_display_power_get(dev_priv
, power_domain
);
1020 edid
= drm_get_edid(connector
,
1021 intel_gmbus_get_adapter(dev_priv
,
1022 intel_hdmi
->ddc_bus
));
1024 if (edid
->input
& DRM_EDID_INPUT_DIGITAL
)
1025 has_audio
= drm_detect_monitor_audio(edid
);
1029 intel_display_power_put(dev_priv
, power_domain
);
1035 intel_hdmi_set_property(struct drm_connector
*connector
,
1036 struct drm_property
*property
,
1039 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
1040 struct intel_digital_port
*intel_dig_port
=
1041 hdmi_to_dig_port(intel_hdmi
);
1042 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
1045 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
1049 if (property
== dev_priv
->force_audio_property
) {
1050 enum hdmi_force_audio i
= val
;
1053 if (i
== intel_hdmi
->force_audio
)
1056 intel_hdmi
->force_audio
= i
;
1058 if (i
== HDMI_AUDIO_AUTO
)
1059 has_audio
= intel_hdmi_detect_audio(connector
);
1061 has_audio
= (i
== HDMI_AUDIO_ON
);
1063 if (i
== HDMI_AUDIO_OFF_DVI
)
1064 intel_hdmi
->has_hdmi_sink
= 0;
1066 intel_hdmi
->has_audio
= has_audio
;
1070 if (property
== dev_priv
->broadcast_rgb_property
) {
1071 bool old_auto
= intel_hdmi
->color_range_auto
;
1072 uint32_t old_range
= intel_hdmi
->color_range
;
1075 case INTEL_BROADCAST_RGB_AUTO
:
1076 intel_hdmi
->color_range_auto
= true;
1078 case INTEL_BROADCAST_RGB_FULL
:
1079 intel_hdmi
->color_range_auto
= false;
1080 intel_hdmi
->color_range
= 0;
1082 case INTEL_BROADCAST_RGB_LIMITED
:
1083 intel_hdmi
->color_range_auto
= false;
1084 intel_hdmi
->color_range
= HDMI_COLOR_RANGE_16_235
;
1090 if (old_auto
== intel_hdmi
->color_range_auto
&&
1091 old_range
== intel_hdmi
->color_range
)
1100 if (intel_dig_port
->base
.base
.crtc
)
1101 intel_crtc_restore_mode(intel_dig_port
->base
.base
.crtc
);
1106 static void vlv_hdmi_pre_enable(struct intel_encoder
*encoder
)
1108 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1109 struct drm_device
*dev
= encoder
->base
.dev
;
1110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1111 struct intel_crtc
*intel_crtc
=
1112 to_intel_crtc(encoder
->base
.crtc
);
1113 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1114 int pipe
= intel_crtc
->pipe
;
1117 if (!IS_VALLEYVIEW(dev
))
1120 /* Enable clock channels for this port */
1121 mutex_lock(&dev_priv
->dpio_lock
);
1122 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
1129 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
1132 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0);
1133 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), 0x2b245f5f);
1134 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
), 0x5578b83a);
1135 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0c782040);
1136 vlv_dpio_write(dev_priv
, pipe
, VLV_TX3_DW4(port
), 0x2b247878);
1137 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
1138 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), 0x00002000);
1139 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), DPIO_TX_OCALINIT_EN
);
1141 /* Program lane clock */
1142 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
1143 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
1144 mutex_unlock(&dev_priv
->dpio_lock
);
1146 intel_enable_hdmi(encoder
);
1148 vlv_wait_port_ready(dev_priv
, dport
);
1151 static void vlv_hdmi_pre_pll_enable(struct intel_encoder
*encoder
)
1153 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1154 struct drm_device
*dev
= encoder
->base
.dev
;
1155 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1156 struct intel_crtc
*intel_crtc
=
1157 to_intel_crtc(encoder
->base
.crtc
);
1158 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1159 int pipe
= intel_crtc
->pipe
;
1161 if (!IS_VALLEYVIEW(dev
))
1164 /* Program Tx lane resets to default */
1165 mutex_lock(&dev_priv
->dpio_lock
);
1166 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
1167 DPIO_PCS_TX_LANE2_RESET
|
1168 DPIO_PCS_TX_LANE1_RESET
);
1169 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
1170 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
1171 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
1172 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
1173 DPIO_PCS_CLK_SOFT_RESET
);
1175 /* Fix up inter-pair skew failure */
1176 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
1177 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
1178 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
1180 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), 0x00002000);
1181 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), DPIO_TX_OCALINIT_EN
);
1182 mutex_unlock(&dev_priv
->dpio_lock
);
1185 static void vlv_hdmi_post_disable(struct intel_encoder
*encoder
)
1187 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1188 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1189 struct intel_crtc
*intel_crtc
=
1190 to_intel_crtc(encoder
->base
.crtc
);
1191 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1192 int pipe
= intel_crtc
->pipe
;
1194 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1195 mutex_lock(&dev_priv
->dpio_lock
);
1196 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
), 0x00000000);
1197 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
), 0x00e00060);
1198 mutex_unlock(&dev_priv
->dpio_lock
);
1201 static void intel_hdmi_destroy(struct drm_connector
*connector
)
1203 drm_connector_cleanup(connector
);
1207 static const struct drm_connector_funcs intel_hdmi_connector_funcs
= {
1208 .dpms
= intel_connector_dpms
,
1209 .detect
= intel_hdmi_detect
,
1210 .fill_modes
= drm_helper_probe_single_connector_modes
,
1211 .set_property
= intel_hdmi_set_property
,
1212 .destroy
= intel_hdmi_destroy
,
1215 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs
= {
1216 .get_modes
= intel_hdmi_get_modes
,
1217 .mode_valid
= intel_hdmi_mode_valid
,
1218 .best_encoder
= intel_best_encoder
,
1221 static const struct drm_encoder_funcs intel_hdmi_enc_funcs
= {
1222 .destroy
= intel_encoder_destroy
,
1226 intel_hdmi_add_properties(struct intel_hdmi
*intel_hdmi
, struct drm_connector
*connector
)
1228 intel_attach_force_audio_property(connector
);
1229 intel_attach_broadcast_rgb_property(connector
);
1230 intel_hdmi
->color_range_auto
= true;
1233 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
1234 struct intel_connector
*intel_connector
)
1236 struct drm_connector
*connector
= &intel_connector
->base
;
1237 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
1238 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1239 struct drm_device
*dev
= intel_encoder
->base
.dev
;
1240 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1241 enum port port
= intel_dig_port
->port
;
1243 drm_connector_init(dev
, connector
, &intel_hdmi_connector_funcs
,
1244 DRM_MODE_CONNECTOR_HDMIA
);
1245 drm_connector_helper_add(connector
, &intel_hdmi_connector_helper_funcs
);
1247 connector
->interlace_allowed
= 1;
1248 connector
->doublescan_allowed
= 0;
1249 connector
->stereo_allowed
= 1;
1253 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPB
;
1254 intel_encoder
->hpd_pin
= HPD_PORT_B
;
1257 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPC
;
1258 intel_encoder
->hpd_pin
= HPD_PORT_C
;
1261 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPD
;
1262 intel_encoder
->hpd_pin
= HPD_PORT_D
;
1265 intel_encoder
->hpd_pin
= HPD_PORT_A
;
1266 /* Internal port only for eDP. */
1271 if (IS_VALLEYVIEW(dev
)) {
1272 intel_hdmi
->write_infoframe
= vlv_write_infoframe
;
1273 intel_hdmi
->set_infoframes
= vlv_set_infoframes
;
1274 } else if (!HAS_PCH_SPLIT(dev
)) {
1275 intel_hdmi
->write_infoframe
= g4x_write_infoframe
;
1276 intel_hdmi
->set_infoframes
= g4x_set_infoframes
;
1277 } else if (HAS_DDI(dev
)) {
1278 intel_hdmi
->write_infoframe
= hsw_write_infoframe
;
1279 intel_hdmi
->set_infoframes
= hsw_set_infoframes
;
1280 } else if (HAS_PCH_IBX(dev
)) {
1281 intel_hdmi
->write_infoframe
= ibx_write_infoframe
;
1282 intel_hdmi
->set_infoframes
= ibx_set_infoframes
;
1284 intel_hdmi
->write_infoframe
= cpt_write_infoframe
;
1285 intel_hdmi
->set_infoframes
= cpt_set_infoframes
;
1289 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
1291 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
1292 intel_connector
->unregister
= intel_connector_unregister
;
1294 intel_hdmi_add_properties(intel_hdmi
, connector
);
1296 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
1297 drm_sysfs_connector_add(connector
);
1299 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1300 * 0xd. Failure to do so will result in spurious interrupts being
1301 * generated on the port when a cable is not attached.
1303 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
1304 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
1305 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
1309 void intel_hdmi_init(struct drm_device
*dev
, int hdmi_reg
, enum port port
)
1311 struct intel_digital_port
*intel_dig_port
;
1312 struct intel_encoder
*intel_encoder
;
1313 struct intel_connector
*intel_connector
;
1315 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
1316 if (!intel_dig_port
)
1319 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
1320 if (!intel_connector
) {
1321 kfree(intel_dig_port
);
1325 intel_encoder
= &intel_dig_port
->base
;
1327 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_hdmi_enc_funcs
,
1328 DRM_MODE_ENCODER_TMDS
);
1330 intel_encoder
->compute_config
= intel_hdmi_compute_config
;
1331 intel_encoder
->mode_set
= intel_hdmi_mode_set
;
1332 intel_encoder
->disable
= intel_disable_hdmi
;
1333 intel_encoder
->get_hw_state
= intel_hdmi_get_hw_state
;
1334 intel_encoder
->get_config
= intel_hdmi_get_config
;
1335 if (IS_VALLEYVIEW(dev
)) {
1336 intel_encoder
->pre_pll_enable
= vlv_hdmi_pre_pll_enable
;
1337 intel_encoder
->pre_enable
= vlv_hdmi_pre_enable
;
1338 intel_encoder
->enable
= vlv_enable_hdmi
;
1339 intel_encoder
->post_disable
= vlv_hdmi_post_disable
;
1341 intel_encoder
->enable
= intel_enable_hdmi
;
1344 intel_encoder
->type
= INTEL_OUTPUT_HDMI
;
1345 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
1346 intel_encoder
->cloneable
= 1 << INTEL_OUTPUT_ANALOG
;
1348 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1349 * to work on real hardware. And since g4x can send infoframes to
1350 * only one port anyway, nothing is lost by allowing it.
1353 intel_encoder
->cloneable
|= 1 << INTEL_OUTPUT_HDMI
;
1355 intel_dig_port
->port
= port
;
1356 intel_dig_port
->hdmi
.hdmi_reg
= hdmi_reg
;
1357 intel_dig_port
->dp
.output_reg
= 0;
1359 intel_hdmi_init_connector(intel_dig_port
, intel_connector
);