2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define GEN8_CTX_STATUS_COMPLETED_MASK \
160 (GEN8_CTX_STATUS_ACTIVE_IDLE | \
161 GEN8_CTX_STATUS_PREEMPTED | \
162 GEN8_CTX_STATUS_ELEMENT_SWITCH)
164 #define CTX_LRI_HEADER_0 0x01
165 #define CTX_CONTEXT_CONTROL 0x02
166 #define CTX_RING_HEAD 0x04
167 #define CTX_RING_TAIL 0x06
168 #define CTX_RING_BUFFER_START 0x08
169 #define CTX_RING_BUFFER_CONTROL 0x0a
170 #define CTX_BB_HEAD_U 0x0c
171 #define CTX_BB_HEAD_L 0x0e
172 #define CTX_BB_STATE 0x10
173 #define CTX_SECOND_BB_HEAD_U 0x12
174 #define CTX_SECOND_BB_HEAD_L 0x14
175 #define CTX_SECOND_BB_STATE 0x16
176 #define CTX_BB_PER_CTX_PTR 0x18
177 #define CTX_RCS_INDIRECT_CTX 0x1a
178 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
179 #define CTX_LRI_HEADER_1 0x21
180 #define CTX_CTX_TIMESTAMP 0x22
181 #define CTX_PDP3_UDW 0x24
182 #define CTX_PDP3_LDW 0x26
183 #define CTX_PDP2_UDW 0x28
184 #define CTX_PDP2_LDW 0x2a
185 #define CTX_PDP1_UDW 0x2c
186 #define CTX_PDP1_LDW 0x2e
187 #define CTX_PDP0_UDW 0x30
188 #define CTX_PDP0_LDW 0x32
189 #define CTX_LRI_HEADER_2 0x41
190 #define CTX_R_PWR_CLK_STATE 0x42
191 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
193 #define CTX_REG(reg_state, pos, reg, val) do { \
194 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
195 (reg_state)[(pos)+1] = (val); \
198 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
199 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
200 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
201 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
204 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
205 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
206 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
209 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
210 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
212 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
213 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
215 #define WA_TAIL_DWORDS 2
217 static int execlists_context_deferred_alloc(struct i915_gem_context
*ctx
,
218 struct intel_engine_cs
*engine
);
219 static void execlists_init_reg_state(u32
*reg_state
,
220 struct i915_gem_context
*ctx
,
221 struct intel_engine_cs
*engine
,
222 struct intel_ring
*ring
);
225 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
226 * @dev_priv: i915 device private
227 * @enable_execlists: value of i915.enable_execlists module parameter.
229 * Only certain platforms support Execlists (the prerequisites being
230 * support for Logical Ring Contexts and Aliasing PPGTT or better).
232 * Return: 1 if Execlists is supported and has to be enabled.
234 int intel_sanitize_enable_execlists(struct drm_i915_private
*dev_priv
, int enable_execlists
)
236 /* On platforms with execlist available, vGPU will only
237 * support execlist mode, no ring buffer mode.
239 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv
) && intel_vgpu_active(dev_priv
))
242 if (INTEL_GEN(dev_priv
) >= 9)
245 if (enable_execlists
== 0)
248 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv
) &&
249 USES_PPGTT(dev_priv
) &&
250 i915
.use_mmio_flip
>= 0)
257 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
258 * descriptor for a pinned context
259 * @ctx: Context to work on
260 * @engine: Engine the descriptor will be used with
262 * The context descriptor encodes various attributes of a context,
263 * including its GTT address and some flags. Because it's fairly
264 * expensive to calculate, we'll just do it once and cache the result,
265 * which remains valid until the context is unpinned.
267 * This is what a descriptor looks like, from LSB to MSB::
269 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
270 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
271 * bits 32-52: ctx ID, a globally unique tag
272 * bits 53-54: mbz, reserved for use by hardware
273 * bits 55-63: group ID, currently unused and set to 0
276 intel_lr_context_descriptor_update(struct i915_gem_context
*ctx
,
277 struct intel_engine_cs
*engine
)
279 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
282 BUILD_BUG_ON(MAX_CONTEXT_HW_ID
> (1<<GEN8_CTX_ID_WIDTH
));
284 desc
= ctx
->desc_template
; /* bits 0-11 */
285 desc
|= i915_ggtt_offset(ce
->state
) + LRC_PPHWSP_PN
* PAGE_SIZE
;
287 desc
|= (u64
)ctx
->hw_id
<< GEN8_CTX_ID_SHIFT
; /* bits 32-52 */
292 uint64_t intel_lr_context_descriptor(struct i915_gem_context
*ctx
,
293 struct intel_engine_cs
*engine
)
295 return ctx
->engine
[engine
->id
].lrc_desc
;
299 execlists_context_status_change(struct drm_i915_gem_request
*rq
,
300 unsigned long status
)
303 * Only used when GVT-g is enabled now. When GVT-g is disabled,
304 * The compiler should eliminate this function as dead-code.
306 if (!IS_ENABLED(CONFIG_DRM_I915_GVT
))
309 atomic_notifier_call_chain(&rq
->engine
->context_status_notifier
,
314 execlists_update_context_pdps(struct i915_hw_ppgtt
*ppgtt
, u32
*reg_state
)
316 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
317 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
318 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
319 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
322 static u64
execlists_update_context(struct drm_i915_gem_request
*rq
)
324 struct intel_context
*ce
= &rq
->ctx
->engine
[rq
->engine
->id
];
325 struct i915_hw_ppgtt
*ppgtt
=
326 rq
->ctx
->ppgtt
?: rq
->i915
->mm
.aliasing_ppgtt
;
327 u32
*reg_state
= ce
->lrc_reg_state
;
329 assert_ring_tail_valid(rq
->ring
, rq
->tail
);
330 reg_state
[CTX_RING_TAIL
+1] = rq
->tail
;
332 /* True 32b PPGTT with dynamic page allocation: update PDP
333 * registers and point the unallocated PDPs to scratch page.
334 * PML4 is allocated during ppgtt init, so this is not needed
337 if (ppgtt
&& !i915_vm_is_48bit(&ppgtt
->base
))
338 execlists_update_context_pdps(ppgtt
, reg_state
);
343 static void execlists_submit_ports(struct intel_engine_cs
*engine
)
345 struct drm_i915_private
*dev_priv
= engine
->i915
;
346 struct execlist_port
*port
= engine
->execlist_port
;
348 dev_priv
->regs
+ i915_mmio_reg_offset(RING_ELSP(engine
));
351 GEM_BUG_ON(port
[0].count
> 1);
353 execlists_context_status_change(port
[0].request
,
354 INTEL_CONTEXT_SCHEDULE_IN
);
355 desc
[0] = execlists_update_context(port
[0].request
);
356 GEM_DEBUG_EXEC(port
[0].context_id
= upper_32_bits(desc
[0]));
359 if (port
[1].request
) {
360 GEM_BUG_ON(port
[1].count
);
361 execlists_context_status_change(port
[1].request
,
362 INTEL_CONTEXT_SCHEDULE_IN
);
363 desc
[1] = execlists_update_context(port
[1].request
);
364 GEM_DEBUG_EXEC(port
[1].context_id
= upper_32_bits(desc
[1]));
369 GEM_BUG_ON(desc
[0] == desc
[1]);
371 /* You must always write both descriptors in the order below. */
372 writel(upper_32_bits(desc
[1]), elsp
);
373 writel(lower_32_bits(desc
[1]), elsp
);
375 writel(upper_32_bits(desc
[0]), elsp
);
376 /* The context is automatically loaded after the following */
377 writel(lower_32_bits(desc
[0]), elsp
);
380 static bool ctx_single_port_submission(const struct i915_gem_context
*ctx
)
382 return (IS_ENABLED(CONFIG_DRM_I915_GVT
) &&
383 i915_gem_context_force_single_submission(ctx
));
386 static bool can_merge_ctx(const struct i915_gem_context
*prev
,
387 const struct i915_gem_context
*next
)
392 if (ctx_single_port_submission(prev
))
398 static void execlists_dequeue(struct intel_engine_cs
*engine
)
400 struct drm_i915_gem_request
*last
;
401 struct execlist_port
*port
= engine
->execlist_port
;
405 /* After execlist_first is updated, the tasklet will be rescheduled.
407 * If we are currently running (inside the tasklet) and a third
408 * party queues a request and so updates engine->execlist_first under
409 * the spinlock (which we have elided), it will atomically set the
410 * TASKLET_SCHED flag causing the us to be re-executed and pick up
411 * the change in state (the update to TASKLET_SCHED incurs a memory
412 * barrier making this cross-cpu checking safe).
414 if (!READ_ONCE(engine
->execlist_first
))
417 last
= port
->request
;
419 /* WaIdleLiteRestore:bdw,skl
420 * Apply the wa NOOPs to prevent ring:HEAD == req:TAIL
421 * as we resubmit the request. See gen8_emit_breadcrumb()
422 * for where we prepare the padding after the end of the
425 last
->tail
= last
->wa_tail
;
427 GEM_BUG_ON(port
[1].request
);
429 /* Hardware submission is through 2 ports. Conceptually each port
430 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
431 * static for a context, and unique to each, so we only execute
432 * requests belonging to a single context from each ring. RING_HEAD
433 * is maintained by the CS in the context image, it marks the place
434 * where it got up to last time, and through RING_TAIL we tell the CS
435 * where we want to execute up to this time.
437 * In this list the requests are in order of execution. Consecutive
438 * requests from the same context are adjacent in the ringbuffer. We
439 * can combine these requests into a single RING_TAIL update:
441 * RING_HEAD...req1...req2
443 * since to execute req2 the CS must first execute req1.
445 * Our goal then is to point each port to the end of a consecutive
446 * sequence of requests as being the most optimal (fewest wake ups
447 * and context switches) submission.
450 spin_lock_irq(&engine
->timeline
->lock
);
451 rb
= engine
->execlist_first
;
453 struct drm_i915_gem_request
*cursor
=
454 rb_entry(rb
, typeof(*cursor
), priotree
.node
);
456 /* Can we combine this request with the current port? It has to
457 * be the same context/ringbuffer and not have any exceptions
458 * (e.g. GVT saying never to combine contexts).
460 * If we can combine the requests, we can execute both by
461 * updating the RING_TAIL to point to the end of the second
462 * request, and so we never need to tell the hardware about
465 if (last
&& !can_merge_ctx(cursor
->ctx
, last
->ctx
)) {
466 /* If we are on the second port and cannot combine
467 * this request with the last, then we are done.
469 if (port
!= engine
->execlist_port
)
472 /* If GVT overrides us we only ever submit port[0],
473 * leaving port[1] empty. Note that we also have
474 * to be careful that we don't queue the same
475 * context (even though a different request) to
478 if (ctx_single_port_submission(last
->ctx
) ||
479 ctx_single_port_submission(cursor
->ctx
))
482 GEM_BUG_ON(last
->ctx
== cursor
->ctx
);
484 i915_gem_request_assign(&port
->request
, last
);
489 rb_erase(&cursor
->priotree
.node
, &engine
->execlist_queue
);
490 RB_CLEAR_NODE(&cursor
->priotree
.node
);
491 cursor
->priotree
.priority
= INT_MAX
;
493 __i915_gem_request_submit(cursor
);
494 trace_i915_gem_request_in(cursor
, port
- engine
->execlist_port
);
499 i915_gem_request_assign(&port
->request
, last
);
500 engine
->execlist_first
= rb
;
502 spin_unlock_irq(&engine
->timeline
->lock
);
505 execlists_submit_ports(engine
);
508 static bool execlists_elsp_idle(struct intel_engine_cs
*engine
)
510 return !engine
->execlist_port
[0].request
;
513 static bool execlists_elsp_ready(const struct intel_engine_cs
*engine
)
515 const struct execlist_port
*port
= engine
->execlist_port
;
517 return port
[0].count
+ port
[1].count
< 2;
521 * Check the unread Context Status Buffers and manage the submission of new
522 * contexts to the ELSP accordingly.
524 static void intel_lrc_irq_handler(unsigned long data
)
526 struct intel_engine_cs
*engine
= (struct intel_engine_cs
*)data
;
527 struct execlist_port
*port
= engine
->execlist_port
;
528 struct drm_i915_private
*dev_priv
= engine
->i915
;
530 intel_uncore_forcewake_get(dev_priv
, engine
->fw_domains
);
532 /* Prefer doing test_and_clear_bit() as a two stage operation to avoid
533 * imposing the cost of a locked atomic transaction when submitting a
534 * new request (outside of the context-switch interrupt).
536 while (test_bit(ENGINE_IRQ_EXECLIST
, &engine
->irq_posted
)) {
537 u32 __iomem
*csb_mmio
=
538 dev_priv
->regs
+ i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine
));
540 dev_priv
->regs
+ i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine
, 0));
541 unsigned int head
, tail
;
543 /* The write will be ordered by the uncached read (itself
544 * a memory barrier), so we do not need another in the form
545 * of a locked instruction. The race between the interrupt
546 * handler and the split test/clear is harmless as we order
547 * our clear before the CSB read. If the interrupt arrived
548 * first between the test and the clear, we read the updated
549 * CSB and clear the bit. If the interrupt arrives as we read
550 * the CSB or later (i.e. after we had cleared the bit) the bit
551 * is set and we do a new loop.
553 __clear_bit(ENGINE_IRQ_EXECLIST
, &engine
->irq_posted
);
554 head
= readl(csb_mmio
);
555 tail
= GEN8_CSB_WRITE_PTR(head
);
556 head
= GEN8_CSB_READ_PTR(head
);
557 while (head
!= tail
) {
560 if (++head
== GEN8_CSB_ENTRIES
)
563 /* We are flying near dragons again.
565 * We hold a reference to the request in execlist_port[]
566 * but no more than that. We are operating in softirq
567 * context and so cannot hold any mutex or sleep. That
568 * prevents us stopping the requests we are processing
569 * in port[] from being retired simultaneously (the
570 * breadcrumb will be complete before we see the
571 * context-switch). As we only hold the reference to the
572 * request, any pointer chasing underneath the request
573 * is subject to a potential use-after-free. Thus we
574 * store all of the bookkeeping within port[] as
575 * required, and avoid using unguarded pointers beneath
576 * request itself. The same applies to the atomic
580 status
= readl(buf
+ 2 * head
);
581 if (!(status
& GEN8_CTX_STATUS_COMPLETED_MASK
))
584 /* Check the context/desc id for this event matches */
585 GEM_DEBUG_BUG_ON(readl(buf
+ 2 * head
+ 1) !=
588 GEM_BUG_ON(port
[0].count
== 0);
589 if (--port
[0].count
== 0) {
590 GEM_BUG_ON(status
& GEN8_CTX_STATUS_PREEMPTED
);
591 GEM_BUG_ON(!i915_gem_request_completed(port
[0].request
));
592 execlists_context_status_change(port
[0].request
,
593 INTEL_CONTEXT_SCHEDULE_OUT
);
595 trace_i915_gem_request_out(port
[0].request
);
596 i915_gem_request_put(port
[0].request
);
598 memset(&port
[1], 0, sizeof(port
[1]));
601 GEM_BUG_ON(port
[0].count
== 0 &&
602 !(status
& GEN8_CTX_STATUS_ACTIVE_IDLE
));
605 writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK
, head
<< 8),
609 if (execlists_elsp_ready(engine
))
610 execlists_dequeue(engine
);
612 intel_uncore_forcewake_put(dev_priv
, engine
->fw_domains
);
615 static bool insert_request(struct i915_priotree
*pt
, struct rb_root
*root
)
617 struct rb_node
**p
, *rb
;
620 /* most positive priority is scheduled first, equal priorities fifo */
624 struct i915_priotree
*pos
;
627 pos
= rb_entry(rb
, typeof(*pos
), node
);
628 if (pt
->priority
> pos
->priority
) {
635 rb_link_node(&pt
->node
, rb
, p
);
636 rb_insert_color(&pt
->node
, root
);
641 static void execlists_submit_request(struct drm_i915_gem_request
*request
)
643 struct intel_engine_cs
*engine
= request
->engine
;
646 /* Will be called from irq-context when using foreign fences. */
647 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
649 if (insert_request(&request
->priotree
, &engine
->execlist_queue
)) {
650 engine
->execlist_first
= &request
->priotree
.node
;
651 if (execlists_elsp_ready(engine
))
652 tasklet_hi_schedule(&engine
->irq_tasklet
);
655 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
658 static struct intel_engine_cs
*
659 pt_lock_engine(struct i915_priotree
*pt
, struct intel_engine_cs
*locked
)
661 struct intel_engine_cs
*engine
=
662 container_of(pt
, struct drm_i915_gem_request
, priotree
)->engine
;
666 if (engine
!= locked
) {
667 spin_unlock(&locked
->timeline
->lock
);
668 spin_lock(&engine
->timeline
->lock
);
674 static void execlists_schedule(struct drm_i915_gem_request
*request
, int prio
)
676 struct intel_engine_cs
*engine
;
677 struct i915_dependency
*dep
, *p
;
678 struct i915_dependency stack
;
681 if (prio
<= READ_ONCE(request
->priotree
.priority
))
684 /* Need BKL in order to use the temporary link inside i915_dependency */
685 lockdep_assert_held(&request
->i915
->drm
.struct_mutex
);
687 stack
.signaler
= &request
->priotree
;
688 list_add(&stack
.dfs_link
, &dfs
);
690 /* Recursively bump all dependent priorities to match the new request.
692 * A naive approach would be to use recursion:
693 * static void update_priorities(struct i915_priotree *pt, prio) {
694 * list_for_each_entry(dep, &pt->signalers_list, signal_link)
695 * update_priorities(dep->signal, prio)
696 * insert_request(pt);
698 * but that may have unlimited recursion depth and so runs a very
699 * real risk of overunning the kernel stack. Instead, we build
700 * a flat list of all dependencies starting with the current request.
701 * As we walk the list of dependencies, we add all of its dependencies
702 * to the end of the list (this may include an already visited
703 * request) and continue to walk onwards onto the new dependencies. The
704 * end result is a topological list of requests in reverse order, the
705 * last element in the list is the request we must execute first.
707 list_for_each_entry_safe(dep
, p
, &dfs
, dfs_link
) {
708 struct i915_priotree
*pt
= dep
->signaler
;
710 /* Within an engine, there can be no cycle, but we may
711 * refer to the same dependency chain multiple times
712 * (redundant dependencies are not eliminated) and across
715 list_for_each_entry(p
, &pt
->signalers_list
, signal_link
) {
716 GEM_BUG_ON(p
->signaler
->priority
< pt
->priority
);
717 if (prio
> READ_ONCE(p
->signaler
->priority
))
718 list_move_tail(&p
->dfs_link
, &dfs
);
721 list_safe_reset_next(dep
, p
, dfs_link
);
724 engine
= request
->engine
;
725 spin_lock_irq(&engine
->timeline
->lock
);
727 /* Fifo and depth-first replacement ensure our deps execute before us */
728 list_for_each_entry_safe_reverse(dep
, p
, &dfs
, dfs_link
) {
729 struct i915_priotree
*pt
= dep
->signaler
;
731 INIT_LIST_HEAD(&dep
->dfs_link
);
733 engine
= pt_lock_engine(pt
, engine
);
735 if (prio
<= pt
->priority
)
739 if (!RB_EMPTY_NODE(&pt
->node
)) {
740 rb_erase(&pt
->node
, &engine
->execlist_queue
);
741 if (insert_request(pt
, &engine
->execlist_queue
))
742 engine
->execlist_first
= &pt
->node
;
746 spin_unlock_irq(&engine
->timeline
->lock
);
748 /* XXX Do we need to preempt to make room for us and our deps? */
751 static int execlists_context_pin(struct intel_engine_cs
*engine
,
752 struct i915_gem_context
*ctx
)
754 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
759 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
763 GEM_BUG_ON(!ce
->pin_count
); /* no overflow please! */
766 ret
= execlists_context_deferred_alloc(ctx
, engine
);
770 GEM_BUG_ON(!ce
->state
);
772 flags
= PIN_GLOBAL
| PIN_HIGH
;
773 if (ctx
->ggtt_offset_bias
)
774 flags
|= PIN_OFFSET_BIAS
| ctx
->ggtt_offset_bias
;
776 ret
= i915_vma_pin(ce
->state
, 0, GEN8_LR_CONTEXT_ALIGN
, flags
);
780 vaddr
= i915_gem_object_pin_map(ce
->state
->obj
, I915_MAP_WB
);
782 ret
= PTR_ERR(vaddr
);
786 ret
= intel_ring_pin(ce
->ring
, ctx
->ggtt_offset_bias
);
790 intel_lr_context_descriptor_update(ctx
, engine
);
792 ce
->lrc_reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
793 ce
->lrc_reg_state
[CTX_RING_BUFFER_START
+1] =
794 i915_ggtt_offset(ce
->ring
->vma
);
796 ce
->state
->obj
->mm
.dirty
= true;
798 i915_gem_context_get(ctx
);
802 i915_gem_object_unpin_map(ce
->state
->obj
);
804 __i915_vma_unpin(ce
->state
);
810 static void execlists_context_unpin(struct intel_engine_cs
*engine
,
811 struct i915_gem_context
*ctx
)
813 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
815 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
816 GEM_BUG_ON(ce
->pin_count
== 0);
821 intel_ring_unpin(ce
->ring
);
823 i915_gem_object_unpin_map(ce
->state
->obj
);
824 i915_vma_unpin(ce
->state
);
826 i915_gem_context_put(ctx
);
829 static int execlists_request_alloc(struct drm_i915_gem_request
*request
)
831 struct intel_engine_cs
*engine
= request
->engine
;
832 struct intel_context
*ce
= &request
->ctx
->engine
[engine
->id
];
836 GEM_BUG_ON(!ce
->pin_count
);
838 /* Flush enough space to reduce the likelihood of waiting after
839 * we start building the request - in which case we will just
840 * have to repeat work.
842 request
->reserved_space
+= EXECLISTS_REQUEST_SIZE
;
844 GEM_BUG_ON(!ce
->ring
);
845 request
->ring
= ce
->ring
;
847 if (i915
.enable_guc_submission
) {
849 * Check that the GuC has space for the request before
850 * going any further, as the i915_add_request() call
851 * later on mustn't fail ...
853 ret
= i915_guc_wq_reserve(request
);
858 cs
= intel_ring_begin(request
, 0);
864 if (!ce
->initialised
) {
865 ret
= engine
->init_context(request
);
869 ce
->initialised
= true;
872 /* Note that after this point, we have committed to using
873 * this request as it is being used to both track the
874 * state of engine initialisation and liveness of the
875 * golden renderstate above. Think twice before you try
876 * to cancel/unwind this request now.
879 request
->reserved_space
-= EXECLISTS_REQUEST_SIZE
;
883 if (i915
.enable_guc_submission
)
884 i915_guc_wq_unreserve(request
);
890 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
891 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
892 * but there is a slight complication as this is applied in WA batch where the
893 * values are only initialized once so we cannot take register value at the
894 * beginning and reuse it further; hence we save its value to memory, upload a
895 * constant value with bit21 set and then we restore it back with the saved value.
896 * To simplify the WA, a constant value is formed by using the default value
897 * of this register. This shouldn't be a problem because we are only modifying
898 * it for a short period and this batch in non-premptible. We can ofcourse
899 * use additional instructions that read the actual value of the register
900 * at that time and set our bit of interest but it makes the WA complicated.
902 * This WA is also required for Gen9 so extracting as a function avoids
906 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*engine
, u32
*batch
)
908 *batch
++ = MI_STORE_REGISTER_MEM_GEN8
| MI_SRM_LRM_GLOBAL_GTT
;
909 *batch
++ = i915_mmio_reg_offset(GEN8_L3SQCREG4
);
910 *batch
++ = i915_ggtt_offset(engine
->scratch
) + 256;
913 *batch
++ = MI_LOAD_REGISTER_IMM(1);
914 *batch
++ = i915_mmio_reg_offset(GEN8_L3SQCREG4
);
915 *batch
++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
;
917 batch
= gen8_emit_pipe_control(batch
,
918 PIPE_CONTROL_CS_STALL
|
919 PIPE_CONTROL_DC_FLUSH_ENABLE
,
922 *batch
++ = MI_LOAD_REGISTER_MEM_GEN8
| MI_SRM_LRM_GLOBAL_GTT
;
923 *batch
++ = i915_mmio_reg_offset(GEN8_L3SQCREG4
);
924 *batch
++ = i915_ggtt_offset(engine
->scratch
) + 256;
931 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
932 * initialized at the beginning and shared across all contexts but this field
933 * helps us to have multiple batches at different offsets and select them based
934 * on a criteria. At the moment this batch always start at the beginning of the page
935 * and at this point we don't have multiple wa_ctx batch buffers.
937 * The number of WA applied are not known at the beginning; we use this field
938 * to return the no of DWORDS written.
940 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
941 * so it adds NOOPs as padding to make it cacheline aligned.
942 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
943 * makes a complete batch buffer.
945 static u32
*gen8_init_indirectctx_bb(struct intel_engine_cs
*engine
, u32
*batch
)
947 /* WaDisableCtxRestoreArbitration:bdw,chv */
948 *batch
++ = MI_ARB_ON_OFF
| MI_ARB_DISABLE
;
950 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
951 if (IS_BROADWELL(engine
->i915
))
952 batch
= gen8_emit_flush_coherentl3_wa(engine
, batch
);
954 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
955 /* Actual scratch location is at 128 bytes offset */
956 batch
= gen8_emit_pipe_control(batch
,
957 PIPE_CONTROL_FLUSH_L3
|
958 PIPE_CONTROL_GLOBAL_GTT_IVB
|
959 PIPE_CONTROL_CS_STALL
|
960 PIPE_CONTROL_QW_WRITE
,
961 i915_ggtt_offset(engine
->scratch
) +
962 2 * CACHELINE_BYTES
);
964 /* Pad to end of cacheline */
965 while ((unsigned long)batch
% CACHELINE_BYTES
)
969 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
970 * execution depends on the length specified in terms of cache lines
971 * in the register CTX_RCS_INDIRECT_CTX
978 * This batch is started immediately after indirect_ctx batch. Since we ensure
979 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
981 * The number of DWORDS written are returned using this field.
983 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
984 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
986 static u32
*gen8_init_perctx_bb(struct intel_engine_cs
*engine
, u32
*batch
)
988 /* WaDisableCtxRestoreArbitration:bdw,chv */
989 *batch
++ = MI_ARB_ON_OFF
| MI_ARB_ENABLE
;
990 *batch
++ = MI_BATCH_BUFFER_END
;
995 static u32
*gen9_init_indirectctx_bb(struct intel_engine_cs
*engine
, u32
*batch
)
997 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
998 batch
= gen8_emit_flush_coherentl3_wa(engine
, batch
);
1000 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
1001 *batch
++ = MI_LOAD_REGISTER_IMM(1);
1002 *batch
++ = i915_mmio_reg_offset(COMMON_SLICE_CHICKEN2
);
1003 *batch
++ = _MASKED_BIT_DISABLE(
1004 GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE
);
1007 /* WaClearSlmSpaceAtContextSwitch:kbl */
1008 /* Actual scratch location is at 128 bytes offset */
1009 if (IS_KBL_REVID(engine
->i915
, 0, KBL_REVID_A0
)) {
1010 batch
= gen8_emit_pipe_control(batch
,
1011 PIPE_CONTROL_FLUSH_L3
|
1012 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1013 PIPE_CONTROL_CS_STALL
|
1014 PIPE_CONTROL_QW_WRITE
,
1015 i915_ggtt_offset(engine
->scratch
)
1016 + 2 * CACHELINE_BYTES
);
1019 /* WaMediaPoolStateCmdInWABB:bxt,glk */
1020 if (HAS_POOLED_EU(engine
->i915
)) {
1022 * EU pool configuration is setup along with golden context
1023 * during context initialization. This value depends on
1024 * device type (2x6 or 3x6) and needs to be updated based
1025 * on which subslice is disabled especially for 2x6
1026 * devices, however it is safe to load default
1027 * configuration of 3x6 device instead of masking off
1028 * corresponding bits because HW ignores bits of a disabled
1029 * subslice and drops down to appropriate config. Please
1030 * see render_state_setup() in i915_gem_render_state.c for
1031 * possible configurations, to avoid duplication they are
1032 * not shown here again.
1034 *batch
++ = GEN9_MEDIA_POOL_STATE
;
1035 *batch
++ = GEN9_MEDIA_POOL_ENABLE
;
1036 *batch
++ = 0x00777000;
1042 /* Pad to end of cacheline */
1043 while ((unsigned long)batch
% CACHELINE_BYTES
)
1049 static u32
*gen9_init_perctx_bb(struct intel_engine_cs
*engine
, u32
*batch
)
1051 *batch
++ = MI_BATCH_BUFFER_END
;
1056 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
1058 static int lrc_setup_wa_ctx(struct intel_engine_cs
*engine
)
1060 struct drm_i915_gem_object
*obj
;
1061 struct i915_vma
*vma
;
1064 obj
= i915_gem_object_create(engine
->i915
, CTX_WA_BB_OBJ_SIZE
);
1066 return PTR_ERR(obj
);
1068 vma
= i915_vma_instance(obj
, &engine
->i915
->ggtt
.base
, NULL
);
1074 err
= i915_vma_pin(vma
, 0, PAGE_SIZE
, PIN_GLOBAL
| PIN_HIGH
);
1078 engine
->wa_ctx
.vma
= vma
;
1082 i915_gem_object_put(obj
);
1086 static void lrc_destroy_wa_ctx(struct intel_engine_cs
*engine
)
1088 i915_vma_unpin_and_release(&engine
->wa_ctx
.vma
);
1091 typedef u32
*(*wa_bb_func_t
)(struct intel_engine_cs
*engine
, u32
*batch
);
1093 static int intel_init_workaround_bb(struct intel_engine_cs
*engine
)
1095 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
1096 struct i915_wa_ctx_bb
*wa_bb
[2] = { &wa_ctx
->indirect_ctx
,
1098 wa_bb_func_t wa_bb_fn
[2];
1100 void *batch
, *batch_ptr
;
1104 if (WARN_ON(engine
->id
!= RCS
|| !engine
->scratch
))
1107 switch (INTEL_GEN(engine
->i915
)) {
1109 wa_bb_fn
[0] = gen9_init_indirectctx_bb
;
1110 wa_bb_fn
[1] = gen9_init_perctx_bb
;
1113 wa_bb_fn
[0] = gen8_init_indirectctx_bb
;
1114 wa_bb_fn
[1] = gen8_init_perctx_bb
;
1117 MISSING_CASE(INTEL_GEN(engine
->i915
));
1121 ret
= lrc_setup_wa_ctx(engine
);
1123 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1127 page
= i915_gem_object_get_dirty_page(wa_ctx
->vma
->obj
, 0);
1128 batch
= batch_ptr
= kmap_atomic(page
);
1131 * Emit the two workaround batch buffers, recording the offset from the
1132 * start of the workaround batch buffer object for each and their
1135 for (i
= 0; i
< ARRAY_SIZE(wa_bb_fn
); i
++) {
1136 wa_bb
[i
]->offset
= batch_ptr
- batch
;
1137 if (WARN_ON(!IS_ALIGNED(wa_bb
[i
]->offset
, CACHELINE_BYTES
))) {
1141 batch_ptr
= wa_bb_fn
[i
](engine
, batch_ptr
);
1142 wa_bb
[i
]->size
= batch_ptr
- (batch
+ wa_bb
[i
]->offset
);
1145 BUG_ON(batch_ptr
- batch
> CTX_WA_BB_OBJ_SIZE
);
1147 kunmap_atomic(batch
);
1149 lrc_destroy_wa_ctx(engine
);
1154 static u32
port_seqno(struct execlist_port
*port
)
1156 return port
->request
? port
->request
->global_seqno
: 0;
1159 static int gen8_init_common_ring(struct intel_engine_cs
*engine
)
1161 struct drm_i915_private
*dev_priv
= engine
->i915
;
1164 ret
= intel_mocs_init_engine(engine
);
1168 intel_engine_reset_breadcrumbs(engine
);
1169 intel_engine_init_hangcheck(engine
);
1171 I915_WRITE(RING_HWSTAM(engine
->mmio_base
), 0xffffffff);
1172 I915_WRITE(RING_MODE_GEN7(engine
),
1173 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1174 I915_WRITE(RING_HWS_PGA(engine
->mmio_base
),
1175 engine
->status_page
.ggtt_offset
);
1176 POSTING_READ(RING_HWS_PGA(engine
->mmio_base
));
1178 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine
->name
);
1180 /* After a GPU reset, we may have requests to replay */
1181 clear_bit(ENGINE_IRQ_EXECLIST
, &engine
->irq_posted
);
1182 if (!i915
.enable_guc_submission
&& !execlists_elsp_idle(engine
)) {
1183 DRM_DEBUG_DRIVER("Restarting %s from requests [0x%x, 0x%x]\n",
1185 port_seqno(&engine
->execlist_port
[0]),
1186 port_seqno(&engine
->execlist_port
[1]));
1187 engine
->execlist_port
[0].count
= 0;
1188 engine
->execlist_port
[1].count
= 0;
1189 execlists_submit_ports(engine
);
1195 static int gen8_init_render_ring(struct intel_engine_cs
*engine
)
1197 struct drm_i915_private
*dev_priv
= engine
->i915
;
1200 ret
= gen8_init_common_ring(engine
);
1204 /* We need to disable the AsyncFlip performance optimisations in order
1205 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1206 * programmed to '1' on all products.
1208 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1210 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1212 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1214 return init_workarounds_ring(engine
);
1217 static int gen9_init_render_ring(struct intel_engine_cs
*engine
)
1221 ret
= gen8_init_common_ring(engine
);
1225 return init_workarounds_ring(engine
);
1228 static void reset_common_ring(struct intel_engine_cs
*engine
,
1229 struct drm_i915_gem_request
*request
)
1231 struct execlist_port
*port
= engine
->execlist_port
;
1232 struct intel_context
*ce
;
1234 /* If the request was innocent, we leave the request in the ELSP
1235 * and will try to replay it on restarting. The context image may
1236 * have been corrupted by the reset, in which case we may have
1237 * to service a new GPU hang, but more likely we can continue on
1240 * If the request was guilty, we presume the context is corrupt
1241 * and have to at least restore the RING register in the context
1242 * image back to the expected values to skip over the guilty request.
1244 if (!request
|| request
->fence
.error
!= -EIO
)
1247 /* We want a simple context + ring to execute the breadcrumb update.
1248 * We cannot rely on the context being intact across the GPU hang,
1249 * so clear it and rebuild just what we need for the breadcrumb.
1250 * All pending requests for this context will be zapped, and any
1251 * future request will be after userspace has had the opportunity
1252 * to recreate its own state.
1254 ce
= &request
->ctx
->engine
[engine
->id
];
1255 execlists_init_reg_state(ce
->lrc_reg_state
,
1256 request
->ctx
, engine
, ce
->ring
);
1258 /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
1259 ce
->lrc_reg_state
[CTX_RING_BUFFER_START
+1] =
1260 i915_ggtt_offset(ce
->ring
->vma
);
1261 ce
->lrc_reg_state
[CTX_RING_HEAD
+1] = request
->postfix
;
1263 request
->ring
->head
= request
->postfix
;
1264 intel_ring_update_space(request
->ring
);
1266 /* Catch up with any missed context-switch interrupts */
1267 if (request
->ctx
!= port
[0].request
->ctx
) {
1268 i915_gem_request_put(port
[0].request
);
1270 memset(&port
[1], 0, sizeof(port
[1]));
1273 GEM_BUG_ON(request
->ctx
!= port
[0].request
->ctx
);
1275 /* Reset WaIdleLiteRestore:bdw,skl as well */
1277 intel_ring_wrap(request
->ring
,
1278 request
->wa_tail
- WA_TAIL_DWORDS
*sizeof(u32
));
1279 assert_ring_tail_valid(request
->ring
, request
->tail
);
1282 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1284 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1285 struct intel_engine_cs
*engine
= req
->engine
;
1286 const int num_lri_cmds
= GEN8_3LVL_PDPES
* 2;
1290 cs
= intel_ring_begin(req
, num_lri_cmds
* 2 + 2);
1294 *cs
++ = MI_LOAD_REGISTER_IMM(num_lri_cmds
);
1295 for (i
= GEN8_3LVL_PDPES
- 1; i
>= 0; i
--) {
1296 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1298 *cs
++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine
, i
));
1299 *cs
++ = upper_32_bits(pd_daddr
);
1300 *cs
++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine
, i
));
1301 *cs
++ = lower_32_bits(pd_daddr
);
1305 intel_ring_advance(req
, cs
);
1310 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1311 u64 offset
, u32 len
,
1312 const unsigned int flags
)
1317 /* Don't rely in hw updating PDPs, specially in lite-restore.
1318 * Ideally, we should set Force PD Restore in ctx descriptor,
1319 * but we can't. Force Restore would be a second option, but
1320 * it is unsafe in case of lite-restore (because the ctx is
1321 * not idle). PML4 is allocated during ppgtt init so this is
1322 * not needed in 48-bit.*/
1323 if (req
->ctx
->ppgtt
&&
1324 (intel_engine_flag(req
->engine
) & req
->ctx
->ppgtt
->pd_dirty_rings
) &&
1325 !i915_vm_is_48bit(&req
->ctx
->ppgtt
->base
) &&
1326 !intel_vgpu_active(req
->i915
)) {
1327 ret
= intel_logical_ring_emit_pdps(req
);
1331 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(req
->engine
);
1334 cs
= intel_ring_begin(req
, 4);
1338 /* FIXME(BDW): Address space and security selectors. */
1339 *cs
++ = MI_BATCH_BUFFER_START_GEN8
|
1340 (flags
& I915_DISPATCH_SECURE
? 0 : BIT(8)) |
1341 (flags
& I915_DISPATCH_RS
? MI_BATCH_RESOURCE_STREAMER
: 0);
1342 *cs
++ = lower_32_bits(offset
);
1343 *cs
++ = upper_32_bits(offset
);
1345 intel_ring_advance(req
, cs
);
1350 static void gen8_logical_ring_enable_irq(struct intel_engine_cs
*engine
)
1352 struct drm_i915_private
*dev_priv
= engine
->i915
;
1353 I915_WRITE_IMR(engine
,
1354 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1355 POSTING_READ_FW(RING_IMR(engine
->mmio_base
));
1358 static void gen8_logical_ring_disable_irq(struct intel_engine_cs
*engine
)
1360 struct drm_i915_private
*dev_priv
= engine
->i915
;
1361 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1364 static int gen8_emit_flush(struct drm_i915_gem_request
*request
, u32 mode
)
1368 cs
= intel_ring_begin(request
, 4);
1372 cmd
= MI_FLUSH_DW
+ 1;
1374 /* We always require a command barrier so that subsequent
1375 * commands, such as breadcrumb interrupts, are strictly ordered
1376 * wrt the contents of the write cache being flushed to memory
1377 * (and thus being coherent from the CPU).
1379 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1381 if (mode
& EMIT_INVALIDATE
) {
1382 cmd
|= MI_INVALIDATE_TLB
;
1383 if (request
->engine
->id
== VCS
)
1384 cmd
|= MI_INVALIDATE_BSD
;
1388 *cs
++ = I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
;
1389 *cs
++ = 0; /* upper addr */
1390 *cs
++ = 0; /* value */
1391 intel_ring_advance(request
, cs
);
1396 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1399 struct intel_engine_cs
*engine
= request
->engine
;
1401 i915_ggtt_offset(engine
->scratch
) + 2 * CACHELINE_BYTES
;
1402 bool vf_flush_wa
= false, dc_flush_wa
= false;
1406 flags
|= PIPE_CONTROL_CS_STALL
;
1408 if (mode
& EMIT_FLUSH
) {
1409 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1410 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1411 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
1412 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
1415 if (mode
& EMIT_INVALIDATE
) {
1416 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1417 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1418 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1419 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1420 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1421 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1422 flags
|= PIPE_CONTROL_QW_WRITE
;
1423 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1426 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1429 if (IS_GEN9(request
->i915
))
1432 /* WaForGAMHang:kbl */
1433 if (IS_KBL_REVID(request
->i915
, 0, KBL_REVID_B0
))
1445 cs
= intel_ring_begin(request
, len
);
1450 cs
= gen8_emit_pipe_control(cs
, 0, 0);
1453 cs
= gen8_emit_pipe_control(cs
, PIPE_CONTROL_DC_FLUSH_ENABLE
,
1456 cs
= gen8_emit_pipe_control(cs
, flags
, scratch_addr
);
1459 cs
= gen8_emit_pipe_control(cs
, PIPE_CONTROL_CS_STALL
, 0);
1461 intel_ring_advance(request
, cs
);
1467 * Reserve space for 2 NOOPs at the end of each request to be
1468 * used as a workaround for not being allowed to do lite
1469 * restore with HEAD==TAIL (WaIdleLiteRestore).
1471 static void gen8_emit_wa_tail(struct drm_i915_gem_request
*request
, u32
*cs
)
1475 request
->wa_tail
= intel_ring_offset(request
, cs
);
1478 static void gen8_emit_breadcrumb(struct drm_i915_gem_request
*request
, u32
*cs
)
1480 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1481 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR
& (1 << 5));
1483 *cs
++ = (MI_FLUSH_DW
+ 1) | MI_FLUSH_DW_OP_STOREDW
;
1484 *cs
++ = intel_hws_seqno_address(request
->engine
) | MI_FLUSH_DW_USE_GTT
;
1486 *cs
++ = request
->global_seqno
;
1487 *cs
++ = MI_USER_INTERRUPT
;
1489 request
->tail
= intel_ring_offset(request
, cs
);
1490 assert_ring_tail_valid(request
->ring
, request
->tail
);
1492 gen8_emit_wa_tail(request
, cs
);
1495 static const int gen8_emit_breadcrumb_sz
= 6 + WA_TAIL_DWORDS
;
1497 static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request
*request
,
1500 /* We're using qword write, seqno should be aligned to 8 bytes. */
1501 BUILD_BUG_ON(I915_GEM_HWS_INDEX
& 1);
1503 /* w/a for post sync ops following a GPGPU operation we
1504 * need a prior CS_STALL, which is emitted by the flush
1505 * following the batch.
1507 *cs
++ = GFX_OP_PIPE_CONTROL(6);
1508 *cs
++ = PIPE_CONTROL_GLOBAL_GTT_IVB
| PIPE_CONTROL_CS_STALL
|
1509 PIPE_CONTROL_QW_WRITE
;
1510 *cs
++ = intel_hws_seqno_address(request
->engine
);
1512 *cs
++ = request
->global_seqno
;
1513 /* We're thrashing one dword of HWS. */
1515 *cs
++ = MI_USER_INTERRUPT
;
1517 request
->tail
= intel_ring_offset(request
, cs
);
1518 assert_ring_tail_valid(request
->ring
, request
->tail
);
1520 gen8_emit_wa_tail(request
, cs
);
1523 static const int gen8_emit_breadcrumb_render_sz
= 8 + WA_TAIL_DWORDS
;
1525 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
1529 ret
= intel_ring_workarounds_emit(req
);
1533 ret
= intel_rcs_context_init_mocs(req
);
1535 * Failing to program the MOCS is non-fatal.The system will not
1536 * run at peak performance. So generate an error and carry on.
1539 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1541 return i915_gem_render_state_emit(req
);
1545 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1546 * @engine: Engine Command Streamer.
1548 void intel_logical_ring_cleanup(struct intel_engine_cs
*engine
)
1550 struct drm_i915_private
*dev_priv
;
1553 * Tasklet cannot be active at this point due intel_mark_active/idle
1554 * so this is just for documentation.
1556 if (WARN_ON(test_bit(TASKLET_STATE_SCHED
, &engine
->irq_tasklet
.state
)))
1557 tasklet_kill(&engine
->irq_tasklet
);
1559 dev_priv
= engine
->i915
;
1561 if (engine
->buffer
) {
1562 WARN_ON((I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
1565 if (engine
->cleanup
)
1566 engine
->cleanup(engine
);
1568 if (engine
->status_page
.vma
) {
1569 i915_gem_object_unpin_map(engine
->status_page
.vma
->obj
);
1570 engine
->status_page
.vma
= NULL
;
1573 intel_engine_cleanup_common(engine
);
1575 lrc_destroy_wa_ctx(engine
);
1576 engine
->i915
= NULL
;
1577 dev_priv
->engine
[engine
->id
] = NULL
;
1581 static void execlists_set_default_submission(struct intel_engine_cs
*engine
)
1583 engine
->submit_request
= execlists_submit_request
;
1584 engine
->schedule
= execlists_schedule
;
1585 engine
->irq_tasklet
.func
= intel_lrc_irq_handler
;
1589 logical_ring_default_vfuncs(struct intel_engine_cs
*engine
)
1591 /* Default vfuncs which can be overriden by each engine. */
1592 engine
->init_hw
= gen8_init_common_ring
;
1593 engine
->reset_hw
= reset_common_ring
;
1595 engine
->context_pin
= execlists_context_pin
;
1596 engine
->context_unpin
= execlists_context_unpin
;
1598 engine
->request_alloc
= execlists_request_alloc
;
1600 engine
->emit_flush
= gen8_emit_flush
;
1601 engine
->emit_breadcrumb
= gen8_emit_breadcrumb
;
1602 engine
->emit_breadcrumb_sz
= gen8_emit_breadcrumb_sz
;
1604 engine
->set_default_submission
= execlists_set_default_submission
;
1606 engine
->irq_enable
= gen8_logical_ring_enable_irq
;
1607 engine
->irq_disable
= gen8_logical_ring_disable_irq
;
1608 engine
->emit_bb_start
= gen8_emit_bb_start
;
1612 logical_ring_default_irqs(struct intel_engine_cs
*engine
)
1614 unsigned shift
= engine
->irq_shift
;
1615 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
<< shift
;
1616 engine
->irq_keep_mask
= GT_CONTEXT_SWITCH_INTERRUPT
<< shift
;
1620 lrc_setup_hws(struct intel_engine_cs
*engine
, struct i915_vma
*vma
)
1622 const int hws_offset
= LRC_PPHWSP_PN
* PAGE_SIZE
;
1625 /* The HWSP is part of the default context object in LRC mode. */
1626 hws
= i915_gem_object_pin_map(vma
->obj
, I915_MAP_WB
);
1628 return PTR_ERR(hws
);
1630 engine
->status_page
.page_addr
= hws
+ hws_offset
;
1631 engine
->status_page
.ggtt_offset
= i915_ggtt_offset(vma
) + hws_offset
;
1632 engine
->status_page
.vma
= vma
;
1638 logical_ring_setup(struct intel_engine_cs
*engine
)
1640 struct drm_i915_private
*dev_priv
= engine
->i915
;
1641 enum forcewake_domains fw_domains
;
1643 intel_engine_setup_common(engine
);
1645 /* Intentionally left blank. */
1646 engine
->buffer
= NULL
;
1648 fw_domains
= intel_uncore_forcewake_for_reg(dev_priv
,
1652 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
1653 RING_CONTEXT_STATUS_PTR(engine
),
1654 FW_REG_READ
| FW_REG_WRITE
);
1656 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
1657 RING_CONTEXT_STATUS_BUF_BASE(engine
),
1660 engine
->fw_domains
= fw_domains
;
1662 tasklet_init(&engine
->irq_tasklet
,
1663 intel_lrc_irq_handler
, (unsigned long)engine
);
1665 logical_ring_default_vfuncs(engine
);
1666 logical_ring_default_irqs(engine
);
1670 logical_ring_init(struct intel_engine_cs
*engine
)
1672 struct i915_gem_context
*dctx
= engine
->i915
->kernel_context
;
1675 ret
= intel_engine_init_common(engine
);
1679 /* And setup the hardware status page. */
1680 ret
= lrc_setup_hws(engine
, dctx
->engine
[engine
->id
].state
);
1682 DRM_ERROR("Failed to set up hws %s: %d\n", engine
->name
, ret
);
1689 intel_logical_ring_cleanup(engine
);
1693 int logical_render_ring_init(struct intel_engine_cs
*engine
)
1695 struct drm_i915_private
*dev_priv
= engine
->i915
;
1698 logical_ring_setup(engine
);
1700 if (HAS_L3_DPF(dev_priv
))
1701 engine
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
1703 /* Override some for render ring. */
1704 if (INTEL_GEN(dev_priv
) >= 9)
1705 engine
->init_hw
= gen9_init_render_ring
;
1707 engine
->init_hw
= gen8_init_render_ring
;
1708 engine
->init_context
= gen8_init_rcs_context
;
1709 engine
->emit_flush
= gen8_emit_flush_render
;
1710 engine
->emit_breadcrumb
= gen8_emit_breadcrumb_render
;
1711 engine
->emit_breadcrumb_sz
= gen8_emit_breadcrumb_render_sz
;
1713 ret
= intel_engine_create_scratch(engine
, PAGE_SIZE
);
1717 ret
= intel_init_workaround_bb(engine
);
1720 * We continue even if we fail to initialize WA batch
1721 * because we only expect rare glitches but nothing
1722 * critical to prevent us from using GPU
1724 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1728 return logical_ring_init(engine
);
1731 int logical_xcs_ring_init(struct intel_engine_cs
*engine
)
1733 logical_ring_setup(engine
);
1735 return logical_ring_init(engine
);
1739 make_rpcs(struct drm_i915_private
*dev_priv
)
1744 * No explicit RPCS request is needed to ensure full
1745 * slice/subslice/EU enablement prior to Gen9.
1747 if (INTEL_GEN(dev_priv
) < 9)
1751 * Starting in Gen9, render power gating can leave
1752 * slice/subslice/EU in a partially enabled state. We
1753 * must make an explicit request through RPCS for full
1756 if (INTEL_INFO(dev_priv
)->sseu
.has_slice_pg
) {
1757 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
1758 rpcs
|= hweight8(INTEL_INFO(dev_priv
)->sseu
.slice_mask
) <<
1759 GEN8_RPCS_S_CNT_SHIFT
;
1760 rpcs
|= GEN8_RPCS_ENABLE
;
1763 if (INTEL_INFO(dev_priv
)->sseu
.has_subslice_pg
) {
1764 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
1765 rpcs
|= hweight8(INTEL_INFO(dev_priv
)->sseu
.subslice_mask
) <<
1766 GEN8_RPCS_SS_CNT_SHIFT
;
1767 rpcs
|= GEN8_RPCS_ENABLE
;
1770 if (INTEL_INFO(dev_priv
)->sseu
.has_eu_pg
) {
1771 rpcs
|= INTEL_INFO(dev_priv
)->sseu
.eu_per_subslice
<<
1772 GEN8_RPCS_EU_MIN_SHIFT
;
1773 rpcs
|= INTEL_INFO(dev_priv
)->sseu
.eu_per_subslice
<<
1774 GEN8_RPCS_EU_MAX_SHIFT
;
1775 rpcs
|= GEN8_RPCS_ENABLE
;
1781 static u32
intel_lr_indirect_ctx_offset(struct intel_engine_cs
*engine
)
1783 u32 indirect_ctx_offset
;
1785 switch (INTEL_GEN(engine
->i915
)) {
1787 MISSING_CASE(INTEL_GEN(engine
->i915
));
1790 indirect_ctx_offset
=
1791 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
1794 indirect_ctx_offset
=
1795 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
1799 return indirect_ctx_offset
;
1802 static void execlists_init_reg_state(u32
*regs
,
1803 struct i915_gem_context
*ctx
,
1804 struct intel_engine_cs
*engine
,
1805 struct intel_ring
*ring
)
1807 struct drm_i915_private
*dev_priv
= engine
->i915
;
1808 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
?: dev_priv
->mm
.aliasing_ppgtt
;
1809 u32 base
= engine
->mmio_base
;
1810 bool rcs
= engine
->id
== RCS
;
1812 /* A context is actually a big batch buffer with several
1813 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
1814 * values we are setting here are only for the first context restore:
1815 * on a subsequent save, the GPU will recreate this batchbuffer with new
1816 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
1817 * we are not initializing here).
1819 regs
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(rcs
? 14 : 11) |
1820 MI_LRI_FORCE_POSTED
;
1822 CTX_REG(regs
, CTX_CONTEXT_CONTROL
, RING_CONTEXT_CONTROL(engine
),
1823 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
1824 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
1825 (HAS_RESOURCE_STREAMER(dev_priv
) ?
1826 CTX_CTRL_RS_CTX_ENABLE
: 0)));
1827 CTX_REG(regs
, CTX_RING_HEAD
, RING_HEAD(base
), 0);
1828 CTX_REG(regs
, CTX_RING_TAIL
, RING_TAIL(base
), 0);
1829 CTX_REG(regs
, CTX_RING_BUFFER_START
, RING_START(base
), 0);
1830 CTX_REG(regs
, CTX_RING_BUFFER_CONTROL
, RING_CTL(base
),
1831 RING_CTL_SIZE(ring
->size
) | RING_VALID
);
1832 CTX_REG(regs
, CTX_BB_HEAD_U
, RING_BBADDR_UDW(base
), 0);
1833 CTX_REG(regs
, CTX_BB_HEAD_L
, RING_BBADDR(base
), 0);
1834 CTX_REG(regs
, CTX_BB_STATE
, RING_BBSTATE(base
), RING_BB_PPGTT
);
1835 CTX_REG(regs
, CTX_SECOND_BB_HEAD_U
, RING_SBBADDR_UDW(base
), 0);
1836 CTX_REG(regs
, CTX_SECOND_BB_HEAD_L
, RING_SBBADDR(base
), 0);
1837 CTX_REG(regs
, CTX_SECOND_BB_STATE
, RING_SBBSTATE(base
), 0);
1839 CTX_REG(regs
, CTX_BB_PER_CTX_PTR
, RING_BB_PER_CTX_PTR(base
), 0);
1840 CTX_REG(regs
, CTX_RCS_INDIRECT_CTX
, RING_INDIRECT_CTX(base
), 0);
1841 CTX_REG(regs
, CTX_RCS_INDIRECT_CTX_OFFSET
,
1842 RING_INDIRECT_CTX_OFFSET(base
), 0);
1844 if (engine
->wa_ctx
.vma
) {
1845 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
1846 u32 ggtt_offset
= i915_ggtt_offset(wa_ctx
->vma
);
1848 regs
[CTX_RCS_INDIRECT_CTX
+ 1] =
1849 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
) |
1850 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_BYTES
);
1852 regs
[CTX_RCS_INDIRECT_CTX_OFFSET
+ 1] =
1853 intel_lr_indirect_ctx_offset(engine
) << 6;
1855 regs
[CTX_BB_PER_CTX_PTR
+ 1] =
1856 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
) | 0x01;
1860 regs
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED
;
1862 CTX_REG(regs
, CTX_CTX_TIMESTAMP
, RING_CTX_TIMESTAMP(base
), 0);
1863 /* PDP values well be assigned later if needed */
1864 CTX_REG(regs
, CTX_PDP3_UDW
, GEN8_RING_PDP_UDW(engine
, 3), 0);
1865 CTX_REG(regs
, CTX_PDP3_LDW
, GEN8_RING_PDP_LDW(engine
, 3), 0);
1866 CTX_REG(regs
, CTX_PDP2_UDW
, GEN8_RING_PDP_UDW(engine
, 2), 0);
1867 CTX_REG(regs
, CTX_PDP2_LDW
, GEN8_RING_PDP_LDW(engine
, 2), 0);
1868 CTX_REG(regs
, CTX_PDP1_UDW
, GEN8_RING_PDP_UDW(engine
, 1), 0);
1869 CTX_REG(regs
, CTX_PDP1_LDW
, GEN8_RING_PDP_LDW(engine
, 1), 0);
1870 CTX_REG(regs
, CTX_PDP0_UDW
, GEN8_RING_PDP_UDW(engine
, 0), 0);
1871 CTX_REG(regs
, CTX_PDP0_LDW
, GEN8_RING_PDP_LDW(engine
, 0), 0);
1873 if (ppgtt
&& i915_vm_is_48bit(&ppgtt
->base
)) {
1874 /* 64b PPGTT (48bit canonical)
1875 * PDP0_DESCRIPTOR contains the base address to PML4 and
1876 * other PDP Descriptors are ignored.
1878 ASSIGN_CTX_PML4(ppgtt
, regs
);
1882 regs
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
1883 CTX_REG(regs
, CTX_R_PWR_CLK_STATE
, GEN8_R_PWR_CLK_STATE
,
1884 make_rpcs(dev_priv
));
1889 populate_lr_context(struct i915_gem_context
*ctx
,
1890 struct drm_i915_gem_object
*ctx_obj
,
1891 struct intel_engine_cs
*engine
,
1892 struct intel_ring
*ring
)
1897 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
1899 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1903 vaddr
= i915_gem_object_pin_map(ctx_obj
, I915_MAP_WB
);
1904 if (IS_ERR(vaddr
)) {
1905 ret
= PTR_ERR(vaddr
);
1906 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret
);
1909 ctx_obj
->mm
.dirty
= true;
1911 /* The second page of the context object contains some fields which must
1912 * be set up prior to the first execution. */
1914 execlists_init_reg_state(vaddr
+ LRC_STATE_PN
* PAGE_SIZE
,
1917 i915_gem_object_unpin_map(ctx_obj
);
1923 * intel_lr_context_size() - return the size of the context for an engine
1924 * @engine: which engine to find the context size for
1926 * Each engine may require a different amount of space for a context image,
1927 * so when allocating (or copying) an image, this function can be used to
1928 * find the right size for the specific engine.
1930 * Return: size (in bytes) of an engine-specific context image
1932 * Note: this size includes the HWSP, which is part of the context image
1933 * in LRC mode, but does not include the "shared data page" used with
1934 * GuC submission. The caller should account for this if using the GuC.
1936 uint32_t intel_lr_context_size(struct intel_engine_cs
*engine
)
1940 WARN_ON(INTEL_GEN(engine
->i915
) < 8);
1942 switch (engine
->id
) {
1944 if (INTEL_GEN(engine
->i915
) >= 9)
1945 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
1947 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
1953 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
1960 static int execlists_context_deferred_alloc(struct i915_gem_context
*ctx
,
1961 struct intel_engine_cs
*engine
)
1963 struct drm_i915_gem_object
*ctx_obj
;
1964 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
1965 struct i915_vma
*vma
;
1966 uint32_t context_size
;
1967 struct intel_ring
*ring
;
1972 context_size
= round_up(intel_lr_context_size(engine
),
1973 I915_GTT_PAGE_SIZE
);
1975 /* One extra page as the sharing data between driver and GuC */
1976 context_size
+= PAGE_SIZE
* LRC_PPHWSP_PN
;
1978 ctx_obj
= i915_gem_object_create(ctx
->i915
, context_size
);
1979 if (IS_ERR(ctx_obj
)) {
1980 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
1981 return PTR_ERR(ctx_obj
);
1984 vma
= i915_vma_instance(ctx_obj
, &ctx
->i915
->ggtt
.base
, NULL
);
1987 goto error_deref_obj
;
1990 ring
= intel_engine_create_ring(engine
, ctx
->ring_size
);
1992 ret
= PTR_ERR(ring
);
1993 goto error_deref_obj
;
1996 ret
= populate_lr_context(ctx
, ctx_obj
, engine
, ring
);
1998 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
1999 goto error_ring_free
;
2004 ce
->initialised
= engine
->init_context
== NULL
;
2009 intel_ring_free(ring
);
2011 i915_gem_object_put(ctx_obj
);
2015 void intel_lr_context_resume(struct drm_i915_private
*dev_priv
)
2017 struct intel_engine_cs
*engine
;
2018 struct i915_gem_context
*ctx
;
2019 enum intel_engine_id id
;
2021 /* Because we emit WA_TAIL_DWORDS there may be a disparity
2022 * between our bookkeeping in ce->ring->head and ce->ring->tail and
2023 * that stored in context. As we only write new commands from
2024 * ce->ring->tail onwards, everything before that is junk. If the GPU
2025 * starts reading from its RING_HEAD from the context, it may try to
2026 * execute that junk and die.
2028 * So to avoid that we reset the context images upon resume. For
2029 * simplicity, we just zero everything out.
2031 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
2032 for_each_engine(engine
, dev_priv
, id
) {
2033 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2039 reg
= i915_gem_object_pin_map(ce
->state
->obj
,
2041 if (WARN_ON(IS_ERR(reg
)))
2044 reg
+= LRC_STATE_PN
* PAGE_SIZE
/ sizeof(*reg
);
2045 reg
[CTX_RING_HEAD
+1] = 0;
2046 reg
[CTX_RING_TAIL
+1] = 0;
2048 ce
->state
->obj
->mm
.dirty
= true;
2049 i915_gem_object_unpin_map(ce
->state
->obj
);
2051 ce
->ring
->head
= ce
->ring
->tail
= 0;
2052 intel_ring_update_space(ce
->ring
);