2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define RING_EXECLIST_QFULL (1 << 0x2)
142 #define RING_EXECLIST1_VALID (1 << 0x3)
143 #define RING_EXECLIST0_VALID (1 << 0x4)
144 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
145 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
146 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
148 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
149 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
150 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
151 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
152 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
153 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
155 #define GEN8_CTX_STATUS_COMPLETED_MASK \
156 (GEN8_CTX_STATUS_ACTIVE_IDLE | \
157 GEN8_CTX_STATUS_PREEMPTED | \
158 GEN8_CTX_STATUS_ELEMENT_SWITCH)
160 #define CTX_LRI_HEADER_0 0x01
161 #define CTX_CONTEXT_CONTROL 0x02
162 #define CTX_RING_HEAD 0x04
163 #define CTX_RING_TAIL 0x06
164 #define CTX_RING_BUFFER_START 0x08
165 #define CTX_RING_BUFFER_CONTROL 0x0a
166 #define CTX_BB_HEAD_U 0x0c
167 #define CTX_BB_HEAD_L 0x0e
168 #define CTX_BB_STATE 0x10
169 #define CTX_SECOND_BB_HEAD_U 0x12
170 #define CTX_SECOND_BB_HEAD_L 0x14
171 #define CTX_SECOND_BB_STATE 0x16
172 #define CTX_BB_PER_CTX_PTR 0x18
173 #define CTX_RCS_INDIRECT_CTX 0x1a
174 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
175 #define CTX_LRI_HEADER_1 0x21
176 #define CTX_CTX_TIMESTAMP 0x22
177 #define CTX_PDP3_UDW 0x24
178 #define CTX_PDP3_LDW 0x26
179 #define CTX_PDP2_UDW 0x28
180 #define CTX_PDP2_LDW 0x2a
181 #define CTX_PDP1_UDW 0x2c
182 #define CTX_PDP1_LDW 0x2e
183 #define CTX_PDP0_UDW 0x30
184 #define CTX_PDP0_LDW 0x32
185 #define CTX_LRI_HEADER_2 0x41
186 #define CTX_R_PWR_CLK_STATE 0x42
187 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
189 #define CTX_REG(reg_state, pos, reg, val) do { \
190 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
191 (reg_state)[(pos)+1] = (val); \
194 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
195 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
196 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
197 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
200 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
201 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
202 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
205 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
206 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
207 #define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x19
209 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
210 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
212 #define WA_TAIL_DWORDS 2
214 static int execlists_context_deferred_alloc(struct i915_gem_context
*ctx
,
215 struct intel_engine_cs
*engine
);
216 static void execlists_init_reg_state(u32
*reg_state
,
217 struct i915_gem_context
*ctx
,
218 struct intel_engine_cs
*engine
,
219 struct intel_ring
*ring
);
222 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
223 * @dev_priv: i915 device private
224 * @enable_execlists: value of i915.enable_execlists module parameter.
226 * Only certain platforms support Execlists (the prerequisites being
227 * support for Logical Ring Contexts and Aliasing PPGTT or better).
229 * Return: 1 if Execlists is supported and has to be enabled.
231 int intel_sanitize_enable_execlists(struct drm_i915_private
*dev_priv
, int enable_execlists
)
233 /* On platforms with execlist available, vGPU will only
234 * support execlist mode, no ring buffer mode.
236 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv
) && intel_vgpu_active(dev_priv
))
239 if (INTEL_GEN(dev_priv
) >= 9)
242 if (enable_execlists
== 0)
245 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv
) &&
246 USES_PPGTT(dev_priv
) &&
247 i915
.use_mmio_flip
>= 0)
254 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
255 * descriptor for a pinned context
256 * @ctx: Context to work on
257 * @engine: Engine the descriptor will be used with
259 * The context descriptor encodes various attributes of a context,
260 * including its GTT address and some flags. Because it's fairly
261 * expensive to calculate, we'll just do it once and cache the result,
262 * which remains valid until the context is unpinned.
264 * This is what a descriptor looks like, from LSB to MSB::
266 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
267 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
268 * bits 32-52: ctx ID, a globally unique tag
269 * bits 53-54: mbz, reserved for use by hardware
270 * bits 55-63: group ID, currently unused and set to 0
273 intel_lr_context_descriptor_update(struct i915_gem_context
*ctx
,
274 struct intel_engine_cs
*engine
)
276 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
279 BUILD_BUG_ON(MAX_CONTEXT_HW_ID
> (1<<GEN8_CTX_ID_WIDTH
));
281 desc
= ctx
->desc_template
; /* bits 0-11 */
282 desc
|= i915_ggtt_offset(ce
->state
) + LRC_PPHWSP_PN
* PAGE_SIZE
;
284 desc
|= (u64
)ctx
->hw_id
<< GEN8_CTX_ID_SHIFT
; /* bits 32-52 */
289 uint64_t intel_lr_context_descriptor(struct i915_gem_context
*ctx
,
290 struct intel_engine_cs
*engine
)
292 return ctx
->engine
[engine
->id
].lrc_desc
;
296 execlists_context_status_change(struct drm_i915_gem_request
*rq
,
297 unsigned long status
)
300 * Only used when GVT-g is enabled now. When GVT-g is disabled,
301 * The compiler should eliminate this function as dead-code.
303 if (!IS_ENABLED(CONFIG_DRM_I915_GVT
))
306 atomic_notifier_call_chain(&rq
->engine
->context_status_notifier
,
311 execlists_update_context_pdps(struct i915_hw_ppgtt
*ppgtt
, u32
*reg_state
)
313 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
314 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
315 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
316 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
319 static u64
execlists_update_context(struct drm_i915_gem_request
*rq
)
321 struct intel_context
*ce
= &rq
->ctx
->engine
[rq
->engine
->id
];
322 struct i915_hw_ppgtt
*ppgtt
=
323 rq
->ctx
->ppgtt
?: rq
->i915
->mm
.aliasing_ppgtt
;
324 u32
*reg_state
= ce
->lrc_reg_state
;
326 reg_state
[CTX_RING_TAIL
+1] = intel_ring_set_tail(rq
->ring
, rq
->tail
);
328 /* True 32b PPGTT with dynamic page allocation: update PDP
329 * registers and point the unallocated PDPs to scratch page.
330 * PML4 is allocated during ppgtt init, so this is not needed
333 if (ppgtt
&& !i915_vm_is_48bit(&ppgtt
->base
))
334 execlists_update_context_pdps(ppgtt
, reg_state
);
339 static void execlists_submit_ports(struct intel_engine_cs
*engine
)
341 struct execlist_port
*port
= engine
->execlist_port
;
343 engine
->i915
->regs
+ i915_mmio_reg_offset(RING_ELSP(engine
));
346 for (n
= ARRAY_SIZE(engine
->execlist_port
); n
--; ) {
347 struct drm_i915_gem_request
*rq
;
351 rq
= port_unpack(&port
[n
], &count
);
353 GEM_BUG_ON(count
> !n
);
355 execlists_context_status_change(rq
, INTEL_CONTEXT_SCHEDULE_IN
);
356 port_set(&port
[n
], port_pack(rq
, count
));
357 desc
= execlists_update_context(rq
);
358 GEM_DEBUG_EXEC(port
[n
].context_id
= upper_32_bits(desc
));
364 writel(upper_32_bits(desc
), elsp
);
365 writel(lower_32_bits(desc
), elsp
);
369 static bool ctx_single_port_submission(const struct i915_gem_context
*ctx
)
371 return (IS_ENABLED(CONFIG_DRM_I915_GVT
) &&
372 i915_gem_context_force_single_submission(ctx
));
375 static bool can_merge_ctx(const struct i915_gem_context
*prev
,
376 const struct i915_gem_context
*next
)
381 if (ctx_single_port_submission(prev
))
387 static void port_assign(struct execlist_port
*port
,
388 struct drm_i915_gem_request
*rq
)
390 GEM_BUG_ON(rq
== port_request(port
));
392 if (port_isset(port
))
393 i915_gem_request_put(port_request(port
));
395 port_set(port
, port_pack(i915_gem_request_get(rq
), port_count(port
)));
398 static void execlists_dequeue(struct intel_engine_cs
*engine
)
400 struct drm_i915_gem_request
*last
;
401 struct execlist_port
*port
= engine
->execlist_port
;
405 last
= port_request(port
);
407 /* WaIdleLiteRestore:bdw,skl
408 * Apply the wa NOOPs to prevent ring:HEAD == req:TAIL
409 * as we resubmit the request. See gen8_emit_breadcrumb()
410 * for where we prepare the padding after the end of the
413 last
->tail
= last
->wa_tail
;
415 GEM_BUG_ON(port_isset(&port
[1]));
417 /* Hardware submission is through 2 ports. Conceptually each port
418 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
419 * static for a context, and unique to each, so we only execute
420 * requests belonging to a single context from each ring. RING_HEAD
421 * is maintained by the CS in the context image, it marks the place
422 * where it got up to last time, and through RING_TAIL we tell the CS
423 * where we want to execute up to this time.
425 * In this list the requests are in order of execution. Consecutive
426 * requests from the same context are adjacent in the ringbuffer. We
427 * can combine these requests into a single RING_TAIL update:
429 * RING_HEAD...req1...req2
431 * since to execute req2 the CS must first execute req1.
433 * Our goal then is to point each port to the end of a consecutive
434 * sequence of requests as being the most optimal (fewest wake ups
435 * and context switches) submission.
438 spin_lock_irq(&engine
->timeline
->lock
);
439 rb
= engine
->execlist_first
;
440 GEM_BUG_ON(rb_first(&engine
->execlist_queue
) != rb
);
442 struct i915_priolist
*p
= rb_entry(rb
, typeof(*p
), node
);
443 struct drm_i915_gem_request
*rq
, *rn
;
445 list_for_each_entry_safe(rq
, rn
, &p
->requests
, priotree
.link
) {
447 * Can we combine this request with the current port?
448 * It has to be the same context/ringbuffer and not
449 * have any exceptions (e.g. GVT saying never to
452 * If we can combine the requests, we can execute both
453 * by updating the RING_TAIL to point to the end of the
454 * second request, and so we never need to tell the
455 * hardware about the first.
457 if (last
&& !can_merge_ctx(rq
->ctx
, last
->ctx
)) {
459 * If we are on the second port and cannot
460 * combine this request with the last, then we
463 if (port
!= engine
->execlist_port
) {
464 __list_del_many(&p
->requests
,
470 * If GVT overrides us we only ever submit
471 * port[0], leaving port[1] empty. Note that we
472 * also have to be careful that we don't queue
473 * the same context (even though a different
474 * request) to the second port.
476 if (ctx_single_port_submission(last
->ctx
) ||
477 ctx_single_port_submission(rq
->ctx
)) {
478 __list_del_many(&p
->requests
,
483 GEM_BUG_ON(last
->ctx
== rq
->ctx
);
486 port_assign(port
, last
);
490 INIT_LIST_HEAD(&rq
->priotree
.link
);
491 rq
->priotree
.priority
= INT_MAX
;
493 __i915_gem_request_submit(rq
);
494 trace_i915_gem_request_in(rq
, port_index(port
, engine
));
500 rb_erase(&p
->node
, &engine
->execlist_queue
);
501 INIT_LIST_HEAD(&p
->requests
);
502 if (p
->priority
!= I915_PRIORITY_NORMAL
)
503 kmem_cache_free(engine
->i915
->priorities
, p
);
506 engine
->execlist_first
= rb
;
508 port_assign(port
, last
);
509 spin_unlock_irq(&engine
->timeline
->lock
);
512 execlists_submit_ports(engine
);
515 static bool execlists_elsp_ready(const struct intel_engine_cs
*engine
)
517 const struct execlist_port
*port
= engine
->execlist_port
;
519 return port_count(&port
[0]) + port_count(&port
[1]) < 2;
523 * Check the unread Context Status Buffers and manage the submission of new
524 * contexts to the ELSP accordingly.
526 static void intel_lrc_irq_handler(unsigned long data
)
528 struct intel_engine_cs
*engine
= (struct intel_engine_cs
*)data
;
529 struct execlist_port
*port
= engine
->execlist_port
;
530 struct drm_i915_private
*dev_priv
= engine
->i915
;
532 /* We can skip acquiring intel_runtime_pm_get() here as it was taken
533 * on our behalf by the request (see i915_gem_mark_busy()) and it will
534 * not be relinquished until the device is idle (see
535 * i915_gem_idle_work_handler()). As a precaution, we make sure
536 * that all ELSP are drained i.e. we have processed the CSB,
537 * before allowing ourselves to idle and calling intel_runtime_pm_put().
539 GEM_BUG_ON(!dev_priv
->gt
.awake
);
541 intel_uncore_forcewake_get(dev_priv
, engine
->fw_domains
);
543 /* Prefer doing test_and_clear_bit() as a two stage operation to avoid
544 * imposing the cost of a locked atomic transaction when submitting a
545 * new request (outside of the context-switch interrupt).
547 while (test_bit(ENGINE_IRQ_EXECLIST
, &engine
->irq_posted
)) {
548 u32 __iomem
*csb_mmio
=
549 dev_priv
->regs
+ i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine
));
551 dev_priv
->regs
+ i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine
, 0));
552 unsigned int head
, tail
;
554 /* The write will be ordered by the uncached read (itself
555 * a memory barrier), so we do not need another in the form
556 * of a locked instruction. The race between the interrupt
557 * handler and the split test/clear is harmless as we order
558 * our clear before the CSB read. If the interrupt arrived
559 * first between the test and the clear, we read the updated
560 * CSB and clear the bit. If the interrupt arrives as we read
561 * the CSB or later (i.e. after we had cleared the bit) the bit
562 * is set and we do a new loop.
564 __clear_bit(ENGINE_IRQ_EXECLIST
, &engine
->irq_posted
);
565 head
= readl(csb_mmio
);
566 tail
= GEN8_CSB_WRITE_PTR(head
);
567 head
= GEN8_CSB_READ_PTR(head
);
568 while (head
!= tail
) {
569 struct drm_i915_gem_request
*rq
;
573 if (++head
== GEN8_CSB_ENTRIES
)
576 /* We are flying near dragons again.
578 * We hold a reference to the request in execlist_port[]
579 * but no more than that. We are operating in softirq
580 * context and so cannot hold any mutex or sleep. That
581 * prevents us stopping the requests we are processing
582 * in port[] from being retired simultaneously (the
583 * breadcrumb will be complete before we see the
584 * context-switch). As we only hold the reference to the
585 * request, any pointer chasing underneath the request
586 * is subject to a potential use-after-free. Thus we
587 * store all of the bookkeeping within port[] as
588 * required, and avoid using unguarded pointers beneath
589 * request itself. The same applies to the atomic
593 status
= readl(buf
+ 2 * head
);
594 if (!(status
& GEN8_CTX_STATUS_COMPLETED_MASK
))
597 /* Check the context/desc id for this event matches */
598 GEM_DEBUG_BUG_ON(readl(buf
+ 2 * head
+ 1) !=
601 rq
= port_unpack(port
, &count
);
602 GEM_BUG_ON(count
== 0);
604 GEM_BUG_ON(status
& GEN8_CTX_STATUS_PREEMPTED
);
605 GEM_BUG_ON(!i915_gem_request_completed(rq
));
606 execlists_context_status_change(rq
, INTEL_CONTEXT_SCHEDULE_OUT
);
608 trace_i915_gem_request_out(rq
);
609 i915_gem_request_put(rq
);
612 memset(&port
[1], 0, sizeof(port
[1]));
614 port_set(port
, port_pack(rq
, count
));
617 /* After the final element, the hw should be idle */
618 GEM_BUG_ON(port_count(port
) == 0 &&
619 !(status
& GEN8_CTX_STATUS_ACTIVE_IDLE
));
622 writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK
, head
<< 8),
626 if (execlists_elsp_ready(engine
))
627 execlists_dequeue(engine
);
629 intel_uncore_forcewake_put(dev_priv
, engine
->fw_domains
);
633 insert_request(struct intel_engine_cs
*engine
,
634 struct i915_priotree
*pt
,
637 struct i915_priolist
*p
;
638 struct rb_node
**parent
, *rb
;
641 if (unlikely(engine
->no_priolist
))
642 prio
= I915_PRIORITY_NORMAL
;
645 /* most positive priority is scheduled first, equal priorities fifo */
647 parent
= &engine
->execlist_queue
.rb_node
;
650 p
= rb_entry(rb
, typeof(*p
), node
);
651 if (prio
> p
->priority
) {
652 parent
= &rb
->rb_left
;
653 } else if (prio
< p
->priority
) {
654 parent
= &rb
->rb_right
;
657 list_add_tail(&pt
->link
, &p
->requests
);
662 if (prio
== I915_PRIORITY_NORMAL
) {
663 p
= &engine
->default_priolist
;
665 p
= kmem_cache_alloc(engine
->i915
->priorities
, GFP_ATOMIC
);
666 /* Convert an allocation failure to a priority bump */
668 prio
= I915_PRIORITY_NORMAL
; /* recurses just once */
670 /* To maintain ordering with all rendering, after an
671 * allocation failure we have to disable all scheduling.
672 * Requests will then be executed in fifo, and schedule
673 * will ensure that dependencies are emitted in fifo.
674 * There will be still some reordering with existing
675 * requests, so if userspace lied about their
676 * dependencies that reordering may be visible.
678 engine
->no_priolist
= true;
684 rb_link_node(&p
->node
, rb
, parent
);
685 rb_insert_color(&p
->node
, &engine
->execlist_queue
);
687 INIT_LIST_HEAD(&p
->requests
);
688 list_add_tail(&pt
->link
, &p
->requests
);
691 engine
->execlist_first
= &p
->node
;
696 static void execlists_submit_request(struct drm_i915_gem_request
*request
)
698 struct intel_engine_cs
*engine
= request
->engine
;
701 /* Will be called from irq-context when using foreign fences. */
702 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
704 if (insert_request(engine
,
706 request
->priotree
.priority
)) {
707 if (execlists_elsp_ready(engine
))
708 tasklet_hi_schedule(&engine
->irq_tasklet
);
711 GEM_BUG_ON(!engine
->execlist_first
);
712 GEM_BUG_ON(list_empty(&request
->priotree
.link
));
714 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
717 static struct intel_engine_cs
*
718 pt_lock_engine(struct i915_priotree
*pt
, struct intel_engine_cs
*locked
)
720 struct intel_engine_cs
*engine
=
721 container_of(pt
, struct drm_i915_gem_request
, priotree
)->engine
;
725 if (engine
!= locked
) {
726 spin_unlock(&locked
->timeline
->lock
);
727 spin_lock(&engine
->timeline
->lock
);
733 static void execlists_schedule(struct drm_i915_gem_request
*request
, int prio
)
735 struct intel_engine_cs
*engine
;
736 struct i915_dependency
*dep
, *p
;
737 struct i915_dependency stack
;
740 if (prio
<= READ_ONCE(request
->priotree
.priority
))
743 /* Need BKL in order to use the temporary link inside i915_dependency */
744 lockdep_assert_held(&request
->i915
->drm
.struct_mutex
);
746 stack
.signaler
= &request
->priotree
;
747 list_add(&stack
.dfs_link
, &dfs
);
749 /* Recursively bump all dependent priorities to match the new request.
751 * A naive approach would be to use recursion:
752 * static void update_priorities(struct i915_priotree *pt, prio) {
753 * list_for_each_entry(dep, &pt->signalers_list, signal_link)
754 * update_priorities(dep->signal, prio)
755 * insert_request(pt);
757 * but that may have unlimited recursion depth and so runs a very
758 * real risk of overunning the kernel stack. Instead, we build
759 * a flat list of all dependencies starting with the current request.
760 * As we walk the list of dependencies, we add all of its dependencies
761 * to the end of the list (this may include an already visited
762 * request) and continue to walk onwards onto the new dependencies. The
763 * end result is a topological list of requests in reverse order, the
764 * last element in the list is the request we must execute first.
766 list_for_each_entry_safe(dep
, p
, &dfs
, dfs_link
) {
767 struct i915_priotree
*pt
= dep
->signaler
;
769 /* Within an engine, there can be no cycle, but we may
770 * refer to the same dependency chain multiple times
771 * (redundant dependencies are not eliminated) and across
774 list_for_each_entry(p
, &pt
->signalers_list
, signal_link
) {
775 GEM_BUG_ON(p
->signaler
->priority
< pt
->priority
);
776 if (prio
> READ_ONCE(p
->signaler
->priority
))
777 list_move_tail(&p
->dfs_link
, &dfs
);
780 list_safe_reset_next(dep
, p
, dfs_link
);
783 /* If we didn't need to bump any existing priorities, and we haven't
784 * yet submitted this request (i.e. there is no potential race with
785 * execlists_submit_request()), we can set our own priority and skip
786 * acquiring the engine locks.
788 if (request
->priotree
.priority
== INT_MIN
) {
789 GEM_BUG_ON(!list_empty(&request
->priotree
.link
));
790 request
->priotree
.priority
= prio
;
791 if (stack
.dfs_link
.next
== stack
.dfs_link
.prev
)
793 __list_del_entry(&stack
.dfs_link
);
796 engine
= request
->engine
;
797 spin_lock_irq(&engine
->timeline
->lock
);
799 /* Fifo and depth-first replacement ensure our deps execute before us */
800 list_for_each_entry_safe_reverse(dep
, p
, &dfs
, dfs_link
) {
801 struct i915_priotree
*pt
= dep
->signaler
;
803 INIT_LIST_HEAD(&dep
->dfs_link
);
805 engine
= pt_lock_engine(pt
, engine
);
807 if (prio
<= pt
->priority
)
811 if (!list_empty(&pt
->link
)) {
812 __list_del_entry(&pt
->link
);
813 insert_request(engine
, pt
, prio
);
817 spin_unlock_irq(&engine
->timeline
->lock
);
819 /* XXX Do we need to preempt to make room for us and our deps? */
822 static struct intel_ring
*
823 execlists_context_pin(struct intel_engine_cs
*engine
,
824 struct i915_gem_context
*ctx
)
826 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
831 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
833 if (likely(ce
->pin_count
++))
835 GEM_BUG_ON(!ce
->pin_count
); /* no overflow please! */
838 ret
= execlists_context_deferred_alloc(ctx
, engine
);
842 GEM_BUG_ON(!ce
->state
);
844 flags
= PIN_GLOBAL
| PIN_HIGH
;
845 if (ctx
->ggtt_offset_bias
)
846 flags
|= PIN_OFFSET_BIAS
| ctx
->ggtt_offset_bias
;
848 ret
= i915_vma_pin(ce
->state
, 0, GEN8_LR_CONTEXT_ALIGN
, flags
);
852 vaddr
= i915_gem_object_pin_map(ce
->state
->obj
, I915_MAP_WB
);
854 ret
= PTR_ERR(vaddr
);
858 ret
= intel_ring_pin(ce
->ring
, ctx
->i915
, ctx
->ggtt_offset_bias
);
862 intel_lr_context_descriptor_update(ctx
, engine
);
864 ce
->lrc_reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
865 ce
->lrc_reg_state
[CTX_RING_BUFFER_START
+1] =
866 i915_ggtt_offset(ce
->ring
->vma
);
868 ce
->state
->obj
->mm
.dirty
= true;
870 i915_gem_context_get(ctx
);
875 i915_gem_object_unpin_map(ce
->state
->obj
);
877 __i915_vma_unpin(ce
->state
);
883 static void execlists_context_unpin(struct intel_engine_cs
*engine
,
884 struct i915_gem_context
*ctx
)
886 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
888 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
889 GEM_BUG_ON(ce
->pin_count
== 0);
894 intel_ring_unpin(ce
->ring
);
896 i915_gem_object_unpin_map(ce
->state
->obj
);
897 i915_vma_unpin(ce
->state
);
899 i915_gem_context_put(ctx
);
902 static int execlists_request_alloc(struct drm_i915_gem_request
*request
)
904 struct intel_engine_cs
*engine
= request
->engine
;
905 struct intel_context
*ce
= &request
->ctx
->engine
[engine
->id
];
909 GEM_BUG_ON(!ce
->pin_count
);
911 /* Flush enough space to reduce the likelihood of waiting after
912 * we start building the request - in which case we will just
913 * have to repeat work.
915 request
->reserved_space
+= EXECLISTS_REQUEST_SIZE
;
917 if (i915
.enable_guc_submission
) {
919 * Check that the GuC has space for the request before
920 * going any further, as the i915_add_request() call
921 * later on mustn't fail ...
923 ret
= i915_guc_wq_reserve(request
);
928 cs
= intel_ring_begin(request
, 0);
934 if (!ce
->initialised
) {
935 ret
= engine
->init_context(request
);
939 ce
->initialised
= true;
942 /* Note that after this point, we have committed to using
943 * this request as it is being used to both track the
944 * state of engine initialisation and liveness of the
945 * golden renderstate above. Think twice before you try
946 * to cancel/unwind this request now.
949 request
->reserved_space
-= EXECLISTS_REQUEST_SIZE
;
953 if (i915
.enable_guc_submission
)
954 i915_guc_wq_unreserve(request
);
960 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
961 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
962 * but there is a slight complication as this is applied in WA batch where the
963 * values are only initialized once so we cannot take register value at the
964 * beginning and reuse it further; hence we save its value to memory, upload a
965 * constant value with bit21 set and then we restore it back with the saved value.
966 * To simplify the WA, a constant value is formed by using the default value
967 * of this register. This shouldn't be a problem because we are only modifying
968 * it for a short period and this batch in non-premptible. We can ofcourse
969 * use additional instructions that read the actual value of the register
970 * at that time and set our bit of interest but it makes the WA complicated.
972 * This WA is also required for Gen9 so extracting as a function avoids
976 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*engine
, u32
*batch
)
978 *batch
++ = MI_STORE_REGISTER_MEM_GEN8
| MI_SRM_LRM_GLOBAL_GTT
;
979 *batch
++ = i915_mmio_reg_offset(GEN8_L3SQCREG4
);
980 *batch
++ = i915_ggtt_offset(engine
->scratch
) + 256;
983 *batch
++ = MI_LOAD_REGISTER_IMM(1);
984 *batch
++ = i915_mmio_reg_offset(GEN8_L3SQCREG4
);
985 *batch
++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
;
987 batch
= gen8_emit_pipe_control(batch
,
988 PIPE_CONTROL_CS_STALL
|
989 PIPE_CONTROL_DC_FLUSH_ENABLE
,
992 *batch
++ = MI_LOAD_REGISTER_MEM_GEN8
| MI_SRM_LRM_GLOBAL_GTT
;
993 *batch
++ = i915_mmio_reg_offset(GEN8_L3SQCREG4
);
994 *batch
++ = i915_ggtt_offset(engine
->scratch
) + 256;
1001 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1002 * initialized at the beginning and shared across all contexts but this field
1003 * helps us to have multiple batches at different offsets and select them based
1004 * on a criteria. At the moment this batch always start at the beginning of the page
1005 * and at this point we don't have multiple wa_ctx batch buffers.
1007 * The number of WA applied are not known at the beginning; we use this field
1008 * to return the no of DWORDS written.
1010 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1011 * so it adds NOOPs as padding to make it cacheline aligned.
1012 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1013 * makes a complete batch buffer.
1015 static u32
*gen8_init_indirectctx_bb(struct intel_engine_cs
*engine
, u32
*batch
)
1017 /* WaDisableCtxRestoreArbitration:bdw,chv */
1018 *batch
++ = MI_ARB_ON_OFF
| MI_ARB_DISABLE
;
1020 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1021 if (IS_BROADWELL(engine
->i915
))
1022 batch
= gen8_emit_flush_coherentl3_wa(engine
, batch
);
1024 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1025 /* Actual scratch location is at 128 bytes offset */
1026 batch
= gen8_emit_pipe_control(batch
,
1027 PIPE_CONTROL_FLUSH_L3
|
1028 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1029 PIPE_CONTROL_CS_STALL
|
1030 PIPE_CONTROL_QW_WRITE
,
1031 i915_ggtt_offset(engine
->scratch
) +
1032 2 * CACHELINE_BYTES
);
1034 /* Pad to end of cacheline */
1035 while ((unsigned long)batch
% CACHELINE_BYTES
)
1039 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1040 * execution depends on the length specified in terms of cache lines
1041 * in the register CTX_RCS_INDIRECT_CTX
1048 * This batch is started immediately after indirect_ctx batch. Since we ensure
1049 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1051 * The number of DWORDS written are returned using this field.
1053 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1054 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1056 static u32
*gen8_init_perctx_bb(struct intel_engine_cs
*engine
, u32
*batch
)
1058 /* WaDisableCtxRestoreArbitration:bdw,chv */
1059 *batch
++ = MI_ARB_ON_OFF
| MI_ARB_ENABLE
;
1060 *batch
++ = MI_BATCH_BUFFER_END
;
1065 static u32
*gen9_init_indirectctx_bb(struct intel_engine_cs
*engine
, u32
*batch
)
1067 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
1068 batch
= gen8_emit_flush_coherentl3_wa(engine
, batch
);
1070 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
1071 *batch
++ = MI_LOAD_REGISTER_IMM(1);
1072 *batch
++ = i915_mmio_reg_offset(COMMON_SLICE_CHICKEN2
);
1073 *batch
++ = _MASKED_BIT_DISABLE(
1074 GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE
);
1077 /* WaClearSlmSpaceAtContextSwitch:kbl */
1078 /* Actual scratch location is at 128 bytes offset */
1079 if (IS_KBL_REVID(engine
->i915
, 0, KBL_REVID_A0
)) {
1080 batch
= gen8_emit_pipe_control(batch
,
1081 PIPE_CONTROL_FLUSH_L3
|
1082 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1083 PIPE_CONTROL_CS_STALL
|
1084 PIPE_CONTROL_QW_WRITE
,
1085 i915_ggtt_offset(engine
->scratch
)
1086 + 2 * CACHELINE_BYTES
);
1089 /* WaMediaPoolStateCmdInWABB:bxt,glk */
1090 if (HAS_POOLED_EU(engine
->i915
)) {
1092 * EU pool configuration is setup along with golden context
1093 * during context initialization. This value depends on
1094 * device type (2x6 or 3x6) and needs to be updated based
1095 * on which subslice is disabled especially for 2x6
1096 * devices, however it is safe to load default
1097 * configuration of 3x6 device instead of masking off
1098 * corresponding bits because HW ignores bits of a disabled
1099 * subslice and drops down to appropriate config. Please
1100 * see render_state_setup() in i915_gem_render_state.c for
1101 * possible configurations, to avoid duplication they are
1102 * not shown here again.
1104 *batch
++ = GEN9_MEDIA_POOL_STATE
;
1105 *batch
++ = GEN9_MEDIA_POOL_ENABLE
;
1106 *batch
++ = 0x00777000;
1112 /* Pad to end of cacheline */
1113 while ((unsigned long)batch
% CACHELINE_BYTES
)
1119 static u32
*gen9_init_perctx_bb(struct intel_engine_cs
*engine
, u32
*batch
)
1121 *batch
++ = MI_BATCH_BUFFER_END
;
1126 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
1128 static int lrc_setup_wa_ctx(struct intel_engine_cs
*engine
)
1130 struct drm_i915_gem_object
*obj
;
1131 struct i915_vma
*vma
;
1134 obj
= i915_gem_object_create(engine
->i915
, CTX_WA_BB_OBJ_SIZE
);
1136 return PTR_ERR(obj
);
1138 vma
= i915_vma_instance(obj
, &engine
->i915
->ggtt
.base
, NULL
);
1144 err
= i915_vma_pin(vma
, 0, PAGE_SIZE
, PIN_GLOBAL
| PIN_HIGH
);
1148 engine
->wa_ctx
.vma
= vma
;
1152 i915_gem_object_put(obj
);
1156 static void lrc_destroy_wa_ctx(struct intel_engine_cs
*engine
)
1158 i915_vma_unpin_and_release(&engine
->wa_ctx
.vma
);
1161 typedef u32
*(*wa_bb_func_t
)(struct intel_engine_cs
*engine
, u32
*batch
);
1163 static int intel_init_workaround_bb(struct intel_engine_cs
*engine
)
1165 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
1166 struct i915_wa_ctx_bb
*wa_bb
[2] = { &wa_ctx
->indirect_ctx
,
1168 wa_bb_func_t wa_bb_fn
[2];
1170 void *batch
, *batch_ptr
;
1174 if (WARN_ON(engine
->id
!= RCS
|| !engine
->scratch
))
1177 switch (INTEL_GEN(engine
->i915
)) {
1179 wa_bb_fn
[0] = gen9_init_indirectctx_bb
;
1180 wa_bb_fn
[1] = gen9_init_perctx_bb
;
1183 wa_bb_fn
[0] = gen8_init_indirectctx_bb
;
1184 wa_bb_fn
[1] = gen8_init_perctx_bb
;
1187 MISSING_CASE(INTEL_GEN(engine
->i915
));
1191 ret
= lrc_setup_wa_ctx(engine
);
1193 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1197 page
= i915_gem_object_get_dirty_page(wa_ctx
->vma
->obj
, 0);
1198 batch
= batch_ptr
= kmap_atomic(page
);
1201 * Emit the two workaround batch buffers, recording the offset from the
1202 * start of the workaround batch buffer object for each and their
1205 for (i
= 0; i
< ARRAY_SIZE(wa_bb_fn
); i
++) {
1206 wa_bb
[i
]->offset
= batch_ptr
- batch
;
1207 if (WARN_ON(!IS_ALIGNED(wa_bb
[i
]->offset
, CACHELINE_BYTES
))) {
1211 batch_ptr
= wa_bb_fn
[i
](engine
, batch_ptr
);
1212 wa_bb
[i
]->size
= batch_ptr
- (batch
+ wa_bb
[i
]->offset
);
1215 BUG_ON(batch_ptr
- batch
> CTX_WA_BB_OBJ_SIZE
);
1217 kunmap_atomic(batch
);
1219 lrc_destroy_wa_ctx(engine
);
1224 static u8 gtiir
[] = {
1232 static int gen8_init_common_ring(struct intel_engine_cs
*engine
)
1234 struct drm_i915_private
*dev_priv
= engine
->i915
;
1235 struct execlist_port
*port
= engine
->execlist_port
;
1240 ret
= intel_mocs_init_engine(engine
);
1244 intel_engine_reset_breadcrumbs(engine
);
1245 intel_engine_init_hangcheck(engine
);
1247 I915_WRITE(RING_HWSTAM(engine
->mmio_base
), 0xffffffff);
1248 I915_WRITE(RING_MODE_GEN7(engine
),
1249 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1250 I915_WRITE(RING_HWS_PGA(engine
->mmio_base
),
1251 engine
->status_page
.ggtt_offset
);
1252 POSTING_READ(RING_HWS_PGA(engine
->mmio_base
));
1254 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine
->name
);
1256 GEM_BUG_ON(engine
->id
>= ARRAY_SIZE(gtiir
));
1259 * Clear any pending interrupt state.
1261 * We do it twice out of paranoia that some of the IIR are double
1262 * buffered, and if we only reset it once there may still be
1263 * an interrupt pending.
1265 I915_WRITE(GEN8_GT_IIR(gtiir
[engine
->id
]),
1266 GT_CONTEXT_SWITCH_INTERRUPT
<< engine
->irq_shift
);
1267 I915_WRITE(GEN8_GT_IIR(gtiir
[engine
->id
]),
1268 GT_CONTEXT_SWITCH_INTERRUPT
<< engine
->irq_shift
);
1269 clear_bit(ENGINE_IRQ_EXECLIST
, &engine
->irq_posted
);
1271 /* After a GPU reset, we may have requests to replay */
1273 for (n
= 0; n
< ARRAY_SIZE(engine
->execlist_port
); n
++) {
1274 if (!port_isset(&port
[n
]))
1277 DRM_DEBUG_DRIVER("Restarting %s:%d from 0x%x\n",
1279 port_request(&port
[n
])->global_seqno
);
1281 /* Discard the current inflight count */
1282 port_set(&port
[n
], port_request(&port
[n
]));
1286 if (submit
&& !i915
.enable_guc_submission
)
1287 execlists_submit_ports(engine
);
1292 static int gen8_init_render_ring(struct intel_engine_cs
*engine
)
1294 struct drm_i915_private
*dev_priv
= engine
->i915
;
1297 ret
= gen8_init_common_ring(engine
);
1301 /* We need to disable the AsyncFlip performance optimisations in order
1302 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1303 * programmed to '1' on all products.
1305 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1307 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1309 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1311 return init_workarounds_ring(engine
);
1314 static int gen9_init_render_ring(struct intel_engine_cs
*engine
)
1318 ret
= gen8_init_common_ring(engine
);
1322 return init_workarounds_ring(engine
);
1325 static void reset_common_ring(struct intel_engine_cs
*engine
,
1326 struct drm_i915_gem_request
*request
)
1328 struct execlist_port
*port
= engine
->execlist_port
;
1329 struct intel_context
*ce
;
1331 /* If the request was innocent, we leave the request in the ELSP
1332 * and will try to replay it on restarting. The context image may
1333 * have been corrupted by the reset, in which case we may have
1334 * to service a new GPU hang, but more likely we can continue on
1337 * If the request was guilty, we presume the context is corrupt
1338 * and have to at least restore the RING register in the context
1339 * image back to the expected values to skip over the guilty request.
1341 if (!request
|| request
->fence
.error
!= -EIO
)
1344 /* We want a simple context + ring to execute the breadcrumb update.
1345 * We cannot rely on the context being intact across the GPU hang,
1346 * so clear it and rebuild just what we need for the breadcrumb.
1347 * All pending requests for this context will be zapped, and any
1348 * future request will be after userspace has had the opportunity
1349 * to recreate its own state.
1351 ce
= &request
->ctx
->engine
[engine
->id
];
1352 execlists_init_reg_state(ce
->lrc_reg_state
,
1353 request
->ctx
, engine
, ce
->ring
);
1355 /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
1356 ce
->lrc_reg_state
[CTX_RING_BUFFER_START
+1] =
1357 i915_ggtt_offset(ce
->ring
->vma
);
1358 ce
->lrc_reg_state
[CTX_RING_HEAD
+1] = request
->postfix
;
1360 request
->ring
->head
= request
->postfix
;
1361 intel_ring_update_space(request
->ring
);
1363 /* Catch up with any missed context-switch interrupts */
1364 if (request
->ctx
!= port_request(port
)->ctx
) {
1365 i915_gem_request_put(port_request(port
));
1367 memset(&port
[1], 0, sizeof(port
[1]));
1370 GEM_BUG_ON(request
->ctx
!= port_request(port
)->ctx
);
1372 /* Reset WaIdleLiteRestore:bdw,skl as well */
1374 intel_ring_wrap(request
->ring
,
1375 request
->wa_tail
- WA_TAIL_DWORDS
*sizeof(u32
));
1376 assert_ring_tail_valid(request
->ring
, request
->tail
);
1379 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1381 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1382 struct intel_engine_cs
*engine
= req
->engine
;
1383 const int num_lri_cmds
= GEN8_3LVL_PDPES
* 2;
1387 cs
= intel_ring_begin(req
, num_lri_cmds
* 2 + 2);
1391 *cs
++ = MI_LOAD_REGISTER_IMM(num_lri_cmds
);
1392 for (i
= GEN8_3LVL_PDPES
- 1; i
>= 0; i
--) {
1393 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1395 *cs
++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine
, i
));
1396 *cs
++ = upper_32_bits(pd_daddr
);
1397 *cs
++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine
, i
));
1398 *cs
++ = lower_32_bits(pd_daddr
);
1402 intel_ring_advance(req
, cs
);
1407 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1408 u64 offset
, u32 len
,
1409 const unsigned int flags
)
1414 /* Don't rely in hw updating PDPs, specially in lite-restore.
1415 * Ideally, we should set Force PD Restore in ctx descriptor,
1416 * but we can't. Force Restore would be a second option, but
1417 * it is unsafe in case of lite-restore (because the ctx is
1418 * not idle). PML4 is allocated during ppgtt init so this is
1419 * not needed in 48-bit.*/
1420 if (req
->ctx
->ppgtt
&&
1421 (intel_engine_flag(req
->engine
) & req
->ctx
->ppgtt
->pd_dirty_rings
) &&
1422 !i915_vm_is_48bit(&req
->ctx
->ppgtt
->base
) &&
1423 !intel_vgpu_active(req
->i915
)) {
1424 ret
= intel_logical_ring_emit_pdps(req
);
1428 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(req
->engine
);
1431 cs
= intel_ring_begin(req
, 4);
1435 /* FIXME(BDW): Address space and security selectors. */
1436 *cs
++ = MI_BATCH_BUFFER_START_GEN8
|
1437 (flags
& I915_DISPATCH_SECURE
? 0 : BIT(8)) |
1438 (flags
& I915_DISPATCH_RS
? MI_BATCH_RESOURCE_STREAMER
: 0);
1439 *cs
++ = lower_32_bits(offset
);
1440 *cs
++ = upper_32_bits(offset
);
1442 intel_ring_advance(req
, cs
);
1447 static void gen8_logical_ring_enable_irq(struct intel_engine_cs
*engine
)
1449 struct drm_i915_private
*dev_priv
= engine
->i915
;
1450 I915_WRITE_IMR(engine
,
1451 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1452 POSTING_READ_FW(RING_IMR(engine
->mmio_base
));
1455 static void gen8_logical_ring_disable_irq(struct intel_engine_cs
*engine
)
1457 struct drm_i915_private
*dev_priv
= engine
->i915
;
1458 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1461 static int gen8_emit_flush(struct drm_i915_gem_request
*request
, u32 mode
)
1465 cs
= intel_ring_begin(request
, 4);
1469 cmd
= MI_FLUSH_DW
+ 1;
1471 /* We always require a command barrier so that subsequent
1472 * commands, such as breadcrumb interrupts, are strictly ordered
1473 * wrt the contents of the write cache being flushed to memory
1474 * (and thus being coherent from the CPU).
1476 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1478 if (mode
& EMIT_INVALIDATE
) {
1479 cmd
|= MI_INVALIDATE_TLB
;
1480 if (request
->engine
->id
== VCS
)
1481 cmd
|= MI_INVALIDATE_BSD
;
1485 *cs
++ = I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
;
1486 *cs
++ = 0; /* upper addr */
1487 *cs
++ = 0; /* value */
1488 intel_ring_advance(request
, cs
);
1493 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1496 struct intel_engine_cs
*engine
= request
->engine
;
1498 i915_ggtt_offset(engine
->scratch
) + 2 * CACHELINE_BYTES
;
1499 bool vf_flush_wa
= false, dc_flush_wa
= false;
1503 flags
|= PIPE_CONTROL_CS_STALL
;
1505 if (mode
& EMIT_FLUSH
) {
1506 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1507 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1508 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
1509 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
1512 if (mode
& EMIT_INVALIDATE
) {
1513 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1514 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1515 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1516 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1517 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1518 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1519 flags
|= PIPE_CONTROL_QW_WRITE
;
1520 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1523 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1526 if (IS_GEN9(request
->i915
))
1529 /* WaForGAMHang:kbl */
1530 if (IS_KBL_REVID(request
->i915
, 0, KBL_REVID_B0
))
1542 cs
= intel_ring_begin(request
, len
);
1547 cs
= gen8_emit_pipe_control(cs
, 0, 0);
1550 cs
= gen8_emit_pipe_control(cs
, PIPE_CONTROL_DC_FLUSH_ENABLE
,
1553 cs
= gen8_emit_pipe_control(cs
, flags
, scratch_addr
);
1556 cs
= gen8_emit_pipe_control(cs
, PIPE_CONTROL_CS_STALL
, 0);
1558 intel_ring_advance(request
, cs
);
1564 * Reserve space for 2 NOOPs at the end of each request to be
1565 * used as a workaround for not being allowed to do lite
1566 * restore with HEAD==TAIL (WaIdleLiteRestore).
1568 static void gen8_emit_wa_tail(struct drm_i915_gem_request
*request
, u32
*cs
)
1572 request
->wa_tail
= intel_ring_offset(request
, cs
);
1575 static void gen8_emit_breadcrumb(struct drm_i915_gem_request
*request
, u32
*cs
)
1577 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1578 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR
& (1 << 5));
1580 *cs
++ = (MI_FLUSH_DW
+ 1) | MI_FLUSH_DW_OP_STOREDW
;
1581 *cs
++ = intel_hws_seqno_address(request
->engine
) | MI_FLUSH_DW_USE_GTT
;
1583 *cs
++ = request
->global_seqno
;
1584 *cs
++ = MI_USER_INTERRUPT
;
1586 request
->tail
= intel_ring_offset(request
, cs
);
1587 assert_ring_tail_valid(request
->ring
, request
->tail
);
1589 gen8_emit_wa_tail(request
, cs
);
1592 static const int gen8_emit_breadcrumb_sz
= 6 + WA_TAIL_DWORDS
;
1594 static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request
*request
,
1597 /* We're using qword write, seqno should be aligned to 8 bytes. */
1598 BUILD_BUG_ON(I915_GEM_HWS_INDEX
& 1);
1600 /* w/a for post sync ops following a GPGPU operation we
1601 * need a prior CS_STALL, which is emitted by the flush
1602 * following the batch.
1604 *cs
++ = GFX_OP_PIPE_CONTROL(6);
1605 *cs
++ = PIPE_CONTROL_GLOBAL_GTT_IVB
| PIPE_CONTROL_CS_STALL
|
1606 PIPE_CONTROL_QW_WRITE
;
1607 *cs
++ = intel_hws_seqno_address(request
->engine
);
1609 *cs
++ = request
->global_seqno
;
1610 /* We're thrashing one dword of HWS. */
1612 *cs
++ = MI_USER_INTERRUPT
;
1614 request
->tail
= intel_ring_offset(request
, cs
);
1615 assert_ring_tail_valid(request
->ring
, request
->tail
);
1617 gen8_emit_wa_tail(request
, cs
);
1620 static const int gen8_emit_breadcrumb_render_sz
= 8 + WA_TAIL_DWORDS
;
1622 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
1626 ret
= intel_ring_workarounds_emit(req
);
1630 ret
= intel_rcs_context_init_mocs(req
);
1632 * Failing to program the MOCS is non-fatal.The system will not
1633 * run at peak performance. So generate an error and carry on.
1636 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1638 return i915_gem_render_state_emit(req
);
1642 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1643 * @engine: Engine Command Streamer.
1645 void intel_logical_ring_cleanup(struct intel_engine_cs
*engine
)
1647 struct drm_i915_private
*dev_priv
;
1650 * Tasklet cannot be active at this point due intel_mark_active/idle
1651 * so this is just for documentation.
1653 if (WARN_ON(test_bit(TASKLET_STATE_SCHED
, &engine
->irq_tasklet
.state
)))
1654 tasklet_kill(&engine
->irq_tasklet
);
1656 dev_priv
= engine
->i915
;
1658 if (engine
->buffer
) {
1659 WARN_ON((I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
1662 if (engine
->cleanup
)
1663 engine
->cleanup(engine
);
1665 if (engine
->status_page
.vma
) {
1666 i915_gem_object_unpin_map(engine
->status_page
.vma
->obj
);
1667 engine
->status_page
.vma
= NULL
;
1670 intel_engine_cleanup_common(engine
);
1672 lrc_destroy_wa_ctx(engine
);
1673 engine
->i915
= NULL
;
1674 dev_priv
->engine
[engine
->id
] = NULL
;
1678 static void execlists_set_default_submission(struct intel_engine_cs
*engine
)
1680 engine
->submit_request
= execlists_submit_request
;
1681 engine
->schedule
= execlists_schedule
;
1682 engine
->irq_tasklet
.func
= intel_lrc_irq_handler
;
1686 logical_ring_default_vfuncs(struct intel_engine_cs
*engine
)
1688 /* Default vfuncs which can be overriden by each engine. */
1689 engine
->init_hw
= gen8_init_common_ring
;
1690 engine
->reset_hw
= reset_common_ring
;
1692 engine
->context_pin
= execlists_context_pin
;
1693 engine
->context_unpin
= execlists_context_unpin
;
1695 engine
->request_alloc
= execlists_request_alloc
;
1697 engine
->emit_flush
= gen8_emit_flush
;
1698 engine
->emit_breadcrumb
= gen8_emit_breadcrumb
;
1699 engine
->emit_breadcrumb_sz
= gen8_emit_breadcrumb_sz
;
1701 engine
->set_default_submission
= execlists_set_default_submission
;
1703 engine
->irq_enable
= gen8_logical_ring_enable_irq
;
1704 engine
->irq_disable
= gen8_logical_ring_disable_irq
;
1705 engine
->emit_bb_start
= gen8_emit_bb_start
;
1709 logical_ring_default_irqs(struct intel_engine_cs
*engine
)
1711 unsigned shift
= engine
->irq_shift
;
1712 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
<< shift
;
1713 engine
->irq_keep_mask
= GT_CONTEXT_SWITCH_INTERRUPT
<< shift
;
1717 lrc_setup_hws(struct intel_engine_cs
*engine
, struct i915_vma
*vma
)
1719 const int hws_offset
= LRC_PPHWSP_PN
* PAGE_SIZE
;
1722 /* The HWSP is part of the default context object in LRC mode. */
1723 hws
= i915_gem_object_pin_map(vma
->obj
, I915_MAP_WB
);
1725 return PTR_ERR(hws
);
1727 engine
->status_page
.page_addr
= hws
+ hws_offset
;
1728 engine
->status_page
.ggtt_offset
= i915_ggtt_offset(vma
) + hws_offset
;
1729 engine
->status_page
.vma
= vma
;
1735 logical_ring_setup(struct intel_engine_cs
*engine
)
1737 struct drm_i915_private
*dev_priv
= engine
->i915
;
1738 enum forcewake_domains fw_domains
;
1740 intel_engine_setup_common(engine
);
1742 /* Intentionally left blank. */
1743 engine
->buffer
= NULL
;
1745 fw_domains
= intel_uncore_forcewake_for_reg(dev_priv
,
1749 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
1750 RING_CONTEXT_STATUS_PTR(engine
),
1751 FW_REG_READ
| FW_REG_WRITE
);
1753 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
1754 RING_CONTEXT_STATUS_BUF_BASE(engine
),
1757 engine
->fw_domains
= fw_domains
;
1759 tasklet_init(&engine
->irq_tasklet
,
1760 intel_lrc_irq_handler
, (unsigned long)engine
);
1762 logical_ring_default_vfuncs(engine
);
1763 logical_ring_default_irqs(engine
);
1767 logical_ring_init(struct intel_engine_cs
*engine
)
1769 struct i915_gem_context
*dctx
= engine
->i915
->kernel_context
;
1772 ret
= intel_engine_init_common(engine
);
1776 /* And setup the hardware status page. */
1777 ret
= lrc_setup_hws(engine
, dctx
->engine
[engine
->id
].state
);
1779 DRM_ERROR("Failed to set up hws %s: %d\n", engine
->name
, ret
);
1786 intel_logical_ring_cleanup(engine
);
1790 int logical_render_ring_init(struct intel_engine_cs
*engine
)
1792 struct drm_i915_private
*dev_priv
= engine
->i915
;
1795 logical_ring_setup(engine
);
1797 if (HAS_L3_DPF(dev_priv
))
1798 engine
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
1800 /* Override some for render ring. */
1801 if (INTEL_GEN(dev_priv
) >= 9)
1802 engine
->init_hw
= gen9_init_render_ring
;
1804 engine
->init_hw
= gen8_init_render_ring
;
1805 engine
->init_context
= gen8_init_rcs_context
;
1806 engine
->emit_flush
= gen8_emit_flush_render
;
1807 engine
->emit_breadcrumb
= gen8_emit_breadcrumb_render
;
1808 engine
->emit_breadcrumb_sz
= gen8_emit_breadcrumb_render_sz
;
1810 ret
= intel_engine_create_scratch(engine
, PAGE_SIZE
);
1814 ret
= intel_init_workaround_bb(engine
);
1817 * We continue even if we fail to initialize WA batch
1818 * because we only expect rare glitches but nothing
1819 * critical to prevent us from using GPU
1821 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1825 return logical_ring_init(engine
);
1828 int logical_xcs_ring_init(struct intel_engine_cs
*engine
)
1830 logical_ring_setup(engine
);
1832 return logical_ring_init(engine
);
1836 make_rpcs(struct drm_i915_private
*dev_priv
)
1841 * No explicit RPCS request is needed to ensure full
1842 * slice/subslice/EU enablement prior to Gen9.
1844 if (INTEL_GEN(dev_priv
) < 9)
1848 * Starting in Gen9, render power gating can leave
1849 * slice/subslice/EU in a partially enabled state. We
1850 * must make an explicit request through RPCS for full
1853 if (INTEL_INFO(dev_priv
)->sseu
.has_slice_pg
) {
1854 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
1855 rpcs
|= hweight8(INTEL_INFO(dev_priv
)->sseu
.slice_mask
) <<
1856 GEN8_RPCS_S_CNT_SHIFT
;
1857 rpcs
|= GEN8_RPCS_ENABLE
;
1860 if (INTEL_INFO(dev_priv
)->sseu
.has_subslice_pg
) {
1861 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
1862 rpcs
|= hweight8(INTEL_INFO(dev_priv
)->sseu
.subslice_mask
) <<
1863 GEN8_RPCS_SS_CNT_SHIFT
;
1864 rpcs
|= GEN8_RPCS_ENABLE
;
1867 if (INTEL_INFO(dev_priv
)->sseu
.has_eu_pg
) {
1868 rpcs
|= INTEL_INFO(dev_priv
)->sseu
.eu_per_subslice
<<
1869 GEN8_RPCS_EU_MIN_SHIFT
;
1870 rpcs
|= INTEL_INFO(dev_priv
)->sseu
.eu_per_subslice
<<
1871 GEN8_RPCS_EU_MAX_SHIFT
;
1872 rpcs
|= GEN8_RPCS_ENABLE
;
1878 static u32
intel_lr_indirect_ctx_offset(struct intel_engine_cs
*engine
)
1880 u32 indirect_ctx_offset
;
1882 switch (INTEL_GEN(engine
->i915
)) {
1884 MISSING_CASE(INTEL_GEN(engine
->i915
));
1887 indirect_ctx_offset
=
1888 GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
1891 indirect_ctx_offset
=
1892 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
1895 indirect_ctx_offset
=
1896 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
1900 return indirect_ctx_offset
;
1903 static void execlists_init_reg_state(u32
*regs
,
1904 struct i915_gem_context
*ctx
,
1905 struct intel_engine_cs
*engine
,
1906 struct intel_ring
*ring
)
1908 struct drm_i915_private
*dev_priv
= engine
->i915
;
1909 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
?: dev_priv
->mm
.aliasing_ppgtt
;
1910 u32 base
= engine
->mmio_base
;
1911 bool rcs
= engine
->id
== RCS
;
1913 /* A context is actually a big batch buffer with several
1914 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
1915 * values we are setting here are only for the first context restore:
1916 * on a subsequent save, the GPU will recreate this batchbuffer with new
1917 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
1918 * we are not initializing here).
1920 regs
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(rcs
? 14 : 11) |
1921 MI_LRI_FORCE_POSTED
;
1923 CTX_REG(regs
, CTX_CONTEXT_CONTROL
, RING_CONTEXT_CONTROL(engine
),
1924 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
1925 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
1926 (HAS_RESOURCE_STREAMER(dev_priv
) ?
1927 CTX_CTRL_RS_CTX_ENABLE
: 0)));
1928 CTX_REG(regs
, CTX_RING_HEAD
, RING_HEAD(base
), 0);
1929 CTX_REG(regs
, CTX_RING_TAIL
, RING_TAIL(base
), 0);
1930 CTX_REG(regs
, CTX_RING_BUFFER_START
, RING_START(base
), 0);
1931 CTX_REG(regs
, CTX_RING_BUFFER_CONTROL
, RING_CTL(base
),
1932 RING_CTL_SIZE(ring
->size
) | RING_VALID
);
1933 CTX_REG(regs
, CTX_BB_HEAD_U
, RING_BBADDR_UDW(base
), 0);
1934 CTX_REG(regs
, CTX_BB_HEAD_L
, RING_BBADDR(base
), 0);
1935 CTX_REG(regs
, CTX_BB_STATE
, RING_BBSTATE(base
), RING_BB_PPGTT
);
1936 CTX_REG(regs
, CTX_SECOND_BB_HEAD_U
, RING_SBBADDR_UDW(base
), 0);
1937 CTX_REG(regs
, CTX_SECOND_BB_HEAD_L
, RING_SBBADDR(base
), 0);
1938 CTX_REG(regs
, CTX_SECOND_BB_STATE
, RING_SBBSTATE(base
), 0);
1940 CTX_REG(regs
, CTX_BB_PER_CTX_PTR
, RING_BB_PER_CTX_PTR(base
), 0);
1941 CTX_REG(regs
, CTX_RCS_INDIRECT_CTX
, RING_INDIRECT_CTX(base
), 0);
1942 CTX_REG(regs
, CTX_RCS_INDIRECT_CTX_OFFSET
,
1943 RING_INDIRECT_CTX_OFFSET(base
), 0);
1945 if (engine
->wa_ctx
.vma
) {
1946 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
1947 u32 ggtt_offset
= i915_ggtt_offset(wa_ctx
->vma
);
1949 regs
[CTX_RCS_INDIRECT_CTX
+ 1] =
1950 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
) |
1951 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_BYTES
);
1953 regs
[CTX_RCS_INDIRECT_CTX_OFFSET
+ 1] =
1954 intel_lr_indirect_ctx_offset(engine
) << 6;
1956 regs
[CTX_BB_PER_CTX_PTR
+ 1] =
1957 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
) | 0x01;
1961 regs
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED
;
1963 CTX_REG(regs
, CTX_CTX_TIMESTAMP
, RING_CTX_TIMESTAMP(base
), 0);
1964 /* PDP values well be assigned later if needed */
1965 CTX_REG(regs
, CTX_PDP3_UDW
, GEN8_RING_PDP_UDW(engine
, 3), 0);
1966 CTX_REG(regs
, CTX_PDP3_LDW
, GEN8_RING_PDP_LDW(engine
, 3), 0);
1967 CTX_REG(regs
, CTX_PDP2_UDW
, GEN8_RING_PDP_UDW(engine
, 2), 0);
1968 CTX_REG(regs
, CTX_PDP2_LDW
, GEN8_RING_PDP_LDW(engine
, 2), 0);
1969 CTX_REG(regs
, CTX_PDP1_UDW
, GEN8_RING_PDP_UDW(engine
, 1), 0);
1970 CTX_REG(regs
, CTX_PDP1_LDW
, GEN8_RING_PDP_LDW(engine
, 1), 0);
1971 CTX_REG(regs
, CTX_PDP0_UDW
, GEN8_RING_PDP_UDW(engine
, 0), 0);
1972 CTX_REG(regs
, CTX_PDP0_LDW
, GEN8_RING_PDP_LDW(engine
, 0), 0);
1974 if (ppgtt
&& i915_vm_is_48bit(&ppgtt
->base
)) {
1975 /* 64b PPGTT (48bit canonical)
1976 * PDP0_DESCRIPTOR contains the base address to PML4 and
1977 * other PDP Descriptors are ignored.
1979 ASSIGN_CTX_PML4(ppgtt
, regs
);
1983 regs
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
1984 CTX_REG(regs
, CTX_R_PWR_CLK_STATE
, GEN8_R_PWR_CLK_STATE
,
1985 make_rpcs(dev_priv
));
1987 i915_oa_init_reg_state(engine
, ctx
, regs
);
1992 populate_lr_context(struct i915_gem_context
*ctx
,
1993 struct drm_i915_gem_object
*ctx_obj
,
1994 struct intel_engine_cs
*engine
,
1995 struct intel_ring
*ring
)
2000 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
2002 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2006 vaddr
= i915_gem_object_pin_map(ctx_obj
, I915_MAP_WB
);
2007 if (IS_ERR(vaddr
)) {
2008 ret
= PTR_ERR(vaddr
);
2009 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret
);
2012 ctx_obj
->mm
.dirty
= true;
2014 /* The second page of the context object contains some fields which must
2015 * be set up prior to the first execution. */
2017 execlists_init_reg_state(vaddr
+ LRC_STATE_PN
* PAGE_SIZE
,
2020 i915_gem_object_unpin_map(ctx_obj
);
2025 static int execlists_context_deferred_alloc(struct i915_gem_context
*ctx
,
2026 struct intel_engine_cs
*engine
)
2028 struct drm_i915_gem_object
*ctx_obj
;
2029 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2030 struct i915_vma
*vma
;
2031 uint32_t context_size
;
2032 struct intel_ring
*ring
;
2037 context_size
= round_up(engine
->context_size
, I915_GTT_PAGE_SIZE
);
2039 /* One extra page as the sharing data between driver and GuC */
2040 context_size
+= PAGE_SIZE
* LRC_PPHWSP_PN
;
2042 ctx_obj
= i915_gem_object_create(ctx
->i915
, context_size
);
2043 if (IS_ERR(ctx_obj
)) {
2044 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2045 return PTR_ERR(ctx_obj
);
2048 vma
= i915_vma_instance(ctx_obj
, &ctx
->i915
->ggtt
.base
, NULL
);
2051 goto error_deref_obj
;
2054 ring
= intel_engine_create_ring(engine
, ctx
->ring_size
);
2056 ret
= PTR_ERR(ring
);
2057 goto error_deref_obj
;
2060 ret
= populate_lr_context(ctx
, ctx_obj
, engine
, ring
);
2062 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2063 goto error_ring_free
;
2068 ce
->initialised
|= engine
->init_context
== NULL
;
2073 intel_ring_free(ring
);
2075 i915_gem_object_put(ctx_obj
);
2079 void intel_lr_context_resume(struct drm_i915_private
*dev_priv
)
2081 struct intel_engine_cs
*engine
;
2082 struct i915_gem_context
*ctx
;
2083 enum intel_engine_id id
;
2085 /* Because we emit WA_TAIL_DWORDS there may be a disparity
2086 * between our bookkeeping in ce->ring->head and ce->ring->tail and
2087 * that stored in context. As we only write new commands from
2088 * ce->ring->tail onwards, everything before that is junk. If the GPU
2089 * starts reading from its RING_HEAD from the context, it may try to
2090 * execute that junk and die.
2092 * So to avoid that we reset the context images upon resume. For
2093 * simplicity, we just zero everything out.
2095 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
2096 for_each_engine(engine
, dev_priv
, id
) {
2097 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2103 reg
= i915_gem_object_pin_map(ce
->state
->obj
,
2105 if (WARN_ON(IS_ERR(reg
)))
2108 reg
+= LRC_STATE_PN
* PAGE_SIZE
/ sizeof(*reg
);
2109 reg
[CTX_RING_HEAD
+1] = 0;
2110 reg
[CTX_RING_TAIL
+1] = 0;
2112 ce
->state
->obj
->mm
.dirty
= true;
2113 i915_gem_object_unpin_map(ce
->state
->obj
);
2115 intel_ring_reset(ce
->ring
, 0);