2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define CTX_LRI_HEADER_0 0x01
160 #define CTX_CONTEXT_CONTROL 0x02
161 #define CTX_RING_HEAD 0x04
162 #define CTX_RING_TAIL 0x06
163 #define CTX_RING_BUFFER_START 0x08
164 #define CTX_RING_BUFFER_CONTROL 0x0a
165 #define CTX_BB_HEAD_U 0x0c
166 #define CTX_BB_HEAD_L 0x0e
167 #define CTX_BB_STATE 0x10
168 #define CTX_SECOND_BB_HEAD_U 0x12
169 #define CTX_SECOND_BB_HEAD_L 0x14
170 #define CTX_SECOND_BB_STATE 0x16
171 #define CTX_BB_PER_CTX_PTR 0x18
172 #define CTX_RCS_INDIRECT_CTX 0x1a
173 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
174 #define CTX_LRI_HEADER_1 0x21
175 #define CTX_CTX_TIMESTAMP 0x22
176 #define CTX_PDP3_UDW 0x24
177 #define CTX_PDP3_LDW 0x26
178 #define CTX_PDP2_UDW 0x28
179 #define CTX_PDP2_LDW 0x2a
180 #define CTX_PDP1_UDW 0x2c
181 #define CTX_PDP1_LDW 0x2e
182 #define CTX_PDP0_UDW 0x30
183 #define CTX_PDP0_LDW 0x32
184 #define CTX_LRI_HEADER_2 0x41
185 #define CTX_R_PWR_CLK_STATE 0x42
186 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
188 #define GEN8_CTX_VALID (1<<0)
189 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
190 #define GEN8_CTX_FORCE_RESTORE (1<<2)
191 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
192 #define GEN8_CTX_PRIVILEGE (1<<8)
194 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
195 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
196 (reg_state)[(pos)+1] = (val); \
199 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
200 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
201 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
202 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
205 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
206 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
207 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
212 FAULT_AND_HALT
, /* Debug only */
214 FAULT_AND_CONTINUE
/* Unsupported */
216 #define GEN8_CTX_ID_SHIFT 32
217 #define GEN8_CTX_ID_WIDTH 21
218 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
219 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
221 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
222 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
224 static int execlists_context_deferred_alloc(struct i915_gem_context
*ctx
,
225 struct intel_engine_cs
*engine
);
226 static int intel_lr_context_pin(struct i915_gem_context
*ctx
,
227 struct intel_engine_cs
*engine
);
230 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
231 * @dev_priv: i915 device private
232 * @enable_execlists: value of i915.enable_execlists module parameter.
234 * Only certain platforms support Execlists (the prerequisites being
235 * support for Logical Ring Contexts and Aliasing PPGTT or better).
237 * Return: 1 if Execlists is supported and has to be enabled.
239 int intel_sanitize_enable_execlists(struct drm_i915_private
*dev_priv
, int enable_execlists
)
241 /* On platforms with execlist available, vGPU will only
242 * support execlist mode, no ring buffer mode.
244 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv
) && intel_vgpu_active(dev_priv
))
247 if (INTEL_GEN(dev_priv
) >= 9)
250 if (enable_execlists
== 0)
253 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv
) &&
254 USES_PPGTT(dev_priv
) &&
255 i915
.use_mmio_flip
>= 0)
262 logical_ring_init_platform_invariants(struct intel_engine_cs
*engine
)
264 struct drm_i915_private
*dev_priv
= engine
->i915
;
266 if (IS_GEN8(dev_priv
) || IS_GEN9(dev_priv
))
267 engine
->idle_lite_restore_wa
= ~0;
269 engine
->disable_lite_restore_wa
= (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_B0
) ||
270 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) &&
271 (engine
->id
== VCS
|| engine
->id
== VCS2
);
273 engine
->ctx_desc_template
= GEN8_CTX_VALID
;
274 if (IS_GEN8(dev_priv
))
275 engine
->ctx_desc_template
|= GEN8_CTX_L3LLC_COHERENT
;
276 engine
->ctx_desc_template
|= GEN8_CTX_PRIVILEGE
;
278 /* TODO: WaDisableLiteRestore when we start using semaphore
279 * signalling between Command Streamers */
280 /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
282 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
283 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
284 if (engine
->disable_lite_restore_wa
)
285 engine
->ctx_desc_template
|= GEN8_CTX_FORCE_RESTORE
;
289 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
290 * descriptor for a pinned context
291 * @ctx: Context to work on
292 * @engine: Engine the descriptor will be used with
294 * The context descriptor encodes various attributes of a context,
295 * including its GTT address and some flags. Because it's fairly
296 * expensive to calculate, we'll just do it once and cache the result,
297 * which remains valid until the context is unpinned.
299 * This is what a descriptor looks like, from LSB to MSB::
301 * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
302 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
303 * bits 32-52: ctx ID, a globally unique tag
304 * bits 53-54: mbz, reserved for use by hardware
305 * bits 55-63: group ID, currently unused and set to 0
308 intel_lr_context_descriptor_update(struct i915_gem_context
*ctx
,
309 struct intel_engine_cs
*engine
)
311 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
314 BUILD_BUG_ON(MAX_CONTEXT_HW_ID
> (1<<GEN8_CTX_ID_WIDTH
));
316 desc
= ctx
->desc_template
; /* bits 3-4 */
317 desc
|= engine
->ctx_desc_template
; /* bits 0-11 */
318 desc
|= ce
->lrc_vma
->node
.start
+ LRC_PPHWSP_PN
* PAGE_SIZE
;
320 desc
|= (u64
)ctx
->hw_id
<< GEN8_CTX_ID_SHIFT
; /* bits 32-52 */
325 uint64_t intel_lr_context_descriptor(struct i915_gem_context
*ctx
,
326 struct intel_engine_cs
*engine
)
328 return ctx
->engine
[engine
->id
].lrc_desc
;
331 static void execlists_elsp_write(struct drm_i915_gem_request
*rq0
,
332 struct drm_i915_gem_request
*rq1
)
335 struct intel_engine_cs
*engine
= rq0
->engine
;
336 struct drm_i915_private
*dev_priv
= rq0
->i915
;
340 desc
[1] = intel_lr_context_descriptor(rq1
->ctx
, rq1
->engine
);
341 rq1
->elsp_submitted
++;
346 desc
[0] = intel_lr_context_descriptor(rq0
->ctx
, rq0
->engine
);
347 rq0
->elsp_submitted
++;
349 /* You must always write both descriptors in the order below. */
350 I915_WRITE_FW(RING_ELSP(engine
), upper_32_bits(desc
[1]));
351 I915_WRITE_FW(RING_ELSP(engine
), lower_32_bits(desc
[1]));
353 I915_WRITE_FW(RING_ELSP(engine
), upper_32_bits(desc
[0]));
354 /* The context is automatically loaded after the following */
355 I915_WRITE_FW(RING_ELSP(engine
), lower_32_bits(desc
[0]));
357 /* ELSP is a wo register, use another nearby reg for posting */
358 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine
));
362 execlists_update_context_pdps(struct i915_hw_ppgtt
*ppgtt
, u32
*reg_state
)
364 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
365 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
366 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
367 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
370 static void execlists_update_context(struct drm_i915_gem_request
*rq
)
372 struct intel_engine_cs
*engine
= rq
->engine
;
373 struct i915_hw_ppgtt
*ppgtt
= rq
->ctx
->ppgtt
;
374 uint32_t *reg_state
= rq
->ctx
->engine
[engine
->id
].lrc_reg_state
;
376 reg_state
[CTX_RING_TAIL
+1] = rq
->tail
;
378 /* True 32b PPGTT with dynamic page allocation: update PDP
379 * registers and point the unallocated PDPs to scratch page.
380 * PML4 is allocated during ppgtt init, so this is not needed
383 if (ppgtt
&& !USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
384 execlists_update_context_pdps(ppgtt
, reg_state
);
387 static void execlists_submit_requests(struct drm_i915_gem_request
*rq0
,
388 struct drm_i915_gem_request
*rq1
)
390 struct drm_i915_private
*dev_priv
= rq0
->i915
;
391 unsigned int fw_domains
= rq0
->engine
->fw_domains
;
393 execlists_update_context(rq0
);
396 execlists_update_context(rq1
);
398 spin_lock_irq(&dev_priv
->uncore
.lock
);
399 intel_uncore_forcewake_get__locked(dev_priv
, fw_domains
);
401 execlists_elsp_write(rq0
, rq1
);
403 intel_uncore_forcewake_put__locked(dev_priv
, fw_domains
);
404 spin_unlock_irq(&dev_priv
->uncore
.lock
);
407 static inline void execlists_context_status_change(
408 struct drm_i915_gem_request
*rq
,
409 unsigned long status
)
412 * Only used when GVT-g is enabled now. When GVT-g is disabled,
413 * The compiler should eliminate this function as dead-code.
415 if (!IS_ENABLED(CONFIG_DRM_I915_GVT
))
418 atomic_notifier_call_chain(&rq
->ctx
->status_notifier
, status
, rq
);
421 static void execlists_context_unqueue(struct intel_engine_cs
*engine
)
423 struct drm_i915_gem_request
*req0
= NULL
, *req1
= NULL
;
424 struct drm_i915_gem_request
*cursor
, *tmp
;
426 assert_spin_locked(&engine
->execlist_lock
);
429 * If irqs are not active generate a warning as batches that finish
430 * without the irqs may get lost and a GPU Hang may occur.
432 WARN_ON(!intel_irqs_enabled(engine
->i915
));
434 /* Try to read in pairs */
435 list_for_each_entry_safe(cursor
, tmp
, &engine
->execlist_queue
,
439 } else if (req0
->ctx
== cursor
->ctx
) {
440 /* Same ctx: ignore first request, as second request
441 * will update tail past first request's workload */
442 cursor
->elsp_submitted
= req0
->elsp_submitted
;
443 list_del(&req0
->execlist_link
);
444 i915_gem_request_put(req0
);
447 if (IS_ENABLED(CONFIG_DRM_I915_GVT
)) {
449 * req0 (after merged) ctx requires single
450 * submission, stop picking
452 if (req0
->ctx
->execlists_force_single_submission
)
455 * req0 ctx doesn't require single submission,
456 * but next req ctx requires, stop picking
458 if (cursor
->ctx
->execlists_force_single_submission
)
462 WARN_ON(req1
->elsp_submitted
);
470 execlists_context_status_change(req0
, INTEL_CONTEXT_SCHEDULE_IN
);
473 execlists_context_status_change(req1
,
474 INTEL_CONTEXT_SCHEDULE_IN
);
476 if (req0
->elsp_submitted
& engine
->idle_lite_restore_wa
) {
478 * WaIdleLiteRestore: make sure we never cause a lite restore
481 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we
482 * resubmit the request. See gen8_emit_request() for where we
483 * prepare the padding after the end of the request.
485 struct intel_ringbuffer
*ringbuf
;
487 ringbuf
= req0
->ctx
->engine
[engine
->id
].ringbuf
;
489 req0
->tail
&= ringbuf
->size
- 1;
492 execlists_submit_requests(req0
, req1
);
496 execlists_check_remove_request(struct intel_engine_cs
*engine
, u32 ctx_id
)
498 struct drm_i915_gem_request
*head_req
;
500 assert_spin_locked(&engine
->execlist_lock
);
502 head_req
= list_first_entry_or_null(&engine
->execlist_queue
,
503 struct drm_i915_gem_request
,
506 if (WARN_ON(!head_req
|| (head_req
->ctx_hw_id
!= ctx_id
)))
509 WARN(head_req
->elsp_submitted
== 0, "Never submitted head request\n");
511 if (--head_req
->elsp_submitted
> 0)
514 execlists_context_status_change(head_req
, INTEL_CONTEXT_SCHEDULE_OUT
);
516 list_del(&head_req
->execlist_link
);
517 i915_gem_request_put(head_req
);
523 get_context_status(struct intel_engine_cs
*engine
, unsigned int read_pointer
,
526 struct drm_i915_private
*dev_priv
= engine
->i915
;
529 read_pointer
%= GEN8_CSB_ENTRIES
;
531 status
= I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine
, read_pointer
));
533 if (status
& GEN8_CTX_STATUS_IDLE_ACTIVE
)
536 *context_id
= I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine
,
543 * Check the unread Context Status Buffers and manage the submission of new
544 * contexts to the ELSP accordingly.
546 static void intel_lrc_irq_handler(unsigned long data
)
548 struct intel_engine_cs
*engine
= (struct intel_engine_cs
*)data
;
549 struct drm_i915_private
*dev_priv
= engine
->i915
;
551 unsigned int read_pointer
, write_pointer
;
552 u32 csb
[GEN8_CSB_ENTRIES
][2];
553 unsigned int csb_read
= 0, i
;
554 unsigned int submit_contexts
= 0;
556 intel_uncore_forcewake_get(dev_priv
, engine
->fw_domains
);
558 status_pointer
= I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine
));
560 read_pointer
= engine
->next_context_status_buffer
;
561 write_pointer
= GEN8_CSB_WRITE_PTR(status_pointer
);
562 if (read_pointer
> write_pointer
)
563 write_pointer
+= GEN8_CSB_ENTRIES
;
565 while (read_pointer
< write_pointer
) {
566 if (WARN_ON_ONCE(csb_read
== GEN8_CSB_ENTRIES
))
568 csb
[csb_read
][0] = get_context_status(engine
, ++read_pointer
,
573 engine
->next_context_status_buffer
= write_pointer
% GEN8_CSB_ENTRIES
;
575 /* Update the read pointer to the old write pointer. Manual ringbuffer
576 * management ftw </sarcasm> */
577 I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine
),
578 _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK
,
579 engine
->next_context_status_buffer
<< 8));
581 intel_uncore_forcewake_put(dev_priv
, engine
->fw_domains
);
583 spin_lock(&engine
->execlist_lock
);
585 for (i
= 0; i
< csb_read
; i
++) {
586 if (unlikely(csb
[i
][0] & GEN8_CTX_STATUS_PREEMPTED
)) {
587 if (csb
[i
][0] & GEN8_CTX_STATUS_LITE_RESTORE
) {
588 if (execlists_check_remove_request(engine
, csb
[i
][1]))
589 WARN(1, "Lite Restored request removed from queue\n");
591 WARN(1, "Preemption without Lite Restore\n");
594 if (csb
[i
][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE
|
595 GEN8_CTX_STATUS_ELEMENT_SWITCH
))
597 execlists_check_remove_request(engine
, csb
[i
][1]);
600 if (submit_contexts
) {
601 if (!engine
->disable_lite_restore_wa
||
602 (csb
[i
][0] & GEN8_CTX_STATUS_ACTIVE_IDLE
))
603 execlists_context_unqueue(engine
);
606 spin_unlock(&engine
->execlist_lock
);
608 if (unlikely(submit_contexts
> 2))
609 DRM_ERROR("More than two context complete events?\n");
612 static void execlists_context_queue(struct drm_i915_gem_request
*request
)
614 struct intel_engine_cs
*engine
= request
->engine
;
615 struct drm_i915_gem_request
*cursor
;
616 int num_elements
= 0;
618 spin_lock_bh(&engine
->execlist_lock
);
620 list_for_each_entry(cursor
, &engine
->execlist_queue
, execlist_link
)
621 if (++num_elements
> 2)
624 if (num_elements
> 2) {
625 struct drm_i915_gem_request
*tail_req
;
627 tail_req
= list_last_entry(&engine
->execlist_queue
,
628 struct drm_i915_gem_request
,
631 if (request
->ctx
== tail_req
->ctx
) {
632 WARN(tail_req
->elsp_submitted
!= 0,
633 "More than 2 already-submitted reqs queued\n");
634 list_del(&tail_req
->execlist_link
);
635 i915_gem_request_put(tail_req
);
639 i915_gem_request_get(request
);
640 list_add_tail(&request
->execlist_link
, &engine
->execlist_queue
);
641 request
->ctx_hw_id
= request
->ctx
->hw_id
;
642 if (num_elements
== 0)
643 execlists_context_unqueue(engine
);
645 spin_unlock_bh(&engine
->execlist_lock
);
648 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
650 struct intel_engine_cs
*engine
= req
->engine
;
651 uint32_t flush_domains
;
655 if (engine
->gpu_caches_dirty
)
656 flush_domains
= I915_GEM_GPU_DOMAINS
;
658 ret
= engine
->emit_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
662 engine
->gpu_caches_dirty
= false;
666 static int execlists_move_to_gpu(struct drm_i915_gem_request
*req
,
667 struct list_head
*vmas
)
669 const unsigned other_rings
= ~intel_engine_flag(req
->engine
);
670 struct i915_vma
*vma
;
671 uint32_t flush_domains
= 0;
672 bool flush_chipset
= false;
675 list_for_each_entry(vma
, vmas
, exec_list
) {
676 struct drm_i915_gem_object
*obj
= vma
->obj
;
678 if (obj
->active
& other_rings
) {
679 ret
= i915_gem_object_sync(obj
, req
->engine
, &req
);
684 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
685 flush_chipset
|= i915_gem_clflush_object(obj
, false);
687 flush_domains
|= obj
->base
.write_domain
;
690 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
693 /* Unconditionally invalidate gpu caches and ensure that we do flush
694 * any residual writes from the previous batch.
696 return logical_ring_invalidate_all_caches(req
);
699 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
701 struct intel_engine_cs
*engine
= request
->engine
;
702 struct intel_context
*ce
= &request
->ctx
->engine
[engine
->id
];
705 /* Flush enough space to reduce the likelihood of waiting after
706 * we start building the request - in which case we will just
707 * have to repeat work.
709 request
->reserved_space
+= EXECLISTS_REQUEST_SIZE
;
712 ret
= execlists_context_deferred_alloc(request
->ctx
, engine
);
717 request
->ringbuf
= ce
->ringbuf
;
719 if (i915
.enable_guc_submission
) {
721 * Check that the GuC has space for the request before
722 * going any further, as the i915_add_request() call
723 * later on mustn't fail ...
725 ret
= i915_guc_wq_check_space(request
);
730 ret
= intel_lr_context_pin(request
->ctx
, engine
);
734 ret
= intel_ring_begin(request
, 0);
738 if (!ce
->initialised
) {
739 ret
= engine
->init_context(request
);
743 ce
->initialised
= true;
746 /* Note that after this point, we have committed to using
747 * this request as it is being used to both track the
748 * state of engine initialisation and liveness of the
749 * golden renderstate above. Think twice before you try
750 * to cancel/unwind this request now.
753 request
->reserved_space
-= EXECLISTS_REQUEST_SIZE
;
757 intel_lr_context_unpin(request
->ctx
, engine
);
762 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
763 * @request: Request to advance the logical ringbuffer of.
765 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
766 * really happens during submission is that the context and current tail will be placed
767 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
768 * point, the tail *inside* the context is updated and the ELSP written to.
771 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request
*request
)
773 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
774 struct intel_engine_cs
*engine
= request
->engine
;
776 intel_logical_ring_advance(ringbuf
);
777 request
->tail
= ringbuf
->tail
;
780 * Here we add two extra NOOPs as padding to avoid
781 * lite restore of a context with HEAD==TAIL.
783 * Caller must reserve WA_TAIL_DWORDS for us!
785 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
786 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
787 intel_logical_ring_advance(ringbuf
);
789 /* We keep the previous context alive until we retire the following
790 * request. This ensures that any the context object is still pinned
791 * for any residual writes the HW makes into it on the context switch
792 * into the next object following the breadcrumb. Otherwise, we may
793 * retire the context too early.
795 request
->previous_context
= engine
->last_context
;
796 engine
->last_context
= request
->ctx
;
798 if (i915
.enable_guc_submission
)
799 i915_guc_submit(request
);
801 execlists_context_queue(request
);
807 * intel_execlists_submission() - submit a batchbuffer for execution, Execlists style
808 * @params: execbuffer call parameters.
809 * @args: execbuffer call arguments.
810 * @vmas: list of vmas.
812 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
813 * away the submission details of the execbuffer ioctl call.
815 * Return: non-zero if the submission fails.
817 int intel_execlists_submission(struct i915_execbuffer_params
*params
,
818 struct drm_i915_gem_execbuffer2
*args
,
819 struct list_head
*vmas
)
821 struct drm_device
*dev
= params
->dev
;
822 struct intel_engine_cs
*engine
= params
->engine
;
823 struct drm_i915_private
*dev_priv
= to_i915(dev
);
824 struct intel_ringbuffer
*ringbuf
= params
->ctx
->engine
[engine
->id
].ringbuf
;
830 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
831 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
832 switch (instp_mode
) {
833 case I915_EXEC_CONSTANTS_REL_GENERAL
:
834 case I915_EXEC_CONSTANTS_ABSOLUTE
:
835 case I915_EXEC_CONSTANTS_REL_SURFACE
:
836 if (instp_mode
!= 0 && engine
!= &dev_priv
->engine
[RCS
]) {
837 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
841 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
842 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
843 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
847 /* The HW changed the meaning on this bit on gen6 */
848 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
852 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
856 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
857 DRM_DEBUG("sol reset is gen7 only\n");
861 ret
= execlists_move_to_gpu(params
->request
, vmas
);
865 if (engine
== &dev_priv
->engine
[RCS
] &&
866 instp_mode
!= dev_priv
->relative_constants_mode
) {
867 ret
= intel_ring_begin(params
->request
, 4);
871 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
872 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
873 intel_logical_ring_emit_reg(ringbuf
, INSTPM
);
874 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
875 intel_logical_ring_advance(ringbuf
);
877 dev_priv
->relative_constants_mode
= instp_mode
;
880 exec_start
= params
->batch_obj_vm_offset
+
881 args
->batch_start_offset
;
883 ret
= engine
->emit_bb_start(params
->request
, exec_start
, params
->dispatch_flags
);
887 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
889 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
894 void intel_execlists_cancel_requests(struct intel_engine_cs
*engine
)
896 struct drm_i915_gem_request
*req
, *tmp
;
897 LIST_HEAD(cancel_list
);
899 WARN_ON(!mutex_is_locked(&engine
->i915
->drm
.struct_mutex
));
901 spin_lock_bh(&engine
->execlist_lock
);
902 list_replace_init(&engine
->execlist_queue
, &cancel_list
);
903 spin_unlock_bh(&engine
->execlist_lock
);
905 list_for_each_entry_safe(req
, tmp
, &cancel_list
, execlist_link
) {
906 list_del(&req
->execlist_link
);
907 i915_gem_request_put(req
);
911 void intel_logical_ring_stop(struct intel_engine_cs
*engine
)
913 struct drm_i915_private
*dev_priv
= engine
->i915
;
916 if (!intel_engine_initialized(engine
))
919 ret
= intel_engine_idle(engine
);
921 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
924 /* TODO: Is this correct with Execlists enabled? */
925 I915_WRITE_MODE(engine
, _MASKED_BIT_ENABLE(STOP_RING
));
926 if (intel_wait_for_register(dev_priv
,
927 RING_MI_MODE(engine
->mmio_base
),
928 MODE_IDLE
, MODE_IDLE
,
930 DRM_ERROR("%s :timed out trying to stop ring\n", engine
->name
);
933 I915_WRITE_MODE(engine
, _MASKED_BIT_DISABLE(STOP_RING
));
936 int logical_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
938 struct intel_engine_cs
*engine
= req
->engine
;
941 if (!engine
->gpu_caches_dirty
)
944 ret
= engine
->emit_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
948 engine
->gpu_caches_dirty
= false;
952 static int intel_lr_context_pin(struct i915_gem_context
*ctx
,
953 struct intel_engine_cs
*engine
)
955 struct drm_i915_private
*dev_priv
= ctx
->i915
;
956 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
961 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
966 ret
= i915_gem_obj_ggtt_pin(ce
->state
, GEN8_LR_CONTEXT_ALIGN
,
967 PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
);
971 vaddr
= i915_gem_object_pin_map(ce
->state
);
973 ret
= PTR_ERR(vaddr
);
977 lrc_reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
979 ret
= intel_pin_and_map_ringbuffer_obj(dev_priv
, ce
->ringbuf
);
983 ce
->lrc_vma
= i915_gem_obj_to_ggtt(ce
->state
);
984 intel_lr_context_descriptor_update(ctx
, engine
);
986 lrc_reg_state
[CTX_RING_BUFFER_START
+1] = ce
->ringbuf
->vma
->node
.start
;
987 ce
->lrc_reg_state
= lrc_reg_state
;
988 ce
->state
->dirty
= true;
990 /* Invalidate GuC TLB. */
991 if (i915
.enable_guc_submission
)
992 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
994 i915_gem_context_get(ctx
);
998 i915_gem_object_unpin_map(ce
->state
);
1000 i915_gem_object_ggtt_unpin(ce
->state
);
1006 void intel_lr_context_unpin(struct i915_gem_context
*ctx
,
1007 struct intel_engine_cs
*engine
)
1009 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
1011 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
1012 GEM_BUG_ON(ce
->pin_count
== 0);
1014 if (--ce
->pin_count
)
1017 intel_unpin_ringbuffer_obj(ce
->ringbuf
);
1019 i915_gem_object_unpin_map(ce
->state
);
1020 i915_gem_object_ggtt_unpin(ce
->state
);
1024 ce
->lrc_reg_state
= NULL
;
1026 i915_gem_context_put(ctx
);
1029 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
1032 struct intel_engine_cs
*engine
= req
->engine
;
1033 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1034 struct i915_workarounds
*w
= &req
->i915
->workarounds
;
1039 engine
->gpu_caches_dirty
= true;
1040 ret
= logical_ring_flush_all_caches(req
);
1044 ret
= intel_ring_begin(req
, w
->count
* 2 + 2);
1048 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(w
->count
));
1049 for (i
= 0; i
< w
->count
; i
++) {
1050 intel_logical_ring_emit_reg(ringbuf
, w
->reg
[i
].addr
);
1051 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].value
);
1053 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1055 intel_logical_ring_advance(ringbuf
);
1057 engine
->gpu_caches_dirty
= true;
1058 ret
= logical_ring_flush_all_caches(req
);
1065 #define wa_ctx_emit(batch, index, cmd) \
1067 int __index = (index)++; \
1068 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1071 batch[__index] = (cmd); \
1074 #define wa_ctx_emit_reg(batch, index, reg) \
1075 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
1078 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1079 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1080 * but there is a slight complication as this is applied in WA batch where the
1081 * values are only initialized once so we cannot take register value at the
1082 * beginning and reuse it further; hence we save its value to memory, upload a
1083 * constant value with bit21 set and then we restore it back with the saved value.
1084 * To simplify the WA, a constant value is formed by using the default value
1085 * of this register. This shouldn't be a problem because we are only modifying
1086 * it for a short period and this batch in non-premptible. We can ofcourse
1087 * use additional instructions that read the actual value of the register
1088 * at that time and set our bit of interest but it makes the WA complicated.
1090 * This WA is also required for Gen9 so extracting as a function avoids
1093 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*engine
,
1097 uint32_t l3sqc4_flush
= (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
);
1100 * WaDisableLSQCROPERFforOCL:skl,kbl
1101 * This WA is implemented in skl_init_clock_gating() but since
1102 * this batch updates GEN8_L3SQCREG4 with default value we need to
1103 * set this bit here to retain the WA during flush.
1105 if (IS_SKL_REVID(engine
->i915
, 0, SKL_REVID_E0
) ||
1106 IS_KBL_REVID(engine
->i915
, 0, KBL_REVID_E0
))
1107 l3sqc4_flush
|= GEN8_LQSC_RO_PERF_DIS
;
1109 wa_ctx_emit(batch
, index
, (MI_STORE_REGISTER_MEM_GEN8
|
1110 MI_SRM_LRM_GLOBAL_GTT
));
1111 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1112 wa_ctx_emit(batch
, index
, engine
->scratch
.gtt_offset
+ 256);
1113 wa_ctx_emit(batch
, index
, 0);
1115 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1116 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1117 wa_ctx_emit(batch
, index
, l3sqc4_flush
);
1119 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1120 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_CS_STALL
|
1121 PIPE_CONTROL_DC_FLUSH_ENABLE
));
1122 wa_ctx_emit(batch
, index
, 0);
1123 wa_ctx_emit(batch
, index
, 0);
1124 wa_ctx_emit(batch
, index
, 0);
1125 wa_ctx_emit(batch
, index
, 0);
1127 wa_ctx_emit(batch
, index
, (MI_LOAD_REGISTER_MEM_GEN8
|
1128 MI_SRM_LRM_GLOBAL_GTT
));
1129 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1130 wa_ctx_emit(batch
, index
, engine
->scratch
.gtt_offset
+ 256);
1131 wa_ctx_emit(batch
, index
, 0);
1136 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb
*wa_ctx
,
1138 uint32_t start_alignment
)
1140 return wa_ctx
->offset
= ALIGN(offset
, start_alignment
);
1143 static inline int wa_ctx_end(struct i915_wa_ctx_bb
*wa_ctx
,
1145 uint32_t size_alignment
)
1147 wa_ctx
->size
= offset
- wa_ctx
->offset
;
1149 WARN(wa_ctx
->size
% size_alignment
,
1150 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1151 wa_ctx
->size
, size_alignment
);
1156 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1157 * initialized at the beginning and shared across all contexts but this field
1158 * helps us to have multiple batches at different offsets and select them based
1159 * on a criteria. At the moment this batch always start at the beginning of the page
1160 * and at this point we don't have multiple wa_ctx batch buffers.
1162 * The number of WA applied are not known at the beginning; we use this field
1163 * to return the no of DWORDS written.
1165 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1166 * so it adds NOOPs as padding to make it cacheline aligned.
1167 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1168 * makes a complete batch buffer.
1170 static int gen8_init_indirectctx_bb(struct intel_engine_cs
*engine
,
1171 struct i915_wa_ctx_bb
*wa_ctx
,
1175 uint32_t scratch_addr
;
1176 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1178 /* WaDisableCtxRestoreArbitration:bdw,chv */
1179 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1181 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1182 if (IS_BROADWELL(engine
->i915
)) {
1183 int rc
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
1189 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1190 /* Actual scratch location is at 128 bytes offset */
1191 scratch_addr
= engine
->scratch
.gtt_offset
+ 2*CACHELINE_BYTES
;
1193 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1194 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1195 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1196 PIPE_CONTROL_CS_STALL
|
1197 PIPE_CONTROL_QW_WRITE
));
1198 wa_ctx_emit(batch
, index
, scratch_addr
);
1199 wa_ctx_emit(batch
, index
, 0);
1200 wa_ctx_emit(batch
, index
, 0);
1201 wa_ctx_emit(batch
, index
, 0);
1203 /* Pad to end of cacheline */
1204 while (index
% CACHELINE_DWORDS
)
1205 wa_ctx_emit(batch
, index
, MI_NOOP
);
1208 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1209 * execution depends on the length specified in terms of cache lines
1210 * in the register CTX_RCS_INDIRECT_CTX
1213 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1217 * This batch is started immediately after indirect_ctx batch. Since we ensure
1218 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1220 * The number of DWORDS written are returned using this field.
1222 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1223 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1225 static int gen8_init_perctx_bb(struct intel_engine_cs
*engine
,
1226 struct i915_wa_ctx_bb
*wa_ctx
,
1230 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1232 /* WaDisableCtxRestoreArbitration:bdw,chv */
1233 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1235 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1237 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1240 static int gen9_init_indirectctx_bb(struct intel_engine_cs
*engine
,
1241 struct i915_wa_ctx_bb
*wa_ctx
,
1246 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1248 /* WaDisableCtxRestoreArbitration:skl,bxt */
1249 if (IS_SKL_REVID(engine
->i915
, 0, SKL_REVID_D0
) ||
1250 IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
))
1251 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1253 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1254 ret
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
1259 /* WaClearSlmSpaceAtContextSwitch:kbl */
1260 /* Actual scratch location is at 128 bytes offset */
1261 if (IS_KBL_REVID(engine
->i915
, 0, KBL_REVID_A0
)) {
1262 uint32_t scratch_addr
1263 = engine
->scratch
.gtt_offset
+ 2*CACHELINE_BYTES
;
1265 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1266 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1267 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1268 PIPE_CONTROL_CS_STALL
|
1269 PIPE_CONTROL_QW_WRITE
));
1270 wa_ctx_emit(batch
, index
, scratch_addr
);
1271 wa_ctx_emit(batch
, index
, 0);
1272 wa_ctx_emit(batch
, index
, 0);
1273 wa_ctx_emit(batch
, index
, 0);
1276 /* WaMediaPoolStateCmdInWABB:bxt */
1277 if (HAS_POOLED_EU(engine
->i915
)) {
1279 * EU pool configuration is setup along with golden context
1280 * during context initialization. This value depends on
1281 * device type (2x6 or 3x6) and needs to be updated based
1282 * on which subslice is disabled especially for 2x6
1283 * devices, however it is safe to load default
1284 * configuration of 3x6 device instead of masking off
1285 * corresponding bits because HW ignores bits of a disabled
1286 * subslice and drops down to appropriate config. Please
1287 * see render_state_setup() in i915_gem_render_state.c for
1288 * possible configurations, to avoid duplication they are
1289 * not shown here again.
1291 u32 eu_pool_config
= 0x00777000;
1292 wa_ctx_emit(batch
, index
, GEN9_MEDIA_POOL_STATE
);
1293 wa_ctx_emit(batch
, index
, GEN9_MEDIA_POOL_ENABLE
);
1294 wa_ctx_emit(batch
, index
, eu_pool_config
);
1295 wa_ctx_emit(batch
, index
, 0);
1296 wa_ctx_emit(batch
, index
, 0);
1297 wa_ctx_emit(batch
, index
, 0);
1300 /* Pad to end of cacheline */
1301 while (index
% CACHELINE_DWORDS
)
1302 wa_ctx_emit(batch
, index
, MI_NOOP
);
1304 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1307 static int gen9_init_perctx_bb(struct intel_engine_cs
*engine
,
1308 struct i915_wa_ctx_bb
*wa_ctx
,
1312 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1314 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1315 if (IS_SKL_REVID(engine
->i915
, 0, SKL_REVID_B0
) ||
1316 IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
)) {
1317 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1318 wa_ctx_emit_reg(batch
, index
, GEN9_SLICE_COMMON_ECO_CHICKEN0
);
1319 wa_ctx_emit(batch
, index
,
1320 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING
));
1321 wa_ctx_emit(batch
, index
, MI_NOOP
);
1324 /* WaClearTdlStateAckDirtyBits:bxt */
1325 if (IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_B0
)) {
1326 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(4));
1328 wa_ctx_emit_reg(batch
, index
, GEN8_STATE_ACK
);
1329 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1331 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE1
);
1332 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1334 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE2
);
1335 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1337 wa_ctx_emit_reg(batch
, index
, GEN7_ROW_CHICKEN2
);
1338 /* dummy write to CS, mask bits are 0 to ensure the register is not modified */
1339 wa_ctx_emit(batch
, index
, 0x0);
1340 wa_ctx_emit(batch
, index
, MI_NOOP
);
1343 /* WaDisableCtxRestoreArbitration:skl,bxt */
1344 if (IS_SKL_REVID(engine
->i915
, 0, SKL_REVID_D0
) ||
1345 IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
))
1346 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1348 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1350 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1353 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs
*engine
, u32 size
)
1357 engine
->wa_ctx
.obj
= i915_gem_object_create(&engine
->i915
->drm
,
1359 if (IS_ERR(engine
->wa_ctx
.obj
)) {
1360 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1361 ret
= PTR_ERR(engine
->wa_ctx
.obj
);
1362 engine
->wa_ctx
.obj
= NULL
;
1366 ret
= i915_gem_obj_ggtt_pin(engine
->wa_ctx
.obj
, PAGE_SIZE
, 0);
1368 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1370 i915_gem_object_put(engine
->wa_ctx
.obj
);
1377 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs
*engine
)
1379 if (engine
->wa_ctx
.obj
) {
1380 i915_gem_object_ggtt_unpin(engine
->wa_ctx
.obj
);
1381 i915_gem_object_put(engine
->wa_ctx
.obj
);
1382 engine
->wa_ctx
.obj
= NULL
;
1386 static int intel_init_workaround_bb(struct intel_engine_cs
*engine
)
1392 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
1394 WARN_ON(engine
->id
!= RCS
);
1396 /* update this when WA for higher Gen are added */
1397 if (INTEL_GEN(engine
->i915
) > 9) {
1398 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1399 INTEL_GEN(engine
->i915
));
1403 /* some WA perform writes to scratch page, ensure it is valid */
1404 if (engine
->scratch
.obj
== NULL
) {
1405 DRM_ERROR("scratch page not allocated for %s\n", engine
->name
);
1409 ret
= lrc_setup_wa_ctx_obj(engine
, PAGE_SIZE
);
1411 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1415 page
= i915_gem_object_get_dirty_page(wa_ctx
->obj
, 0);
1416 batch
= kmap_atomic(page
);
1419 if (IS_GEN8(engine
->i915
)) {
1420 ret
= gen8_init_indirectctx_bb(engine
,
1421 &wa_ctx
->indirect_ctx
,
1427 ret
= gen8_init_perctx_bb(engine
,
1433 } else if (IS_GEN9(engine
->i915
)) {
1434 ret
= gen9_init_indirectctx_bb(engine
,
1435 &wa_ctx
->indirect_ctx
,
1441 ret
= gen9_init_perctx_bb(engine
,
1450 kunmap_atomic(batch
);
1452 lrc_destroy_wa_ctx_obj(engine
);
1457 static void lrc_init_hws(struct intel_engine_cs
*engine
)
1459 struct drm_i915_private
*dev_priv
= engine
->i915
;
1461 I915_WRITE(RING_HWS_PGA(engine
->mmio_base
),
1462 (u32
)engine
->status_page
.gfx_addr
);
1463 POSTING_READ(RING_HWS_PGA(engine
->mmio_base
));
1466 static int gen8_init_common_ring(struct intel_engine_cs
*engine
)
1468 struct drm_i915_private
*dev_priv
= engine
->i915
;
1469 unsigned int next_context_status_buffer_hw
;
1471 lrc_init_hws(engine
);
1473 I915_WRITE_IMR(engine
,
1474 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1475 I915_WRITE(RING_HWSTAM(engine
->mmio_base
), 0xffffffff);
1477 I915_WRITE(RING_MODE_GEN7(engine
),
1478 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1479 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1480 POSTING_READ(RING_MODE_GEN7(engine
));
1483 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1484 * zero, we need to read the write pointer from hardware and use its
1485 * value because "this register is power context save restored".
1486 * Effectively, these states have been observed:
1488 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1489 * BDW | CSB regs not reset | CSB regs reset |
1490 * CHT | CSB regs not reset | CSB regs not reset |
1494 next_context_status_buffer_hw
=
1495 GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine
)));
1498 * When the CSB registers are reset (also after power-up / gpu reset),
1499 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1500 * this special case, so the first element read is CSB[0].
1502 if (next_context_status_buffer_hw
== GEN8_CSB_PTR_MASK
)
1503 next_context_status_buffer_hw
= (GEN8_CSB_ENTRIES
- 1);
1505 engine
->next_context_status_buffer
= next_context_status_buffer_hw
;
1506 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine
->name
);
1508 intel_engine_init_hangcheck(engine
);
1510 return intel_mocs_init_engine(engine
);
1513 static int gen8_init_render_ring(struct intel_engine_cs
*engine
)
1515 struct drm_i915_private
*dev_priv
= engine
->i915
;
1518 ret
= gen8_init_common_ring(engine
);
1522 /* We need to disable the AsyncFlip performance optimisations in order
1523 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1524 * programmed to '1' on all products.
1526 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1528 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1530 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1532 return init_workarounds_ring(engine
);
1535 static int gen9_init_render_ring(struct intel_engine_cs
*engine
)
1539 ret
= gen8_init_common_ring(engine
);
1543 return init_workarounds_ring(engine
);
1546 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1548 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1549 struct intel_engine_cs
*engine
= req
->engine
;
1550 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1551 const int num_lri_cmds
= GEN8_LEGACY_PDPES
* 2;
1554 ret
= intel_ring_begin(req
, num_lri_cmds
* 2 + 2);
1558 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(num_lri_cmds
));
1559 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
1560 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1562 intel_logical_ring_emit_reg(ringbuf
,
1563 GEN8_RING_PDP_UDW(engine
, i
));
1564 intel_logical_ring_emit(ringbuf
, upper_32_bits(pd_daddr
));
1565 intel_logical_ring_emit_reg(ringbuf
,
1566 GEN8_RING_PDP_LDW(engine
, i
));
1567 intel_logical_ring_emit(ringbuf
, lower_32_bits(pd_daddr
));
1570 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1571 intel_logical_ring_advance(ringbuf
);
1576 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1577 u64 offset
, unsigned dispatch_flags
)
1579 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1580 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1583 /* Don't rely in hw updating PDPs, specially in lite-restore.
1584 * Ideally, we should set Force PD Restore in ctx descriptor,
1585 * but we can't. Force Restore would be a second option, but
1586 * it is unsafe in case of lite-restore (because the ctx is
1587 * not idle). PML4 is allocated during ppgtt init so this is
1588 * not needed in 48-bit.*/
1589 if (req
->ctx
->ppgtt
&&
1590 (intel_engine_flag(req
->engine
) & req
->ctx
->ppgtt
->pd_dirty_rings
)) {
1591 if (!USES_FULL_48BIT_PPGTT(req
->i915
) &&
1592 !intel_vgpu_active(req
->i915
)) {
1593 ret
= intel_logical_ring_emit_pdps(req
);
1598 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(req
->engine
);
1601 ret
= intel_ring_begin(req
, 4);
1605 /* FIXME(BDW): Address space and security selectors. */
1606 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
|
1608 (dispatch_flags
& I915_DISPATCH_RS
?
1609 MI_BATCH_RESOURCE_STREAMER
: 0));
1610 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1611 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1612 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1613 intel_logical_ring_advance(ringbuf
);
1618 static void gen8_logical_ring_enable_irq(struct intel_engine_cs
*engine
)
1620 struct drm_i915_private
*dev_priv
= engine
->i915
;
1621 I915_WRITE_IMR(engine
,
1622 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1623 POSTING_READ_FW(RING_IMR(engine
->mmio_base
));
1626 static void gen8_logical_ring_disable_irq(struct intel_engine_cs
*engine
)
1628 struct drm_i915_private
*dev_priv
= engine
->i915
;
1629 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1632 static int gen8_emit_flush(struct drm_i915_gem_request
*request
,
1633 u32 invalidate_domains
,
1636 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1637 struct intel_engine_cs
*engine
= ringbuf
->engine
;
1638 struct drm_i915_private
*dev_priv
= request
->i915
;
1642 ret
= intel_ring_begin(request
, 4);
1646 cmd
= MI_FLUSH_DW
+ 1;
1648 /* We always require a command barrier so that subsequent
1649 * commands, such as breadcrumb interrupts, are strictly ordered
1650 * wrt the contents of the write cache being flushed to memory
1651 * (and thus being coherent from the CPU).
1653 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1655 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
) {
1656 cmd
|= MI_INVALIDATE_TLB
;
1657 if (engine
== &dev_priv
->engine
[VCS
])
1658 cmd
|= MI_INVALIDATE_BSD
;
1661 intel_logical_ring_emit(ringbuf
, cmd
);
1662 intel_logical_ring_emit(ringbuf
,
1663 I915_GEM_HWS_SCRATCH_ADDR
|
1664 MI_FLUSH_DW_USE_GTT
);
1665 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1666 intel_logical_ring_emit(ringbuf
, 0); /* value */
1667 intel_logical_ring_advance(ringbuf
);
1672 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1673 u32 invalidate_domains
,
1676 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1677 struct intel_engine_cs
*engine
= ringbuf
->engine
;
1678 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1679 bool vf_flush_wa
= false, dc_flush_wa
= false;
1684 flags
|= PIPE_CONTROL_CS_STALL
;
1686 if (flush_domains
) {
1687 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1688 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1689 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
1690 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
1693 if (invalidate_domains
) {
1694 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1695 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1696 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1697 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1698 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1699 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1700 flags
|= PIPE_CONTROL_QW_WRITE
;
1701 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1704 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1707 if (IS_GEN9(request
->i915
))
1710 /* WaForGAMHang:kbl */
1711 if (IS_KBL_REVID(request
->i915
, 0, KBL_REVID_B0
))
1723 ret
= intel_ring_begin(request
, len
);
1728 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1729 intel_logical_ring_emit(ringbuf
, 0);
1730 intel_logical_ring_emit(ringbuf
, 0);
1731 intel_logical_ring_emit(ringbuf
, 0);
1732 intel_logical_ring_emit(ringbuf
, 0);
1733 intel_logical_ring_emit(ringbuf
, 0);
1737 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1738 intel_logical_ring_emit(ringbuf
, PIPE_CONTROL_DC_FLUSH_ENABLE
);
1739 intel_logical_ring_emit(ringbuf
, 0);
1740 intel_logical_ring_emit(ringbuf
, 0);
1741 intel_logical_ring_emit(ringbuf
, 0);
1742 intel_logical_ring_emit(ringbuf
, 0);
1745 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1746 intel_logical_ring_emit(ringbuf
, flags
);
1747 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1748 intel_logical_ring_emit(ringbuf
, 0);
1749 intel_logical_ring_emit(ringbuf
, 0);
1750 intel_logical_ring_emit(ringbuf
, 0);
1753 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1754 intel_logical_ring_emit(ringbuf
, PIPE_CONTROL_CS_STALL
);
1755 intel_logical_ring_emit(ringbuf
, 0);
1756 intel_logical_ring_emit(ringbuf
, 0);
1757 intel_logical_ring_emit(ringbuf
, 0);
1758 intel_logical_ring_emit(ringbuf
, 0);
1761 intel_logical_ring_advance(ringbuf
);
1766 static void bxt_a_seqno_barrier(struct intel_engine_cs
*engine
)
1769 * On BXT A steppings there is a HW coherency issue whereby the
1770 * MI_STORE_DATA_IMM storing the completed request's seqno
1771 * occasionally doesn't invalidate the CPU cache. Work around this by
1772 * clflushing the corresponding cacheline whenever the caller wants
1773 * the coherency to be guaranteed. Note that this cacheline is known
1774 * to be clean at this point, since we only write it in
1775 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1776 * this clflush in practice becomes an invalidate operation.
1778 intel_flush_status_page(engine
, I915_GEM_HWS_INDEX
);
1782 * Reserve space for 2 NOOPs at the end of each request to be
1783 * used as a workaround for not being allowed to do lite
1784 * restore with HEAD==TAIL (WaIdleLiteRestore).
1786 #define WA_TAIL_DWORDS 2
1788 static int gen8_emit_request(struct drm_i915_gem_request
*request
)
1790 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1793 ret
= intel_ring_begin(request
, 6 + WA_TAIL_DWORDS
);
1797 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1798 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR
& (1 << 5));
1800 intel_logical_ring_emit(ringbuf
,
1801 (MI_FLUSH_DW
+ 1) | MI_FLUSH_DW_OP_STOREDW
);
1802 intel_logical_ring_emit(ringbuf
,
1803 intel_hws_seqno_address(request
->engine
) |
1804 MI_FLUSH_DW_USE_GTT
);
1805 intel_logical_ring_emit(ringbuf
, 0);
1806 intel_logical_ring_emit(ringbuf
, request
->fence
.seqno
);
1807 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1808 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1809 return intel_logical_ring_advance_and_submit(request
);
1812 static int gen8_emit_request_render(struct drm_i915_gem_request
*request
)
1814 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1817 ret
= intel_ring_begin(request
, 8 + WA_TAIL_DWORDS
);
1821 /* We're using qword write, seqno should be aligned to 8 bytes. */
1822 BUILD_BUG_ON(I915_GEM_HWS_INDEX
& 1);
1824 /* w/a for post sync ops following a GPGPU operation we
1825 * need a prior CS_STALL, which is emitted by the flush
1826 * following the batch.
1828 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1829 intel_logical_ring_emit(ringbuf
,
1830 (PIPE_CONTROL_GLOBAL_GTT_IVB
|
1831 PIPE_CONTROL_CS_STALL
|
1832 PIPE_CONTROL_QW_WRITE
));
1833 intel_logical_ring_emit(ringbuf
,
1834 intel_hws_seqno_address(request
->engine
));
1835 intel_logical_ring_emit(ringbuf
, 0);
1836 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1837 /* We're thrashing one dword of HWS. */
1838 intel_logical_ring_emit(ringbuf
, 0);
1839 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1840 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1841 return intel_logical_ring_advance_and_submit(request
);
1844 static int intel_lr_context_render_state_init(struct drm_i915_gem_request
*req
)
1846 struct render_state so
;
1849 ret
= i915_gem_render_state_prepare(req
->engine
, &so
);
1853 if (so
.rodata
== NULL
)
1856 ret
= req
->engine
->emit_bb_start(req
, so
.ggtt_offset
,
1857 I915_DISPATCH_SECURE
);
1861 ret
= req
->engine
->emit_bb_start(req
,
1862 (so
.ggtt_offset
+ so
.aux_batch_offset
),
1863 I915_DISPATCH_SECURE
);
1867 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), req
);
1870 i915_gem_render_state_fini(&so
);
1874 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
1878 ret
= intel_logical_ring_workarounds_emit(req
);
1882 ret
= intel_rcs_context_init_mocs(req
);
1884 * Failing to program the MOCS is non-fatal.The system will not
1885 * run at peak performance. So generate an error and carry on.
1888 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1890 return intel_lr_context_render_state_init(req
);
1894 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1895 * @engine: Engine Command Streamer.
1897 void intel_logical_ring_cleanup(struct intel_engine_cs
*engine
)
1899 struct drm_i915_private
*dev_priv
;
1901 if (!intel_engine_initialized(engine
))
1905 * Tasklet cannot be active at this point due intel_mark_active/idle
1906 * so this is just for documentation.
1908 if (WARN_ON(test_bit(TASKLET_STATE_SCHED
, &engine
->irq_tasklet
.state
)))
1909 tasklet_kill(&engine
->irq_tasklet
);
1911 dev_priv
= engine
->i915
;
1913 if (engine
->buffer
) {
1914 intel_logical_ring_stop(engine
);
1915 WARN_ON((I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
1918 if (engine
->cleanup
)
1919 engine
->cleanup(engine
);
1921 i915_cmd_parser_fini_ring(engine
);
1922 i915_gem_batch_pool_fini(&engine
->batch_pool
);
1924 intel_engine_fini_breadcrumbs(engine
);
1926 if (engine
->status_page
.obj
) {
1927 i915_gem_object_unpin_map(engine
->status_page
.obj
);
1928 engine
->status_page
.obj
= NULL
;
1930 intel_lr_context_unpin(dev_priv
->kernel_context
, engine
);
1932 engine
->idle_lite_restore_wa
= 0;
1933 engine
->disable_lite_restore_wa
= false;
1934 engine
->ctx_desc_template
= 0;
1936 lrc_destroy_wa_ctx_obj(engine
);
1937 engine
->i915
= NULL
;
1941 logical_ring_default_vfuncs(struct intel_engine_cs
*engine
)
1943 /* Default vfuncs which can be overriden by each engine. */
1944 engine
->init_hw
= gen8_init_common_ring
;
1945 engine
->emit_request
= gen8_emit_request
;
1946 engine
->emit_flush
= gen8_emit_flush
;
1947 engine
->irq_enable
= gen8_logical_ring_enable_irq
;
1948 engine
->irq_disable
= gen8_logical_ring_disable_irq
;
1949 engine
->emit_bb_start
= gen8_emit_bb_start
;
1950 if (IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
))
1951 engine
->irq_seqno_barrier
= bxt_a_seqno_barrier
;
1955 logical_ring_default_irqs(struct intel_engine_cs
*engine
)
1957 unsigned shift
= engine
->irq_shift
;
1958 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
<< shift
;
1959 engine
->irq_keep_mask
= GT_CONTEXT_SWITCH_INTERRUPT
<< shift
;
1963 lrc_setup_hws(struct intel_engine_cs
*engine
,
1964 struct drm_i915_gem_object
*dctx_obj
)
1968 /* The HWSP is part of the default context object in LRC mode. */
1969 engine
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(dctx_obj
) +
1970 LRC_PPHWSP_PN
* PAGE_SIZE
;
1971 hws
= i915_gem_object_pin_map(dctx_obj
);
1973 return PTR_ERR(hws
);
1974 engine
->status_page
.page_addr
= hws
+ LRC_PPHWSP_PN
* PAGE_SIZE
;
1975 engine
->status_page
.obj
= dctx_obj
;
1981 logical_ring_setup(struct intel_engine_cs
*engine
)
1983 struct drm_i915_private
*dev_priv
= engine
->i915
;
1984 enum forcewake_domains fw_domains
;
1986 intel_engine_setup_common(engine
);
1988 /* Intentionally left blank. */
1989 engine
->buffer
= NULL
;
1991 fw_domains
= intel_uncore_forcewake_for_reg(dev_priv
,
1995 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
1996 RING_CONTEXT_STATUS_PTR(engine
),
1997 FW_REG_READ
| FW_REG_WRITE
);
1999 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
2000 RING_CONTEXT_STATUS_BUF_BASE(engine
),
2003 engine
->fw_domains
= fw_domains
;
2005 tasklet_init(&engine
->irq_tasklet
,
2006 intel_lrc_irq_handler
, (unsigned long)engine
);
2008 logical_ring_init_platform_invariants(engine
);
2009 logical_ring_default_vfuncs(engine
);
2010 logical_ring_default_irqs(engine
);
2014 logical_ring_init(struct intel_engine_cs
*engine
)
2016 struct i915_gem_context
*dctx
= engine
->i915
->kernel_context
;
2019 ret
= intel_engine_init_common(engine
);
2023 ret
= execlists_context_deferred_alloc(dctx
, engine
);
2027 /* As this is the default context, always pin it */
2028 ret
= intel_lr_context_pin(dctx
, engine
);
2030 DRM_ERROR("Failed to pin context for %s: %d\n",
2035 /* And setup the hardware status page. */
2036 ret
= lrc_setup_hws(engine
, dctx
->engine
[engine
->id
].state
);
2038 DRM_ERROR("Failed to set up hws %s: %d\n", engine
->name
, ret
);
2045 intel_logical_ring_cleanup(engine
);
2049 int logical_render_ring_init(struct intel_engine_cs
*engine
)
2051 struct drm_i915_private
*dev_priv
= engine
->i915
;
2054 logical_ring_setup(engine
);
2056 if (HAS_L3_DPF(dev_priv
))
2057 engine
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2059 /* Override some for render ring. */
2060 if (INTEL_GEN(dev_priv
) >= 9)
2061 engine
->init_hw
= gen9_init_render_ring
;
2063 engine
->init_hw
= gen8_init_render_ring
;
2064 engine
->init_context
= gen8_init_rcs_context
;
2065 engine
->cleanup
= intel_fini_pipe_control
;
2066 engine
->emit_flush
= gen8_emit_flush_render
;
2067 engine
->emit_request
= gen8_emit_request_render
;
2069 ret
= intel_init_pipe_control(engine
, 4096);
2073 ret
= intel_init_workaround_bb(engine
);
2076 * We continue even if we fail to initialize WA batch
2077 * because we only expect rare glitches but nothing
2078 * critical to prevent us from using GPU
2080 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2084 ret
= logical_ring_init(engine
);
2086 lrc_destroy_wa_ctx_obj(engine
);
2092 int logical_xcs_ring_init(struct intel_engine_cs
*engine
)
2094 logical_ring_setup(engine
);
2096 return logical_ring_init(engine
);
2100 make_rpcs(struct drm_i915_private
*dev_priv
)
2105 * No explicit RPCS request is needed to ensure full
2106 * slice/subslice/EU enablement prior to Gen9.
2108 if (INTEL_GEN(dev_priv
) < 9)
2112 * Starting in Gen9, render power gating can leave
2113 * slice/subslice/EU in a partially enabled state. We
2114 * must make an explicit request through RPCS for full
2117 if (INTEL_INFO(dev_priv
)->has_slice_pg
) {
2118 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
2119 rpcs
|= INTEL_INFO(dev_priv
)->slice_total
<<
2120 GEN8_RPCS_S_CNT_SHIFT
;
2121 rpcs
|= GEN8_RPCS_ENABLE
;
2124 if (INTEL_INFO(dev_priv
)->has_subslice_pg
) {
2125 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
2126 rpcs
|= INTEL_INFO(dev_priv
)->subslice_per_slice
<<
2127 GEN8_RPCS_SS_CNT_SHIFT
;
2128 rpcs
|= GEN8_RPCS_ENABLE
;
2131 if (INTEL_INFO(dev_priv
)->has_eu_pg
) {
2132 rpcs
|= INTEL_INFO(dev_priv
)->eu_per_subslice
<<
2133 GEN8_RPCS_EU_MIN_SHIFT
;
2134 rpcs
|= INTEL_INFO(dev_priv
)->eu_per_subslice
<<
2135 GEN8_RPCS_EU_MAX_SHIFT
;
2136 rpcs
|= GEN8_RPCS_ENABLE
;
2142 static u32
intel_lr_indirect_ctx_offset(struct intel_engine_cs
*engine
)
2144 u32 indirect_ctx_offset
;
2146 switch (INTEL_GEN(engine
->i915
)) {
2148 MISSING_CASE(INTEL_GEN(engine
->i915
));
2151 indirect_ctx_offset
=
2152 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
2155 indirect_ctx_offset
=
2156 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
2160 return indirect_ctx_offset
;
2164 populate_lr_context(struct i915_gem_context
*ctx
,
2165 struct drm_i915_gem_object
*ctx_obj
,
2166 struct intel_engine_cs
*engine
,
2167 struct intel_ringbuffer
*ringbuf
)
2169 struct drm_i915_private
*dev_priv
= ctx
->i915
;
2170 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2176 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2178 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
2180 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2184 vaddr
= i915_gem_object_pin_map(ctx_obj
);
2185 if (IS_ERR(vaddr
)) {
2186 ret
= PTR_ERR(vaddr
);
2187 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret
);
2190 ctx_obj
->dirty
= true;
2192 /* The second page of the context object contains some fields which must
2193 * be set up prior to the first execution. */
2194 reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
2196 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2197 * commands followed by (reg, value) pairs. The values we are setting here are
2198 * only for the first context restore: on a subsequent save, the GPU will
2199 * recreate this batchbuffer with new values (including all the missing
2200 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2201 reg_state
[CTX_LRI_HEADER_0
] =
2202 MI_LOAD_REGISTER_IMM(engine
->id
== RCS
? 14 : 11) | MI_LRI_FORCE_POSTED
;
2203 ASSIGN_CTX_REG(reg_state
, CTX_CONTEXT_CONTROL
,
2204 RING_CONTEXT_CONTROL(engine
),
2205 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
2206 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
2207 (HAS_RESOURCE_STREAMER(dev_priv
) ?
2208 CTX_CTRL_RS_CTX_ENABLE
: 0)));
2209 ASSIGN_CTX_REG(reg_state
, CTX_RING_HEAD
, RING_HEAD(engine
->mmio_base
),
2211 ASSIGN_CTX_REG(reg_state
, CTX_RING_TAIL
, RING_TAIL(engine
->mmio_base
),
2213 /* Ring buffer start address is not known until the buffer is pinned.
2214 * It is written to the context image in execlists_update_context()
2216 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_START
,
2217 RING_START(engine
->mmio_base
), 0);
2218 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_CONTROL
,
2219 RING_CTL(engine
->mmio_base
),
2220 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
);
2221 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_U
,
2222 RING_BBADDR_UDW(engine
->mmio_base
), 0);
2223 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_L
,
2224 RING_BBADDR(engine
->mmio_base
), 0);
2225 ASSIGN_CTX_REG(reg_state
, CTX_BB_STATE
,
2226 RING_BBSTATE(engine
->mmio_base
),
2228 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_U
,
2229 RING_SBBADDR_UDW(engine
->mmio_base
), 0);
2230 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_L
,
2231 RING_SBBADDR(engine
->mmio_base
), 0);
2232 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_STATE
,
2233 RING_SBBSTATE(engine
->mmio_base
), 0);
2234 if (engine
->id
== RCS
) {
2235 ASSIGN_CTX_REG(reg_state
, CTX_BB_PER_CTX_PTR
,
2236 RING_BB_PER_CTX_PTR(engine
->mmio_base
), 0);
2237 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX
,
2238 RING_INDIRECT_CTX(engine
->mmio_base
), 0);
2239 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX_OFFSET
,
2240 RING_INDIRECT_CTX_OFFSET(engine
->mmio_base
), 0);
2241 if (engine
->wa_ctx
.obj
) {
2242 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
2243 uint32_t ggtt_offset
= i915_gem_obj_ggtt_offset(wa_ctx
->obj
);
2245 reg_state
[CTX_RCS_INDIRECT_CTX
+1] =
2246 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
* sizeof(uint32_t)) |
2247 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_DWORDS
);
2249 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] =
2250 intel_lr_indirect_ctx_offset(engine
) << 6;
2252 reg_state
[CTX_BB_PER_CTX_PTR
+1] =
2253 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
* sizeof(uint32_t)) |
2257 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED
;
2258 ASSIGN_CTX_REG(reg_state
, CTX_CTX_TIMESTAMP
,
2259 RING_CTX_TIMESTAMP(engine
->mmio_base
), 0);
2260 /* PDP values well be assigned later if needed */
2261 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_UDW
, GEN8_RING_PDP_UDW(engine
, 3),
2263 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_LDW
, GEN8_RING_PDP_LDW(engine
, 3),
2265 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_UDW
, GEN8_RING_PDP_UDW(engine
, 2),
2267 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_LDW
, GEN8_RING_PDP_LDW(engine
, 2),
2269 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_UDW
, GEN8_RING_PDP_UDW(engine
, 1),
2271 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_LDW
, GEN8_RING_PDP_LDW(engine
, 1),
2273 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_UDW
, GEN8_RING_PDP_UDW(engine
, 0),
2275 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_LDW
, GEN8_RING_PDP_LDW(engine
, 0),
2278 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
2279 /* 64b PPGTT (48bit canonical)
2280 * PDP0_DESCRIPTOR contains the base address to PML4 and
2281 * other PDP Descriptors are ignored.
2283 ASSIGN_CTX_PML4(ppgtt
, reg_state
);
2286 * PDP*_DESCRIPTOR contains the base address of space supported.
2287 * With dynamic page allocation, PDPs may not be allocated at
2288 * this point. Point the unallocated PDPs to the scratch page
2290 execlists_update_context_pdps(ppgtt
, reg_state
);
2293 if (engine
->id
== RCS
) {
2294 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
2295 ASSIGN_CTX_REG(reg_state
, CTX_R_PWR_CLK_STATE
, GEN8_R_PWR_CLK_STATE
,
2296 make_rpcs(dev_priv
));
2299 i915_gem_object_unpin_map(ctx_obj
);
2305 * intel_lr_context_size() - return the size of the context for an engine
2306 * @engine: which engine to find the context size for
2308 * Each engine may require a different amount of space for a context image,
2309 * so when allocating (or copying) an image, this function can be used to
2310 * find the right size for the specific engine.
2312 * Return: size (in bytes) of an engine-specific context image
2314 * Note: this size includes the HWSP, which is part of the context image
2315 * in LRC mode, but does not include the "shared data page" used with
2316 * GuC submission. The caller should account for this if using the GuC.
2318 uint32_t intel_lr_context_size(struct intel_engine_cs
*engine
)
2322 WARN_ON(INTEL_GEN(engine
->i915
) < 8);
2324 switch (engine
->id
) {
2326 if (INTEL_GEN(engine
->i915
) >= 9)
2327 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
2329 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
2335 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
2342 static int execlists_context_deferred_alloc(struct i915_gem_context
*ctx
,
2343 struct intel_engine_cs
*engine
)
2345 struct drm_i915_gem_object
*ctx_obj
;
2346 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2347 uint32_t context_size
;
2348 struct intel_ringbuffer
*ringbuf
;
2353 context_size
= round_up(intel_lr_context_size(engine
), 4096);
2355 /* One extra page as the sharing data between driver and GuC */
2356 context_size
+= PAGE_SIZE
* LRC_PPHWSP_PN
;
2358 ctx_obj
= i915_gem_object_create(&ctx
->i915
->drm
, context_size
);
2359 if (IS_ERR(ctx_obj
)) {
2360 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2361 return PTR_ERR(ctx_obj
);
2364 ringbuf
= intel_engine_create_ringbuffer(engine
, ctx
->ring_size
);
2365 if (IS_ERR(ringbuf
)) {
2366 ret
= PTR_ERR(ringbuf
);
2367 goto error_deref_obj
;
2370 ret
= populate_lr_context(ctx
, ctx_obj
, engine
, ringbuf
);
2372 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2376 ce
->ringbuf
= ringbuf
;
2377 ce
->state
= ctx_obj
;
2378 ce
->initialised
= engine
->init_context
== NULL
;
2383 intel_ringbuffer_free(ringbuf
);
2385 i915_gem_object_put(ctx_obj
);
2391 void intel_lr_context_reset(struct drm_i915_private
*dev_priv
,
2392 struct i915_gem_context
*ctx
)
2394 struct intel_engine_cs
*engine
;
2396 for_each_engine(engine
, dev_priv
) {
2397 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2398 struct drm_i915_gem_object
*ctx_obj
= ce
->state
;
2400 uint32_t *reg_state
;
2405 vaddr
= i915_gem_object_pin_map(ctx_obj
);
2406 if (WARN_ON(IS_ERR(vaddr
)))
2409 reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
2410 ctx_obj
->dirty
= true;
2412 reg_state
[CTX_RING_HEAD
+1] = 0;
2413 reg_state
[CTX_RING_TAIL
+1] = 0;
2415 i915_gem_object_unpin_map(ctx_obj
);
2417 ce
->ringbuf
->head
= 0;
2418 ce
->ringbuf
->tail
= 0;