2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define RING_EXECLIST_QFULL (1 << 0x2)
142 #define RING_EXECLIST1_VALID (1 << 0x3)
143 #define RING_EXECLIST0_VALID (1 << 0x4)
144 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
145 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
146 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
148 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
149 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
150 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
151 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
152 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
153 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
155 #define GEN8_CTX_STATUS_COMPLETED_MASK \
156 (GEN8_CTX_STATUS_ACTIVE_IDLE | \
157 GEN8_CTX_STATUS_PREEMPTED | \
158 GEN8_CTX_STATUS_ELEMENT_SWITCH)
160 #define CTX_LRI_HEADER_0 0x01
161 #define CTX_CONTEXT_CONTROL 0x02
162 #define CTX_RING_HEAD 0x04
163 #define CTX_RING_TAIL 0x06
164 #define CTX_RING_BUFFER_START 0x08
165 #define CTX_RING_BUFFER_CONTROL 0x0a
166 #define CTX_BB_HEAD_U 0x0c
167 #define CTX_BB_HEAD_L 0x0e
168 #define CTX_BB_STATE 0x10
169 #define CTX_SECOND_BB_HEAD_U 0x12
170 #define CTX_SECOND_BB_HEAD_L 0x14
171 #define CTX_SECOND_BB_STATE 0x16
172 #define CTX_BB_PER_CTX_PTR 0x18
173 #define CTX_RCS_INDIRECT_CTX 0x1a
174 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
175 #define CTX_LRI_HEADER_1 0x21
176 #define CTX_CTX_TIMESTAMP 0x22
177 #define CTX_PDP3_UDW 0x24
178 #define CTX_PDP3_LDW 0x26
179 #define CTX_PDP2_UDW 0x28
180 #define CTX_PDP2_LDW 0x2a
181 #define CTX_PDP1_UDW 0x2c
182 #define CTX_PDP1_LDW 0x2e
183 #define CTX_PDP0_UDW 0x30
184 #define CTX_PDP0_LDW 0x32
185 #define CTX_LRI_HEADER_2 0x41
186 #define CTX_R_PWR_CLK_STATE 0x42
187 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
189 #define CTX_REG(reg_state, pos, reg, val) do { \
190 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
191 (reg_state)[(pos)+1] = (val); \
194 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
195 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
196 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
197 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
200 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
201 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
202 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
205 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
206 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
207 #define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x19
209 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
210 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
212 #define WA_TAIL_DWORDS 2
214 static int execlists_context_deferred_alloc(struct i915_gem_context
*ctx
,
215 struct intel_engine_cs
*engine
);
216 static void execlists_init_reg_state(u32
*reg_state
,
217 struct i915_gem_context
*ctx
,
218 struct intel_engine_cs
*engine
,
219 struct intel_ring
*ring
);
222 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
223 * @dev_priv: i915 device private
224 * @enable_execlists: value of i915.enable_execlists module parameter.
226 * Only certain platforms support Execlists (the prerequisites being
227 * support for Logical Ring Contexts and Aliasing PPGTT or better).
229 * Return: 1 if Execlists is supported and has to be enabled.
231 int intel_sanitize_enable_execlists(struct drm_i915_private
*dev_priv
, int enable_execlists
)
233 /* On platforms with execlist available, vGPU will only
234 * support execlist mode, no ring buffer mode.
236 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv
) && intel_vgpu_active(dev_priv
))
239 if (INTEL_GEN(dev_priv
) >= 9)
242 if (enable_execlists
== 0)
245 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv
) &&
246 USES_PPGTT(dev_priv
) &&
247 i915_modparams
.use_mmio_flip
>= 0)
254 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
255 * descriptor for a pinned context
256 * @ctx: Context to work on
257 * @engine: Engine the descriptor will be used with
259 * The context descriptor encodes various attributes of a context,
260 * including its GTT address and some flags. Because it's fairly
261 * expensive to calculate, we'll just do it once and cache the result,
262 * which remains valid until the context is unpinned.
264 * This is what a descriptor looks like, from LSB to MSB::
266 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
267 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
268 * bits 32-52: ctx ID, a globally unique tag
269 * bits 53-54: mbz, reserved for use by hardware
270 * bits 55-63: group ID, currently unused and set to 0
273 intel_lr_context_descriptor_update(struct i915_gem_context
*ctx
,
274 struct intel_engine_cs
*engine
)
276 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
279 BUILD_BUG_ON(MAX_CONTEXT_HW_ID
> (1<<GEN8_CTX_ID_WIDTH
));
281 desc
= ctx
->desc_template
; /* bits 0-11 */
282 desc
|= i915_ggtt_offset(ce
->state
) + LRC_HEADER_PAGES
* PAGE_SIZE
;
284 desc
|= (u64
)ctx
->hw_id
<< GEN8_CTX_ID_SHIFT
; /* bits 32-52 */
289 static struct i915_priolist
*
290 lookup_priolist(struct intel_engine_cs
*engine
,
291 struct i915_priotree
*pt
,
294 struct intel_engine_execlists
* const execlists
= &engine
->execlists
;
295 struct i915_priolist
*p
;
296 struct rb_node
**parent
, *rb
;
299 if (unlikely(execlists
->no_priolist
))
300 prio
= I915_PRIORITY_NORMAL
;
303 /* most positive priority is scheduled first, equal priorities fifo */
305 parent
= &execlists
->queue
.rb_node
;
308 p
= rb_entry(rb
, typeof(*p
), node
);
309 if (prio
> p
->priority
) {
310 parent
= &rb
->rb_left
;
311 } else if (prio
< p
->priority
) {
312 parent
= &rb
->rb_right
;
319 if (prio
== I915_PRIORITY_NORMAL
) {
320 p
= &execlists
->default_priolist
;
322 p
= kmem_cache_alloc(engine
->i915
->priorities
, GFP_ATOMIC
);
323 /* Convert an allocation failure to a priority bump */
325 prio
= I915_PRIORITY_NORMAL
; /* recurses just once */
327 /* To maintain ordering with all rendering, after an
328 * allocation failure we have to disable all scheduling.
329 * Requests will then be executed in fifo, and schedule
330 * will ensure that dependencies are emitted in fifo.
331 * There will be still some reordering with existing
332 * requests, so if userspace lied about their
333 * dependencies that reordering may be visible.
335 execlists
->no_priolist
= true;
341 INIT_LIST_HEAD(&p
->requests
);
342 rb_link_node(&p
->node
, rb
, parent
);
343 rb_insert_color(&p
->node
, &execlists
->queue
);
346 execlists
->first
= &p
->node
;
348 return ptr_pack_bits(p
, first
, 1);
352 execlists_context_status_change(struct drm_i915_gem_request
*rq
,
353 unsigned long status
)
356 * Only used when GVT-g is enabled now. When GVT-g is disabled,
357 * The compiler should eliminate this function as dead-code.
359 if (!IS_ENABLED(CONFIG_DRM_I915_GVT
))
362 atomic_notifier_call_chain(&rq
->engine
->context_status_notifier
,
367 execlists_update_context_pdps(struct i915_hw_ppgtt
*ppgtt
, u32
*reg_state
)
369 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
370 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
371 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
372 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
375 static u64
execlists_update_context(struct drm_i915_gem_request
*rq
)
377 struct intel_context
*ce
= &rq
->ctx
->engine
[rq
->engine
->id
];
378 struct i915_hw_ppgtt
*ppgtt
=
379 rq
->ctx
->ppgtt
?: rq
->i915
->mm
.aliasing_ppgtt
;
380 u32
*reg_state
= ce
->lrc_reg_state
;
382 reg_state
[CTX_RING_TAIL
+1] = intel_ring_set_tail(rq
->ring
, rq
->tail
);
384 /* True 32b PPGTT with dynamic page allocation: update PDP
385 * registers and point the unallocated PDPs to scratch page.
386 * PML4 is allocated during ppgtt init, so this is not needed
389 if (ppgtt
&& !i915_vm_is_48bit(&ppgtt
->base
))
390 execlists_update_context_pdps(ppgtt
, reg_state
);
395 static void execlists_submit_ports(struct intel_engine_cs
*engine
)
397 struct execlist_port
*port
= engine
->execlists
.port
;
399 engine
->i915
->regs
+ i915_mmio_reg_offset(RING_ELSP(engine
));
402 for (n
= execlists_num_ports(&engine
->execlists
); n
--; ) {
403 struct drm_i915_gem_request
*rq
;
407 rq
= port_unpack(&port
[n
], &count
);
409 GEM_BUG_ON(count
> !n
);
411 execlists_context_status_change(rq
, INTEL_CONTEXT_SCHEDULE_IN
);
412 port_set(&port
[n
], port_pack(rq
, count
));
413 desc
= execlists_update_context(rq
);
414 GEM_DEBUG_EXEC(port
[n
].context_id
= upper_32_bits(desc
));
420 writel(upper_32_bits(desc
), elsp
);
421 writel(lower_32_bits(desc
), elsp
);
425 static bool ctx_single_port_submission(const struct i915_gem_context
*ctx
)
427 return (IS_ENABLED(CONFIG_DRM_I915_GVT
) &&
428 i915_gem_context_force_single_submission(ctx
));
431 static bool can_merge_ctx(const struct i915_gem_context
*prev
,
432 const struct i915_gem_context
*next
)
437 if (ctx_single_port_submission(prev
))
443 static void port_assign(struct execlist_port
*port
,
444 struct drm_i915_gem_request
*rq
)
446 GEM_BUG_ON(rq
== port_request(port
));
448 if (port_isset(port
))
449 i915_gem_request_put(port_request(port
));
451 port_set(port
, port_pack(i915_gem_request_get(rq
), port_count(port
)));
454 static void execlists_dequeue(struct intel_engine_cs
*engine
)
456 struct drm_i915_gem_request
*last
;
457 struct intel_engine_execlists
* const execlists
= &engine
->execlists
;
458 struct execlist_port
*port
= execlists
->port
;
459 const struct execlist_port
* const last_port
=
460 &execlists
->port
[execlists
->port_mask
];
464 last
= port_request(port
);
466 /* WaIdleLiteRestore:bdw,skl
467 * Apply the wa NOOPs to prevent ring:HEAD == req:TAIL
468 * as we resubmit the request. See gen8_emit_breadcrumb()
469 * for where we prepare the padding after the end of the
472 last
->tail
= last
->wa_tail
;
474 /* Hardware submission is through 2 ports. Conceptually each port
475 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
476 * static for a context, and unique to each, so we only execute
477 * requests belonging to a single context from each ring. RING_HEAD
478 * is maintained by the CS in the context image, it marks the place
479 * where it got up to last time, and through RING_TAIL we tell the CS
480 * where we want to execute up to this time.
482 * In this list the requests are in order of execution. Consecutive
483 * requests from the same context are adjacent in the ringbuffer. We
484 * can combine these requests into a single RING_TAIL update:
486 * RING_HEAD...req1...req2
488 * since to execute req2 the CS must first execute req1.
490 * Our goal then is to point each port to the end of a consecutive
491 * sequence of requests as being the most optimal (fewest wake ups
492 * and context switches) submission.
495 spin_lock_irq(&engine
->timeline
->lock
);
496 rb
= execlists
->first
;
497 GEM_BUG_ON(rb_first(&execlists
->queue
) != rb
);
499 struct i915_priolist
*p
= rb_entry(rb
, typeof(*p
), node
);
500 struct drm_i915_gem_request
*rq
, *rn
;
502 list_for_each_entry_safe(rq
, rn
, &p
->requests
, priotree
.link
) {
504 * Can we combine this request with the current port?
505 * It has to be the same context/ringbuffer and not
506 * have any exceptions (e.g. GVT saying never to
509 * If we can combine the requests, we can execute both
510 * by updating the RING_TAIL to point to the end of the
511 * second request, and so we never need to tell the
512 * hardware about the first.
514 if (last
&& !can_merge_ctx(rq
->ctx
, last
->ctx
)) {
516 * If we are on the second port and cannot
517 * combine this request with the last, then we
520 if (port
== last_port
) {
521 __list_del_many(&p
->requests
,
527 * If GVT overrides us we only ever submit
528 * port[0], leaving port[1] empty. Note that we
529 * also have to be careful that we don't queue
530 * the same context (even though a different
531 * request) to the second port.
533 if (ctx_single_port_submission(last
->ctx
) ||
534 ctx_single_port_submission(rq
->ctx
)) {
535 __list_del_many(&p
->requests
,
540 GEM_BUG_ON(last
->ctx
== rq
->ctx
);
543 port_assign(port
, last
);
546 GEM_BUG_ON(port_isset(port
));
549 INIT_LIST_HEAD(&rq
->priotree
.link
);
550 rq
->priotree
.priority
= INT_MAX
;
552 __i915_gem_request_submit(rq
);
553 trace_i915_gem_request_in(rq
, port_index(port
, execlists
));
559 rb_erase(&p
->node
, &execlists
->queue
);
560 INIT_LIST_HEAD(&p
->requests
);
561 if (p
->priority
!= I915_PRIORITY_NORMAL
)
562 kmem_cache_free(engine
->i915
->priorities
, p
);
565 execlists
->first
= rb
;
567 port_assign(port
, last
);
568 spin_unlock_irq(&engine
->timeline
->lock
);
571 execlists_submit_ports(engine
);
575 execlist_cancel_port_requests(struct intel_engine_execlists
*execlists
)
577 struct execlist_port
*port
= execlists
->port
;
578 unsigned int num_ports
= ARRAY_SIZE(execlists
->port
);
580 while (num_ports
-- && port_isset(port
)) {
581 struct drm_i915_gem_request
*rq
= port_request(port
);
583 execlists_context_status_change(rq
, INTEL_CONTEXT_SCHEDULE_OUT
);
584 i915_gem_request_put(rq
);
586 memset(port
, 0, sizeof(*port
));
591 static void execlists_cancel_requests(struct intel_engine_cs
*engine
)
593 struct intel_engine_execlists
* const execlists
= &engine
->execlists
;
594 struct drm_i915_gem_request
*rq
, *rn
;
598 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
600 /* Cancel the requests on the HW and clear the ELSP tracker. */
601 execlist_cancel_port_requests(execlists
);
603 /* Mark all executing requests as skipped. */
604 list_for_each_entry(rq
, &engine
->timeline
->requests
, link
) {
605 GEM_BUG_ON(!rq
->global_seqno
);
606 if (!i915_gem_request_completed(rq
))
607 dma_fence_set_error(&rq
->fence
, -EIO
);
610 /* Flush the queued requests to the timeline list (for retiring). */
611 rb
= execlists
->first
;
613 struct i915_priolist
*p
= rb_entry(rb
, typeof(*p
), node
);
615 list_for_each_entry_safe(rq
, rn
, &p
->requests
, priotree
.link
) {
616 INIT_LIST_HEAD(&rq
->priotree
.link
);
617 rq
->priotree
.priority
= INT_MAX
;
619 dma_fence_set_error(&rq
->fence
, -EIO
);
620 __i915_gem_request_submit(rq
);
624 rb_erase(&p
->node
, &execlists
->queue
);
625 INIT_LIST_HEAD(&p
->requests
);
626 if (p
->priority
!= I915_PRIORITY_NORMAL
)
627 kmem_cache_free(engine
->i915
->priorities
, p
);
630 /* Remaining _unready_ requests will be nop'ed when submitted */
633 execlists
->queue
= RB_ROOT
;
634 execlists
->first
= NULL
;
635 GEM_BUG_ON(port_isset(execlists
->port
));
638 * The port is checked prior to scheduling a tasklet, but
639 * just in case we have suspended the tasklet to do the
640 * wedging make sure that when it wakes, it decides there
641 * is no work to do by clearing the irq_posted bit.
643 clear_bit(ENGINE_IRQ_EXECLIST
, &engine
->irq_posted
);
645 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
648 static bool execlists_elsp_ready(const struct intel_engine_cs
*engine
)
650 const struct execlist_port
*port
= engine
->execlists
.port
;
652 return port_count(&port
[0]) + port_count(&port
[1]) < 2;
656 * Check the unread Context Status Buffers and manage the submission of new
657 * contexts to the ELSP accordingly.
659 static void intel_lrc_irq_handler(unsigned long data
)
661 struct intel_engine_cs
* const engine
= (struct intel_engine_cs
*)data
;
662 struct intel_engine_execlists
* const execlists
= &engine
->execlists
;
663 struct execlist_port
*port
= execlists
->port
;
664 struct drm_i915_private
*dev_priv
= engine
->i915
;
666 /* We can skip acquiring intel_runtime_pm_get() here as it was taken
667 * on our behalf by the request (see i915_gem_mark_busy()) and it will
668 * not be relinquished until the device is idle (see
669 * i915_gem_idle_work_handler()). As a precaution, we make sure
670 * that all ELSP are drained i.e. we have processed the CSB,
671 * before allowing ourselves to idle and calling intel_runtime_pm_put().
673 GEM_BUG_ON(!dev_priv
->gt
.awake
);
675 intel_uncore_forcewake_get(dev_priv
, execlists
->fw_domains
);
677 /* Prefer doing test_and_clear_bit() as a two stage operation to avoid
678 * imposing the cost of a locked atomic transaction when submitting a
679 * new request (outside of the context-switch interrupt).
681 while (test_bit(ENGINE_IRQ_EXECLIST
, &engine
->irq_posted
)) {
682 /* The HWSP contains a (cacheable) mirror of the CSB */
684 &engine
->status_page
.page_addr
[I915_HWS_CSB_BUF0_INDEX
];
685 unsigned int head
, tail
;
687 /* However GVT emulation depends upon intercepting CSB mmio */
688 if (unlikely(execlists
->csb_use_mmio
)) {
689 buf
= (u32
* __force
)
690 (dev_priv
->regs
+ i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine
, 0)));
691 execlists
->csb_head
= -1; /* force mmio read of CSB ptrs */
694 /* The write will be ordered by the uncached read (itself
695 * a memory barrier), so we do not need another in the form
696 * of a locked instruction. The race between the interrupt
697 * handler and the split test/clear is harmless as we order
698 * our clear before the CSB read. If the interrupt arrived
699 * first between the test and the clear, we read the updated
700 * CSB and clear the bit. If the interrupt arrives as we read
701 * the CSB or later (i.e. after we had cleared the bit) the bit
702 * is set and we do a new loop.
704 __clear_bit(ENGINE_IRQ_EXECLIST
, &engine
->irq_posted
);
705 if (unlikely(execlists
->csb_head
== -1)) { /* following a reset */
706 head
= readl(dev_priv
->regs
+ i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine
)));
707 tail
= GEN8_CSB_WRITE_PTR(head
);
708 head
= GEN8_CSB_READ_PTR(head
);
709 execlists
->csb_head
= head
;
711 const int write_idx
=
712 intel_hws_csb_write_index(dev_priv
) -
713 I915_HWS_CSB_BUF0_INDEX
;
715 head
= execlists
->csb_head
;
716 tail
= READ_ONCE(buf
[write_idx
]);
719 while (head
!= tail
) {
720 struct drm_i915_gem_request
*rq
;
724 if (++head
== GEN8_CSB_ENTRIES
)
727 /* We are flying near dragons again.
729 * We hold a reference to the request in execlist_port[]
730 * but no more than that. We are operating in softirq
731 * context and so cannot hold any mutex or sleep. That
732 * prevents us stopping the requests we are processing
733 * in port[] from being retired simultaneously (the
734 * breadcrumb will be complete before we see the
735 * context-switch). As we only hold the reference to the
736 * request, any pointer chasing underneath the request
737 * is subject to a potential use-after-free. Thus we
738 * store all of the bookkeeping within port[] as
739 * required, and avoid using unguarded pointers beneath
740 * request itself. The same applies to the atomic
744 status
= READ_ONCE(buf
[2 * head
]); /* maybe mmio! */
745 if (!(status
& GEN8_CTX_STATUS_COMPLETED_MASK
))
748 /* Check the context/desc id for this event matches */
749 GEM_DEBUG_BUG_ON(buf
[2 * head
+ 1] != port
->context_id
);
751 rq
= port_unpack(port
, &count
);
752 GEM_BUG_ON(count
== 0);
754 GEM_BUG_ON(status
& GEN8_CTX_STATUS_PREEMPTED
);
755 GEM_BUG_ON(!i915_gem_request_completed(rq
));
756 execlists_context_status_change(rq
, INTEL_CONTEXT_SCHEDULE_OUT
);
758 trace_i915_gem_request_out(rq
);
759 i915_gem_request_put(rq
);
761 execlists_port_complete(execlists
, port
);
763 port_set(port
, port_pack(rq
, count
));
766 /* After the final element, the hw should be idle */
767 GEM_BUG_ON(port_count(port
) == 0 &&
768 !(status
& GEN8_CTX_STATUS_ACTIVE_IDLE
));
771 if (head
!= execlists
->csb_head
) {
772 execlists
->csb_head
= head
;
773 writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK
, head
<< 8),
774 dev_priv
->regs
+ i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine
)));
778 if (execlists_elsp_ready(engine
))
779 execlists_dequeue(engine
);
781 intel_uncore_forcewake_put(dev_priv
, execlists
->fw_domains
);
784 static void insert_request(struct intel_engine_cs
*engine
,
785 struct i915_priotree
*pt
,
788 struct i915_priolist
*p
= lookup_priolist(engine
, pt
, prio
);
790 list_add_tail(&pt
->link
, &ptr_mask_bits(p
, 1)->requests
);
791 if (ptr_unmask_bits(p
, 1) && execlists_elsp_ready(engine
))
792 tasklet_hi_schedule(&engine
->execlists
.irq_tasklet
);
795 static void execlists_submit_request(struct drm_i915_gem_request
*request
)
797 struct intel_engine_cs
*engine
= request
->engine
;
800 /* Will be called from irq-context when using foreign fences. */
801 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
803 insert_request(engine
, &request
->priotree
, request
->priotree
.priority
);
805 GEM_BUG_ON(!engine
->execlists
.first
);
806 GEM_BUG_ON(list_empty(&request
->priotree
.link
));
808 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
811 static struct intel_engine_cs
*
812 pt_lock_engine(struct i915_priotree
*pt
, struct intel_engine_cs
*locked
)
814 struct intel_engine_cs
*engine
=
815 container_of(pt
, struct drm_i915_gem_request
, priotree
)->engine
;
819 if (engine
!= locked
) {
820 spin_unlock(&locked
->timeline
->lock
);
821 spin_lock(&engine
->timeline
->lock
);
827 static void execlists_schedule(struct drm_i915_gem_request
*request
, int prio
)
829 struct intel_engine_cs
*engine
;
830 struct i915_dependency
*dep
, *p
;
831 struct i915_dependency stack
;
834 if (prio
<= READ_ONCE(request
->priotree
.priority
))
837 /* Need BKL in order to use the temporary link inside i915_dependency */
838 lockdep_assert_held(&request
->i915
->drm
.struct_mutex
);
840 stack
.signaler
= &request
->priotree
;
841 list_add(&stack
.dfs_link
, &dfs
);
843 /* Recursively bump all dependent priorities to match the new request.
845 * A naive approach would be to use recursion:
846 * static void update_priorities(struct i915_priotree *pt, prio) {
847 * list_for_each_entry(dep, &pt->signalers_list, signal_link)
848 * update_priorities(dep->signal, prio)
849 * insert_request(pt);
851 * but that may have unlimited recursion depth and so runs a very
852 * real risk of overunning the kernel stack. Instead, we build
853 * a flat list of all dependencies starting with the current request.
854 * As we walk the list of dependencies, we add all of its dependencies
855 * to the end of the list (this may include an already visited
856 * request) and continue to walk onwards onto the new dependencies. The
857 * end result is a topological list of requests in reverse order, the
858 * last element in the list is the request we must execute first.
860 list_for_each_entry_safe(dep
, p
, &dfs
, dfs_link
) {
861 struct i915_priotree
*pt
= dep
->signaler
;
863 /* Within an engine, there can be no cycle, but we may
864 * refer to the same dependency chain multiple times
865 * (redundant dependencies are not eliminated) and across
868 list_for_each_entry(p
, &pt
->signalers_list
, signal_link
) {
869 GEM_BUG_ON(p
->signaler
->priority
< pt
->priority
);
870 if (prio
> READ_ONCE(p
->signaler
->priority
))
871 list_move_tail(&p
->dfs_link
, &dfs
);
874 list_safe_reset_next(dep
, p
, dfs_link
);
877 /* If we didn't need to bump any existing priorities, and we haven't
878 * yet submitted this request (i.e. there is no potential race with
879 * execlists_submit_request()), we can set our own priority and skip
880 * acquiring the engine locks.
882 if (request
->priotree
.priority
== INT_MIN
) {
883 GEM_BUG_ON(!list_empty(&request
->priotree
.link
));
884 request
->priotree
.priority
= prio
;
885 if (stack
.dfs_link
.next
== stack
.dfs_link
.prev
)
887 __list_del_entry(&stack
.dfs_link
);
890 engine
= request
->engine
;
891 spin_lock_irq(&engine
->timeline
->lock
);
893 /* Fifo and depth-first replacement ensure our deps execute before us */
894 list_for_each_entry_safe_reverse(dep
, p
, &dfs
, dfs_link
) {
895 struct i915_priotree
*pt
= dep
->signaler
;
897 INIT_LIST_HEAD(&dep
->dfs_link
);
899 engine
= pt_lock_engine(pt
, engine
);
901 if (prio
<= pt
->priority
)
905 if (!list_empty(&pt
->link
)) {
906 __list_del_entry(&pt
->link
);
907 insert_request(engine
, pt
, prio
);
911 spin_unlock_irq(&engine
->timeline
->lock
);
913 /* XXX Do we need to preempt to make room for us and our deps? */
916 static struct intel_ring
*
917 execlists_context_pin(struct intel_engine_cs
*engine
,
918 struct i915_gem_context
*ctx
)
920 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
925 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
927 if (likely(ce
->pin_count
++))
929 GEM_BUG_ON(!ce
->pin_count
); /* no overflow please! */
932 ret
= execlists_context_deferred_alloc(ctx
, engine
);
936 GEM_BUG_ON(!ce
->state
);
938 flags
= PIN_GLOBAL
| PIN_HIGH
;
939 if (ctx
->ggtt_offset_bias
)
940 flags
|= PIN_OFFSET_BIAS
| ctx
->ggtt_offset_bias
;
942 ret
= i915_vma_pin(ce
->state
, 0, GEN8_LR_CONTEXT_ALIGN
, flags
);
946 vaddr
= i915_gem_object_pin_map(ce
->state
->obj
, I915_MAP_WB
);
948 ret
= PTR_ERR(vaddr
);
952 ret
= intel_ring_pin(ce
->ring
, ctx
->i915
, ctx
->ggtt_offset_bias
);
956 intel_lr_context_descriptor_update(ctx
, engine
);
958 ce
->lrc_reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
959 ce
->lrc_reg_state
[CTX_RING_BUFFER_START
+1] =
960 i915_ggtt_offset(ce
->ring
->vma
);
962 ce
->state
->obj
->mm
.dirty
= true;
964 i915_gem_context_get(ctx
);
969 i915_gem_object_unpin_map(ce
->state
->obj
);
971 __i915_vma_unpin(ce
->state
);
977 static void execlists_context_unpin(struct intel_engine_cs
*engine
,
978 struct i915_gem_context
*ctx
)
980 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
982 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
983 GEM_BUG_ON(ce
->pin_count
== 0);
988 intel_ring_unpin(ce
->ring
);
990 i915_gem_object_unpin_map(ce
->state
->obj
);
991 i915_vma_unpin(ce
->state
);
993 i915_gem_context_put(ctx
);
996 static int execlists_request_alloc(struct drm_i915_gem_request
*request
)
998 struct intel_engine_cs
*engine
= request
->engine
;
999 struct intel_context
*ce
= &request
->ctx
->engine
[engine
->id
];
1003 GEM_BUG_ON(!ce
->pin_count
);
1005 /* Flush enough space to reduce the likelihood of waiting after
1006 * we start building the request - in which case we will just
1007 * have to repeat work.
1009 request
->reserved_space
+= EXECLISTS_REQUEST_SIZE
;
1011 cs
= intel_ring_begin(request
, 0);
1015 if (!ce
->initialised
) {
1016 ret
= engine
->init_context(request
);
1020 ce
->initialised
= true;
1023 /* Note that after this point, we have committed to using
1024 * this request as it is being used to both track the
1025 * state of engine initialisation and liveness of the
1026 * golden renderstate above. Think twice before you try
1027 * to cancel/unwind this request now.
1030 request
->reserved_space
-= EXECLISTS_REQUEST_SIZE
;
1035 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1036 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1037 * but there is a slight complication as this is applied in WA batch where the
1038 * values are only initialized once so we cannot take register value at the
1039 * beginning and reuse it further; hence we save its value to memory, upload a
1040 * constant value with bit21 set and then we restore it back with the saved value.
1041 * To simplify the WA, a constant value is formed by using the default value
1042 * of this register. This shouldn't be a problem because we are only modifying
1043 * it for a short period and this batch in non-premptible. We can ofcourse
1044 * use additional instructions that read the actual value of the register
1045 * at that time and set our bit of interest but it makes the WA complicated.
1047 * This WA is also required for Gen9 so extracting as a function avoids
1051 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*engine
, u32
*batch
)
1053 *batch
++ = MI_STORE_REGISTER_MEM_GEN8
| MI_SRM_LRM_GLOBAL_GTT
;
1054 *batch
++ = i915_mmio_reg_offset(GEN8_L3SQCREG4
);
1055 *batch
++ = i915_ggtt_offset(engine
->scratch
) + 256;
1058 *batch
++ = MI_LOAD_REGISTER_IMM(1);
1059 *batch
++ = i915_mmio_reg_offset(GEN8_L3SQCREG4
);
1060 *batch
++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
;
1062 batch
= gen8_emit_pipe_control(batch
,
1063 PIPE_CONTROL_CS_STALL
|
1064 PIPE_CONTROL_DC_FLUSH_ENABLE
,
1067 *batch
++ = MI_LOAD_REGISTER_MEM_GEN8
| MI_SRM_LRM_GLOBAL_GTT
;
1068 *batch
++ = i915_mmio_reg_offset(GEN8_L3SQCREG4
);
1069 *batch
++ = i915_ggtt_offset(engine
->scratch
) + 256;
1076 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1077 * initialized at the beginning and shared across all contexts but this field
1078 * helps us to have multiple batches at different offsets and select them based
1079 * on a criteria. At the moment this batch always start at the beginning of the page
1080 * and at this point we don't have multiple wa_ctx batch buffers.
1082 * The number of WA applied are not known at the beginning; we use this field
1083 * to return the no of DWORDS written.
1085 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1086 * so it adds NOOPs as padding to make it cacheline aligned.
1087 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1088 * makes a complete batch buffer.
1090 static u32
*gen8_init_indirectctx_bb(struct intel_engine_cs
*engine
, u32
*batch
)
1092 /* WaDisableCtxRestoreArbitration:bdw,chv */
1093 *batch
++ = MI_ARB_ON_OFF
| MI_ARB_DISABLE
;
1095 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1096 if (IS_BROADWELL(engine
->i915
))
1097 batch
= gen8_emit_flush_coherentl3_wa(engine
, batch
);
1099 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1100 /* Actual scratch location is at 128 bytes offset */
1101 batch
= gen8_emit_pipe_control(batch
,
1102 PIPE_CONTROL_FLUSH_L3
|
1103 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1104 PIPE_CONTROL_CS_STALL
|
1105 PIPE_CONTROL_QW_WRITE
,
1106 i915_ggtt_offset(engine
->scratch
) +
1107 2 * CACHELINE_BYTES
);
1109 /* Pad to end of cacheline */
1110 while ((unsigned long)batch
% CACHELINE_BYTES
)
1114 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1115 * execution depends on the length specified in terms of cache lines
1116 * in the register CTX_RCS_INDIRECT_CTX
1123 * This batch is started immediately after indirect_ctx batch. Since we ensure
1124 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1126 * The number of DWORDS written are returned using this field.
1128 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1129 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1131 static u32
*gen8_init_perctx_bb(struct intel_engine_cs
*engine
, u32
*batch
)
1133 /* WaDisableCtxRestoreArbitration:bdw,chv */
1134 *batch
++ = MI_ARB_ON_OFF
| MI_ARB_ENABLE
;
1135 *batch
++ = MI_BATCH_BUFFER_END
;
1140 static u32
*gen9_init_indirectctx_bb(struct intel_engine_cs
*engine
, u32
*batch
)
1142 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
1143 batch
= gen8_emit_flush_coherentl3_wa(engine
, batch
);
1145 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
1146 *batch
++ = MI_LOAD_REGISTER_IMM(1);
1147 *batch
++ = i915_mmio_reg_offset(COMMON_SLICE_CHICKEN2
);
1148 *batch
++ = _MASKED_BIT_DISABLE(
1149 GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE
);
1152 /* WaClearSlmSpaceAtContextSwitch:kbl */
1153 /* Actual scratch location is at 128 bytes offset */
1154 if (IS_KBL_REVID(engine
->i915
, 0, KBL_REVID_A0
)) {
1155 batch
= gen8_emit_pipe_control(batch
,
1156 PIPE_CONTROL_FLUSH_L3
|
1157 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1158 PIPE_CONTROL_CS_STALL
|
1159 PIPE_CONTROL_QW_WRITE
,
1160 i915_ggtt_offset(engine
->scratch
)
1161 + 2 * CACHELINE_BYTES
);
1164 /* WaMediaPoolStateCmdInWABB:bxt,glk */
1165 if (HAS_POOLED_EU(engine
->i915
)) {
1167 * EU pool configuration is setup along with golden context
1168 * during context initialization. This value depends on
1169 * device type (2x6 or 3x6) and needs to be updated based
1170 * on which subslice is disabled especially for 2x6
1171 * devices, however it is safe to load default
1172 * configuration of 3x6 device instead of masking off
1173 * corresponding bits because HW ignores bits of a disabled
1174 * subslice and drops down to appropriate config. Please
1175 * see render_state_setup() in i915_gem_render_state.c for
1176 * possible configurations, to avoid duplication they are
1177 * not shown here again.
1179 *batch
++ = GEN9_MEDIA_POOL_STATE
;
1180 *batch
++ = GEN9_MEDIA_POOL_ENABLE
;
1181 *batch
++ = 0x00777000;
1187 /* Pad to end of cacheline */
1188 while ((unsigned long)batch
% CACHELINE_BYTES
)
1194 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
1196 static int lrc_setup_wa_ctx(struct intel_engine_cs
*engine
)
1198 struct drm_i915_gem_object
*obj
;
1199 struct i915_vma
*vma
;
1202 obj
= i915_gem_object_create(engine
->i915
, CTX_WA_BB_OBJ_SIZE
);
1204 return PTR_ERR(obj
);
1206 vma
= i915_vma_instance(obj
, &engine
->i915
->ggtt
.base
, NULL
);
1212 err
= i915_vma_pin(vma
, 0, PAGE_SIZE
, PIN_GLOBAL
| PIN_HIGH
);
1216 engine
->wa_ctx
.vma
= vma
;
1220 i915_gem_object_put(obj
);
1224 static void lrc_destroy_wa_ctx(struct intel_engine_cs
*engine
)
1226 i915_vma_unpin_and_release(&engine
->wa_ctx
.vma
);
1229 typedef u32
*(*wa_bb_func_t
)(struct intel_engine_cs
*engine
, u32
*batch
);
1231 static int intel_init_workaround_bb(struct intel_engine_cs
*engine
)
1233 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
1234 struct i915_wa_ctx_bb
*wa_bb
[2] = { &wa_ctx
->indirect_ctx
,
1236 wa_bb_func_t wa_bb_fn
[2];
1238 void *batch
, *batch_ptr
;
1242 if (WARN_ON(engine
->id
!= RCS
|| !engine
->scratch
))
1245 switch (INTEL_GEN(engine
->i915
)) {
1249 wa_bb_fn
[0] = gen9_init_indirectctx_bb
;
1253 wa_bb_fn
[0] = gen8_init_indirectctx_bb
;
1254 wa_bb_fn
[1] = gen8_init_perctx_bb
;
1257 MISSING_CASE(INTEL_GEN(engine
->i915
));
1261 ret
= lrc_setup_wa_ctx(engine
);
1263 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1267 page
= i915_gem_object_get_dirty_page(wa_ctx
->vma
->obj
, 0);
1268 batch
= batch_ptr
= kmap_atomic(page
);
1271 * Emit the two workaround batch buffers, recording the offset from the
1272 * start of the workaround batch buffer object for each and their
1275 for (i
= 0; i
< ARRAY_SIZE(wa_bb_fn
); i
++) {
1276 wa_bb
[i
]->offset
= batch_ptr
- batch
;
1277 if (WARN_ON(!IS_ALIGNED(wa_bb
[i
]->offset
, CACHELINE_BYTES
))) {
1282 batch_ptr
= wa_bb_fn
[i
](engine
, batch_ptr
);
1283 wa_bb
[i
]->size
= batch_ptr
- (batch
+ wa_bb
[i
]->offset
);
1286 BUG_ON(batch_ptr
- batch
> CTX_WA_BB_OBJ_SIZE
);
1288 kunmap_atomic(batch
);
1290 lrc_destroy_wa_ctx(engine
);
1295 static u8 gtiir
[] = {
1303 static int gen8_init_common_ring(struct intel_engine_cs
*engine
)
1305 struct drm_i915_private
*dev_priv
= engine
->i915
;
1306 struct intel_engine_execlists
* const execlists
= &engine
->execlists
;
1309 ret
= intel_mocs_init_engine(engine
);
1313 intel_engine_reset_breadcrumbs(engine
);
1314 intel_engine_init_hangcheck(engine
);
1316 I915_WRITE(RING_HWSTAM(engine
->mmio_base
), 0xffffffff);
1317 I915_WRITE(RING_MODE_GEN7(engine
),
1318 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1319 I915_WRITE(RING_HWS_PGA(engine
->mmio_base
),
1320 engine
->status_page
.ggtt_offset
);
1321 POSTING_READ(RING_HWS_PGA(engine
->mmio_base
));
1323 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine
->name
);
1325 GEM_BUG_ON(engine
->id
>= ARRAY_SIZE(gtiir
));
1328 * Clear any pending interrupt state.
1330 * We do it twice out of paranoia that some of the IIR are double
1331 * buffered, and if we only reset it once there may still be
1332 * an interrupt pending.
1334 I915_WRITE(GEN8_GT_IIR(gtiir
[engine
->id
]),
1335 GT_CONTEXT_SWITCH_INTERRUPT
<< engine
->irq_shift
);
1336 I915_WRITE(GEN8_GT_IIR(gtiir
[engine
->id
]),
1337 GT_CONTEXT_SWITCH_INTERRUPT
<< engine
->irq_shift
);
1338 clear_bit(ENGINE_IRQ_EXECLIST
, &engine
->irq_posted
);
1339 execlists
->csb_head
= -1;
1341 /* After a GPU reset, we may have requests to replay */
1342 if (!i915_modparams
.enable_guc_submission
&& execlists
->first
)
1343 tasklet_schedule(&execlists
->irq_tasklet
);
1348 static int gen8_init_render_ring(struct intel_engine_cs
*engine
)
1350 struct drm_i915_private
*dev_priv
= engine
->i915
;
1353 ret
= gen8_init_common_ring(engine
);
1357 /* We need to disable the AsyncFlip performance optimisations in order
1358 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1359 * programmed to '1' on all products.
1361 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1363 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1365 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1367 return init_workarounds_ring(engine
);
1370 static int gen9_init_render_ring(struct intel_engine_cs
*engine
)
1374 ret
= gen8_init_common_ring(engine
);
1378 return init_workarounds_ring(engine
);
1381 static void reset_common_ring(struct intel_engine_cs
*engine
,
1382 struct drm_i915_gem_request
*request
)
1384 struct intel_engine_execlists
* const execlists
= &engine
->execlists
;
1385 struct drm_i915_gem_request
*rq
, *rn
;
1386 struct intel_context
*ce
;
1387 unsigned long flags
;
1389 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
1392 * Catch up with any missed context-switch interrupts.
1394 * Ideally we would just read the remaining CSB entries now that we
1395 * know the gpu is idle. However, the CSB registers are sometimes^W
1396 * often trashed across a GPU reset! Instead we have to rely on
1397 * guessing the missed context-switch events by looking at what
1398 * requests were completed.
1400 execlist_cancel_port_requests(execlists
);
1402 /* Push back any incomplete requests for replay after the reset. */
1403 list_for_each_entry_safe_reverse(rq
, rn
,
1404 &engine
->timeline
->requests
, link
) {
1405 struct i915_priolist
*p
;
1407 if (i915_gem_request_completed(rq
))
1410 __i915_gem_request_unsubmit(rq
);
1412 p
= lookup_priolist(engine
,
1414 rq
->priotree
.priority
);
1415 list_add(&rq
->priotree
.link
,
1416 &ptr_mask_bits(p
, 1)->requests
);
1419 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
1421 /* If the request was innocent, we leave the request in the ELSP
1422 * and will try to replay it on restarting. The context image may
1423 * have been corrupted by the reset, in which case we may have
1424 * to service a new GPU hang, but more likely we can continue on
1427 * If the request was guilty, we presume the context is corrupt
1428 * and have to at least restore the RING register in the context
1429 * image back to the expected values to skip over the guilty request.
1431 if (!request
|| request
->fence
.error
!= -EIO
)
1434 /* We want a simple context + ring to execute the breadcrumb update.
1435 * We cannot rely on the context being intact across the GPU hang,
1436 * so clear it and rebuild just what we need for the breadcrumb.
1437 * All pending requests for this context will be zapped, and any
1438 * future request will be after userspace has had the opportunity
1439 * to recreate its own state.
1441 ce
= &request
->ctx
->engine
[engine
->id
];
1442 execlists_init_reg_state(ce
->lrc_reg_state
,
1443 request
->ctx
, engine
, ce
->ring
);
1445 /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
1446 ce
->lrc_reg_state
[CTX_RING_BUFFER_START
+1] =
1447 i915_ggtt_offset(ce
->ring
->vma
);
1448 ce
->lrc_reg_state
[CTX_RING_HEAD
+1] = request
->postfix
;
1450 request
->ring
->head
= request
->postfix
;
1451 intel_ring_update_space(request
->ring
);
1453 /* Reset WaIdleLiteRestore:bdw,skl as well */
1455 intel_ring_wrap(request
->ring
,
1456 request
->wa_tail
- WA_TAIL_DWORDS
*sizeof(u32
));
1457 assert_ring_tail_valid(request
->ring
, request
->tail
);
1460 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1462 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1463 struct intel_engine_cs
*engine
= req
->engine
;
1464 const int num_lri_cmds
= GEN8_3LVL_PDPES
* 2;
1468 cs
= intel_ring_begin(req
, num_lri_cmds
* 2 + 2);
1472 *cs
++ = MI_LOAD_REGISTER_IMM(num_lri_cmds
);
1473 for (i
= GEN8_3LVL_PDPES
- 1; i
>= 0; i
--) {
1474 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1476 *cs
++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine
, i
));
1477 *cs
++ = upper_32_bits(pd_daddr
);
1478 *cs
++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine
, i
));
1479 *cs
++ = lower_32_bits(pd_daddr
);
1483 intel_ring_advance(req
, cs
);
1488 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1489 u64 offset
, u32 len
,
1490 const unsigned int flags
)
1495 /* Don't rely in hw updating PDPs, specially in lite-restore.
1496 * Ideally, we should set Force PD Restore in ctx descriptor,
1497 * but we can't. Force Restore would be a second option, but
1498 * it is unsafe in case of lite-restore (because the ctx is
1499 * not idle). PML4 is allocated during ppgtt init so this is
1500 * not needed in 48-bit.*/
1501 if (req
->ctx
->ppgtt
&&
1502 (intel_engine_flag(req
->engine
) & req
->ctx
->ppgtt
->pd_dirty_rings
) &&
1503 !i915_vm_is_48bit(&req
->ctx
->ppgtt
->base
) &&
1504 !intel_vgpu_active(req
->i915
)) {
1505 ret
= intel_logical_ring_emit_pdps(req
);
1509 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(req
->engine
);
1512 cs
= intel_ring_begin(req
, 4);
1516 /* FIXME(BDW): Address space and security selectors. */
1517 *cs
++ = MI_BATCH_BUFFER_START_GEN8
|
1518 (flags
& I915_DISPATCH_SECURE
? 0 : BIT(8)) |
1519 (flags
& I915_DISPATCH_RS
? MI_BATCH_RESOURCE_STREAMER
: 0);
1520 *cs
++ = lower_32_bits(offset
);
1521 *cs
++ = upper_32_bits(offset
);
1523 intel_ring_advance(req
, cs
);
1528 static void gen8_logical_ring_enable_irq(struct intel_engine_cs
*engine
)
1530 struct drm_i915_private
*dev_priv
= engine
->i915
;
1531 I915_WRITE_IMR(engine
,
1532 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1533 POSTING_READ_FW(RING_IMR(engine
->mmio_base
));
1536 static void gen8_logical_ring_disable_irq(struct intel_engine_cs
*engine
)
1538 struct drm_i915_private
*dev_priv
= engine
->i915
;
1539 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1542 static int gen8_emit_flush(struct drm_i915_gem_request
*request
, u32 mode
)
1546 cs
= intel_ring_begin(request
, 4);
1550 cmd
= MI_FLUSH_DW
+ 1;
1552 /* We always require a command barrier so that subsequent
1553 * commands, such as breadcrumb interrupts, are strictly ordered
1554 * wrt the contents of the write cache being flushed to memory
1555 * (and thus being coherent from the CPU).
1557 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1559 if (mode
& EMIT_INVALIDATE
) {
1560 cmd
|= MI_INVALIDATE_TLB
;
1561 if (request
->engine
->id
== VCS
)
1562 cmd
|= MI_INVALIDATE_BSD
;
1566 *cs
++ = I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
;
1567 *cs
++ = 0; /* upper addr */
1568 *cs
++ = 0; /* value */
1569 intel_ring_advance(request
, cs
);
1574 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1577 struct intel_engine_cs
*engine
= request
->engine
;
1579 i915_ggtt_offset(engine
->scratch
) + 2 * CACHELINE_BYTES
;
1580 bool vf_flush_wa
= false, dc_flush_wa
= false;
1584 flags
|= PIPE_CONTROL_CS_STALL
;
1586 if (mode
& EMIT_FLUSH
) {
1587 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1588 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1589 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
1590 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
1593 if (mode
& EMIT_INVALIDATE
) {
1594 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1595 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1596 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1597 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1598 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1599 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1600 flags
|= PIPE_CONTROL_QW_WRITE
;
1601 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1604 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1607 if (IS_GEN9(request
->i915
))
1610 /* WaForGAMHang:kbl */
1611 if (IS_KBL_REVID(request
->i915
, 0, KBL_REVID_B0
))
1623 cs
= intel_ring_begin(request
, len
);
1628 cs
= gen8_emit_pipe_control(cs
, 0, 0);
1631 cs
= gen8_emit_pipe_control(cs
, PIPE_CONTROL_DC_FLUSH_ENABLE
,
1634 cs
= gen8_emit_pipe_control(cs
, flags
, scratch_addr
);
1637 cs
= gen8_emit_pipe_control(cs
, PIPE_CONTROL_CS_STALL
, 0);
1639 intel_ring_advance(request
, cs
);
1645 * Reserve space for 2 NOOPs at the end of each request to be
1646 * used as a workaround for not being allowed to do lite
1647 * restore with HEAD==TAIL (WaIdleLiteRestore).
1649 static void gen8_emit_wa_tail(struct drm_i915_gem_request
*request
, u32
*cs
)
1653 request
->wa_tail
= intel_ring_offset(request
, cs
);
1656 static void gen8_emit_breadcrumb(struct drm_i915_gem_request
*request
, u32
*cs
)
1658 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1659 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR
& (1 << 5));
1661 *cs
++ = (MI_FLUSH_DW
+ 1) | MI_FLUSH_DW_OP_STOREDW
;
1662 *cs
++ = intel_hws_seqno_address(request
->engine
) | MI_FLUSH_DW_USE_GTT
;
1664 *cs
++ = request
->global_seqno
;
1665 *cs
++ = MI_USER_INTERRUPT
;
1667 request
->tail
= intel_ring_offset(request
, cs
);
1668 assert_ring_tail_valid(request
->ring
, request
->tail
);
1670 gen8_emit_wa_tail(request
, cs
);
1673 static const int gen8_emit_breadcrumb_sz
= 6 + WA_TAIL_DWORDS
;
1675 static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request
*request
,
1678 /* We're using qword write, seqno should be aligned to 8 bytes. */
1679 BUILD_BUG_ON(I915_GEM_HWS_INDEX
& 1);
1681 /* w/a for post sync ops following a GPGPU operation we
1682 * need a prior CS_STALL, which is emitted by the flush
1683 * following the batch.
1685 *cs
++ = GFX_OP_PIPE_CONTROL(6);
1686 *cs
++ = PIPE_CONTROL_GLOBAL_GTT_IVB
| PIPE_CONTROL_CS_STALL
|
1687 PIPE_CONTROL_QW_WRITE
;
1688 *cs
++ = intel_hws_seqno_address(request
->engine
);
1690 *cs
++ = request
->global_seqno
;
1691 /* We're thrashing one dword of HWS. */
1693 *cs
++ = MI_USER_INTERRUPT
;
1695 request
->tail
= intel_ring_offset(request
, cs
);
1696 assert_ring_tail_valid(request
->ring
, request
->tail
);
1698 gen8_emit_wa_tail(request
, cs
);
1701 static const int gen8_emit_breadcrumb_render_sz
= 8 + WA_TAIL_DWORDS
;
1703 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
1707 ret
= intel_ring_workarounds_emit(req
);
1711 ret
= intel_rcs_context_init_mocs(req
);
1713 * Failing to program the MOCS is non-fatal.The system will not
1714 * run at peak performance. So generate an error and carry on.
1717 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1719 return i915_gem_render_state_emit(req
);
1723 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1724 * @engine: Engine Command Streamer.
1726 void intel_logical_ring_cleanup(struct intel_engine_cs
*engine
)
1728 struct drm_i915_private
*dev_priv
;
1731 * Tasklet cannot be active at this point due intel_mark_active/idle
1732 * so this is just for documentation.
1734 if (WARN_ON(test_bit(TASKLET_STATE_SCHED
, &engine
->execlists
.irq_tasklet
.state
)))
1735 tasklet_kill(&engine
->execlists
.irq_tasklet
);
1737 dev_priv
= engine
->i915
;
1739 if (engine
->buffer
) {
1740 WARN_ON((I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
1743 if (engine
->cleanup
)
1744 engine
->cleanup(engine
);
1746 intel_engine_cleanup_common(engine
);
1748 lrc_destroy_wa_ctx(engine
);
1749 engine
->i915
= NULL
;
1750 dev_priv
->engine
[engine
->id
] = NULL
;
1754 static void execlists_set_default_submission(struct intel_engine_cs
*engine
)
1756 engine
->submit_request
= execlists_submit_request
;
1757 engine
->cancel_requests
= execlists_cancel_requests
;
1758 engine
->schedule
= execlists_schedule
;
1759 engine
->execlists
.irq_tasklet
.func
= intel_lrc_irq_handler
;
1763 logical_ring_default_vfuncs(struct intel_engine_cs
*engine
)
1765 /* Default vfuncs which can be overriden by each engine. */
1766 engine
->init_hw
= gen8_init_common_ring
;
1767 engine
->reset_hw
= reset_common_ring
;
1769 engine
->context_pin
= execlists_context_pin
;
1770 engine
->context_unpin
= execlists_context_unpin
;
1772 engine
->request_alloc
= execlists_request_alloc
;
1774 engine
->emit_flush
= gen8_emit_flush
;
1775 engine
->emit_breadcrumb
= gen8_emit_breadcrumb
;
1776 engine
->emit_breadcrumb_sz
= gen8_emit_breadcrumb_sz
;
1778 engine
->set_default_submission
= execlists_set_default_submission
;
1780 engine
->irq_enable
= gen8_logical_ring_enable_irq
;
1781 engine
->irq_disable
= gen8_logical_ring_disable_irq
;
1782 engine
->emit_bb_start
= gen8_emit_bb_start
;
1786 logical_ring_default_irqs(struct intel_engine_cs
*engine
)
1788 unsigned shift
= engine
->irq_shift
;
1789 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
<< shift
;
1790 engine
->irq_keep_mask
= GT_CONTEXT_SWITCH_INTERRUPT
<< shift
;
1794 logical_ring_setup(struct intel_engine_cs
*engine
)
1796 struct drm_i915_private
*dev_priv
= engine
->i915
;
1797 enum forcewake_domains fw_domains
;
1799 intel_engine_setup_common(engine
);
1801 /* Intentionally left blank. */
1802 engine
->buffer
= NULL
;
1804 fw_domains
= intel_uncore_forcewake_for_reg(dev_priv
,
1808 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
1809 RING_CONTEXT_STATUS_PTR(engine
),
1810 FW_REG_READ
| FW_REG_WRITE
);
1812 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
1813 RING_CONTEXT_STATUS_BUF_BASE(engine
),
1816 engine
->execlists
.fw_domains
= fw_domains
;
1818 tasklet_init(&engine
->execlists
.irq_tasklet
,
1819 intel_lrc_irq_handler
, (unsigned long)engine
);
1821 logical_ring_default_vfuncs(engine
);
1822 logical_ring_default_irqs(engine
);
1825 static int logical_ring_init(struct intel_engine_cs
*engine
)
1829 ret
= intel_engine_init_common(engine
);
1836 intel_logical_ring_cleanup(engine
);
1840 int logical_render_ring_init(struct intel_engine_cs
*engine
)
1842 struct drm_i915_private
*dev_priv
= engine
->i915
;
1845 logical_ring_setup(engine
);
1847 if (HAS_L3_DPF(dev_priv
))
1848 engine
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
1850 /* Override some for render ring. */
1851 if (INTEL_GEN(dev_priv
) >= 9)
1852 engine
->init_hw
= gen9_init_render_ring
;
1854 engine
->init_hw
= gen8_init_render_ring
;
1855 engine
->init_context
= gen8_init_rcs_context
;
1856 engine
->emit_flush
= gen8_emit_flush_render
;
1857 engine
->emit_breadcrumb
= gen8_emit_breadcrumb_render
;
1858 engine
->emit_breadcrumb_sz
= gen8_emit_breadcrumb_render_sz
;
1860 ret
= intel_engine_create_scratch(engine
, PAGE_SIZE
);
1864 ret
= intel_init_workaround_bb(engine
);
1867 * We continue even if we fail to initialize WA batch
1868 * because we only expect rare glitches but nothing
1869 * critical to prevent us from using GPU
1871 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1875 return logical_ring_init(engine
);
1878 int logical_xcs_ring_init(struct intel_engine_cs
*engine
)
1880 logical_ring_setup(engine
);
1882 return logical_ring_init(engine
);
1886 make_rpcs(struct drm_i915_private
*dev_priv
)
1891 * No explicit RPCS request is needed to ensure full
1892 * slice/subslice/EU enablement prior to Gen9.
1894 if (INTEL_GEN(dev_priv
) < 9)
1898 * Starting in Gen9, render power gating can leave
1899 * slice/subslice/EU in a partially enabled state. We
1900 * must make an explicit request through RPCS for full
1903 if (INTEL_INFO(dev_priv
)->sseu
.has_slice_pg
) {
1904 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
1905 rpcs
|= hweight8(INTEL_INFO(dev_priv
)->sseu
.slice_mask
) <<
1906 GEN8_RPCS_S_CNT_SHIFT
;
1907 rpcs
|= GEN8_RPCS_ENABLE
;
1910 if (INTEL_INFO(dev_priv
)->sseu
.has_subslice_pg
) {
1911 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
1912 rpcs
|= hweight8(INTEL_INFO(dev_priv
)->sseu
.subslice_mask
) <<
1913 GEN8_RPCS_SS_CNT_SHIFT
;
1914 rpcs
|= GEN8_RPCS_ENABLE
;
1917 if (INTEL_INFO(dev_priv
)->sseu
.has_eu_pg
) {
1918 rpcs
|= INTEL_INFO(dev_priv
)->sseu
.eu_per_subslice
<<
1919 GEN8_RPCS_EU_MIN_SHIFT
;
1920 rpcs
|= INTEL_INFO(dev_priv
)->sseu
.eu_per_subslice
<<
1921 GEN8_RPCS_EU_MAX_SHIFT
;
1922 rpcs
|= GEN8_RPCS_ENABLE
;
1928 static u32
intel_lr_indirect_ctx_offset(struct intel_engine_cs
*engine
)
1930 u32 indirect_ctx_offset
;
1932 switch (INTEL_GEN(engine
->i915
)) {
1934 MISSING_CASE(INTEL_GEN(engine
->i915
));
1937 indirect_ctx_offset
=
1938 GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
1941 indirect_ctx_offset
=
1942 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
1945 indirect_ctx_offset
=
1946 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
1950 return indirect_ctx_offset
;
1953 static void execlists_init_reg_state(u32
*regs
,
1954 struct i915_gem_context
*ctx
,
1955 struct intel_engine_cs
*engine
,
1956 struct intel_ring
*ring
)
1958 struct drm_i915_private
*dev_priv
= engine
->i915
;
1959 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
?: dev_priv
->mm
.aliasing_ppgtt
;
1960 u32 base
= engine
->mmio_base
;
1961 bool rcs
= engine
->id
== RCS
;
1963 /* A context is actually a big batch buffer with several
1964 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
1965 * values we are setting here are only for the first context restore:
1966 * on a subsequent save, the GPU will recreate this batchbuffer with new
1967 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
1968 * we are not initializing here).
1970 regs
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(rcs
? 14 : 11) |
1971 MI_LRI_FORCE_POSTED
;
1973 CTX_REG(regs
, CTX_CONTEXT_CONTROL
, RING_CONTEXT_CONTROL(engine
),
1974 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
1975 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
1976 (HAS_RESOURCE_STREAMER(dev_priv
) ?
1977 CTX_CTRL_RS_CTX_ENABLE
: 0)));
1978 CTX_REG(regs
, CTX_RING_HEAD
, RING_HEAD(base
), 0);
1979 CTX_REG(regs
, CTX_RING_TAIL
, RING_TAIL(base
), 0);
1980 CTX_REG(regs
, CTX_RING_BUFFER_START
, RING_START(base
), 0);
1981 CTX_REG(regs
, CTX_RING_BUFFER_CONTROL
, RING_CTL(base
),
1982 RING_CTL_SIZE(ring
->size
) | RING_VALID
);
1983 CTX_REG(regs
, CTX_BB_HEAD_U
, RING_BBADDR_UDW(base
), 0);
1984 CTX_REG(regs
, CTX_BB_HEAD_L
, RING_BBADDR(base
), 0);
1985 CTX_REG(regs
, CTX_BB_STATE
, RING_BBSTATE(base
), RING_BB_PPGTT
);
1986 CTX_REG(regs
, CTX_SECOND_BB_HEAD_U
, RING_SBBADDR_UDW(base
), 0);
1987 CTX_REG(regs
, CTX_SECOND_BB_HEAD_L
, RING_SBBADDR(base
), 0);
1988 CTX_REG(regs
, CTX_SECOND_BB_STATE
, RING_SBBSTATE(base
), 0);
1990 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
1992 CTX_REG(regs
, CTX_RCS_INDIRECT_CTX
, RING_INDIRECT_CTX(base
), 0);
1993 CTX_REG(regs
, CTX_RCS_INDIRECT_CTX_OFFSET
,
1994 RING_INDIRECT_CTX_OFFSET(base
), 0);
1995 if (wa_ctx
->indirect_ctx
.size
) {
1996 u32 ggtt_offset
= i915_ggtt_offset(wa_ctx
->vma
);
1998 regs
[CTX_RCS_INDIRECT_CTX
+ 1] =
1999 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
) |
2000 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_BYTES
);
2002 regs
[CTX_RCS_INDIRECT_CTX_OFFSET
+ 1] =
2003 intel_lr_indirect_ctx_offset(engine
) << 6;
2006 CTX_REG(regs
, CTX_BB_PER_CTX_PTR
, RING_BB_PER_CTX_PTR(base
), 0);
2007 if (wa_ctx
->per_ctx
.size
) {
2008 u32 ggtt_offset
= i915_ggtt_offset(wa_ctx
->vma
);
2010 regs
[CTX_BB_PER_CTX_PTR
+ 1] =
2011 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
) | 0x01;
2015 regs
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED
;
2017 CTX_REG(regs
, CTX_CTX_TIMESTAMP
, RING_CTX_TIMESTAMP(base
), 0);
2018 /* PDP values well be assigned later if needed */
2019 CTX_REG(regs
, CTX_PDP3_UDW
, GEN8_RING_PDP_UDW(engine
, 3), 0);
2020 CTX_REG(regs
, CTX_PDP3_LDW
, GEN8_RING_PDP_LDW(engine
, 3), 0);
2021 CTX_REG(regs
, CTX_PDP2_UDW
, GEN8_RING_PDP_UDW(engine
, 2), 0);
2022 CTX_REG(regs
, CTX_PDP2_LDW
, GEN8_RING_PDP_LDW(engine
, 2), 0);
2023 CTX_REG(regs
, CTX_PDP1_UDW
, GEN8_RING_PDP_UDW(engine
, 1), 0);
2024 CTX_REG(regs
, CTX_PDP1_LDW
, GEN8_RING_PDP_LDW(engine
, 1), 0);
2025 CTX_REG(regs
, CTX_PDP0_UDW
, GEN8_RING_PDP_UDW(engine
, 0), 0);
2026 CTX_REG(regs
, CTX_PDP0_LDW
, GEN8_RING_PDP_LDW(engine
, 0), 0);
2028 if (ppgtt
&& i915_vm_is_48bit(&ppgtt
->base
)) {
2029 /* 64b PPGTT (48bit canonical)
2030 * PDP0_DESCRIPTOR contains the base address to PML4 and
2031 * other PDP Descriptors are ignored.
2033 ASSIGN_CTX_PML4(ppgtt
, regs
);
2037 regs
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
2038 CTX_REG(regs
, CTX_R_PWR_CLK_STATE
, GEN8_R_PWR_CLK_STATE
,
2039 make_rpcs(dev_priv
));
2041 i915_oa_init_reg_state(engine
, ctx
, regs
);
2046 populate_lr_context(struct i915_gem_context
*ctx
,
2047 struct drm_i915_gem_object
*ctx_obj
,
2048 struct intel_engine_cs
*engine
,
2049 struct intel_ring
*ring
)
2054 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
2056 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2060 vaddr
= i915_gem_object_pin_map(ctx_obj
, I915_MAP_WB
);
2061 if (IS_ERR(vaddr
)) {
2062 ret
= PTR_ERR(vaddr
);
2063 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret
);
2066 ctx_obj
->mm
.dirty
= true;
2068 /* The second page of the context object contains some fields which must
2069 * be set up prior to the first execution. */
2071 execlists_init_reg_state(vaddr
+ LRC_STATE_PN
* PAGE_SIZE
,
2074 i915_gem_object_unpin_map(ctx_obj
);
2079 static int execlists_context_deferred_alloc(struct i915_gem_context
*ctx
,
2080 struct intel_engine_cs
*engine
)
2082 struct drm_i915_gem_object
*ctx_obj
;
2083 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2084 struct i915_vma
*vma
;
2085 uint32_t context_size
;
2086 struct intel_ring
*ring
;
2091 context_size
= round_up(engine
->context_size
, I915_GTT_PAGE_SIZE
);
2094 * Before the actual start of the context image, we insert a few pages
2095 * for our own use and for sharing with the GuC.
2097 context_size
+= LRC_HEADER_PAGES
* PAGE_SIZE
;
2099 ctx_obj
= i915_gem_object_create(ctx
->i915
, context_size
);
2100 if (IS_ERR(ctx_obj
)) {
2101 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2102 return PTR_ERR(ctx_obj
);
2105 vma
= i915_vma_instance(ctx_obj
, &ctx
->i915
->ggtt
.base
, NULL
);
2108 goto error_deref_obj
;
2111 ring
= intel_engine_create_ring(engine
, ctx
->ring_size
);
2113 ret
= PTR_ERR(ring
);
2114 goto error_deref_obj
;
2117 ret
= populate_lr_context(ctx
, ctx_obj
, engine
, ring
);
2119 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2120 goto error_ring_free
;
2125 ce
->initialised
|= engine
->init_context
== NULL
;
2130 intel_ring_free(ring
);
2132 i915_gem_object_put(ctx_obj
);
2136 void intel_lr_context_resume(struct drm_i915_private
*dev_priv
)
2138 struct intel_engine_cs
*engine
;
2139 struct i915_gem_context
*ctx
;
2140 enum intel_engine_id id
;
2142 /* Because we emit WA_TAIL_DWORDS there may be a disparity
2143 * between our bookkeeping in ce->ring->head and ce->ring->tail and
2144 * that stored in context. As we only write new commands from
2145 * ce->ring->tail onwards, everything before that is junk. If the GPU
2146 * starts reading from its RING_HEAD from the context, it may try to
2147 * execute that junk and die.
2149 * So to avoid that we reset the context images upon resume. For
2150 * simplicity, we just zero everything out.
2152 list_for_each_entry(ctx
, &dev_priv
->contexts
.list
, link
) {
2153 for_each_engine(engine
, dev_priv
, id
) {
2154 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2160 reg
= i915_gem_object_pin_map(ce
->state
->obj
,
2162 if (WARN_ON(IS_ERR(reg
)))
2165 reg
+= LRC_STATE_PN
* PAGE_SIZE
/ sizeof(*reg
);
2166 reg
[CTX_RING_HEAD
+1] = 0;
2167 reg
[CTX_RING_TAIL
+1] = 0;
2169 ce
->state
->obj
->mm
.dirty
= true;
2170 i915_gem_object_unpin_map(ce
->state
->obj
);
2172 intel_ring_reset(ce
->ring
, 0);