2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
139 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
140 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
143 #define RING_EXECLIST_QFULL (1 << 0x2)
144 #define RING_EXECLIST1_VALID (1 << 0x3)
145 #define RING_EXECLIST0_VALID (1 << 0x4)
146 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
147 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
148 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
150 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
151 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
152 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
153 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
154 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
155 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
157 #define CTX_LRI_HEADER_0 0x01
158 #define CTX_CONTEXT_CONTROL 0x02
159 #define CTX_RING_HEAD 0x04
160 #define CTX_RING_TAIL 0x06
161 #define CTX_RING_BUFFER_START 0x08
162 #define CTX_RING_BUFFER_CONTROL 0x0a
163 #define CTX_BB_HEAD_U 0x0c
164 #define CTX_BB_HEAD_L 0x0e
165 #define CTX_BB_STATE 0x10
166 #define CTX_SECOND_BB_HEAD_U 0x12
167 #define CTX_SECOND_BB_HEAD_L 0x14
168 #define CTX_SECOND_BB_STATE 0x16
169 #define CTX_BB_PER_CTX_PTR 0x18
170 #define CTX_RCS_INDIRECT_CTX 0x1a
171 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
172 #define CTX_LRI_HEADER_1 0x21
173 #define CTX_CTX_TIMESTAMP 0x22
174 #define CTX_PDP3_UDW 0x24
175 #define CTX_PDP3_LDW 0x26
176 #define CTX_PDP2_UDW 0x28
177 #define CTX_PDP2_LDW 0x2a
178 #define CTX_PDP1_UDW 0x2c
179 #define CTX_PDP1_LDW 0x2e
180 #define CTX_PDP0_UDW 0x30
181 #define CTX_PDP0_LDW 0x32
182 #define CTX_LRI_HEADER_2 0x41
183 #define CTX_R_PWR_CLK_STATE 0x42
184 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
186 #define GEN8_CTX_VALID (1<<0)
187 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
188 #define GEN8_CTX_FORCE_RESTORE (1<<2)
189 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
190 #define GEN8_CTX_PRIVILEGE (1<<8)
192 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
193 const u64 _addr = test_bit(n, ppgtt->pdp.used_pdpes) ? \
194 ppgtt->pdp.page_directory[n]->daddr : \
195 ppgtt->scratch_pd->daddr; \
196 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
197 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
201 ADVANCED_CONTEXT
= 0,
206 #define GEN8_CTX_MODE_SHIFT 3
209 FAULT_AND_HALT
, /* Debug only */
211 FAULT_AND_CONTINUE
/* Unsupported */
213 #define GEN8_CTX_ID_SHIFT 32
215 static int intel_lr_context_pin(struct intel_engine_cs
*ring
,
216 struct intel_context
*ctx
);
219 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
221 * @enable_execlists: value of i915.enable_execlists module parameter.
223 * Only certain platforms support Execlists (the prerequisites being
224 * support for Logical Ring Contexts and Aliasing PPGTT or better).
226 * Return: 1 if Execlists is supported and has to be enabled.
228 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
)
230 WARN_ON(i915
.enable_ppgtt
== -1);
232 if (INTEL_INFO(dev
)->gen
>= 9)
235 if (enable_execlists
== 0)
238 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && USES_PPGTT(dev
) &&
239 i915
.use_mmio_flip
>= 0)
246 * intel_execlists_ctx_id() - get the Execlists Context ID
247 * @ctx_obj: Logical Ring Context backing object.
249 * Do not confuse with ctx->id! Unfortunately we have a name overload
250 * here: the old context ID we pass to userspace as a handler so that
251 * they can refer to a context, and the new context ID we pass to the
252 * ELSP so that the GPU can inform us of the context status via
255 * Return: 20-bits globally unique context ID.
257 u32
intel_execlists_ctx_id(struct drm_i915_gem_object
*ctx_obj
)
259 u32 lrca
= i915_gem_obj_ggtt_offset(ctx_obj
);
261 /* LRCA is required to be 4K aligned so the more significant 20 bits
262 * are globally unique */
266 static uint64_t execlists_ctx_descriptor(struct intel_engine_cs
*ring
,
267 struct drm_i915_gem_object
*ctx_obj
)
269 struct drm_device
*dev
= ring
->dev
;
271 uint64_t lrca
= i915_gem_obj_ggtt_offset(ctx_obj
);
273 WARN_ON(lrca
& 0xFFFFFFFF00000FFFULL
);
275 desc
= GEN8_CTX_VALID
;
276 desc
|= LEGACY_CONTEXT
<< GEN8_CTX_MODE_SHIFT
;
277 if (IS_GEN8(ctx_obj
->base
.dev
))
278 desc
|= GEN8_CTX_L3LLC_COHERENT
;
279 desc
|= GEN8_CTX_PRIVILEGE
;
281 desc
|= (u64
)intel_execlists_ctx_id(ctx_obj
) << GEN8_CTX_ID_SHIFT
;
283 /* TODO: WaDisableLiteRestore when we start using semaphore
284 * signalling between Command Streamers */
285 /* desc |= GEN8_CTX_FORCE_RESTORE; */
287 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
289 INTEL_REVID(dev
) <= SKL_REVID_B0
&&
290 (ring
->id
== BCS
|| ring
->id
== VCS
||
291 ring
->id
== VECS
|| ring
->id
== VCS2
))
292 desc
|= GEN8_CTX_FORCE_RESTORE
;
297 static void execlists_elsp_write(struct intel_engine_cs
*ring
,
298 struct drm_i915_gem_object
*ctx_obj0
,
299 struct drm_i915_gem_object
*ctx_obj1
)
301 struct drm_device
*dev
= ring
->dev
;
302 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
306 /* XXX: You must always write both descriptors in the order below. */
308 temp
= execlists_ctx_descriptor(ring
, ctx_obj1
);
311 desc
[1] = (u32
)(temp
>> 32);
314 temp
= execlists_ctx_descriptor(ring
, ctx_obj0
);
315 desc
[3] = (u32
)(temp
>> 32);
318 spin_lock(&dev_priv
->uncore
.lock
);
319 intel_uncore_forcewake_get__locked(dev_priv
, FORCEWAKE_ALL
);
320 I915_WRITE_FW(RING_ELSP(ring
), desc
[1]);
321 I915_WRITE_FW(RING_ELSP(ring
), desc
[0]);
322 I915_WRITE_FW(RING_ELSP(ring
), desc
[3]);
324 /* The context is automatically loaded after the following */
325 I915_WRITE_FW(RING_ELSP(ring
), desc
[2]);
327 /* ELSP is a wo register, so use another nearby reg for posting instead */
328 POSTING_READ_FW(RING_EXECLIST_STATUS(ring
));
329 intel_uncore_forcewake_put__locked(dev_priv
, FORCEWAKE_ALL
);
330 spin_unlock(&dev_priv
->uncore
.lock
);
333 static int execlists_update_context(struct drm_i915_gem_object
*ctx_obj
,
334 struct drm_i915_gem_object
*ring_obj
,
335 struct i915_hw_ppgtt
*ppgtt
,
341 page
= i915_gem_object_get_page(ctx_obj
, 1);
342 reg_state
= kmap_atomic(page
);
344 reg_state
[CTX_RING_TAIL
+1] = tail
;
345 reg_state
[CTX_RING_BUFFER_START
+1] = i915_gem_obj_ggtt_offset(ring_obj
);
347 /* True PPGTT with dynamic page allocation: update PDP registers and
348 * point the unallocated PDPs to the scratch page
351 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
352 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
353 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
354 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
357 kunmap_atomic(reg_state
);
362 static void execlists_submit_contexts(struct intel_engine_cs
*ring
,
363 struct intel_context
*to0
, u32 tail0
,
364 struct intel_context
*to1
, u32 tail1
)
366 struct drm_i915_gem_object
*ctx_obj0
= to0
->engine
[ring
->id
].state
;
367 struct intel_ringbuffer
*ringbuf0
= to0
->engine
[ring
->id
].ringbuf
;
368 struct drm_i915_gem_object
*ctx_obj1
= NULL
;
369 struct intel_ringbuffer
*ringbuf1
= NULL
;
372 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0
));
373 WARN_ON(!i915_gem_obj_is_pinned(ringbuf0
->obj
));
375 execlists_update_context(ctx_obj0
, ringbuf0
->obj
, to0
->ppgtt
, tail0
);
378 ringbuf1
= to1
->engine
[ring
->id
].ringbuf
;
379 ctx_obj1
= to1
->engine
[ring
->id
].state
;
381 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1
));
382 WARN_ON(!i915_gem_obj_is_pinned(ringbuf1
->obj
));
384 execlists_update_context(ctx_obj1
, ringbuf1
->obj
, to1
->ppgtt
, tail1
);
387 execlists_elsp_write(ring
, ctx_obj0
, ctx_obj1
);
390 static void execlists_context_unqueue(struct intel_engine_cs
*ring
)
392 struct drm_i915_gem_request
*req0
= NULL
, *req1
= NULL
;
393 struct drm_i915_gem_request
*cursor
= NULL
, *tmp
= NULL
;
395 assert_spin_locked(&ring
->execlist_lock
);
398 * If irqs are not active generate a warning as batches that finish
399 * without the irqs may get lost and a GPU Hang may occur.
401 WARN_ON(!intel_irqs_enabled(ring
->dev
->dev_private
));
403 if (list_empty(&ring
->execlist_queue
))
406 /* Try to read in pairs */
407 list_for_each_entry_safe(cursor
, tmp
, &ring
->execlist_queue
,
411 } else if (req0
->ctx
== cursor
->ctx
) {
412 /* Same ctx: ignore first request, as second request
413 * will update tail past first request's workload */
414 cursor
->elsp_submitted
= req0
->elsp_submitted
;
415 list_del(&req0
->execlist_link
);
416 list_add_tail(&req0
->execlist_link
,
417 &ring
->execlist_retired_req_list
);
425 if (IS_GEN8(ring
->dev
) || IS_GEN9(ring
->dev
)) {
427 * WaIdleLiteRestore: make sure we never cause a lite
428 * restore with HEAD==TAIL
430 if (req0
->elsp_submitted
) {
432 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
433 * as we resubmit the request. See gen8_emit_request()
434 * for where we prepare the padding after the end of the
437 struct intel_ringbuffer
*ringbuf
;
439 ringbuf
= req0
->ctx
->engine
[ring
->id
].ringbuf
;
441 req0
->tail
&= ringbuf
->size
- 1;
445 WARN_ON(req1
&& req1
->elsp_submitted
);
447 execlists_submit_contexts(ring
, req0
->ctx
, req0
->tail
,
448 req1
? req1
->ctx
: NULL
,
449 req1
? req1
->tail
: 0);
451 req0
->elsp_submitted
++;
453 req1
->elsp_submitted
++;
456 static bool execlists_check_remove_request(struct intel_engine_cs
*ring
,
459 struct drm_i915_gem_request
*head_req
;
461 assert_spin_locked(&ring
->execlist_lock
);
463 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
464 struct drm_i915_gem_request
,
467 if (head_req
!= NULL
) {
468 struct drm_i915_gem_object
*ctx_obj
=
469 head_req
->ctx
->engine
[ring
->id
].state
;
470 if (intel_execlists_ctx_id(ctx_obj
) == request_id
) {
471 WARN(head_req
->elsp_submitted
== 0,
472 "Never submitted head request\n");
474 if (--head_req
->elsp_submitted
<= 0) {
475 list_del(&head_req
->execlist_link
);
476 list_add_tail(&head_req
->execlist_link
,
477 &ring
->execlist_retired_req_list
);
487 * intel_lrc_irq_handler() - handle Context Switch interrupts
488 * @ring: Engine Command Streamer to handle.
490 * Check the unread Context Status Buffers and manage the submission of new
491 * contexts to the ELSP accordingly.
493 void intel_lrc_irq_handler(struct intel_engine_cs
*ring
)
495 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
501 u32 submit_contexts
= 0;
503 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
505 read_pointer
= ring
->next_context_status_buffer
;
506 write_pointer
= status_pointer
& 0x07;
507 if (read_pointer
> write_pointer
)
510 spin_lock(&ring
->execlist_lock
);
512 while (read_pointer
< write_pointer
) {
514 status
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
515 (read_pointer
% 6) * 8);
516 status_id
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
517 (read_pointer
% 6) * 8 + 4);
519 if (status
& GEN8_CTX_STATUS_PREEMPTED
) {
520 if (status
& GEN8_CTX_STATUS_LITE_RESTORE
) {
521 if (execlists_check_remove_request(ring
, status_id
))
522 WARN(1, "Lite Restored request removed from queue\n");
524 WARN(1, "Preemption without Lite Restore\n");
527 if ((status
& GEN8_CTX_STATUS_ACTIVE_IDLE
) ||
528 (status
& GEN8_CTX_STATUS_ELEMENT_SWITCH
)) {
529 if (execlists_check_remove_request(ring
, status_id
))
534 if (submit_contexts
!= 0)
535 execlists_context_unqueue(ring
);
537 spin_unlock(&ring
->execlist_lock
);
539 WARN(submit_contexts
> 2, "More than two context complete events?\n");
540 ring
->next_context_status_buffer
= write_pointer
% 6;
542 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring
),
543 ((u32
)ring
->next_context_status_buffer
& 0x07) << 8);
546 static int execlists_context_queue(struct intel_engine_cs
*ring
,
547 struct intel_context
*to
,
549 struct drm_i915_gem_request
*request
)
551 struct drm_i915_gem_request
*cursor
;
552 int num_elements
= 0;
554 if (to
!= ring
->default_context
)
555 intel_lr_context_pin(ring
, to
);
559 * If there isn't a request associated with this submission,
560 * create one as a temporary holder.
562 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
565 request
->ring
= ring
;
567 kref_init(&request
->ref
);
568 i915_gem_context_reference(request
->ctx
);
570 i915_gem_request_reference(request
);
571 WARN_ON(to
!= request
->ctx
);
573 request
->tail
= tail
;
575 spin_lock_irq(&ring
->execlist_lock
);
577 list_for_each_entry(cursor
, &ring
->execlist_queue
, execlist_link
)
578 if (++num_elements
> 2)
581 if (num_elements
> 2) {
582 struct drm_i915_gem_request
*tail_req
;
584 tail_req
= list_last_entry(&ring
->execlist_queue
,
585 struct drm_i915_gem_request
,
588 if (to
== tail_req
->ctx
) {
589 WARN(tail_req
->elsp_submitted
!= 0,
590 "More than 2 already-submitted reqs queued\n");
591 list_del(&tail_req
->execlist_link
);
592 list_add_tail(&tail_req
->execlist_link
,
593 &ring
->execlist_retired_req_list
);
597 list_add_tail(&request
->execlist_link
, &ring
->execlist_queue
);
598 if (num_elements
== 0)
599 execlists_context_unqueue(ring
);
601 spin_unlock_irq(&ring
->execlist_lock
);
606 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer
*ringbuf
,
607 struct intel_context
*ctx
)
609 struct intel_engine_cs
*ring
= ringbuf
->ring
;
610 uint32_t flush_domains
;
614 if (ring
->gpu_caches_dirty
)
615 flush_domains
= I915_GEM_GPU_DOMAINS
;
617 ret
= ring
->emit_flush(ringbuf
, ctx
,
618 I915_GEM_GPU_DOMAINS
, flush_domains
);
622 ring
->gpu_caches_dirty
= false;
626 static int execlists_move_to_gpu(struct intel_ringbuffer
*ringbuf
,
627 struct intel_context
*ctx
,
628 struct list_head
*vmas
)
630 struct intel_engine_cs
*ring
= ringbuf
->ring
;
631 const unsigned other_rings
= ~intel_ring_flag(ring
);
632 struct i915_vma
*vma
;
633 uint32_t flush_domains
= 0;
634 bool flush_chipset
= false;
637 list_for_each_entry(vma
, vmas
, exec_list
) {
638 struct drm_i915_gem_object
*obj
= vma
->obj
;
640 if (obj
->active
& other_rings
) {
641 ret
= i915_gem_object_sync(obj
, ring
);
646 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
647 flush_chipset
|= i915_gem_clflush_object(obj
, false);
649 flush_domains
|= obj
->base
.write_domain
;
652 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
655 /* Unconditionally invalidate gpu caches and ensure that we do flush
656 * any residual writes from the previous batch.
658 return logical_ring_invalidate_all_caches(ringbuf
, ctx
);
661 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
,
662 struct intel_context
*ctx
)
666 if (ctx
!= request
->ring
->default_context
) {
667 ret
= intel_lr_context_pin(request
->ring
, ctx
);
672 request
->ringbuf
= ctx
->engine
[request
->ring
->id
].ringbuf
;
674 i915_gem_context_reference(request
->ctx
);
679 static int logical_ring_wait_for_space(struct intel_ringbuffer
*ringbuf
,
680 struct intel_context
*ctx
,
683 struct intel_engine_cs
*ring
= ringbuf
->ring
;
684 struct drm_i915_gem_request
*request
;
688 if (intel_ring_space(ringbuf
) >= bytes
)
691 list_for_each_entry(request
, &ring
->request_list
, list
) {
693 * The request queue is per-engine, so can contain requests
694 * from multiple ringbuffers. Here, we must ignore any that
695 * aren't from the ringbuffer we're considering.
697 if (request
->ringbuf
!= ringbuf
)
700 /* Would completion of this request free enough space? */
701 space
= __intel_ring_space(request
->postfix
, ringbuf
->tail
,
707 if (WARN_ON(&request
->list
== &ring
->request_list
))
710 ret
= i915_wait_request(request
);
714 ringbuf
->space
= space
;
719 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
720 * @ringbuf: Logical Ringbuffer to advance.
722 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
723 * really happens during submission is that the context and current tail will be placed
724 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
725 * point, the tail *inside* the context is updated and the ELSP written to.
728 intel_logical_ring_advance_and_submit(struct intel_ringbuffer
*ringbuf
,
729 struct intel_context
*ctx
,
730 struct drm_i915_gem_request
*request
)
732 struct intel_engine_cs
*ring
= ringbuf
->ring
;
734 intel_logical_ring_advance(ringbuf
);
736 if (intel_ring_stopped(ring
))
739 execlists_context_queue(ring
, ctx
, ringbuf
->tail
, request
);
742 static int logical_ring_wrap_buffer(struct intel_ringbuffer
*ringbuf
,
743 struct intel_context
*ctx
)
745 uint32_t __iomem
*virt
;
746 int rem
= ringbuf
->size
- ringbuf
->tail
;
748 if (ringbuf
->space
< rem
) {
749 int ret
= logical_ring_wait_for_space(ringbuf
, ctx
, rem
);
755 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
758 iowrite32(MI_NOOP
, virt
++);
761 intel_ring_update_space(ringbuf
);
766 static int logical_ring_prepare(struct intel_ringbuffer
*ringbuf
,
767 struct intel_context
*ctx
, int bytes
)
771 if (unlikely(ringbuf
->tail
+ bytes
> ringbuf
->effective_size
)) {
772 ret
= logical_ring_wrap_buffer(ringbuf
, ctx
);
777 if (unlikely(ringbuf
->space
< bytes
)) {
778 ret
= logical_ring_wait_for_space(ringbuf
, ctx
, bytes
);
787 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
789 * @ringbuf: Logical ringbuffer.
790 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
792 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
793 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
794 * and also preallocates a request (every workload submission is still mediated through
795 * requests, same as it did with legacy ringbuffer submission).
797 * Return: non-zero if the ringbuffer is not ready to be written to.
799 static int intel_logical_ring_begin(struct intel_ringbuffer
*ringbuf
,
800 struct intel_context
*ctx
, int num_dwords
)
802 struct intel_engine_cs
*ring
= ringbuf
->ring
;
803 struct drm_device
*dev
= ring
->dev
;
804 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
807 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
808 dev_priv
->mm
.interruptible
);
812 ret
= logical_ring_prepare(ringbuf
, ctx
, num_dwords
* sizeof(uint32_t));
816 /* Preallocate the olr before touching the ring */
817 ret
= i915_gem_request_alloc(ring
, ctx
);
821 ringbuf
->space
-= num_dwords
* sizeof(uint32_t);
826 * execlists_submission() - submit a batchbuffer for execution, Execlists style
829 * @ring: Engine Command Streamer to submit to.
830 * @ctx: Context to employ for this submission.
831 * @args: execbuffer call arguments.
832 * @vmas: list of vmas.
833 * @batch_obj: the batchbuffer to submit.
834 * @exec_start: batchbuffer start virtual address pointer.
835 * @dispatch_flags: translated execbuffer call flags.
837 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
838 * away the submission details of the execbuffer ioctl call.
840 * Return: non-zero if the submission fails.
842 int intel_execlists_submission(struct drm_device
*dev
, struct drm_file
*file
,
843 struct intel_engine_cs
*ring
,
844 struct intel_context
*ctx
,
845 struct drm_i915_gem_execbuffer2
*args
,
846 struct list_head
*vmas
,
847 struct drm_i915_gem_object
*batch_obj
,
848 u64 exec_start
, u32 dispatch_flags
)
850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
851 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
856 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
857 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
858 switch (instp_mode
) {
859 case I915_EXEC_CONSTANTS_REL_GENERAL
:
860 case I915_EXEC_CONSTANTS_ABSOLUTE
:
861 case I915_EXEC_CONSTANTS_REL_SURFACE
:
862 if (instp_mode
!= 0 && ring
!= &dev_priv
->ring
[RCS
]) {
863 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
867 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
868 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
869 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
873 /* The HW changed the meaning on this bit on gen6 */
874 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
878 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
882 if (args
->num_cliprects
!= 0) {
883 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
886 if (args
->DR4
== 0xffffffff) {
887 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
891 if (args
->DR1
|| args
->DR4
|| args
->cliprects_ptr
) {
892 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
897 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
898 DRM_DEBUG("sol reset is gen7 only\n");
902 ret
= execlists_move_to_gpu(ringbuf
, ctx
, vmas
);
906 if (ring
== &dev_priv
->ring
[RCS
] &&
907 instp_mode
!= dev_priv
->relative_constants_mode
) {
908 ret
= intel_logical_ring_begin(ringbuf
, ctx
, 4);
912 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
913 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
914 intel_logical_ring_emit(ringbuf
, INSTPM
);
915 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
916 intel_logical_ring_advance(ringbuf
);
918 dev_priv
->relative_constants_mode
= instp_mode
;
921 ret
= ring
->emit_bb_start(ringbuf
, ctx
, exec_start
, dispatch_flags
);
925 trace_i915_gem_ring_dispatch(intel_ring_get_request(ring
), dispatch_flags
);
927 i915_gem_execbuffer_move_to_active(vmas
, ring
);
928 i915_gem_execbuffer_retire_commands(dev
, file
, ring
, batch_obj
);
933 void intel_execlists_retire_requests(struct intel_engine_cs
*ring
)
935 struct drm_i915_gem_request
*req
, *tmp
;
936 struct list_head retired_list
;
938 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
939 if (list_empty(&ring
->execlist_retired_req_list
))
942 INIT_LIST_HEAD(&retired_list
);
943 spin_lock_irq(&ring
->execlist_lock
);
944 list_replace_init(&ring
->execlist_retired_req_list
, &retired_list
);
945 spin_unlock_irq(&ring
->execlist_lock
);
947 list_for_each_entry_safe(req
, tmp
, &retired_list
, execlist_link
) {
948 struct intel_context
*ctx
= req
->ctx
;
949 struct drm_i915_gem_object
*ctx_obj
=
950 ctx
->engine
[ring
->id
].state
;
952 if (ctx_obj
&& (ctx
!= ring
->default_context
))
953 intel_lr_context_unpin(ring
, ctx
);
954 list_del(&req
->execlist_link
);
955 i915_gem_request_unreference(req
);
959 void intel_logical_ring_stop(struct intel_engine_cs
*ring
)
961 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
964 if (!intel_ring_initialized(ring
))
967 ret
= intel_ring_idle(ring
);
968 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
969 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
972 /* TODO: Is this correct with Execlists enabled? */
973 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
974 if (wait_for_atomic((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
975 DRM_ERROR("%s :timed out trying to stop ring\n", ring
->name
);
978 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
981 int logical_ring_flush_all_caches(struct intel_ringbuffer
*ringbuf
,
982 struct intel_context
*ctx
)
984 struct intel_engine_cs
*ring
= ringbuf
->ring
;
987 if (!ring
->gpu_caches_dirty
)
990 ret
= ring
->emit_flush(ringbuf
, ctx
, 0, I915_GEM_GPU_DOMAINS
);
994 ring
->gpu_caches_dirty
= false;
998 static int intel_lr_context_pin(struct intel_engine_cs
*ring
,
999 struct intel_context
*ctx
)
1001 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[ring
->id
].state
;
1002 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
1005 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1006 if (ctx
->engine
[ring
->id
].pin_count
++ == 0) {
1007 ret
= i915_gem_obj_ggtt_pin(ctx_obj
,
1008 GEN8_LR_CONTEXT_ALIGN
, 0);
1010 goto reset_pin_count
;
1012 ret
= intel_pin_and_map_ringbuffer_obj(ring
->dev
, ringbuf
);
1016 ctx_obj
->dirty
= true;
1022 i915_gem_object_ggtt_unpin(ctx_obj
);
1024 ctx
->engine
[ring
->id
].pin_count
= 0;
1029 void intel_lr_context_unpin(struct intel_engine_cs
*ring
,
1030 struct intel_context
*ctx
)
1032 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[ring
->id
].state
;
1033 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
1036 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1037 if (--ctx
->engine
[ring
->id
].pin_count
== 0) {
1038 intel_unpin_ringbuffer_obj(ringbuf
);
1039 i915_gem_object_ggtt_unpin(ctx_obj
);
1044 static int intel_logical_ring_workarounds_emit(struct intel_engine_cs
*ring
,
1045 struct intel_context
*ctx
)
1048 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
1049 struct drm_device
*dev
= ring
->dev
;
1050 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1051 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
1053 if (WARN_ON_ONCE(w
->count
== 0))
1056 ring
->gpu_caches_dirty
= true;
1057 ret
= logical_ring_flush_all_caches(ringbuf
, ctx
);
1061 ret
= intel_logical_ring_begin(ringbuf
, ctx
, w
->count
* 2 + 2);
1065 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(w
->count
));
1066 for (i
= 0; i
< w
->count
; i
++) {
1067 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].addr
);
1068 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].value
);
1070 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1072 intel_logical_ring_advance(ringbuf
);
1074 ring
->gpu_caches_dirty
= true;
1075 ret
= logical_ring_flush_all_caches(ringbuf
, ctx
);
1082 static int gen8_init_common_ring(struct intel_engine_cs
*ring
)
1084 struct drm_device
*dev
= ring
->dev
;
1085 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1087 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1088 I915_WRITE(RING_HWSTAM(ring
->mmio_base
), 0xffffffff);
1090 if (ring
->status_page
.obj
) {
1091 I915_WRITE(RING_HWS_PGA(ring
->mmio_base
),
1092 (u32
)ring
->status_page
.gfx_addr
);
1093 POSTING_READ(RING_HWS_PGA(ring
->mmio_base
));
1096 I915_WRITE(RING_MODE_GEN7(ring
),
1097 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1098 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1099 POSTING_READ(RING_MODE_GEN7(ring
));
1100 ring
->next_context_status_buffer
= 0;
1101 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring
->name
);
1103 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
1108 static int gen8_init_render_ring(struct intel_engine_cs
*ring
)
1110 struct drm_device
*dev
= ring
->dev
;
1111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1114 ret
= gen8_init_common_ring(ring
);
1118 /* We need to disable the AsyncFlip performance optimisations in order
1119 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1120 * programmed to '1' on all products.
1122 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1124 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1126 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1128 return init_workarounds_ring(ring
);
1131 static int gen9_init_render_ring(struct intel_engine_cs
*ring
)
1135 ret
= gen8_init_common_ring(ring
);
1139 return init_workarounds_ring(ring
);
1142 static int gen8_emit_bb_start(struct intel_ringbuffer
*ringbuf
,
1143 struct intel_context
*ctx
,
1144 u64 offset
, unsigned dispatch_flags
)
1146 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1149 ret
= intel_logical_ring_begin(ringbuf
, ctx
, 4);
1153 /* FIXME(BDW): Address space and security selectors. */
1154 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8));
1155 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1156 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1157 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1158 intel_logical_ring_advance(ringbuf
);
1163 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*ring
)
1165 struct drm_device
*dev
= ring
->dev
;
1166 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1167 unsigned long flags
;
1169 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1172 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1173 if (ring
->irq_refcount
++ == 0) {
1174 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1175 POSTING_READ(RING_IMR(ring
->mmio_base
));
1177 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1182 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*ring
)
1184 struct drm_device
*dev
= ring
->dev
;
1185 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1186 unsigned long flags
;
1188 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1189 if (--ring
->irq_refcount
== 0) {
1190 I915_WRITE_IMR(ring
, ~ring
->irq_keep_mask
);
1191 POSTING_READ(RING_IMR(ring
->mmio_base
));
1193 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1196 static int gen8_emit_flush(struct intel_ringbuffer
*ringbuf
,
1197 struct intel_context
*ctx
,
1198 u32 invalidate_domains
,
1201 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1202 struct drm_device
*dev
= ring
->dev
;
1203 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1207 ret
= intel_logical_ring_begin(ringbuf
, ctx
, 4);
1211 cmd
= MI_FLUSH_DW
+ 1;
1213 /* We always require a command barrier so that subsequent
1214 * commands, such as breadcrumb interrupts, are strictly ordered
1215 * wrt the contents of the write cache being flushed to memory
1216 * (and thus being coherent from the CPU).
1218 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1220 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
) {
1221 cmd
|= MI_INVALIDATE_TLB
;
1222 if (ring
== &dev_priv
->ring
[VCS
])
1223 cmd
|= MI_INVALIDATE_BSD
;
1226 intel_logical_ring_emit(ringbuf
, cmd
);
1227 intel_logical_ring_emit(ringbuf
,
1228 I915_GEM_HWS_SCRATCH_ADDR
|
1229 MI_FLUSH_DW_USE_GTT
);
1230 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1231 intel_logical_ring_emit(ringbuf
, 0); /* value */
1232 intel_logical_ring_advance(ringbuf
);
1237 static int gen8_emit_flush_render(struct intel_ringbuffer
*ringbuf
,
1238 struct intel_context
*ctx
,
1239 u32 invalidate_domains
,
1242 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1243 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1248 flags
|= PIPE_CONTROL_CS_STALL
;
1250 if (flush_domains
) {
1251 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1252 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1255 if (invalidate_domains
) {
1256 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1257 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1258 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1259 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1260 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1261 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1262 flags
|= PIPE_CONTROL_QW_WRITE
;
1263 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1267 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
1270 vf_flush_wa
= INTEL_INFO(ring
->dev
)->gen
>= 9 &&
1271 flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1273 ret
= intel_logical_ring_begin(ringbuf
, ctx
, vf_flush_wa
? 12 : 6);
1278 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1279 intel_logical_ring_emit(ringbuf
, 0);
1280 intel_logical_ring_emit(ringbuf
, 0);
1281 intel_logical_ring_emit(ringbuf
, 0);
1282 intel_logical_ring_emit(ringbuf
, 0);
1283 intel_logical_ring_emit(ringbuf
, 0);
1286 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1287 intel_logical_ring_emit(ringbuf
, flags
);
1288 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1289 intel_logical_ring_emit(ringbuf
, 0);
1290 intel_logical_ring_emit(ringbuf
, 0);
1291 intel_logical_ring_emit(ringbuf
, 0);
1292 intel_logical_ring_advance(ringbuf
);
1297 static u32
gen8_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1299 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1302 static void gen8_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1304 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1307 static int gen8_emit_request(struct intel_ringbuffer
*ringbuf
,
1308 struct drm_i915_gem_request
*request
)
1310 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1315 * Reserve space for 2 NOOPs at the end of each request to be
1316 * used as a workaround for not being allowed to do lite
1317 * restore with HEAD==TAIL (WaIdleLiteRestore).
1319 ret
= intel_logical_ring_begin(ringbuf
, request
->ctx
, 8);
1323 cmd
= MI_STORE_DWORD_IMM_GEN4
;
1324 cmd
|= MI_GLOBAL_GTT
;
1326 intel_logical_ring_emit(ringbuf
, cmd
);
1327 intel_logical_ring_emit(ringbuf
,
1328 (ring
->status_page
.gfx_addr
+
1329 (I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
)));
1330 intel_logical_ring_emit(ringbuf
, 0);
1331 intel_logical_ring_emit(ringbuf
,
1332 i915_gem_request_get_seqno(ring
->outstanding_lazy_request
));
1333 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1334 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1335 intel_logical_ring_advance_and_submit(ringbuf
, request
->ctx
, request
);
1338 * Here we add two extra NOOPs as padding to avoid
1339 * lite restore of a context with HEAD==TAIL.
1341 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1342 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1343 intel_logical_ring_advance(ringbuf
);
1348 static int intel_lr_context_render_state_init(struct intel_engine_cs
*ring
,
1349 struct intel_context
*ctx
)
1351 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
1352 struct render_state so
;
1353 struct drm_i915_file_private
*file_priv
= ctx
->file_priv
;
1354 struct drm_file
*file
= file_priv
? file_priv
->file
: NULL
;
1357 ret
= i915_gem_render_state_prepare(ring
, &so
);
1361 if (so
.rodata
== NULL
)
1364 ret
= ring
->emit_bb_start(ringbuf
,
1367 I915_DISPATCH_SECURE
);
1371 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), ring
);
1373 ret
= __i915_add_request(ring
, file
, so
.obj
);
1374 /* intel_logical_ring_add_request moves object to inactive if it
1377 i915_gem_render_state_fini(&so
);
1381 static int gen8_init_rcs_context(struct intel_engine_cs
*ring
,
1382 struct intel_context
*ctx
)
1386 ret
= intel_logical_ring_workarounds_emit(ring
, ctx
);
1390 return intel_lr_context_render_state_init(ring
, ctx
);
1394 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1396 * @ring: Engine Command Streamer.
1399 void intel_logical_ring_cleanup(struct intel_engine_cs
*ring
)
1401 struct drm_i915_private
*dev_priv
;
1403 if (!intel_ring_initialized(ring
))
1406 dev_priv
= ring
->dev
->dev_private
;
1408 intel_logical_ring_stop(ring
);
1409 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1410 i915_gem_request_assign(&ring
->outstanding_lazy_request
, NULL
);
1413 ring
->cleanup(ring
);
1415 i915_cmd_parser_fini_ring(ring
);
1416 i915_gem_batch_pool_fini(&ring
->batch_pool
);
1418 if (ring
->status_page
.obj
) {
1419 kunmap(sg_page(ring
->status_page
.obj
->pages
->sgl
));
1420 ring
->status_page
.obj
= NULL
;
1424 static int logical_ring_init(struct drm_device
*dev
, struct intel_engine_cs
*ring
)
1428 /* Intentionally left blank. */
1429 ring
->buffer
= NULL
;
1432 INIT_LIST_HEAD(&ring
->active_list
);
1433 INIT_LIST_HEAD(&ring
->request_list
);
1434 i915_gem_batch_pool_init(dev
, &ring
->batch_pool
);
1435 init_waitqueue_head(&ring
->irq_queue
);
1437 INIT_LIST_HEAD(&ring
->execlist_queue
);
1438 INIT_LIST_HEAD(&ring
->execlist_retired_req_list
);
1439 spin_lock_init(&ring
->execlist_lock
);
1441 ret
= i915_cmd_parser_init_ring(ring
);
1445 ret
= intel_lr_context_deferred_create(ring
->default_context
, ring
);
1450 static int logical_render_ring_init(struct drm_device
*dev
)
1452 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1453 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
1456 ring
->name
= "render ring";
1458 ring
->mmio_base
= RENDER_RING_BASE
;
1459 ring
->irq_enable_mask
=
1460 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1461 ring
->irq_keep_mask
=
1462 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1463 if (HAS_L3_DPF(dev
))
1464 ring
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
1466 if (INTEL_INFO(dev
)->gen
>= 9)
1467 ring
->init_hw
= gen9_init_render_ring
;
1469 ring
->init_hw
= gen8_init_render_ring
;
1470 ring
->init_context
= gen8_init_rcs_context
;
1471 ring
->cleanup
= intel_fini_pipe_control
;
1472 ring
->get_seqno
= gen8_get_seqno
;
1473 ring
->set_seqno
= gen8_set_seqno
;
1474 ring
->emit_request
= gen8_emit_request
;
1475 ring
->emit_flush
= gen8_emit_flush_render
;
1476 ring
->irq_get
= gen8_logical_ring_get_irq
;
1477 ring
->irq_put
= gen8_logical_ring_put_irq
;
1478 ring
->emit_bb_start
= gen8_emit_bb_start
;
1481 ret
= logical_ring_init(dev
, ring
);
1485 return intel_init_pipe_control(ring
);
1488 static int logical_bsd_ring_init(struct drm_device
*dev
)
1490 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1491 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
1493 ring
->name
= "bsd ring";
1495 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
1496 ring
->irq_enable_mask
=
1497 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1498 ring
->irq_keep_mask
=
1499 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1501 ring
->init_hw
= gen8_init_common_ring
;
1502 ring
->get_seqno
= gen8_get_seqno
;
1503 ring
->set_seqno
= gen8_set_seqno
;
1504 ring
->emit_request
= gen8_emit_request
;
1505 ring
->emit_flush
= gen8_emit_flush
;
1506 ring
->irq_get
= gen8_logical_ring_get_irq
;
1507 ring
->irq_put
= gen8_logical_ring_put_irq
;
1508 ring
->emit_bb_start
= gen8_emit_bb_start
;
1510 return logical_ring_init(dev
, ring
);
1513 static int logical_bsd2_ring_init(struct drm_device
*dev
)
1515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1516 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
1518 ring
->name
= "bds2 ring";
1520 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
1521 ring
->irq_enable_mask
=
1522 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
1523 ring
->irq_keep_mask
=
1524 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
1526 ring
->init_hw
= gen8_init_common_ring
;
1527 ring
->get_seqno
= gen8_get_seqno
;
1528 ring
->set_seqno
= gen8_set_seqno
;
1529 ring
->emit_request
= gen8_emit_request
;
1530 ring
->emit_flush
= gen8_emit_flush
;
1531 ring
->irq_get
= gen8_logical_ring_get_irq
;
1532 ring
->irq_put
= gen8_logical_ring_put_irq
;
1533 ring
->emit_bb_start
= gen8_emit_bb_start
;
1535 return logical_ring_init(dev
, ring
);
1538 static int logical_blt_ring_init(struct drm_device
*dev
)
1540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1541 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
1543 ring
->name
= "blitter ring";
1545 ring
->mmio_base
= BLT_RING_BASE
;
1546 ring
->irq_enable_mask
=
1547 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
1548 ring
->irq_keep_mask
=
1549 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
1551 ring
->init_hw
= gen8_init_common_ring
;
1552 ring
->get_seqno
= gen8_get_seqno
;
1553 ring
->set_seqno
= gen8_set_seqno
;
1554 ring
->emit_request
= gen8_emit_request
;
1555 ring
->emit_flush
= gen8_emit_flush
;
1556 ring
->irq_get
= gen8_logical_ring_get_irq
;
1557 ring
->irq_put
= gen8_logical_ring_put_irq
;
1558 ring
->emit_bb_start
= gen8_emit_bb_start
;
1560 return logical_ring_init(dev
, ring
);
1563 static int logical_vebox_ring_init(struct drm_device
*dev
)
1565 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1566 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
1568 ring
->name
= "video enhancement ring";
1570 ring
->mmio_base
= VEBOX_RING_BASE
;
1571 ring
->irq_enable_mask
=
1572 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
1573 ring
->irq_keep_mask
=
1574 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
1576 ring
->init_hw
= gen8_init_common_ring
;
1577 ring
->get_seqno
= gen8_get_seqno
;
1578 ring
->set_seqno
= gen8_set_seqno
;
1579 ring
->emit_request
= gen8_emit_request
;
1580 ring
->emit_flush
= gen8_emit_flush
;
1581 ring
->irq_get
= gen8_logical_ring_get_irq
;
1582 ring
->irq_put
= gen8_logical_ring_put_irq
;
1583 ring
->emit_bb_start
= gen8_emit_bb_start
;
1585 return logical_ring_init(dev
, ring
);
1589 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1592 * This function inits the engines for an Execlists submission style (the equivalent in the
1593 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1594 * those engines that are present in the hardware.
1596 * Return: non-zero if the initialization failed.
1598 int intel_logical_rings_init(struct drm_device
*dev
)
1600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1603 ret
= logical_render_ring_init(dev
);
1608 ret
= logical_bsd_ring_init(dev
);
1610 goto cleanup_render_ring
;
1614 ret
= logical_blt_ring_init(dev
);
1616 goto cleanup_bsd_ring
;
1619 if (HAS_VEBOX(dev
)) {
1620 ret
= logical_vebox_ring_init(dev
);
1622 goto cleanup_blt_ring
;
1625 if (HAS_BSD2(dev
)) {
1626 ret
= logical_bsd2_ring_init(dev
);
1628 goto cleanup_vebox_ring
;
1631 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
1633 goto cleanup_bsd2_ring
;
1638 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS2
]);
1640 intel_logical_ring_cleanup(&dev_priv
->ring
[VECS
]);
1642 intel_logical_ring_cleanup(&dev_priv
->ring
[BCS
]);
1644 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS
]);
1645 cleanup_render_ring
:
1646 intel_logical_ring_cleanup(&dev_priv
->ring
[RCS
]);
1652 make_rpcs(struct drm_device
*dev
)
1657 * No explicit RPCS request is needed to ensure full
1658 * slice/subslice/EU enablement prior to Gen9.
1660 if (INTEL_INFO(dev
)->gen
< 9)
1664 * Starting in Gen9, render power gating can leave
1665 * slice/subslice/EU in a partially enabled state. We
1666 * must make an explicit request through RPCS for full
1669 if (INTEL_INFO(dev
)->has_slice_pg
) {
1670 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
1671 rpcs
|= INTEL_INFO(dev
)->slice_total
<<
1672 GEN8_RPCS_S_CNT_SHIFT
;
1673 rpcs
|= GEN8_RPCS_ENABLE
;
1676 if (INTEL_INFO(dev
)->has_subslice_pg
) {
1677 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
1678 rpcs
|= INTEL_INFO(dev
)->subslice_per_slice
<<
1679 GEN8_RPCS_SS_CNT_SHIFT
;
1680 rpcs
|= GEN8_RPCS_ENABLE
;
1683 if (INTEL_INFO(dev
)->has_eu_pg
) {
1684 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
1685 GEN8_RPCS_EU_MIN_SHIFT
;
1686 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
1687 GEN8_RPCS_EU_MAX_SHIFT
;
1688 rpcs
|= GEN8_RPCS_ENABLE
;
1695 populate_lr_context(struct intel_context
*ctx
, struct drm_i915_gem_object
*ctx_obj
,
1696 struct intel_engine_cs
*ring
, struct intel_ringbuffer
*ringbuf
)
1698 struct drm_device
*dev
= ring
->dev
;
1699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1700 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
1702 uint32_t *reg_state
;
1706 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1708 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
1710 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1714 ret
= i915_gem_object_get_pages(ctx_obj
);
1716 DRM_DEBUG_DRIVER("Could not get object pages\n");
1720 i915_gem_object_pin_pages(ctx_obj
);
1722 /* The second page of the context object contains some fields which must
1723 * be set up prior to the first execution. */
1724 page
= i915_gem_object_get_page(ctx_obj
, 1);
1725 reg_state
= kmap_atomic(page
);
1727 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1728 * commands followed by (reg, value) pairs. The values we are setting here are
1729 * only for the first context restore: on a subsequent save, the GPU will
1730 * recreate this batchbuffer with new values (including all the missing
1731 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1732 if (ring
->id
== RCS
)
1733 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(14);
1735 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(11);
1736 reg_state
[CTX_LRI_HEADER_0
] |= MI_LRI_FORCE_POSTED
;
1737 reg_state
[CTX_CONTEXT_CONTROL
] = RING_CONTEXT_CONTROL(ring
);
1738 reg_state
[CTX_CONTEXT_CONTROL
+1] =
1739 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
1740 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
);
1741 reg_state
[CTX_RING_HEAD
] = RING_HEAD(ring
->mmio_base
);
1742 reg_state
[CTX_RING_HEAD
+1] = 0;
1743 reg_state
[CTX_RING_TAIL
] = RING_TAIL(ring
->mmio_base
);
1744 reg_state
[CTX_RING_TAIL
+1] = 0;
1745 reg_state
[CTX_RING_BUFFER_START
] = RING_START(ring
->mmio_base
);
1746 /* Ring buffer start address is not known until the buffer is pinned.
1747 * It is written to the context image in execlists_update_context()
1749 reg_state
[CTX_RING_BUFFER_CONTROL
] = RING_CTL(ring
->mmio_base
);
1750 reg_state
[CTX_RING_BUFFER_CONTROL
+1] =
1751 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
;
1752 reg_state
[CTX_BB_HEAD_U
] = ring
->mmio_base
+ 0x168;
1753 reg_state
[CTX_BB_HEAD_U
+1] = 0;
1754 reg_state
[CTX_BB_HEAD_L
] = ring
->mmio_base
+ 0x140;
1755 reg_state
[CTX_BB_HEAD_L
+1] = 0;
1756 reg_state
[CTX_BB_STATE
] = ring
->mmio_base
+ 0x110;
1757 reg_state
[CTX_BB_STATE
+1] = (1<<5);
1758 reg_state
[CTX_SECOND_BB_HEAD_U
] = ring
->mmio_base
+ 0x11c;
1759 reg_state
[CTX_SECOND_BB_HEAD_U
+1] = 0;
1760 reg_state
[CTX_SECOND_BB_HEAD_L
] = ring
->mmio_base
+ 0x114;
1761 reg_state
[CTX_SECOND_BB_HEAD_L
+1] = 0;
1762 reg_state
[CTX_SECOND_BB_STATE
] = ring
->mmio_base
+ 0x118;
1763 reg_state
[CTX_SECOND_BB_STATE
+1] = 0;
1764 if (ring
->id
== RCS
) {
1765 /* TODO: according to BSpec, the register state context
1766 * for CHV does not have these. OTOH, these registers do
1767 * exist in CHV. I'm waiting for a clarification */
1768 reg_state
[CTX_BB_PER_CTX_PTR
] = ring
->mmio_base
+ 0x1c0;
1769 reg_state
[CTX_BB_PER_CTX_PTR
+1] = 0;
1770 reg_state
[CTX_RCS_INDIRECT_CTX
] = ring
->mmio_base
+ 0x1c4;
1771 reg_state
[CTX_RCS_INDIRECT_CTX
+1] = 0;
1772 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
] = ring
->mmio_base
+ 0x1c8;
1773 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] = 0;
1775 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9);
1776 reg_state
[CTX_LRI_HEADER_1
] |= MI_LRI_FORCE_POSTED
;
1777 reg_state
[CTX_CTX_TIMESTAMP
] = ring
->mmio_base
+ 0x3a8;
1778 reg_state
[CTX_CTX_TIMESTAMP
+1] = 0;
1779 reg_state
[CTX_PDP3_UDW
] = GEN8_RING_PDP_UDW(ring
, 3);
1780 reg_state
[CTX_PDP3_LDW
] = GEN8_RING_PDP_LDW(ring
, 3);
1781 reg_state
[CTX_PDP2_UDW
] = GEN8_RING_PDP_UDW(ring
, 2);
1782 reg_state
[CTX_PDP2_LDW
] = GEN8_RING_PDP_LDW(ring
, 2);
1783 reg_state
[CTX_PDP1_UDW
] = GEN8_RING_PDP_UDW(ring
, 1);
1784 reg_state
[CTX_PDP1_LDW
] = GEN8_RING_PDP_LDW(ring
, 1);
1785 reg_state
[CTX_PDP0_UDW
] = GEN8_RING_PDP_UDW(ring
, 0);
1786 reg_state
[CTX_PDP0_LDW
] = GEN8_RING_PDP_LDW(ring
, 0);
1788 /* With dynamic page allocation, PDPs may not be allocated at this point,
1789 * Point the unallocated PDPs to the scratch page
1791 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
1792 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
1793 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
1794 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
1795 if (ring
->id
== RCS
) {
1796 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
1797 reg_state
[CTX_R_PWR_CLK_STATE
] = GEN8_R_PWR_CLK_STATE
;
1798 reg_state
[CTX_R_PWR_CLK_STATE
+1] = make_rpcs(dev
);
1801 kunmap_atomic(reg_state
);
1804 set_page_dirty(page
);
1805 i915_gem_object_unpin_pages(ctx_obj
);
1811 * intel_lr_context_free() - free the LRC specific bits of a context
1812 * @ctx: the LR context to free.
1814 * The real context freeing is done in i915_gem_context_free: this only
1815 * takes care of the bits that are LRC related: the per-engine backing
1816 * objects and the logical ringbuffer.
1818 void intel_lr_context_free(struct intel_context
*ctx
)
1822 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1823 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
1826 struct intel_ringbuffer
*ringbuf
=
1827 ctx
->engine
[i
].ringbuf
;
1828 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1830 if (ctx
== ring
->default_context
) {
1831 intel_unpin_ringbuffer_obj(ringbuf
);
1832 i915_gem_object_ggtt_unpin(ctx_obj
);
1834 WARN_ON(ctx
->engine
[ring
->id
].pin_count
);
1835 intel_destroy_ringbuffer_obj(ringbuf
);
1837 drm_gem_object_unreference(&ctx_obj
->base
);
1842 static uint32_t get_lr_context_size(struct intel_engine_cs
*ring
)
1846 WARN_ON(INTEL_INFO(ring
->dev
)->gen
< 8);
1850 if (INTEL_INFO(ring
->dev
)->gen
>= 9)
1851 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
1853 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
1859 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
1866 static void lrc_setup_hardware_status_page(struct intel_engine_cs
*ring
,
1867 struct drm_i915_gem_object
*default_ctx_obj
)
1869 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1871 /* The status page is offset 0 from the default context object
1873 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(default_ctx_obj
);
1874 ring
->status_page
.page_addr
=
1875 kmap(sg_page(default_ctx_obj
->pages
->sgl
));
1876 ring
->status_page
.obj
= default_ctx_obj
;
1878 I915_WRITE(RING_HWS_PGA(ring
->mmio_base
),
1879 (u32
)ring
->status_page
.gfx_addr
);
1880 POSTING_READ(RING_HWS_PGA(ring
->mmio_base
));
1884 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
1885 * @ctx: LR context to create.
1886 * @ring: engine to be used with the context.
1888 * This function can be called more than once, with different engines, if we plan
1889 * to use the context with them. The context backing objects and the ringbuffers
1890 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
1891 * the creation is a deferred call: it's better to make sure first that we need to use
1892 * a given ring with the context.
1894 * Return: non-zero on error.
1896 int intel_lr_context_deferred_create(struct intel_context
*ctx
,
1897 struct intel_engine_cs
*ring
)
1899 const bool is_global_default_ctx
= (ctx
== ring
->default_context
);
1900 struct drm_device
*dev
= ring
->dev
;
1901 struct drm_i915_gem_object
*ctx_obj
;
1902 uint32_t context_size
;
1903 struct intel_ringbuffer
*ringbuf
;
1906 WARN_ON(ctx
->legacy_hw_ctx
.rcs_state
!= NULL
);
1907 WARN_ON(ctx
->engine
[ring
->id
].state
);
1909 context_size
= round_up(get_lr_context_size(ring
), 4096);
1911 ctx_obj
= i915_gem_alloc_object(dev
, context_size
);
1913 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
1917 if (is_global_default_ctx
) {
1918 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
, 0);
1920 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
1922 drm_gem_object_unreference(&ctx_obj
->base
);
1927 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
1929 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1932 goto error_unpin_ctx
;
1935 ringbuf
->ring
= ring
;
1937 ringbuf
->size
= 32 * PAGE_SIZE
;
1938 ringbuf
->effective_size
= ringbuf
->size
;
1941 ringbuf
->last_retired_head
= -1;
1942 intel_ring_update_space(ringbuf
);
1944 if (ringbuf
->obj
== NULL
) {
1945 ret
= intel_alloc_ringbuffer_obj(dev
, ringbuf
);
1948 "Failed to allocate ringbuffer obj %s: %d\n",
1950 goto error_free_rbuf
;
1953 if (is_global_default_ctx
) {
1954 ret
= intel_pin_and_map_ringbuffer_obj(dev
, ringbuf
);
1957 "Failed to pin and map ringbuffer %s: %d\n",
1959 goto error_destroy_rbuf
;
1965 ret
= populate_lr_context(ctx
, ctx_obj
, ring
, ringbuf
);
1967 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
1971 ctx
->engine
[ring
->id
].ringbuf
= ringbuf
;
1972 ctx
->engine
[ring
->id
].state
= ctx_obj
;
1974 if (ctx
== ring
->default_context
)
1975 lrc_setup_hardware_status_page(ring
, ctx_obj
);
1976 else if (ring
->id
== RCS
&& !ctx
->rcs_initialized
) {
1977 if (ring
->init_context
) {
1978 ret
= ring
->init_context(ring
, ctx
);
1980 DRM_ERROR("ring init context: %d\n", ret
);
1981 ctx
->engine
[ring
->id
].ringbuf
= NULL
;
1982 ctx
->engine
[ring
->id
].state
= NULL
;
1987 ctx
->rcs_initialized
= true;
1993 if (is_global_default_ctx
)
1994 intel_unpin_ringbuffer_obj(ringbuf
);
1996 intel_destroy_ringbuffer_obj(ringbuf
);
2000 if (is_global_default_ctx
)
2001 i915_gem_object_ggtt_unpin(ctx_obj
);
2002 drm_gem_object_unreference(&ctx_obj
->base
);
2006 void intel_lr_context_reset(struct drm_device
*dev
,
2007 struct intel_context
*ctx
)
2009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2010 struct intel_engine_cs
*ring
;
2013 for_each_ring(ring
, dev_priv
, i
) {
2014 struct drm_i915_gem_object
*ctx_obj
=
2015 ctx
->engine
[ring
->id
].state
;
2016 struct intel_ringbuffer
*ringbuf
=
2017 ctx
->engine
[ring
->id
].ringbuf
;
2018 uint32_t *reg_state
;
2024 if (i915_gem_object_get_pages(ctx_obj
)) {
2025 WARN(1, "Failed get_pages for context obj\n");
2028 page
= i915_gem_object_get_page(ctx_obj
, 1);
2029 reg_state
= kmap_atomic(page
);
2031 reg_state
[CTX_RING_HEAD
+1] = 0;
2032 reg_state
[CTX_RING_TAIL
+1] = 0;
2034 kunmap_atomic(reg_state
);