2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
139 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
140 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_ALIGN 4096
144 #define RING_EXECLIST_QFULL (1 << 0x2)
145 #define RING_EXECLIST1_VALID (1 << 0x3)
146 #define RING_EXECLIST0_VALID (1 << 0x4)
147 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
148 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
149 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
151 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
152 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
153 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
154 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
155 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
156 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
158 #define CTX_LRI_HEADER_0 0x01
159 #define CTX_CONTEXT_CONTROL 0x02
160 #define CTX_RING_HEAD 0x04
161 #define CTX_RING_TAIL 0x06
162 #define CTX_RING_BUFFER_START 0x08
163 #define CTX_RING_BUFFER_CONTROL 0x0a
164 #define CTX_BB_HEAD_U 0x0c
165 #define CTX_BB_HEAD_L 0x0e
166 #define CTX_BB_STATE 0x10
167 #define CTX_SECOND_BB_HEAD_U 0x12
168 #define CTX_SECOND_BB_HEAD_L 0x14
169 #define CTX_SECOND_BB_STATE 0x16
170 #define CTX_BB_PER_CTX_PTR 0x18
171 #define CTX_RCS_INDIRECT_CTX 0x1a
172 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
173 #define CTX_LRI_HEADER_1 0x21
174 #define CTX_CTX_TIMESTAMP 0x22
175 #define CTX_PDP3_UDW 0x24
176 #define CTX_PDP3_LDW 0x26
177 #define CTX_PDP2_UDW 0x28
178 #define CTX_PDP2_LDW 0x2a
179 #define CTX_PDP1_UDW 0x2c
180 #define CTX_PDP1_LDW 0x2e
181 #define CTX_PDP0_UDW 0x30
182 #define CTX_PDP0_LDW 0x32
183 #define CTX_LRI_HEADER_2 0x41
184 #define CTX_R_PWR_CLK_STATE 0x42
185 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
187 #define GEN8_CTX_VALID (1<<0)
188 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
189 #define GEN8_CTX_FORCE_RESTORE (1<<2)
190 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
191 #define GEN8_CTX_PRIVILEGE (1<<8)
193 ADVANCED_CONTEXT
= 0,
198 #define GEN8_CTX_MODE_SHIFT 3
201 FAULT_AND_HALT
, /* Debug only */
203 FAULT_AND_CONTINUE
/* Unsupported */
205 #define GEN8_CTX_ID_SHIFT 32
208 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
210 * @enable_execlists: value of i915.enable_execlists module parameter.
212 * Only certain platforms support Execlists (the prerequisites being
213 * support for Logical Ring Contexts and Aliasing PPGTT or better),
214 * and only when enabled via module parameter.
216 * Return: 1 if Execlists is supported and has to be enabled.
218 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
)
220 WARN_ON(i915
.enable_ppgtt
== -1);
222 if (enable_execlists
== 0)
225 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && USES_PPGTT(dev
) &&
226 i915
.use_mmio_flip
>= 0)
233 * intel_execlists_ctx_id() - get the Execlists Context ID
234 * @ctx_obj: Logical Ring Context backing object.
236 * Do not confuse with ctx->id! Unfortunately we have a name overload
237 * here: the old context ID we pass to userspace as a handler so that
238 * they can refer to a context, and the new context ID we pass to the
239 * ELSP so that the GPU can inform us of the context status via
242 * Return: 20-bits globally unique context ID.
244 u32
intel_execlists_ctx_id(struct drm_i915_gem_object
*ctx_obj
)
246 u32 lrca
= i915_gem_obj_ggtt_offset(ctx_obj
);
248 /* LRCA is required to be 4K aligned so the more significant 20 bits
249 * are globally unique */
253 static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object
*ctx_obj
)
256 uint64_t lrca
= i915_gem_obj_ggtt_offset(ctx_obj
);
258 WARN_ON(lrca
& 0xFFFFFFFF00000FFFULL
);
260 desc
= GEN8_CTX_VALID
;
261 desc
|= LEGACY_CONTEXT
<< GEN8_CTX_MODE_SHIFT
;
262 desc
|= GEN8_CTX_L3LLC_COHERENT
;
263 desc
|= GEN8_CTX_PRIVILEGE
;
265 desc
|= (u64
)intel_execlists_ctx_id(ctx_obj
) << GEN8_CTX_ID_SHIFT
;
267 /* TODO: WaDisableLiteRestore when we start using semaphore
268 * signalling between Command Streamers */
269 /* desc |= GEN8_CTX_FORCE_RESTORE; */
274 static void execlists_elsp_write(struct intel_engine_cs
*ring
,
275 struct drm_i915_gem_object
*ctx_obj0
,
276 struct drm_i915_gem_object
*ctx_obj1
)
278 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
283 /* XXX: You must always write both descriptors in the order below. */
285 temp
= execlists_ctx_descriptor(ctx_obj1
);
288 desc
[1] = (u32
)(temp
>> 32);
291 temp
= execlists_ctx_descriptor(ctx_obj0
);
292 desc
[3] = (u32
)(temp
>> 32);
295 /* Set Force Wakeup bit to prevent GT from entering C6 while ELSP writes
298 * The other problem is that we can't just call gen6_gt_force_wake_get()
299 * because that function calls intel_runtime_pm_get(), which might sleep.
300 * Instead, we do the runtime_pm_get/put when creating/destroying requests.
302 spin_lock_irqsave(&dev_priv
->uncore
.lock
, flags
);
303 if (IS_CHERRYVIEW(dev_priv
->dev
)) {
304 if (dev_priv
->uncore
.fw_rendercount
++ == 0)
305 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
,
307 if (dev_priv
->uncore
.fw_mediacount
++ == 0)
308 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
,
311 if (dev_priv
->uncore
.forcewake_count
++ == 0)
312 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
,
315 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, flags
);
317 I915_WRITE(RING_ELSP(ring
), desc
[1]);
318 I915_WRITE(RING_ELSP(ring
), desc
[0]);
319 I915_WRITE(RING_ELSP(ring
), desc
[3]);
320 /* The context is automatically loaded after the following */
321 I915_WRITE(RING_ELSP(ring
), desc
[2]);
323 /* ELSP is a wo register, so use another nearby reg for posting instead */
324 POSTING_READ(RING_EXECLIST_STATUS(ring
));
326 /* Release Force Wakeup (see the big comment above). */
327 spin_lock_irqsave(&dev_priv
->uncore
.lock
, flags
);
328 if (IS_CHERRYVIEW(dev_priv
->dev
)) {
329 if (--dev_priv
->uncore
.fw_rendercount
== 0)
330 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
,
332 if (--dev_priv
->uncore
.fw_mediacount
== 0)
333 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
,
336 if (--dev_priv
->uncore
.forcewake_count
== 0)
337 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
,
341 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, flags
);
344 static int execlists_ctx_write_tail(struct drm_i915_gem_object
*ctx_obj
, u32 tail
)
349 page
= i915_gem_object_get_page(ctx_obj
, 1);
350 reg_state
= kmap_atomic(page
);
352 reg_state
[CTX_RING_TAIL
+1] = tail
;
354 kunmap_atomic(reg_state
);
359 static int execlists_submit_context(struct intel_engine_cs
*ring
,
360 struct intel_context
*to0
, u32 tail0
,
361 struct intel_context
*to1
, u32 tail1
)
363 struct drm_i915_gem_object
*ctx_obj0
;
364 struct drm_i915_gem_object
*ctx_obj1
= NULL
;
366 ctx_obj0
= to0
->engine
[ring
->id
].state
;
368 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0
));
370 execlists_ctx_write_tail(ctx_obj0
, tail0
);
373 ctx_obj1
= to1
->engine
[ring
->id
].state
;
375 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1
));
377 execlists_ctx_write_tail(ctx_obj1
, tail1
);
380 execlists_elsp_write(ring
, ctx_obj0
, ctx_obj1
);
385 static void execlists_context_unqueue(struct intel_engine_cs
*ring
)
387 struct intel_ctx_submit_request
*req0
= NULL
, *req1
= NULL
;
388 struct intel_ctx_submit_request
*cursor
= NULL
, *tmp
= NULL
;
389 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
391 assert_spin_locked(&ring
->execlist_lock
);
393 if (list_empty(&ring
->execlist_queue
))
396 /* Try to read in pairs */
397 list_for_each_entry_safe(cursor
, tmp
, &ring
->execlist_queue
,
401 } else if (req0
->ctx
== cursor
->ctx
) {
402 /* Same ctx: ignore first request, as second request
403 * will update tail past first request's workload */
404 cursor
->elsp_submitted
= req0
->elsp_submitted
;
405 list_del(&req0
->execlist_link
);
406 queue_work(dev_priv
->wq
, &req0
->work
);
414 WARN_ON(req1
&& req1
->elsp_submitted
);
416 WARN_ON(execlists_submit_context(ring
, req0
->ctx
, req0
->tail
,
417 req1
? req1
->ctx
: NULL
,
418 req1
? req1
->tail
: 0));
420 req0
->elsp_submitted
++;
422 req1
->elsp_submitted
++;
425 static bool execlists_check_remove_request(struct intel_engine_cs
*ring
,
428 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
429 struct intel_ctx_submit_request
*head_req
;
431 assert_spin_locked(&ring
->execlist_lock
);
433 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
434 struct intel_ctx_submit_request
,
437 if (head_req
!= NULL
) {
438 struct drm_i915_gem_object
*ctx_obj
=
439 head_req
->ctx
->engine
[ring
->id
].state
;
440 if (intel_execlists_ctx_id(ctx_obj
) == request_id
) {
441 WARN(head_req
->elsp_submitted
== 0,
442 "Never submitted head request\n");
444 if (--head_req
->elsp_submitted
<= 0) {
445 list_del(&head_req
->execlist_link
);
446 queue_work(dev_priv
->wq
, &head_req
->work
);
456 * intel_execlists_handle_ctx_events() - handle Context Switch interrupts
457 * @ring: Engine Command Streamer to handle.
459 * Check the unread Context Status Buffers and manage the submission of new
460 * contexts to the ELSP accordingly.
462 void intel_execlists_handle_ctx_events(struct intel_engine_cs
*ring
)
464 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
470 u32 submit_contexts
= 0;
472 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
474 read_pointer
= ring
->next_context_status_buffer
;
475 write_pointer
= status_pointer
& 0x07;
476 if (read_pointer
> write_pointer
)
479 spin_lock(&ring
->execlist_lock
);
481 while (read_pointer
< write_pointer
) {
483 status
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
484 (read_pointer
% 6) * 8);
485 status_id
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
486 (read_pointer
% 6) * 8 + 4);
488 if (status
& GEN8_CTX_STATUS_PREEMPTED
) {
489 if (status
& GEN8_CTX_STATUS_LITE_RESTORE
) {
490 if (execlists_check_remove_request(ring
, status_id
))
491 WARN(1, "Lite Restored request removed from queue\n");
493 WARN(1, "Preemption without Lite Restore\n");
496 if ((status
& GEN8_CTX_STATUS_ACTIVE_IDLE
) ||
497 (status
& GEN8_CTX_STATUS_ELEMENT_SWITCH
)) {
498 if (execlists_check_remove_request(ring
, status_id
))
503 if (submit_contexts
!= 0)
504 execlists_context_unqueue(ring
);
506 spin_unlock(&ring
->execlist_lock
);
508 WARN(submit_contexts
> 2, "More than two context complete events?\n");
509 ring
->next_context_status_buffer
= write_pointer
% 6;
511 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring
),
512 ((u32
)ring
->next_context_status_buffer
& 0x07) << 8);
515 static void execlists_free_request_task(struct work_struct
*work
)
517 struct intel_ctx_submit_request
*req
=
518 container_of(work
, struct intel_ctx_submit_request
, work
);
519 struct drm_device
*dev
= req
->ring
->dev
;
520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
522 intel_runtime_pm_put(dev_priv
);
524 mutex_lock(&dev
->struct_mutex
);
525 i915_gem_context_unreference(req
->ctx
);
526 mutex_unlock(&dev
->struct_mutex
);
531 static int execlists_context_queue(struct intel_engine_cs
*ring
,
532 struct intel_context
*to
,
535 struct intel_ctx_submit_request
*req
= NULL
, *cursor
;
536 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
538 int num_elements
= 0;
540 req
= kzalloc(sizeof(*req
), GFP_KERNEL
);
544 i915_gem_context_reference(req
->ctx
);
547 INIT_WORK(&req
->work
, execlists_free_request_task
);
549 intel_runtime_pm_get(dev_priv
);
551 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
553 list_for_each_entry(cursor
, &ring
->execlist_queue
, execlist_link
)
554 if (++num_elements
> 2)
557 if (num_elements
> 2) {
558 struct intel_ctx_submit_request
*tail_req
;
560 tail_req
= list_last_entry(&ring
->execlist_queue
,
561 struct intel_ctx_submit_request
,
564 if (to
== tail_req
->ctx
) {
565 WARN(tail_req
->elsp_submitted
!= 0,
566 "More than 2 already-submitted reqs queued\n");
567 list_del(&tail_req
->execlist_link
);
568 queue_work(dev_priv
->wq
, &tail_req
->work
);
572 list_add_tail(&req
->execlist_link
, &ring
->execlist_queue
);
573 if (num_elements
== 0)
574 execlists_context_unqueue(ring
);
576 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
581 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer
*ringbuf
)
583 struct intel_engine_cs
*ring
= ringbuf
->ring
;
584 uint32_t flush_domains
;
588 if (ring
->gpu_caches_dirty
)
589 flush_domains
= I915_GEM_GPU_DOMAINS
;
591 ret
= ring
->emit_flush(ringbuf
, I915_GEM_GPU_DOMAINS
, flush_domains
);
595 ring
->gpu_caches_dirty
= false;
599 static int execlists_move_to_gpu(struct intel_ringbuffer
*ringbuf
,
600 struct list_head
*vmas
)
602 struct intel_engine_cs
*ring
= ringbuf
->ring
;
603 struct i915_vma
*vma
;
604 uint32_t flush_domains
= 0;
605 bool flush_chipset
= false;
608 list_for_each_entry(vma
, vmas
, exec_list
) {
609 struct drm_i915_gem_object
*obj
= vma
->obj
;
611 ret
= i915_gem_object_sync(obj
, ring
);
615 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
616 flush_chipset
|= i915_gem_clflush_object(obj
, false);
618 flush_domains
|= obj
->base
.write_domain
;
621 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
624 /* Unconditionally invalidate gpu caches and ensure that we do flush
625 * any residual writes from the previous batch.
627 return logical_ring_invalidate_all_caches(ringbuf
);
631 * execlists_submission() - submit a batchbuffer for execution, Execlists style
634 * @ring: Engine Command Streamer to submit to.
635 * @ctx: Context to employ for this submission.
636 * @args: execbuffer call arguments.
637 * @vmas: list of vmas.
638 * @batch_obj: the batchbuffer to submit.
639 * @exec_start: batchbuffer start virtual address pointer.
640 * @flags: translated execbuffer call flags.
642 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
643 * away the submission details of the execbuffer ioctl call.
645 * Return: non-zero if the submission fails.
647 int intel_execlists_submission(struct drm_device
*dev
, struct drm_file
*file
,
648 struct intel_engine_cs
*ring
,
649 struct intel_context
*ctx
,
650 struct drm_i915_gem_execbuffer2
*args
,
651 struct list_head
*vmas
,
652 struct drm_i915_gem_object
*batch_obj
,
653 u64 exec_start
, u32 flags
)
655 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
656 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
661 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
662 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
663 switch (instp_mode
) {
664 case I915_EXEC_CONSTANTS_REL_GENERAL
:
665 case I915_EXEC_CONSTANTS_ABSOLUTE
:
666 case I915_EXEC_CONSTANTS_REL_SURFACE
:
667 if (instp_mode
!= 0 && ring
!= &dev_priv
->ring
[RCS
]) {
668 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
672 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
673 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
674 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
678 /* The HW changed the meaning on this bit on gen6 */
679 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
683 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
687 if (args
->num_cliprects
!= 0) {
688 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
691 if (args
->DR4
== 0xffffffff) {
692 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
696 if (args
->DR1
|| args
->DR4
|| args
->cliprects_ptr
) {
697 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
702 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
703 DRM_DEBUG("sol reset is gen7 only\n");
707 ret
= execlists_move_to_gpu(ringbuf
, vmas
);
711 if (ring
== &dev_priv
->ring
[RCS
] &&
712 instp_mode
!= dev_priv
->relative_constants_mode
) {
713 ret
= intel_logical_ring_begin(ringbuf
, 4);
717 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
718 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
719 intel_logical_ring_emit(ringbuf
, INSTPM
);
720 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
721 intel_logical_ring_advance(ringbuf
);
723 dev_priv
->relative_constants_mode
= instp_mode
;
726 ret
= ring
->emit_bb_start(ringbuf
, exec_start
, flags
);
730 i915_gem_execbuffer_move_to_active(vmas
, ring
);
731 i915_gem_execbuffer_retire_commands(dev
, file
, ring
, batch_obj
);
736 void intel_logical_ring_stop(struct intel_engine_cs
*ring
)
738 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
741 if (!intel_ring_initialized(ring
))
744 ret
= intel_ring_idle(ring
);
745 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
746 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
749 /* TODO: Is this correct with Execlists enabled? */
750 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
751 if (wait_for_atomic((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
752 DRM_ERROR("%s :timed out trying to stop ring\n", ring
->name
);
755 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
758 int logical_ring_flush_all_caches(struct intel_ringbuffer
*ringbuf
)
760 struct intel_engine_cs
*ring
= ringbuf
->ring
;
763 if (!ring
->gpu_caches_dirty
)
766 ret
= ring
->emit_flush(ringbuf
, 0, I915_GEM_GPU_DOMAINS
);
770 ring
->gpu_caches_dirty
= false;
775 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
776 * @ringbuf: Logical Ringbuffer to advance.
778 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
779 * really happens during submission is that the context and current tail will be placed
780 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
781 * point, the tail *inside* the context is updated and the ELSP written to.
783 void intel_logical_ring_advance_and_submit(struct intel_ringbuffer
*ringbuf
)
785 struct intel_engine_cs
*ring
= ringbuf
->ring
;
786 struct intel_context
*ctx
= ringbuf
->FIXME_lrc_ctx
;
788 intel_logical_ring_advance(ringbuf
);
790 if (intel_ring_stopped(ring
))
793 execlists_context_queue(ring
, ctx
, ringbuf
->tail
);
796 static int logical_ring_alloc_seqno(struct intel_engine_cs
*ring
,
797 struct intel_context
*ctx
)
799 if (ring
->outstanding_lazy_seqno
)
802 if (ring
->preallocated_lazy_request
== NULL
) {
803 struct drm_i915_gem_request
*request
;
805 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
809 /* Hold a reference to the context this request belongs to
810 * (we will need it when the time comes to emit/retire the
814 i915_gem_context_reference(request
->ctx
);
816 ring
->preallocated_lazy_request
= request
;
819 return i915_gem_get_seqno(ring
->dev
, &ring
->outstanding_lazy_seqno
);
822 static int logical_ring_wait_request(struct intel_ringbuffer
*ringbuf
,
825 struct intel_engine_cs
*ring
= ringbuf
->ring
;
826 struct drm_i915_gem_request
*request
;
830 if (ringbuf
->last_retired_head
!= -1) {
831 ringbuf
->head
= ringbuf
->last_retired_head
;
832 ringbuf
->last_retired_head
= -1;
834 ringbuf
->space
= intel_ring_space(ringbuf
);
835 if (ringbuf
->space
>= bytes
)
839 list_for_each_entry(request
, &ring
->request_list
, list
) {
840 if (__intel_ring_space(request
->tail
, ringbuf
->tail
,
841 ringbuf
->size
) >= bytes
) {
842 seqno
= request
->seqno
;
850 ret
= i915_wait_seqno(ring
, seqno
);
854 i915_gem_retire_requests_ring(ring
);
855 ringbuf
->head
= ringbuf
->last_retired_head
;
856 ringbuf
->last_retired_head
= -1;
858 ringbuf
->space
= intel_ring_space(ringbuf
);
862 static int logical_ring_wait_for_space(struct intel_ringbuffer
*ringbuf
,
865 struct intel_engine_cs
*ring
= ringbuf
->ring
;
866 struct drm_device
*dev
= ring
->dev
;
867 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
871 ret
= logical_ring_wait_request(ringbuf
, bytes
);
875 /* Force the context submission in case we have been skipping it */
876 intel_logical_ring_advance_and_submit(ringbuf
);
878 /* With GEM the hangcheck timer should kick us out of the loop,
879 * leaving it early runs the risk of corrupting GEM state (due
880 * to running on almost untested codepaths). But on resume
881 * timers don't work yet, so prevent a complete hang in that
882 * case by choosing an insanely large timeout. */
883 end
= jiffies
+ 60 * HZ
;
886 ringbuf
->head
= I915_READ_HEAD(ring
);
887 ringbuf
->space
= intel_ring_space(ringbuf
);
888 if (ringbuf
->space
>= bytes
) {
895 if (dev_priv
->mm
.interruptible
&& signal_pending(current
)) {
900 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
901 dev_priv
->mm
.interruptible
);
905 if (time_after(jiffies
, end
)) {
914 static int logical_ring_wrap_buffer(struct intel_ringbuffer
*ringbuf
)
916 uint32_t __iomem
*virt
;
917 int rem
= ringbuf
->size
- ringbuf
->tail
;
919 if (ringbuf
->space
< rem
) {
920 int ret
= logical_ring_wait_for_space(ringbuf
, rem
);
926 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
929 iowrite32(MI_NOOP
, virt
++);
932 ringbuf
->space
= intel_ring_space(ringbuf
);
937 static int logical_ring_prepare(struct intel_ringbuffer
*ringbuf
, int bytes
)
941 if (unlikely(ringbuf
->tail
+ bytes
> ringbuf
->effective_size
)) {
942 ret
= logical_ring_wrap_buffer(ringbuf
);
947 if (unlikely(ringbuf
->space
< bytes
)) {
948 ret
= logical_ring_wait_for_space(ringbuf
, bytes
);
957 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
959 * @ringbuf: Logical ringbuffer.
960 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
962 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
963 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
964 * and also preallocates a request (every workload submission is still mediated through
965 * requests, same as it did with legacy ringbuffer submission).
967 * Return: non-zero if the ringbuffer is not ready to be written to.
969 int intel_logical_ring_begin(struct intel_ringbuffer
*ringbuf
, int num_dwords
)
971 struct intel_engine_cs
*ring
= ringbuf
->ring
;
972 struct drm_device
*dev
= ring
->dev
;
973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
976 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
977 dev_priv
->mm
.interruptible
);
981 ret
= logical_ring_prepare(ringbuf
, num_dwords
* sizeof(uint32_t));
985 /* Preallocate the olr before touching the ring */
986 ret
= logical_ring_alloc_seqno(ring
, ringbuf
->FIXME_lrc_ctx
);
990 ringbuf
->space
-= num_dwords
* sizeof(uint32_t);
994 static int gen8_init_common_ring(struct intel_engine_cs
*ring
)
996 struct drm_device
*dev
= ring
->dev
;
997 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
999 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1000 I915_WRITE(RING_HWSTAM(ring
->mmio_base
), 0xffffffff);
1002 I915_WRITE(RING_MODE_GEN7(ring
),
1003 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1004 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1005 POSTING_READ(RING_MODE_GEN7(ring
));
1006 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring
->name
);
1008 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
1013 static int gen8_init_render_ring(struct intel_engine_cs
*ring
)
1015 struct drm_device
*dev
= ring
->dev
;
1016 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1019 ret
= gen8_init_common_ring(ring
);
1023 /* We need to disable the AsyncFlip performance optimisations in order
1024 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1025 * programmed to '1' on all products.
1027 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1029 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1031 ret
= intel_init_pipe_control(ring
);
1035 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1040 static int gen8_emit_bb_start(struct intel_ringbuffer
*ringbuf
,
1041 u64 offset
, unsigned flags
)
1043 bool ppgtt
= !(flags
& I915_DISPATCH_SECURE
);
1046 ret
= intel_logical_ring_begin(ringbuf
, 4);
1050 /* FIXME(BDW): Address space and security selectors. */
1051 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8));
1052 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1053 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1054 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1055 intel_logical_ring_advance(ringbuf
);
1060 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*ring
)
1062 struct drm_device
*dev
= ring
->dev
;
1063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1064 unsigned long flags
;
1066 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1069 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1070 if (ring
->irq_refcount
++ == 0) {
1071 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1072 POSTING_READ(RING_IMR(ring
->mmio_base
));
1074 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1079 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*ring
)
1081 struct drm_device
*dev
= ring
->dev
;
1082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1083 unsigned long flags
;
1085 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1086 if (--ring
->irq_refcount
== 0) {
1087 I915_WRITE_IMR(ring
, ~ring
->irq_keep_mask
);
1088 POSTING_READ(RING_IMR(ring
->mmio_base
));
1090 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1093 static int gen8_emit_flush(struct intel_ringbuffer
*ringbuf
,
1094 u32 invalidate_domains
,
1097 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1098 struct drm_device
*dev
= ring
->dev
;
1099 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1103 ret
= intel_logical_ring_begin(ringbuf
, 4);
1107 cmd
= MI_FLUSH_DW
+ 1;
1109 if (ring
== &dev_priv
->ring
[VCS
]) {
1110 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
)
1111 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
|
1112 MI_FLUSH_DW_STORE_INDEX
|
1113 MI_FLUSH_DW_OP_STOREDW
;
1115 if (invalidate_domains
& I915_GEM_DOMAIN_RENDER
)
1116 cmd
|= MI_INVALIDATE_TLB
| MI_FLUSH_DW_STORE_INDEX
|
1117 MI_FLUSH_DW_OP_STOREDW
;
1120 intel_logical_ring_emit(ringbuf
, cmd
);
1121 intel_logical_ring_emit(ringbuf
,
1122 I915_GEM_HWS_SCRATCH_ADDR
|
1123 MI_FLUSH_DW_USE_GTT
);
1124 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1125 intel_logical_ring_emit(ringbuf
, 0); /* value */
1126 intel_logical_ring_advance(ringbuf
);
1131 static int gen8_emit_flush_render(struct intel_ringbuffer
*ringbuf
,
1132 u32 invalidate_domains
,
1135 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1136 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1140 flags
|= PIPE_CONTROL_CS_STALL
;
1142 if (flush_domains
) {
1143 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1144 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1147 if (invalidate_domains
) {
1148 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1149 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1150 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1151 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1152 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1153 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1154 flags
|= PIPE_CONTROL_QW_WRITE
;
1155 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1158 ret
= intel_logical_ring_begin(ringbuf
, 6);
1162 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1163 intel_logical_ring_emit(ringbuf
, flags
);
1164 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1165 intel_logical_ring_emit(ringbuf
, 0);
1166 intel_logical_ring_emit(ringbuf
, 0);
1167 intel_logical_ring_emit(ringbuf
, 0);
1168 intel_logical_ring_advance(ringbuf
);
1173 static u32
gen8_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1175 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1178 static void gen8_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1180 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1183 static int gen8_emit_request(struct intel_ringbuffer
*ringbuf
)
1185 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1189 ret
= intel_logical_ring_begin(ringbuf
, 6);
1193 cmd
= MI_STORE_DWORD_IMM_GEN8
;
1194 cmd
|= MI_GLOBAL_GTT
;
1196 intel_logical_ring_emit(ringbuf
, cmd
);
1197 intel_logical_ring_emit(ringbuf
,
1198 (ring
->status_page
.gfx_addr
+
1199 (I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
)));
1200 intel_logical_ring_emit(ringbuf
, 0);
1201 intel_logical_ring_emit(ringbuf
, ring
->outstanding_lazy_seqno
);
1202 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1203 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1204 intel_logical_ring_advance_and_submit(ringbuf
);
1210 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1212 * @ring: Engine Command Streamer.
1215 void intel_logical_ring_cleanup(struct intel_engine_cs
*ring
)
1217 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1219 if (!intel_ring_initialized(ring
))
1222 intel_logical_ring_stop(ring
);
1223 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1224 ring
->preallocated_lazy_request
= NULL
;
1225 ring
->outstanding_lazy_seqno
= 0;
1228 ring
->cleanup(ring
);
1230 i915_cmd_parser_fini_ring(ring
);
1232 if (ring
->status_page
.obj
) {
1233 kunmap(sg_page(ring
->status_page
.obj
->pages
->sgl
));
1234 ring
->status_page
.obj
= NULL
;
1238 static int logical_ring_init(struct drm_device
*dev
, struct intel_engine_cs
*ring
)
1242 /* Intentionally left blank. */
1243 ring
->buffer
= NULL
;
1246 INIT_LIST_HEAD(&ring
->active_list
);
1247 INIT_LIST_HEAD(&ring
->request_list
);
1248 init_waitqueue_head(&ring
->irq_queue
);
1250 INIT_LIST_HEAD(&ring
->execlist_queue
);
1251 spin_lock_init(&ring
->execlist_lock
);
1252 ring
->next_context_status_buffer
= 0;
1254 ret
= i915_cmd_parser_init_ring(ring
);
1259 ret
= ring
->init(ring
);
1264 ret
= intel_lr_context_deferred_create(ring
->default_context
, ring
);
1269 static int logical_render_ring_init(struct drm_device
*dev
)
1271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1272 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
1274 ring
->name
= "render ring";
1276 ring
->mmio_base
= RENDER_RING_BASE
;
1277 ring
->irq_enable_mask
=
1278 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1279 ring
->irq_keep_mask
=
1280 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1281 if (HAS_L3_DPF(dev
))
1282 ring
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
1284 ring
->init
= gen8_init_render_ring
;
1285 ring
->cleanup
= intel_fini_pipe_control
;
1286 ring
->get_seqno
= gen8_get_seqno
;
1287 ring
->set_seqno
= gen8_set_seqno
;
1288 ring
->emit_request
= gen8_emit_request
;
1289 ring
->emit_flush
= gen8_emit_flush_render
;
1290 ring
->irq_get
= gen8_logical_ring_get_irq
;
1291 ring
->irq_put
= gen8_logical_ring_put_irq
;
1292 ring
->emit_bb_start
= gen8_emit_bb_start
;
1294 return logical_ring_init(dev
, ring
);
1297 static int logical_bsd_ring_init(struct drm_device
*dev
)
1299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1300 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
1302 ring
->name
= "bsd ring";
1304 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
1305 ring
->irq_enable_mask
=
1306 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1307 ring
->irq_keep_mask
=
1308 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1310 ring
->init
= gen8_init_common_ring
;
1311 ring
->get_seqno
= gen8_get_seqno
;
1312 ring
->set_seqno
= gen8_set_seqno
;
1313 ring
->emit_request
= gen8_emit_request
;
1314 ring
->emit_flush
= gen8_emit_flush
;
1315 ring
->irq_get
= gen8_logical_ring_get_irq
;
1316 ring
->irq_put
= gen8_logical_ring_put_irq
;
1317 ring
->emit_bb_start
= gen8_emit_bb_start
;
1319 return logical_ring_init(dev
, ring
);
1322 static int logical_bsd2_ring_init(struct drm_device
*dev
)
1324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1325 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
1327 ring
->name
= "bds2 ring";
1329 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
1330 ring
->irq_enable_mask
=
1331 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
1332 ring
->irq_keep_mask
=
1333 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
1335 ring
->init
= gen8_init_common_ring
;
1336 ring
->get_seqno
= gen8_get_seqno
;
1337 ring
->set_seqno
= gen8_set_seqno
;
1338 ring
->emit_request
= gen8_emit_request
;
1339 ring
->emit_flush
= gen8_emit_flush
;
1340 ring
->irq_get
= gen8_logical_ring_get_irq
;
1341 ring
->irq_put
= gen8_logical_ring_put_irq
;
1342 ring
->emit_bb_start
= gen8_emit_bb_start
;
1344 return logical_ring_init(dev
, ring
);
1347 static int logical_blt_ring_init(struct drm_device
*dev
)
1349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1350 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
1352 ring
->name
= "blitter ring";
1354 ring
->mmio_base
= BLT_RING_BASE
;
1355 ring
->irq_enable_mask
=
1356 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
1357 ring
->irq_keep_mask
=
1358 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
1360 ring
->init
= gen8_init_common_ring
;
1361 ring
->get_seqno
= gen8_get_seqno
;
1362 ring
->set_seqno
= gen8_set_seqno
;
1363 ring
->emit_request
= gen8_emit_request
;
1364 ring
->emit_flush
= gen8_emit_flush
;
1365 ring
->irq_get
= gen8_logical_ring_get_irq
;
1366 ring
->irq_put
= gen8_logical_ring_put_irq
;
1367 ring
->emit_bb_start
= gen8_emit_bb_start
;
1369 return logical_ring_init(dev
, ring
);
1372 static int logical_vebox_ring_init(struct drm_device
*dev
)
1374 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1375 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
1377 ring
->name
= "video enhancement ring";
1379 ring
->mmio_base
= VEBOX_RING_BASE
;
1380 ring
->irq_enable_mask
=
1381 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
1382 ring
->irq_keep_mask
=
1383 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
1385 ring
->init
= gen8_init_common_ring
;
1386 ring
->get_seqno
= gen8_get_seqno
;
1387 ring
->set_seqno
= gen8_set_seqno
;
1388 ring
->emit_request
= gen8_emit_request
;
1389 ring
->emit_flush
= gen8_emit_flush
;
1390 ring
->irq_get
= gen8_logical_ring_get_irq
;
1391 ring
->irq_put
= gen8_logical_ring_put_irq
;
1392 ring
->emit_bb_start
= gen8_emit_bb_start
;
1394 return logical_ring_init(dev
, ring
);
1398 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1401 * This function inits the engines for an Execlists submission style (the equivalent in the
1402 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1403 * those engines that are present in the hardware.
1405 * Return: non-zero if the initialization failed.
1407 int intel_logical_rings_init(struct drm_device
*dev
)
1409 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1412 ret
= logical_render_ring_init(dev
);
1417 ret
= logical_bsd_ring_init(dev
);
1419 goto cleanup_render_ring
;
1423 ret
= logical_blt_ring_init(dev
);
1425 goto cleanup_bsd_ring
;
1428 if (HAS_VEBOX(dev
)) {
1429 ret
= logical_vebox_ring_init(dev
);
1431 goto cleanup_blt_ring
;
1434 if (HAS_BSD2(dev
)) {
1435 ret
= logical_bsd2_ring_init(dev
);
1437 goto cleanup_vebox_ring
;
1440 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
1442 goto cleanup_bsd2_ring
;
1447 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS2
]);
1449 intel_logical_ring_cleanup(&dev_priv
->ring
[VECS
]);
1451 intel_logical_ring_cleanup(&dev_priv
->ring
[BCS
]);
1453 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS
]);
1454 cleanup_render_ring
:
1455 intel_logical_ring_cleanup(&dev_priv
->ring
[RCS
]);
1460 int intel_lr_context_render_state_init(struct intel_engine_cs
*ring
,
1461 struct intel_context
*ctx
)
1463 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
1464 struct render_state so
;
1465 struct drm_i915_file_private
*file_priv
= ctx
->file_priv
;
1466 struct drm_file
*file
= file_priv
? file_priv
->file
: NULL
;
1469 ret
= i915_gem_render_state_prepare(ring
, &so
);
1473 if (so
.rodata
== NULL
)
1476 ret
= ring
->emit_bb_start(ringbuf
,
1478 I915_DISPATCH_SECURE
);
1482 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), ring
);
1484 ret
= __i915_add_request(ring
, file
, so
.obj
, NULL
);
1485 /* intel_logical_ring_add_request moves object to inactive if it
1488 i915_gem_render_state_fini(&so
);
1493 populate_lr_context(struct intel_context
*ctx
, struct drm_i915_gem_object
*ctx_obj
,
1494 struct intel_engine_cs
*ring
, struct intel_ringbuffer
*ringbuf
)
1496 struct drm_device
*dev
= ring
->dev
;
1497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1498 struct drm_i915_gem_object
*ring_obj
= ringbuf
->obj
;
1499 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
1501 uint32_t *reg_state
;
1505 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1507 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
1509 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1513 ret
= i915_gem_object_get_pages(ctx_obj
);
1515 DRM_DEBUG_DRIVER("Could not get object pages\n");
1519 i915_gem_object_pin_pages(ctx_obj
);
1521 /* The second page of the context object contains some fields which must
1522 * be set up prior to the first execution. */
1523 page
= i915_gem_object_get_page(ctx_obj
, 1);
1524 reg_state
= kmap_atomic(page
);
1526 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1527 * commands followed by (reg, value) pairs. The values we are setting here are
1528 * only for the first context restore: on a subsequent save, the GPU will
1529 * recreate this batchbuffer with new values (including all the missing
1530 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1531 if (ring
->id
== RCS
)
1532 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(14);
1534 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(11);
1535 reg_state
[CTX_LRI_HEADER_0
] |= MI_LRI_FORCE_POSTED
;
1536 reg_state
[CTX_CONTEXT_CONTROL
] = RING_CONTEXT_CONTROL(ring
);
1537 reg_state
[CTX_CONTEXT_CONTROL
+1] =
1538 _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT
);
1539 reg_state
[CTX_RING_HEAD
] = RING_HEAD(ring
->mmio_base
);
1540 reg_state
[CTX_RING_HEAD
+1] = 0;
1541 reg_state
[CTX_RING_TAIL
] = RING_TAIL(ring
->mmio_base
);
1542 reg_state
[CTX_RING_TAIL
+1] = 0;
1543 reg_state
[CTX_RING_BUFFER_START
] = RING_START(ring
->mmio_base
);
1544 reg_state
[CTX_RING_BUFFER_START
+1] = i915_gem_obj_ggtt_offset(ring_obj
);
1545 reg_state
[CTX_RING_BUFFER_CONTROL
] = RING_CTL(ring
->mmio_base
);
1546 reg_state
[CTX_RING_BUFFER_CONTROL
+1] =
1547 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
;
1548 reg_state
[CTX_BB_HEAD_U
] = ring
->mmio_base
+ 0x168;
1549 reg_state
[CTX_BB_HEAD_U
+1] = 0;
1550 reg_state
[CTX_BB_HEAD_L
] = ring
->mmio_base
+ 0x140;
1551 reg_state
[CTX_BB_HEAD_L
+1] = 0;
1552 reg_state
[CTX_BB_STATE
] = ring
->mmio_base
+ 0x110;
1553 reg_state
[CTX_BB_STATE
+1] = (1<<5);
1554 reg_state
[CTX_SECOND_BB_HEAD_U
] = ring
->mmio_base
+ 0x11c;
1555 reg_state
[CTX_SECOND_BB_HEAD_U
+1] = 0;
1556 reg_state
[CTX_SECOND_BB_HEAD_L
] = ring
->mmio_base
+ 0x114;
1557 reg_state
[CTX_SECOND_BB_HEAD_L
+1] = 0;
1558 reg_state
[CTX_SECOND_BB_STATE
] = ring
->mmio_base
+ 0x118;
1559 reg_state
[CTX_SECOND_BB_STATE
+1] = 0;
1560 if (ring
->id
== RCS
) {
1561 /* TODO: according to BSpec, the register state context
1562 * for CHV does not have these. OTOH, these registers do
1563 * exist in CHV. I'm waiting for a clarification */
1564 reg_state
[CTX_BB_PER_CTX_PTR
] = ring
->mmio_base
+ 0x1c0;
1565 reg_state
[CTX_BB_PER_CTX_PTR
+1] = 0;
1566 reg_state
[CTX_RCS_INDIRECT_CTX
] = ring
->mmio_base
+ 0x1c4;
1567 reg_state
[CTX_RCS_INDIRECT_CTX
+1] = 0;
1568 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
] = ring
->mmio_base
+ 0x1c8;
1569 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] = 0;
1571 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9);
1572 reg_state
[CTX_LRI_HEADER_1
] |= MI_LRI_FORCE_POSTED
;
1573 reg_state
[CTX_CTX_TIMESTAMP
] = ring
->mmio_base
+ 0x3a8;
1574 reg_state
[CTX_CTX_TIMESTAMP
+1] = 0;
1575 reg_state
[CTX_PDP3_UDW
] = GEN8_RING_PDP_UDW(ring
, 3);
1576 reg_state
[CTX_PDP3_LDW
] = GEN8_RING_PDP_LDW(ring
, 3);
1577 reg_state
[CTX_PDP2_UDW
] = GEN8_RING_PDP_UDW(ring
, 2);
1578 reg_state
[CTX_PDP2_LDW
] = GEN8_RING_PDP_LDW(ring
, 2);
1579 reg_state
[CTX_PDP1_UDW
] = GEN8_RING_PDP_UDW(ring
, 1);
1580 reg_state
[CTX_PDP1_LDW
] = GEN8_RING_PDP_LDW(ring
, 1);
1581 reg_state
[CTX_PDP0_UDW
] = GEN8_RING_PDP_UDW(ring
, 0);
1582 reg_state
[CTX_PDP0_LDW
] = GEN8_RING_PDP_LDW(ring
, 0);
1583 reg_state
[CTX_PDP3_UDW
+1] = upper_32_bits(ppgtt
->pd_dma_addr
[3]);
1584 reg_state
[CTX_PDP3_LDW
+1] = lower_32_bits(ppgtt
->pd_dma_addr
[3]);
1585 reg_state
[CTX_PDP2_UDW
+1] = upper_32_bits(ppgtt
->pd_dma_addr
[2]);
1586 reg_state
[CTX_PDP2_LDW
+1] = lower_32_bits(ppgtt
->pd_dma_addr
[2]);
1587 reg_state
[CTX_PDP1_UDW
+1] = upper_32_bits(ppgtt
->pd_dma_addr
[1]);
1588 reg_state
[CTX_PDP1_LDW
+1] = lower_32_bits(ppgtt
->pd_dma_addr
[1]);
1589 reg_state
[CTX_PDP0_UDW
+1] = upper_32_bits(ppgtt
->pd_dma_addr
[0]);
1590 reg_state
[CTX_PDP0_LDW
+1] = lower_32_bits(ppgtt
->pd_dma_addr
[0]);
1591 if (ring
->id
== RCS
) {
1592 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
1593 reg_state
[CTX_R_PWR_CLK_STATE
] = 0x20c8;
1594 reg_state
[CTX_R_PWR_CLK_STATE
+1] = 0;
1597 kunmap_atomic(reg_state
);
1600 set_page_dirty(page
);
1601 i915_gem_object_unpin_pages(ctx_obj
);
1607 * intel_lr_context_free() - free the LRC specific bits of a context
1608 * @ctx: the LR context to free.
1610 * The real context freeing is done in i915_gem_context_free: this only
1611 * takes care of the bits that are LRC related: the per-engine backing
1612 * objects and the logical ringbuffer.
1614 void intel_lr_context_free(struct intel_context
*ctx
)
1618 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1619 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
1620 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[i
].ringbuf
;
1623 intel_destroy_ringbuffer_obj(ringbuf
);
1625 i915_gem_object_ggtt_unpin(ctx_obj
);
1626 drm_gem_object_unreference(&ctx_obj
->base
);
1631 static uint32_t get_lr_context_size(struct intel_engine_cs
*ring
)
1635 WARN_ON(INTEL_INFO(ring
->dev
)->gen
!= 8);
1639 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
1645 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
1653 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
1654 * @ctx: LR context to create.
1655 * @ring: engine to be used with the context.
1657 * This function can be called more than once, with different engines, if we plan
1658 * to use the context with them. The context backing objects and the ringbuffers
1659 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
1660 * the creation is a deferred call: it's better to make sure first that we need to use
1661 * a given ring with the context.
1663 * Return: non-zero on error.
1665 int intel_lr_context_deferred_create(struct intel_context
*ctx
,
1666 struct intel_engine_cs
*ring
)
1668 struct drm_device
*dev
= ring
->dev
;
1669 struct drm_i915_gem_object
*ctx_obj
;
1670 uint32_t context_size
;
1671 struct intel_ringbuffer
*ringbuf
;
1674 WARN_ON(ctx
->legacy_hw_ctx
.rcs_state
!= NULL
);
1675 if (ctx
->engine
[ring
->id
].state
)
1678 context_size
= round_up(get_lr_context_size(ring
), 4096);
1680 ctx_obj
= i915_gem_alloc_context_obj(dev
, context_size
);
1681 if (IS_ERR(ctx_obj
)) {
1682 ret
= PTR_ERR(ctx_obj
);
1683 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret
);
1687 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
, 0);
1689 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", ret
);
1690 drm_gem_object_unreference(&ctx_obj
->base
);
1694 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
1696 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1698 i915_gem_object_ggtt_unpin(ctx_obj
);
1699 drm_gem_object_unreference(&ctx_obj
->base
);
1704 ringbuf
->ring
= ring
;
1705 ringbuf
->FIXME_lrc_ctx
= ctx
;
1707 ringbuf
->size
= 32 * PAGE_SIZE
;
1708 ringbuf
->effective_size
= ringbuf
->size
;
1711 ringbuf
->space
= ringbuf
->size
;
1712 ringbuf
->last_retired_head
= -1;
1714 /* TODO: For now we put this in the mappable region so that we can reuse
1715 * the existing ringbuffer code which ioremaps it. When we start
1716 * creating many contexts, this will no longer work and we must switch
1717 * to a kmapish interface.
1719 ret
= intel_alloc_ringbuffer_obj(dev
, ringbuf
);
1721 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer obj %s: %d\n",
1726 ret
= populate_lr_context(ctx
, ctx_obj
, ring
, ringbuf
);
1728 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
1729 intel_destroy_ringbuffer_obj(ringbuf
);
1733 ctx
->engine
[ring
->id
].ringbuf
= ringbuf
;
1734 ctx
->engine
[ring
->id
].state
= ctx_obj
;
1736 if (ctx
== ring
->default_context
) {
1737 /* The status page is offset 0 from the default context object
1739 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(ctx_obj
);
1740 ring
->status_page
.page_addr
=
1741 kmap(sg_page(ctx_obj
->pages
->sgl
));
1742 if (ring
->status_page
.page_addr
== NULL
)
1744 ring
->status_page
.obj
= ctx_obj
;
1747 if (ring
->id
== RCS
&& !ctx
->rcs_initialized
) {
1748 ret
= intel_lr_context_render_state_init(ring
, ctx
);
1750 DRM_ERROR("Init render state failed: %d\n", ret
);
1751 ctx
->engine
[ring
->id
].ringbuf
= NULL
;
1752 ctx
->engine
[ring
->id
].state
= NULL
;
1753 intel_destroy_ringbuffer_obj(ringbuf
);
1756 ctx
->rcs_initialized
= true;
1763 i915_gem_object_ggtt_unpin(ctx_obj
);
1764 drm_gem_object_unreference(&ctx_obj
->base
);