2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
138 #include "intel_mocs.h"
140 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
144 #define RING_EXECLIST_QFULL (1 << 0x2)
145 #define RING_EXECLIST1_VALID (1 << 0x3)
146 #define RING_EXECLIST0_VALID (1 << 0x4)
147 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
148 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
149 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
151 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
152 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
153 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
154 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
155 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
156 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
158 #define CTX_LRI_HEADER_0 0x01
159 #define CTX_CONTEXT_CONTROL 0x02
160 #define CTX_RING_HEAD 0x04
161 #define CTX_RING_TAIL 0x06
162 #define CTX_RING_BUFFER_START 0x08
163 #define CTX_RING_BUFFER_CONTROL 0x0a
164 #define CTX_BB_HEAD_U 0x0c
165 #define CTX_BB_HEAD_L 0x0e
166 #define CTX_BB_STATE 0x10
167 #define CTX_SECOND_BB_HEAD_U 0x12
168 #define CTX_SECOND_BB_HEAD_L 0x14
169 #define CTX_SECOND_BB_STATE 0x16
170 #define CTX_BB_PER_CTX_PTR 0x18
171 #define CTX_RCS_INDIRECT_CTX 0x1a
172 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
173 #define CTX_LRI_HEADER_1 0x21
174 #define CTX_CTX_TIMESTAMP 0x22
175 #define CTX_PDP3_UDW 0x24
176 #define CTX_PDP3_LDW 0x26
177 #define CTX_PDP2_UDW 0x28
178 #define CTX_PDP2_LDW 0x2a
179 #define CTX_PDP1_UDW 0x2c
180 #define CTX_PDP1_LDW 0x2e
181 #define CTX_PDP0_UDW 0x30
182 #define CTX_PDP0_LDW 0x32
183 #define CTX_LRI_HEADER_2 0x41
184 #define CTX_R_PWR_CLK_STATE 0x42
185 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
187 #define GEN8_CTX_VALID (1<<0)
188 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
189 #define GEN8_CTX_FORCE_RESTORE (1<<2)
190 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
191 #define GEN8_CTX_PRIVILEGE (1<<8)
193 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
194 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
195 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
196 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
199 #define ASSIGN_CTX_PML4(ppgtt, reg_state) { \
200 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
201 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
205 ADVANCED_CONTEXT
= 0,
210 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
211 #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
212 LEGACY_64B_CONTEXT :\
216 FAULT_AND_HALT
, /* Debug only */
218 FAULT_AND_CONTINUE
/* Unsupported */
220 #define GEN8_CTX_ID_SHIFT 32
221 #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
223 static int intel_lr_context_pin(struct drm_i915_gem_request
*rq
);
224 static void lrc_setup_hardware_status_page(struct intel_engine_cs
*ring
,
225 struct drm_i915_gem_object
*default_ctx_obj
);
229 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
231 * @enable_execlists: value of i915.enable_execlists module parameter.
233 * Only certain platforms support Execlists (the prerequisites being
234 * support for Logical Ring Contexts and Aliasing PPGTT or better).
236 * Return: 1 if Execlists is supported and has to be enabled.
238 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
)
240 WARN_ON(i915
.enable_ppgtt
== -1);
242 /* On platforms with execlist available, vGPU will only
243 * support execlist mode, no ring buffer mode.
245 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && intel_vgpu_active(dev
))
248 if (INTEL_INFO(dev
)->gen
>= 9)
251 if (enable_execlists
== 0)
254 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && USES_PPGTT(dev
) &&
255 i915
.use_mmio_flip
>= 0)
262 * intel_execlists_ctx_id() - get the Execlists Context ID
263 * @ctx_obj: Logical Ring Context backing object.
265 * Do not confuse with ctx->id! Unfortunately we have a name overload
266 * here: the old context ID we pass to userspace as a handler so that
267 * they can refer to a context, and the new context ID we pass to the
268 * ELSP so that the GPU can inform us of the context status via
271 * Return: 20-bits globally unique context ID.
273 u32
intel_execlists_ctx_id(struct drm_i915_gem_object
*ctx_obj
)
275 u32 lrca
= i915_gem_obj_ggtt_offset(ctx_obj
) +
276 LRC_PPHWSP_PN
* PAGE_SIZE
;
278 /* LRCA is required to be 4K aligned so the more significant 20 bits
279 * are globally unique */
283 static bool disable_lite_restore_wa(struct intel_engine_cs
*ring
)
285 struct drm_device
*dev
= ring
->dev
;
287 return ((IS_SKYLAKE(dev
) && INTEL_REVID(dev
) <= SKL_REVID_B0
) ||
288 (IS_BROXTON(dev
) && INTEL_REVID(dev
) == BXT_REVID_A0
)) &&
289 (ring
->id
== VCS
|| ring
->id
== VCS2
);
292 uint64_t intel_lr_context_descriptor(struct intel_context
*ctx
,
293 struct intel_engine_cs
*ring
)
295 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[ring
->id
].state
;
297 uint64_t lrca
= i915_gem_obj_ggtt_offset(ctx_obj
) +
298 LRC_PPHWSP_PN
* PAGE_SIZE
;
300 WARN_ON(lrca
& 0xFFFFFFFF00000FFFULL
);
302 desc
= GEN8_CTX_VALID
;
303 desc
|= GEN8_CTX_ADDRESSING_MODE(dev
) << GEN8_CTX_ADDRESSING_MODE_SHIFT
;
304 if (IS_GEN8(ctx_obj
->base
.dev
))
305 desc
|= GEN8_CTX_L3LLC_COHERENT
;
306 desc
|= GEN8_CTX_PRIVILEGE
;
308 desc
|= (u64
)intel_execlists_ctx_id(ctx_obj
) << GEN8_CTX_ID_SHIFT
;
310 /* TODO: WaDisableLiteRestore when we start using semaphore
311 * signalling between Command Streamers */
312 /* desc |= GEN8_CTX_FORCE_RESTORE; */
314 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
315 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
316 if (disable_lite_restore_wa(ring
))
317 desc
|= GEN8_CTX_FORCE_RESTORE
;
322 static void execlists_elsp_write(struct drm_i915_gem_request
*rq0
,
323 struct drm_i915_gem_request
*rq1
)
326 struct intel_engine_cs
*ring
= rq0
->ring
;
327 struct drm_device
*dev
= ring
->dev
;
328 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
332 desc
[1] = intel_lr_context_descriptor(rq1
->ctx
, rq1
->ring
);
333 rq1
->elsp_submitted
++;
338 desc
[0] = intel_lr_context_descriptor(rq0
->ctx
, rq0
->ring
);
339 rq0
->elsp_submitted
++;
341 /* You must always write both descriptors in the order below. */
342 spin_lock(&dev_priv
->uncore
.lock
);
343 intel_uncore_forcewake_get__locked(dev_priv
, FORCEWAKE_ALL
);
344 I915_WRITE_FW(RING_ELSP(ring
), upper_32_bits(desc
[1]));
345 I915_WRITE_FW(RING_ELSP(ring
), lower_32_bits(desc
[1]));
347 I915_WRITE_FW(RING_ELSP(ring
), upper_32_bits(desc
[0]));
348 /* The context is automatically loaded after the following */
349 I915_WRITE_FW(RING_ELSP(ring
), lower_32_bits(desc
[0]));
351 /* ELSP is a wo register, use another nearby reg for posting */
352 POSTING_READ_FW(RING_EXECLIST_STATUS(ring
));
353 intel_uncore_forcewake_put__locked(dev_priv
, FORCEWAKE_ALL
);
354 spin_unlock(&dev_priv
->uncore
.lock
);
357 static int execlists_update_context(struct drm_i915_gem_request
*rq
)
359 struct intel_engine_cs
*ring
= rq
->ring
;
360 struct i915_hw_ppgtt
*ppgtt
= rq
->ctx
->ppgtt
;
361 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
362 struct drm_i915_gem_object
*rb_obj
= rq
->ringbuf
->obj
;
367 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj
));
368 WARN_ON(!i915_gem_obj_is_pinned(rb_obj
));
370 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
371 reg_state
= kmap_atomic(page
);
373 reg_state
[CTX_RING_TAIL
+1] = rq
->tail
;
374 reg_state
[CTX_RING_BUFFER_START
+1] = i915_gem_obj_ggtt_offset(rb_obj
);
376 if (ppgtt
&& !USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
377 /* True 32b PPGTT with dynamic page allocation: update PDP
378 * registers and point the unallocated PDPs to scratch page.
379 * PML4 is allocated during ppgtt init, so this is not needed
382 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
383 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
384 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
385 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
388 kunmap_atomic(reg_state
);
393 static void execlists_submit_requests(struct drm_i915_gem_request
*rq0
,
394 struct drm_i915_gem_request
*rq1
)
396 execlists_update_context(rq0
);
399 execlists_update_context(rq1
);
401 execlists_elsp_write(rq0
, rq1
);
404 static void execlists_context_unqueue(struct intel_engine_cs
*ring
)
406 struct drm_i915_gem_request
*req0
= NULL
, *req1
= NULL
;
407 struct drm_i915_gem_request
*cursor
= NULL
, *tmp
= NULL
;
409 assert_spin_locked(&ring
->execlist_lock
);
412 * If irqs are not active generate a warning as batches that finish
413 * without the irqs may get lost and a GPU Hang may occur.
415 WARN_ON(!intel_irqs_enabled(ring
->dev
->dev_private
));
417 if (list_empty(&ring
->execlist_queue
))
420 /* Try to read in pairs */
421 list_for_each_entry_safe(cursor
, tmp
, &ring
->execlist_queue
,
425 } else if (req0
->ctx
== cursor
->ctx
) {
426 /* Same ctx: ignore first request, as second request
427 * will update tail past first request's workload */
428 cursor
->elsp_submitted
= req0
->elsp_submitted
;
429 list_del(&req0
->execlist_link
);
430 list_add_tail(&req0
->execlist_link
,
431 &ring
->execlist_retired_req_list
);
439 if (IS_GEN8(ring
->dev
) || IS_GEN9(ring
->dev
)) {
441 * WaIdleLiteRestore: make sure we never cause a lite
442 * restore with HEAD==TAIL
444 if (req0
->elsp_submitted
) {
446 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
447 * as we resubmit the request. See gen8_emit_request()
448 * for where we prepare the padding after the end of the
451 struct intel_ringbuffer
*ringbuf
;
453 ringbuf
= req0
->ctx
->engine
[ring
->id
].ringbuf
;
455 req0
->tail
&= ringbuf
->size
- 1;
459 WARN_ON(req1
&& req1
->elsp_submitted
);
461 execlists_submit_requests(req0
, req1
);
464 static bool execlists_check_remove_request(struct intel_engine_cs
*ring
,
467 struct drm_i915_gem_request
*head_req
;
469 assert_spin_locked(&ring
->execlist_lock
);
471 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
472 struct drm_i915_gem_request
,
475 if (head_req
!= NULL
) {
476 struct drm_i915_gem_object
*ctx_obj
=
477 head_req
->ctx
->engine
[ring
->id
].state
;
478 if (intel_execlists_ctx_id(ctx_obj
) == request_id
) {
479 WARN(head_req
->elsp_submitted
== 0,
480 "Never submitted head request\n");
482 if (--head_req
->elsp_submitted
<= 0) {
483 list_del(&head_req
->execlist_link
);
484 list_add_tail(&head_req
->execlist_link
,
485 &ring
->execlist_retired_req_list
);
495 * intel_lrc_irq_handler() - handle Context Switch interrupts
496 * @ring: Engine Command Streamer to handle.
498 * Check the unread Context Status Buffers and manage the submission of new
499 * contexts to the ELSP accordingly.
501 void intel_lrc_irq_handler(struct intel_engine_cs
*ring
)
503 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
509 u32 submit_contexts
= 0;
511 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
513 read_pointer
= ring
->next_context_status_buffer
;
514 write_pointer
= status_pointer
& 0x07;
515 if (read_pointer
> write_pointer
)
518 spin_lock(&ring
->execlist_lock
);
520 while (read_pointer
< write_pointer
) {
522 status
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
523 (read_pointer
% 6) * 8);
524 status_id
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
525 (read_pointer
% 6) * 8 + 4);
527 if (status
& GEN8_CTX_STATUS_IDLE_ACTIVE
)
530 if (status
& GEN8_CTX_STATUS_PREEMPTED
) {
531 if (status
& GEN8_CTX_STATUS_LITE_RESTORE
) {
532 if (execlists_check_remove_request(ring
, status_id
))
533 WARN(1, "Lite Restored request removed from queue\n");
535 WARN(1, "Preemption without Lite Restore\n");
538 if ((status
& GEN8_CTX_STATUS_ACTIVE_IDLE
) ||
539 (status
& GEN8_CTX_STATUS_ELEMENT_SWITCH
)) {
540 if (execlists_check_remove_request(ring
, status_id
))
545 if (disable_lite_restore_wa(ring
)) {
546 /* Prevent a ctx to preempt itself */
547 if ((status
& GEN8_CTX_STATUS_ACTIVE_IDLE
) &&
548 (submit_contexts
!= 0))
549 execlists_context_unqueue(ring
);
550 } else if (submit_contexts
!= 0) {
551 execlists_context_unqueue(ring
);
554 spin_unlock(&ring
->execlist_lock
);
556 WARN(submit_contexts
> 2, "More than two context complete events?\n");
557 ring
->next_context_status_buffer
= write_pointer
% 6;
559 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring
),
560 _MASKED_FIELD(0x07 << 8, ((u32
)ring
->next_context_status_buffer
& 0x07) << 8));
563 static int execlists_context_queue(struct drm_i915_gem_request
*request
)
565 struct intel_engine_cs
*ring
= request
->ring
;
566 struct drm_i915_gem_request
*cursor
;
567 int num_elements
= 0;
569 if (request
->ctx
!= ring
->default_context
)
570 intel_lr_context_pin(request
);
572 i915_gem_request_reference(request
);
574 spin_lock_irq(&ring
->execlist_lock
);
576 list_for_each_entry(cursor
, &ring
->execlist_queue
, execlist_link
)
577 if (++num_elements
> 2)
580 if (num_elements
> 2) {
581 struct drm_i915_gem_request
*tail_req
;
583 tail_req
= list_last_entry(&ring
->execlist_queue
,
584 struct drm_i915_gem_request
,
587 if (request
->ctx
== tail_req
->ctx
) {
588 WARN(tail_req
->elsp_submitted
!= 0,
589 "More than 2 already-submitted reqs queued\n");
590 list_del(&tail_req
->execlist_link
);
591 list_add_tail(&tail_req
->execlist_link
,
592 &ring
->execlist_retired_req_list
);
596 list_add_tail(&request
->execlist_link
, &ring
->execlist_queue
);
597 if (num_elements
== 0)
598 execlists_context_unqueue(ring
);
600 spin_unlock_irq(&ring
->execlist_lock
);
605 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
607 struct intel_engine_cs
*ring
= req
->ring
;
608 uint32_t flush_domains
;
612 if (ring
->gpu_caches_dirty
)
613 flush_domains
= I915_GEM_GPU_DOMAINS
;
615 ret
= ring
->emit_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
619 ring
->gpu_caches_dirty
= false;
623 static int execlists_move_to_gpu(struct drm_i915_gem_request
*req
,
624 struct list_head
*vmas
)
626 const unsigned other_rings
= ~intel_ring_flag(req
->ring
);
627 struct i915_vma
*vma
;
628 uint32_t flush_domains
= 0;
629 bool flush_chipset
= false;
632 list_for_each_entry(vma
, vmas
, exec_list
) {
633 struct drm_i915_gem_object
*obj
= vma
->obj
;
635 if (obj
->active
& other_rings
) {
636 ret
= i915_gem_object_sync(obj
, req
->ring
, &req
);
641 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
642 flush_chipset
|= i915_gem_clflush_object(obj
, false);
644 flush_domains
|= obj
->base
.write_domain
;
647 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
650 /* Unconditionally invalidate gpu caches and ensure that we do flush
651 * any residual writes from the previous batch.
653 return logical_ring_invalidate_all_caches(req
);
656 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
660 request
->ringbuf
= request
->ctx
->engine
[request
->ring
->id
].ringbuf
;
662 if (request
->ctx
!= request
->ring
->default_context
) {
663 ret
= intel_lr_context_pin(request
);
671 static int logical_ring_wait_for_space(struct drm_i915_gem_request
*req
,
674 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
675 struct intel_engine_cs
*ring
= req
->ring
;
676 struct drm_i915_gem_request
*target
;
680 if (intel_ring_space(ringbuf
) >= bytes
)
683 /* The whole point of reserving space is to not wait! */
684 WARN_ON(ringbuf
->reserved_in_use
);
686 list_for_each_entry(target
, &ring
->request_list
, list
) {
688 * The request queue is per-engine, so can contain requests
689 * from multiple ringbuffers. Here, we must ignore any that
690 * aren't from the ringbuffer we're considering.
692 if (target
->ringbuf
!= ringbuf
)
695 /* Would completion of this request free enough space? */
696 space
= __intel_ring_space(target
->postfix
, ringbuf
->tail
,
702 if (WARN_ON(&target
->list
== &ring
->request_list
))
705 ret
= i915_wait_request(target
);
709 ringbuf
->space
= space
;
714 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
715 * @request: Request to advance the logical ringbuffer of.
717 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
718 * really happens during submission is that the context and current tail will be placed
719 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
720 * point, the tail *inside* the context is updated and the ELSP written to.
723 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request
*request
)
725 struct intel_engine_cs
*ring
= request
->ring
;
726 struct drm_i915_private
*dev_priv
= request
->i915
;
728 intel_logical_ring_advance(request
->ringbuf
);
730 request
->tail
= request
->ringbuf
->tail
;
732 if (intel_ring_stopped(ring
))
735 if (dev_priv
->guc
.execbuf_client
)
736 i915_guc_submit(dev_priv
->guc
.execbuf_client
, request
);
738 execlists_context_queue(request
);
741 static void __wrap_ring_buffer(struct intel_ringbuffer
*ringbuf
)
743 uint32_t __iomem
*virt
;
744 int rem
= ringbuf
->size
- ringbuf
->tail
;
746 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
749 iowrite32(MI_NOOP
, virt
++);
752 intel_ring_update_space(ringbuf
);
755 static int logical_ring_prepare(struct drm_i915_gem_request
*req
, int bytes
)
757 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
758 int remain_usable
= ringbuf
->effective_size
- ringbuf
->tail
;
759 int remain_actual
= ringbuf
->size
- ringbuf
->tail
;
760 int ret
, total_bytes
, wait_bytes
= 0;
761 bool need_wrap
= false;
763 if (ringbuf
->reserved_in_use
)
766 total_bytes
= bytes
+ ringbuf
->reserved_size
;
768 if (unlikely(bytes
> remain_usable
)) {
770 * Not enough space for the basic request. So need to flush
771 * out the remainder and then wait for base + reserved.
773 wait_bytes
= remain_actual
+ total_bytes
;
776 if (unlikely(total_bytes
> remain_usable
)) {
778 * The base request will fit but the reserved space
779 * falls off the end. So only need to to wait for the
780 * reserved size after flushing out the remainder.
782 wait_bytes
= remain_actual
+ ringbuf
->reserved_size
;
784 } else if (total_bytes
> ringbuf
->space
) {
785 /* No wrapping required, just waiting. */
786 wait_bytes
= total_bytes
;
791 ret
= logical_ring_wait_for_space(req
, wait_bytes
);
796 __wrap_ring_buffer(ringbuf
);
803 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
805 * @req: The request to start some new work for
806 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
808 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
809 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
810 * and also preallocates a request (every workload submission is still mediated through
811 * requests, same as it did with legacy ringbuffer submission).
813 * Return: non-zero if the ringbuffer is not ready to be written to.
815 int intel_logical_ring_begin(struct drm_i915_gem_request
*req
, int num_dwords
)
817 struct drm_i915_private
*dev_priv
;
820 WARN_ON(req
== NULL
);
821 dev_priv
= req
->ring
->dev
->dev_private
;
823 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
824 dev_priv
->mm
.interruptible
);
828 ret
= logical_ring_prepare(req
, num_dwords
* sizeof(uint32_t));
832 req
->ringbuf
->space
-= num_dwords
* sizeof(uint32_t);
836 int intel_logical_ring_reserve_space(struct drm_i915_gem_request
*request
)
839 * The first call merely notes the reserve request and is common for
840 * all back ends. The subsequent localised _begin() call actually
841 * ensures that the reservation is available. Without the begin, if
842 * the request creator immediately submitted the request without
843 * adding any commands to it then there might not actually be
844 * sufficient room for the submission commands.
846 intel_ring_reserved_space_reserve(request
->ringbuf
, MIN_SPACE_FOR_ADD_REQUEST
);
848 return intel_logical_ring_begin(request
, 0);
852 * execlists_submission() - submit a batchbuffer for execution, Execlists style
855 * @ring: Engine Command Streamer to submit to.
856 * @ctx: Context to employ for this submission.
857 * @args: execbuffer call arguments.
858 * @vmas: list of vmas.
859 * @batch_obj: the batchbuffer to submit.
860 * @exec_start: batchbuffer start virtual address pointer.
861 * @dispatch_flags: translated execbuffer call flags.
863 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
864 * away the submission details of the execbuffer ioctl call.
866 * Return: non-zero if the submission fails.
868 int intel_execlists_submission(struct i915_execbuffer_params
*params
,
869 struct drm_i915_gem_execbuffer2
*args
,
870 struct list_head
*vmas
)
872 struct drm_device
*dev
= params
->dev
;
873 struct intel_engine_cs
*ring
= params
->ring
;
874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
875 struct intel_ringbuffer
*ringbuf
= params
->ctx
->engine
[ring
->id
].ringbuf
;
881 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
882 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
883 switch (instp_mode
) {
884 case I915_EXEC_CONSTANTS_REL_GENERAL
:
885 case I915_EXEC_CONSTANTS_ABSOLUTE
:
886 case I915_EXEC_CONSTANTS_REL_SURFACE
:
887 if (instp_mode
!= 0 && ring
!= &dev_priv
->ring
[RCS
]) {
888 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
892 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
893 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
894 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
898 /* The HW changed the meaning on this bit on gen6 */
899 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
903 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
907 if (args
->num_cliprects
!= 0) {
908 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
911 if (args
->DR4
== 0xffffffff) {
912 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
916 if (args
->DR1
|| args
->DR4
|| args
->cliprects_ptr
) {
917 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
922 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
923 DRM_DEBUG("sol reset is gen7 only\n");
927 ret
= execlists_move_to_gpu(params
->request
, vmas
);
931 if (ring
== &dev_priv
->ring
[RCS
] &&
932 instp_mode
!= dev_priv
->relative_constants_mode
) {
933 ret
= intel_logical_ring_begin(params
->request
, 4);
937 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
938 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
939 intel_logical_ring_emit(ringbuf
, INSTPM
);
940 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
941 intel_logical_ring_advance(ringbuf
);
943 dev_priv
->relative_constants_mode
= instp_mode
;
946 exec_start
= params
->batch_obj_vm_offset
+
947 args
->batch_start_offset
;
949 ret
= ring
->emit_bb_start(params
->request
, exec_start
, params
->dispatch_flags
);
953 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
955 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
956 i915_gem_execbuffer_retire_commands(params
);
961 void intel_execlists_retire_requests(struct intel_engine_cs
*ring
)
963 struct drm_i915_gem_request
*req
, *tmp
;
964 struct list_head retired_list
;
966 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
967 if (list_empty(&ring
->execlist_retired_req_list
))
970 INIT_LIST_HEAD(&retired_list
);
971 spin_lock_irq(&ring
->execlist_lock
);
972 list_replace_init(&ring
->execlist_retired_req_list
, &retired_list
);
973 spin_unlock_irq(&ring
->execlist_lock
);
975 list_for_each_entry_safe(req
, tmp
, &retired_list
, execlist_link
) {
976 struct intel_context
*ctx
= req
->ctx
;
977 struct drm_i915_gem_object
*ctx_obj
=
978 ctx
->engine
[ring
->id
].state
;
980 if (ctx_obj
&& (ctx
!= ring
->default_context
))
981 intel_lr_context_unpin(req
);
982 list_del(&req
->execlist_link
);
983 i915_gem_request_unreference(req
);
987 void intel_logical_ring_stop(struct intel_engine_cs
*ring
)
989 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
992 if (!intel_ring_initialized(ring
))
995 ret
= intel_ring_idle(ring
);
996 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
997 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1000 /* TODO: Is this correct with Execlists enabled? */
1001 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
1002 if (wait_for_atomic((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
1003 DRM_ERROR("%s :timed out trying to stop ring\n", ring
->name
);
1006 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
1009 int logical_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
1011 struct intel_engine_cs
*ring
= req
->ring
;
1014 if (!ring
->gpu_caches_dirty
)
1017 ret
= ring
->emit_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
1021 ring
->gpu_caches_dirty
= false;
1025 static int intel_lr_context_do_pin(struct intel_engine_cs
*ring
,
1026 struct drm_i915_gem_object
*ctx_obj
,
1027 struct intel_ringbuffer
*ringbuf
)
1029 struct drm_device
*dev
= ring
->dev
;
1030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1033 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1034 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
,
1035 PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
);
1039 ret
= intel_pin_and_map_ringbuffer_obj(ring
->dev
, ringbuf
);
1043 ctx_obj
->dirty
= true;
1045 /* Invalidate GuC TLB. */
1046 if (i915
.enable_guc_submission
)
1047 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
1052 i915_gem_object_ggtt_unpin(ctx_obj
);
1057 static int intel_lr_context_pin(struct drm_i915_gem_request
*rq
)
1060 struct intel_engine_cs
*ring
= rq
->ring
;
1061 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
1062 struct intel_ringbuffer
*ringbuf
= rq
->ringbuf
;
1064 if (rq
->ctx
->engine
[ring
->id
].pin_count
++ == 0) {
1065 ret
= intel_lr_context_do_pin(ring
, ctx_obj
, ringbuf
);
1067 goto reset_pin_count
;
1072 rq
->ctx
->engine
[ring
->id
].pin_count
= 0;
1076 void intel_lr_context_unpin(struct drm_i915_gem_request
*rq
)
1078 struct intel_engine_cs
*ring
= rq
->ring
;
1079 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
1080 struct intel_ringbuffer
*ringbuf
= rq
->ringbuf
;
1083 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1084 if (--rq
->ctx
->engine
[ring
->id
].pin_count
== 0) {
1085 intel_unpin_ringbuffer_obj(ringbuf
);
1086 i915_gem_object_ggtt_unpin(ctx_obj
);
1091 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
1094 struct intel_engine_cs
*ring
= req
->ring
;
1095 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1096 struct drm_device
*dev
= ring
->dev
;
1097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1098 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
1100 if (WARN_ON_ONCE(w
->count
== 0))
1103 ring
->gpu_caches_dirty
= true;
1104 ret
= logical_ring_flush_all_caches(req
);
1108 ret
= intel_logical_ring_begin(req
, w
->count
* 2 + 2);
1112 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(w
->count
));
1113 for (i
= 0; i
< w
->count
; i
++) {
1114 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].addr
);
1115 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].value
);
1117 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1119 intel_logical_ring_advance(ringbuf
);
1121 ring
->gpu_caches_dirty
= true;
1122 ret
= logical_ring_flush_all_caches(req
);
1129 #define wa_ctx_emit(batch, index, cmd) \
1131 int __index = (index)++; \
1132 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1135 batch[__index] = (cmd); \
1140 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1141 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1142 * but there is a slight complication as this is applied in WA batch where the
1143 * values are only initialized once so we cannot take register value at the
1144 * beginning and reuse it further; hence we save its value to memory, upload a
1145 * constant value with bit21 set and then we restore it back with the saved value.
1146 * To simplify the WA, a constant value is formed by using the default value
1147 * of this register. This shouldn't be a problem because we are only modifying
1148 * it for a short period and this batch in non-premptible. We can ofcourse
1149 * use additional instructions that read the actual value of the register
1150 * at that time and set our bit of interest but it makes the WA complicated.
1152 * This WA is also required for Gen9 so extracting as a function avoids
1155 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*ring
,
1156 uint32_t *const batch
,
1159 uint32_t l3sqc4_flush
= (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
);
1162 * WaDisableLSQCROPERFforOCL:skl
1163 * This WA is implemented in skl_init_clock_gating() but since
1164 * this batch updates GEN8_L3SQCREG4 with default value we need to
1165 * set this bit here to retain the WA during flush.
1167 if (IS_SKYLAKE(ring
->dev
) && INTEL_REVID(ring
->dev
) <= SKL_REVID_E0
)
1168 l3sqc4_flush
|= GEN8_LQSC_RO_PERF_DIS
;
1170 wa_ctx_emit(batch
, index
, (MI_STORE_REGISTER_MEM_GEN8
|
1171 MI_SRM_LRM_GLOBAL_GTT
));
1172 wa_ctx_emit(batch
, index
, GEN8_L3SQCREG4
);
1173 wa_ctx_emit(batch
, index
, ring
->scratch
.gtt_offset
+ 256);
1174 wa_ctx_emit(batch
, index
, 0);
1176 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1177 wa_ctx_emit(batch
, index
, GEN8_L3SQCREG4
);
1178 wa_ctx_emit(batch
, index
, l3sqc4_flush
);
1180 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1181 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_CS_STALL
|
1182 PIPE_CONTROL_DC_FLUSH_ENABLE
));
1183 wa_ctx_emit(batch
, index
, 0);
1184 wa_ctx_emit(batch
, index
, 0);
1185 wa_ctx_emit(batch
, index
, 0);
1186 wa_ctx_emit(batch
, index
, 0);
1188 wa_ctx_emit(batch
, index
, (MI_LOAD_REGISTER_MEM_GEN8
|
1189 MI_SRM_LRM_GLOBAL_GTT
));
1190 wa_ctx_emit(batch
, index
, GEN8_L3SQCREG4
);
1191 wa_ctx_emit(batch
, index
, ring
->scratch
.gtt_offset
+ 256);
1192 wa_ctx_emit(batch
, index
, 0);
1197 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb
*wa_ctx
,
1199 uint32_t start_alignment
)
1201 return wa_ctx
->offset
= ALIGN(offset
, start_alignment
);
1204 static inline int wa_ctx_end(struct i915_wa_ctx_bb
*wa_ctx
,
1206 uint32_t size_alignment
)
1208 wa_ctx
->size
= offset
- wa_ctx
->offset
;
1210 WARN(wa_ctx
->size
% size_alignment
,
1211 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1212 wa_ctx
->size
, size_alignment
);
1217 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1219 * @ring: only applicable for RCS
1220 * @wa_ctx: structure representing wa_ctx
1221 * offset: specifies start of the batch, should be cache-aligned. This is updated
1222 * with the offset value received as input.
1223 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1224 * @batch: page in which WA are loaded
1225 * @offset: This field specifies the start of the batch, it should be
1226 * cache-aligned otherwise it is adjusted accordingly.
1227 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1228 * initialized at the beginning and shared across all contexts but this field
1229 * helps us to have multiple batches at different offsets and select them based
1230 * on a criteria. At the moment this batch always start at the beginning of the page
1231 * and at this point we don't have multiple wa_ctx batch buffers.
1233 * The number of WA applied are not known at the beginning; we use this field
1234 * to return the no of DWORDS written.
1236 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1237 * so it adds NOOPs as padding to make it cacheline aligned.
1238 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1239 * makes a complete batch buffer.
1241 * Return: non-zero if we exceed the PAGE_SIZE limit.
1244 static int gen8_init_indirectctx_bb(struct intel_engine_cs
*ring
,
1245 struct i915_wa_ctx_bb
*wa_ctx
,
1246 uint32_t *const batch
,
1249 uint32_t scratch_addr
;
1250 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1252 /* WaDisableCtxRestoreArbitration:bdw,chv */
1253 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1255 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1256 if (IS_BROADWELL(ring
->dev
)) {
1257 index
= gen8_emit_flush_coherentl3_wa(ring
, batch
, index
);
1262 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1263 /* Actual scratch location is at 128 bytes offset */
1264 scratch_addr
= ring
->scratch
.gtt_offset
+ 2*CACHELINE_BYTES
;
1266 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1267 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1268 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1269 PIPE_CONTROL_CS_STALL
|
1270 PIPE_CONTROL_QW_WRITE
));
1271 wa_ctx_emit(batch
, index
, scratch_addr
);
1272 wa_ctx_emit(batch
, index
, 0);
1273 wa_ctx_emit(batch
, index
, 0);
1274 wa_ctx_emit(batch
, index
, 0);
1276 /* Pad to end of cacheline */
1277 while (index
% CACHELINE_DWORDS
)
1278 wa_ctx_emit(batch
, index
, MI_NOOP
);
1281 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1282 * execution depends on the length specified in terms of cache lines
1283 * in the register CTX_RCS_INDIRECT_CTX
1286 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1290 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1292 * @ring: only applicable for RCS
1293 * @wa_ctx: structure representing wa_ctx
1294 * offset: specifies start of the batch, should be cache-aligned.
1295 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1296 * @batch: page in which WA are loaded
1297 * @offset: This field specifies the start of this batch.
1298 * This batch is started immediately after indirect_ctx batch. Since we ensure
1299 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1301 * The number of DWORDS written are returned using this field.
1303 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1304 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1306 static int gen8_init_perctx_bb(struct intel_engine_cs
*ring
,
1307 struct i915_wa_ctx_bb
*wa_ctx
,
1308 uint32_t *const batch
,
1311 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1313 /* WaDisableCtxRestoreArbitration:bdw,chv */
1314 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1316 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1318 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1321 static int gen9_init_indirectctx_bb(struct intel_engine_cs
*ring
,
1322 struct i915_wa_ctx_bb
*wa_ctx
,
1323 uint32_t *const batch
,
1327 struct drm_device
*dev
= ring
->dev
;
1328 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1330 /* WaDisableCtxRestoreArbitration:skl,bxt */
1331 if ((IS_SKYLAKE(dev
) && (INTEL_REVID(dev
) <= SKL_REVID_D0
)) ||
1332 (IS_BROXTON(dev
) && (INTEL_REVID(dev
) == BXT_REVID_A0
)))
1333 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1335 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1336 ret
= gen8_emit_flush_coherentl3_wa(ring
, batch
, index
);
1341 /* Pad to end of cacheline */
1342 while (index
% CACHELINE_DWORDS
)
1343 wa_ctx_emit(batch
, index
, MI_NOOP
);
1345 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1348 static int gen9_init_perctx_bb(struct intel_engine_cs
*ring
,
1349 struct i915_wa_ctx_bb
*wa_ctx
,
1350 uint32_t *const batch
,
1353 struct drm_device
*dev
= ring
->dev
;
1354 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1356 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1357 if ((IS_SKYLAKE(dev
) && (INTEL_REVID(dev
) <= SKL_REVID_B0
)) ||
1358 (IS_BROXTON(dev
) && (INTEL_REVID(dev
) == BXT_REVID_A0
))) {
1359 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1360 wa_ctx_emit(batch
, index
, GEN9_SLICE_COMMON_ECO_CHICKEN0
);
1361 wa_ctx_emit(batch
, index
,
1362 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING
));
1363 wa_ctx_emit(batch
, index
, MI_NOOP
);
1366 /* WaDisableCtxRestoreArbitration:skl,bxt */
1367 if ((IS_SKYLAKE(dev
) && (INTEL_REVID(dev
) <= SKL_REVID_D0
)) ||
1368 (IS_BROXTON(dev
) && (INTEL_REVID(dev
) == BXT_REVID_A0
)))
1369 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1371 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1373 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1376 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs
*ring
, u32 size
)
1380 ring
->wa_ctx
.obj
= i915_gem_alloc_object(ring
->dev
, PAGE_ALIGN(size
));
1381 if (!ring
->wa_ctx
.obj
) {
1382 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1386 ret
= i915_gem_obj_ggtt_pin(ring
->wa_ctx
.obj
, PAGE_SIZE
, 0);
1388 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1390 drm_gem_object_unreference(&ring
->wa_ctx
.obj
->base
);
1397 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs
*ring
)
1399 if (ring
->wa_ctx
.obj
) {
1400 i915_gem_object_ggtt_unpin(ring
->wa_ctx
.obj
);
1401 drm_gem_object_unreference(&ring
->wa_ctx
.obj
->base
);
1402 ring
->wa_ctx
.obj
= NULL
;
1406 static int intel_init_workaround_bb(struct intel_engine_cs
*ring
)
1412 struct i915_ctx_workarounds
*wa_ctx
= &ring
->wa_ctx
;
1414 WARN_ON(ring
->id
!= RCS
);
1416 /* update this when WA for higher Gen are added */
1417 if (INTEL_INFO(ring
->dev
)->gen
> 9) {
1418 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1419 INTEL_INFO(ring
->dev
)->gen
);
1423 /* some WA perform writes to scratch page, ensure it is valid */
1424 if (ring
->scratch
.obj
== NULL
) {
1425 DRM_ERROR("scratch page not allocated for %s\n", ring
->name
);
1429 ret
= lrc_setup_wa_ctx_obj(ring
, PAGE_SIZE
);
1431 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1435 page
= i915_gem_object_get_page(wa_ctx
->obj
, 0);
1436 batch
= kmap_atomic(page
);
1439 if (INTEL_INFO(ring
->dev
)->gen
== 8) {
1440 ret
= gen8_init_indirectctx_bb(ring
,
1441 &wa_ctx
->indirect_ctx
,
1447 ret
= gen8_init_perctx_bb(ring
,
1453 } else if (INTEL_INFO(ring
->dev
)->gen
== 9) {
1454 ret
= gen9_init_indirectctx_bb(ring
,
1455 &wa_ctx
->indirect_ctx
,
1461 ret
= gen9_init_perctx_bb(ring
,
1470 kunmap_atomic(batch
);
1472 lrc_destroy_wa_ctx_obj(ring
);
1477 static int gen8_init_common_ring(struct intel_engine_cs
*ring
)
1479 struct drm_device
*dev
= ring
->dev
;
1480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1482 lrc_setup_hardware_status_page(ring
,
1483 ring
->default_context
->engine
[ring
->id
].state
);
1485 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1486 I915_WRITE(RING_HWSTAM(ring
->mmio_base
), 0xffffffff);
1488 if (ring
->status_page
.obj
) {
1489 I915_WRITE(RING_HWS_PGA(ring
->mmio_base
),
1490 (u32
)ring
->status_page
.gfx_addr
);
1491 POSTING_READ(RING_HWS_PGA(ring
->mmio_base
));
1494 I915_WRITE(RING_MODE_GEN7(ring
),
1495 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1496 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1497 POSTING_READ(RING_MODE_GEN7(ring
));
1498 ring
->next_context_status_buffer
= 0;
1499 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring
->name
);
1501 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
1506 static int gen8_init_render_ring(struct intel_engine_cs
*ring
)
1508 struct drm_device
*dev
= ring
->dev
;
1509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1512 ret
= gen8_init_common_ring(ring
);
1516 /* We need to disable the AsyncFlip performance optimisations in order
1517 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1518 * programmed to '1' on all products.
1520 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1522 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1524 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1526 return init_workarounds_ring(ring
);
1529 static int gen9_init_render_ring(struct intel_engine_cs
*ring
)
1533 ret
= gen8_init_common_ring(ring
);
1537 return init_workarounds_ring(ring
);
1540 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1542 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1543 struct intel_engine_cs
*ring
= req
->ring
;
1544 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1545 const int num_lri_cmds
= GEN8_LEGACY_PDPES
* 2;
1548 ret
= intel_logical_ring_begin(req
, num_lri_cmds
* 2 + 2);
1552 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(num_lri_cmds
));
1553 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
1554 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1556 intel_logical_ring_emit(ringbuf
, GEN8_RING_PDP_UDW(ring
, i
));
1557 intel_logical_ring_emit(ringbuf
, upper_32_bits(pd_daddr
));
1558 intel_logical_ring_emit(ringbuf
, GEN8_RING_PDP_LDW(ring
, i
));
1559 intel_logical_ring_emit(ringbuf
, lower_32_bits(pd_daddr
));
1562 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1563 intel_logical_ring_advance(ringbuf
);
1568 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1569 u64 offset
, unsigned dispatch_flags
)
1571 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1572 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1575 /* Don't rely in hw updating PDPs, specially in lite-restore.
1576 * Ideally, we should set Force PD Restore in ctx descriptor,
1577 * but we can't. Force Restore would be a second option, but
1578 * it is unsafe in case of lite-restore (because the ctx is
1579 * not idle). PML4 is allocated during ppgtt init so this is
1580 * not needed in 48-bit.*/
1581 if (req
->ctx
->ppgtt
&&
1582 (intel_ring_flag(req
->ring
) & req
->ctx
->ppgtt
->pd_dirty_rings
)) {
1583 if (!USES_FULL_48BIT_PPGTT(req
->i915
) &&
1584 !intel_vgpu_active(req
->i915
->dev
)) {
1585 ret
= intel_logical_ring_emit_pdps(req
);
1590 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_ring_flag(req
->ring
);
1593 ret
= intel_logical_ring_begin(req
, 4);
1597 /* FIXME(BDW): Address space and security selectors. */
1598 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
|
1600 (dispatch_flags
& I915_DISPATCH_RS
?
1601 MI_BATCH_RESOURCE_STREAMER
: 0));
1602 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1603 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1604 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1605 intel_logical_ring_advance(ringbuf
);
1610 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*ring
)
1612 struct drm_device
*dev
= ring
->dev
;
1613 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1614 unsigned long flags
;
1616 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1619 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1620 if (ring
->irq_refcount
++ == 0) {
1621 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1622 POSTING_READ(RING_IMR(ring
->mmio_base
));
1624 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1629 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*ring
)
1631 struct drm_device
*dev
= ring
->dev
;
1632 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1633 unsigned long flags
;
1635 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1636 if (--ring
->irq_refcount
== 0) {
1637 I915_WRITE_IMR(ring
, ~ring
->irq_keep_mask
);
1638 POSTING_READ(RING_IMR(ring
->mmio_base
));
1640 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1643 static int gen8_emit_flush(struct drm_i915_gem_request
*request
,
1644 u32 invalidate_domains
,
1647 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1648 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1649 struct drm_device
*dev
= ring
->dev
;
1650 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1654 ret
= intel_logical_ring_begin(request
, 4);
1658 cmd
= MI_FLUSH_DW
+ 1;
1660 /* We always require a command barrier so that subsequent
1661 * commands, such as breadcrumb interrupts, are strictly ordered
1662 * wrt the contents of the write cache being flushed to memory
1663 * (and thus being coherent from the CPU).
1665 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1667 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
) {
1668 cmd
|= MI_INVALIDATE_TLB
;
1669 if (ring
== &dev_priv
->ring
[VCS
])
1670 cmd
|= MI_INVALIDATE_BSD
;
1673 intel_logical_ring_emit(ringbuf
, cmd
);
1674 intel_logical_ring_emit(ringbuf
,
1675 I915_GEM_HWS_SCRATCH_ADDR
|
1676 MI_FLUSH_DW_USE_GTT
);
1677 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1678 intel_logical_ring_emit(ringbuf
, 0); /* value */
1679 intel_logical_ring_advance(ringbuf
);
1684 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1685 u32 invalidate_domains
,
1688 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1689 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1690 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1695 flags
|= PIPE_CONTROL_CS_STALL
;
1697 if (flush_domains
) {
1698 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1699 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1702 if (invalidate_domains
) {
1703 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1704 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1705 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1706 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1707 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1708 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1709 flags
|= PIPE_CONTROL_QW_WRITE
;
1710 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1714 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
1717 vf_flush_wa
= INTEL_INFO(ring
->dev
)->gen
>= 9 &&
1718 flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1720 ret
= intel_logical_ring_begin(request
, vf_flush_wa
? 12 : 6);
1725 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1726 intel_logical_ring_emit(ringbuf
, 0);
1727 intel_logical_ring_emit(ringbuf
, 0);
1728 intel_logical_ring_emit(ringbuf
, 0);
1729 intel_logical_ring_emit(ringbuf
, 0);
1730 intel_logical_ring_emit(ringbuf
, 0);
1733 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1734 intel_logical_ring_emit(ringbuf
, flags
);
1735 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1736 intel_logical_ring_emit(ringbuf
, 0);
1737 intel_logical_ring_emit(ringbuf
, 0);
1738 intel_logical_ring_emit(ringbuf
, 0);
1739 intel_logical_ring_advance(ringbuf
);
1744 static u32
gen8_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1746 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1749 static void gen8_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1751 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1754 static u32
bxt_a_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1758 * On BXT A steppings there is a HW coherency issue whereby the
1759 * MI_STORE_DATA_IMM storing the completed request's seqno
1760 * occasionally doesn't invalidate the CPU cache. Work around this by
1761 * clflushing the corresponding cacheline whenever the caller wants
1762 * the coherency to be guaranteed. Note that this cacheline is known
1763 * to be clean at this point, since we only write it in
1764 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1765 * this clflush in practice becomes an invalidate operation.
1768 if (!lazy_coherency
)
1769 intel_flush_status_page(ring
, I915_GEM_HWS_INDEX
);
1771 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1774 static void bxt_a_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1776 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1778 /* See bxt_a_get_seqno() explaining the reason for the clflush. */
1779 intel_flush_status_page(ring
, I915_GEM_HWS_INDEX
);
1782 static int gen8_emit_request(struct drm_i915_gem_request
*request
)
1784 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1785 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1790 * Reserve space for 2 NOOPs at the end of each request to be
1791 * used as a workaround for not being allowed to do lite
1792 * restore with HEAD==TAIL (WaIdleLiteRestore).
1794 ret
= intel_logical_ring_begin(request
, 8);
1798 cmd
= MI_STORE_DWORD_IMM_GEN4
;
1799 cmd
|= MI_GLOBAL_GTT
;
1801 intel_logical_ring_emit(ringbuf
, cmd
);
1802 intel_logical_ring_emit(ringbuf
,
1803 (ring
->status_page
.gfx_addr
+
1804 (I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
)));
1805 intel_logical_ring_emit(ringbuf
, 0);
1806 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1807 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1808 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1809 intel_logical_ring_advance_and_submit(request
);
1812 * Here we add two extra NOOPs as padding to avoid
1813 * lite restore of a context with HEAD==TAIL.
1815 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1816 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1817 intel_logical_ring_advance(ringbuf
);
1822 static int intel_lr_context_render_state_init(struct drm_i915_gem_request
*req
)
1824 struct render_state so
;
1827 ret
= i915_gem_render_state_prepare(req
->ring
, &so
);
1831 if (so
.rodata
== NULL
)
1834 ret
= req
->ring
->emit_bb_start(req
, so
.ggtt_offset
,
1835 I915_DISPATCH_SECURE
);
1839 ret
= req
->ring
->emit_bb_start(req
,
1840 (so
.ggtt_offset
+ so
.aux_batch_offset
),
1841 I915_DISPATCH_SECURE
);
1845 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), req
);
1848 i915_gem_render_state_fini(&so
);
1852 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
1856 ret
= intel_logical_ring_workarounds_emit(req
);
1860 ret
= intel_rcs_context_init_mocs(req
);
1862 * Failing to program the MOCS is non-fatal.The system will not
1863 * run at peak performance. So generate an error and carry on.
1866 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1868 return intel_lr_context_render_state_init(req
);
1872 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1874 * @ring: Engine Command Streamer.
1877 void intel_logical_ring_cleanup(struct intel_engine_cs
*ring
)
1879 struct drm_i915_private
*dev_priv
;
1881 if (!intel_ring_initialized(ring
))
1884 dev_priv
= ring
->dev
->dev_private
;
1886 intel_logical_ring_stop(ring
);
1887 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1890 ring
->cleanup(ring
);
1892 i915_cmd_parser_fini_ring(ring
);
1893 i915_gem_batch_pool_fini(&ring
->batch_pool
);
1895 if (ring
->status_page
.obj
) {
1896 kunmap(sg_page(ring
->status_page
.obj
->pages
->sgl
));
1897 ring
->status_page
.obj
= NULL
;
1900 lrc_destroy_wa_ctx_obj(ring
);
1903 static int logical_ring_init(struct drm_device
*dev
, struct intel_engine_cs
*ring
)
1907 /* Intentionally left blank. */
1908 ring
->buffer
= NULL
;
1911 INIT_LIST_HEAD(&ring
->active_list
);
1912 INIT_LIST_HEAD(&ring
->request_list
);
1913 i915_gem_batch_pool_init(dev
, &ring
->batch_pool
);
1914 init_waitqueue_head(&ring
->irq_queue
);
1916 INIT_LIST_HEAD(&ring
->execlist_queue
);
1917 INIT_LIST_HEAD(&ring
->execlist_retired_req_list
);
1918 spin_lock_init(&ring
->execlist_lock
);
1920 ret
= i915_cmd_parser_init_ring(ring
);
1924 ret
= intel_lr_context_deferred_alloc(ring
->default_context
, ring
);
1928 /* As this is the default context, always pin it */
1929 ret
= intel_lr_context_do_pin(
1931 ring
->default_context
->engine
[ring
->id
].state
,
1932 ring
->default_context
->engine
[ring
->id
].ringbuf
);
1935 "Failed to pin and map ringbuffer %s: %d\n",
1943 static int logical_render_ring_init(struct drm_device
*dev
)
1945 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1946 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
1949 ring
->name
= "render ring";
1951 ring
->mmio_base
= RENDER_RING_BASE
;
1952 ring
->irq_enable_mask
=
1953 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1954 ring
->irq_keep_mask
=
1955 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1956 if (HAS_L3_DPF(dev
))
1957 ring
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
1959 if (INTEL_INFO(dev
)->gen
>= 9)
1960 ring
->init_hw
= gen9_init_render_ring
;
1962 ring
->init_hw
= gen8_init_render_ring
;
1963 ring
->init_context
= gen8_init_rcs_context
;
1964 ring
->cleanup
= intel_fini_pipe_control
;
1965 if (IS_BROXTON(dev
) && INTEL_REVID(dev
) < BXT_REVID_B0
) {
1966 ring
->get_seqno
= bxt_a_get_seqno
;
1967 ring
->set_seqno
= bxt_a_set_seqno
;
1969 ring
->get_seqno
= gen8_get_seqno
;
1970 ring
->set_seqno
= gen8_set_seqno
;
1972 ring
->emit_request
= gen8_emit_request
;
1973 ring
->emit_flush
= gen8_emit_flush_render
;
1974 ring
->irq_get
= gen8_logical_ring_get_irq
;
1975 ring
->irq_put
= gen8_logical_ring_put_irq
;
1976 ring
->emit_bb_start
= gen8_emit_bb_start
;
1980 ret
= intel_init_pipe_control(ring
);
1984 ret
= intel_init_workaround_bb(ring
);
1987 * We continue even if we fail to initialize WA batch
1988 * because we only expect rare glitches but nothing
1989 * critical to prevent us from using GPU
1991 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1995 ret
= logical_ring_init(dev
, ring
);
1997 lrc_destroy_wa_ctx_obj(ring
);
2003 static int logical_bsd_ring_init(struct drm_device
*dev
)
2005 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2006 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
2008 ring
->name
= "bsd ring";
2010 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
2011 ring
->irq_enable_mask
=
2012 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
2013 ring
->irq_keep_mask
=
2014 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
2016 ring
->init_hw
= gen8_init_common_ring
;
2017 if (IS_BROXTON(dev
) && INTEL_REVID(dev
) < BXT_REVID_B0
) {
2018 ring
->get_seqno
= bxt_a_get_seqno
;
2019 ring
->set_seqno
= bxt_a_set_seqno
;
2021 ring
->get_seqno
= gen8_get_seqno
;
2022 ring
->set_seqno
= gen8_set_seqno
;
2024 ring
->emit_request
= gen8_emit_request
;
2025 ring
->emit_flush
= gen8_emit_flush
;
2026 ring
->irq_get
= gen8_logical_ring_get_irq
;
2027 ring
->irq_put
= gen8_logical_ring_put_irq
;
2028 ring
->emit_bb_start
= gen8_emit_bb_start
;
2030 return logical_ring_init(dev
, ring
);
2033 static int logical_bsd2_ring_init(struct drm_device
*dev
)
2035 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2036 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
2038 ring
->name
= "bds2 ring";
2040 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
2041 ring
->irq_enable_mask
=
2042 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
2043 ring
->irq_keep_mask
=
2044 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
2046 ring
->init_hw
= gen8_init_common_ring
;
2047 ring
->get_seqno
= gen8_get_seqno
;
2048 ring
->set_seqno
= gen8_set_seqno
;
2049 ring
->emit_request
= gen8_emit_request
;
2050 ring
->emit_flush
= gen8_emit_flush
;
2051 ring
->irq_get
= gen8_logical_ring_get_irq
;
2052 ring
->irq_put
= gen8_logical_ring_put_irq
;
2053 ring
->emit_bb_start
= gen8_emit_bb_start
;
2055 return logical_ring_init(dev
, ring
);
2058 static int logical_blt_ring_init(struct drm_device
*dev
)
2060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2061 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
2063 ring
->name
= "blitter ring";
2065 ring
->mmio_base
= BLT_RING_BASE
;
2066 ring
->irq_enable_mask
=
2067 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2068 ring
->irq_keep_mask
=
2069 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2071 ring
->init_hw
= gen8_init_common_ring
;
2072 if (IS_BROXTON(dev
) && INTEL_REVID(dev
) < BXT_REVID_B0
) {
2073 ring
->get_seqno
= bxt_a_get_seqno
;
2074 ring
->set_seqno
= bxt_a_set_seqno
;
2076 ring
->get_seqno
= gen8_get_seqno
;
2077 ring
->set_seqno
= gen8_set_seqno
;
2079 ring
->emit_request
= gen8_emit_request
;
2080 ring
->emit_flush
= gen8_emit_flush
;
2081 ring
->irq_get
= gen8_logical_ring_get_irq
;
2082 ring
->irq_put
= gen8_logical_ring_put_irq
;
2083 ring
->emit_bb_start
= gen8_emit_bb_start
;
2085 return logical_ring_init(dev
, ring
);
2088 static int logical_vebox_ring_init(struct drm_device
*dev
)
2090 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2091 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
2093 ring
->name
= "video enhancement ring";
2095 ring
->mmio_base
= VEBOX_RING_BASE
;
2096 ring
->irq_enable_mask
=
2097 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
2098 ring
->irq_keep_mask
=
2099 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
2101 ring
->init_hw
= gen8_init_common_ring
;
2102 if (IS_BROXTON(dev
) && INTEL_REVID(dev
) < BXT_REVID_B0
) {
2103 ring
->get_seqno
= bxt_a_get_seqno
;
2104 ring
->set_seqno
= bxt_a_set_seqno
;
2106 ring
->get_seqno
= gen8_get_seqno
;
2107 ring
->set_seqno
= gen8_set_seqno
;
2109 ring
->emit_request
= gen8_emit_request
;
2110 ring
->emit_flush
= gen8_emit_flush
;
2111 ring
->irq_get
= gen8_logical_ring_get_irq
;
2112 ring
->irq_put
= gen8_logical_ring_put_irq
;
2113 ring
->emit_bb_start
= gen8_emit_bb_start
;
2115 return logical_ring_init(dev
, ring
);
2119 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2122 * This function inits the engines for an Execlists submission style (the equivalent in the
2123 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
2124 * those engines that are present in the hardware.
2126 * Return: non-zero if the initialization failed.
2128 int intel_logical_rings_init(struct drm_device
*dev
)
2130 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2133 ret
= logical_render_ring_init(dev
);
2138 ret
= logical_bsd_ring_init(dev
);
2140 goto cleanup_render_ring
;
2144 ret
= logical_blt_ring_init(dev
);
2146 goto cleanup_bsd_ring
;
2149 if (HAS_VEBOX(dev
)) {
2150 ret
= logical_vebox_ring_init(dev
);
2152 goto cleanup_blt_ring
;
2155 if (HAS_BSD2(dev
)) {
2156 ret
= logical_bsd2_ring_init(dev
);
2158 goto cleanup_vebox_ring
;
2164 intel_logical_ring_cleanup(&dev_priv
->ring
[VECS
]);
2166 intel_logical_ring_cleanup(&dev_priv
->ring
[BCS
]);
2168 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS
]);
2169 cleanup_render_ring
:
2170 intel_logical_ring_cleanup(&dev_priv
->ring
[RCS
]);
2176 make_rpcs(struct drm_device
*dev
)
2181 * No explicit RPCS request is needed to ensure full
2182 * slice/subslice/EU enablement prior to Gen9.
2184 if (INTEL_INFO(dev
)->gen
< 9)
2188 * Starting in Gen9, render power gating can leave
2189 * slice/subslice/EU in a partially enabled state. We
2190 * must make an explicit request through RPCS for full
2193 if (INTEL_INFO(dev
)->has_slice_pg
) {
2194 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
2195 rpcs
|= INTEL_INFO(dev
)->slice_total
<<
2196 GEN8_RPCS_S_CNT_SHIFT
;
2197 rpcs
|= GEN8_RPCS_ENABLE
;
2200 if (INTEL_INFO(dev
)->has_subslice_pg
) {
2201 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
2202 rpcs
|= INTEL_INFO(dev
)->subslice_per_slice
<<
2203 GEN8_RPCS_SS_CNT_SHIFT
;
2204 rpcs
|= GEN8_RPCS_ENABLE
;
2207 if (INTEL_INFO(dev
)->has_eu_pg
) {
2208 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2209 GEN8_RPCS_EU_MIN_SHIFT
;
2210 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2211 GEN8_RPCS_EU_MAX_SHIFT
;
2212 rpcs
|= GEN8_RPCS_ENABLE
;
2219 populate_lr_context(struct intel_context
*ctx
, struct drm_i915_gem_object
*ctx_obj
,
2220 struct intel_engine_cs
*ring
, struct intel_ringbuffer
*ringbuf
)
2222 struct drm_device
*dev
= ring
->dev
;
2223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2224 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2226 uint32_t *reg_state
;
2230 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2232 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
2234 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2238 ret
= i915_gem_object_get_pages(ctx_obj
);
2240 DRM_DEBUG_DRIVER("Could not get object pages\n");
2244 i915_gem_object_pin_pages(ctx_obj
);
2246 /* The second page of the context object contains some fields which must
2247 * be set up prior to the first execution. */
2248 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
2249 reg_state
= kmap_atomic(page
);
2251 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2252 * commands followed by (reg, value) pairs. The values we are setting here are
2253 * only for the first context restore: on a subsequent save, the GPU will
2254 * recreate this batchbuffer with new values (including all the missing
2255 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2256 if (ring
->id
== RCS
)
2257 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(14);
2259 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(11);
2260 reg_state
[CTX_LRI_HEADER_0
] |= MI_LRI_FORCE_POSTED
;
2261 reg_state
[CTX_CONTEXT_CONTROL
] = RING_CONTEXT_CONTROL(ring
);
2262 reg_state
[CTX_CONTEXT_CONTROL
+1] =
2263 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
2264 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
2265 CTX_CTRL_RS_CTX_ENABLE
);
2266 reg_state
[CTX_RING_HEAD
] = RING_HEAD(ring
->mmio_base
);
2267 reg_state
[CTX_RING_HEAD
+1] = 0;
2268 reg_state
[CTX_RING_TAIL
] = RING_TAIL(ring
->mmio_base
);
2269 reg_state
[CTX_RING_TAIL
+1] = 0;
2270 reg_state
[CTX_RING_BUFFER_START
] = RING_START(ring
->mmio_base
);
2271 /* Ring buffer start address is not known until the buffer is pinned.
2272 * It is written to the context image in execlists_update_context()
2274 reg_state
[CTX_RING_BUFFER_CONTROL
] = RING_CTL(ring
->mmio_base
);
2275 reg_state
[CTX_RING_BUFFER_CONTROL
+1] =
2276 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
;
2277 reg_state
[CTX_BB_HEAD_U
] = ring
->mmio_base
+ 0x168;
2278 reg_state
[CTX_BB_HEAD_U
+1] = 0;
2279 reg_state
[CTX_BB_HEAD_L
] = ring
->mmio_base
+ 0x140;
2280 reg_state
[CTX_BB_HEAD_L
+1] = 0;
2281 reg_state
[CTX_BB_STATE
] = ring
->mmio_base
+ 0x110;
2282 reg_state
[CTX_BB_STATE
+1] = (1<<5);
2283 reg_state
[CTX_SECOND_BB_HEAD_U
] = ring
->mmio_base
+ 0x11c;
2284 reg_state
[CTX_SECOND_BB_HEAD_U
+1] = 0;
2285 reg_state
[CTX_SECOND_BB_HEAD_L
] = ring
->mmio_base
+ 0x114;
2286 reg_state
[CTX_SECOND_BB_HEAD_L
+1] = 0;
2287 reg_state
[CTX_SECOND_BB_STATE
] = ring
->mmio_base
+ 0x118;
2288 reg_state
[CTX_SECOND_BB_STATE
+1] = 0;
2289 if (ring
->id
== RCS
) {
2290 reg_state
[CTX_BB_PER_CTX_PTR
] = ring
->mmio_base
+ 0x1c0;
2291 reg_state
[CTX_BB_PER_CTX_PTR
+1] = 0;
2292 reg_state
[CTX_RCS_INDIRECT_CTX
] = ring
->mmio_base
+ 0x1c4;
2293 reg_state
[CTX_RCS_INDIRECT_CTX
+1] = 0;
2294 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
] = ring
->mmio_base
+ 0x1c8;
2295 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] = 0;
2296 if (ring
->wa_ctx
.obj
) {
2297 struct i915_ctx_workarounds
*wa_ctx
= &ring
->wa_ctx
;
2298 uint32_t ggtt_offset
= i915_gem_obj_ggtt_offset(wa_ctx
->obj
);
2300 reg_state
[CTX_RCS_INDIRECT_CTX
+1] =
2301 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
* sizeof(uint32_t)) |
2302 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_DWORDS
);
2304 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] =
2305 CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
<< 6;
2307 reg_state
[CTX_BB_PER_CTX_PTR
+1] =
2308 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
* sizeof(uint32_t)) |
2312 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9);
2313 reg_state
[CTX_LRI_HEADER_1
] |= MI_LRI_FORCE_POSTED
;
2314 reg_state
[CTX_CTX_TIMESTAMP
] = ring
->mmio_base
+ 0x3a8;
2315 reg_state
[CTX_CTX_TIMESTAMP
+1] = 0;
2316 reg_state
[CTX_PDP3_UDW
] = GEN8_RING_PDP_UDW(ring
, 3);
2317 reg_state
[CTX_PDP3_LDW
] = GEN8_RING_PDP_LDW(ring
, 3);
2318 reg_state
[CTX_PDP2_UDW
] = GEN8_RING_PDP_UDW(ring
, 2);
2319 reg_state
[CTX_PDP2_LDW
] = GEN8_RING_PDP_LDW(ring
, 2);
2320 reg_state
[CTX_PDP1_UDW
] = GEN8_RING_PDP_UDW(ring
, 1);
2321 reg_state
[CTX_PDP1_LDW
] = GEN8_RING_PDP_LDW(ring
, 1);
2322 reg_state
[CTX_PDP0_UDW
] = GEN8_RING_PDP_UDW(ring
, 0);
2323 reg_state
[CTX_PDP0_LDW
] = GEN8_RING_PDP_LDW(ring
, 0);
2325 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
2326 /* 64b PPGTT (48bit canonical)
2327 * PDP0_DESCRIPTOR contains the base address to PML4 and
2328 * other PDP Descriptors are ignored.
2330 ASSIGN_CTX_PML4(ppgtt
, reg_state
);
2333 * PDP*_DESCRIPTOR contains the base address of space supported.
2334 * With dynamic page allocation, PDPs may not be allocated at
2335 * this point. Point the unallocated PDPs to the scratch page
2337 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
2338 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
2339 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
2340 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
2343 if (ring
->id
== RCS
) {
2344 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
2345 reg_state
[CTX_R_PWR_CLK_STATE
] = GEN8_R_PWR_CLK_STATE
;
2346 reg_state
[CTX_R_PWR_CLK_STATE
+1] = make_rpcs(dev
);
2349 kunmap_atomic(reg_state
);
2352 set_page_dirty(page
);
2353 i915_gem_object_unpin_pages(ctx_obj
);
2359 * intel_lr_context_free() - free the LRC specific bits of a context
2360 * @ctx: the LR context to free.
2362 * The real context freeing is done in i915_gem_context_free: this only
2363 * takes care of the bits that are LRC related: the per-engine backing
2364 * objects and the logical ringbuffer.
2366 void intel_lr_context_free(struct intel_context
*ctx
)
2370 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2371 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
2374 struct intel_ringbuffer
*ringbuf
=
2375 ctx
->engine
[i
].ringbuf
;
2376 struct intel_engine_cs
*ring
= ringbuf
->ring
;
2378 if (ctx
== ring
->default_context
) {
2379 intel_unpin_ringbuffer_obj(ringbuf
);
2380 i915_gem_object_ggtt_unpin(ctx_obj
);
2382 WARN_ON(ctx
->engine
[ring
->id
].pin_count
);
2383 intel_ringbuffer_free(ringbuf
);
2384 drm_gem_object_unreference(&ctx_obj
->base
);
2389 static uint32_t get_lr_context_size(struct intel_engine_cs
*ring
)
2393 WARN_ON(INTEL_INFO(ring
->dev
)->gen
< 8);
2397 if (INTEL_INFO(ring
->dev
)->gen
>= 9)
2398 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
2400 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
2406 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
2413 static void lrc_setup_hardware_status_page(struct intel_engine_cs
*ring
,
2414 struct drm_i915_gem_object
*default_ctx_obj
)
2416 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2419 /* The HWSP is part of the default context object in LRC mode. */
2420 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(default_ctx_obj
)
2421 + LRC_PPHWSP_PN
* PAGE_SIZE
;
2422 page
= i915_gem_object_get_page(default_ctx_obj
, LRC_PPHWSP_PN
);
2423 ring
->status_page
.page_addr
= kmap(page
);
2424 ring
->status_page
.obj
= default_ctx_obj
;
2426 I915_WRITE(RING_HWS_PGA(ring
->mmio_base
),
2427 (u32
)ring
->status_page
.gfx_addr
);
2428 POSTING_READ(RING_HWS_PGA(ring
->mmio_base
));
2432 * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context
2433 * @ctx: LR context to create.
2434 * @ring: engine to be used with the context.
2436 * This function can be called more than once, with different engines, if we plan
2437 * to use the context with them. The context backing objects and the ringbuffers
2438 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2439 * the creation is a deferred call: it's better to make sure first that we need to use
2440 * a given ring with the context.
2442 * Return: non-zero on error.
2445 int intel_lr_context_deferred_alloc(struct intel_context
*ctx
,
2446 struct intel_engine_cs
*ring
)
2448 struct drm_device
*dev
= ring
->dev
;
2449 struct drm_i915_gem_object
*ctx_obj
;
2450 uint32_t context_size
;
2451 struct intel_ringbuffer
*ringbuf
;
2454 WARN_ON(ctx
->legacy_hw_ctx
.rcs_state
!= NULL
);
2455 WARN_ON(ctx
->engine
[ring
->id
].state
);
2457 context_size
= round_up(get_lr_context_size(ring
), 4096);
2459 /* One extra page as the sharing data between driver and GuC */
2460 context_size
+= PAGE_SIZE
* LRC_PPHWSP_PN
;
2462 ctx_obj
= i915_gem_alloc_object(dev
, context_size
);
2464 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2468 ringbuf
= intel_engine_create_ringbuffer(ring
, 4 * PAGE_SIZE
);
2469 if (IS_ERR(ringbuf
)) {
2470 ret
= PTR_ERR(ringbuf
);
2471 goto error_deref_obj
;
2474 ret
= populate_lr_context(ctx
, ctx_obj
, ring
, ringbuf
);
2476 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2480 ctx
->engine
[ring
->id
].ringbuf
= ringbuf
;
2481 ctx
->engine
[ring
->id
].state
= ctx_obj
;
2483 if (ctx
!= ring
->default_context
&& ring
->init_context
) {
2484 struct drm_i915_gem_request
*req
;
2486 ret
= i915_gem_request_alloc(ring
,
2489 DRM_ERROR("ring create req: %d\n",
2491 i915_gem_request_cancel(req
);
2495 ret
= ring
->init_context(req
);
2497 DRM_ERROR("ring init context: %d\n",
2499 i915_gem_request_cancel(req
);
2502 i915_add_request_no_flush(req
);
2507 intel_ringbuffer_free(ringbuf
);
2509 drm_gem_object_unreference(&ctx_obj
->base
);
2510 ctx
->engine
[ring
->id
].ringbuf
= NULL
;
2511 ctx
->engine
[ring
->id
].state
= NULL
;
2515 void intel_lr_context_reset(struct drm_device
*dev
,
2516 struct intel_context
*ctx
)
2518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2519 struct intel_engine_cs
*ring
;
2522 for_each_ring(ring
, dev_priv
, i
) {
2523 struct drm_i915_gem_object
*ctx_obj
=
2524 ctx
->engine
[ring
->id
].state
;
2525 struct intel_ringbuffer
*ringbuf
=
2526 ctx
->engine
[ring
->id
].ringbuf
;
2527 uint32_t *reg_state
;
2533 if (i915_gem_object_get_pages(ctx_obj
)) {
2534 WARN(1, "Failed get_pages for context obj\n");
2537 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
2538 reg_state
= kmap_atomic(page
);
2540 reg_state
[CTX_RING_HEAD
+1] = 0;
2541 reg_state
[CTX_RING_TAIL
+1] = 0;
2543 kunmap_atomic(reg_state
);