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git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - drivers/gpu/drm/i915/intel_lrc.h
2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
27 #include "intel_ringbuffer.h"
29 #define GEN8_LR_CONTEXT_ALIGN 4096
32 #define RING_ELSP(ring) _MMIO((ring)->mmio_base + 0x230)
33 #define RING_EXECLIST_STATUS_LO(ring) _MMIO((ring)->mmio_base + 0x234)
34 #define RING_EXECLIST_STATUS_HI(ring) _MMIO((ring)->mmio_base + 0x234 + 4)
35 #define RING_CONTEXT_CONTROL(ring) _MMIO((ring)->mmio_base + 0x244)
36 #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
37 #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
38 #define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
39 #define RING_CONTEXT_STATUS_BUF_BASE(ring) _MMIO((ring)->mmio_base + 0x370)
40 #define RING_CONTEXT_STATUS_BUF_LO(ring, i) _MMIO((ring)->mmio_base + 0x370 + (i) * 8)
41 #define RING_CONTEXT_STATUS_BUF_HI(ring, i) _MMIO((ring)->mmio_base + 0x370 + (i) * 8 + 4)
42 #define RING_CONTEXT_STATUS_PTR(ring) _MMIO((ring)->mmio_base + 0x3a0)
44 /* The docs specify that the write pointer wraps around after 5h, "After status
45 * is written out to the last available status QW at offset 5h, this pointer
48 * Therefore, one must infer than even though there are 3 bits available, 6 and
49 * 7 appear to be * reserved.
51 #define GEN8_CSB_ENTRIES 6
52 #define GEN8_CSB_PTR_MASK 0x7
53 #define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
54 #define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
55 #define GEN8_CSB_WRITE_PTR(csb_status) \
56 (((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0)
57 #define GEN8_CSB_READ_PTR(csb_status) \
58 (((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
61 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
);
62 int intel_logical_ring_reserve_space(struct drm_i915_gem_request
*request
);
63 void intel_logical_ring_stop(struct intel_engine_cs
*engine
);
64 void intel_logical_ring_cleanup(struct intel_engine_cs
*engine
);
65 int intel_logical_rings_init(struct drm_device
*dev
);
67 int logical_ring_flush_all_caches(struct drm_i915_gem_request
*req
);
69 * intel_logical_ring_advance() - advance the ringbuffer tail
70 * @ringbuf: Ringbuffer to advance.
72 * The tail is only updated in our logical ringbuffer struct.
74 static inline void intel_logical_ring_advance(struct intel_ringbuffer
*ringbuf
)
76 ringbuf
->tail
&= ringbuf
->size
- 1;
79 * intel_logical_ring_emit() - write a DWORD to the ringbuffer.
80 * @ringbuf: Ringbuffer to write to.
81 * @data: DWORD to write.
83 static inline void intel_logical_ring_emit(struct intel_ringbuffer
*ringbuf
,
86 iowrite32(data
, ringbuf
->virtual_start
+ ringbuf
->tail
);
89 static inline void intel_logical_ring_emit_reg(struct intel_ringbuffer
*ringbuf
,
92 intel_logical_ring_emit(ringbuf
, i915_mmio_reg_offset(reg
));
95 /* Logical Ring Contexts */
97 /* One extra page is added before LRC for GuC as shared data */
98 #define LRC_GUCSHR_PN (0)
99 #define LRC_PPHWSP_PN (LRC_GUCSHR_PN + 1)
100 #define LRC_STATE_PN (LRC_PPHWSP_PN + 1)
102 void intel_lr_context_free(struct intel_context
*ctx
);
103 uint32_t intel_lr_context_size(struct intel_engine_cs
*engine
);
104 int intel_lr_context_deferred_alloc(struct intel_context
*ctx
,
105 struct intel_engine_cs
*engine
);
106 void intel_lr_context_unpin(struct intel_context
*ctx
,
107 struct intel_engine_cs
*engine
);
109 struct drm_i915_private
;
111 void intel_lr_context_reset(struct drm_i915_private
*dev_priv
,
112 struct intel_context
*ctx
);
113 uint64_t intel_lr_context_descriptor(struct intel_context
*ctx
,
114 struct intel_engine_cs
*engine
);
116 u32
intel_execlists_ctx_id(struct intel_context
*ctx
,
117 struct intel_engine_cs
*engine
);
120 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
);
121 struct i915_execbuffer_params
;
122 int intel_execlists_submission(struct i915_execbuffer_params
*params
,
123 struct drm_i915_gem_execbuffer2
*args
,
124 struct list_head
*vmas
);
126 void intel_execlists_retire_requests(struct intel_engine_cs
*engine
);
128 #endif /* _INTEL_LRC_H_ */