drivers/gpu/drm/i915/intel_lvds.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Dave Airlie <airlied@linux.ie>
  27  *      Jesse Barnes <jesse.barnes@intel.com>
  28  */
  29
  30 #include <acpi/button.h>
  31 #include <linux/dmi.h>
  32 #include <linux/i2c.h>
  33 #include <linux/slab.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_edid.h>
  39 #include "intel_drv.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42 #include <linux/acpi.h>
  43
  44 /* Private structure for the integrated LVDS support */
  45 struct intel_lvds_connector {
  46         struct intel_connector base;
  47
  48         struct notifier_block lid_notifier;
  49 };
  50
  51 struct intel_lvds_pps {
  52         /* 100us units */
  53         int t1_t2;
  54         int t3;
  55         int t4;
  56         int t5;
  57         int tx;
  58
  59         int divider;
  60
  61         int port;
  62         bool powerdown_on_reset;
  63 };
  64
  65 struct intel_lvds_encoder {
  66         struct intel_encoder base;
  67
  68         bool is_dual_link;
  69         i915_reg_t reg;
  70         u32 a3_power;
  71
  72         struct intel_lvds_pps init_pps;
  73         u32 init_lvds_val;
  74
  75         struct intel_lvds_connector *attached_connector;
  76 };
  77
  78 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
  79 {
  80         return container_of(encoder, struct intel_lvds_encoder, base.base);
  81 }
  82
  83 static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
  84 {
  85         return container_of(connector, struct intel_lvds_connector, base.base);
  86 }
  87
  88 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
  89                                     enum pipe *pipe)
  90 {
  91         struct drm_device *dev = encoder->base.dev;
  92         struct drm_i915_private *dev_priv = to_i915(dev);
  93         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
  94         u32 tmp;
  95         bool ret;
  96
  97         if (!intel_display_power_get_if_enabled(dev_priv,
  98                                                 encoder->power_domain))
  99                 return false;
 100
 101         ret = false;
 102
 103         tmp = I915_READ(lvds_encoder->reg);
 104
 105         if (!(tmp & LVDS_PORT_EN))
 106                 goto out;
 107
 108         if (HAS_PCH_CPT(dev_priv))
 109                 *pipe = PORT_TO_PIPE_CPT(tmp);
 110         else
 111                 *pipe = PORT_TO_PIPE(tmp);
 112
 113         ret = true;
 114
 115 out:
 116         intel_display_power_put(dev_priv, encoder->power_domain);
 117
 118         return ret;
 119 }
 120
 121 static void intel_lvds_get_config(struct intel_encoder *encoder,
 122                                   struct intel_crtc_state *pipe_config)
 123 {
 124         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 125         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 126         u32 tmp, flags = 0;
 127
 128         tmp = I915_READ(lvds_encoder->reg);
 129         if (tmp & LVDS_HSYNC_POLARITY)
 130                 flags |= DRM_MODE_FLAG_NHSYNC;
 131         else
 132                 flags |= DRM_MODE_FLAG_PHSYNC;
 133         if (tmp & LVDS_VSYNC_POLARITY)
 134                 flags |= DRM_MODE_FLAG_NVSYNC;
 135         else
 136                 flags |= DRM_MODE_FLAG_PVSYNC;
 137
 138         pipe_config->base.adjusted_mode.flags |= flags;
 139
 140         if (INTEL_GEN(dev_priv) < 5)
 141                 pipe_config->gmch_pfit.lvds_border_bits =
 142                         tmp & LVDS_BORDER_ENABLE;
 143
 144         /* gen2/3 store dither state in pfit control, needs to match */
 145         if (INTEL_GEN(dev_priv) < 4) {
 146                 tmp = I915_READ(PFIT_CONTROL);
 147
 148                 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
 149         }
 150
 151         pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 152 }
 153
 154 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
 155                                         struct intel_lvds_pps *pps)
 156 {
 157         u32 val;
 158
 159         pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
 160
 161         val = I915_READ(PP_ON_DELAYS(0));
 162         pps->port = (val & PANEL_PORT_SELECT_MASK) >>
 163                     PANEL_PORT_SELECT_SHIFT;
 164         pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >>
 165                      PANEL_POWER_UP_DELAY_SHIFT;
 166         pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >>
 167                   PANEL_LIGHT_ON_DELAY_SHIFT;
 168
 169         val = I915_READ(PP_OFF_DELAYS(0));
 170         pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >>
 171                   PANEL_POWER_DOWN_DELAY_SHIFT;
 172         pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >>
 173                   PANEL_LIGHT_OFF_DELAY_SHIFT;
 174
 175         val = I915_READ(PP_DIVISOR(0));
 176         pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >>
 177                        PP_REFERENCE_DIVIDER_SHIFT;
 178         val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >>
 179               PANEL_POWER_CYCLE_DELAY_SHIFT;
 180         /*
 181          * Remove the BSpec specified +1 (100ms) offset that accounts for a
 182          * too short power-cycle delay due to the asynchronous programming of
 183          * the register.
 184          */
 185         if (val)
 186                 val--;
 187         /* Convert from 100ms to 100us units */
 188         pps->t4 = val * 1000;
 189
 190         if (INTEL_INFO(dev_priv)->gen <= 4 &&
 191             pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
 192                 DRM_DEBUG_KMS("Panel power timings uninitialized, "
 193                               "setting defaults\n");
 194                 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
 195                 pps->t1_t2 = 40 * 10;
 196                 pps->t5 = 200 * 10;
 197                 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
 198                 pps->t3 = 35 * 10;
 199                 pps->tx = 200 * 10;
 200         }
 201
 202         DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
 203                          "divider %d port %d powerdown_on_reset %d\n",
 204                          pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
 205                          pps->divider, pps->port, pps->powerdown_on_reset);
 206 }
 207
 208 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
 209                                    struct intel_lvds_pps *pps)
 210 {
 211         u32 val;
 212
 213         val = I915_READ(PP_CONTROL(0));
 214         WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
 215         if (pps->powerdown_on_reset)
 216                 val |= PANEL_POWER_RESET;
 217         I915_WRITE(PP_CONTROL(0), val);
 218
 219         I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) |
 220                                     (pps->t1_t2 << PANEL_POWER_UP_DELAY_SHIFT) |
 221                                     (pps->t5 << PANEL_LIGHT_ON_DELAY_SHIFT));
 222         I915_WRITE(PP_OFF_DELAYS(0), (pps->t3 << PANEL_POWER_DOWN_DELAY_SHIFT) |
 223                                      (pps->tx << PANEL_LIGHT_OFF_DELAY_SHIFT));
 224
 225         val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT;
 226         val |= (DIV_ROUND_UP(pps->t4, 1000) + 1) <<
 227                PANEL_POWER_CYCLE_DELAY_SHIFT;
 228         I915_WRITE(PP_DIVISOR(0), val);
 229 }
 230
 231 static void intel_pre_enable_lvds(struct intel_encoder *encoder,
 232                                   struct intel_crtc_state *pipe_config,
 233                                   struct drm_connector_state *conn_state)
 234 {
 235         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 236         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 237         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 238         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 239         int pipe = crtc->pipe;
 240         u32 temp;
 241
 242         if (HAS_PCH_SPLIT(dev_priv)) {
 243                 assert_fdi_rx_pll_disabled(dev_priv, pipe);
 244                 assert_shared_dpll_disabled(dev_priv,
 245                                             pipe_config->shared_dpll);
 246         } else {
 247                 assert_pll_disabled(dev_priv, pipe);
 248         }
 249
 250         intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps);
 251
 252         temp = lvds_encoder->init_lvds_val;
 253         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 254
 255         if (HAS_PCH_CPT(dev_priv)) {
 256                 temp &= ~PORT_TRANS_SEL_MASK;
 257                 temp |= PORT_TRANS_SEL_CPT(pipe);
 258         } else {
 259                 if (pipe == 1) {
 260                         temp |= LVDS_PIPEB_SELECT;
 261                 } else {
 262                         temp &= ~LVDS_PIPEB_SELECT;
 263                 }
 264         }
 265
 266         /* set the corresponsding LVDS_BORDER bit */
 267         temp &= ~LVDS_BORDER_ENABLE;
 268         temp |= pipe_config->gmch_pfit.lvds_border_bits;
 269         /* Set the B0-B3 data pairs corresponding to whether we're going to
 270          * set the DPLLs for dual-channel mode or not.
 271          */
 272         if (lvds_encoder->is_dual_link)
 273                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
 274         else
 275                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
 276
 277         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
 278          * appropriately here, but we need to look more thoroughly into how
 279          * panels behave in the two modes. For now, let's just maintain the
 280          * value we got from the BIOS.
 281          */
 282         temp &= ~LVDS_A3_POWER_MASK;
 283         temp |= lvds_encoder->a3_power;
 284
 285         /* Set the dithering flag on LVDS as needed, note that there is no
 286          * special lvds dither control bit on pch-split platforms, dithering is
 287          * only controlled through the PIPECONF reg. */
 288         if (IS_GEN4(dev_priv)) {
 289                 /* Bspec wording suggests that LVDS port dithering only exists
 290                  * for 18bpp panels. */
 291                 if (pipe_config->dither && pipe_config->pipe_bpp == 18)
 292                         temp |= LVDS_ENABLE_DITHER;
 293                 else
 294                         temp &= ~LVDS_ENABLE_DITHER;
 295         }
 296         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
 297         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 298                 temp |= LVDS_HSYNC_POLARITY;
 299         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 300                 temp |= LVDS_VSYNC_POLARITY;
 301
 302         I915_WRITE(lvds_encoder->reg, temp);
 303 }
 304
 305 /**
 306  * Sets the power state for the panel.
 307  */
 308 static void intel_enable_lvds(struct intel_encoder *encoder,
 309                               struct intel_crtc_state *pipe_config,
 310                               struct drm_connector_state *conn_state)
 311 {
 312         struct drm_device *dev = encoder->base.dev;
 313         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 314         struct intel_connector *intel_connector =
 315                 &lvds_encoder->attached_connector->base;
 316         struct drm_i915_private *dev_priv = to_i915(dev);
 317
 318         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
 319
 320         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
 321         POSTING_READ(lvds_encoder->reg);
 322         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 1000))
 323                 DRM_ERROR("timed out waiting for panel to power on\n");
 324
 325         intel_panel_enable_backlight(intel_connector);
 326 }
 327
 328 static void intel_disable_lvds(struct intel_encoder *encoder,
 329                                struct intel_crtc_state *old_crtc_state,
 330                                struct drm_connector_state *old_conn_state)
 331 {
 332         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 333         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 334
 335         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
 336         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000))
 337                 DRM_ERROR("timed out waiting for panel to power off\n");
 338
 339         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
 340         POSTING_READ(lvds_encoder->reg);
 341 }
 342
 343 static void gmch_disable_lvds(struct intel_encoder *encoder,
 344                               struct intel_crtc_state *old_crtc_state,
 345                               struct drm_connector_state *old_conn_state)
 346
 347 {
 348         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 349         struct intel_connector *intel_connector =
 350                 &lvds_encoder->attached_connector->base;
 351
 352         intel_panel_disable_backlight(intel_connector);
 353
 354         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 355 }
 356
 357 static void pch_disable_lvds(struct intel_encoder *encoder,
 358                              struct intel_crtc_state *old_crtc_state,
 359                              struct drm_connector_state *old_conn_state)
 360 {
 361         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 362         struct intel_connector *intel_connector =
 363                 &lvds_encoder->attached_connector->base;
 364
 365         intel_panel_disable_backlight(intel_connector);
 366 }
 367
 368 static void pch_post_disable_lvds(struct intel_encoder *encoder,
 369                                   struct intel_crtc_state *old_crtc_state,
 370                                   struct drm_connector_state *old_conn_state)
 371 {
 372         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 373 }
 374
 375 static enum drm_mode_status
 376 intel_lvds_mode_valid(struct drm_connector *connector,
 377                       struct drm_display_mode *mode)
 378 {
 379         struct intel_connector *intel_connector = to_intel_connector(connector);
 380         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 381         int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
 382
 383         if (mode->hdisplay > fixed_mode->hdisplay)
 384                 return MODE_PANEL;
 385         if (mode->vdisplay > fixed_mode->vdisplay)
 386                 return MODE_PANEL;
 387         if (fixed_mode->clock > max_pixclk)
 388                 return MODE_CLOCK_HIGH;
 389
 390         return MODE_OK;
 391 }
 392
 393 static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
 394                                       struct intel_crtc_state *pipe_config,
 395                                       struct drm_connector_state *conn_state)
 396 {
 397         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
 398         struct intel_lvds_encoder *lvds_encoder =
 399                 to_lvds_encoder(&intel_encoder->base);
 400         struct intel_connector *intel_connector =
 401                 &lvds_encoder->attached_connector->base;
 402         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 403         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
 404         unsigned int lvds_bpp;
 405
 406         /* Should never happen!! */
 407         if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
 408                 DRM_ERROR("Can't support LVDS on pipe A\n");
 409                 return false;
 410         }
 411
 412         if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
 413                 lvds_bpp = 8*3;
 414         else
 415                 lvds_bpp = 6*3;
 416
 417         if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
 418                 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
 419                               pipe_config->pipe_bpp, lvds_bpp);
 420                 pipe_config->pipe_bpp = lvds_bpp;
 421         }
 422
 423         /*
 424          * We have timings from the BIOS for the panel, put them in
 425          * to the adjusted mode.  The CRTC will be set up for this mode,
 426          * with the panel scaling set up to source from the H/VDisplay
 427          * of the original mode.
 428          */
 429         intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 430                                adjusted_mode);
 431
 432         if (HAS_PCH_SPLIT(dev_priv)) {
 433                 pipe_config->has_pch_encoder = true;
 434
 435                 intel_pch_panel_fitting(intel_crtc, pipe_config,
 436                                         intel_connector->panel.fitting_mode);
 437         } else {
 438                 intel_gmch_panel_fitting(intel_crtc, pipe_config,
 439                                          intel_connector->panel.fitting_mode);
 440
 441         }
 442
 443         /*
 444          * XXX: It would be nice to support lower refresh rates on the
 445          * panels to reduce power consumption, and perhaps match the
 446          * user's requested refresh rate.
 447          */
 448
 449         return true;
 450 }
 451
 452 /**
 453  * Detect the LVDS connection.
 454  *
 455  * Since LVDS doesn't have hotlug, we use the lid as a proxy.  Open means
 456  * connected and closed means disconnected.  We also send hotplug events as
 457  * needed, using lid status notification from the input layer.
 458  */
 459 static enum drm_connector_status
 460 intel_lvds_detect(struct drm_connector *connector, bool force)
 461 {
 462         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 463         enum drm_connector_status status;
 464
 465         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
 466                       connector->base.id, connector->name);
 467
 468         status = intel_panel_detect(dev_priv);
 469         if (status != connector_status_unknown)
 470                 return status;
 471
 472         return connector_status_connected;
 473 }
 474
 475 /**
 476  * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
 477  */
 478 static int intel_lvds_get_modes(struct drm_connector *connector)
 479 {
 480         struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
 481         struct drm_device *dev = connector->dev;
 482         struct drm_display_mode *mode;
 483
 484         /* use cached edid if we have one */
 485         if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
 486                 return drm_add_edid_modes(connector, lvds_connector->base.edid);
 487
 488         mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
 489         if (mode == NULL)
 490                 return 0;
 491
 492         drm_mode_probed_add(connector, mode);
 493         return 1;
 494 }
 495
 496 static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
 497 {
 498         DRM_INFO("Skipping forced modeset for %s\n", id->ident);
 499         return 1;
 500 }
 501
 502 /* The GPU hangs up on these systems if modeset is performed on LID open */
 503 static const struct dmi_system_id intel_no_modeset_on_lid[] = {
 504         {
 505                 .callback = intel_no_modeset_on_lid_dmi_callback,
 506                 .ident = "Toshiba Tecra A11",
 507                 .matches = {
 508                         DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 509                         DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
 510                 },
 511         },
 512
 513         { }     /* terminating entry */
 514 };
 515
 516 /*
 517  * Lid events. Note the use of 'modeset':
 518  *  - we set it to MODESET_ON_LID_OPEN on lid close,
 519  *    and set it to MODESET_DONE on open
 520  *  - we use it as a "only once" bit (ie we ignore
 521  *    duplicate events where it was already properly set)
 522  *  - the suspend/resume paths will set it to
 523  *    MODESET_SUSPENDED and ignore the lid open event,
 524  *    because they restore the mode ("lid open").
 525  */
 526 static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
 527                             void *unused)
 528 {
 529         struct intel_lvds_connector *lvds_connector =
 530                 container_of(nb, struct intel_lvds_connector, lid_notifier);
 531         struct drm_connector *connector = &lvds_connector->base.base;
 532         struct drm_device *dev = connector->dev;
 533         struct drm_i915_private *dev_priv = to_i915(dev);
 534
 535         if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
 536                 return NOTIFY_OK;
 537
 538         mutex_lock(&dev_priv->modeset_restore_lock);
 539         if (dev_priv->modeset_restore == MODESET_SUSPENDED)
 540                 goto exit;
 541         /*
 542          * check and update the status of LVDS connector after receiving
 543          * the LID nofication event.
 544          */
 545         connector->status = connector->funcs->detect(connector, false);
 546
 547         /* Don't force modeset on machines where it causes a GPU lockup */
 548         if (dmi_check_system(intel_no_modeset_on_lid))
 549                 goto exit;
 550         if (!acpi_lid_open()) {
 551                 /* do modeset on next lid open event */
 552                 dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
 553                 goto exit;
 554         }
 555
 556         if (dev_priv->modeset_restore == MODESET_DONE)
 557                 goto exit;
 558
 559         /*
 560          * Some old platform's BIOS love to wreak havoc while the lid is closed.
 561          * We try to detect this here and undo any damage. The split for PCH
 562          * platforms is rather conservative and a bit arbitrary expect that on
 563          * those platforms VGA disabling requires actual legacy VGA I/O access,
 564          * and as part of the cleanup in the hw state restore we also redisable
 565          * the vga plane.
 566          */
 567         if (!HAS_PCH_SPLIT(dev_priv))
 568                 intel_display_resume(dev);
 569
 570         dev_priv->modeset_restore = MODESET_DONE;
 571
 572 exit:
 573         mutex_unlock(&dev_priv->modeset_restore_lock);
 574         return NOTIFY_OK;
 575 }
 576
 577 /**
 578  * intel_lvds_destroy - unregister and free LVDS structures
 579  * @connector: connector to free
 580  *
 581  * Unregister the DDC bus for this connector then free the driver private
 582  * structure.
 583  */
 584 static void intel_lvds_destroy(struct drm_connector *connector)
 585 {
 586         struct intel_lvds_connector *lvds_connector =
 587                 to_lvds_connector(connector);
 588
 589         if (lvds_connector->lid_notifier.notifier_call)
 590                 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
 591
 592         if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
 593                 kfree(lvds_connector->base.edid);
 594
 595         intel_panel_fini(&lvds_connector->base.panel);
 596
 597         drm_connector_cleanup(connector);
 598         kfree(connector);
 599 }
 600
 601 static int intel_lvds_set_property(struct drm_connector *connector,
 602                                    struct drm_property *property,
 603                                    uint64_t value)
 604 {
 605         struct intel_connector *intel_connector = to_intel_connector(connector);
 606         struct drm_device *dev = connector->dev;
 607
 608         if (property == dev->mode_config.scaling_mode_property) {
 609                 struct drm_crtc *crtc;
 610
 611                 if (value == DRM_MODE_SCALE_NONE) {
 612                         DRM_DEBUG_KMS("no scaling not supported\n");
 613                         return -EINVAL;
 614                 }
 615
 616                 if (intel_connector->panel.fitting_mode == value) {
 617                         /* the LVDS scaling property is not changed */
 618                         return 0;
 619                 }
 620                 intel_connector->panel.fitting_mode = value;
 621
 622                 crtc = intel_attached_encoder(connector)->base.crtc;
 623                 if (crtc && crtc->state->enable) {
 624                         /*
 625                          * If the CRTC is enabled, the display will be changed
 626                          * according to the new panel fitting mode.
 627                          */
 628                         intel_crtc_restore_mode(crtc);
 629                 }
 630         }
 631
 632         return 0;
 633 }
 634
 635 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
 636         .get_modes = intel_lvds_get_modes,
 637         .mode_valid = intel_lvds_mode_valid,
 638 };
 639
 640 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
 641         .dpms = drm_atomic_helper_connector_dpms,
 642         .detect = intel_lvds_detect,
 643         .fill_modes = drm_helper_probe_single_connector_modes,
 644         .set_property = intel_lvds_set_property,
 645         .atomic_get_property = intel_connector_atomic_get_property,
 646         .late_register = intel_connector_register,
 647         .early_unregister = intel_connector_unregister,
 648         .destroy = intel_lvds_destroy,
 649         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 650         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 651 };
 652
 653 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
 654         .destroy = intel_encoder_destroy,
 655 };
 656
 657 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
 658 {
 659         DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
 660         return 1;
 661 }
 662
 663 /* These systems claim to have LVDS, but really don't */
 664 static const struct dmi_system_id intel_no_lvds[] = {
 665         {
 666                 .callback = intel_no_lvds_dmi_callback,
 667                 .ident = "Apple Mac Mini (Core series)",
 668                 .matches = {
 669                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 670                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
 671                 },
 672         },
 673         {
 674                 .callback = intel_no_lvds_dmi_callback,
 675                 .ident = "Apple Mac Mini (Core 2 series)",
 676                 .matches = {
 677                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 678                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
 679                 },
 680         },
 681         {
 682                 .callback = intel_no_lvds_dmi_callback,
 683                 .ident = "MSI IM-945GSE-A",
 684                 .matches = {
 685                         DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
 686                         DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
 687                 },
 688         },
 689         {
 690                 .callback = intel_no_lvds_dmi_callback,
 691                 .ident = "Dell Studio Hybrid",
 692                 .matches = {
 693                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 694                         DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
 695                 },
 696         },
 697         {
 698                 .callback = intel_no_lvds_dmi_callback,
 699                 .ident = "Dell OptiPlex FX170",
 700                 .matches = {
 701                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 702                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
 703                 },
 704         },
 705         {
 706                 .callback = intel_no_lvds_dmi_callback,
 707                 .ident = "AOpen Mini PC",
 708                 .matches = {
 709                         DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
 710                         DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
 711                 },
 712         },
 713         {
 714                 .callback = intel_no_lvds_dmi_callback,
 715                 .ident = "AOpen Mini PC MP915",
 716                 .matches = {
 717                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 718                         DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
 719                 },
 720         },
 721         {
 722                 .callback = intel_no_lvds_dmi_callback,
 723                 .ident = "AOpen i915GMm-HFS",
 724                 .matches = {
 725                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 726                         DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
 727                 },
 728         },
 729         {
 730                 .callback = intel_no_lvds_dmi_callback,
 731                 .ident = "AOpen i45GMx-I",
 732                 .matches = {
 733                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 734                         DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
 735                 },
 736         },
 737         {
 738                 .callback = intel_no_lvds_dmi_callback,
 739                 .ident = "Aopen i945GTt-VFA",
 740                 .matches = {
 741                         DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
 742                 },
 743         },
 744         {
 745                 .callback = intel_no_lvds_dmi_callback,
 746                 .ident = "Clientron U800",
 747                 .matches = {
 748                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 749                         DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
 750                 },
 751         },
 752         {
 753                 .callback = intel_no_lvds_dmi_callback,
 754                 .ident = "Clientron E830",
 755                 .matches = {
 756                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 757                         DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
 758                 },
 759         },
 760         {
 761                 .callback = intel_no_lvds_dmi_callback,
 762                 .ident = "Asus EeeBox PC EB1007",
 763                 .matches = {
 764                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
 765                         DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
 766                 },
 767         },
 768         {
 769                 .callback = intel_no_lvds_dmi_callback,
 770                 .ident = "Asus AT5NM10T-I",
 771                 .matches = {
 772                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 773                         DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
 774                 },
 775         },
 776         {
 777                 .callback = intel_no_lvds_dmi_callback,
 778                 .ident = "Hewlett-Packard HP t5740",
 779                 .matches = {
 780                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 781                         DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
 782                 },
 783         },
 784         {
 785                 .callback = intel_no_lvds_dmi_callback,
 786                 .ident = "Hewlett-Packard t5745",
 787                 .matches = {
 788                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 789                         DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
 790                 },
 791         },
 792         {
 793                 .callback = intel_no_lvds_dmi_callback,
 794                 .ident = "Hewlett-Packard st5747",
 795                 .matches = {
 796                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 797                         DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
 798                 },
 799         },
 800         {
 801                 .callback = intel_no_lvds_dmi_callback,
 802                 .ident = "MSI Wind Box DC500",
 803                 .matches = {
 804                         DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
 805                         DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
 806                 },
 807         },
 808         {
 809                 .callback = intel_no_lvds_dmi_callback,
 810                 .ident = "Gigabyte GA-D525TUD",
 811                 .matches = {
 812                         DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
 813                         DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
 814                 },
 815         },
 816         {
 817                 .callback = intel_no_lvds_dmi_callback,
 818                 .ident = "Supermicro X7SPA-H",
 819                 .matches = {
 820                         DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
 821                         DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
 822                 },
 823         },
 824         {
 825                 .callback = intel_no_lvds_dmi_callback,
 826                 .ident = "Fujitsu Esprimo Q900",
 827                 .matches = {
 828                         DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
 829                         DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
 830                 },
 831         },
 832         {
 833                 .callback = intel_no_lvds_dmi_callback,
 834                 .ident = "Intel D410PT",
 835                 .matches = {
 836                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 837                         DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
 838                 },
 839         },
 840         {
 841                 .callback = intel_no_lvds_dmi_callback,
 842                 .ident = "Intel D425KT",
 843                 .matches = {
 844                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 845                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
 846                 },
 847         },
 848         {
 849                 .callback = intel_no_lvds_dmi_callback,
 850                 .ident = "Intel D510MO",
 851                 .matches = {
 852                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 853                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
 854                 },
 855         },
 856         {
 857                 .callback = intel_no_lvds_dmi_callback,
 858                 .ident = "Intel D525MW",
 859                 .matches = {
 860                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 861                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
 862                 },
 863         },
 864
 865         { }     /* terminating entry */
 866 };
 867
 868 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 869 {
 870         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 871         return 1;
 872 }
 873
 874 static const struct dmi_system_id intel_dual_link_lvds[] = {
 875         {
 876                 .callback = intel_dual_link_lvds_callback,
 877                 .ident = "Apple MacBook Pro 15\" (2010)",
 878                 .matches = {
 879                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 880                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
 881                 },
 882         },
 883         {
 884                 .callback = intel_dual_link_lvds_callback,
 885                 .ident = "Apple MacBook Pro 15\" (2011)",
 886                 .matches = {
 887                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 888                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 889                 },
 890         },
 891         {
 892                 .callback = intel_dual_link_lvds_callback,
 893                 .ident = "Apple MacBook Pro 15\" (2012)",
 894                 .matches = {
 895                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 896                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
 897                 },
 898         },
 899         { }     /* terminating entry */
 900 };
 901
 902 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev)
 903 {
 904         struct intel_encoder *intel_encoder;
 905
 906         for_each_intel_encoder(dev, intel_encoder)
 907                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
 908                         return intel_encoder;
 909
 910         return NULL;
 911 }
 912
 913 bool intel_is_dual_link_lvds(struct drm_device *dev)
 914 {
 915         struct intel_encoder *encoder = intel_get_lvds_encoder(dev);
 916
 917         return encoder && to_lvds_encoder(&encoder->base)->is_dual_link;
 918 }
 919
 920 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
 921 {
 922         struct drm_device *dev = lvds_encoder->base.base.dev;
 923         unsigned int val;
 924         struct drm_i915_private *dev_priv = to_i915(dev);
 925
 926         /* use the module option value if specified */
 927         if (i915.lvds_channel_mode > 0)
 928                 return i915.lvds_channel_mode == 2;
 929
 930         /* single channel LVDS is limited to 112 MHz */
 931         if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock
 932             > 112999)
 933                 return true;
 934
 935         if (dmi_check_system(intel_dual_link_lvds))
 936                 return true;
 937
 938         /* BIOS should set the proper LVDS register value at boot, but
 939          * in reality, it doesn't set the value when the lid is closed;
 940          * we need to check "the value to be set" in VBT when LVDS
 941          * register is uninitialized.
 942          */
 943         val = I915_READ(lvds_encoder->reg);
 944         if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 945                 val = dev_priv->vbt.bios_lvds_val;
 946
 947         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 948 }
 949
 950 static bool intel_lvds_supported(struct drm_i915_private *dev_priv)
 951 {
 952         /* With the introduction of the PCH we gained a dedicated
 953          * LVDS presence pin, use it. */
 954         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
 955                 return true;
 956
 957         /* Otherwise LVDS was only attached to mobile products,
 958          * except for the inglorious 830gm */
 959         if (INTEL_GEN(dev_priv) <= 4 &&
 960             IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
 961                 return true;
 962
 963         return false;
 964 }
 965
 966 /**
 967  * intel_lvds_init - setup LVDS connectors on this device
 968  * @dev: drm device
 969  *
 970  * Create the connector, register the LVDS DDC bus, and try to figure out what
 971  * modes we can display on the LVDS panel (if present).
 972  */
 973 void intel_lvds_init(struct drm_i915_private *dev_priv)
 974 {
 975         struct drm_device *dev = &dev_priv->drm;
 976         struct intel_lvds_encoder *lvds_encoder;
 977         struct intel_encoder *intel_encoder;
 978         struct intel_lvds_connector *lvds_connector;
 979         struct intel_connector *intel_connector;
 980         struct drm_connector *connector;
 981         struct drm_encoder *encoder;
 982         struct drm_display_mode *scan; /* *modes, *bios_mode; */
 983         struct drm_display_mode *fixed_mode = NULL;
 984         struct drm_display_mode *downclock_mode = NULL;
 985         struct edid *edid;
 986         struct intel_crtc *crtc;
 987         i915_reg_t lvds_reg;
 988         u32 lvds;
 989         int pipe;
 990         u8 pin;
 991
 992         if (!intel_lvds_supported(dev_priv))
 993                 return;
 994
 995         /* Skip init on machines we know falsely report LVDS */
 996         if (dmi_check_system(intel_no_lvds))
 997                 return;
 998
 999         if (HAS_PCH_SPLIT(dev_priv))
1000                 lvds_reg = PCH_LVDS;
1001         else
1002                 lvds_reg = LVDS;
1003
1004         lvds = I915_READ(lvds_reg);
1005
1006         if (HAS_PCH_SPLIT(dev_priv)) {
1007                 if ((lvds & LVDS_DETECTED) == 0)
1008                         return;
1009                 if (dev_priv->vbt.edp.support) {
1010                         DRM_DEBUG_KMS("disable LVDS for eDP support\n");
1011                         return;
1012                 }
1013         }
1014
1015         pin = GMBUS_PIN_PANEL;
1016         if (!intel_bios_is_lvds_present(dev_priv, &pin)) {
1017                 if ((lvds & LVDS_PORT_EN) == 0) {
1018                         DRM_DEBUG_KMS("LVDS is not present in VBT\n");
1019                         return;
1020                 }
1021                 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n");
1022         }
1023
1024         lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
1025         if (!lvds_encoder)
1026                 return;
1027
1028         lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL);
1029         if (!lvds_connector) {
1030                 kfree(lvds_encoder);
1031                 return;
1032         }
1033
1034         if (intel_connector_init(&lvds_connector->base) < 0) {
1035                 kfree(lvds_connector);
1036                 kfree(lvds_encoder);
1037                 return;
1038         }
1039
1040         lvds_encoder->attached_connector = lvds_connector;
1041
1042         intel_encoder = &lvds_encoder->base;
1043         encoder = &intel_encoder->base;
1044         intel_connector = &lvds_connector->base;
1045         connector = &intel_connector->base;
1046         drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
1047                            DRM_MODE_CONNECTOR_LVDS);
1048
1049         drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
1050                          DRM_MODE_ENCODER_LVDS, "LVDS");
1051
1052         intel_encoder->enable = intel_enable_lvds;
1053         intel_encoder->pre_enable = intel_pre_enable_lvds;
1054         intel_encoder->compute_config = intel_lvds_compute_config;
1055         if (HAS_PCH_SPLIT(dev_priv)) {
1056                 intel_encoder->disable = pch_disable_lvds;
1057                 intel_encoder->post_disable = pch_post_disable_lvds;
1058         } else {
1059                 intel_encoder->disable = gmch_disable_lvds;
1060         }
1061         intel_encoder->get_hw_state = intel_lvds_get_hw_state;
1062         intel_encoder->get_config = intel_lvds_get_config;
1063         intel_connector->get_hw_state = intel_connector_get_hw_state;
1064
1065         intel_connector_attach_encoder(intel_connector, intel_encoder);
1066
1067         intel_encoder->type = INTEL_OUTPUT_LVDS;
1068         intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
1069         intel_encoder->port = PORT_NONE;
1070         intel_encoder->cloneable = 0;
1071         if (HAS_PCH_SPLIT(dev_priv))
1072                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1073         else if (IS_GEN4(dev_priv))
1074                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1075         else
1076                 intel_encoder->crtc_mask = (1 << 1);
1077
1078         drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
1079         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1080         connector->interlace_allowed = false;
1081         connector->doublescan_allowed = false;
1082
1083         lvds_encoder->reg = lvds_reg;
1084
1085         /* create the scaling mode property */
1086         drm_mode_create_scaling_mode_property(dev);
1087         drm_object_attach_property(&connector->base,
1088                                       dev->mode_config.scaling_mode_property,
1089                                       DRM_MODE_SCALE_ASPECT);
1090         intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
1091
1092         intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps);
1093         lvds_encoder->init_lvds_val = lvds;
1094
1095         /*
1096          * LVDS discovery:
1097          * 1) check for EDID on DDC
1098          * 2) check for VBT data
1099          * 3) check to see if LVDS is already on
1100          *    if none of the above, no panel
1101          * 4) make sure lid is open
1102          *    if closed, act like it's not there for now
1103          */
1104
1105         /*
1106          * Attempt to get the fixed panel mode from DDC.  Assume that the
1107          * preferred mode is the right one.
1108          */
1109         mutex_lock(&dev->mode_config.mutex);
1110         if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
1111                 edid = drm_get_edid_switcheroo(connector,
1112                                     intel_gmbus_get_adapter(dev_priv, pin));
1113         else
1114                 edid = drm_get_edid(connector,
1115                                     intel_gmbus_get_adapter(dev_priv, pin));
1116         if (edid) {
1117                 if (drm_add_edid_modes(connector, edid)) {
1118                         drm_mode_connector_update_edid_property(connector,
1119                                                                 edid);
1120                 } else {
1121                         kfree(edid);
1122                         edid = ERR_PTR(-EINVAL);
1123                 }
1124         } else {
1125                 edid = ERR_PTR(-ENOENT);
1126         }
1127         lvds_connector->base.edid = edid;
1128
1129         list_for_each_entry(scan, &connector->probed_modes, head) {
1130                 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
1131                         DRM_DEBUG_KMS("using preferred mode from EDID: ");
1132                         drm_mode_debug_printmodeline(scan);
1133
1134                         fixed_mode = drm_mode_duplicate(dev, scan);
1135                         if (fixed_mode)
1136                                 goto out;
1137                 }
1138         }
1139
1140         /* Failed to get EDID, what about VBT? */
1141         if (dev_priv->vbt.lfp_lvds_vbt_mode) {
1142                 DRM_DEBUG_KMS("using mode from VBT: ");
1143                 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
1144
1145                 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
1146                 if (fixed_mode) {
1147                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1148                         connector->display_info.width_mm = fixed_mode->width_mm;
1149                         connector->display_info.height_mm = fixed_mode->height_mm;
1150                         goto out;
1151                 }
1152         }
1153
1154         /*
1155          * If we didn't get EDID, try checking if the panel is already turned
1156          * on.  If so, assume that whatever is currently programmed is the
1157          * correct mode.
1158          */
1159
1160         /* Ironlake: FIXME if still fail, not try pipe mode now */
1161         if (HAS_PCH_SPLIT(dev_priv))
1162                 goto failed;
1163
1164         pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
1165         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1166
1167         if (crtc && (lvds & LVDS_PORT_EN)) {
1168                 fixed_mode = intel_crtc_mode_get(dev, &crtc->base);
1169                 if (fixed_mode) {
1170                         DRM_DEBUG_KMS("using current (BIOS) mode: ");
1171                         drm_mode_debug_printmodeline(fixed_mode);
1172                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1173                         goto out;
1174                 }
1175         }
1176
1177         /* If we still don't have a mode after all that, give up. */
1178         if (!fixed_mode)
1179                 goto failed;
1180
1181 out:
1182         mutex_unlock(&dev->mode_config.mutex);
1183
1184         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
1185         intel_panel_setup_backlight(connector, INVALID_PIPE);
1186
1187         lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
1188         DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1189                       lvds_encoder->is_dual_link ? "dual" : "single");
1190
1191         lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1192
1193         lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1194         if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
1195                 DRM_DEBUG_KMS("lid notifier registration failed\n");
1196                 lvds_connector->lid_notifier.notifier_call = NULL;
1197         }
1198
1199         return;
1200
1201 failed:
1202         mutex_unlock(&dev->mode_config.mutex);
1203
1204         DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1205         drm_connector_cleanup(connector);
1206         drm_encoder_cleanup(encoder);
1207         kfree(lvds_encoder);
1208         kfree(lvds_connector);
1209         return;
1210 }