drivers/gpu/drm/i915/intel_mocs.c

   1 /*
   2  * Copyright (c) 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions: *
  10  * The above copyright notice and this permission notice (including the next
  11  * paragraph) shall be included in all copies or substantial portions of the
  12  * Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "intel_mocs.h"
  24 #include "intel_lrc.h"
  25 #include "intel_ringbuffer.h"
  26
  27 /* structures required */
  28 struct drm_i915_mocs_entry {
  29         u32 control_value;
  30         u16 l3cc_value;
  31 };
  32
  33 struct drm_i915_mocs_table {
  34         u32 size;
  35         const struct drm_i915_mocs_entry *table;
  36 };
  37
  38 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
  39 #define LE_CACHEABILITY(value)  ((value) << 0)
  40 #define LE_TGT_CACHE(value)     ((value) << 2)
  41 #define LE_LRUM(value)          ((value) << 4)
  42 #define LE_AOM(value)           ((value) << 6)
  43 #define LE_RSC(value)           ((value) << 7)
  44 #define LE_SCC(value)           ((value) << 8)
  45 #define LE_PFM(value)           ((value) << 11)
  46 #define LE_SCF(value)           ((value) << 14)
  47
  48 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
  49 #define L3_ESC(value)           ((value) << 0)
  50 #define L3_SCC(value)           ((value) << 1)
  51 #define L3_CACHEABILITY(value)  ((value) << 4)
  52
  53 /* Helper defines */
  54 #define GEN9_NUM_MOCS_ENTRIES   62  /* 62 out of 64 - 63 & 64 are reserved. */
  55
  56 /* (e)LLC caching options */
  57 #define LE_PAGETABLE            0
  58 #define LE_UC                   1
  59 #define LE_WT                   2
  60 #define LE_WB                   3
  61
  62 /* L3 caching options */
  63 #define L3_DIRECT               0
  64 #define L3_UC                   1
  65 #define L3_RESERVED             2
  66 #define L3_WB                   3
  67
  68 /* Target cache */
  69 #define ELLC                    0
  70 #define LLC                     1
  71 #define LLC_ELLC                2
  72
  73 /*
  74  * MOCS tables
  75  *
  76  * These are the MOCS tables that are programmed across all the rings.
  77  * The control value is programmed to all the rings that support the
  78  * MOCS registers. While the l3cc_values are only programmed to the
  79  * LNCFCMOCS0 - LNCFCMOCS32 registers.
  80  *
  81  * These tables are intended to be kept reasonably consistent across
  82  * platforms. However some of the fields are not applicable to all of
  83  * them.
  84  *
  85  * Entries not part of the following tables are undefined as far as
  86  * userspace is concerned and shouldn't be relied upon.  For the time
  87  * being they will be implicitly initialized to the strictest caching
  88  * configuration (uncached) to guarantee forwards compatibility with
  89  * userspace programs written against more recent kernels providing
  90  * additional MOCS entries.
  91  *
  92  * NOTE: These tables MUST start with being uncached and the length
  93  *       MUST be less than 63 as the last two registers are reserved
  94  *       by the hardware.  These tables are part of the kernel ABI and
  95  *       may only be updated incrementally by adding entries at the
  96  *       end.
  97  */
  98 static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
  99         /* { 0x00000009, 0x0010 } */
 100         { (LE_CACHEABILITY(LE_UC) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(0) |
 101            LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
 102           (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC)) },
 103         /* { 0x00000038, 0x0030 } */
 104         { (LE_CACHEABILITY(LE_PAGETABLE) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
 105            LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
 106           (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) },
 107         /* { 0x0000003b, 0x0030 } */
 108         { (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
 109            LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
 110           (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }
 111 };
 112
 113 /* NOTE: the LE_TGT_CACHE is not used on Broxton */
 114 static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
 115         /* { 0x00000009, 0x0010 } */
 116         { (LE_CACHEABILITY(LE_UC) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(0) |
 117            LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
 118           (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC)) },
 119         /* { 0x00000038, 0x0030 } */
 120         { (LE_CACHEABILITY(LE_PAGETABLE) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
 121            LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
 122           (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) },
 123         /* { 0x0000003b, 0x0030 } */
 124         { (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
 125            LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
 126           (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }
 127 };
 128
 129 /**
 130  * get_mocs_settings()
 131  * @dev_priv:   i915 device.
 132  * @table:      Output table that will be made to point at appropriate
 133  *            MOCS values for the device.
 134  *
 135  * This function will return the values of the MOCS table that needs to
 136  * be programmed for the platform. It will return the values that need
 137  * to be programmed and if they need to be programmed.
 138  *
 139  * Return: true if there are applicable MOCS settings for the device.
 140  */
 141 static bool get_mocs_settings(struct drm_i915_private *dev_priv,
 142                               struct drm_i915_mocs_table *table)
 143 {
 144         bool result = false;
 145
 146         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 147                 table->size  = ARRAY_SIZE(skylake_mocs_table);
 148                 table->table = skylake_mocs_table;
 149                 result = true;
 150         } else if (IS_BROXTON(dev_priv)) {
 151                 table->size  = ARRAY_SIZE(broxton_mocs_table);
 152                 table->table = broxton_mocs_table;
 153                 result = true;
 154         } else {
 155                 WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
 156                           "Platform that should have a MOCS table does not.\n");
 157         }
 158
 159         return result;
 160 }
 161
 162 static i915_reg_t mocs_register(enum intel_engine_id ring, int index)
 163 {
 164         switch (ring) {
 165         case RCS:
 166                 return GEN9_GFX_MOCS(index);
 167         case VCS:
 168                 return GEN9_MFX0_MOCS(index);
 169         case BCS:
 170                 return GEN9_BLT_MOCS(index);
 171         case VECS:
 172                 return GEN9_VEBOX_MOCS(index);
 173         case VCS2:
 174                 return GEN9_MFX1_MOCS(index);
 175         default:
 176                 MISSING_CASE(ring);
 177                 return INVALID_MMIO_REG;
 178         }
 179 }
 180
 181 /**
 182  * intel_mocs_init_engine() - emit the mocs control table
 183  * @engine:     The engine for whom to emit the registers.
 184  *
 185  * This function simply emits a MI_LOAD_REGISTER_IMM command for the
 186  * given table starting at the given address.
 187  *
 188  * Return: 0 on success, otherwise the error status.
 189  */
 190 int intel_mocs_init_engine(struct intel_engine_cs *engine)
 191 {
 192         struct drm_i915_private *dev_priv = to_i915(engine->dev);
 193         struct drm_i915_mocs_table table;
 194         unsigned int index;
 195
 196         if (!get_mocs_settings(dev_priv, &table))
 197                 return 0;
 198
 199         if (WARN_ON(table.size > GEN9_NUM_MOCS_ENTRIES))
 200                 return -ENODEV;
 201
 202         for (index = 0; index < table.size; index++)
 203                 I915_WRITE(mocs_register(engine->id, index),
 204                            table.table[index].control_value);
 205
 206         /*
 207          * Ok, now set the unused entries to uncached. These entries
 208          * are officially undefined and no contract for the contents
 209          * and settings is given for these entries.
 210          *
 211          * Entry 0 in the table is uncached - so we are just writing
 212          * that value to all the used entries.
 213          */
 214         for (; index < GEN9_NUM_MOCS_ENTRIES; index++)
 215                 I915_WRITE(mocs_register(engine->id, index),
 216                            table.table[0].control_value);
 217
 218         return 0;
 219 }
 220
 221 /**
 222  * emit_mocs_control_table() - emit the mocs control table
 223  * @req:        Request to set up the MOCS table for.
 224  * @table:      The values to program into the control regs.
 225  *
 226  * This function simply emits a MI_LOAD_REGISTER_IMM command for the
 227  * given table starting at the given address.
 228  *
 229  * Return: 0 on success, otherwise the error status.
 230  */
 231 static int emit_mocs_control_table(struct drm_i915_gem_request *req,
 232                                    const struct drm_i915_mocs_table *table)
 233 {
 234         struct intel_ringbuffer *ringbuf = req->ringbuf;
 235         enum intel_engine_id engine = req->engine->id;
 236         unsigned int index;
 237         int ret;
 238
 239         if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
 240                 return -ENODEV;
 241
 242         ret = intel_ring_begin(req, 2 + 2 * GEN9_NUM_MOCS_ENTRIES);
 243         if (ret)
 244                 return ret;
 245
 246         intel_logical_ring_emit(ringbuf,
 247                                 MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
 248
 249         for (index = 0; index < table->size; index++) {
 250                 intel_logical_ring_emit_reg(ringbuf,
 251                                             mocs_register(engine, index));
 252                 intel_logical_ring_emit(ringbuf,
 253                                         table->table[index].control_value);
 254         }
 255
 256         /*
 257          * Ok, now set the unused entries to uncached. These entries
 258          * are officially undefined and no contract for the contents
 259          * and settings is given for these entries.
 260          *
 261          * Entry 0 in the table is uncached - so we are just writing
 262          * that value to all the used entries.
 263          */
 264         for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
 265                 intel_logical_ring_emit_reg(ringbuf,
 266                                             mocs_register(engine, index));
 267                 intel_logical_ring_emit(ringbuf,
 268                                         table->table[0].control_value);
 269         }
 270
 271         intel_logical_ring_emit(ringbuf, MI_NOOP);
 272         intel_logical_ring_advance(ringbuf);
 273
 274         return 0;
 275 }
 276
 277 static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table,
 278                                u16 low,
 279                                u16 high)
 280 {
 281         return table->table[low].l3cc_value |
 282                table->table[high].l3cc_value << 16;
 283 }
 284
 285 /**
 286  * emit_mocs_l3cc_table() - emit the mocs control table
 287  * @req:        Request to set up the MOCS table for.
 288  * @table:      The values to program into the control regs.
 289  *
 290  * This function simply emits a MI_LOAD_REGISTER_IMM command for the
 291  * given table starting at the given address. This register set is
 292  * programmed in pairs.
 293  *
 294  * Return: 0 on success, otherwise the error status.
 295  */
 296 static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
 297                                 const struct drm_i915_mocs_table *table)
 298 {
 299         struct intel_ringbuffer *ringbuf = req->ringbuf;
 300         unsigned int i;
 301         int ret;
 302
 303         if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
 304                 return -ENODEV;
 305
 306         ret = intel_ring_begin(req, 2 + GEN9_NUM_MOCS_ENTRIES);
 307         if (ret)
 308                 return ret;
 309
 310         intel_logical_ring_emit(ringbuf,
 311                         MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2));
 312
 313         for (i = 0; i < table->size/2; i++) {
 314                 intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
 315                 intel_logical_ring_emit(ringbuf,
 316                                         l3cc_combine(table, 2*i, 2*i+1));
 317         }
 318
 319         if (table->size & 0x01) {
 320                 /* Odd table size - 1 left over */
 321                 intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
 322                 intel_logical_ring_emit(ringbuf, l3cc_combine(table, 2*i, 0));
 323                 i++;
 324         }
 325
 326         /*
 327          * Now set the rest of the table to uncached - use entry 0 as
 328          * this will be uncached. Leave the last pair uninitialised as
 329          * they are reserved by the hardware.
 330          */
 331         for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
 332                 intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
 333                 intel_logical_ring_emit(ringbuf, l3cc_combine(table, 0, 0));
 334         }
 335
 336         intel_logical_ring_emit(ringbuf, MI_NOOP);
 337         intel_logical_ring_advance(ringbuf);
 338
 339         return 0;
 340 }
 341
 342 /**
 343  * intel_mocs_init_l3cc_table() - program the mocs control table
 344  * @dev:      The the device to be programmed.
 345  *
 346  * This function simply programs the mocs registers for the given table
 347  * starting at the given address. This register set is  programmed in pairs.
 348  *
 349  * These registers may get programmed more than once, it is simpler to
 350  * re-program 32 registers than maintain the state of when they were programmed.
 351  * We are always reprogramming with the same values and this only on context
 352  * start.
 353  *
 354  * Return: Nothing.
 355  */
 356 void intel_mocs_init_l3cc_table(struct drm_device *dev)
 357 {
 358         struct drm_i915_private *dev_priv = to_i915(dev);
 359         struct drm_i915_mocs_table table;
 360         unsigned int i;
 361
 362         if (!get_mocs_settings(dev_priv, &table))
 363                 return;
 364
 365         for (i = 0; i < table.size/2; i++)
 366                 I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 2*i, 2*i+1));
 367
 368         /* Odd table size - 1 left over */
 369         if (table.size & 0x01) {
 370                 I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 2*i, 0));
 371                 i++;
 372         }
 373
 374         /*
 375          * Now set the rest of the table to uncached - use entry 0 as
 376          * this will be uncached. Leave the last pair as initialised as
 377          * they are reserved by the hardware.
 378          */
 379         for (; i < (GEN9_NUM_MOCS_ENTRIES / 2); i++)
 380                 I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 0, 0));
 381 }
 382
 383 /**
 384  * intel_rcs_context_init_mocs() - program the MOCS register.
 385  * @req:        Request to set up the MOCS tables for.
 386  *
 387  * This function will emit a batch buffer with the values required for
 388  * programming the MOCS register values for all the currently supported
 389  * rings.
 390  *
 391  * These registers are partially stored in the RCS context, so they are
 392  * emitted at the same time so that when a context is created these registers
 393  * are set up. These registers have to be emitted into the start of the
 394  * context as setting the ELSP will re-init some of these registers back
 395  * to the hw values.
 396  *
 397  * Return: 0 on success, otherwise the error status.
 398  */
 399 int intel_rcs_context_init_mocs(struct drm_i915_gem_request *req)
 400 {
 401         struct drm_i915_mocs_table t;
 402         int ret;
 403
 404         if (get_mocs_settings(req->i915, &t)) {
 405                 /* Program the RCS control registers */
 406                 ret = emit_mocs_control_table(req, &t);
 407                 if (ret)
 408                         return ret;
 409
 410                 /* Now program the l3cc registers */
 411                 ret = emit_mocs_l3cc_table(req, &t);
 412                 if (ret)
 413                         return ret;
 414         }
 415
 416         return 0;
 417 }