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23 #include "intel_mocs.h"
24 #include "intel_lrc.h"
25 #include "intel_ringbuffer.h"
27 /* structures required */
28 struct drm_i915_mocs_entry
{
33 struct drm_i915_mocs_table
{
35 const struct drm_i915_mocs_entry
*table
;
38 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
39 #define LE_CACHEABILITY(value) ((value) << 0)
40 #define LE_TGT_CACHE(value) ((value) << 2)
41 #define LE_LRUM(value) ((value) << 4)
42 #define LE_AOM(value) ((value) << 6)
43 #define LE_RSC(value) ((value) << 7)
44 #define LE_SCC(value) ((value) << 8)
45 #define LE_PFM(value) ((value) << 11)
46 #define LE_SCF(value) ((value) << 14)
48 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
49 #define L3_ESC(value) ((value) << 0)
50 #define L3_SCC(value) ((value) << 1)
51 #define L3_CACHEABILITY(value) ((value) << 4)
54 #define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
56 /* (e)LLC caching options */
57 #define LE_PAGETABLE 0
62 /* L3 caching options */
76 * These are the MOCS tables that are programmed across all the rings.
77 * The control value is programmed to all the rings that support the
78 * MOCS registers. While the l3cc_values are only programmed to the
79 * LNCFCMOCS0 - LNCFCMOCS32 registers.
81 * These tables are intended to be kept reasonably consistent across
82 * platforms. However some of the fields are not applicable to all of
85 * Entries not part of the following tables are undefined as far as
86 * userspace is concerned and shouldn't be relied upon. For the time
87 * being they will be implicitly initialized to the strictest caching
88 * configuration (uncached) to guarantee forwards compatibility with
89 * userspace programs written against more recent kernels providing
90 * additional MOCS entries.
92 * NOTE: These tables MUST start with being uncached and the length
93 * MUST be less than 63 as the last two registers are reserved
94 * by the hardware. These tables are part of the kernel ABI and
95 * may only be updated incrementally by adding entries at the
98 static const struct drm_i915_mocs_entry skylake_mocs_table
[] = {
99 /* { 0x00000009, 0x0010 } */
100 { (LE_CACHEABILITY(LE_UC
) | LE_TGT_CACHE(LLC_ELLC
) | LE_LRUM(0) |
101 LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
102 (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC
)) },
103 /* { 0x00000038, 0x0030 } */
104 { (LE_CACHEABILITY(LE_PAGETABLE
) | LE_TGT_CACHE(LLC_ELLC
) | LE_LRUM(3) |
105 LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
106 (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB
)) },
107 /* { 0x0000003b, 0x0030 } */
108 { (LE_CACHEABILITY(LE_WB
) | LE_TGT_CACHE(LLC_ELLC
) | LE_LRUM(3) |
109 LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
110 (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB
)) }
113 /* NOTE: the LE_TGT_CACHE is not used on Broxton */
114 static const struct drm_i915_mocs_entry broxton_mocs_table
[] = {
115 /* { 0x00000009, 0x0010 } */
116 { (LE_CACHEABILITY(LE_UC
) | LE_TGT_CACHE(LLC_ELLC
) | LE_LRUM(0) |
117 LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
118 (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC
)) },
119 /* { 0x00000038, 0x0030 } */
120 { (LE_CACHEABILITY(LE_PAGETABLE
) | LE_TGT_CACHE(LLC_ELLC
) | LE_LRUM(3) |
121 LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
122 (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB
)) },
123 /* { 0x0000003b, 0x0030 } */
124 { (LE_CACHEABILITY(LE_WB
) | LE_TGT_CACHE(LLC_ELLC
) | LE_LRUM(3) |
125 LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
126 (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB
)) }
130 * get_mocs_settings()
132 * @table: Output table that will be made to point at appropriate
133 * MOCS values for the device.
135 * This function will return the values of the MOCS table that needs to
136 * be programmed for the platform. It will return the values that need
137 * to be programmed and if they need to be programmed.
139 * Return: true if there are applicable MOCS settings for the device.
141 static bool get_mocs_settings(struct drm_device
*dev
,
142 struct drm_i915_mocs_table
*table
)
146 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
147 table
->size
= ARRAY_SIZE(skylake_mocs_table
);
148 table
->table
= skylake_mocs_table
;
150 } else if (IS_BROXTON(dev
)) {
151 table
->size
= ARRAY_SIZE(broxton_mocs_table
);
152 table
->table
= broxton_mocs_table
;
155 WARN_ONCE(INTEL_INFO(dev
)->gen
>= 9,
156 "Platform that should have a MOCS table does not.\n");
163 * emit_mocs_control_table() - emit the mocs control table
164 * @req: Request to set up the MOCS table for.
165 * @table: The values to program into the control regs.
166 * @reg_base: The base for the engine that needs to be programmed.
168 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
169 * given table starting at the given address.
171 * Return: 0 on success, otherwise the error status.
173 static int emit_mocs_control_table(struct drm_i915_gem_request
*req
,
174 const struct drm_i915_mocs_table
*table
,
177 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
181 if (WARN_ON(table
->size
> GEN9_NUM_MOCS_ENTRIES
))
184 ret
= intel_logical_ring_begin(req
, 2 + 2 * GEN9_NUM_MOCS_ENTRIES
);
186 DRM_DEBUG("intel_logical_ring_begin failed %d\n", ret
);
190 intel_logical_ring_emit(ringbuf
,
191 MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES
));
193 for (index
= 0; index
< table
->size
; index
++) {
194 intel_logical_ring_emit(ringbuf
, reg_base
+ index
* 4);
195 intel_logical_ring_emit(ringbuf
,
196 table
->table
[index
].control_value
);
200 * Ok, now set the unused entries to uncached. These entries
201 * are officially undefined and no contract for the contents
202 * and settings is given for these entries.
204 * Entry 0 in the table is uncached - so we are just writing
205 * that value to all the used entries.
207 for (; index
< GEN9_NUM_MOCS_ENTRIES
; index
++) {
208 intel_logical_ring_emit(ringbuf
, reg_base
+ index
* 4);
209 intel_logical_ring_emit(ringbuf
, table
->table
[0].control_value
);
212 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
213 intel_logical_ring_advance(ringbuf
);
219 * emit_mocs_l3cc_table() - emit the mocs control table
220 * @req: Request to set up the MOCS table for.
221 * @table: The values to program into the control regs.
223 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
224 * given table starting at the given address. This register set is
225 * programmed in pairs.
227 * Return: 0 on success, otherwise the error status.
229 static int emit_mocs_l3cc_table(struct drm_i915_gem_request
*req
,
230 const struct drm_i915_mocs_table
*table
)
232 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
236 u32 filler
= (table
->table
[0].l3cc_value
& 0xffff) |
237 ((table
->table
[0].l3cc_value
& 0xffff) << 16);
240 if (WARN_ON(table
->size
> GEN9_NUM_MOCS_ENTRIES
))
243 ret
= intel_logical_ring_begin(req
, 2 + GEN9_NUM_MOCS_ENTRIES
);
245 DRM_DEBUG("intel_logical_ring_begin failed %d\n", ret
);
249 intel_logical_ring_emit(ringbuf
,
250 MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES
/ 2));
252 for (i
= 0, count
= 0; i
< table
->size
/ 2; i
++, count
+= 2) {
253 value
= (table
->table
[count
].l3cc_value
& 0xffff) |
254 ((table
->table
[count
+ 1].l3cc_value
& 0xffff) << 16);
256 intel_logical_ring_emit(ringbuf
, GEN9_LNCFCMOCS0
+ i
* 4);
257 intel_logical_ring_emit(ringbuf
, value
);
260 if (table
->size
& 0x01) {
261 /* Odd table size - 1 left over */
262 value
= (table
->table
[count
].l3cc_value
& 0xffff) |
263 ((table
->table
[0].l3cc_value
& 0xffff) << 16);
268 * Now set the rest of the table to uncached - use entry 0 as
269 * this will be uncached. Leave the last pair uninitialised as
270 * they are reserved by the hardware.
272 for (; i
< GEN9_NUM_MOCS_ENTRIES
/ 2; i
++) {
273 intel_logical_ring_emit(ringbuf
, GEN9_LNCFCMOCS0
+ i
* 4);
274 intel_logical_ring_emit(ringbuf
, value
);
279 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
280 intel_logical_ring_advance(ringbuf
);
286 * intel_rcs_context_init_mocs() - program the MOCS register.
287 * @req: Request to set up the MOCS tables for.
289 * This function will emit a batch buffer with the values required for
290 * programming the MOCS register values for all the currently supported
293 * These registers are partially stored in the RCS context, so they are
294 * emitted at the same time so that when a context is created these registers
295 * are set up. These registers have to be emitted into the start of the
296 * context as setting the ELSP will re-init some of these registers back
299 * Return: 0 on success, otherwise the error status.
301 int intel_rcs_context_init_mocs(struct drm_i915_gem_request
*req
)
303 struct drm_i915_mocs_table t
;
306 if (get_mocs_settings(req
->ring
->dev
, &t
)) {
307 /* Program the control registers */
308 ret
= emit_mocs_control_table(req
, &t
, GEN9_GFX_MOCS_0
);
312 ret
= emit_mocs_control_table(req
, &t
, GEN9_MFX0_MOCS_0
);
316 ret
= emit_mocs_control_table(req
, &t
, GEN9_MFX1_MOCS_0
);
320 ret
= emit_mocs_control_table(req
, &t
, GEN9_VEBOX_MOCS_0
);
324 ret
= emit_mocs_control_table(req
, &t
, GEN9_BLT_MOCS_0
);
328 /* Now program the l3cc registers */
329 ret
= emit_mocs_l3cc_table(req
, &t
);