4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Daniel Vetter <daniel@ffwll.ch>
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
29 #include <drm/i915_drm.h>
32 #include "intel_drv.h"
34 /* Limits for overlay size. According to intel doc, the real limits are:
35 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
36 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
37 * the mininum of both. */
38 #define IMAGE_MAX_WIDTH 2048
39 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
40 /* on 830 and 845 these large limits result in the card hanging */
41 #define IMAGE_MAX_WIDTH_LEGACY 1024
42 #define IMAGE_MAX_HEIGHT_LEGACY 1088
44 /* overlay register definitions */
46 #define OCMD_TILED_SURFACE (0x1<<19)
47 #define OCMD_MIRROR_MASK (0x3<<17)
48 #define OCMD_MIRROR_MODE (0x3<<17)
49 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
50 #define OCMD_MIRROR_VERTICAL (0x2<<17)
51 #define OCMD_MIRROR_BOTH (0x3<<17)
52 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
53 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
54 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
55 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
56 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
57 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
58 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
59 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
60 #define OCMD_YUV_422_PACKED (0x8<<10)
61 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
62 #define OCMD_YUV_420_PLANAR (0xc<<10)
63 #define OCMD_YUV_422_PLANAR (0xd<<10)
64 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
65 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
66 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
67 #define OCMD_BUF_TYPE_MASK (0x1<<5)
68 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
69 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
70 #define OCMD_TEST_MODE (0x1<<4)
71 #define OCMD_BUFFER_SELECT (0x3<<2)
72 #define OCMD_BUFFER0 (0x0<<2)
73 #define OCMD_BUFFER1 (0x1<<2)
74 #define OCMD_FIELD_SELECT (0x1<<2)
75 #define OCMD_FIELD0 (0x0<<1)
76 #define OCMD_FIELD1 (0x1<<1)
77 #define OCMD_ENABLE (0x1<<0)
79 /* OCONFIG register */
80 #define OCONF_PIPE_MASK (0x1<<18)
81 #define OCONF_PIPE_A (0x0<<18)
82 #define OCONF_PIPE_B (0x1<<18)
83 #define OCONF_GAMMA2_ENABLE (0x1<<16)
84 #define OCONF_CSC_MODE_BT601 (0x0<<5)
85 #define OCONF_CSC_MODE_BT709 (0x1<<5)
86 #define OCONF_CSC_BYPASS (0x1<<4)
87 #define OCONF_CC_OUT_8BIT (0x1<<3)
88 #define OCONF_TEST_MODE (0x1<<2)
89 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
90 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
92 /* DCLRKM (dst-key) register */
93 #define DST_KEY_ENABLE (0x1<<31)
94 #define CLK_RGB24_MASK 0x0
95 #define CLK_RGB16_MASK 0x070307
96 #define CLK_RGB15_MASK 0x070707
97 #define CLK_RGB8I_MASK 0xffffff
99 #define RGB16_TO_COLORKEY(c) \
100 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
101 #define RGB15_TO_COLORKEY(c) \
102 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
104 /* overlay flip addr flag */
105 #define OFC_UPDATE 0x1
107 /* polyphase filter coefficients */
108 #define N_HORIZ_Y_TAPS 5
109 #define N_VERT_Y_TAPS 3
110 #define N_HORIZ_UV_TAPS 3
111 #define N_VERT_UV_TAPS 3
115 /* memory bufferd overlay registers */
116 struct overlay_registers
{
144 u32 RESERVED1
; /* 0x6C */
157 u32 FASTHSCALE
; /* 0xA0 */
158 u32 UVSCALEV
; /* 0xA4 */
159 u32 RESERVEDC
[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
160 u16 Y_VCOEFS
[N_VERT_Y_TAPS
* N_PHASES
]; /* 0x200 */
161 u16 RESERVEDD
[0x100 / 2 - N_VERT_Y_TAPS
* N_PHASES
];
162 u16 Y_HCOEFS
[N_HORIZ_Y_TAPS
* N_PHASES
]; /* 0x300 */
163 u16 RESERVEDE
[0x200 / 2 - N_HORIZ_Y_TAPS
* N_PHASES
];
164 u16 UV_VCOEFS
[N_VERT_UV_TAPS
* N_PHASES
]; /* 0x500 */
165 u16 RESERVEDF
[0x100 / 2 - N_VERT_UV_TAPS
* N_PHASES
];
166 u16 UV_HCOEFS
[N_HORIZ_UV_TAPS
* N_PHASES
]; /* 0x600 */
167 u16 RESERVEDG
[0x100 / 2 - N_HORIZ_UV_TAPS
* N_PHASES
];
170 struct intel_overlay
{
171 struct drm_i915_private
*i915
;
172 struct intel_crtc
*crtc
;
173 struct drm_i915_gem_object
*vid_bo
;
174 struct drm_i915_gem_object
*old_vid_bo
;
177 u32 pfit_vscale_ratio
; /* shifted-point number, (1<<12) == 1.0 */
179 u32 color_key_enabled
:1;
180 u32 brightness
, contrast
, saturation
;
181 u32 old_xscale
, old_yscale
;
182 /* register access */
184 struct drm_i915_gem_object
*reg_bo
;
186 struct drm_i915_gem_request
*last_flip_req
;
187 void (*flip_tail
)(struct intel_overlay
*);
190 static struct overlay_registers __iomem
*
191 intel_overlay_map_regs(struct intel_overlay
*overlay
)
193 struct drm_i915_private
*dev_priv
= overlay
->i915
;
194 struct overlay_registers __iomem
*regs
;
196 if (OVERLAY_NEEDS_PHYSICAL(dev_priv
))
197 regs
= (struct overlay_registers __iomem
*)overlay
->reg_bo
->phys_handle
->vaddr
;
199 regs
= io_mapping_map_wc(dev_priv
->ggtt
.mappable
,
206 static void intel_overlay_unmap_regs(struct intel_overlay
*overlay
,
207 struct overlay_registers __iomem
*regs
)
209 if (!OVERLAY_NEEDS_PHYSICAL(overlay
->i915
))
210 io_mapping_unmap(regs
);
213 static int intel_overlay_do_wait_request(struct intel_overlay
*overlay
,
214 struct drm_i915_gem_request
*req
,
215 void (*tail
)(struct intel_overlay
*))
219 WARN_ON(overlay
->last_flip_req
);
220 i915_gem_request_assign(&overlay
->last_flip_req
, req
);
221 i915_add_request(req
);
223 overlay
->flip_tail
= tail
;
224 ret
= i915_wait_request(overlay
->last_flip_req
);
228 i915_gem_request_assign(&overlay
->last_flip_req
, NULL
);
232 /* overlay needs to be disable in OCMD reg */
233 static int intel_overlay_on(struct intel_overlay
*overlay
)
235 struct drm_i915_private
*dev_priv
= overlay
->i915
;
236 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
237 struct drm_i915_gem_request
*req
;
240 WARN_ON(overlay
->active
);
241 WARN_ON(IS_I830(dev_priv
) && !(dev_priv
->quirks
& QUIRK_PIPEA_FORCE
));
243 req
= i915_gem_request_alloc(engine
, NULL
);
247 ret
= intel_ring_begin(req
, 4);
249 i915_add_request_no_flush(req
);
253 overlay
->active
= true;
255 intel_ring_emit(engine
, MI_OVERLAY_FLIP
| MI_OVERLAY_ON
);
256 intel_ring_emit(engine
, overlay
->flip_addr
| OFC_UPDATE
);
257 intel_ring_emit(engine
, MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
258 intel_ring_emit(engine
, MI_NOOP
);
259 intel_ring_advance(engine
);
261 return intel_overlay_do_wait_request(overlay
, req
, NULL
);
264 /* overlay needs to be enabled in OCMD reg */
265 static int intel_overlay_continue(struct intel_overlay
*overlay
,
266 bool load_polyphase_filter
)
268 struct drm_i915_private
*dev_priv
= overlay
->i915
;
269 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
270 struct drm_i915_gem_request
*req
;
271 u32 flip_addr
= overlay
->flip_addr
;
275 WARN_ON(!overlay
->active
);
277 if (load_polyphase_filter
)
278 flip_addr
|= OFC_UPDATE
;
280 /* check for underruns */
281 tmp
= I915_READ(DOVSTA
);
283 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp
);
285 req
= i915_gem_request_alloc(engine
, NULL
);
289 ret
= intel_ring_begin(req
, 2);
291 i915_add_request_no_flush(req
);
295 intel_ring_emit(engine
, MI_OVERLAY_FLIP
| MI_OVERLAY_CONTINUE
);
296 intel_ring_emit(engine
, flip_addr
);
297 intel_ring_advance(engine
);
299 WARN_ON(overlay
->last_flip_req
);
300 i915_gem_request_assign(&overlay
->last_flip_req
, req
);
301 i915_add_request(req
);
306 static void intel_overlay_release_old_vid_tail(struct intel_overlay
*overlay
)
308 struct drm_i915_gem_object
*obj
= overlay
->old_vid_bo
;
310 i915_gem_object_ggtt_unpin(obj
);
311 drm_gem_object_unreference(&obj
->base
);
313 overlay
->old_vid_bo
= NULL
;
316 static void intel_overlay_off_tail(struct intel_overlay
*overlay
)
318 struct drm_i915_gem_object
*obj
= overlay
->vid_bo
;
320 /* never have the overlay hw on without showing a frame */
324 i915_gem_object_ggtt_unpin(obj
);
325 drm_gem_object_unreference(&obj
->base
);
326 overlay
->vid_bo
= NULL
;
328 overlay
->crtc
->overlay
= NULL
;
329 overlay
->crtc
= NULL
;
330 overlay
->active
= false;
333 /* overlay needs to be disabled in OCMD reg */
334 static int intel_overlay_off(struct intel_overlay
*overlay
)
336 struct drm_i915_private
*dev_priv
= overlay
->i915
;
337 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
338 struct drm_i915_gem_request
*req
;
339 u32 flip_addr
= overlay
->flip_addr
;
342 WARN_ON(!overlay
->active
);
344 /* According to intel docs the overlay hw may hang (when switching
345 * off) without loading the filter coeffs. It is however unclear whether
346 * this applies to the disabling of the overlay or to the switching off
347 * of the hw. Do it in both cases */
348 flip_addr
|= OFC_UPDATE
;
350 req
= i915_gem_request_alloc(engine
, NULL
);
354 ret
= intel_ring_begin(req
, 6);
356 i915_add_request_no_flush(req
);
360 /* wait for overlay to go idle */
361 intel_ring_emit(engine
, MI_OVERLAY_FLIP
| MI_OVERLAY_CONTINUE
);
362 intel_ring_emit(engine
, flip_addr
);
363 intel_ring_emit(engine
, MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
364 /* turn overlay off */
365 if (IS_I830(dev_priv
)) {
366 /* Workaround: Don't disable the overlay fully, since otherwise
367 * it dies on the next OVERLAY_ON cmd. */
368 intel_ring_emit(engine
, MI_NOOP
);
369 intel_ring_emit(engine
, MI_NOOP
);
370 intel_ring_emit(engine
, MI_NOOP
);
372 intel_ring_emit(engine
, MI_OVERLAY_FLIP
| MI_OVERLAY_OFF
);
373 intel_ring_emit(engine
, flip_addr
);
374 intel_ring_emit(engine
,
375 MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
377 intel_ring_advance(engine
);
379 return intel_overlay_do_wait_request(overlay
, req
, intel_overlay_off_tail
);
382 /* recover from an interruption due to a signal
383 * We have to be careful not to repeat work forever an make forward progess. */
384 static int intel_overlay_recover_from_interrupt(struct intel_overlay
*overlay
)
388 if (overlay
->last_flip_req
== NULL
)
391 ret
= i915_wait_request(overlay
->last_flip_req
);
395 if (overlay
->flip_tail
)
396 overlay
->flip_tail(overlay
);
398 i915_gem_request_assign(&overlay
->last_flip_req
, NULL
);
402 /* Wait for pending overlay flip and release old frame.
403 * Needs to be called before the overlay register are changed
404 * via intel_overlay_(un)map_regs
406 static int intel_overlay_release_old_vid(struct intel_overlay
*overlay
)
408 struct drm_i915_private
*dev_priv
= overlay
->i915
;
409 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
412 lockdep_assert_held(&dev_priv
->dev
->struct_mutex
);
414 /* Only wait if there is actually an old frame to release to
415 * guarantee forward progress.
417 if (!overlay
->old_vid_bo
)
420 if (I915_READ(ISR
) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT
) {
421 /* synchronous slowpath */
422 struct drm_i915_gem_request
*req
;
424 req
= i915_gem_request_alloc(engine
, NULL
);
428 ret
= intel_ring_begin(req
, 2);
430 i915_add_request_no_flush(req
);
434 intel_ring_emit(engine
,
435 MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
436 intel_ring_emit(engine
, MI_NOOP
);
437 intel_ring_advance(engine
);
439 ret
= intel_overlay_do_wait_request(overlay
, req
,
440 intel_overlay_release_old_vid_tail
);
445 intel_overlay_release_old_vid_tail(overlay
);
448 i915_gem_track_fb(overlay
->old_vid_bo
, NULL
,
449 INTEL_FRONTBUFFER_OVERLAY(overlay
->crtc
->pipe
));
453 void intel_overlay_reset(struct drm_i915_private
*dev_priv
)
455 struct intel_overlay
*overlay
= dev_priv
->overlay
;
460 intel_overlay_release_old_vid(overlay
);
462 overlay
->last_flip_req
= NULL
;
463 overlay
->old_xscale
= 0;
464 overlay
->old_yscale
= 0;
465 overlay
->crtc
= NULL
;
466 overlay
->active
= false;
469 struct put_image_params
{
486 static int packed_depth_bytes(u32 format
)
488 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
489 case I915_OVERLAY_YUV422
:
491 case I915_OVERLAY_YUV411
:
492 /* return 6; not implemented */
498 static int packed_width_bytes(u32 format
, short width
)
500 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
501 case I915_OVERLAY_YUV422
:
508 static int uv_hsubsampling(u32 format
)
510 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
511 case I915_OVERLAY_YUV422
:
512 case I915_OVERLAY_YUV420
:
514 case I915_OVERLAY_YUV411
:
515 case I915_OVERLAY_YUV410
:
522 static int uv_vsubsampling(u32 format
)
524 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
525 case I915_OVERLAY_YUV420
:
526 case I915_OVERLAY_YUV410
:
528 case I915_OVERLAY_YUV422
:
529 case I915_OVERLAY_YUV411
:
536 static u32
calc_swidthsw(struct drm_i915_private
*dev_priv
, u32 offset
, u32 width
)
538 u32 mask
, shift
, ret
;
539 if (IS_GEN2(dev_priv
)) {
546 ret
= ((offset
+ width
+ mask
) >> shift
) - (offset
>> shift
);
547 if (!IS_GEN2(dev_priv
))
553 static const u16 y_static_hcoeffs
[N_HORIZ_Y_TAPS
* N_PHASES
] = {
554 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
555 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
556 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
557 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
558 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
559 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
560 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
561 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
562 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
563 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
564 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
565 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
566 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
567 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
568 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
569 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
570 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
573 static const u16 uv_static_hcoeffs
[N_HORIZ_UV_TAPS
* N_PHASES
] = {
574 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
575 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
576 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
577 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
578 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
579 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
580 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
581 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
582 0x3000, 0x0800, 0x3000
585 static void update_polyphase_filter(struct overlay_registers __iomem
*regs
)
587 memcpy_toio(regs
->Y_HCOEFS
, y_static_hcoeffs
, sizeof(y_static_hcoeffs
));
588 memcpy_toio(regs
->UV_HCOEFS
, uv_static_hcoeffs
,
589 sizeof(uv_static_hcoeffs
));
592 static bool update_scaling_factors(struct intel_overlay
*overlay
,
593 struct overlay_registers __iomem
*regs
,
594 struct put_image_params
*params
)
596 /* fixed point with a 12 bit shift */
597 u32 xscale
, yscale
, xscale_UV
, yscale_UV
;
599 #define FRACT_MASK 0xfff
600 bool scale_changed
= false;
601 int uv_hscale
= uv_hsubsampling(params
->format
);
602 int uv_vscale
= uv_vsubsampling(params
->format
);
604 if (params
->dst_w
> 1)
605 xscale
= ((params
->src_scan_w
- 1) << FP_SHIFT
)
608 xscale
= 1 << FP_SHIFT
;
610 if (params
->dst_h
> 1)
611 yscale
= ((params
->src_scan_h
- 1) << FP_SHIFT
)
614 yscale
= 1 << FP_SHIFT
;
616 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
617 xscale_UV
= xscale
/uv_hscale
;
618 yscale_UV
= yscale
/uv_vscale
;
619 /* make the Y scale to UV scale ratio an exact multiply */
620 xscale
= xscale_UV
* uv_hscale
;
621 yscale
= yscale_UV
* uv_vscale
;
627 if (xscale
!= overlay
->old_xscale
|| yscale
!= overlay
->old_yscale
)
628 scale_changed
= true;
629 overlay
->old_xscale
= xscale
;
630 overlay
->old_yscale
= yscale
;
632 iowrite32(((yscale
& FRACT_MASK
) << 20) |
633 ((xscale
>> FP_SHIFT
) << 16) |
634 ((xscale
& FRACT_MASK
) << 3),
637 iowrite32(((yscale_UV
& FRACT_MASK
) << 20) |
638 ((xscale_UV
>> FP_SHIFT
) << 16) |
639 ((xscale_UV
& FRACT_MASK
) << 3),
642 iowrite32((((yscale
>> FP_SHIFT
) << 16) |
643 ((yscale_UV
>> FP_SHIFT
) << 0)),
647 update_polyphase_filter(regs
);
649 return scale_changed
;
652 static void update_colorkey(struct intel_overlay
*overlay
,
653 struct overlay_registers __iomem
*regs
)
655 u32 key
= overlay
->color_key
;
659 if (overlay
->color_key_enabled
)
660 flags
|= DST_KEY_ENABLE
;
662 switch (overlay
->crtc
->base
.primary
->fb
->bits_per_pixel
) {
665 flags
|= CLK_RGB8I_MASK
;
669 if (overlay
->crtc
->base
.primary
->fb
->depth
== 15) {
670 key
= RGB15_TO_COLORKEY(key
);
671 flags
|= CLK_RGB15_MASK
;
673 key
= RGB16_TO_COLORKEY(key
);
674 flags
|= CLK_RGB16_MASK
;
680 flags
|= CLK_RGB24_MASK
;
684 iowrite32(key
, ®s
->DCLRKV
);
685 iowrite32(flags
, ®s
->DCLRKM
);
688 static u32
overlay_cmd_reg(struct put_image_params
*params
)
690 u32 cmd
= OCMD_ENABLE
| OCMD_BUF_TYPE_FRAME
| OCMD_BUFFER0
;
692 if (params
->format
& I915_OVERLAY_YUV_PLANAR
) {
693 switch (params
->format
& I915_OVERLAY_DEPTH_MASK
) {
694 case I915_OVERLAY_YUV422
:
695 cmd
|= OCMD_YUV_422_PLANAR
;
697 case I915_OVERLAY_YUV420
:
698 cmd
|= OCMD_YUV_420_PLANAR
;
700 case I915_OVERLAY_YUV411
:
701 case I915_OVERLAY_YUV410
:
702 cmd
|= OCMD_YUV_410_PLANAR
;
705 } else { /* YUV packed */
706 switch (params
->format
& I915_OVERLAY_DEPTH_MASK
) {
707 case I915_OVERLAY_YUV422
:
708 cmd
|= OCMD_YUV_422_PACKED
;
710 case I915_OVERLAY_YUV411
:
711 cmd
|= OCMD_YUV_411_PACKED
;
715 switch (params
->format
& I915_OVERLAY_SWAP_MASK
) {
716 case I915_OVERLAY_NO_SWAP
:
718 case I915_OVERLAY_UV_SWAP
:
721 case I915_OVERLAY_Y_SWAP
:
724 case I915_OVERLAY_Y_AND_UV_SWAP
:
725 cmd
|= OCMD_Y_AND_UV_SWAP
;
733 static int intel_overlay_do_put_image(struct intel_overlay
*overlay
,
734 struct drm_i915_gem_object
*new_bo
,
735 struct put_image_params
*params
)
738 struct overlay_registers __iomem
*regs
;
739 bool scale_changed
= false;
740 struct drm_i915_private
*dev_priv
= overlay
->i915
;
741 u32 swidth
, swidthsw
, sheight
, ostride
;
742 enum pipe pipe
= overlay
->crtc
->pipe
;
744 lockdep_assert_held(&dev_priv
->dev
->struct_mutex
);
745 WARN_ON(!drm_modeset_is_locked(&dev_priv
->dev
->mode_config
.connection_mutex
));
747 ret
= intel_overlay_release_old_vid(overlay
);
751 ret
= i915_gem_object_pin_to_display_plane(new_bo
, 0,
752 &i915_ggtt_view_normal
);
756 ret
= i915_gem_object_put_fence(new_bo
);
760 if (!overlay
->active
) {
762 regs
= intel_overlay_map_regs(overlay
);
767 oconfig
= OCONF_CC_OUT_8BIT
;
768 if (IS_GEN4(dev_priv
))
769 oconfig
|= OCONF_CSC_MODE_BT709
;
770 oconfig
|= pipe
== 0 ?
771 OCONF_PIPE_A
: OCONF_PIPE_B
;
772 iowrite32(oconfig
, ®s
->OCONFIG
);
773 intel_overlay_unmap_regs(overlay
, regs
);
775 ret
= intel_overlay_on(overlay
);
780 regs
= intel_overlay_map_regs(overlay
);
786 iowrite32((params
->dst_y
<< 16) | params
->dst_x
, ®s
->DWINPOS
);
787 iowrite32((params
->dst_h
<< 16) | params
->dst_w
, ®s
->DWINSZ
);
789 if (params
->format
& I915_OVERLAY_YUV_PACKED
)
790 tmp_width
= packed_width_bytes(params
->format
, params
->src_w
);
792 tmp_width
= params
->src_w
;
794 swidth
= params
->src_w
;
795 swidthsw
= calc_swidthsw(dev_priv
, params
->offset_Y
, tmp_width
);
796 sheight
= params
->src_h
;
797 iowrite32(i915_gem_obj_ggtt_offset(new_bo
) + params
->offset_Y
, ®s
->OBUF_0Y
);
798 ostride
= params
->stride_Y
;
800 if (params
->format
& I915_OVERLAY_YUV_PLANAR
) {
801 int uv_hscale
= uv_hsubsampling(params
->format
);
802 int uv_vscale
= uv_vsubsampling(params
->format
);
804 swidth
|= (params
->src_w
/uv_hscale
) << 16;
805 tmp_U
= calc_swidthsw(dev_priv
, params
->offset_U
,
806 params
->src_w
/uv_hscale
);
807 tmp_V
= calc_swidthsw(dev_priv
, params
->offset_V
,
808 params
->src_w
/uv_hscale
);
809 swidthsw
|= max_t(u32
, tmp_U
, tmp_V
) << 16;
810 sheight
|= (params
->src_h
/uv_vscale
) << 16;
811 iowrite32(i915_gem_obj_ggtt_offset(new_bo
) + params
->offset_U
, ®s
->OBUF_0U
);
812 iowrite32(i915_gem_obj_ggtt_offset(new_bo
) + params
->offset_V
, ®s
->OBUF_0V
);
813 ostride
|= params
->stride_UV
<< 16;
816 iowrite32(swidth
, ®s
->SWIDTH
);
817 iowrite32(swidthsw
, ®s
->SWIDTHSW
);
818 iowrite32(sheight
, ®s
->SHEIGHT
);
819 iowrite32(ostride
, ®s
->OSTRIDE
);
821 scale_changed
= update_scaling_factors(overlay
, regs
, params
);
823 update_colorkey(overlay
, regs
);
825 iowrite32(overlay_cmd_reg(params
), ®s
->OCMD
);
827 intel_overlay_unmap_regs(overlay
, regs
);
829 ret
= intel_overlay_continue(overlay
, scale_changed
);
833 i915_gem_track_fb(overlay
->vid_bo
, new_bo
,
834 INTEL_FRONTBUFFER_OVERLAY(pipe
));
836 overlay
->old_vid_bo
= overlay
->vid_bo
;
837 overlay
->vid_bo
= new_bo
;
839 intel_frontbuffer_flip(dev_priv
->dev
, INTEL_FRONTBUFFER_OVERLAY(pipe
));
844 i915_gem_object_ggtt_unpin(new_bo
);
848 int intel_overlay_switch_off(struct intel_overlay
*overlay
)
850 struct drm_i915_private
*dev_priv
= overlay
->i915
;
851 struct overlay_registers __iomem
*regs
;
854 lockdep_assert_held(&dev_priv
->dev
->struct_mutex
);
855 WARN_ON(!drm_modeset_is_locked(&dev_priv
->dev
->mode_config
.connection_mutex
));
857 ret
= intel_overlay_recover_from_interrupt(overlay
);
861 if (!overlay
->active
)
864 ret
= intel_overlay_release_old_vid(overlay
);
868 regs
= intel_overlay_map_regs(overlay
);
869 iowrite32(0, ®s
->OCMD
);
870 intel_overlay_unmap_regs(overlay
, regs
);
872 ret
= intel_overlay_off(overlay
);
876 intel_overlay_off_tail(overlay
);
880 static int check_overlay_possible_on_crtc(struct intel_overlay
*overlay
,
881 struct intel_crtc
*crtc
)
886 /* can't use the overlay with double wide pipe */
887 if (crtc
->config
->double_wide
)
893 static void update_pfit_vscale_ratio(struct intel_overlay
*overlay
)
895 struct drm_i915_private
*dev_priv
= overlay
->i915
;
896 u32 pfit_control
= I915_READ(PFIT_CONTROL
);
899 /* XXX: This is not the same logic as in the xorg driver, but more in
900 * line with the intel documentation for the i965
902 if (INTEL_GEN(dev_priv
) >= 4) {
903 /* on i965 use the PGM reg to read out the autoscaler values */
904 ratio
= I915_READ(PFIT_PGM_RATIOS
) >> PFIT_VERT_SCALE_SHIFT_965
;
906 if (pfit_control
& VERT_AUTO_SCALE
)
907 ratio
= I915_READ(PFIT_AUTO_RATIOS
);
909 ratio
= I915_READ(PFIT_PGM_RATIOS
);
910 ratio
>>= PFIT_VERT_SCALE_SHIFT
;
913 overlay
->pfit_vscale_ratio
= ratio
;
916 static int check_overlay_dst(struct intel_overlay
*overlay
,
917 struct drm_intel_overlay_put_image
*rec
)
919 struct drm_display_mode
*mode
= &overlay
->crtc
->base
.mode
;
921 if (rec
->dst_x
< mode
->hdisplay
&&
922 rec
->dst_x
+ rec
->dst_width
<= mode
->hdisplay
&&
923 rec
->dst_y
< mode
->vdisplay
&&
924 rec
->dst_y
+ rec
->dst_height
<= mode
->vdisplay
)
930 static int check_overlay_scaling(struct put_image_params
*rec
)
934 /* downscaling limit is 8.0 */
935 tmp
= ((rec
->src_scan_h
<< 16) / rec
->dst_h
) >> 16;
938 tmp
= ((rec
->src_scan_w
<< 16) / rec
->dst_w
) >> 16;
945 static int check_overlay_src(struct drm_i915_private
*dev_priv
,
946 struct drm_intel_overlay_put_image
*rec
,
947 struct drm_i915_gem_object
*new_bo
)
949 int uv_hscale
= uv_hsubsampling(rec
->flags
);
950 int uv_vscale
= uv_vsubsampling(rec
->flags
);
955 /* check src dimensions */
956 if (IS_845G(dev_priv
) || IS_I830(dev_priv
)) {
957 if (rec
->src_height
> IMAGE_MAX_HEIGHT_LEGACY
||
958 rec
->src_width
> IMAGE_MAX_WIDTH_LEGACY
)
961 if (rec
->src_height
> IMAGE_MAX_HEIGHT
||
962 rec
->src_width
> IMAGE_MAX_WIDTH
)
966 /* better safe than sorry, use 4 as the maximal subsampling ratio */
967 if (rec
->src_height
< N_VERT_Y_TAPS
*4 ||
968 rec
->src_width
< N_HORIZ_Y_TAPS
*4)
971 /* check alignment constraints */
972 switch (rec
->flags
& I915_OVERLAY_TYPE_MASK
) {
973 case I915_OVERLAY_RGB
:
974 /* not implemented */
977 case I915_OVERLAY_YUV_PACKED
:
981 depth
= packed_depth_bytes(rec
->flags
);
985 /* ignore UV planes */
989 /* check pixel alignment */
990 if (rec
->offset_Y
% depth
)
994 case I915_OVERLAY_YUV_PLANAR
:
995 if (uv_vscale
< 0 || uv_hscale
< 0)
997 /* no offset restrictions for planar formats */
1004 if (rec
->src_width
% uv_hscale
)
1007 /* stride checking */
1008 if (IS_I830(dev_priv
) || IS_845G(dev_priv
))
1013 if (rec
->stride_Y
& stride_mask
|| rec
->stride_UV
& stride_mask
)
1015 if (IS_GEN4(dev_priv
) && rec
->stride_Y
< 512)
1018 tmp
= (rec
->flags
& I915_OVERLAY_TYPE_MASK
) == I915_OVERLAY_YUV_PLANAR
?
1020 if (rec
->stride_Y
> tmp
|| rec
->stride_UV
> 2*1024)
1023 /* check buffer dimensions */
1024 switch (rec
->flags
& I915_OVERLAY_TYPE_MASK
) {
1025 case I915_OVERLAY_RGB
:
1026 case I915_OVERLAY_YUV_PACKED
:
1027 /* always 4 Y values per depth pixels */
1028 if (packed_width_bytes(rec
->flags
, rec
->src_width
) > rec
->stride_Y
)
1031 tmp
= rec
->stride_Y
*rec
->src_height
;
1032 if (rec
->offset_Y
+ tmp
> new_bo
->base
.size
)
1036 case I915_OVERLAY_YUV_PLANAR
:
1037 if (rec
->src_width
> rec
->stride_Y
)
1039 if (rec
->src_width
/uv_hscale
> rec
->stride_UV
)
1042 tmp
= rec
->stride_Y
* rec
->src_height
;
1043 if (rec
->offset_Y
+ tmp
> new_bo
->base
.size
)
1046 tmp
= rec
->stride_UV
* (rec
->src_height
/ uv_vscale
);
1047 if (rec
->offset_U
+ tmp
> new_bo
->base
.size
||
1048 rec
->offset_V
+ tmp
> new_bo
->base
.size
)
1057 * Return the pipe currently connected to the panel fitter,
1058 * or -1 if the panel fitter is not present or not in use
1060 static int intel_panel_fitter_pipe(struct drm_i915_private
*dev_priv
)
1064 /* i830 doesn't have a panel fitter */
1065 if (INTEL_GEN(dev_priv
) <= 3 &&
1066 (IS_I830(dev_priv
) || !IS_MOBILE(dev_priv
)))
1069 pfit_control
= I915_READ(PFIT_CONTROL
);
1071 /* See if the panel fitter is in use */
1072 if ((pfit_control
& PFIT_ENABLE
) == 0)
1075 /* 965 can place panel fitter on either pipe */
1076 if (IS_GEN4(dev_priv
))
1077 return (pfit_control
>> 29) & 0x3;
1079 /* older chips can only use pipe 1 */
1083 int intel_overlay_put_image_ioctl(struct drm_device
*dev
, void *data
,
1084 struct drm_file
*file_priv
)
1086 struct drm_intel_overlay_put_image
*put_image_rec
= data
;
1087 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1088 struct intel_overlay
*overlay
;
1089 struct drm_crtc
*drmmode_crtc
;
1090 struct intel_crtc
*crtc
;
1091 struct drm_i915_gem_object
*new_bo
;
1092 struct put_image_params
*params
;
1095 overlay
= dev_priv
->overlay
;
1097 DRM_DEBUG("userspace bug: no overlay\n");
1101 if (!(put_image_rec
->flags
& I915_OVERLAY_ENABLE
)) {
1102 drm_modeset_lock_all(dev
);
1103 mutex_lock(&dev
->struct_mutex
);
1105 ret
= intel_overlay_switch_off(overlay
);
1107 mutex_unlock(&dev
->struct_mutex
);
1108 drm_modeset_unlock_all(dev
);
1113 params
= kmalloc(sizeof(*params
), GFP_KERNEL
);
1117 drmmode_crtc
= drm_crtc_find(dev
, put_image_rec
->crtc_id
);
1118 if (!drmmode_crtc
) {
1122 crtc
= to_intel_crtc(drmmode_crtc
);
1124 new_bo
= to_intel_bo(drm_gem_object_lookup(file_priv
,
1125 put_image_rec
->bo_handle
));
1126 if (&new_bo
->base
== NULL
) {
1131 drm_modeset_lock_all(dev
);
1132 mutex_lock(&dev
->struct_mutex
);
1134 if (new_bo
->tiling_mode
) {
1135 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n");
1140 ret
= intel_overlay_recover_from_interrupt(overlay
);
1144 if (overlay
->crtc
!= crtc
) {
1145 struct drm_display_mode
*mode
= &crtc
->base
.mode
;
1146 ret
= intel_overlay_switch_off(overlay
);
1150 ret
= check_overlay_possible_on_crtc(overlay
, crtc
);
1154 overlay
->crtc
= crtc
;
1155 crtc
->overlay
= overlay
;
1157 /* line too wide, i.e. one-line-mode */
1158 if (mode
->hdisplay
> 1024 &&
1159 intel_panel_fitter_pipe(dev_priv
) == crtc
->pipe
) {
1160 overlay
->pfit_active
= true;
1161 update_pfit_vscale_ratio(overlay
);
1163 overlay
->pfit_active
= false;
1166 ret
= check_overlay_dst(overlay
, put_image_rec
);
1170 if (overlay
->pfit_active
) {
1171 params
->dst_y
= ((((u32
)put_image_rec
->dst_y
) << 12) /
1172 overlay
->pfit_vscale_ratio
);
1173 /* shifting right rounds downwards, so add 1 */
1174 params
->dst_h
= ((((u32
)put_image_rec
->dst_height
) << 12) /
1175 overlay
->pfit_vscale_ratio
) + 1;
1177 params
->dst_y
= put_image_rec
->dst_y
;
1178 params
->dst_h
= put_image_rec
->dst_height
;
1180 params
->dst_x
= put_image_rec
->dst_x
;
1181 params
->dst_w
= put_image_rec
->dst_width
;
1183 params
->src_w
= put_image_rec
->src_width
;
1184 params
->src_h
= put_image_rec
->src_height
;
1185 params
->src_scan_w
= put_image_rec
->src_scan_width
;
1186 params
->src_scan_h
= put_image_rec
->src_scan_height
;
1187 if (params
->src_scan_h
> params
->src_h
||
1188 params
->src_scan_w
> params
->src_w
) {
1193 ret
= check_overlay_src(dev_priv
, put_image_rec
, new_bo
);
1196 params
->format
= put_image_rec
->flags
& ~I915_OVERLAY_FLAGS_MASK
;
1197 params
->stride_Y
= put_image_rec
->stride_Y
;
1198 params
->stride_UV
= put_image_rec
->stride_UV
;
1199 params
->offset_Y
= put_image_rec
->offset_Y
;
1200 params
->offset_U
= put_image_rec
->offset_U
;
1201 params
->offset_V
= put_image_rec
->offset_V
;
1203 /* Check scaling after src size to prevent a divide-by-zero. */
1204 ret
= check_overlay_scaling(params
);
1208 ret
= intel_overlay_do_put_image(overlay
, new_bo
, params
);
1212 mutex_unlock(&dev
->struct_mutex
);
1213 drm_modeset_unlock_all(dev
);
1220 mutex_unlock(&dev
->struct_mutex
);
1221 drm_modeset_unlock_all(dev
);
1222 drm_gem_object_unreference_unlocked(&new_bo
->base
);
1229 static void update_reg_attrs(struct intel_overlay
*overlay
,
1230 struct overlay_registers __iomem
*regs
)
1232 iowrite32((overlay
->contrast
<< 18) | (overlay
->brightness
& 0xff),
1234 iowrite32(overlay
->saturation
, ®s
->OCLRC1
);
1237 static bool check_gamma_bounds(u32 gamma1
, u32 gamma2
)
1241 if (gamma1
& 0xff000000 || gamma2
& 0xff000000)
1244 for (i
= 0; i
< 3; i
++) {
1245 if (((gamma1
>> i
*8) & 0xff) >= ((gamma2
>> i
*8) & 0xff))
1252 static bool check_gamma5_errata(u32 gamma5
)
1256 for (i
= 0; i
< 3; i
++) {
1257 if (((gamma5
>> i
*8) & 0xff) == 0x80)
1264 static int check_gamma(struct drm_intel_overlay_attrs
*attrs
)
1266 if (!check_gamma_bounds(0, attrs
->gamma0
) ||
1267 !check_gamma_bounds(attrs
->gamma0
, attrs
->gamma1
) ||
1268 !check_gamma_bounds(attrs
->gamma1
, attrs
->gamma2
) ||
1269 !check_gamma_bounds(attrs
->gamma2
, attrs
->gamma3
) ||
1270 !check_gamma_bounds(attrs
->gamma3
, attrs
->gamma4
) ||
1271 !check_gamma_bounds(attrs
->gamma4
, attrs
->gamma5
) ||
1272 !check_gamma_bounds(attrs
->gamma5
, 0x00ffffff))
1275 if (!check_gamma5_errata(attrs
->gamma5
))
1281 int intel_overlay_attrs_ioctl(struct drm_device
*dev
, void *data
,
1282 struct drm_file
*file_priv
)
1284 struct drm_intel_overlay_attrs
*attrs
= data
;
1285 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1286 struct intel_overlay
*overlay
;
1287 struct overlay_registers __iomem
*regs
;
1290 overlay
= dev_priv
->overlay
;
1292 DRM_DEBUG("userspace bug: no overlay\n");
1296 drm_modeset_lock_all(dev
);
1297 mutex_lock(&dev
->struct_mutex
);
1300 if (!(attrs
->flags
& I915_OVERLAY_UPDATE_ATTRS
)) {
1301 attrs
->color_key
= overlay
->color_key
;
1302 attrs
->brightness
= overlay
->brightness
;
1303 attrs
->contrast
= overlay
->contrast
;
1304 attrs
->saturation
= overlay
->saturation
;
1306 if (!IS_GEN2(dev_priv
)) {
1307 attrs
->gamma0
= I915_READ(OGAMC0
);
1308 attrs
->gamma1
= I915_READ(OGAMC1
);
1309 attrs
->gamma2
= I915_READ(OGAMC2
);
1310 attrs
->gamma3
= I915_READ(OGAMC3
);
1311 attrs
->gamma4
= I915_READ(OGAMC4
);
1312 attrs
->gamma5
= I915_READ(OGAMC5
);
1315 if (attrs
->brightness
< -128 || attrs
->brightness
> 127)
1317 if (attrs
->contrast
> 255)
1319 if (attrs
->saturation
> 1023)
1322 overlay
->color_key
= attrs
->color_key
;
1323 overlay
->brightness
= attrs
->brightness
;
1324 overlay
->contrast
= attrs
->contrast
;
1325 overlay
->saturation
= attrs
->saturation
;
1327 regs
= intel_overlay_map_regs(overlay
);
1333 update_reg_attrs(overlay
, regs
);
1335 intel_overlay_unmap_regs(overlay
, regs
);
1337 if (attrs
->flags
& I915_OVERLAY_UPDATE_GAMMA
) {
1338 if (IS_GEN2(dev_priv
))
1341 if (overlay
->active
) {
1346 ret
= check_gamma(attrs
);
1350 I915_WRITE(OGAMC0
, attrs
->gamma0
);
1351 I915_WRITE(OGAMC1
, attrs
->gamma1
);
1352 I915_WRITE(OGAMC2
, attrs
->gamma2
);
1353 I915_WRITE(OGAMC3
, attrs
->gamma3
);
1354 I915_WRITE(OGAMC4
, attrs
->gamma4
);
1355 I915_WRITE(OGAMC5
, attrs
->gamma5
);
1358 overlay
->color_key_enabled
= (attrs
->flags
& I915_OVERLAY_DISABLE_DEST_COLORKEY
) == 0;
1362 mutex_unlock(&dev
->struct_mutex
);
1363 drm_modeset_unlock_all(dev
);
1368 void intel_setup_overlay(struct drm_i915_private
*dev_priv
)
1370 struct intel_overlay
*overlay
;
1371 struct drm_i915_gem_object
*reg_bo
;
1372 struct overlay_registers __iomem
*regs
;
1375 if (!HAS_OVERLAY(dev_priv
))
1378 overlay
= kzalloc(sizeof(*overlay
), GFP_KERNEL
);
1382 mutex_lock(&dev_priv
->dev
->struct_mutex
);
1383 if (WARN_ON(dev_priv
->overlay
))
1386 overlay
->i915
= dev_priv
;
1389 if (!OVERLAY_NEEDS_PHYSICAL(dev_priv
))
1390 reg_bo
= i915_gem_object_create_stolen(dev_priv
->dev
, PAGE_SIZE
);
1392 reg_bo
= i915_gem_object_create(dev_priv
->dev
, PAGE_SIZE
);
1395 overlay
->reg_bo
= reg_bo
;
1397 if (OVERLAY_NEEDS_PHYSICAL(dev_priv
)) {
1398 ret
= i915_gem_object_attach_phys(reg_bo
, PAGE_SIZE
);
1400 DRM_ERROR("failed to attach phys overlay regs\n");
1403 overlay
->flip_addr
= reg_bo
->phys_handle
->busaddr
;
1405 ret
= i915_gem_obj_ggtt_pin(reg_bo
, PAGE_SIZE
, PIN_MAPPABLE
);
1407 DRM_ERROR("failed to pin overlay register bo\n");
1410 overlay
->flip_addr
= i915_gem_obj_ggtt_offset(reg_bo
);
1412 ret
= i915_gem_object_set_to_gtt_domain(reg_bo
, true);
1414 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1419 /* init all values */
1420 overlay
->color_key
= 0x0101fe;
1421 overlay
->color_key_enabled
= true;
1422 overlay
->brightness
= -19;
1423 overlay
->contrast
= 75;
1424 overlay
->saturation
= 146;
1426 regs
= intel_overlay_map_regs(overlay
);
1430 memset_io(regs
, 0, sizeof(struct overlay_registers
));
1431 update_polyphase_filter(regs
);
1432 update_reg_attrs(overlay
, regs
);
1434 intel_overlay_unmap_regs(overlay
, regs
);
1436 dev_priv
->overlay
= overlay
;
1437 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
1438 DRM_INFO("initialized overlay support\n");
1442 if (!OVERLAY_NEEDS_PHYSICAL(dev_priv
))
1443 i915_gem_object_ggtt_unpin(reg_bo
);
1445 drm_gem_object_unreference(®_bo
->base
);
1447 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
1452 void intel_cleanup_overlay(struct drm_i915_private
*dev_priv
)
1454 if (!dev_priv
->overlay
)
1457 /* The bo's should be free'd by the generic code already.
1458 * Furthermore modesetting teardown happens beforehand so the
1459 * hardware should be off already */
1460 WARN_ON(dev_priv
->overlay
->active
);
1462 drm_gem_object_unreference_unlocked(&dev_priv
->overlay
->reg_bo
->base
);
1463 kfree(dev_priv
->overlay
);
1466 struct intel_overlay_error_state
{
1467 struct overlay_registers regs
;
1473 static struct overlay_registers __iomem
*
1474 intel_overlay_map_regs_atomic(struct intel_overlay
*overlay
)
1476 struct drm_i915_private
*dev_priv
= overlay
->i915
;
1477 struct overlay_registers __iomem
*regs
;
1479 if (OVERLAY_NEEDS_PHYSICAL(dev_priv
))
1480 /* Cast to make sparse happy, but it's wc memory anyway, so
1481 * equivalent to the wc io mapping on X86. */
1482 regs
= (struct overlay_registers __iomem
*)
1483 overlay
->reg_bo
->phys_handle
->vaddr
;
1485 regs
= io_mapping_map_atomic_wc(dev_priv
->ggtt
.mappable
,
1486 overlay
->flip_addr
);
1491 static void intel_overlay_unmap_regs_atomic(struct intel_overlay
*overlay
,
1492 struct overlay_registers __iomem
*regs
)
1494 if (!OVERLAY_NEEDS_PHYSICAL(overlay
->i915
))
1495 io_mapping_unmap_atomic(regs
);
1498 struct intel_overlay_error_state
*
1499 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
)
1501 struct intel_overlay
*overlay
= dev_priv
->overlay
;
1502 struct intel_overlay_error_state
*error
;
1503 struct overlay_registers __iomem
*regs
;
1505 if (!overlay
|| !overlay
->active
)
1508 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
1512 error
->dovsta
= I915_READ(DOVSTA
);
1513 error
->isr
= I915_READ(ISR
);
1514 error
->base
= overlay
->flip_addr
;
1516 regs
= intel_overlay_map_regs_atomic(overlay
);
1520 memcpy_fromio(&error
->regs
, regs
, sizeof(struct overlay_registers
));
1521 intel_overlay_unmap_regs_atomic(overlay
, regs
);
1531 intel_overlay_print_error_state(struct drm_i915_error_state_buf
*m
,
1532 struct intel_overlay_error_state
*error
)
1534 i915_error_printf(m
, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1535 error
->dovsta
, error
->isr
);
1536 i915_error_printf(m
, " Register file at 0x%08lx:\n",
1539 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x)