drivers/gpu/drm/i915/intel_pipe_crc.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Author: Damien Lespiau <damien.lespiau@intel.com>
  24  *
  25  */
  26
  27 #include <linux/seq_file.h>
  28 #include <linux/circ_buf.h>
  29 #include <linux/ctype.h>
  30 #include <linux/debugfs.h>
  31 #include "intel_drv.h"
  32
  33 struct pipe_crc_info {
  34         const char *name;
  35         struct drm_i915_private *dev_priv;
  36         enum pipe pipe;
  37 };
  38
  39 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
  40 {
  41         struct pipe_crc_info *info = inode->i_private;
  42         struct drm_i915_private *dev_priv = info->dev_priv;
  43         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
  44
  45         if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
  46                 return -ENODEV;
  47
  48         spin_lock_irq(&pipe_crc->lock);
  49
  50         if (pipe_crc->opened) {
  51                 spin_unlock_irq(&pipe_crc->lock);
  52                 return -EBUSY; /* already open */
  53         }
  54
  55         pipe_crc->opened = true;
  56         filep->private_data = inode->i_private;
  57
  58         spin_unlock_irq(&pipe_crc->lock);
  59
  60         return 0;
  61 }
  62
  63 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
  64 {
  65         struct pipe_crc_info *info = inode->i_private;
  66         struct drm_i915_private *dev_priv = info->dev_priv;
  67         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
  68
  69         spin_lock_irq(&pipe_crc->lock);
  70         pipe_crc->opened = false;
  71         spin_unlock_irq(&pipe_crc->lock);
  72
  73         return 0;
  74 }
  75
  76 /* (6 fields, 8 chars each, space separated (5) + '\n') */
  77 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
  78 /* account for \'0' */
  79 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
  80
  81 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
  82 {
  83         assert_spin_locked(&pipe_crc->lock);
  84         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
  85                         INTEL_PIPE_CRC_ENTRIES_NR);
  86 }
  87
  88 static ssize_t
  89 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
  90                    loff_t *pos)
  91 {
  92         struct pipe_crc_info *info = filep->private_data;
  93         struct drm_i915_private *dev_priv = info->dev_priv;
  94         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
  95         char buf[PIPE_CRC_BUFFER_LEN];
  96         int n_entries;
  97         ssize_t bytes_read;
  98
  99         /*
 100          * Don't allow user space to provide buffers not big enough to hold
 101          * a line of data.
 102          */
 103         if (count < PIPE_CRC_LINE_LEN)
 104                 return -EINVAL;
 105
 106         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
 107                 return 0;
 108
 109         /* nothing to read */
 110         spin_lock_irq(&pipe_crc->lock);
 111         while (pipe_crc_data_count(pipe_crc) == 0) {
 112                 int ret;
 113
 114                 if (filep->f_flags & O_NONBLOCK) {
 115                         spin_unlock_irq(&pipe_crc->lock);
 116                         return -EAGAIN;
 117                 }
 118
 119                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
 120                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
 121                 if (ret) {
 122                         spin_unlock_irq(&pipe_crc->lock);
 123                         return ret;
 124                 }
 125         }
 126
 127         /* We now have one or more entries to read */
 128         n_entries = count / PIPE_CRC_LINE_LEN;
 129
 130         bytes_read = 0;
 131         while (n_entries > 0) {
 132                 struct intel_pipe_crc_entry *entry =
 133                         &pipe_crc->entries[pipe_crc->tail];
 134
 135                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
 136                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
 137                         break;
 138
 139                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
 140                 pipe_crc->tail = (pipe_crc->tail + 1) &
 141                                  (INTEL_PIPE_CRC_ENTRIES_NR - 1);
 142
 143                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
 144                                        "%8u %8x %8x %8x %8x %8x\n",
 145                                        entry->frame, entry->crc[0],
 146                                        entry->crc[1], entry->crc[2],
 147                                        entry->crc[3], entry->crc[4]);
 148
 149                 spin_unlock_irq(&pipe_crc->lock);
 150
 151                 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
 152                         return -EFAULT;
 153
 154                 user_buf += PIPE_CRC_LINE_LEN;
 155                 n_entries--;
 156
 157                 spin_lock_irq(&pipe_crc->lock);
 158         }
 159
 160         spin_unlock_irq(&pipe_crc->lock);
 161
 162         return bytes_read;
 163 }
 164
 165 static const struct file_operations i915_pipe_crc_fops = {
 166         .owner = THIS_MODULE,
 167         .open = i915_pipe_crc_open,
 168         .read = i915_pipe_crc_read,
 169         .release = i915_pipe_crc_release,
 170 };
 171
 172 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
 173         {
 174                 .name = "i915_pipe_A_crc",
 175                 .pipe = PIPE_A,
 176         },
 177         {
 178                 .name = "i915_pipe_B_crc",
 179                 .pipe = PIPE_B,
 180         },
 181         {
 182                 .name = "i915_pipe_C_crc",
 183                 .pipe = PIPE_C,
 184         },
 185 };
 186
 187 static const char * const pipe_crc_sources[] = {
 188         "none",
 189         "plane1",
 190         "plane2",
 191         "pf",
 192         "pipe",
 193         "TV",
 194         "DP-B",
 195         "DP-C",
 196         "DP-D",
 197         "auto",
 198 };
 199
 200 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
 201 {
 202         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
 203         return pipe_crc_sources[source];
 204 }
 205
 206 static int display_crc_ctl_show(struct seq_file *m, void *data)
 207 {
 208         struct drm_i915_private *dev_priv = m->private;
 209         int i;
 210
 211         for (i = 0; i < I915_MAX_PIPES; i++)
 212                 seq_printf(m, "%c %s\n", pipe_name(i),
 213                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
 214
 215         return 0;
 216 }
 217
 218 static int display_crc_ctl_open(struct inode *inode, struct file *file)
 219 {
 220         return single_open(file, display_crc_ctl_show, inode->i_private);
 221 }
 222
 223 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
 224                                  uint32_t *val)
 225 {
 226         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
 227                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
 228
 229         switch (*source) {
 230         case INTEL_PIPE_CRC_SOURCE_PIPE:
 231                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
 232                 break;
 233         case INTEL_PIPE_CRC_SOURCE_NONE:
 234                 *val = 0;
 235                 break;
 236         default:
 237                 return -EINVAL;
 238         }
 239
 240         return 0;
 241 }
 242
 243 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
 244                                      enum pipe pipe,
 245                                      enum intel_pipe_crc_source *source)
 246 {
 247         struct drm_device *dev = &dev_priv->drm;
 248         struct intel_encoder *encoder;
 249         struct intel_crtc *crtc;
 250         struct intel_digital_port *dig_port;
 251         int ret = 0;
 252
 253         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
 254
 255         drm_modeset_lock_all(dev);
 256         for_each_intel_encoder(dev, encoder) {
 257                 if (!encoder->base.crtc)
 258                         continue;
 259
 260                 crtc = to_intel_crtc(encoder->base.crtc);
 261
 262                 if (crtc->pipe != pipe)
 263                         continue;
 264
 265                 switch (encoder->type) {
 266                 case INTEL_OUTPUT_TVOUT:
 267                         *source = INTEL_PIPE_CRC_SOURCE_TV;
 268                         break;
 269                 case INTEL_OUTPUT_DP:
 270                 case INTEL_OUTPUT_EDP:
 271                         dig_port = enc_to_dig_port(&encoder->base);
 272                         switch (dig_port->port) {
 273                         case PORT_B:
 274                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
 275                                 break;
 276                         case PORT_C:
 277                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
 278                                 break;
 279                         case PORT_D:
 280                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
 281                                 break;
 282                         default:
 283                                 WARN(1, "nonexisting DP port %c\n",
 284                                      port_name(dig_port->port));
 285                                 break;
 286                         }
 287                         break;
 288                 default:
 289                         break;
 290                 }
 291         }
 292         drm_modeset_unlock_all(dev);
 293
 294         return ret;
 295 }
 296
 297 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
 298                                 enum pipe pipe,
 299                                 enum intel_pipe_crc_source *source,
 300                                 uint32_t *val)
 301 {
 302         bool need_stable_symbols = false;
 303
 304         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
 305                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
 306                 if (ret)
 307                         return ret;
 308         }
 309
 310         switch (*source) {
 311         case INTEL_PIPE_CRC_SOURCE_PIPE:
 312                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
 313                 break;
 314         case INTEL_PIPE_CRC_SOURCE_DP_B:
 315                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
 316                 need_stable_symbols = true;
 317                 break;
 318         case INTEL_PIPE_CRC_SOURCE_DP_C:
 319                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
 320                 need_stable_symbols = true;
 321                 break;
 322         case INTEL_PIPE_CRC_SOURCE_DP_D:
 323                 if (!IS_CHERRYVIEW(dev_priv))
 324                         return -EINVAL;
 325                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
 326                 need_stable_symbols = true;
 327                 break;
 328         case INTEL_PIPE_CRC_SOURCE_NONE:
 329                 *val = 0;
 330                 break;
 331         default:
 332                 return -EINVAL;
 333         }
 334
 335         /*
 336          * When the pipe CRC tap point is after the transcoders we need
 337          * to tweak symbol-level features to produce a deterministic series of
 338          * symbols for a given frame. We need to reset those features only once
 339          * a frame (instead of every nth symbol):
 340          *   - DC-balance: used to ensure a better clock recovery from the data
 341          *     link (SDVO)
 342          *   - DisplayPort scrambling: used for EMI reduction
 343          */
 344         if (need_stable_symbols) {
 345                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
 346
 347                 tmp |= DC_BALANCE_RESET_VLV;
 348                 switch (pipe) {
 349                 case PIPE_A:
 350                         tmp |= PIPE_A_SCRAMBLE_RESET;
 351                         break;
 352                 case PIPE_B:
 353                         tmp |= PIPE_B_SCRAMBLE_RESET;
 354                         break;
 355                 case PIPE_C:
 356                         tmp |= PIPE_C_SCRAMBLE_RESET;
 357                         break;
 358                 default:
 359                         return -EINVAL;
 360                 }
 361                 I915_WRITE(PORT_DFT2_G4X, tmp);
 362         }
 363
 364         return 0;
 365 }
 366
 367 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
 368                                  enum pipe pipe,
 369                                  enum intel_pipe_crc_source *source,
 370                                  uint32_t *val)
 371 {
 372         bool need_stable_symbols = false;
 373
 374         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
 375                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
 376                 if (ret)
 377                         return ret;
 378         }
 379
 380         switch (*source) {
 381         case INTEL_PIPE_CRC_SOURCE_PIPE:
 382                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
 383                 break;
 384         case INTEL_PIPE_CRC_SOURCE_TV:
 385                 if (!SUPPORTS_TV(dev_priv))
 386                         return -EINVAL;
 387                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
 388                 break;
 389         case INTEL_PIPE_CRC_SOURCE_DP_B:
 390                 if (!IS_G4X(dev_priv))
 391                         return -EINVAL;
 392                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
 393                 need_stable_symbols = true;
 394                 break;
 395         case INTEL_PIPE_CRC_SOURCE_DP_C:
 396                 if (!IS_G4X(dev_priv))
 397                         return -EINVAL;
 398                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
 399                 need_stable_symbols = true;
 400                 break;
 401         case INTEL_PIPE_CRC_SOURCE_DP_D:
 402                 if (!IS_G4X(dev_priv))
 403                         return -EINVAL;
 404                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
 405                 need_stable_symbols = true;
 406                 break;
 407         case INTEL_PIPE_CRC_SOURCE_NONE:
 408                 *val = 0;
 409                 break;
 410         default:
 411                 return -EINVAL;
 412         }
 413
 414         /*
 415          * When the pipe CRC tap point is after the transcoders we need
 416          * to tweak symbol-level features to produce a deterministic series of
 417          * symbols for a given frame. We need to reset those features only once
 418          * a frame (instead of every nth symbol):
 419          *   - DC-balance: used to ensure a better clock recovery from the data
 420          *     link (SDVO)
 421          *   - DisplayPort scrambling: used for EMI reduction
 422          */
 423         if (need_stable_symbols) {
 424                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
 425
 426                 WARN_ON(!IS_G4X(dev_priv));
 427
 428                 I915_WRITE(PORT_DFT_I9XX,
 429                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
 430
 431                 if (pipe == PIPE_A)
 432                         tmp |= PIPE_A_SCRAMBLE_RESET;
 433                 else
 434                         tmp |= PIPE_B_SCRAMBLE_RESET;
 435
 436                 I915_WRITE(PORT_DFT2_G4X, tmp);
 437         }
 438
 439         return 0;
 440 }
 441
 442 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
 443                                          enum pipe pipe)
 444 {
 445         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
 446
 447         switch (pipe) {
 448         case PIPE_A:
 449                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
 450                 break;
 451         case PIPE_B:
 452                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
 453                 break;
 454         case PIPE_C:
 455                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
 456                 break;
 457         default:
 458                 return;
 459         }
 460         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
 461                 tmp &= ~DC_BALANCE_RESET_VLV;
 462         I915_WRITE(PORT_DFT2_G4X, tmp);
 463
 464 }
 465
 466 static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
 467                                          enum pipe pipe)
 468 {
 469         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
 470
 471         if (pipe == PIPE_A)
 472                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
 473         else
 474                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
 475         I915_WRITE(PORT_DFT2_G4X, tmp);
 476
 477         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
 478                 I915_WRITE(PORT_DFT_I9XX,
 479                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
 480         }
 481 }
 482
 483 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
 484                                 uint32_t *val)
 485 {
 486         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
 487                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
 488
 489         switch (*source) {
 490         case INTEL_PIPE_CRC_SOURCE_PLANE1:
 491                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
 492                 break;
 493         case INTEL_PIPE_CRC_SOURCE_PLANE2:
 494                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
 495                 break;
 496         case INTEL_PIPE_CRC_SOURCE_PIPE:
 497                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
 498                 break;
 499         case INTEL_PIPE_CRC_SOURCE_NONE:
 500                 *val = 0;
 501                 break;
 502         default:
 503                 return -EINVAL;
 504         }
 505
 506         return 0;
 507 }
 508
 509 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
 510                                         bool enable)
 511 {
 512         struct drm_device *dev = &dev_priv->drm;
 513         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
 514         struct intel_crtc_state *pipe_config;
 515         struct drm_atomic_state *state;
 516         int ret = 0;
 517
 518         drm_modeset_lock_all(dev);
 519         state = drm_atomic_state_alloc(dev);
 520         if (!state) {
 521                 ret = -ENOMEM;
 522                 goto unlock;
 523         }
 524
 525         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
 526         pipe_config = intel_atomic_get_crtc_state(state, crtc);
 527         if (IS_ERR(pipe_config)) {
 528                 ret = PTR_ERR(pipe_config);
 529                 goto put_state;
 530         }
 531
 532         pipe_config->pch_pfit.force_thru = enable;
 533         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
 534             pipe_config->pch_pfit.enabled != enable)
 535                 pipe_config->base.connectors_changed = true;
 536
 537         ret = drm_atomic_commit(state);
 538
 539 put_state:
 540         drm_atomic_state_put(state);
 541 unlock:
 542         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
 543         drm_modeset_unlock_all(dev);
 544 }
 545
 546 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
 547                                 enum pipe pipe,
 548                                 enum intel_pipe_crc_source *source,
 549                                 uint32_t *val)
 550 {
 551         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
 552                 *source = INTEL_PIPE_CRC_SOURCE_PF;
 553
 554         switch (*source) {
 555         case INTEL_PIPE_CRC_SOURCE_PLANE1:
 556                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
 557                 break;
 558         case INTEL_PIPE_CRC_SOURCE_PLANE2:
 559                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
 560                 break;
 561         case INTEL_PIPE_CRC_SOURCE_PF:
 562                 if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
 563                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, true);
 564
 565                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
 566                 break;
 567         case INTEL_PIPE_CRC_SOURCE_NONE:
 568                 *val = 0;
 569                 break;
 570         default:
 571                 return -EINVAL;
 572         }
 573
 574         return 0;
 575 }
 576
 577 static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
 578                                enum pipe pipe,
 579                                enum intel_pipe_crc_source *source, u32 *val)
 580 {
 581         if (IS_GEN2(dev_priv))
 582                 return i8xx_pipe_crc_ctl_reg(source, val);
 583         else if (INTEL_GEN(dev_priv) < 5)
 584                 return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
 585         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 586                 return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
 587         else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
 588                 return ilk_pipe_crc_ctl_reg(source, val);
 589         else
 590                 return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
 591 }
 592
 593 static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
 594                                enum pipe pipe,
 595                                enum intel_pipe_crc_source source)
 596 {
 597         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
 598         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 599         enum intel_display_power_domain power_domain;
 600         u32 val = 0; /* shut up gcc */
 601         int ret;
 602
 603         if (pipe_crc->source == source)
 604                 return 0;
 605
 606         /* forbid changing the source without going back to 'none' */
 607         if (pipe_crc->source && source)
 608                 return -EINVAL;
 609
 610         power_domain = POWER_DOMAIN_PIPE(pipe);
 611         if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
 612                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
 613                 return -EIO;
 614         }
 615
 616         ret = get_new_crc_ctl_reg(dev_priv, pipe, &source, &val);
 617         if (ret != 0)
 618                 goto out;
 619
 620         /* none -> real source transition */
 621         if (source) {
 622                 struct intel_pipe_crc_entry *entries;
 623
 624                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
 625                                  pipe_name(pipe), pipe_crc_source_name(source));
 626
 627                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
 628                                   sizeof(pipe_crc->entries[0]),
 629                                   GFP_KERNEL);
 630                 if (!entries) {
 631                         ret = -ENOMEM;
 632                         goto out;
 633                 }
 634
 635                 /*
 636                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
 637                  * enabled and disabled dynamically based on package C states,
 638                  * user space can't make reliable use of the CRCs, so let's just
 639                  * completely disable it.
 640                  */
 641                 hsw_disable_ips(crtc);
 642
 643                 spin_lock_irq(&pipe_crc->lock);
 644                 kfree(pipe_crc->entries);
 645                 pipe_crc->entries = entries;
 646                 pipe_crc->head = 0;
 647                 pipe_crc->tail = 0;
 648                 spin_unlock_irq(&pipe_crc->lock);
 649         }
 650
 651         pipe_crc->source = source;
 652
 653         I915_WRITE(PIPE_CRC_CTL(pipe), val);
 654         POSTING_READ(PIPE_CRC_CTL(pipe));
 655
 656         /* real source -> none transition */
 657         if (!source) {
 658                 struct intel_pipe_crc_entry *entries;
 659                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
 660                                                                   pipe);
 661
 662                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
 663                                  pipe_name(pipe));
 664
 665                 drm_modeset_lock(&crtc->base.mutex, NULL);
 666                 if (crtc->base.state->active)
 667                         intel_wait_for_vblank(dev_priv, pipe);
 668                 drm_modeset_unlock(&crtc->base.mutex);
 669
 670                 spin_lock_irq(&pipe_crc->lock);
 671                 entries = pipe_crc->entries;
 672                 pipe_crc->entries = NULL;
 673                 pipe_crc->head = 0;
 674                 pipe_crc->tail = 0;
 675                 spin_unlock_irq(&pipe_crc->lock);
 676
 677                 kfree(entries);
 678
 679                 if (IS_G4X(dev_priv))
 680                         g4x_undo_pipe_scramble_reset(dev_priv, pipe);
 681                 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 682                         vlv_undo_pipe_scramble_reset(dev_priv, pipe);
 683                 else if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
 684                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
 685
 686                 hsw_enable_ips(crtc);
 687         }
 688
 689         ret = 0;
 690
 691 out:
 692         intel_display_power_put(dev_priv, power_domain);
 693
 694         return ret;
 695 }
 696
 697 /*
 698  * Parse pipe CRC command strings:
 699  *   command: wsp* object wsp+ name wsp+ source wsp*
 700  *   object: 'pipe'
 701  *   name: (A | B | C)
 702  *   source: (none | plane1 | plane2 | pf)
 703  *   wsp: (#0x20 | #0x9 | #0xA)+
 704  *
 705  * eg.:
 706  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
 707  *  "pipe A none"    ->  Stop CRC
 708  */
 709 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
 710 {
 711         int n_words = 0;
 712
 713         while (*buf) {
 714                 char *end;
 715
 716                 /* skip leading white space */
 717                 buf = skip_spaces(buf);
 718                 if (!*buf)
 719                         break;  /* end of buffer */
 720
 721                 /* find end of word */
 722                 for (end = buf; *end && !isspace(*end); end++)
 723                         ;
 724
 725                 if (n_words == max_words) {
 726                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
 727                                          max_words);
 728                         return -EINVAL; /* ran out of words[] before bytes */
 729                 }
 730
 731                 if (*end)
 732                         *end++ = '\0';
 733                 words[n_words++] = buf;
 734                 buf = end;
 735         }
 736
 737         return n_words;
 738 }
 739
 740 enum intel_pipe_crc_object {
 741         PIPE_CRC_OBJECT_PIPE,
 742 };
 743
 744 static const char * const pipe_crc_objects[] = {
 745         "pipe",
 746 };
 747
 748 static int
 749 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
 750 {
 751         int i;
 752
 753         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
 754                 if (!strcmp(buf, pipe_crc_objects[i])) {
 755                         *o = i;
 756                         return 0;
 757                 }
 758
 759         return -EINVAL;
 760 }
 761
 762 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
 763 {
 764         const char name = buf[0];
 765
 766         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
 767                 return -EINVAL;
 768
 769         *pipe = name - 'A';
 770
 771         return 0;
 772 }
 773
 774 static int
 775 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
 776 {
 777         int i;
 778
 779         if (!buf) {
 780                 *s = INTEL_PIPE_CRC_SOURCE_NONE;
 781                 return 0;
 782         }
 783
 784         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
 785                 if (!strcmp(buf, pipe_crc_sources[i])) {
 786                         *s = i;
 787                         return 0;
 788                 }
 789
 790         return -EINVAL;
 791 }
 792
 793 static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
 794                                  char *buf, size_t len)
 795 {
 796 #define N_WORDS 3
 797         int n_words;
 798         char *words[N_WORDS];
 799         enum pipe pipe;
 800         enum intel_pipe_crc_object object;
 801         enum intel_pipe_crc_source source;
 802
 803         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
 804         if (n_words != N_WORDS) {
 805                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
 806                                  N_WORDS);
 807                 return -EINVAL;
 808         }
 809
 810         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
 811                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
 812                 return -EINVAL;
 813         }
 814
 815         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
 816                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
 817                 return -EINVAL;
 818         }
 819
 820         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
 821                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
 822                 return -EINVAL;
 823         }
 824
 825         return pipe_crc_set_source(dev_priv, pipe, source);
 826 }
 827
 828 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
 829                                      size_t len, loff_t *offp)
 830 {
 831         struct seq_file *m = file->private_data;
 832         struct drm_i915_private *dev_priv = m->private;
 833         char *tmpbuf;
 834         int ret;
 835
 836         if (len == 0)
 837                 return 0;
 838
 839         if (len > PAGE_SIZE - 1) {
 840                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
 841                                  PAGE_SIZE);
 842                 return -E2BIG;
 843         }
 844
 845         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
 846         if (!tmpbuf)
 847                 return -ENOMEM;
 848
 849         if (copy_from_user(tmpbuf, ubuf, len)) {
 850                 ret = -EFAULT;
 851                 goto out;
 852         }
 853         tmpbuf[len] = '\0';
 854
 855         ret = display_crc_ctl_parse(dev_priv, tmpbuf, len);
 856
 857 out:
 858         kfree(tmpbuf);
 859         if (ret < 0)
 860                 return ret;
 861
 862         *offp += len;
 863         return len;
 864 }
 865
 866 const struct file_operations i915_display_crc_ctl_fops = {
 867         .owner = THIS_MODULE,
 868         .open = display_crc_ctl_open,
 869         .read = seq_read,
 870         .llseek = seq_lseek,
 871         .release = single_release,
 872         .write = display_crc_ctl_write
 873 };
 874
 875 void intel_display_crc_init(struct drm_i915_private *dev_priv)
 876 {
 877         enum pipe pipe;
 878
 879         for_each_pipe(dev_priv, pipe) {
 880                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
 881
 882                 pipe_crc->opened = false;
 883                 spin_lock_init(&pipe_crc->lock);
 884                 init_waitqueue_head(&pipe_crc->wq);
 885         }
 886 }
 887
 888 int intel_pipe_crc_create(struct drm_minor *minor)
 889 {
 890         struct drm_i915_private *dev_priv = to_i915(minor->dev);
 891         struct dentry *ent;
 892         int i;
 893
 894         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
 895                 struct pipe_crc_info *info = &i915_pipe_crc_data[i];
 896
 897                 info->dev_priv = dev_priv;
 898                 ent = debugfs_create_file(info->name, S_IRUGO,
 899                                           minor->debugfs_root, info,
 900                                           &i915_pipe_crc_fops);
 901                 if (!ent)
 902                         return -ENOMEM;
 903         }
 904
 905         return 0;
 906 }
 907
 908 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
 909                               size_t *values_cnt)
 910 {
 911         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 912         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
 913         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 914         enum intel_display_power_domain power_domain;
 915         enum intel_pipe_crc_source source;
 916         u32 val = 0; /* shut up gcc */
 917         int ret = 0;
 918
 919         if (display_crc_ctl_parse_source(source_name, &source) < 0) {
 920                 DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
 921                 return -EINVAL;
 922         }
 923
 924         power_domain = POWER_DOMAIN_PIPE(crtc->index);
 925         if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
 926                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
 927                 return -EIO;
 928         }
 929
 930         ret = get_new_crc_ctl_reg(dev_priv, crtc->index, &source, &val);
 931         if (ret != 0)
 932                 goto out;
 933
 934         if (source) {
 935                 /*
 936                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
 937                  * enabled and disabled dynamically based on package C states,
 938                  * user space can't make reliable use of the CRCs, so let's just
 939                  * completely disable it.
 940                  */
 941                 hsw_disable_ips(intel_crtc);
 942         }
 943
 944         I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
 945         POSTING_READ(PIPE_CRC_CTL(crtc->index));
 946
 947         if (!source) {
 948                 if (IS_G4X(dev_priv))
 949                         g4x_undo_pipe_scramble_reset(dev_priv, crtc->index);
 950                 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 951                         vlv_undo_pipe_scramble_reset(dev_priv, crtc->index);
 952                 else if (IS_HASWELL(dev_priv) && crtc->index == PIPE_A)
 953                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
 954
 955                 hsw_enable_ips(intel_crtc);
 956         }
 957
 958         pipe_crc->skipped = 0;
 959         *values_cnt = 5;
 960
 961 out:
 962         intel_display_power_put(dev_priv, power_domain);
 963
 964         return ret;
 965 }