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[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33
34 /**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51 #define INTEL_RC6_ENABLE (1<<0)
52 #define INTEL_RC6p_ENABLE (1<<1)
53 #define INTEL_RC6pp_ENABLE (1<<2)
54
55 static void gen9_init_clock_gating(struct drm_device *dev)
56 {
57 struct drm_i915_private *dev_priv = dev->dev_private;
58
59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
62
63 /* WaDisableKillLogic:bxt,skl */
64 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
65 ECOCHK_DIS_TLB);
66 }
67
68 static void skl_init_clock_gating(struct drm_device *dev)
69 {
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 gen9_init_clock_gating(dev);
73
74 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
75 /* WaDisableHDCInvalidation:skl */
76 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
77 BDW_DISABLE_HDC_INVALIDATION);
78
79 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
80 I915_WRITE(FF_SLICE_CS_CHICKEN2,
81 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
82 }
83
84 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
85 * involving this register should also be added to WA batch as required.
86 */
87 if (INTEL_REVID(dev) <= SKL_REVID_E0)
88 /* WaDisableLSQCROPERFforOCL:skl */
89 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
90 GEN8_LQSC_RO_PERF_DIS);
91
92 /* WaEnableGapsTsvCreditFix:skl */
93 if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) {
94 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
95 GEN9_GAPS_TSV_CREDIT_DISABLE));
96 }
97 }
98
99 static void bxt_init_clock_gating(struct drm_device *dev)
100 {
101 struct drm_i915_private *dev_priv = dev->dev_private;
102
103 gen9_init_clock_gating(dev);
104
105 /* WaDisableSDEUnitClockGating:bxt */
106 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
107 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
108
109 /*
110 * FIXME:
111 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
112 */
113 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
114 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
115
116 /* WaStoreMultiplePTEenable:bxt */
117 /* This is a requirement according to Hardware specification */
118 if (INTEL_REVID(dev) == BXT_REVID_A0)
119 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
120
121 /* WaSetClckGatingDisableMedia:bxt */
122 if (INTEL_REVID(dev) == BXT_REVID_A0) {
123 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
124 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
125 }
126 }
127
128 static void i915_pineview_get_mem_freq(struct drm_device *dev)
129 {
130 struct drm_i915_private *dev_priv = dev->dev_private;
131 u32 tmp;
132
133 tmp = I915_READ(CLKCFG);
134
135 switch (tmp & CLKCFG_FSB_MASK) {
136 case CLKCFG_FSB_533:
137 dev_priv->fsb_freq = 533; /* 133*4 */
138 break;
139 case CLKCFG_FSB_800:
140 dev_priv->fsb_freq = 800; /* 200*4 */
141 break;
142 case CLKCFG_FSB_667:
143 dev_priv->fsb_freq = 667; /* 167*4 */
144 break;
145 case CLKCFG_FSB_400:
146 dev_priv->fsb_freq = 400; /* 100*4 */
147 break;
148 }
149
150 switch (tmp & CLKCFG_MEM_MASK) {
151 case CLKCFG_MEM_533:
152 dev_priv->mem_freq = 533;
153 break;
154 case CLKCFG_MEM_667:
155 dev_priv->mem_freq = 667;
156 break;
157 case CLKCFG_MEM_800:
158 dev_priv->mem_freq = 800;
159 break;
160 }
161
162 /* detect pineview DDR3 setting */
163 tmp = I915_READ(CSHRDDR3CTL);
164 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
165 }
166
167 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
168 {
169 struct drm_i915_private *dev_priv = dev->dev_private;
170 u16 ddrpll, csipll;
171
172 ddrpll = I915_READ16(DDRMPLL1);
173 csipll = I915_READ16(CSIPLL0);
174
175 switch (ddrpll & 0xff) {
176 case 0xc:
177 dev_priv->mem_freq = 800;
178 break;
179 case 0x10:
180 dev_priv->mem_freq = 1066;
181 break;
182 case 0x14:
183 dev_priv->mem_freq = 1333;
184 break;
185 case 0x18:
186 dev_priv->mem_freq = 1600;
187 break;
188 default:
189 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
190 ddrpll & 0xff);
191 dev_priv->mem_freq = 0;
192 break;
193 }
194
195 dev_priv->ips.r_t = dev_priv->mem_freq;
196
197 switch (csipll & 0x3ff) {
198 case 0x00c:
199 dev_priv->fsb_freq = 3200;
200 break;
201 case 0x00e:
202 dev_priv->fsb_freq = 3733;
203 break;
204 case 0x010:
205 dev_priv->fsb_freq = 4266;
206 break;
207 case 0x012:
208 dev_priv->fsb_freq = 4800;
209 break;
210 case 0x014:
211 dev_priv->fsb_freq = 5333;
212 break;
213 case 0x016:
214 dev_priv->fsb_freq = 5866;
215 break;
216 case 0x018:
217 dev_priv->fsb_freq = 6400;
218 break;
219 default:
220 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
221 csipll & 0x3ff);
222 dev_priv->fsb_freq = 0;
223 break;
224 }
225
226 if (dev_priv->fsb_freq == 3200) {
227 dev_priv->ips.c_m = 0;
228 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
229 dev_priv->ips.c_m = 1;
230 } else {
231 dev_priv->ips.c_m = 2;
232 }
233 }
234
235 static const struct cxsr_latency cxsr_latency_table[] = {
236 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
237 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
238 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
239 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
240 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
241
242 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
243 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
244 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
245 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
246 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
247
248 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
249 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
250 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
251 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
252 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
253
254 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
255 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
256 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
257 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
258 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
259
260 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
261 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
262 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
263 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
264 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
265
266 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
267 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
268 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
269 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
270 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
271 };
272
273 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
274 int is_ddr3,
275 int fsb,
276 int mem)
277 {
278 const struct cxsr_latency *latency;
279 int i;
280
281 if (fsb == 0 || mem == 0)
282 return NULL;
283
284 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
285 latency = &cxsr_latency_table[i];
286 if (is_desktop == latency->is_desktop &&
287 is_ddr3 == latency->is_ddr3 &&
288 fsb == latency->fsb_freq && mem == latency->mem_freq)
289 return latency;
290 }
291
292 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
293
294 return NULL;
295 }
296
297 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
298 {
299 u32 val;
300
301 mutex_lock(&dev_priv->rps.hw_lock);
302
303 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
304 if (enable)
305 val &= ~FORCE_DDR_HIGH_FREQ;
306 else
307 val |= FORCE_DDR_HIGH_FREQ;
308 val &= ~FORCE_DDR_LOW_FREQ;
309 val |= FORCE_DDR_FREQ_REQ_ACK;
310 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
311
312 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
313 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
314 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
315
316 mutex_unlock(&dev_priv->rps.hw_lock);
317 }
318
319 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
320 {
321 u32 val;
322
323 mutex_lock(&dev_priv->rps.hw_lock);
324
325 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
326 if (enable)
327 val |= DSP_MAXFIFO_PM5_ENABLE;
328 else
329 val &= ~DSP_MAXFIFO_PM5_ENABLE;
330 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
331
332 mutex_unlock(&dev_priv->rps.hw_lock);
333 }
334
335 #define FW_WM(value, plane) \
336 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
337
338 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
339 {
340 struct drm_device *dev = dev_priv->dev;
341 u32 val;
342
343 if (IS_VALLEYVIEW(dev)) {
344 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
345 POSTING_READ(FW_BLC_SELF_VLV);
346 dev_priv->wm.vlv.cxsr = enable;
347 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
348 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
349 POSTING_READ(FW_BLC_SELF);
350 } else if (IS_PINEVIEW(dev)) {
351 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
352 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
353 I915_WRITE(DSPFW3, val);
354 POSTING_READ(DSPFW3);
355 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
356 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
357 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
358 I915_WRITE(FW_BLC_SELF, val);
359 POSTING_READ(FW_BLC_SELF);
360 } else if (IS_I915GM(dev)) {
361 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
362 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
363 I915_WRITE(INSTPM, val);
364 POSTING_READ(INSTPM);
365 } else {
366 return;
367 }
368
369 DRM_DEBUG_KMS("memory self-refresh is %s\n",
370 enable ? "enabled" : "disabled");
371 }
372
373
374 /*
375 * Latency for FIFO fetches is dependent on several factors:
376 * - memory configuration (speed, channels)
377 * - chipset
378 * - current MCH state
379 * It can be fairly high in some situations, so here we assume a fairly
380 * pessimal value. It's a tradeoff between extra memory fetches (if we
381 * set this value too high, the FIFO will fetch frequently to stay full)
382 * and power consumption (set it too low to save power and we might see
383 * FIFO underruns and display "flicker").
384 *
385 * A value of 5us seems to be a good balance; safe for very low end
386 * platforms but not overly aggressive on lower latency configs.
387 */
388 static const int pessimal_latency_ns = 5000;
389
390 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
391 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
392
393 static int vlv_get_fifo_size(struct drm_device *dev,
394 enum pipe pipe, int plane)
395 {
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 int sprite0_start, sprite1_start, size;
398
399 switch (pipe) {
400 uint32_t dsparb, dsparb2, dsparb3;
401 case PIPE_A:
402 dsparb = I915_READ(DSPARB);
403 dsparb2 = I915_READ(DSPARB2);
404 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
405 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
406 break;
407 case PIPE_B:
408 dsparb = I915_READ(DSPARB);
409 dsparb2 = I915_READ(DSPARB2);
410 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
411 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
412 break;
413 case PIPE_C:
414 dsparb2 = I915_READ(DSPARB2);
415 dsparb3 = I915_READ(DSPARB3);
416 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
417 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
418 break;
419 default:
420 return 0;
421 }
422
423 switch (plane) {
424 case 0:
425 size = sprite0_start;
426 break;
427 case 1:
428 size = sprite1_start - sprite0_start;
429 break;
430 case 2:
431 size = 512 - 1 - sprite1_start;
432 break;
433 default:
434 return 0;
435 }
436
437 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
438 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
439 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
440 size);
441
442 return size;
443 }
444
445 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
446 {
447 struct drm_i915_private *dev_priv = dev->dev_private;
448 uint32_t dsparb = I915_READ(DSPARB);
449 int size;
450
451 size = dsparb & 0x7f;
452 if (plane)
453 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
454
455 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
456 plane ? "B" : "A", size);
457
458 return size;
459 }
460
461 static int i830_get_fifo_size(struct drm_device *dev, int plane)
462 {
463 struct drm_i915_private *dev_priv = dev->dev_private;
464 uint32_t dsparb = I915_READ(DSPARB);
465 int size;
466
467 size = dsparb & 0x1ff;
468 if (plane)
469 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
470 size >>= 1; /* Convert to cachelines */
471
472 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
473 plane ? "B" : "A", size);
474
475 return size;
476 }
477
478 static int i845_get_fifo_size(struct drm_device *dev, int plane)
479 {
480 struct drm_i915_private *dev_priv = dev->dev_private;
481 uint32_t dsparb = I915_READ(DSPARB);
482 int size;
483
484 size = dsparb & 0x7f;
485 size >>= 2; /* Convert to cachelines */
486
487 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
488 plane ? "B" : "A",
489 size);
490
491 return size;
492 }
493
494 /* Pineview has different values for various configs */
495 static const struct intel_watermark_params pineview_display_wm = {
496 .fifo_size = PINEVIEW_DISPLAY_FIFO,
497 .max_wm = PINEVIEW_MAX_WM,
498 .default_wm = PINEVIEW_DFT_WM,
499 .guard_size = PINEVIEW_GUARD_WM,
500 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
501 };
502 static const struct intel_watermark_params pineview_display_hplloff_wm = {
503 .fifo_size = PINEVIEW_DISPLAY_FIFO,
504 .max_wm = PINEVIEW_MAX_WM,
505 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
506 .guard_size = PINEVIEW_GUARD_WM,
507 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
508 };
509 static const struct intel_watermark_params pineview_cursor_wm = {
510 .fifo_size = PINEVIEW_CURSOR_FIFO,
511 .max_wm = PINEVIEW_CURSOR_MAX_WM,
512 .default_wm = PINEVIEW_CURSOR_DFT_WM,
513 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
514 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
515 };
516 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
517 .fifo_size = PINEVIEW_CURSOR_FIFO,
518 .max_wm = PINEVIEW_CURSOR_MAX_WM,
519 .default_wm = PINEVIEW_CURSOR_DFT_WM,
520 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
521 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
522 };
523 static const struct intel_watermark_params g4x_wm_info = {
524 .fifo_size = G4X_FIFO_SIZE,
525 .max_wm = G4X_MAX_WM,
526 .default_wm = G4X_MAX_WM,
527 .guard_size = 2,
528 .cacheline_size = G4X_FIFO_LINE_SIZE,
529 };
530 static const struct intel_watermark_params g4x_cursor_wm_info = {
531 .fifo_size = I965_CURSOR_FIFO,
532 .max_wm = I965_CURSOR_MAX_WM,
533 .default_wm = I965_CURSOR_DFT_WM,
534 .guard_size = 2,
535 .cacheline_size = G4X_FIFO_LINE_SIZE,
536 };
537 static const struct intel_watermark_params valleyview_wm_info = {
538 .fifo_size = VALLEYVIEW_FIFO_SIZE,
539 .max_wm = VALLEYVIEW_MAX_WM,
540 .default_wm = VALLEYVIEW_MAX_WM,
541 .guard_size = 2,
542 .cacheline_size = G4X_FIFO_LINE_SIZE,
543 };
544 static const struct intel_watermark_params valleyview_cursor_wm_info = {
545 .fifo_size = I965_CURSOR_FIFO,
546 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
547 .default_wm = I965_CURSOR_DFT_WM,
548 .guard_size = 2,
549 .cacheline_size = G4X_FIFO_LINE_SIZE,
550 };
551 static const struct intel_watermark_params i965_cursor_wm_info = {
552 .fifo_size = I965_CURSOR_FIFO,
553 .max_wm = I965_CURSOR_MAX_WM,
554 .default_wm = I965_CURSOR_DFT_WM,
555 .guard_size = 2,
556 .cacheline_size = I915_FIFO_LINE_SIZE,
557 };
558 static const struct intel_watermark_params i945_wm_info = {
559 .fifo_size = I945_FIFO_SIZE,
560 .max_wm = I915_MAX_WM,
561 .default_wm = 1,
562 .guard_size = 2,
563 .cacheline_size = I915_FIFO_LINE_SIZE,
564 };
565 static const struct intel_watermark_params i915_wm_info = {
566 .fifo_size = I915_FIFO_SIZE,
567 .max_wm = I915_MAX_WM,
568 .default_wm = 1,
569 .guard_size = 2,
570 .cacheline_size = I915_FIFO_LINE_SIZE,
571 };
572 static const struct intel_watermark_params i830_a_wm_info = {
573 .fifo_size = I855GM_FIFO_SIZE,
574 .max_wm = I915_MAX_WM,
575 .default_wm = 1,
576 .guard_size = 2,
577 .cacheline_size = I830_FIFO_LINE_SIZE,
578 };
579 static const struct intel_watermark_params i830_bc_wm_info = {
580 .fifo_size = I855GM_FIFO_SIZE,
581 .max_wm = I915_MAX_WM/2,
582 .default_wm = 1,
583 .guard_size = 2,
584 .cacheline_size = I830_FIFO_LINE_SIZE,
585 };
586 static const struct intel_watermark_params i845_wm_info = {
587 .fifo_size = I830_FIFO_SIZE,
588 .max_wm = I915_MAX_WM,
589 .default_wm = 1,
590 .guard_size = 2,
591 .cacheline_size = I830_FIFO_LINE_SIZE,
592 };
593
594 /**
595 * intel_calculate_wm - calculate watermark level
596 * @clock_in_khz: pixel clock
597 * @wm: chip FIFO params
598 * @pixel_size: display pixel size
599 * @latency_ns: memory latency for the platform
600 *
601 * Calculate the watermark level (the level at which the display plane will
602 * start fetching from memory again). Each chip has a different display
603 * FIFO size and allocation, so the caller needs to figure that out and pass
604 * in the correct intel_watermark_params structure.
605 *
606 * As the pixel clock runs, the FIFO will be drained at a rate that depends
607 * on the pixel size. When it reaches the watermark level, it'll start
608 * fetching FIFO line sized based chunks from memory until the FIFO fills
609 * past the watermark point. If the FIFO drains completely, a FIFO underrun
610 * will occur, and a display engine hang could result.
611 */
612 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
613 const struct intel_watermark_params *wm,
614 int fifo_size,
615 int pixel_size,
616 unsigned long latency_ns)
617 {
618 long entries_required, wm_size;
619
620 /*
621 * Note: we need to make sure we don't overflow for various clock &
622 * latency values.
623 * clocks go from a few thousand to several hundred thousand.
624 * latency is usually a few thousand
625 */
626 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
627 1000;
628 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
629
630 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
631
632 wm_size = fifo_size - (entries_required + wm->guard_size);
633
634 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
635
636 /* Don't promote wm_size to unsigned... */
637 if (wm_size > (long)wm->max_wm)
638 wm_size = wm->max_wm;
639 if (wm_size <= 0)
640 wm_size = wm->default_wm;
641
642 /*
643 * Bspec seems to indicate that the value shouldn't be lower than
644 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
645 * Lets go for 8 which is the burst size since certain platforms
646 * already use a hardcoded 8 (which is what the spec says should be
647 * done).
648 */
649 if (wm_size <= 8)
650 wm_size = 8;
651
652 return wm_size;
653 }
654
655 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
656 {
657 struct drm_crtc *crtc, *enabled = NULL;
658
659 for_each_crtc(dev, crtc) {
660 if (intel_crtc_active(crtc)) {
661 if (enabled)
662 return NULL;
663 enabled = crtc;
664 }
665 }
666
667 return enabled;
668 }
669
670 static void pineview_update_wm(struct drm_crtc *unused_crtc)
671 {
672 struct drm_device *dev = unused_crtc->dev;
673 struct drm_i915_private *dev_priv = dev->dev_private;
674 struct drm_crtc *crtc;
675 const struct cxsr_latency *latency;
676 u32 reg;
677 unsigned long wm;
678
679 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
680 dev_priv->fsb_freq, dev_priv->mem_freq);
681 if (!latency) {
682 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
683 intel_set_memory_cxsr(dev_priv, false);
684 return;
685 }
686
687 crtc = single_enabled_crtc(dev);
688 if (crtc) {
689 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
690 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
691 int clock = adjusted_mode->crtc_clock;
692
693 /* Display SR */
694 wm = intel_calculate_wm(clock, &pineview_display_wm,
695 pineview_display_wm.fifo_size,
696 pixel_size, latency->display_sr);
697 reg = I915_READ(DSPFW1);
698 reg &= ~DSPFW_SR_MASK;
699 reg |= FW_WM(wm, SR);
700 I915_WRITE(DSPFW1, reg);
701 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
702
703 /* cursor SR */
704 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
705 pineview_display_wm.fifo_size,
706 pixel_size, latency->cursor_sr);
707 reg = I915_READ(DSPFW3);
708 reg &= ~DSPFW_CURSOR_SR_MASK;
709 reg |= FW_WM(wm, CURSOR_SR);
710 I915_WRITE(DSPFW3, reg);
711
712 /* Display HPLL off SR */
713 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
714 pineview_display_hplloff_wm.fifo_size,
715 pixel_size, latency->display_hpll_disable);
716 reg = I915_READ(DSPFW3);
717 reg &= ~DSPFW_HPLL_SR_MASK;
718 reg |= FW_WM(wm, HPLL_SR);
719 I915_WRITE(DSPFW3, reg);
720
721 /* cursor HPLL off SR */
722 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
723 pineview_display_hplloff_wm.fifo_size,
724 pixel_size, latency->cursor_hpll_disable);
725 reg = I915_READ(DSPFW3);
726 reg &= ~DSPFW_HPLL_CURSOR_MASK;
727 reg |= FW_WM(wm, HPLL_CURSOR);
728 I915_WRITE(DSPFW3, reg);
729 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
730
731 intel_set_memory_cxsr(dev_priv, true);
732 } else {
733 intel_set_memory_cxsr(dev_priv, false);
734 }
735 }
736
737 static bool g4x_compute_wm0(struct drm_device *dev,
738 int plane,
739 const struct intel_watermark_params *display,
740 int display_latency_ns,
741 const struct intel_watermark_params *cursor,
742 int cursor_latency_ns,
743 int *plane_wm,
744 int *cursor_wm)
745 {
746 struct drm_crtc *crtc;
747 const struct drm_display_mode *adjusted_mode;
748 int htotal, hdisplay, clock, pixel_size;
749 int line_time_us, line_count;
750 int entries, tlb_miss;
751
752 crtc = intel_get_crtc_for_plane(dev, plane);
753 if (!intel_crtc_active(crtc)) {
754 *cursor_wm = cursor->guard_size;
755 *plane_wm = display->guard_size;
756 return false;
757 }
758
759 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
760 clock = adjusted_mode->crtc_clock;
761 htotal = adjusted_mode->crtc_htotal;
762 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
763 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
764
765 /* Use the small buffer method to calculate plane watermark */
766 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
767 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
768 if (tlb_miss > 0)
769 entries += tlb_miss;
770 entries = DIV_ROUND_UP(entries, display->cacheline_size);
771 *plane_wm = entries + display->guard_size;
772 if (*plane_wm > (int)display->max_wm)
773 *plane_wm = display->max_wm;
774
775 /* Use the large buffer method to calculate cursor watermark */
776 line_time_us = max(htotal * 1000 / clock, 1);
777 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
778 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
779 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
780 if (tlb_miss > 0)
781 entries += tlb_miss;
782 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
783 *cursor_wm = entries + cursor->guard_size;
784 if (*cursor_wm > (int)cursor->max_wm)
785 *cursor_wm = (int)cursor->max_wm;
786
787 return true;
788 }
789
790 /*
791 * Check the wm result.
792 *
793 * If any calculated watermark values is larger than the maximum value that
794 * can be programmed into the associated watermark register, that watermark
795 * must be disabled.
796 */
797 static bool g4x_check_srwm(struct drm_device *dev,
798 int display_wm, int cursor_wm,
799 const struct intel_watermark_params *display,
800 const struct intel_watermark_params *cursor)
801 {
802 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
803 display_wm, cursor_wm);
804
805 if (display_wm > display->max_wm) {
806 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
807 display_wm, display->max_wm);
808 return false;
809 }
810
811 if (cursor_wm > cursor->max_wm) {
812 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
813 cursor_wm, cursor->max_wm);
814 return false;
815 }
816
817 if (!(display_wm || cursor_wm)) {
818 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
819 return false;
820 }
821
822 return true;
823 }
824
825 static bool g4x_compute_srwm(struct drm_device *dev,
826 int plane,
827 int latency_ns,
828 const struct intel_watermark_params *display,
829 const struct intel_watermark_params *cursor,
830 int *display_wm, int *cursor_wm)
831 {
832 struct drm_crtc *crtc;
833 const struct drm_display_mode *adjusted_mode;
834 int hdisplay, htotal, pixel_size, clock;
835 unsigned long line_time_us;
836 int line_count, line_size;
837 int small, large;
838 int entries;
839
840 if (!latency_ns) {
841 *display_wm = *cursor_wm = 0;
842 return false;
843 }
844
845 crtc = intel_get_crtc_for_plane(dev, plane);
846 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
847 clock = adjusted_mode->crtc_clock;
848 htotal = adjusted_mode->crtc_htotal;
849 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
850 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
851
852 line_time_us = max(htotal * 1000 / clock, 1);
853 line_count = (latency_ns / line_time_us + 1000) / 1000;
854 line_size = hdisplay * pixel_size;
855
856 /* Use the minimum of the small and large buffer method for primary */
857 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
858 large = line_count * line_size;
859
860 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
861 *display_wm = entries + display->guard_size;
862
863 /* calculate the self-refresh watermark for display cursor */
864 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
865 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
866 *cursor_wm = entries + cursor->guard_size;
867
868 return g4x_check_srwm(dev,
869 *display_wm, *cursor_wm,
870 display, cursor);
871 }
872
873 #define FW_WM_VLV(value, plane) \
874 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
875
876 static void vlv_write_wm_values(struct intel_crtc *crtc,
877 const struct vlv_wm_values *wm)
878 {
879 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
880 enum pipe pipe = crtc->pipe;
881
882 I915_WRITE(VLV_DDL(pipe),
883 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
884 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
885 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
886 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
887
888 I915_WRITE(DSPFW1,
889 FW_WM(wm->sr.plane, SR) |
890 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
891 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
892 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
893 I915_WRITE(DSPFW2,
894 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
895 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
896 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
897 I915_WRITE(DSPFW3,
898 FW_WM(wm->sr.cursor, CURSOR_SR));
899
900 if (IS_CHERRYVIEW(dev_priv)) {
901 I915_WRITE(DSPFW7_CHV,
902 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
903 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
904 I915_WRITE(DSPFW8_CHV,
905 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
906 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
907 I915_WRITE(DSPFW9_CHV,
908 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
909 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
910 I915_WRITE(DSPHOWM,
911 FW_WM(wm->sr.plane >> 9, SR_HI) |
912 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
913 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
914 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
915 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
916 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
917 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
918 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
919 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
920 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
921 } else {
922 I915_WRITE(DSPFW7,
923 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
924 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
925 I915_WRITE(DSPHOWM,
926 FW_WM(wm->sr.plane >> 9, SR_HI) |
927 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
928 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
929 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
930 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
931 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
932 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
933 }
934
935 /* zero (unused) WM1 watermarks */
936 I915_WRITE(DSPFW4, 0);
937 I915_WRITE(DSPFW5, 0);
938 I915_WRITE(DSPFW6, 0);
939 I915_WRITE(DSPHOWM1, 0);
940
941 POSTING_READ(DSPFW1);
942 }
943
944 #undef FW_WM_VLV
945
946 enum vlv_wm_level {
947 VLV_WM_LEVEL_PM2,
948 VLV_WM_LEVEL_PM5,
949 VLV_WM_LEVEL_DDR_DVFS,
950 };
951
952 /* latency must be in 0.1us units. */
953 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
954 unsigned int pipe_htotal,
955 unsigned int horiz_pixels,
956 unsigned int bytes_per_pixel,
957 unsigned int latency)
958 {
959 unsigned int ret;
960
961 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
962 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
963 ret = DIV_ROUND_UP(ret, 64);
964
965 return ret;
966 }
967
968 static void vlv_setup_wm_latency(struct drm_device *dev)
969 {
970 struct drm_i915_private *dev_priv = dev->dev_private;
971
972 /* all latencies in usec */
973 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
974
975 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
976
977 if (IS_CHERRYVIEW(dev_priv)) {
978 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
979 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
980
981 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
982 }
983 }
984
985 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
986 struct intel_crtc *crtc,
987 const struct intel_plane_state *state,
988 int level)
989 {
990 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
991 int clock, htotal, pixel_size, width, wm;
992
993 if (dev_priv->wm.pri_latency[level] == 0)
994 return USHRT_MAX;
995
996 if (!state->visible)
997 return 0;
998
999 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1000 clock = crtc->config->base.adjusted_mode.crtc_clock;
1001 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
1002 width = crtc->config->pipe_src_w;
1003 if (WARN_ON(htotal == 0))
1004 htotal = 1;
1005
1006 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1007 /*
1008 * FIXME the formula gives values that are
1009 * too big for the cursor FIFO, and hence we
1010 * would never be able to use cursors. For
1011 * now just hardcode the watermark.
1012 */
1013 wm = 63;
1014 } else {
1015 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
1016 dev_priv->wm.pri_latency[level] * 10);
1017 }
1018
1019 return min_t(int, wm, USHRT_MAX);
1020 }
1021
1022 static void vlv_compute_fifo(struct intel_crtc *crtc)
1023 {
1024 struct drm_device *dev = crtc->base.dev;
1025 struct vlv_wm_state *wm_state = &crtc->wm_state;
1026 struct intel_plane *plane;
1027 unsigned int total_rate = 0;
1028 const int fifo_size = 512 - 1;
1029 int fifo_extra, fifo_left = fifo_size;
1030
1031 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1032 struct intel_plane_state *state =
1033 to_intel_plane_state(plane->base.state);
1034
1035 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1036 continue;
1037
1038 if (state->visible) {
1039 wm_state->num_active_planes++;
1040 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1041 }
1042 }
1043
1044 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1045 struct intel_plane_state *state =
1046 to_intel_plane_state(plane->base.state);
1047 unsigned int rate;
1048
1049 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1050 plane->wm.fifo_size = 63;
1051 continue;
1052 }
1053
1054 if (!state->visible) {
1055 plane->wm.fifo_size = 0;
1056 continue;
1057 }
1058
1059 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1060 plane->wm.fifo_size = fifo_size * rate / total_rate;
1061 fifo_left -= plane->wm.fifo_size;
1062 }
1063
1064 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1065
1066 /* spread the remainder evenly */
1067 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1068 int plane_extra;
1069
1070 if (fifo_left == 0)
1071 break;
1072
1073 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1074 continue;
1075
1076 /* give it all to the first plane if none are active */
1077 if (plane->wm.fifo_size == 0 &&
1078 wm_state->num_active_planes)
1079 continue;
1080
1081 plane_extra = min(fifo_extra, fifo_left);
1082 plane->wm.fifo_size += plane_extra;
1083 fifo_left -= plane_extra;
1084 }
1085
1086 WARN_ON(fifo_left != 0);
1087 }
1088
1089 static void vlv_invert_wms(struct intel_crtc *crtc)
1090 {
1091 struct vlv_wm_state *wm_state = &crtc->wm_state;
1092 int level;
1093
1094 for (level = 0; level < wm_state->num_levels; level++) {
1095 struct drm_device *dev = crtc->base.dev;
1096 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1097 struct intel_plane *plane;
1098
1099 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1100 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1101
1102 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1103 switch (plane->base.type) {
1104 int sprite;
1105 case DRM_PLANE_TYPE_CURSOR:
1106 wm_state->wm[level].cursor = plane->wm.fifo_size -
1107 wm_state->wm[level].cursor;
1108 break;
1109 case DRM_PLANE_TYPE_PRIMARY:
1110 wm_state->wm[level].primary = plane->wm.fifo_size -
1111 wm_state->wm[level].primary;
1112 break;
1113 case DRM_PLANE_TYPE_OVERLAY:
1114 sprite = plane->plane;
1115 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1116 wm_state->wm[level].sprite[sprite];
1117 break;
1118 }
1119 }
1120 }
1121 }
1122
1123 static void vlv_compute_wm(struct intel_crtc *crtc)
1124 {
1125 struct drm_device *dev = crtc->base.dev;
1126 struct vlv_wm_state *wm_state = &crtc->wm_state;
1127 struct intel_plane *plane;
1128 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1129 int level;
1130
1131 memset(wm_state, 0, sizeof(*wm_state));
1132
1133 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1134 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1135
1136 wm_state->num_active_planes = 0;
1137
1138 vlv_compute_fifo(crtc);
1139
1140 if (wm_state->num_active_planes != 1)
1141 wm_state->cxsr = false;
1142
1143 if (wm_state->cxsr) {
1144 for (level = 0; level < wm_state->num_levels; level++) {
1145 wm_state->sr[level].plane = sr_fifo_size;
1146 wm_state->sr[level].cursor = 63;
1147 }
1148 }
1149
1150 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1151 struct intel_plane_state *state =
1152 to_intel_plane_state(plane->base.state);
1153
1154 if (!state->visible)
1155 continue;
1156
1157 /* normal watermarks */
1158 for (level = 0; level < wm_state->num_levels; level++) {
1159 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1160 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1161
1162 /* hack */
1163 if (WARN_ON(level == 0 && wm > max_wm))
1164 wm = max_wm;
1165
1166 if (wm > plane->wm.fifo_size)
1167 break;
1168
1169 switch (plane->base.type) {
1170 int sprite;
1171 case DRM_PLANE_TYPE_CURSOR:
1172 wm_state->wm[level].cursor = wm;
1173 break;
1174 case DRM_PLANE_TYPE_PRIMARY:
1175 wm_state->wm[level].primary = wm;
1176 break;
1177 case DRM_PLANE_TYPE_OVERLAY:
1178 sprite = plane->plane;
1179 wm_state->wm[level].sprite[sprite] = wm;
1180 break;
1181 }
1182 }
1183
1184 wm_state->num_levels = level;
1185
1186 if (!wm_state->cxsr)
1187 continue;
1188
1189 /* maxfifo watermarks */
1190 switch (plane->base.type) {
1191 int sprite, level;
1192 case DRM_PLANE_TYPE_CURSOR:
1193 for (level = 0; level < wm_state->num_levels; level++)
1194 wm_state->sr[level].cursor =
1195 wm_state->sr[level].cursor;
1196 break;
1197 case DRM_PLANE_TYPE_PRIMARY:
1198 for (level = 0; level < wm_state->num_levels; level++)
1199 wm_state->sr[level].plane =
1200 min(wm_state->sr[level].plane,
1201 wm_state->wm[level].primary);
1202 break;
1203 case DRM_PLANE_TYPE_OVERLAY:
1204 sprite = plane->plane;
1205 for (level = 0; level < wm_state->num_levels; level++)
1206 wm_state->sr[level].plane =
1207 min(wm_state->sr[level].plane,
1208 wm_state->wm[level].sprite[sprite]);
1209 break;
1210 }
1211 }
1212
1213 /* clear any (partially) filled invalid levels */
1214 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1215 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1216 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1217 }
1218
1219 vlv_invert_wms(crtc);
1220 }
1221
1222 #define VLV_FIFO(plane, value) \
1223 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1224
1225 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1226 {
1227 struct drm_device *dev = crtc->base.dev;
1228 struct drm_i915_private *dev_priv = to_i915(dev);
1229 struct intel_plane *plane;
1230 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1231
1232 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1233 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1234 WARN_ON(plane->wm.fifo_size != 63);
1235 continue;
1236 }
1237
1238 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1239 sprite0_start = plane->wm.fifo_size;
1240 else if (plane->plane == 0)
1241 sprite1_start = sprite0_start + plane->wm.fifo_size;
1242 else
1243 fifo_size = sprite1_start + plane->wm.fifo_size;
1244 }
1245
1246 WARN_ON(fifo_size != 512 - 1);
1247
1248 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1249 pipe_name(crtc->pipe), sprite0_start,
1250 sprite1_start, fifo_size);
1251
1252 switch (crtc->pipe) {
1253 uint32_t dsparb, dsparb2, dsparb3;
1254 case PIPE_A:
1255 dsparb = I915_READ(DSPARB);
1256 dsparb2 = I915_READ(DSPARB2);
1257
1258 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1259 VLV_FIFO(SPRITEB, 0xff));
1260 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1261 VLV_FIFO(SPRITEB, sprite1_start));
1262
1263 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1264 VLV_FIFO(SPRITEB_HI, 0x1));
1265 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1266 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1267
1268 I915_WRITE(DSPARB, dsparb);
1269 I915_WRITE(DSPARB2, dsparb2);
1270 break;
1271 case PIPE_B:
1272 dsparb = I915_READ(DSPARB);
1273 dsparb2 = I915_READ(DSPARB2);
1274
1275 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1276 VLV_FIFO(SPRITED, 0xff));
1277 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1278 VLV_FIFO(SPRITED, sprite1_start));
1279
1280 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1281 VLV_FIFO(SPRITED_HI, 0xff));
1282 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1283 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1284
1285 I915_WRITE(DSPARB, dsparb);
1286 I915_WRITE(DSPARB2, dsparb2);
1287 break;
1288 case PIPE_C:
1289 dsparb3 = I915_READ(DSPARB3);
1290 dsparb2 = I915_READ(DSPARB2);
1291
1292 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1293 VLV_FIFO(SPRITEF, 0xff));
1294 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1295 VLV_FIFO(SPRITEF, sprite1_start));
1296
1297 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1298 VLV_FIFO(SPRITEF_HI, 0xff));
1299 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1300 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1301
1302 I915_WRITE(DSPARB3, dsparb3);
1303 I915_WRITE(DSPARB2, dsparb2);
1304 break;
1305 default:
1306 break;
1307 }
1308 }
1309
1310 #undef VLV_FIFO
1311
1312 static void vlv_merge_wm(struct drm_device *dev,
1313 struct vlv_wm_values *wm)
1314 {
1315 struct intel_crtc *crtc;
1316 int num_active_crtcs = 0;
1317
1318 wm->level = to_i915(dev)->wm.max_level;
1319 wm->cxsr = true;
1320
1321 for_each_intel_crtc(dev, crtc) {
1322 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1323
1324 if (!crtc->active)
1325 continue;
1326
1327 if (!wm_state->cxsr)
1328 wm->cxsr = false;
1329
1330 num_active_crtcs++;
1331 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1332 }
1333
1334 if (num_active_crtcs != 1)
1335 wm->cxsr = false;
1336
1337 if (num_active_crtcs > 1)
1338 wm->level = VLV_WM_LEVEL_PM2;
1339
1340 for_each_intel_crtc(dev, crtc) {
1341 struct vlv_wm_state *wm_state = &crtc->wm_state;
1342 enum pipe pipe = crtc->pipe;
1343
1344 if (!crtc->active)
1345 continue;
1346
1347 wm->pipe[pipe] = wm_state->wm[wm->level];
1348 if (wm->cxsr)
1349 wm->sr = wm_state->sr[wm->level];
1350
1351 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1352 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1353 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1354 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1355 }
1356 }
1357
1358 static void vlv_update_wm(struct drm_crtc *crtc)
1359 {
1360 struct drm_device *dev = crtc->dev;
1361 struct drm_i915_private *dev_priv = dev->dev_private;
1362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1363 enum pipe pipe = intel_crtc->pipe;
1364 struct vlv_wm_values wm = {};
1365
1366 vlv_compute_wm(intel_crtc);
1367 vlv_merge_wm(dev, &wm);
1368
1369 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1370 /* FIXME should be part of crtc atomic commit */
1371 vlv_pipe_set_fifo_size(intel_crtc);
1372 return;
1373 }
1374
1375 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1376 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1377 chv_set_memory_dvfs(dev_priv, false);
1378
1379 if (wm.level < VLV_WM_LEVEL_PM5 &&
1380 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1381 chv_set_memory_pm5(dev_priv, false);
1382
1383 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1384 intel_set_memory_cxsr(dev_priv, false);
1385
1386 /* FIXME should be part of crtc atomic commit */
1387 vlv_pipe_set_fifo_size(intel_crtc);
1388
1389 vlv_write_wm_values(intel_crtc, &wm);
1390
1391 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1392 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1393 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1394 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1395 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1396
1397 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1398 intel_set_memory_cxsr(dev_priv, true);
1399
1400 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1401 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1402 chv_set_memory_pm5(dev_priv, true);
1403
1404 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1405 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1406 chv_set_memory_dvfs(dev_priv, true);
1407
1408 dev_priv->wm.vlv = wm;
1409 }
1410
1411 #define single_plane_enabled(mask) is_power_of_2(mask)
1412
1413 static void g4x_update_wm(struct drm_crtc *crtc)
1414 {
1415 struct drm_device *dev = crtc->dev;
1416 static const int sr_latency_ns = 12000;
1417 struct drm_i915_private *dev_priv = dev->dev_private;
1418 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1419 int plane_sr, cursor_sr;
1420 unsigned int enabled = 0;
1421 bool cxsr_enabled;
1422
1423 if (g4x_compute_wm0(dev, PIPE_A,
1424 &g4x_wm_info, pessimal_latency_ns,
1425 &g4x_cursor_wm_info, pessimal_latency_ns,
1426 &planea_wm, &cursora_wm))
1427 enabled |= 1 << PIPE_A;
1428
1429 if (g4x_compute_wm0(dev, PIPE_B,
1430 &g4x_wm_info, pessimal_latency_ns,
1431 &g4x_cursor_wm_info, pessimal_latency_ns,
1432 &planeb_wm, &cursorb_wm))
1433 enabled |= 1 << PIPE_B;
1434
1435 if (single_plane_enabled(enabled) &&
1436 g4x_compute_srwm(dev, ffs(enabled) - 1,
1437 sr_latency_ns,
1438 &g4x_wm_info,
1439 &g4x_cursor_wm_info,
1440 &plane_sr, &cursor_sr)) {
1441 cxsr_enabled = true;
1442 } else {
1443 cxsr_enabled = false;
1444 intel_set_memory_cxsr(dev_priv, false);
1445 plane_sr = cursor_sr = 0;
1446 }
1447
1448 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1449 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1450 planea_wm, cursora_wm,
1451 planeb_wm, cursorb_wm,
1452 plane_sr, cursor_sr);
1453
1454 I915_WRITE(DSPFW1,
1455 FW_WM(plane_sr, SR) |
1456 FW_WM(cursorb_wm, CURSORB) |
1457 FW_WM(planeb_wm, PLANEB) |
1458 FW_WM(planea_wm, PLANEA));
1459 I915_WRITE(DSPFW2,
1460 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1461 FW_WM(cursora_wm, CURSORA));
1462 /* HPLL off in SR has some issues on G4x... disable it */
1463 I915_WRITE(DSPFW3,
1464 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1465 FW_WM(cursor_sr, CURSOR_SR));
1466
1467 if (cxsr_enabled)
1468 intel_set_memory_cxsr(dev_priv, true);
1469 }
1470
1471 static void i965_update_wm(struct drm_crtc *unused_crtc)
1472 {
1473 struct drm_device *dev = unused_crtc->dev;
1474 struct drm_i915_private *dev_priv = dev->dev_private;
1475 struct drm_crtc *crtc;
1476 int srwm = 1;
1477 int cursor_sr = 16;
1478 bool cxsr_enabled;
1479
1480 /* Calc sr entries for one plane configs */
1481 crtc = single_enabled_crtc(dev);
1482 if (crtc) {
1483 /* self-refresh has much higher latency */
1484 static const int sr_latency_ns = 12000;
1485 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1486 int clock = adjusted_mode->crtc_clock;
1487 int htotal = adjusted_mode->crtc_htotal;
1488 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1489 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
1490 unsigned long line_time_us;
1491 int entries;
1492
1493 line_time_us = max(htotal * 1000 / clock, 1);
1494
1495 /* Use ns/us then divide to preserve precision */
1496 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1497 pixel_size * hdisplay;
1498 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1499 srwm = I965_FIFO_SIZE - entries;
1500 if (srwm < 0)
1501 srwm = 1;
1502 srwm &= 0x1ff;
1503 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1504 entries, srwm);
1505
1506 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1507 pixel_size * crtc->cursor->state->crtc_w;
1508 entries = DIV_ROUND_UP(entries,
1509 i965_cursor_wm_info.cacheline_size);
1510 cursor_sr = i965_cursor_wm_info.fifo_size -
1511 (entries + i965_cursor_wm_info.guard_size);
1512
1513 if (cursor_sr > i965_cursor_wm_info.max_wm)
1514 cursor_sr = i965_cursor_wm_info.max_wm;
1515
1516 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1517 "cursor %d\n", srwm, cursor_sr);
1518
1519 cxsr_enabled = true;
1520 } else {
1521 cxsr_enabled = false;
1522 /* Turn off self refresh if both pipes are enabled */
1523 intel_set_memory_cxsr(dev_priv, false);
1524 }
1525
1526 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1527 srwm);
1528
1529 /* 965 has limitations... */
1530 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1531 FW_WM(8, CURSORB) |
1532 FW_WM(8, PLANEB) |
1533 FW_WM(8, PLANEA));
1534 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1535 FW_WM(8, PLANEC_OLD));
1536 /* update cursor SR watermark */
1537 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1538
1539 if (cxsr_enabled)
1540 intel_set_memory_cxsr(dev_priv, true);
1541 }
1542
1543 #undef FW_WM
1544
1545 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1546 {
1547 struct drm_device *dev = unused_crtc->dev;
1548 struct drm_i915_private *dev_priv = dev->dev_private;
1549 const struct intel_watermark_params *wm_info;
1550 uint32_t fwater_lo;
1551 uint32_t fwater_hi;
1552 int cwm, srwm = 1;
1553 int fifo_size;
1554 int planea_wm, planeb_wm;
1555 struct drm_crtc *crtc, *enabled = NULL;
1556
1557 if (IS_I945GM(dev))
1558 wm_info = &i945_wm_info;
1559 else if (!IS_GEN2(dev))
1560 wm_info = &i915_wm_info;
1561 else
1562 wm_info = &i830_a_wm_info;
1563
1564 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1565 crtc = intel_get_crtc_for_plane(dev, 0);
1566 if (intel_crtc_active(crtc)) {
1567 const struct drm_display_mode *adjusted_mode;
1568 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1569 if (IS_GEN2(dev))
1570 cpp = 4;
1571
1572 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1573 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1574 wm_info, fifo_size, cpp,
1575 pessimal_latency_ns);
1576 enabled = crtc;
1577 } else {
1578 planea_wm = fifo_size - wm_info->guard_size;
1579 if (planea_wm > (long)wm_info->max_wm)
1580 planea_wm = wm_info->max_wm;
1581 }
1582
1583 if (IS_GEN2(dev))
1584 wm_info = &i830_bc_wm_info;
1585
1586 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1587 crtc = intel_get_crtc_for_plane(dev, 1);
1588 if (intel_crtc_active(crtc)) {
1589 const struct drm_display_mode *adjusted_mode;
1590 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1591 if (IS_GEN2(dev))
1592 cpp = 4;
1593
1594 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1595 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1596 wm_info, fifo_size, cpp,
1597 pessimal_latency_ns);
1598 if (enabled == NULL)
1599 enabled = crtc;
1600 else
1601 enabled = NULL;
1602 } else {
1603 planeb_wm = fifo_size - wm_info->guard_size;
1604 if (planeb_wm > (long)wm_info->max_wm)
1605 planeb_wm = wm_info->max_wm;
1606 }
1607
1608 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1609
1610 if (IS_I915GM(dev) && enabled) {
1611 struct drm_i915_gem_object *obj;
1612
1613 obj = intel_fb_obj(enabled->primary->state->fb);
1614
1615 /* self-refresh seems busted with untiled */
1616 if (obj->tiling_mode == I915_TILING_NONE)
1617 enabled = NULL;
1618 }
1619
1620 /*
1621 * Overlay gets an aggressive default since video jitter is bad.
1622 */
1623 cwm = 2;
1624
1625 /* Play safe and disable self-refresh before adjusting watermarks. */
1626 intel_set_memory_cxsr(dev_priv, false);
1627
1628 /* Calc sr entries for one plane configs */
1629 if (HAS_FW_BLC(dev) && enabled) {
1630 /* self-refresh has much higher latency */
1631 static const int sr_latency_ns = 6000;
1632 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1633 int clock = adjusted_mode->crtc_clock;
1634 int htotal = adjusted_mode->crtc_htotal;
1635 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1636 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
1637 unsigned long line_time_us;
1638 int entries;
1639
1640 line_time_us = max(htotal * 1000 / clock, 1);
1641
1642 /* Use ns/us then divide to preserve precision */
1643 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1644 pixel_size * hdisplay;
1645 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1646 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1647 srwm = wm_info->fifo_size - entries;
1648 if (srwm < 0)
1649 srwm = 1;
1650
1651 if (IS_I945G(dev) || IS_I945GM(dev))
1652 I915_WRITE(FW_BLC_SELF,
1653 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1654 else if (IS_I915GM(dev))
1655 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1656 }
1657
1658 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1659 planea_wm, planeb_wm, cwm, srwm);
1660
1661 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1662 fwater_hi = (cwm & 0x1f);
1663
1664 /* Set request length to 8 cachelines per fetch */
1665 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1666 fwater_hi = fwater_hi | (1 << 8);
1667
1668 I915_WRITE(FW_BLC, fwater_lo);
1669 I915_WRITE(FW_BLC2, fwater_hi);
1670
1671 if (enabled)
1672 intel_set_memory_cxsr(dev_priv, true);
1673 }
1674
1675 static void i845_update_wm(struct drm_crtc *unused_crtc)
1676 {
1677 struct drm_device *dev = unused_crtc->dev;
1678 struct drm_i915_private *dev_priv = dev->dev_private;
1679 struct drm_crtc *crtc;
1680 const struct drm_display_mode *adjusted_mode;
1681 uint32_t fwater_lo;
1682 int planea_wm;
1683
1684 crtc = single_enabled_crtc(dev);
1685 if (crtc == NULL)
1686 return;
1687
1688 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1689 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1690 &i845_wm_info,
1691 dev_priv->display.get_fifo_size(dev, 0),
1692 4, pessimal_latency_ns);
1693 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1694 fwater_lo |= (3<<8) | planea_wm;
1695
1696 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1697
1698 I915_WRITE(FW_BLC, fwater_lo);
1699 }
1700
1701 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1702 {
1703 uint32_t pixel_rate;
1704
1705 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1706
1707 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1708 * adjust the pixel_rate here. */
1709
1710 if (pipe_config->pch_pfit.enabled) {
1711 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1712 uint32_t pfit_size = pipe_config->pch_pfit.size;
1713
1714 pipe_w = pipe_config->pipe_src_w;
1715 pipe_h = pipe_config->pipe_src_h;
1716
1717 pfit_w = (pfit_size >> 16) & 0xFFFF;
1718 pfit_h = pfit_size & 0xFFFF;
1719 if (pipe_w < pfit_w)
1720 pipe_w = pfit_w;
1721 if (pipe_h < pfit_h)
1722 pipe_h = pfit_h;
1723
1724 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1725 pfit_w * pfit_h);
1726 }
1727
1728 return pixel_rate;
1729 }
1730
1731 /* latency must be in 0.1us units. */
1732 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1733 uint32_t latency)
1734 {
1735 uint64_t ret;
1736
1737 if (WARN(latency == 0, "Latency value missing\n"))
1738 return UINT_MAX;
1739
1740 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1741 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1742
1743 return ret;
1744 }
1745
1746 /* latency must be in 0.1us units. */
1747 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1748 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1749 uint32_t latency)
1750 {
1751 uint32_t ret;
1752
1753 if (WARN(latency == 0, "Latency value missing\n"))
1754 return UINT_MAX;
1755
1756 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1757 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1758 ret = DIV_ROUND_UP(ret, 64) + 2;
1759 return ret;
1760 }
1761
1762 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1763 uint8_t bytes_per_pixel)
1764 {
1765 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1766 }
1767
1768 struct skl_pipe_wm_parameters {
1769 bool active;
1770 uint32_t pipe_htotal;
1771 uint32_t pixel_rate; /* in KHz */
1772 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1773 };
1774
1775 struct ilk_wm_maximums {
1776 uint16_t pri;
1777 uint16_t spr;
1778 uint16_t cur;
1779 uint16_t fbc;
1780 };
1781
1782 /* used in computing the new watermarks state */
1783 struct intel_wm_config {
1784 unsigned int num_pipes_active;
1785 bool sprites_enabled;
1786 bool sprites_scaled;
1787 };
1788
1789 /*
1790 * For both WM_PIPE and WM_LP.
1791 * mem_value must be in 0.1us units.
1792 */
1793 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1794 const struct intel_plane_state *pstate,
1795 uint32_t mem_value,
1796 bool is_lp)
1797 {
1798 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1799 uint32_t method1, method2;
1800
1801 if (!cstate->base.active || !pstate->visible)
1802 return 0;
1803
1804 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1805
1806 if (!is_lp)
1807 return method1;
1808
1809 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1810 cstate->base.adjusted_mode.crtc_htotal,
1811 drm_rect_width(&pstate->dst),
1812 bpp,
1813 mem_value);
1814
1815 return min(method1, method2);
1816 }
1817
1818 /*
1819 * For both WM_PIPE and WM_LP.
1820 * mem_value must be in 0.1us units.
1821 */
1822 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1823 const struct intel_plane_state *pstate,
1824 uint32_t mem_value)
1825 {
1826 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1827 uint32_t method1, method2;
1828
1829 if (!cstate->base.active || !pstate->visible)
1830 return 0;
1831
1832 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1833 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1834 cstate->base.adjusted_mode.crtc_htotal,
1835 drm_rect_width(&pstate->dst),
1836 bpp,
1837 mem_value);
1838 return min(method1, method2);
1839 }
1840
1841 /*
1842 * For both WM_PIPE and WM_LP.
1843 * mem_value must be in 0.1us units.
1844 */
1845 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1846 const struct intel_plane_state *pstate,
1847 uint32_t mem_value)
1848 {
1849 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1850
1851 if (!cstate->base.active || !pstate->visible)
1852 return 0;
1853
1854 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1855 cstate->base.adjusted_mode.crtc_htotal,
1856 drm_rect_width(&pstate->dst),
1857 bpp,
1858 mem_value);
1859 }
1860
1861 /* Only for WM_LP. */
1862 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1863 const struct intel_plane_state *pstate,
1864 uint32_t pri_val)
1865 {
1866 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1867
1868 if (!cstate->base.active || !pstate->visible)
1869 return 0;
1870
1871 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
1872 }
1873
1874 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1875 {
1876 if (INTEL_INFO(dev)->gen >= 8)
1877 return 3072;
1878 else if (INTEL_INFO(dev)->gen >= 7)
1879 return 768;
1880 else
1881 return 512;
1882 }
1883
1884 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1885 int level, bool is_sprite)
1886 {
1887 if (INTEL_INFO(dev)->gen >= 8)
1888 /* BDW primary/sprite plane watermarks */
1889 return level == 0 ? 255 : 2047;
1890 else if (INTEL_INFO(dev)->gen >= 7)
1891 /* IVB/HSW primary/sprite plane watermarks */
1892 return level == 0 ? 127 : 1023;
1893 else if (!is_sprite)
1894 /* ILK/SNB primary plane watermarks */
1895 return level == 0 ? 127 : 511;
1896 else
1897 /* ILK/SNB sprite plane watermarks */
1898 return level == 0 ? 63 : 255;
1899 }
1900
1901 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1902 int level)
1903 {
1904 if (INTEL_INFO(dev)->gen >= 7)
1905 return level == 0 ? 63 : 255;
1906 else
1907 return level == 0 ? 31 : 63;
1908 }
1909
1910 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1911 {
1912 if (INTEL_INFO(dev)->gen >= 8)
1913 return 31;
1914 else
1915 return 15;
1916 }
1917
1918 /* Calculate the maximum primary/sprite plane watermark */
1919 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1920 int level,
1921 const struct intel_wm_config *config,
1922 enum intel_ddb_partitioning ddb_partitioning,
1923 bool is_sprite)
1924 {
1925 unsigned int fifo_size = ilk_display_fifo_size(dev);
1926
1927 /* if sprites aren't enabled, sprites get nothing */
1928 if (is_sprite && !config->sprites_enabled)
1929 return 0;
1930
1931 /* HSW allows LP1+ watermarks even with multiple pipes */
1932 if (level == 0 || config->num_pipes_active > 1) {
1933 fifo_size /= INTEL_INFO(dev)->num_pipes;
1934
1935 /*
1936 * For some reason the non self refresh
1937 * FIFO size is only half of the self
1938 * refresh FIFO size on ILK/SNB.
1939 */
1940 if (INTEL_INFO(dev)->gen <= 6)
1941 fifo_size /= 2;
1942 }
1943
1944 if (config->sprites_enabled) {
1945 /* level 0 is always calculated with 1:1 split */
1946 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1947 if (is_sprite)
1948 fifo_size *= 5;
1949 fifo_size /= 6;
1950 } else {
1951 fifo_size /= 2;
1952 }
1953 }
1954
1955 /* clamp to max that the registers can hold */
1956 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1957 }
1958
1959 /* Calculate the maximum cursor plane watermark */
1960 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1961 int level,
1962 const struct intel_wm_config *config)
1963 {
1964 /* HSW LP1+ watermarks w/ multiple pipes */
1965 if (level > 0 && config->num_pipes_active > 1)
1966 return 64;
1967
1968 /* otherwise just report max that registers can hold */
1969 return ilk_cursor_wm_reg_max(dev, level);
1970 }
1971
1972 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1973 int level,
1974 const struct intel_wm_config *config,
1975 enum intel_ddb_partitioning ddb_partitioning,
1976 struct ilk_wm_maximums *max)
1977 {
1978 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1979 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1980 max->cur = ilk_cursor_wm_max(dev, level, config);
1981 max->fbc = ilk_fbc_wm_reg_max(dev);
1982 }
1983
1984 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1985 int level,
1986 struct ilk_wm_maximums *max)
1987 {
1988 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1989 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1990 max->cur = ilk_cursor_wm_reg_max(dev, level);
1991 max->fbc = ilk_fbc_wm_reg_max(dev);
1992 }
1993
1994 static bool ilk_validate_wm_level(int level,
1995 const struct ilk_wm_maximums *max,
1996 struct intel_wm_level *result)
1997 {
1998 bool ret;
1999
2000 /* already determined to be invalid? */
2001 if (!result->enable)
2002 return false;
2003
2004 result->enable = result->pri_val <= max->pri &&
2005 result->spr_val <= max->spr &&
2006 result->cur_val <= max->cur;
2007
2008 ret = result->enable;
2009
2010 /*
2011 * HACK until we can pre-compute everything,
2012 * and thus fail gracefully if LP0 watermarks
2013 * are exceeded...
2014 */
2015 if (level == 0 && !result->enable) {
2016 if (result->pri_val > max->pri)
2017 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2018 level, result->pri_val, max->pri);
2019 if (result->spr_val > max->spr)
2020 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2021 level, result->spr_val, max->spr);
2022 if (result->cur_val > max->cur)
2023 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2024 level, result->cur_val, max->cur);
2025
2026 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2027 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2028 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2029 result->enable = true;
2030 }
2031
2032 return ret;
2033 }
2034
2035 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2036 const struct intel_crtc *intel_crtc,
2037 int level,
2038 struct intel_crtc_state *cstate,
2039 struct intel_wm_level *result)
2040 {
2041 struct intel_plane *intel_plane;
2042 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2043 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2044 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2045
2046 /* WM1+ latency values stored in 0.5us units */
2047 if (level > 0) {
2048 pri_latency *= 5;
2049 spr_latency *= 5;
2050 cur_latency *= 5;
2051 }
2052
2053 for_each_intel_plane_on_crtc(dev_priv->dev, intel_crtc, intel_plane) {
2054 struct intel_plane_state *pstate =
2055 to_intel_plane_state(intel_plane->base.state);
2056
2057 switch (intel_plane->base.type) {
2058 case DRM_PLANE_TYPE_PRIMARY:
2059 result->pri_val = ilk_compute_pri_wm(cstate, pstate,
2060 pri_latency,
2061 level);
2062 result->fbc_val = ilk_compute_fbc_wm(cstate, pstate,
2063 result->pri_val);
2064 break;
2065 case DRM_PLANE_TYPE_OVERLAY:
2066 result->spr_val = ilk_compute_spr_wm(cstate, pstate,
2067 spr_latency);
2068 break;
2069 case DRM_PLANE_TYPE_CURSOR:
2070 result->cur_val = ilk_compute_cur_wm(cstate, pstate,
2071 cur_latency);
2072 break;
2073 }
2074 }
2075
2076 result->enable = true;
2077 }
2078
2079 static uint32_t
2080 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2081 {
2082 struct drm_i915_private *dev_priv = dev->dev_private;
2083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2084 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
2085 u32 linetime, ips_linetime;
2086
2087 if (!intel_crtc->active)
2088 return 0;
2089
2090 /* The WM are computed with base on how long it takes to fill a single
2091 * row at the given clock rate, multiplied by 8.
2092 * */
2093 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2094 adjusted_mode->crtc_clock);
2095 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2096 dev_priv->cdclk_freq);
2097
2098 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2099 PIPE_WM_LINETIME_TIME(linetime);
2100 }
2101
2102 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2103 {
2104 struct drm_i915_private *dev_priv = dev->dev_private;
2105
2106 if (IS_GEN9(dev)) {
2107 uint32_t val;
2108 int ret, i;
2109 int level, max_level = ilk_wm_max_level(dev);
2110
2111 /* read the first set of memory latencies[0:3] */
2112 val = 0; /* data0 to be programmed to 0 for first set */
2113 mutex_lock(&dev_priv->rps.hw_lock);
2114 ret = sandybridge_pcode_read(dev_priv,
2115 GEN9_PCODE_READ_MEM_LATENCY,
2116 &val);
2117 mutex_unlock(&dev_priv->rps.hw_lock);
2118
2119 if (ret) {
2120 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2121 return;
2122 }
2123
2124 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2125 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2126 GEN9_MEM_LATENCY_LEVEL_MASK;
2127 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2128 GEN9_MEM_LATENCY_LEVEL_MASK;
2129 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2130 GEN9_MEM_LATENCY_LEVEL_MASK;
2131
2132 /* read the second set of memory latencies[4:7] */
2133 val = 1; /* data0 to be programmed to 1 for second set */
2134 mutex_lock(&dev_priv->rps.hw_lock);
2135 ret = sandybridge_pcode_read(dev_priv,
2136 GEN9_PCODE_READ_MEM_LATENCY,
2137 &val);
2138 mutex_unlock(&dev_priv->rps.hw_lock);
2139 if (ret) {
2140 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2141 return;
2142 }
2143
2144 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2145 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2146 GEN9_MEM_LATENCY_LEVEL_MASK;
2147 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2148 GEN9_MEM_LATENCY_LEVEL_MASK;
2149 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2150 GEN9_MEM_LATENCY_LEVEL_MASK;
2151
2152 /*
2153 * WaWmMemoryReadLatency:skl
2154 *
2155 * punit doesn't take into account the read latency so we need
2156 * to add 2us to the various latency levels we retrieve from
2157 * the punit.
2158 * - W0 is a bit special in that it's the only level that
2159 * can't be disabled if we want to have display working, so
2160 * we always add 2us there.
2161 * - For levels >=1, punit returns 0us latency when they are
2162 * disabled, so we respect that and don't add 2us then
2163 *
2164 * Additionally, if a level n (n > 1) has a 0us latency, all
2165 * levels m (m >= n) need to be disabled. We make sure to
2166 * sanitize the values out of the punit to satisfy this
2167 * requirement.
2168 */
2169 wm[0] += 2;
2170 for (level = 1; level <= max_level; level++)
2171 if (wm[level] != 0)
2172 wm[level] += 2;
2173 else {
2174 for (i = level + 1; i <= max_level; i++)
2175 wm[i] = 0;
2176
2177 break;
2178 }
2179 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2180 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2181
2182 wm[0] = (sskpd >> 56) & 0xFF;
2183 if (wm[0] == 0)
2184 wm[0] = sskpd & 0xF;
2185 wm[1] = (sskpd >> 4) & 0xFF;
2186 wm[2] = (sskpd >> 12) & 0xFF;
2187 wm[3] = (sskpd >> 20) & 0x1FF;
2188 wm[4] = (sskpd >> 32) & 0x1FF;
2189 } else if (INTEL_INFO(dev)->gen >= 6) {
2190 uint32_t sskpd = I915_READ(MCH_SSKPD);
2191
2192 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2193 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2194 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2195 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2196 } else if (INTEL_INFO(dev)->gen >= 5) {
2197 uint32_t mltr = I915_READ(MLTR_ILK);
2198
2199 /* ILK primary LP0 latency is 700 ns */
2200 wm[0] = 7;
2201 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2202 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2203 }
2204 }
2205
2206 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2207 {
2208 /* ILK sprite LP0 latency is 1300 ns */
2209 if (INTEL_INFO(dev)->gen == 5)
2210 wm[0] = 13;
2211 }
2212
2213 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2214 {
2215 /* ILK cursor LP0 latency is 1300 ns */
2216 if (INTEL_INFO(dev)->gen == 5)
2217 wm[0] = 13;
2218
2219 /* WaDoubleCursorLP3Latency:ivb */
2220 if (IS_IVYBRIDGE(dev))
2221 wm[3] *= 2;
2222 }
2223
2224 int ilk_wm_max_level(const struct drm_device *dev)
2225 {
2226 /* how many WM levels are we expecting */
2227 if (INTEL_INFO(dev)->gen >= 9)
2228 return 7;
2229 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2230 return 4;
2231 else if (INTEL_INFO(dev)->gen >= 6)
2232 return 3;
2233 else
2234 return 2;
2235 }
2236
2237 static void intel_print_wm_latency(struct drm_device *dev,
2238 const char *name,
2239 const uint16_t wm[8])
2240 {
2241 int level, max_level = ilk_wm_max_level(dev);
2242
2243 for (level = 0; level <= max_level; level++) {
2244 unsigned int latency = wm[level];
2245
2246 if (latency == 0) {
2247 DRM_ERROR("%s WM%d latency not provided\n",
2248 name, level);
2249 continue;
2250 }
2251
2252 /*
2253 * - latencies are in us on gen9.
2254 * - before then, WM1+ latency values are in 0.5us units
2255 */
2256 if (IS_GEN9(dev))
2257 latency *= 10;
2258 else if (level > 0)
2259 latency *= 5;
2260
2261 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2262 name, level, wm[level],
2263 latency / 10, latency % 10);
2264 }
2265 }
2266
2267 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2268 uint16_t wm[5], uint16_t min)
2269 {
2270 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2271
2272 if (wm[0] >= min)
2273 return false;
2274
2275 wm[0] = max(wm[0], min);
2276 for (level = 1; level <= max_level; level++)
2277 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2278
2279 return true;
2280 }
2281
2282 static void snb_wm_latency_quirk(struct drm_device *dev)
2283 {
2284 struct drm_i915_private *dev_priv = dev->dev_private;
2285 bool changed;
2286
2287 /*
2288 * The BIOS provided WM memory latency values are often
2289 * inadequate for high resolution displays. Adjust them.
2290 */
2291 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2292 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2293 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2294
2295 if (!changed)
2296 return;
2297
2298 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2299 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2300 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2301 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2302 }
2303
2304 static void ilk_setup_wm_latency(struct drm_device *dev)
2305 {
2306 struct drm_i915_private *dev_priv = dev->dev_private;
2307
2308 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2309
2310 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2311 sizeof(dev_priv->wm.pri_latency));
2312 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2313 sizeof(dev_priv->wm.pri_latency));
2314
2315 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2316 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2317
2318 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2319 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2320 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2321
2322 if (IS_GEN6(dev))
2323 snb_wm_latency_quirk(dev);
2324 }
2325
2326 static void skl_setup_wm_latency(struct drm_device *dev)
2327 {
2328 struct drm_i915_private *dev_priv = dev->dev_private;
2329
2330 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2331 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2332 }
2333
2334 static void ilk_compute_wm_config(struct drm_device *dev,
2335 struct intel_wm_config *config)
2336 {
2337 struct intel_crtc *intel_crtc;
2338
2339 /* Compute the currently _active_ config */
2340 for_each_intel_crtc(dev, intel_crtc) {
2341 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2342
2343 if (!wm->pipe_enabled)
2344 continue;
2345
2346 config->sprites_enabled |= wm->sprites_enabled;
2347 config->sprites_scaled |= wm->sprites_scaled;
2348 config->num_pipes_active++;
2349 }
2350 }
2351
2352 /* Compute new watermarks for the pipe */
2353 static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate,
2354 struct intel_pipe_wm *pipe_wm)
2355 {
2356 struct drm_crtc *crtc = cstate->base.crtc;
2357 struct drm_device *dev = crtc->dev;
2358 const struct drm_i915_private *dev_priv = dev->dev_private;
2359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2360 struct intel_plane *intel_plane;
2361 struct intel_plane_state *sprstate = NULL;
2362 int level, max_level = ilk_wm_max_level(dev);
2363 /* LP0 watermark maximums depend on this pipe alone */
2364 struct intel_wm_config config = {
2365 .num_pipes_active = 1,
2366 };
2367 struct ilk_wm_maximums max;
2368
2369 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2370 if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) {
2371 sprstate = to_intel_plane_state(intel_plane->base.state);
2372 break;
2373 }
2374 }
2375
2376 config.sprites_enabled = sprstate->visible;
2377 config.sprites_scaled = sprstate->visible &&
2378 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2379 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2380
2381 pipe_wm->pipe_enabled = cstate->base.active;
2382 pipe_wm->sprites_enabled = sprstate->visible;
2383 pipe_wm->sprites_scaled = config.sprites_scaled;
2384
2385 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2386 if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
2387 max_level = 1;
2388
2389 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2390 if (config.sprites_scaled)
2391 max_level = 0;
2392
2393 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, &pipe_wm->wm[0]);
2394
2395 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2396 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2397
2398 /* LP0 watermarks always use 1/2 DDB partitioning */
2399 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2400
2401 /* At least LP0 must be valid */
2402 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2403 return false;
2404
2405 ilk_compute_wm_reg_maximums(dev, 1, &max);
2406
2407 for (level = 1; level <= max_level; level++) {
2408 struct intel_wm_level wm = {};
2409
2410 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm);
2411
2412 /*
2413 * Disable any watermark level that exceeds the
2414 * register maximums since such watermarks are
2415 * always invalid.
2416 */
2417 if (!ilk_validate_wm_level(level, &max, &wm))
2418 break;
2419
2420 pipe_wm->wm[level] = wm;
2421 }
2422
2423 return true;
2424 }
2425
2426 /*
2427 * Merge the watermarks from all active pipes for a specific level.
2428 */
2429 static void ilk_merge_wm_level(struct drm_device *dev,
2430 int level,
2431 struct intel_wm_level *ret_wm)
2432 {
2433 const struct intel_crtc *intel_crtc;
2434
2435 ret_wm->enable = true;
2436
2437 for_each_intel_crtc(dev, intel_crtc) {
2438 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2439 const struct intel_wm_level *wm = &active->wm[level];
2440
2441 if (!active->pipe_enabled)
2442 continue;
2443
2444 /*
2445 * The watermark values may have been used in the past,
2446 * so we must maintain them in the registers for some
2447 * time even if the level is now disabled.
2448 */
2449 if (!wm->enable)
2450 ret_wm->enable = false;
2451
2452 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2453 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2454 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2455 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2456 }
2457 }
2458
2459 /*
2460 * Merge all low power watermarks for all active pipes.
2461 */
2462 static void ilk_wm_merge(struct drm_device *dev,
2463 const struct intel_wm_config *config,
2464 const struct ilk_wm_maximums *max,
2465 struct intel_pipe_wm *merged)
2466 {
2467 struct drm_i915_private *dev_priv = dev->dev_private;
2468 int level, max_level = ilk_wm_max_level(dev);
2469 int last_enabled_level = max_level;
2470
2471 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2472 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2473 config->num_pipes_active > 1)
2474 return;
2475
2476 /* ILK: FBC WM must be disabled always */
2477 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2478
2479 /* merge each WM1+ level */
2480 for (level = 1; level <= max_level; level++) {
2481 struct intel_wm_level *wm = &merged->wm[level];
2482
2483 ilk_merge_wm_level(dev, level, wm);
2484
2485 if (level > last_enabled_level)
2486 wm->enable = false;
2487 else if (!ilk_validate_wm_level(level, max, wm))
2488 /* make sure all following levels get disabled */
2489 last_enabled_level = level - 1;
2490
2491 /*
2492 * The spec says it is preferred to disable
2493 * FBC WMs instead of disabling a WM level.
2494 */
2495 if (wm->fbc_val > max->fbc) {
2496 if (wm->enable)
2497 merged->fbc_wm_enabled = false;
2498 wm->fbc_val = 0;
2499 }
2500 }
2501
2502 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2503 /*
2504 * FIXME this is racy. FBC might get enabled later.
2505 * What we should check here is whether FBC can be
2506 * enabled sometime later.
2507 */
2508 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2509 intel_fbc_enabled(dev_priv)) {
2510 for (level = 2; level <= max_level; level++) {
2511 struct intel_wm_level *wm = &merged->wm[level];
2512
2513 wm->enable = false;
2514 }
2515 }
2516 }
2517
2518 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2519 {
2520 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2521 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2522 }
2523
2524 /* The value we need to program into the WM_LPx latency field */
2525 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2526 {
2527 struct drm_i915_private *dev_priv = dev->dev_private;
2528
2529 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2530 return 2 * level;
2531 else
2532 return dev_priv->wm.pri_latency[level];
2533 }
2534
2535 static void ilk_compute_wm_results(struct drm_device *dev,
2536 const struct intel_pipe_wm *merged,
2537 enum intel_ddb_partitioning partitioning,
2538 struct ilk_wm_values *results)
2539 {
2540 struct intel_crtc *intel_crtc;
2541 int level, wm_lp;
2542
2543 results->enable_fbc_wm = merged->fbc_wm_enabled;
2544 results->partitioning = partitioning;
2545
2546 /* LP1+ register values */
2547 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2548 const struct intel_wm_level *r;
2549
2550 level = ilk_wm_lp_to_level(wm_lp, merged);
2551
2552 r = &merged->wm[level];
2553
2554 /*
2555 * Maintain the watermark values even if the level is
2556 * disabled. Doing otherwise could cause underruns.
2557 */
2558 results->wm_lp[wm_lp - 1] =
2559 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2560 (r->pri_val << WM1_LP_SR_SHIFT) |
2561 r->cur_val;
2562
2563 if (r->enable)
2564 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2565
2566 if (INTEL_INFO(dev)->gen >= 8)
2567 results->wm_lp[wm_lp - 1] |=
2568 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2569 else
2570 results->wm_lp[wm_lp - 1] |=
2571 r->fbc_val << WM1_LP_FBC_SHIFT;
2572
2573 /*
2574 * Always set WM1S_LP_EN when spr_val != 0, even if the
2575 * level is disabled. Doing otherwise could cause underruns.
2576 */
2577 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2578 WARN_ON(wm_lp != 1);
2579 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2580 } else
2581 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2582 }
2583
2584 /* LP0 register values */
2585 for_each_intel_crtc(dev, intel_crtc) {
2586 enum pipe pipe = intel_crtc->pipe;
2587 const struct intel_wm_level *r =
2588 &intel_crtc->wm.active.wm[0];
2589
2590 if (WARN_ON(!r->enable))
2591 continue;
2592
2593 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2594
2595 results->wm_pipe[pipe] =
2596 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2597 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2598 r->cur_val;
2599 }
2600 }
2601
2602 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2603 * case both are at the same level. Prefer r1 in case they're the same. */
2604 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2605 struct intel_pipe_wm *r1,
2606 struct intel_pipe_wm *r2)
2607 {
2608 int level, max_level = ilk_wm_max_level(dev);
2609 int level1 = 0, level2 = 0;
2610
2611 for (level = 1; level <= max_level; level++) {
2612 if (r1->wm[level].enable)
2613 level1 = level;
2614 if (r2->wm[level].enable)
2615 level2 = level;
2616 }
2617
2618 if (level1 == level2) {
2619 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2620 return r2;
2621 else
2622 return r1;
2623 } else if (level1 > level2) {
2624 return r1;
2625 } else {
2626 return r2;
2627 }
2628 }
2629
2630 /* dirty bits used to track which watermarks need changes */
2631 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2632 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2633 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2634 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2635 #define WM_DIRTY_FBC (1 << 24)
2636 #define WM_DIRTY_DDB (1 << 25)
2637
2638 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2639 const struct ilk_wm_values *old,
2640 const struct ilk_wm_values *new)
2641 {
2642 unsigned int dirty = 0;
2643 enum pipe pipe;
2644 int wm_lp;
2645
2646 for_each_pipe(dev_priv, pipe) {
2647 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2648 dirty |= WM_DIRTY_LINETIME(pipe);
2649 /* Must disable LP1+ watermarks too */
2650 dirty |= WM_DIRTY_LP_ALL;
2651 }
2652
2653 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2654 dirty |= WM_DIRTY_PIPE(pipe);
2655 /* Must disable LP1+ watermarks too */
2656 dirty |= WM_DIRTY_LP_ALL;
2657 }
2658 }
2659
2660 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2661 dirty |= WM_DIRTY_FBC;
2662 /* Must disable LP1+ watermarks too */
2663 dirty |= WM_DIRTY_LP_ALL;
2664 }
2665
2666 if (old->partitioning != new->partitioning) {
2667 dirty |= WM_DIRTY_DDB;
2668 /* Must disable LP1+ watermarks too */
2669 dirty |= WM_DIRTY_LP_ALL;
2670 }
2671
2672 /* LP1+ watermarks already deemed dirty, no need to continue */
2673 if (dirty & WM_DIRTY_LP_ALL)
2674 return dirty;
2675
2676 /* Find the lowest numbered LP1+ watermark in need of an update... */
2677 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2678 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2679 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2680 break;
2681 }
2682
2683 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2684 for (; wm_lp <= 3; wm_lp++)
2685 dirty |= WM_DIRTY_LP(wm_lp);
2686
2687 return dirty;
2688 }
2689
2690 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2691 unsigned int dirty)
2692 {
2693 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2694 bool changed = false;
2695
2696 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2697 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2698 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2699 changed = true;
2700 }
2701 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2702 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2703 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2704 changed = true;
2705 }
2706 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2707 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2708 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2709 changed = true;
2710 }
2711
2712 /*
2713 * Don't touch WM1S_LP_EN here.
2714 * Doing so could cause underruns.
2715 */
2716
2717 return changed;
2718 }
2719
2720 /*
2721 * The spec says we shouldn't write when we don't need, because every write
2722 * causes WMs to be re-evaluated, expending some power.
2723 */
2724 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2725 struct ilk_wm_values *results)
2726 {
2727 struct drm_device *dev = dev_priv->dev;
2728 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2729 unsigned int dirty;
2730 uint32_t val;
2731
2732 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2733 if (!dirty)
2734 return;
2735
2736 _ilk_disable_lp_wm(dev_priv, dirty);
2737
2738 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2739 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2740 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2741 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2742 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2743 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2744
2745 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2746 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2747 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2748 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2749 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2750 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2751
2752 if (dirty & WM_DIRTY_DDB) {
2753 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2754 val = I915_READ(WM_MISC);
2755 if (results->partitioning == INTEL_DDB_PART_1_2)
2756 val &= ~WM_MISC_DATA_PARTITION_5_6;
2757 else
2758 val |= WM_MISC_DATA_PARTITION_5_6;
2759 I915_WRITE(WM_MISC, val);
2760 } else {
2761 val = I915_READ(DISP_ARB_CTL2);
2762 if (results->partitioning == INTEL_DDB_PART_1_2)
2763 val &= ~DISP_DATA_PARTITION_5_6;
2764 else
2765 val |= DISP_DATA_PARTITION_5_6;
2766 I915_WRITE(DISP_ARB_CTL2, val);
2767 }
2768 }
2769
2770 if (dirty & WM_DIRTY_FBC) {
2771 val = I915_READ(DISP_ARB_CTL);
2772 if (results->enable_fbc_wm)
2773 val &= ~DISP_FBC_WM_DIS;
2774 else
2775 val |= DISP_FBC_WM_DIS;
2776 I915_WRITE(DISP_ARB_CTL, val);
2777 }
2778
2779 if (dirty & WM_DIRTY_LP(1) &&
2780 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2781 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2782
2783 if (INTEL_INFO(dev)->gen >= 7) {
2784 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2785 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2786 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2787 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2788 }
2789
2790 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2791 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2792 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2793 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2794 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2795 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2796
2797 dev_priv->wm.hw = *results;
2798 }
2799
2800 static bool ilk_disable_lp_wm(struct drm_device *dev)
2801 {
2802 struct drm_i915_private *dev_priv = dev->dev_private;
2803
2804 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2805 }
2806
2807 /*
2808 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2809 * different active planes.
2810 */
2811
2812 #define SKL_DDB_SIZE 896 /* in blocks */
2813 #define BXT_DDB_SIZE 512
2814
2815 static void
2816 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2817 struct drm_crtc *for_crtc,
2818 const struct intel_wm_config *config,
2819 const struct skl_pipe_wm_parameters *params,
2820 struct skl_ddb_entry *alloc /* out */)
2821 {
2822 struct drm_crtc *crtc;
2823 unsigned int pipe_size, ddb_size;
2824 int nth_active_pipe;
2825
2826 if (!params->active) {
2827 alloc->start = 0;
2828 alloc->end = 0;
2829 return;
2830 }
2831
2832 if (IS_BROXTON(dev))
2833 ddb_size = BXT_DDB_SIZE;
2834 else
2835 ddb_size = SKL_DDB_SIZE;
2836
2837 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2838
2839 nth_active_pipe = 0;
2840 for_each_crtc(dev, crtc) {
2841 if (!to_intel_crtc(crtc)->active)
2842 continue;
2843
2844 if (crtc == for_crtc)
2845 break;
2846
2847 nth_active_pipe++;
2848 }
2849
2850 pipe_size = ddb_size / config->num_pipes_active;
2851 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2852 alloc->end = alloc->start + pipe_size;
2853 }
2854
2855 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2856 {
2857 if (config->num_pipes_active == 1)
2858 return 32;
2859
2860 return 8;
2861 }
2862
2863 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2864 {
2865 entry->start = reg & 0x3ff;
2866 entry->end = (reg >> 16) & 0x3ff;
2867 if (entry->end)
2868 entry->end += 1;
2869 }
2870
2871 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2872 struct skl_ddb_allocation *ddb /* out */)
2873 {
2874 enum pipe pipe;
2875 int plane;
2876 u32 val;
2877
2878 for_each_pipe(dev_priv, pipe) {
2879 for_each_plane(dev_priv, pipe, plane) {
2880 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2881 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2882 val);
2883 }
2884
2885 val = I915_READ(CUR_BUF_CFG(pipe));
2886 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2887 val);
2888 }
2889 }
2890
2891 static unsigned int
2892 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
2893 {
2894
2895 /* for planar format */
2896 if (p->y_bytes_per_pixel) {
2897 if (y) /* y-plane data rate */
2898 return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2899 else /* uv-plane data rate */
2900 return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2901 }
2902
2903 /* for packed formats */
2904 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2905 }
2906
2907 /*
2908 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2909 * a 8192x4096@32bpp framebuffer:
2910 * 3 * 4096 * 8192 * 4 < 2^32
2911 */
2912 static unsigned int
2913 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2914 const struct skl_pipe_wm_parameters *params)
2915 {
2916 unsigned int total_data_rate = 0;
2917 int plane;
2918
2919 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2920 const struct intel_plane_wm_parameters *p;
2921
2922 p = &params->plane[plane];
2923 if (!p->enabled)
2924 continue;
2925
2926 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2927 if (p->y_bytes_per_pixel) {
2928 total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2929 }
2930 }
2931
2932 return total_data_rate;
2933 }
2934
2935 static void
2936 skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2937 const struct intel_wm_config *config,
2938 const struct skl_pipe_wm_parameters *params,
2939 struct skl_ddb_allocation *ddb /* out */)
2940 {
2941 struct drm_device *dev = crtc->dev;
2942 struct drm_i915_private *dev_priv = dev->dev_private;
2943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2944 enum pipe pipe = intel_crtc->pipe;
2945 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2946 uint16_t alloc_size, start, cursor_blocks;
2947 uint16_t minimum[I915_MAX_PLANES];
2948 uint16_t y_minimum[I915_MAX_PLANES];
2949 unsigned int total_data_rate;
2950 int plane;
2951
2952 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2953 alloc_size = skl_ddb_entry_size(alloc);
2954 if (alloc_size == 0) {
2955 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2956 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2957 sizeof(ddb->plane[pipe][PLANE_CURSOR]));
2958 return;
2959 }
2960
2961 cursor_blocks = skl_cursor_allocation(config);
2962 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2963 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
2964
2965 alloc_size -= cursor_blocks;
2966 alloc->end -= cursor_blocks;
2967
2968 /* 1. Allocate the mininum required blocks for each active plane */
2969 for_each_plane(dev_priv, pipe, plane) {
2970 const struct intel_plane_wm_parameters *p;
2971
2972 p = &params->plane[plane];
2973 if (!p->enabled)
2974 continue;
2975
2976 minimum[plane] = 8;
2977 alloc_size -= minimum[plane];
2978 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
2979 alloc_size -= y_minimum[plane];
2980 }
2981
2982 /*
2983 * 2. Distribute the remaining space in proportion to the amount of
2984 * data each plane needs to fetch from memory.
2985 *
2986 * FIXME: we may not allocate every single block here.
2987 */
2988 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
2989
2990 start = alloc->start;
2991 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2992 const struct intel_plane_wm_parameters *p;
2993 unsigned int data_rate, y_data_rate;
2994 uint16_t plane_blocks, y_plane_blocks = 0;
2995
2996 p = &params->plane[plane];
2997 if (!p->enabled)
2998 continue;
2999
3000 data_rate = skl_plane_relative_data_rate(p, 0);
3001
3002 /*
3003 * allocation for (packed formats) or (uv-plane part of planar format):
3004 * promote the expression to 64 bits to avoid overflowing, the
3005 * result is < available as data_rate / total_data_rate < 1
3006 */
3007 plane_blocks = minimum[plane];
3008 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3009 total_data_rate);
3010
3011 ddb->plane[pipe][plane].start = start;
3012 ddb->plane[pipe][plane].end = start + plane_blocks;
3013
3014 start += plane_blocks;
3015
3016 /*
3017 * allocation for y_plane part of planar format:
3018 */
3019 if (p->y_bytes_per_pixel) {
3020 y_data_rate = skl_plane_relative_data_rate(p, 1);
3021 y_plane_blocks = y_minimum[plane];
3022 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3023 total_data_rate);
3024
3025 ddb->y_plane[pipe][plane].start = start;
3026 ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
3027
3028 start += y_plane_blocks;
3029 }
3030
3031 }
3032
3033 }
3034
3035 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3036 {
3037 /* TODO: Take into account the scalers once we support them */
3038 return config->base.adjusted_mode.crtc_clock;
3039 }
3040
3041 /*
3042 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3043 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3044 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3045 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3046 */
3047 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3048 uint32_t latency)
3049 {
3050 uint32_t wm_intermediate_val, ret;
3051
3052 if (latency == 0)
3053 return UINT_MAX;
3054
3055 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
3056 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3057
3058 return ret;
3059 }
3060
3061 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3062 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
3063 uint64_t tiling, uint32_t latency)
3064 {
3065 uint32_t ret;
3066 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3067 uint32_t wm_intermediate_val;
3068
3069 if (latency == 0)
3070 return UINT_MAX;
3071
3072 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
3073
3074 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3075 tiling == I915_FORMAT_MOD_Yf_TILED) {
3076 plane_bytes_per_line *= 4;
3077 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3078 plane_blocks_per_line /= 4;
3079 } else {
3080 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3081 }
3082
3083 wm_intermediate_val = latency * pixel_rate;
3084 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3085 plane_blocks_per_line;
3086
3087 return ret;
3088 }
3089
3090 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3091 const struct intel_crtc *intel_crtc)
3092 {
3093 struct drm_device *dev = intel_crtc->base.dev;
3094 struct drm_i915_private *dev_priv = dev->dev_private;
3095 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3096 enum pipe pipe = intel_crtc->pipe;
3097
3098 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3099 sizeof(new_ddb->plane[pipe])))
3100 return true;
3101
3102 if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR],
3103 sizeof(new_ddb->plane[pipe][PLANE_CURSOR])))
3104 return true;
3105
3106 return false;
3107 }
3108
3109 static void skl_compute_wm_global_parameters(struct drm_device *dev,
3110 struct intel_wm_config *config)
3111 {
3112 struct drm_crtc *crtc;
3113 struct drm_plane *plane;
3114
3115 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3116 config->num_pipes_active += to_intel_crtc(crtc)->active;
3117
3118 /* FIXME: I don't think we need those two global parameters on SKL */
3119 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3120 struct intel_plane *intel_plane = to_intel_plane(plane);
3121
3122 config->sprites_enabled |= intel_plane->wm.enabled;
3123 config->sprites_scaled |= intel_plane->wm.scaled;
3124 }
3125 }
3126
3127 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3128 struct skl_pipe_wm_parameters *p)
3129 {
3130 struct drm_device *dev = crtc->dev;
3131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3132 enum pipe pipe = intel_crtc->pipe;
3133 struct drm_plane *plane;
3134 struct drm_framebuffer *fb;
3135 int i = 1; /* Index for sprite planes start */
3136
3137 p->active = intel_crtc->active;
3138 if (p->active) {
3139 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
3140 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
3141
3142 fb = crtc->primary->state->fb;
3143 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
3144 if (fb) {
3145 p->plane[0].enabled = true;
3146 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3147 drm_format_plane_cpp(fb->pixel_format, 1) :
3148 drm_format_plane_cpp(fb->pixel_format, 0);
3149 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3150 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
3151 p->plane[0].tiling = fb->modifier[0];
3152 } else {
3153 p->plane[0].enabled = false;
3154 p->plane[0].bytes_per_pixel = 0;
3155 p->plane[0].y_bytes_per_pixel = 0;
3156 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
3157 }
3158 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
3159 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
3160 p->plane[0].rotation = crtc->primary->state->rotation;
3161
3162 fb = crtc->cursor->state->fb;
3163 p->plane[PLANE_CURSOR].y_bytes_per_pixel = 0;
3164 if (fb) {
3165 p->plane[PLANE_CURSOR].enabled = true;
3166 p->plane[PLANE_CURSOR].bytes_per_pixel = fb->bits_per_pixel / 8;
3167 p->plane[PLANE_CURSOR].horiz_pixels = crtc->cursor->state->crtc_w;
3168 p->plane[PLANE_CURSOR].vert_pixels = crtc->cursor->state->crtc_h;
3169 } else {
3170 p->plane[PLANE_CURSOR].enabled = false;
3171 p->plane[PLANE_CURSOR].bytes_per_pixel = 0;
3172 p->plane[PLANE_CURSOR].horiz_pixels = 64;
3173 p->plane[PLANE_CURSOR].vert_pixels = 64;
3174 }
3175 }
3176
3177 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3178 struct intel_plane *intel_plane = to_intel_plane(plane);
3179
3180 if (intel_plane->pipe == pipe &&
3181 plane->type == DRM_PLANE_TYPE_OVERLAY)
3182 p->plane[i++] = intel_plane->wm;
3183 }
3184 }
3185
3186 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3187 struct skl_pipe_wm_parameters *p,
3188 struct intel_plane_wm_parameters *p_params,
3189 uint16_t ddb_allocation,
3190 int level,
3191 uint16_t *out_blocks, /* out */
3192 uint8_t *out_lines /* out */)
3193 {
3194 uint32_t latency = dev_priv->wm.skl_latency[level];
3195 uint32_t method1, method2;
3196 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3197 uint32_t res_blocks, res_lines;
3198 uint32_t selected_result;
3199 uint8_t bytes_per_pixel;
3200
3201 if (latency == 0 || !p->active || !p_params->enabled)
3202 return false;
3203
3204 bytes_per_pixel = p_params->y_bytes_per_pixel ?
3205 p_params->y_bytes_per_pixel :
3206 p_params->bytes_per_pixel;
3207 method1 = skl_wm_method1(p->pixel_rate,
3208 bytes_per_pixel,
3209 latency);
3210 method2 = skl_wm_method2(p->pixel_rate,
3211 p->pipe_htotal,
3212 p_params->horiz_pixels,
3213 bytes_per_pixel,
3214 p_params->tiling,
3215 latency);
3216
3217 plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
3218 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3219
3220 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3221 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
3222 uint32_t min_scanlines = 4;
3223 uint32_t y_tile_minimum;
3224 if (intel_rotation_90_or_270(p_params->rotation)) {
3225 switch (p_params->bytes_per_pixel) {
3226 case 1:
3227 min_scanlines = 16;
3228 break;
3229 case 2:
3230 min_scanlines = 8;
3231 break;
3232 case 8:
3233 WARN(1, "Unsupported pixel depth for rotation");
3234 }
3235 }
3236 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3237 selected_result = max(method2, y_tile_minimum);
3238 } else {
3239 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3240 selected_result = min(method1, method2);
3241 else
3242 selected_result = method1;
3243 }
3244
3245 res_blocks = selected_result + 1;
3246 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3247
3248 if (level >= 1 && level <= 7) {
3249 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3250 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
3251 res_lines += 4;
3252 else
3253 res_blocks++;
3254 }
3255
3256 if (res_blocks >= ddb_allocation || res_lines > 31)
3257 return false;
3258
3259 *out_blocks = res_blocks;
3260 *out_lines = res_lines;
3261
3262 return true;
3263 }
3264
3265 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3266 struct skl_ddb_allocation *ddb,
3267 struct skl_pipe_wm_parameters *p,
3268 enum pipe pipe,
3269 int level,
3270 int num_planes,
3271 struct skl_wm_level *result)
3272 {
3273 uint16_t ddb_blocks;
3274 int i;
3275
3276 for (i = 0; i < num_planes; i++) {
3277 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3278
3279 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3280 p, &p->plane[i],
3281 ddb_blocks,
3282 level,
3283 &result->plane_res_b[i],
3284 &result->plane_res_l[i]);
3285 }
3286
3287 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][PLANE_CURSOR]);
3288 result->plane_en[PLANE_CURSOR] = skl_compute_plane_wm(dev_priv, p,
3289 &p->plane[PLANE_CURSOR],
3290 ddb_blocks, level,
3291 &result->plane_res_b[PLANE_CURSOR],
3292 &result->plane_res_l[PLANE_CURSOR]);
3293 }
3294
3295 static uint32_t
3296 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3297 {
3298 if (!to_intel_crtc(crtc)->active)
3299 return 0;
3300
3301 if (WARN_ON(p->pixel_rate == 0))
3302 return 0;
3303
3304 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3305 }
3306
3307 static void skl_compute_transition_wm(struct drm_crtc *crtc,
3308 struct skl_pipe_wm_parameters *params,
3309 struct skl_wm_level *trans_wm /* out */)
3310 {
3311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3312 int i;
3313
3314 if (!params->active)
3315 return;
3316
3317 /* Until we know more, just disable transition WMs */
3318 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3319 trans_wm->plane_en[i] = false;
3320 trans_wm->plane_en[PLANE_CURSOR] = false;
3321 }
3322
3323 static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3324 struct skl_ddb_allocation *ddb,
3325 struct skl_pipe_wm_parameters *params,
3326 struct skl_pipe_wm *pipe_wm)
3327 {
3328 struct drm_device *dev = crtc->dev;
3329 const struct drm_i915_private *dev_priv = dev->dev_private;
3330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3331 int level, max_level = ilk_wm_max_level(dev);
3332
3333 for (level = 0; level <= max_level; level++) {
3334 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3335 level, intel_num_planes(intel_crtc),
3336 &pipe_wm->wm[level]);
3337 }
3338 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3339
3340 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
3341 }
3342
3343 static void skl_compute_wm_results(struct drm_device *dev,
3344 struct skl_pipe_wm_parameters *p,
3345 struct skl_pipe_wm *p_wm,
3346 struct skl_wm_values *r,
3347 struct intel_crtc *intel_crtc)
3348 {
3349 int level, max_level = ilk_wm_max_level(dev);
3350 enum pipe pipe = intel_crtc->pipe;
3351 uint32_t temp;
3352 int i;
3353
3354 for (level = 0; level <= max_level; level++) {
3355 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3356 temp = 0;
3357
3358 temp |= p_wm->wm[level].plane_res_l[i] <<
3359 PLANE_WM_LINES_SHIFT;
3360 temp |= p_wm->wm[level].plane_res_b[i];
3361 if (p_wm->wm[level].plane_en[i])
3362 temp |= PLANE_WM_EN;
3363
3364 r->plane[pipe][i][level] = temp;
3365 }
3366
3367 temp = 0;
3368
3369 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3370 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3371
3372 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3373 temp |= PLANE_WM_EN;
3374
3375 r->plane[pipe][PLANE_CURSOR][level] = temp;
3376
3377 }
3378
3379 /* transition WMs */
3380 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3381 temp = 0;
3382 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3383 temp |= p_wm->trans_wm.plane_res_b[i];
3384 if (p_wm->trans_wm.plane_en[i])
3385 temp |= PLANE_WM_EN;
3386
3387 r->plane_trans[pipe][i] = temp;
3388 }
3389
3390 temp = 0;
3391 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3392 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3393 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3394 temp |= PLANE_WM_EN;
3395
3396 r->plane_trans[pipe][PLANE_CURSOR] = temp;
3397
3398 r->wm_linetime[pipe] = p_wm->linetime;
3399 }
3400
3401 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3402 const struct skl_ddb_entry *entry)
3403 {
3404 if (entry->end)
3405 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3406 else
3407 I915_WRITE(reg, 0);
3408 }
3409
3410 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3411 const struct skl_wm_values *new)
3412 {
3413 struct drm_device *dev = dev_priv->dev;
3414 struct intel_crtc *crtc;
3415
3416 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3417 int i, level, max_level = ilk_wm_max_level(dev);
3418 enum pipe pipe = crtc->pipe;
3419
3420 if (!new->dirty[pipe])
3421 continue;
3422
3423 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3424
3425 for (level = 0; level <= max_level; level++) {
3426 for (i = 0; i < intel_num_planes(crtc); i++)
3427 I915_WRITE(PLANE_WM(pipe, i, level),
3428 new->plane[pipe][i][level]);
3429 I915_WRITE(CUR_WM(pipe, level),
3430 new->plane[pipe][PLANE_CURSOR][level]);
3431 }
3432 for (i = 0; i < intel_num_planes(crtc); i++)
3433 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3434 new->plane_trans[pipe][i]);
3435 I915_WRITE(CUR_WM_TRANS(pipe),
3436 new->plane_trans[pipe][PLANE_CURSOR]);
3437
3438 for (i = 0; i < intel_num_planes(crtc); i++) {
3439 skl_ddb_entry_write(dev_priv,
3440 PLANE_BUF_CFG(pipe, i),
3441 &new->ddb.plane[pipe][i]);
3442 skl_ddb_entry_write(dev_priv,
3443 PLANE_NV12_BUF_CFG(pipe, i),
3444 &new->ddb.y_plane[pipe][i]);
3445 }
3446
3447 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3448 &new->ddb.plane[pipe][PLANE_CURSOR]);
3449 }
3450 }
3451
3452 /*
3453 * When setting up a new DDB allocation arrangement, we need to correctly
3454 * sequence the times at which the new allocations for the pipes are taken into
3455 * account or we'll have pipes fetching from space previously allocated to
3456 * another pipe.
3457 *
3458 * Roughly the sequence looks like:
3459 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3460 * overlapping with a previous light-up pipe (another way to put it is:
3461 * pipes with their new allocation strickly included into their old ones).
3462 * 2. re-allocate the other pipes that get their allocation reduced
3463 * 3. allocate the pipes having their allocation increased
3464 *
3465 * Steps 1. and 2. are here to take care of the following case:
3466 * - Initially DDB looks like this:
3467 * | B | C |
3468 * - enable pipe A.
3469 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3470 * allocation
3471 * | A | B | C |
3472 *
3473 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3474 */
3475
3476 static void
3477 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3478 {
3479 int plane;
3480
3481 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3482
3483 for_each_plane(dev_priv, pipe, plane) {
3484 I915_WRITE(PLANE_SURF(pipe, plane),
3485 I915_READ(PLANE_SURF(pipe, plane)));
3486 }
3487 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3488 }
3489
3490 static bool
3491 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3492 const struct skl_ddb_allocation *new,
3493 enum pipe pipe)
3494 {
3495 uint16_t old_size, new_size;
3496
3497 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3498 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3499
3500 return old_size != new_size &&
3501 new->pipe[pipe].start >= old->pipe[pipe].start &&
3502 new->pipe[pipe].end <= old->pipe[pipe].end;
3503 }
3504
3505 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3506 struct skl_wm_values *new_values)
3507 {
3508 struct drm_device *dev = dev_priv->dev;
3509 struct skl_ddb_allocation *cur_ddb, *new_ddb;
3510 bool reallocated[I915_MAX_PIPES] = {};
3511 struct intel_crtc *crtc;
3512 enum pipe pipe;
3513
3514 new_ddb = &new_values->ddb;
3515 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3516
3517 /*
3518 * First pass: flush the pipes with the new allocation contained into
3519 * the old space.
3520 *
3521 * We'll wait for the vblank on those pipes to ensure we can safely
3522 * re-allocate the freed space without this pipe fetching from it.
3523 */
3524 for_each_intel_crtc(dev, crtc) {
3525 if (!crtc->active)
3526 continue;
3527
3528 pipe = crtc->pipe;
3529
3530 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3531 continue;
3532
3533 skl_wm_flush_pipe(dev_priv, pipe, 1);
3534 intel_wait_for_vblank(dev, pipe);
3535
3536 reallocated[pipe] = true;
3537 }
3538
3539
3540 /*
3541 * Second pass: flush the pipes that are having their allocation
3542 * reduced, but overlapping with a previous allocation.
3543 *
3544 * Here as well we need to wait for the vblank to make sure the freed
3545 * space is not used anymore.
3546 */
3547 for_each_intel_crtc(dev, crtc) {
3548 if (!crtc->active)
3549 continue;
3550
3551 pipe = crtc->pipe;
3552
3553 if (reallocated[pipe])
3554 continue;
3555
3556 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3557 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3558 skl_wm_flush_pipe(dev_priv, pipe, 2);
3559 intel_wait_for_vblank(dev, pipe);
3560 reallocated[pipe] = true;
3561 }
3562 }
3563
3564 /*
3565 * Third pass: flush the pipes that got more space allocated.
3566 *
3567 * We don't need to actively wait for the update here, next vblank
3568 * will just get more DDB space with the correct WM values.
3569 */
3570 for_each_intel_crtc(dev, crtc) {
3571 if (!crtc->active)
3572 continue;
3573
3574 pipe = crtc->pipe;
3575
3576 /*
3577 * At this point, only the pipes more space than before are
3578 * left to re-allocate.
3579 */
3580 if (reallocated[pipe])
3581 continue;
3582
3583 skl_wm_flush_pipe(dev_priv, pipe, 3);
3584 }
3585 }
3586
3587 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3588 struct skl_pipe_wm_parameters *params,
3589 struct intel_wm_config *config,
3590 struct skl_ddb_allocation *ddb, /* out */
3591 struct skl_pipe_wm *pipe_wm /* out */)
3592 {
3593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3594
3595 skl_compute_wm_pipe_parameters(crtc, params);
3596 skl_allocate_pipe_ddb(crtc, config, params, ddb);
3597 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3598
3599 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3600 return false;
3601
3602 intel_crtc->wm.skl_active = *pipe_wm;
3603
3604 return true;
3605 }
3606
3607 static void skl_update_other_pipe_wm(struct drm_device *dev,
3608 struct drm_crtc *crtc,
3609 struct intel_wm_config *config,
3610 struct skl_wm_values *r)
3611 {
3612 struct intel_crtc *intel_crtc;
3613 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3614
3615 /*
3616 * If the WM update hasn't changed the allocation for this_crtc (the
3617 * crtc we are currently computing the new WM values for), other
3618 * enabled crtcs will keep the same allocation and we don't need to
3619 * recompute anything for them.
3620 */
3621 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3622 return;
3623
3624 /*
3625 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3626 * other active pipes need new DDB allocation and WM values.
3627 */
3628 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3629 base.head) {
3630 struct skl_pipe_wm_parameters params = {};
3631 struct skl_pipe_wm pipe_wm = {};
3632 bool wm_changed;
3633
3634 if (this_crtc->pipe == intel_crtc->pipe)
3635 continue;
3636
3637 if (!intel_crtc->active)
3638 continue;
3639
3640 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3641 &params, config,
3642 &r->ddb, &pipe_wm);
3643
3644 /*
3645 * If we end up re-computing the other pipe WM values, it's
3646 * because it was really needed, so we expect the WM values to
3647 * be different.
3648 */
3649 WARN_ON(!wm_changed);
3650
3651 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3652 r->dirty[intel_crtc->pipe] = true;
3653 }
3654 }
3655
3656 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3657 {
3658 watermarks->wm_linetime[pipe] = 0;
3659 memset(watermarks->plane[pipe], 0,
3660 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3661 memset(watermarks->plane_trans[pipe],
3662 0, sizeof(uint32_t) * I915_MAX_PLANES);
3663 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3664
3665 /* Clear ddb entries for pipe */
3666 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3667 memset(&watermarks->ddb.plane[pipe], 0,
3668 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3669 memset(&watermarks->ddb.y_plane[pipe], 0,
3670 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3671 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3672 sizeof(struct skl_ddb_entry));
3673
3674 }
3675
3676 static void skl_update_wm(struct drm_crtc *crtc)
3677 {
3678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3679 struct drm_device *dev = crtc->dev;
3680 struct drm_i915_private *dev_priv = dev->dev_private;
3681 struct skl_pipe_wm_parameters params = {};
3682 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3683 struct skl_pipe_wm pipe_wm = {};
3684 struct intel_wm_config config = {};
3685
3686
3687 /* Clear all dirty flags */
3688 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3689
3690 skl_clear_wm(results, intel_crtc->pipe);
3691
3692 skl_compute_wm_global_parameters(dev, &config);
3693
3694 if (!skl_update_pipe_wm(crtc, &params, &config,
3695 &results->ddb, &pipe_wm))
3696 return;
3697
3698 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3699 results->dirty[intel_crtc->pipe] = true;
3700
3701 skl_update_other_pipe_wm(dev, crtc, &config, results);
3702 skl_write_wm_values(dev_priv, results);
3703 skl_flush_wm_values(dev_priv, results);
3704
3705 /* store the new configuration */
3706 dev_priv->wm.skl_hw = *results;
3707 }
3708
3709 static void
3710 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3711 uint32_t sprite_width, uint32_t sprite_height,
3712 int pixel_size, bool enabled, bool scaled)
3713 {
3714 struct intel_plane *intel_plane = to_intel_plane(plane);
3715 struct drm_framebuffer *fb = plane->state->fb;
3716
3717 intel_plane->wm.enabled = enabled;
3718 intel_plane->wm.scaled = scaled;
3719 intel_plane->wm.horiz_pixels = sprite_width;
3720 intel_plane->wm.vert_pixels = sprite_height;
3721 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3722
3723 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3724 intel_plane->wm.bytes_per_pixel =
3725 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3726 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3727 intel_plane->wm.y_bytes_per_pixel =
3728 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3729 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3730
3731 /*
3732 * Framebuffer can be NULL on plane disable, but it does not
3733 * matter for watermarks if we assume no tiling in that case.
3734 */
3735 if (fb)
3736 intel_plane->wm.tiling = fb->modifier[0];
3737 intel_plane->wm.rotation = plane->state->rotation;
3738
3739 skl_update_wm(crtc);
3740 }
3741
3742 static void ilk_update_wm(struct drm_crtc *crtc)
3743 {
3744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3745 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3746 struct drm_device *dev = crtc->dev;
3747 struct drm_i915_private *dev_priv = dev->dev_private;
3748 struct ilk_wm_maximums max;
3749 struct ilk_wm_values results = {};
3750 enum intel_ddb_partitioning partitioning;
3751 struct intel_pipe_wm pipe_wm = {};
3752 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3753 struct intel_wm_config config = {};
3754
3755 WARN_ON(cstate->base.active != intel_crtc->active);
3756
3757 intel_compute_pipe_wm(cstate, &pipe_wm);
3758
3759 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3760 return;
3761
3762 intel_crtc->wm.active = pipe_wm;
3763
3764 ilk_compute_wm_config(dev, &config);
3765
3766 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3767 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3768
3769 /* 5/6 split only in single pipe config on IVB+ */
3770 if (INTEL_INFO(dev)->gen >= 7 &&
3771 config.num_pipes_active == 1 && config.sprites_enabled) {
3772 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3773 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3774
3775 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3776 } else {
3777 best_lp_wm = &lp_wm_1_2;
3778 }
3779
3780 partitioning = (best_lp_wm == &lp_wm_1_2) ?
3781 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3782
3783 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3784
3785 ilk_write_wm_values(dev_priv, &results);
3786 }
3787
3788 static void
3789 ilk_update_sprite_wm(struct drm_plane *plane,
3790 struct drm_crtc *crtc,
3791 uint32_t sprite_width, uint32_t sprite_height,
3792 int pixel_size, bool enabled, bool scaled)
3793 {
3794 struct drm_device *dev = plane->dev;
3795 struct intel_plane *intel_plane = to_intel_plane(plane);
3796
3797 /*
3798 * IVB workaround: must disable low power watermarks for at least
3799 * one frame before enabling scaling. LP watermarks can be re-enabled
3800 * when scaling is disabled.
3801 *
3802 * WaCxSRDisabledForSpriteScaling:ivb
3803 */
3804 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3805 intel_wait_for_vblank(dev, intel_plane->pipe);
3806
3807 ilk_update_wm(crtc);
3808 }
3809
3810 static void skl_pipe_wm_active_state(uint32_t val,
3811 struct skl_pipe_wm *active,
3812 bool is_transwm,
3813 bool is_cursor,
3814 int i,
3815 int level)
3816 {
3817 bool is_enabled = (val & PLANE_WM_EN) != 0;
3818
3819 if (!is_transwm) {
3820 if (!is_cursor) {
3821 active->wm[level].plane_en[i] = is_enabled;
3822 active->wm[level].plane_res_b[i] =
3823 val & PLANE_WM_BLOCKS_MASK;
3824 active->wm[level].plane_res_l[i] =
3825 (val >> PLANE_WM_LINES_SHIFT) &
3826 PLANE_WM_LINES_MASK;
3827 } else {
3828 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3829 active->wm[level].plane_res_b[PLANE_CURSOR] =
3830 val & PLANE_WM_BLOCKS_MASK;
3831 active->wm[level].plane_res_l[PLANE_CURSOR] =
3832 (val >> PLANE_WM_LINES_SHIFT) &
3833 PLANE_WM_LINES_MASK;
3834 }
3835 } else {
3836 if (!is_cursor) {
3837 active->trans_wm.plane_en[i] = is_enabled;
3838 active->trans_wm.plane_res_b[i] =
3839 val & PLANE_WM_BLOCKS_MASK;
3840 active->trans_wm.plane_res_l[i] =
3841 (val >> PLANE_WM_LINES_SHIFT) &
3842 PLANE_WM_LINES_MASK;
3843 } else {
3844 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3845 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3846 val & PLANE_WM_BLOCKS_MASK;
3847 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3848 (val >> PLANE_WM_LINES_SHIFT) &
3849 PLANE_WM_LINES_MASK;
3850 }
3851 }
3852 }
3853
3854 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3855 {
3856 struct drm_device *dev = crtc->dev;
3857 struct drm_i915_private *dev_priv = dev->dev_private;
3858 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3860 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3861 enum pipe pipe = intel_crtc->pipe;
3862 int level, i, max_level;
3863 uint32_t temp;
3864
3865 max_level = ilk_wm_max_level(dev);
3866
3867 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3868
3869 for (level = 0; level <= max_level; level++) {
3870 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3871 hw->plane[pipe][i][level] =
3872 I915_READ(PLANE_WM(pipe, i, level));
3873 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3874 }
3875
3876 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3877 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3878 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3879
3880 if (!intel_crtc->active)
3881 return;
3882
3883 hw->dirty[pipe] = true;
3884
3885 active->linetime = hw->wm_linetime[pipe];
3886
3887 for (level = 0; level <= max_level; level++) {
3888 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3889 temp = hw->plane[pipe][i][level];
3890 skl_pipe_wm_active_state(temp, active, false,
3891 false, i, level);
3892 }
3893 temp = hw->plane[pipe][PLANE_CURSOR][level];
3894 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3895 }
3896
3897 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3898 temp = hw->plane_trans[pipe][i];
3899 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3900 }
3901
3902 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3903 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3904 }
3905
3906 void skl_wm_get_hw_state(struct drm_device *dev)
3907 {
3908 struct drm_i915_private *dev_priv = dev->dev_private;
3909 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3910 struct drm_crtc *crtc;
3911
3912 skl_ddb_get_hw_state(dev_priv, ddb);
3913 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3914 skl_pipe_wm_get_hw_state(crtc);
3915 }
3916
3917 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3918 {
3919 struct drm_device *dev = crtc->dev;
3920 struct drm_i915_private *dev_priv = dev->dev_private;
3921 struct ilk_wm_values *hw = &dev_priv->wm.hw;
3922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3923 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3924 enum pipe pipe = intel_crtc->pipe;
3925 static const unsigned int wm0_pipe_reg[] = {
3926 [PIPE_A] = WM0_PIPEA_ILK,
3927 [PIPE_B] = WM0_PIPEB_ILK,
3928 [PIPE_C] = WM0_PIPEC_IVB,
3929 };
3930
3931 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3932 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3933 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3934
3935 active->pipe_enabled = intel_crtc->active;
3936
3937 if (active->pipe_enabled) {
3938 u32 tmp = hw->wm_pipe[pipe];
3939
3940 /*
3941 * For active pipes LP0 watermark is marked as
3942 * enabled, and LP1+ watermaks as disabled since
3943 * we can't really reverse compute them in case
3944 * multiple pipes are active.
3945 */
3946 active->wm[0].enable = true;
3947 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3948 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3949 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3950 active->linetime = hw->wm_linetime[pipe];
3951 } else {
3952 int level, max_level = ilk_wm_max_level(dev);
3953
3954 /*
3955 * For inactive pipes, all watermark levels
3956 * should be marked as enabled but zeroed,
3957 * which is what we'd compute them to.
3958 */
3959 for (level = 0; level <= max_level; level++)
3960 active->wm[level].enable = true;
3961 }
3962 }
3963
3964 #define _FW_WM(value, plane) \
3965 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3966 #define _FW_WM_VLV(value, plane) \
3967 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3968
3969 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3970 struct vlv_wm_values *wm)
3971 {
3972 enum pipe pipe;
3973 uint32_t tmp;
3974
3975 for_each_pipe(dev_priv, pipe) {
3976 tmp = I915_READ(VLV_DDL(pipe));
3977
3978 wm->ddl[pipe].primary =
3979 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3980 wm->ddl[pipe].cursor =
3981 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3982 wm->ddl[pipe].sprite[0] =
3983 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3984 wm->ddl[pipe].sprite[1] =
3985 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3986 }
3987
3988 tmp = I915_READ(DSPFW1);
3989 wm->sr.plane = _FW_WM(tmp, SR);
3990 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3991 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3992 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3993
3994 tmp = I915_READ(DSPFW2);
3995 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3996 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3997 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3998
3999 tmp = I915_READ(DSPFW3);
4000 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4001
4002 if (IS_CHERRYVIEW(dev_priv)) {
4003 tmp = I915_READ(DSPFW7_CHV);
4004 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4005 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4006
4007 tmp = I915_READ(DSPFW8_CHV);
4008 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4009 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4010
4011 tmp = I915_READ(DSPFW9_CHV);
4012 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4013 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4014
4015 tmp = I915_READ(DSPHOWM);
4016 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4017 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4018 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4019 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4020 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4021 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4022 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4023 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4024 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4025 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4026 } else {
4027 tmp = I915_READ(DSPFW7);
4028 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4029 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4030
4031 tmp = I915_READ(DSPHOWM);
4032 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4033 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4034 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4035 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4036 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4037 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4038 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4039 }
4040 }
4041
4042 #undef _FW_WM
4043 #undef _FW_WM_VLV
4044
4045 void vlv_wm_get_hw_state(struct drm_device *dev)
4046 {
4047 struct drm_i915_private *dev_priv = to_i915(dev);
4048 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4049 struct intel_plane *plane;
4050 enum pipe pipe;
4051 u32 val;
4052
4053 vlv_read_wm_values(dev_priv, wm);
4054
4055 for_each_intel_plane(dev, plane) {
4056 switch (plane->base.type) {
4057 int sprite;
4058 case DRM_PLANE_TYPE_CURSOR:
4059 plane->wm.fifo_size = 63;
4060 break;
4061 case DRM_PLANE_TYPE_PRIMARY:
4062 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4063 break;
4064 case DRM_PLANE_TYPE_OVERLAY:
4065 sprite = plane->plane;
4066 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4067 break;
4068 }
4069 }
4070
4071 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4072 wm->level = VLV_WM_LEVEL_PM2;
4073
4074 if (IS_CHERRYVIEW(dev_priv)) {
4075 mutex_lock(&dev_priv->rps.hw_lock);
4076
4077 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4078 if (val & DSP_MAXFIFO_PM5_ENABLE)
4079 wm->level = VLV_WM_LEVEL_PM5;
4080
4081 /*
4082 * If DDR DVFS is disabled in the BIOS, Punit
4083 * will never ack the request. So if that happens
4084 * assume we don't have to enable/disable DDR DVFS
4085 * dynamically. To test that just set the REQ_ACK
4086 * bit to poke the Punit, but don't change the
4087 * HIGH/LOW bits so that we don't actually change
4088 * the current state.
4089 */
4090 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4091 val |= FORCE_DDR_FREQ_REQ_ACK;
4092 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4093
4094 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4095 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4096 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4097 "assuming DDR DVFS is disabled\n");
4098 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4099 } else {
4100 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4101 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4102 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4103 }
4104
4105 mutex_unlock(&dev_priv->rps.hw_lock);
4106 }
4107
4108 for_each_pipe(dev_priv, pipe)
4109 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4110 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4111 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4112
4113 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4114 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4115 }
4116
4117 void ilk_wm_get_hw_state(struct drm_device *dev)
4118 {
4119 struct drm_i915_private *dev_priv = dev->dev_private;
4120 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4121 struct drm_crtc *crtc;
4122
4123 for_each_crtc(dev, crtc)
4124 ilk_pipe_wm_get_hw_state(crtc);
4125
4126 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4127 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4128 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4129
4130 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4131 if (INTEL_INFO(dev)->gen >= 7) {
4132 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4133 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4134 }
4135
4136 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4137 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4138 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4139 else if (IS_IVYBRIDGE(dev))
4140 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4141 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4142
4143 hw->enable_fbc_wm =
4144 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4145 }
4146
4147 /**
4148 * intel_update_watermarks - update FIFO watermark values based on current modes
4149 *
4150 * Calculate watermark values for the various WM regs based on current mode
4151 * and plane configuration.
4152 *
4153 * There are several cases to deal with here:
4154 * - normal (i.e. non-self-refresh)
4155 * - self-refresh (SR) mode
4156 * - lines are large relative to FIFO size (buffer can hold up to 2)
4157 * - lines are small relative to FIFO size (buffer can hold more than 2
4158 * lines), so need to account for TLB latency
4159 *
4160 * The normal calculation is:
4161 * watermark = dotclock * bytes per pixel * latency
4162 * where latency is platform & configuration dependent (we assume pessimal
4163 * values here).
4164 *
4165 * The SR calculation is:
4166 * watermark = (trunc(latency/line time)+1) * surface width *
4167 * bytes per pixel
4168 * where
4169 * line time = htotal / dotclock
4170 * surface width = hdisplay for normal plane and 64 for cursor
4171 * and latency is assumed to be high, as above.
4172 *
4173 * The final value programmed to the register should always be rounded up,
4174 * and include an extra 2 entries to account for clock crossings.
4175 *
4176 * We don't use the sprite, so we can ignore that. And on Crestline we have
4177 * to set the non-SR watermarks to 8.
4178 */
4179 void intel_update_watermarks(struct drm_crtc *crtc)
4180 {
4181 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4182
4183 if (dev_priv->display.update_wm)
4184 dev_priv->display.update_wm(crtc);
4185 }
4186
4187 void intel_update_sprite_watermarks(struct drm_plane *plane,
4188 struct drm_crtc *crtc,
4189 uint32_t sprite_width,
4190 uint32_t sprite_height,
4191 int pixel_size,
4192 bool enabled, bool scaled)
4193 {
4194 struct drm_i915_private *dev_priv = plane->dev->dev_private;
4195
4196 if (dev_priv->display.update_sprite_wm)
4197 dev_priv->display.update_sprite_wm(plane, crtc,
4198 sprite_width, sprite_height,
4199 pixel_size, enabled, scaled);
4200 }
4201
4202 /**
4203 * Lock protecting IPS related data structures
4204 */
4205 DEFINE_SPINLOCK(mchdev_lock);
4206
4207 /* Global for IPS driver to get at the current i915 device. Protected by
4208 * mchdev_lock. */
4209 static struct drm_i915_private *i915_mch_dev;
4210
4211 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4212 {
4213 struct drm_i915_private *dev_priv = dev->dev_private;
4214 u16 rgvswctl;
4215
4216 assert_spin_locked(&mchdev_lock);
4217
4218 rgvswctl = I915_READ16(MEMSWCTL);
4219 if (rgvswctl & MEMCTL_CMD_STS) {
4220 DRM_DEBUG("gpu busy, RCS change rejected\n");
4221 return false; /* still busy with another command */
4222 }
4223
4224 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4225 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4226 I915_WRITE16(MEMSWCTL, rgvswctl);
4227 POSTING_READ16(MEMSWCTL);
4228
4229 rgvswctl |= MEMCTL_CMD_STS;
4230 I915_WRITE16(MEMSWCTL, rgvswctl);
4231
4232 return true;
4233 }
4234
4235 static void ironlake_enable_drps(struct drm_device *dev)
4236 {
4237 struct drm_i915_private *dev_priv = dev->dev_private;
4238 u32 rgvmodectl = I915_READ(MEMMODECTL);
4239 u8 fmax, fmin, fstart, vstart;
4240
4241 spin_lock_irq(&mchdev_lock);
4242
4243 /* Enable temp reporting */
4244 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4245 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4246
4247 /* 100ms RC evaluation intervals */
4248 I915_WRITE(RCUPEI, 100000);
4249 I915_WRITE(RCDNEI, 100000);
4250
4251 /* Set max/min thresholds to 90ms and 80ms respectively */
4252 I915_WRITE(RCBMAXAVG, 90000);
4253 I915_WRITE(RCBMINAVG, 80000);
4254
4255 I915_WRITE(MEMIHYST, 1);
4256
4257 /* Set up min, max, and cur for interrupt handling */
4258 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4259 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4260 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4261 MEMMODE_FSTART_SHIFT;
4262
4263 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4264 PXVFREQ_PX_SHIFT;
4265
4266 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4267 dev_priv->ips.fstart = fstart;
4268
4269 dev_priv->ips.max_delay = fstart;
4270 dev_priv->ips.min_delay = fmin;
4271 dev_priv->ips.cur_delay = fstart;
4272
4273 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4274 fmax, fmin, fstart);
4275
4276 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4277
4278 /*
4279 * Interrupts will be enabled in ironlake_irq_postinstall
4280 */
4281
4282 I915_WRITE(VIDSTART, vstart);
4283 POSTING_READ(VIDSTART);
4284
4285 rgvmodectl |= MEMMODE_SWMODE_EN;
4286 I915_WRITE(MEMMODECTL, rgvmodectl);
4287
4288 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4289 DRM_ERROR("stuck trying to change perf mode\n");
4290 mdelay(1);
4291
4292 ironlake_set_drps(dev, fstart);
4293
4294 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4295 I915_READ(DDREC) + I915_READ(CSIEC);
4296 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4297 dev_priv->ips.last_count2 = I915_READ(GFXEC);
4298 dev_priv->ips.last_time2 = ktime_get_raw_ns();
4299
4300 spin_unlock_irq(&mchdev_lock);
4301 }
4302
4303 static void ironlake_disable_drps(struct drm_device *dev)
4304 {
4305 struct drm_i915_private *dev_priv = dev->dev_private;
4306 u16 rgvswctl;
4307
4308 spin_lock_irq(&mchdev_lock);
4309
4310 rgvswctl = I915_READ16(MEMSWCTL);
4311
4312 /* Ack interrupts, disable EFC interrupt */
4313 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4314 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4315 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4316 I915_WRITE(DEIIR, DE_PCU_EVENT);
4317 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4318
4319 /* Go back to the starting frequency */
4320 ironlake_set_drps(dev, dev_priv->ips.fstart);
4321 mdelay(1);
4322 rgvswctl |= MEMCTL_CMD_STS;
4323 I915_WRITE(MEMSWCTL, rgvswctl);
4324 mdelay(1);
4325
4326 spin_unlock_irq(&mchdev_lock);
4327 }
4328
4329 /* There's a funny hw issue where the hw returns all 0 when reading from
4330 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4331 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4332 * all limits and the gpu stuck at whatever frequency it is at atm).
4333 */
4334 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4335 {
4336 u32 limits;
4337
4338 /* Only set the down limit when we've reached the lowest level to avoid
4339 * getting more interrupts, otherwise leave this clear. This prevents a
4340 * race in the hw when coming out of rc6: There's a tiny window where
4341 * the hw runs at the minimal clock before selecting the desired
4342 * frequency, if the down threshold expires in that window we will not
4343 * receive a down interrupt. */
4344 if (IS_GEN9(dev_priv->dev)) {
4345 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4346 if (val <= dev_priv->rps.min_freq_softlimit)
4347 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4348 } else {
4349 limits = dev_priv->rps.max_freq_softlimit << 24;
4350 if (val <= dev_priv->rps.min_freq_softlimit)
4351 limits |= dev_priv->rps.min_freq_softlimit << 16;
4352 }
4353
4354 return limits;
4355 }
4356
4357 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4358 {
4359 int new_power;
4360 u32 threshold_up = 0, threshold_down = 0; /* in % */
4361 u32 ei_up = 0, ei_down = 0;
4362
4363 new_power = dev_priv->rps.power;
4364 switch (dev_priv->rps.power) {
4365 case LOW_POWER:
4366 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4367 new_power = BETWEEN;
4368 break;
4369
4370 case BETWEEN:
4371 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4372 new_power = LOW_POWER;
4373 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4374 new_power = HIGH_POWER;
4375 break;
4376
4377 case HIGH_POWER:
4378 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4379 new_power = BETWEEN;
4380 break;
4381 }
4382 /* Max/min bins are special */
4383 if (val <= dev_priv->rps.min_freq_softlimit)
4384 new_power = LOW_POWER;
4385 if (val >= dev_priv->rps.max_freq_softlimit)
4386 new_power = HIGH_POWER;
4387 if (new_power == dev_priv->rps.power)
4388 return;
4389
4390 /* Note the units here are not exactly 1us, but 1280ns. */
4391 switch (new_power) {
4392 case LOW_POWER:
4393 /* Upclock if more than 95% busy over 16ms */
4394 ei_up = 16000;
4395 threshold_up = 95;
4396
4397 /* Downclock if less than 85% busy over 32ms */
4398 ei_down = 32000;
4399 threshold_down = 85;
4400 break;
4401
4402 case BETWEEN:
4403 /* Upclock if more than 90% busy over 13ms */
4404 ei_up = 13000;
4405 threshold_up = 90;
4406
4407 /* Downclock if less than 75% busy over 32ms */
4408 ei_down = 32000;
4409 threshold_down = 75;
4410 break;
4411
4412 case HIGH_POWER:
4413 /* Upclock if more than 85% busy over 10ms */
4414 ei_up = 10000;
4415 threshold_up = 85;
4416
4417 /* Downclock if less than 60% busy over 32ms */
4418 ei_down = 32000;
4419 threshold_down = 60;
4420 break;
4421 }
4422
4423 I915_WRITE(GEN6_RP_UP_EI,
4424 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4425 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4426 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4427
4428 I915_WRITE(GEN6_RP_DOWN_EI,
4429 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4430 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4431 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4432
4433 I915_WRITE(GEN6_RP_CONTROL,
4434 GEN6_RP_MEDIA_TURBO |
4435 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4436 GEN6_RP_MEDIA_IS_GFX |
4437 GEN6_RP_ENABLE |
4438 GEN6_RP_UP_BUSY_AVG |
4439 GEN6_RP_DOWN_IDLE_AVG);
4440
4441 dev_priv->rps.power = new_power;
4442 dev_priv->rps.up_threshold = threshold_up;
4443 dev_priv->rps.down_threshold = threshold_down;
4444 dev_priv->rps.last_adj = 0;
4445 }
4446
4447 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4448 {
4449 u32 mask = 0;
4450
4451 if (val > dev_priv->rps.min_freq_softlimit)
4452 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4453 if (val < dev_priv->rps.max_freq_softlimit)
4454 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4455
4456 mask &= dev_priv->pm_rps_events;
4457
4458 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4459 }
4460
4461 /* gen6_set_rps is called to update the frequency request, but should also be
4462 * called when the range (min_delay and max_delay) is modified so that we can
4463 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4464 static void gen6_set_rps(struct drm_device *dev, u8 val)
4465 {
4466 struct drm_i915_private *dev_priv = dev->dev_private;
4467
4468 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4469 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
4470 return;
4471
4472 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4473 WARN_ON(val > dev_priv->rps.max_freq);
4474 WARN_ON(val < dev_priv->rps.min_freq);
4475
4476 /* min/max delay may still have been modified so be sure to
4477 * write the limits value.
4478 */
4479 if (val != dev_priv->rps.cur_freq) {
4480 gen6_set_rps_thresholds(dev_priv, val);
4481
4482 if (IS_GEN9(dev))
4483 I915_WRITE(GEN6_RPNSWREQ,
4484 GEN9_FREQUENCY(val));
4485 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4486 I915_WRITE(GEN6_RPNSWREQ,
4487 HSW_FREQUENCY(val));
4488 else
4489 I915_WRITE(GEN6_RPNSWREQ,
4490 GEN6_FREQUENCY(val) |
4491 GEN6_OFFSET(0) |
4492 GEN6_AGGRESSIVE_TURBO);
4493 }
4494
4495 /* Make sure we continue to get interrupts
4496 * until we hit the minimum or maximum frequencies.
4497 */
4498 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4499 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4500
4501 POSTING_READ(GEN6_RPNSWREQ);
4502
4503 dev_priv->rps.cur_freq = val;
4504 trace_intel_gpu_freq_change(val * 50);
4505 }
4506
4507 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4508 {
4509 struct drm_i915_private *dev_priv = dev->dev_private;
4510
4511 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4512 WARN_ON(val > dev_priv->rps.max_freq);
4513 WARN_ON(val < dev_priv->rps.min_freq);
4514
4515 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4516 "Odd GPU freq value\n"))
4517 val &= ~1;
4518
4519 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4520
4521 if (val != dev_priv->rps.cur_freq) {
4522 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4523 if (!IS_CHERRYVIEW(dev_priv))
4524 gen6_set_rps_thresholds(dev_priv, val);
4525 }
4526
4527 dev_priv->rps.cur_freq = val;
4528 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4529 }
4530
4531 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4532 *
4533 * * If Gfx is Idle, then
4534 * 1. Forcewake Media well.
4535 * 2. Request idle freq.
4536 * 3. Release Forcewake of Media well.
4537 */
4538 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4539 {
4540 u32 val = dev_priv->rps.idle_freq;
4541
4542 if (dev_priv->rps.cur_freq <= val)
4543 return;
4544
4545 /* Wake up the media well, as that takes a lot less
4546 * power than the Render well. */
4547 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4548 valleyview_set_rps(dev_priv->dev, val);
4549 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4550 }
4551
4552 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4553 {
4554 mutex_lock(&dev_priv->rps.hw_lock);
4555 if (dev_priv->rps.enabled) {
4556 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4557 gen6_rps_reset_ei(dev_priv);
4558 I915_WRITE(GEN6_PMINTRMSK,
4559 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4560 }
4561 mutex_unlock(&dev_priv->rps.hw_lock);
4562 }
4563
4564 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4565 {
4566 struct drm_device *dev = dev_priv->dev;
4567
4568 mutex_lock(&dev_priv->rps.hw_lock);
4569 if (dev_priv->rps.enabled) {
4570 if (IS_VALLEYVIEW(dev))
4571 vlv_set_rps_idle(dev_priv);
4572 else
4573 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4574 dev_priv->rps.last_adj = 0;
4575 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4576 }
4577 mutex_unlock(&dev_priv->rps.hw_lock);
4578
4579 spin_lock(&dev_priv->rps.client_lock);
4580 while (!list_empty(&dev_priv->rps.clients))
4581 list_del_init(dev_priv->rps.clients.next);
4582 spin_unlock(&dev_priv->rps.client_lock);
4583 }
4584
4585 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4586 struct intel_rps_client *rps,
4587 unsigned long submitted)
4588 {
4589 /* This is intentionally racy! We peek at the state here, then
4590 * validate inside the RPS worker.
4591 */
4592 if (!(dev_priv->mm.busy &&
4593 dev_priv->rps.enabled &&
4594 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4595 return;
4596
4597 /* Force a RPS boost (and don't count it against the client) if
4598 * the GPU is severely congested.
4599 */
4600 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4601 rps = NULL;
4602
4603 spin_lock(&dev_priv->rps.client_lock);
4604 if (rps == NULL || list_empty(&rps->link)) {
4605 spin_lock_irq(&dev_priv->irq_lock);
4606 if (dev_priv->rps.interrupts_enabled) {
4607 dev_priv->rps.client_boost = true;
4608 queue_work(dev_priv->wq, &dev_priv->rps.work);
4609 }
4610 spin_unlock_irq(&dev_priv->irq_lock);
4611
4612 if (rps != NULL) {
4613 list_add(&rps->link, &dev_priv->rps.clients);
4614 rps->boosts++;
4615 } else
4616 dev_priv->rps.boosts++;
4617 }
4618 spin_unlock(&dev_priv->rps.client_lock);
4619 }
4620
4621 void intel_set_rps(struct drm_device *dev, u8 val)
4622 {
4623 if (IS_VALLEYVIEW(dev))
4624 valleyview_set_rps(dev, val);
4625 else
4626 gen6_set_rps(dev, val);
4627 }
4628
4629 static void gen9_disable_rps(struct drm_device *dev)
4630 {
4631 struct drm_i915_private *dev_priv = dev->dev_private;
4632
4633 I915_WRITE(GEN6_RC_CONTROL, 0);
4634 I915_WRITE(GEN9_PG_ENABLE, 0);
4635 }
4636
4637 static void gen6_disable_rps(struct drm_device *dev)
4638 {
4639 struct drm_i915_private *dev_priv = dev->dev_private;
4640
4641 I915_WRITE(GEN6_RC_CONTROL, 0);
4642 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4643 }
4644
4645 static void cherryview_disable_rps(struct drm_device *dev)
4646 {
4647 struct drm_i915_private *dev_priv = dev->dev_private;
4648
4649 I915_WRITE(GEN6_RC_CONTROL, 0);
4650 }
4651
4652 static void valleyview_disable_rps(struct drm_device *dev)
4653 {
4654 struct drm_i915_private *dev_priv = dev->dev_private;
4655
4656 /* we're doing forcewake before Disabling RC6,
4657 * This what the BIOS expects when going into suspend */
4658 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4659
4660 I915_WRITE(GEN6_RC_CONTROL, 0);
4661
4662 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4663 }
4664
4665 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4666 {
4667 if (IS_VALLEYVIEW(dev)) {
4668 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4669 mode = GEN6_RC_CTL_RC6_ENABLE;
4670 else
4671 mode = 0;
4672 }
4673 if (HAS_RC6p(dev))
4674 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4675 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4676 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4677 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4678
4679 else
4680 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4681 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
4682 }
4683
4684 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4685 {
4686 /* No RC6 before Ironlake and code is gone for ilk. */
4687 if (INTEL_INFO(dev)->gen < 6)
4688 return 0;
4689
4690 /* Respect the kernel parameter if it is set */
4691 if (enable_rc6 >= 0) {
4692 int mask;
4693
4694 if (HAS_RC6p(dev))
4695 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4696 INTEL_RC6pp_ENABLE;
4697 else
4698 mask = INTEL_RC6_ENABLE;
4699
4700 if ((enable_rc6 & mask) != enable_rc6)
4701 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4702 enable_rc6 & mask, enable_rc6, mask);
4703
4704 return enable_rc6 & mask;
4705 }
4706
4707 if (IS_IVYBRIDGE(dev))
4708 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4709
4710 return INTEL_RC6_ENABLE;
4711 }
4712
4713 int intel_enable_rc6(const struct drm_device *dev)
4714 {
4715 return i915.enable_rc6;
4716 }
4717
4718 static void gen6_init_rps_frequencies(struct drm_device *dev)
4719 {
4720 struct drm_i915_private *dev_priv = dev->dev_private;
4721 uint32_t rp_state_cap;
4722 u32 ddcc_status = 0;
4723 int ret;
4724
4725 /* All of these values are in units of 50MHz */
4726 dev_priv->rps.cur_freq = 0;
4727 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4728 if (IS_BROXTON(dev)) {
4729 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4730 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4731 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4732 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4733 } else {
4734 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4735 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4736 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4737 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4738 }
4739
4740 /* hw_max = RP0 until we check for overclocking */
4741 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4742
4743 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4744 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
4745 ret = sandybridge_pcode_read(dev_priv,
4746 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4747 &ddcc_status);
4748 if (0 == ret)
4749 dev_priv->rps.efficient_freq =
4750 clamp_t(u8,
4751 ((ddcc_status >> 8) & 0xff),
4752 dev_priv->rps.min_freq,
4753 dev_priv->rps.max_freq);
4754 }
4755
4756 if (IS_SKYLAKE(dev)) {
4757 /* Store the frequency values in 16.66 MHZ units, which is
4758 the natural hardware unit for SKL */
4759 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4760 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4761 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4762 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4763 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4764 }
4765
4766 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4767
4768 /* Preserve min/max settings in case of re-init */
4769 if (dev_priv->rps.max_freq_softlimit == 0)
4770 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4771
4772 if (dev_priv->rps.min_freq_softlimit == 0) {
4773 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4774 dev_priv->rps.min_freq_softlimit =
4775 max_t(int, dev_priv->rps.efficient_freq,
4776 intel_freq_opcode(dev_priv, 450));
4777 else
4778 dev_priv->rps.min_freq_softlimit =
4779 dev_priv->rps.min_freq;
4780 }
4781 }
4782
4783 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4784 static void gen9_enable_rps(struct drm_device *dev)
4785 {
4786 struct drm_i915_private *dev_priv = dev->dev_private;
4787
4788 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4789
4790 gen6_init_rps_frequencies(dev);
4791
4792 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4793 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
4794 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4795 return;
4796 }
4797
4798 /* Program defaults and thresholds for RPS*/
4799 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4800 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4801
4802 /* 1 second timeout*/
4803 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4804 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4805
4806 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4807
4808 /* Leaning on the below call to gen6_set_rps to program/setup the
4809 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4810 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4811 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4812 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4813
4814 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4815 }
4816
4817 static void gen9_enable_rc6(struct drm_device *dev)
4818 {
4819 struct drm_i915_private *dev_priv = dev->dev_private;
4820 struct intel_engine_cs *ring;
4821 uint32_t rc6_mask = 0;
4822 int unused;
4823
4824 /* 1a: Software RC state - RC0 */
4825 I915_WRITE(GEN6_RC_STATE, 0);
4826
4827 /* 1b: Get forcewake during program sequence. Although the driver
4828 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4829 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4830
4831 /* 2a: Disable RC states. */
4832 I915_WRITE(GEN6_RC_CONTROL, 0);
4833
4834 /* 2b: Program RC6 thresholds.*/
4835
4836 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4837 if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
4838 (INTEL_REVID(dev) <= SKL_REVID_E0)))
4839 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4840 else
4841 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4842 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4843 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4844 for_each_ring(ring, dev_priv, unused)
4845 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4846
4847 if (HAS_GUC_UCODE(dev))
4848 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4849
4850 I915_WRITE(GEN6_RC_SLEEP, 0);
4851 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4852
4853 /* 2c: Program Coarse Power Gating Policies. */
4854 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4855 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4856
4857 /* 3a: Enable RC6 */
4858 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4859 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4860 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4861 "on" : "off");
4862
4863 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
4864 (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
4865 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4866 GEN7_RC_CTL_TO_MODE |
4867 rc6_mask);
4868 else
4869 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4870 GEN6_RC_CTL_EI_MODE(1) |
4871 rc6_mask);
4872
4873 /*
4874 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4875 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4876 */
4877 if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
4878 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
4879 I915_WRITE(GEN9_PG_ENABLE, 0);
4880 else
4881 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4882 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4883
4884 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4885
4886 }
4887
4888 static void gen8_enable_rps(struct drm_device *dev)
4889 {
4890 struct drm_i915_private *dev_priv = dev->dev_private;
4891 struct intel_engine_cs *ring;
4892 uint32_t rc6_mask = 0;
4893 int unused;
4894
4895 /* 1a: Software RC state - RC0 */
4896 I915_WRITE(GEN6_RC_STATE, 0);
4897
4898 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4899 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4900 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4901
4902 /* 2a: Disable RC states. */
4903 I915_WRITE(GEN6_RC_CONTROL, 0);
4904
4905 /* Initialize rps frequencies */
4906 gen6_init_rps_frequencies(dev);
4907
4908 /* 2b: Program RC6 thresholds.*/
4909 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4910 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4911 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4912 for_each_ring(ring, dev_priv, unused)
4913 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4914 I915_WRITE(GEN6_RC_SLEEP, 0);
4915 if (IS_BROADWELL(dev))
4916 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4917 else
4918 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4919
4920 /* 3: Enable RC6 */
4921 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4922 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4923 intel_print_rc6_info(dev, rc6_mask);
4924 if (IS_BROADWELL(dev))
4925 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4926 GEN7_RC_CTL_TO_MODE |
4927 rc6_mask);
4928 else
4929 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4930 GEN6_RC_CTL_EI_MODE(1) |
4931 rc6_mask);
4932
4933 /* 4 Program defaults and thresholds for RPS*/
4934 I915_WRITE(GEN6_RPNSWREQ,
4935 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4936 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4937 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4938 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4939 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4940
4941 /* Docs recommend 900MHz, and 300 MHz respectively */
4942 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4943 dev_priv->rps.max_freq_softlimit << 24 |
4944 dev_priv->rps.min_freq_softlimit << 16);
4945
4946 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4947 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4948 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4949 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4950
4951 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4952
4953 /* 5: Enable RPS */
4954 I915_WRITE(GEN6_RP_CONTROL,
4955 GEN6_RP_MEDIA_TURBO |
4956 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4957 GEN6_RP_MEDIA_IS_GFX |
4958 GEN6_RP_ENABLE |
4959 GEN6_RP_UP_BUSY_AVG |
4960 GEN6_RP_DOWN_IDLE_AVG);
4961
4962 /* 6: Ring frequency + overclocking (our driver does this later */
4963
4964 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4965 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4966
4967 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4968 }
4969
4970 static void gen6_enable_rps(struct drm_device *dev)
4971 {
4972 struct drm_i915_private *dev_priv = dev->dev_private;
4973 struct intel_engine_cs *ring;
4974 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4975 u32 gtfifodbg;
4976 int rc6_mode;
4977 int i, ret;
4978
4979 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4980
4981 /* Here begins a magic sequence of register writes to enable
4982 * auto-downclocking.
4983 *
4984 * Perhaps there might be some value in exposing these to
4985 * userspace...
4986 */
4987 I915_WRITE(GEN6_RC_STATE, 0);
4988
4989 /* Clear the DBG now so we don't confuse earlier errors */
4990 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4991 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4992 I915_WRITE(GTFIFODBG, gtfifodbg);
4993 }
4994
4995 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4996
4997 /* Initialize rps frequencies */
4998 gen6_init_rps_frequencies(dev);
4999
5000 /* disable the counters and set deterministic thresholds */
5001 I915_WRITE(GEN6_RC_CONTROL, 0);
5002
5003 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5004 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5005 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5006 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5007 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5008
5009 for_each_ring(ring, dev_priv, i)
5010 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5011
5012 I915_WRITE(GEN6_RC_SLEEP, 0);
5013 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5014 if (IS_IVYBRIDGE(dev))
5015 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5016 else
5017 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5018 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5019 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5020
5021 /* Check if we are enabling RC6 */
5022 rc6_mode = intel_enable_rc6(dev_priv->dev);
5023 if (rc6_mode & INTEL_RC6_ENABLE)
5024 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5025
5026 /* We don't use those on Haswell */
5027 if (!IS_HASWELL(dev)) {
5028 if (rc6_mode & INTEL_RC6p_ENABLE)
5029 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5030
5031 if (rc6_mode & INTEL_RC6pp_ENABLE)
5032 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5033 }
5034
5035 intel_print_rc6_info(dev, rc6_mask);
5036
5037 I915_WRITE(GEN6_RC_CONTROL,
5038 rc6_mask |
5039 GEN6_RC_CTL_EI_MODE(1) |
5040 GEN6_RC_CTL_HW_ENABLE);
5041
5042 /* Power down if completely idle for over 50ms */
5043 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5044 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5045
5046 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5047 if (ret)
5048 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5049
5050 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5051 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5052 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5053 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5054 (pcu_mbox & 0xff) * 50);
5055 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5056 }
5057
5058 dev_priv->rps.power = HIGH_POWER; /* force a reset */
5059 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5060
5061 rc6vids = 0;
5062 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5063 if (IS_GEN6(dev) && ret) {
5064 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5065 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5066 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5067 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5068 rc6vids &= 0xffff00;
5069 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5070 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5071 if (ret)
5072 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5073 }
5074
5075 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5076 }
5077
5078 static void __gen6_update_ring_freq(struct drm_device *dev)
5079 {
5080 struct drm_i915_private *dev_priv = dev->dev_private;
5081 int min_freq = 15;
5082 unsigned int gpu_freq;
5083 unsigned int max_ia_freq, min_ring_freq;
5084 unsigned int max_gpu_freq, min_gpu_freq;
5085 int scaling_factor = 180;
5086 struct cpufreq_policy *policy;
5087
5088 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5089
5090 policy = cpufreq_cpu_get(0);
5091 if (policy) {
5092 max_ia_freq = policy->cpuinfo.max_freq;
5093 cpufreq_cpu_put(policy);
5094 } else {
5095 /*
5096 * Default to measured freq if none found, PCU will ensure we
5097 * don't go over
5098 */
5099 max_ia_freq = tsc_khz;
5100 }
5101
5102 /* Convert from kHz to MHz */
5103 max_ia_freq /= 1000;
5104
5105 min_ring_freq = I915_READ(DCLK) & 0xf;
5106 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5107 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5108
5109 if (IS_SKYLAKE(dev)) {
5110 /* Convert GT frequency to 50 HZ units */
5111 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5112 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5113 } else {
5114 min_gpu_freq = dev_priv->rps.min_freq;
5115 max_gpu_freq = dev_priv->rps.max_freq;
5116 }
5117
5118 /*
5119 * For each potential GPU frequency, load a ring frequency we'd like
5120 * to use for memory access. We do this by specifying the IA frequency
5121 * the PCU should use as a reference to determine the ring frequency.
5122 */
5123 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5124 int diff = max_gpu_freq - gpu_freq;
5125 unsigned int ia_freq = 0, ring_freq = 0;
5126
5127 if (IS_SKYLAKE(dev)) {
5128 /*
5129 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5130 * No floor required for ring frequency on SKL.
5131 */
5132 ring_freq = gpu_freq;
5133 } else if (INTEL_INFO(dev)->gen >= 8) {
5134 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5135 ring_freq = max(min_ring_freq, gpu_freq);
5136 } else if (IS_HASWELL(dev)) {
5137 ring_freq = mult_frac(gpu_freq, 5, 4);
5138 ring_freq = max(min_ring_freq, ring_freq);
5139 /* leave ia_freq as the default, chosen by cpufreq */
5140 } else {
5141 /* On older processors, there is no separate ring
5142 * clock domain, so in order to boost the bandwidth
5143 * of the ring, we need to upclock the CPU (ia_freq).
5144 *
5145 * For GPU frequencies less than 750MHz,
5146 * just use the lowest ring freq.
5147 */
5148 if (gpu_freq < min_freq)
5149 ia_freq = 800;
5150 else
5151 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5152 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5153 }
5154
5155 sandybridge_pcode_write(dev_priv,
5156 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5157 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5158 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5159 gpu_freq);
5160 }
5161 }
5162
5163 void gen6_update_ring_freq(struct drm_device *dev)
5164 {
5165 struct drm_i915_private *dev_priv = dev->dev_private;
5166
5167 if (!HAS_CORE_RING_FREQ(dev))
5168 return;
5169
5170 mutex_lock(&dev_priv->rps.hw_lock);
5171 __gen6_update_ring_freq(dev);
5172 mutex_unlock(&dev_priv->rps.hw_lock);
5173 }
5174
5175 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5176 {
5177 struct drm_device *dev = dev_priv->dev;
5178 u32 val, rp0;
5179
5180 if (dev->pdev->revision >= 0x20) {
5181 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5182
5183 switch (INTEL_INFO(dev)->eu_total) {
5184 case 8:
5185 /* (2 * 4) config */
5186 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5187 break;
5188 case 12:
5189 /* (2 * 6) config */
5190 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5191 break;
5192 case 16:
5193 /* (2 * 8) config */
5194 default:
5195 /* Setting (2 * 8) Min RP0 for any other combination */
5196 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5197 break;
5198 }
5199 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5200 } else {
5201 /* For pre-production hardware */
5202 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
5203 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5204 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
5205 }
5206 return rp0;
5207 }
5208
5209 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5210 {
5211 u32 val, rpe;
5212
5213 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5214 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5215
5216 return rpe;
5217 }
5218
5219 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5220 {
5221 struct drm_device *dev = dev_priv->dev;
5222 u32 val, rp1;
5223
5224 if (dev->pdev->revision >= 0x20) {
5225 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5226 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5227 } else {
5228 /* For pre-production hardware */
5229 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5230 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5231 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
5232 }
5233 return rp1;
5234 }
5235
5236 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5237 {
5238 u32 val, rp1;
5239
5240 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5241
5242 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5243
5244 return rp1;
5245 }
5246
5247 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5248 {
5249 u32 val, rp0;
5250
5251 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5252
5253 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5254 /* Clamp to max */
5255 rp0 = min_t(u32, rp0, 0xea);
5256
5257 return rp0;
5258 }
5259
5260 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5261 {
5262 u32 val, rpe;
5263
5264 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5265 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5266 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5267 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5268
5269 return rpe;
5270 }
5271
5272 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5273 {
5274 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5275 }
5276
5277 /* Check that the pctx buffer wasn't move under us. */
5278 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5279 {
5280 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5281
5282 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5283 dev_priv->vlv_pctx->stolen->start);
5284 }
5285
5286
5287 /* Check that the pcbr address is not empty. */
5288 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5289 {
5290 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5291
5292 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5293 }
5294
5295 static void cherryview_setup_pctx(struct drm_device *dev)
5296 {
5297 struct drm_i915_private *dev_priv = dev->dev_private;
5298 unsigned long pctx_paddr, paddr;
5299 struct i915_gtt *gtt = &dev_priv->gtt;
5300 u32 pcbr;
5301 int pctx_size = 32*1024;
5302
5303 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5304
5305 pcbr = I915_READ(VLV_PCBR);
5306 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5307 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5308 paddr = (dev_priv->mm.stolen_base +
5309 (gtt->stolen_size - pctx_size));
5310
5311 pctx_paddr = (paddr & (~4095));
5312 I915_WRITE(VLV_PCBR, pctx_paddr);
5313 }
5314
5315 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5316 }
5317
5318 static void valleyview_setup_pctx(struct drm_device *dev)
5319 {
5320 struct drm_i915_private *dev_priv = dev->dev_private;
5321 struct drm_i915_gem_object *pctx;
5322 unsigned long pctx_paddr;
5323 u32 pcbr;
5324 int pctx_size = 24*1024;
5325
5326 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5327
5328 pcbr = I915_READ(VLV_PCBR);
5329 if (pcbr) {
5330 /* BIOS set it up already, grab the pre-alloc'd space */
5331 int pcbr_offset;
5332
5333 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5334 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5335 pcbr_offset,
5336 I915_GTT_OFFSET_NONE,
5337 pctx_size);
5338 goto out;
5339 }
5340
5341 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5342
5343 /*
5344 * From the Gunit register HAS:
5345 * The Gfx driver is expected to program this register and ensure
5346 * proper allocation within Gfx stolen memory. For example, this
5347 * register should be programmed such than the PCBR range does not
5348 * overlap with other ranges, such as the frame buffer, protected
5349 * memory, or any other relevant ranges.
5350 */
5351 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5352 if (!pctx) {
5353 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5354 return;
5355 }
5356
5357 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5358 I915_WRITE(VLV_PCBR, pctx_paddr);
5359
5360 out:
5361 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5362 dev_priv->vlv_pctx = pctx;
5363 }
5364
5365 static void valleyview_cleanup_pctx(struct drm_device *dev)
5366 {
5367 struct drm_i915_private *dev_priv = dev->dev_private;
5368
5369 if (WARN_ON(!dev_priv->vlv_pctx))
5370 return;
5371
5372 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5373 dev_priv->vlv_pctx = NULL;
5374 }
5375
5376 static void valleyview_init_gt_powersave(struct drm_device *dev)
5377 {
5378 struct drm_i915_private *dev_priv = dev->dev_private;
5379 u32 val;
5380
5381 valleyview_setup_pctx(dev);
5382
5383 mutex_lock(&dev_priv->rps.hw_lock);
5384
5385 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5386 switch ((val >> 6) & 3) {
5387 case 0:
5388 case 1:
5389 dev_priv->mem_freq = 800;
5390 break;
5391 case 2:
5392 dev_priv->mem_freq = 1066;
5393 break;
5394 case 3:
5395 dev_priv->mem_freq = 1333;
5396 break;
5397 }
5398 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5399
5400 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5401 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5402 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5403 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5404 dev_priv->rps.max_freq);
5405
5406 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5407 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5408 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5409 dev_priv->rps.efficient_freq);
5410
5411 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5412 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5413 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5414 dev_priv->rps.rp1_freq);
5415
5416 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5417 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5418 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5419 dev_priv->rps.min_freq);
5420
5421 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5422
5423 /* Preserve min/max settings in case of re-init */
5424 if (dev_priv->rps.max_freq_softlimit == 0)
5425 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5426
5427 if (dev_priv->rps.min_freq_softlimit == 0)
5428 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5429
5430 mutex_unlock(&dev_priv->rps.hw_lock);
5431 }
5432
5433 static void cherryview_init_gt_powersave(struct drm_device *dev)
5434 {
5435 struct drm_i915_private *dev_priv = dev->dev_private;
5436 u32 val;
5437
5438 cherryview_setup_pctx(dev);
5439
5440 mutex_lock(&dev_priv->rps.hw_lock);
5441
5442 mutex_lock(&dev_priv->sb_lock);
5443 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5444 mutex_unlock(&dev_priv->sb_lock);
5445
5446 switch ((val >> 2) & 0x7) {
5447 case 3:
5448 dev_priv->mem_freq = 2000;
5449 break;
5450 default:
5451 dev_priv->mem_freq = 1600;
5452 break;
5453 }
5454 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5455
5456 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5457 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5458 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5459 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5460 dev_priv->rps.max_freq);
5461
5462 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5463 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5464 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5465 dev_priv->rps.efficient_freq);
5466
5467 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5468 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5469 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5470 dev_priv->rps.rp1_freq);
5471
5472 /* PUnit validated range is only [RPe, RP0] */
5473 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5474 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5475 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5476 dev_priv->rps.min_freq);
5477
5478 WARN_ONCE((dev_priv->rps.max_freq |
5479 dev_priv->rps.efficient_freq |
5480 dev_priv->rps.rp1_freq |
5481 dev_priv->rps.min_freq) & 1,
5482 "Odd GPU freq values\n");
5483
5484 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5485
5486 /* Preserve min/max settings in case of re-init */
5487 if (dev_priv->rps.max_freq_softlimit == 0)
5488 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5489
5490 if (dev_priv->rps.min_freq_softlimit == 0)
5491 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5492
5493 mutex_unlock(&dev_priv->rps.hw_lock);
5494 }
5495
5496 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5497 {
5498 valleyview_cleanup_pctx(dev);
5499 }
5500
5501 static void cherryview_enable_rps(struct drm_device *dev)
5502 {
5503 struct drm_i915_private *dev_priv = dev->dev_private;
5504 struct intel_engine_cs *ring;
5505 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5506 int i;
5507
5508 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5509
5510 gtfifodbg = I915_READ(GTFIFODBG);
5511 if (gtfifodbg) {
5512 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5513 gtfifodbg);
5514 I915_WRITE(GTFIFODBG, gtfifodbg);
5515 }
5516
5517 cherryview_check_pctx(dev_priv);
5518
5519 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5520 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5521 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5522
5523 /* Disable RC states. */
5524 I915_WRITE(GEN6_RC_CONTROL, 0);
5525
5526 /* 2a: Program RC6 thresholds.*/
5527 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5528 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5529 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5530
5531 for_each_ring(ring, dev_priv, i)
5532 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5533 I915_WRITE(GEN6_RC_SLEEP, 0);
5534
5535 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5536 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5537
5538 /* allows RC6 residency counter to work */
5539 I915_WRITE(VLV_COUNTER_CONTROL,
5540 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5541 VLV_MEDIA_RC6_COUNT_EN |
5542 VLV_RENDER_RC6_COUNT_EN));
5543
5544 /* For now we assume BIOS is allocating and populating the PCBR */
5545 pcbr = I915_READ(VLV_PCBR);
5546
5547 /* 3: Enable RC6 */
5548 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5549 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5550 rc6_mode = GEN7_RC_CTL_TO_MODE;
5551
5552 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5553
5554 /* 4 Program defaults and thresholds for RPS*/
5555 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5556 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5557 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5558 I915_WRITE(GEN6_RP_UP_EI, 66000);
5559 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5560
5561 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5562
5563 /* 5: Enable RPS */
5564 I915_WRITE(GEN6_RP_CONTROL,
5565 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5566 GEN6_RP_MEDIA_IS_GFX |
5567 GEN6_RP_ENABLE |
5568 GEN6_RP_UP_BUSY_AVG |
5569 GEN6_RP_DOWN_IDLE_AVG);
5570
5571 /* Setting Fixed Bias */
5572 val = VLV_OVERRIDE_EN |
5573 VLV_SOC_TDP_EN |
5574 CHV_BIAS_CPU_50_SOC_50;
5575 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5576
5577 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5578
5579 /* RPS code assumes GPLL is used */
5580 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5581
5582 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5583 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5584
5585 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5586 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5587 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5588 dev_priv->rps.cur_freq);
5589
5590 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5591 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5592 dev_priv->rps.efficient_freq);
5593
5594 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5595
5596 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5597 }
5598
5599 static void valleyview_enable_rps(struct drm_device *dev)
5600 {
5601 struct drm_i915_private *dev_priv = dev->dev_private;
5602 struct intel_engine_cs *ring;
5603 u32 gtfifodbg, val, rc6_mode = 0;
5604 int i;
5605
5606 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5607
5608 valleyview_check_pctx(dev_priv);
5609
5610 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5611 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5612 gtfifodbg);
5613 I915_WRITE(GTFIFODBG, gtfifodbg);
5614 }
5615
5616 /* If VLV, Forcewake all wells, else re-direct to regular path */
5617 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5618
5619 /* Disable RC states. */
5620 I915_WRITE(GEN6_RC_CONTROL, 0);
5621
5622 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5623 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5624 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5625 I915_WRITE(GEN6_RP_UP_EI, 66000);
5626 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5627
5628 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5629
5630 I915_WRITE(GEN6_RP_CONTROL,
5631 GEN6_RP_MEDIA_TURBO |
5632 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5633 GEN6_RP_MEDIA_IS_GFX |
5634 GEN6_RP_ENABLE |
5635 GEN6_RP_UP_BUSY_AVG |
5636 GEN6_RP_DOWN_IDLE_CONT);
5637
5638 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5639 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5640 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5641
5642 for_each_ring(ring, dev_priv, i)
5643 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5644
5645 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5646
5647 /* allows RC6 residency counter to work */
5648 I915_WRITE(VLV_COUNTER_CONTROL,
5649 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5650 VLV_RENDER_RC0_COUNT_EN |
5651 VLV_MEDIA_RC6_COUNT_EN |
5652 VLV_RENDER_RC6_COUNT_EN));
5653
5654 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5655 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5656
5657 intel_print_rc6_info(dev, rc6_mode);
5658
5659 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5660
5661 /* Setting Fixed Bias */
5662 val = VLV_OVERRIDE_EN |
5663 VLV_SOC_TDP_EN |
5664 VLV_BIAS_CPU_125_SOC_875;
5665 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5666
5667 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5668
5669 /* RPS code assumes GPLL is used */
5670 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5671
5672 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5673 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5674
5675 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5676 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5677 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5678 dev_priv->rps.cur_freq);
5679
5680 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5681 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5682 dev_priv->rps.efficient_freq);
5683
5684 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5685
5686 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5687 }
5688
5689 static unsigned long intel_pxfreq(u32 vidfreq)
5690 {
5691 unsigned long freq;
5692 int div = (vidfreq & 0x3f0000) >> 16;
5693 int post = (vidfreq & 0x3000) >> 12;
5694 int pre = (vidfreq & 0x7);
5695
5696 if (!pre)
5697 return 0;
5698
5699 freq = ((div * 133333) / ((1<<post) * pre));
5700
5701 return freq;
5702 }
5703
5704 static const struct cparams {
5705 u16 i;
5706 u16 t;
5707 u16 m;
5708 u16 c;
5709 } cparams[] = {
5710 { 1, 1333, 301, 28664 },
5711 { 1, 1066, 294, 24460 },
5712 { 1, 800, 294, 25192 },
5713 { 0, 1333, 276, 27605 },
5714 { 0, 1066, 276, 27605 },
5715 { 0, 800, 231, 23784 },
5716 };
5717
5718 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5719 {
5720 u64 total_count, diff, ret;
5721 u32 count1, count2, count3, m = 0, c = 0;
5722 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5723 int i;
5724
5725 assert_spin_locked(&mchdev_lock);
5726
5727 diff1 = now - dev_priv->ips.last_time1;
5728
5729 /* Prevent division-by-zero if we are asking too fast.
5730 * Also, we don't get interesting results if we are polling
5731 * faster than once in 10ms, so just return the saved value
5732 * in such cases.
5733 */
5734 if (diff1 <= 10)
5735 return dev_priv->ips.chipset_power;
5736
5737 count1 = I915_READ(DMIEC);
5738 count2 = I915_READ(DDREC);
5739 count3 = I915_READ(CSIEC);
5740
5741 total_count = count1 + count2 + count3;
5742
5743 /* FIXME: handle per-counter overflow */
5744 if (total_count < dev_priv->ips.last_count1) {
5745 diff = ~0UL - dev_priv->ips.last_count1;
5746 diff += total_count;
5747 } else {
5748 diff = total_count - dev_priv->ips.last_count1;
5749 }
5750
5751 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5752 if (cparams[i].i == dev_priv->ips.c_m &&
5753 cparams[i].t == dev_priv->ips.r_t) {
5754 m = cparams[i].m;
5755 c = cparams[i].c;
5756 break;
5757 }
5758 }
5759
5760 diff = div_u64(diff, diff1);
5761 ret = ((m * diff) + c);
5762 ret = div_u64(ret, 10);
5763
5764 dev_priv->ips.last_count1 = total_count;
5765 dev_priv->ips.last_time1 = now;
5766
5767 dev_priv->ips.chipset_power = ret;
5768
5769 return ret;
5770 }
5771
5772 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5773 {
5774 struct drm_device *dev = dev_priv->dev;
5775 unsigned long val;
5776
5777 if (INTEL_INFO(dev)->gen != 5)
5778 return 0;
5779
5780 spin_lock_irq(&mchdev_lock);
5781
5782 val = __i915_chipset_val(dev_priv);
5783
5784 spin_unlock_irq(&mchdev_lock);
5785
5786 return val;
5787 }
5788
5789 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5790 {
5791 unsigned long m, x, b;
5792 u32 tsfs;
5793
5794 tsfs = I915_READ(TSFS);
5795
5796 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5797 x = I915_READ8(TR1);
5798
5799 b = tsfs & TSFS_INTR_MASK;
5800
5801 return ((m * x) / 127) - b;
5802 }
5803
5804 static int _pxvid_to_vd(u8 pxvid)
5805 {
5806 if (pxvid == 0)
5807 return 0;
5808
5809 if (pxvid >= 8 && pxvid < 31)
5810 pxvid = 31;
5811
5812 return (pxvid + 2) * 125;
5813 }
5814
5815 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5816 {
5817 struct drm_device *dev = dev_priv->dev;
5818 const int vd = _pxvid_to_vd(pxvid);
5819 const int vm = vd - 1125;
5820
5821 if (INTEL_INFO(dev)->is_mobile)
5822 return vm > 0 ? vm : 0;
5823
5824 return vd;
5825 }
5826
5827 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5828 {
5829 u64 now, diff, diffms;
5830 u32 count;
5831
5832 assert_spin_locked(&mchdev_lock);
5833
5834 now = ktime_get_raw_ns();
5835 diffms = now - dev_priv->ips.last_time2;
5836 do_div(diffms, NSEC_PER_MSEC);
5837
5838 /* Don't divide by 0 */
5839 if (!diffms)
5840 return;
5841
5842 count = I915_READ(GFXEC);
5843
5844 if (count < dev_priv->ips.last_count2) {
5845 diff = ~0UL - dev_priv->ips.last_count2;
5846 diff += count;
5847 } else {
5848 diff = count - dev_priv->ips.last_count2;
5849 }
5850
5851 dev_priv->ips.last_count2 = count;
5852 dev_priv->ips.last_time2 = now;
5853
5854 /* More magic constants... */
5855 diff = diff * 1181;
5856 diff = div_u64(diff, diffms * 10);
5857 dev_priv->ips.gfx_power = diff;
5858 }
5859
5860 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5861 {
5862 struct drm_device *dev = dev_priv->dev;
5863
5864 if (INTEL_INFO(dev)->gen != 5)
5865 return;
5866
5867 spin_lock_irq(&mchdev_lock);
5868
5869 __i915_update_gfx_val(dev_priv);
5870
5871 spin_unlock_irq(&mchdev_lock);
5872 }
5873
5874 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5875 {
5876 unsigned long t, corr, state1, corr2, state2;
5877 u32 pxvid, ext_v;
5878
5879 assert_spin_locked(&mchdev_lock);
5880
5881 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5882 pxvid = (pxvid >> 24) & 0x7f;
5883 ext_v = pvid_to_extvid(dev_priv, pxvid);
5884
5885 state1 = ext_v;
5886
5887 t = i915_mch_val(dev_priv);
5888
5889 /* Revel in the empirically derived constants */
5890
5891 /* Correction factor in 1/100000 units */
5892 if (t > 80)
5893 corr = ((t * 2349) + 135940);
5894 else if (t >= 50)
5895 corr = ((t * 964) + 29317);
5896 else /* < 50 */
5897 corr = ((t * 301) + 1004);
5898
5899 corr = corr * ((150142 * state1) / 10000 - 78642);
5900 corr /= 100000;
5901 corr2 = (corr * dev_priv->ips.corr);
5902
5903 state2 = (corr2 * state1) / 10000;
5904 state2 /= 100; /* convert to mW */
5905
5906 __i915_update_gfx_val(dev_priv);
5907
5908 return dev_priv->ips.gfx_power + state2;
5909 }
5910
5911 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5912 {
5913 struct drm_device *dev = dev_priv->dev;
5914 unsigned long val;
5915
5916 if (INTEL_INFO(dev)->gen != 5)
5917 return 0;
5918
5919 spin_lock_irq(&mchdev_lock);
5920
5921 val = __i915_gfx_val(dev_priv);
5922
5923 spin_unlock_irq(&mchdev_lock);
5924
5925 return val;
5926 }
5927
5928 /**
5929 * i915_read_mch_val - return value for IPS use
5930 *
5931 * Calculate and return a value for the IPS driver to use when deciding whether
5932 * we have thermal and power headroom to increase CPU or GPU power budget.
5933 */
5934 unsigned long i915_read_mch_val(void)
5935 {
5936 struct drm_i915_private *dev_priv;
5937 unsigned long chipset_val, graphics_val, ret = 0;
5938
5939 spin_lock_irq(&mchdev_lock);
5940 if (!i915_mch_dev)
5941 goto out_unlock;
5942 dev_priv = i915_mch_dev;
5943
5944 chipset_val = __i915_chipset_val(dev_priv);
5945 graphics_val = __i915_gfx_val(dev_priv);
5946
5947 ret = chipset_val + graphics_val;
5948
5949 out_unlock:
5950 spin_unlock_irq(&mchdev_lock);
5951
5952 return ret;
5953 }
5954 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5955
5956 /**
5957 * i915_gpu_raise - raise GPU frequency limit
5958 *
5959 * Raise the limit; IPS indicates we have thermal headroom.
5960 */
5961 bool i915_gpu_raise(void)
5962 {
5963 struct drm_i915_private *dev_priv;
5964 bool ret = true;
5965
5966 spin_lock_irq(&mchdev_lock);
5967 if (!i915_mch_dev) {
5968 ret = false;
5969 goto out_unlock;
5970 }
5971 dev_priv = i915_mch_dev;
5972
5973 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5974 dev_priv->ips.max_delay--;
5975
5976 out_unlock:
5977 spin_unlock_irq(&mchdev_lock);
5978
5979 return ret;
5980 }
5981 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5982
5983 /**
5984 * i915_gpu_lower - lower GPU frequency limit
5985 *
5986 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5987 * frequency maximum.
5988 */
5989 bool i915_gpu_lower(void)
5990 {
5991 struct drm_i915_private *dev_priv;
5992 bool ret = true;
5993
5994 spin_lock_irq(&mchdev_lock);
5995 if (!i915_mch_dev) {
5996 ret = false;
5997 goto out_unlock;
5998 }
5999 dev_priv = i915_mch_dev;
6000
6001 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6002 dev_priv->ips.max_delay++;
6003
6004 out_unlock:
6005 spin_unlock_irq(&mchdev_lock);
6006
6007 return ret;
6008 }
6009 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6010
6011 /**
6012 * i915_gpu_busy - indicate GPU business to IPS
6013 *
6014 * Tell the IPS driver whether or not the GPU is busy.
6015 */
6016 bool i915_gpu_busy(void)
6017 {
6018 struct drm_i915_private *dev_priv;
6019 struct intel_engine_cs *ring;
6020 bool ret = false;
6021 int i;
6022
6023 spin_lock_irq(&mchdev_lock);
6024 if (!i915_mch_dev)
6025 goto out_unlock;
6026 dev_priv = i915_mch_dev;
6027
6028 for_each_ring(ring, dev_priv, i)
6029 ret |= !list_empty(&ring->request_list);
6030
6031 out_unlock:
6032 spin_unlock_irq(&mchdev_lock);
6033
6034 return ret;
6035 }
6036 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6037
6038 /**
6039 * i915_gpu_turbo_disable - disable graphics turbo
6040 *
6041 * Disable graphics turbo by resetting the max frequency and setting the
6042 * current frequency to the default.
6043 */
6044 bool i915_gpu_turbo_disable(void)
6045 {
6046 struct drm_i915_private *dev_priv;
6047 bool ret = true;
6048
6049 spin_lock_irq(&mchdev_lock);
6050 if (!i915_mch_dev) {
6051 ret = false;
6052 goto out_unlock;
6053 }
6054 dev_priv = i915_mch_dev;
6055
6056 dev_priv->ips.max_delay = dev_priv->ips.fstart;
6057
6058 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
6059 ret = false;
6060
6061 out_unlock:
6062 spin_unlock_irq(&mchdev_lock);
6063
6064 return ret;
6065 }
6066 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6067
6068 /**
6069 * Tells the intel_ips driver that the i915 driver is now loaded, if
6070 * IPS got loaded first.
6071 *
6072 * This awkward dance is so that neither module has to depend on the
6073 * other in order for IPS to do the appropriate communication of
6074 * GPU turbo limits to i915.
6075 */
6076 static void
6077 ips_ping_for_i915_load(void)
6078 {
6079 void (*link)(void);
6080
6081 link = symbol_get(ips_link_to_i915_driver);
6082 if (link) {
6083 link();
6084 symbol_put(ips_link_to_i915_driver);
6085 }
6086 }
6087
6088 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6089 {
6090 /* We only register the i915 ips part with intel-ips once everything is
6091 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6092 spin_lock_irq(&mchdev_lock);
6093 i915_mch_dev = dev_priv;
6094 spin_unlock_irq(&mchdev_lock);
6095
6096 ips_ping_for_i915_load();
6097 }
6098
6099 void intel_gpu_ips_teardown(void)
6100 {
6101 spin_lock_irq(&mchdev_lock);
6102 i915_mch_dev = NULL;
6103 spin_unlock_irq(&mchdev_lock);
6104 }
6105
6106 static void intel_init_emon(struct drm_device *dev)
6107 {
6108 struct drm_i915_private *dev_priv = dev->dev_private;
6109 u32 lcfuse;
6110 u8 pxw[16];
6111 int i;
6112
6113 /* Disable to program */
6114 I915_WRITE(ECR, 0);
6115 POSTING_READ(ECR);
6116
6117 /* Program energy weights for various events */
6118 I915_WRITE(SDEW, 0x15040d00);
6119 I915_WRITE(CSIEW0, 0x007f0000);
6120 I915_WRITE(CSIEW1, 0x1e220004);
6121 I915_WRITE(CSIEW2, 0x04000004);
6122
6123 for (i = 0; i < 5; i++)
6124 I915_WRITE(PEW(i), 0);
6125 for (i = 0; i < 3; i++)
6126 I915_WRITE(DEW(i), 0);
6127
6128 /* Program P-state weights to account for frequency power adjustment */
6129 for (i = 0; i < 16; i++) {
6130 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6131 unsigned long freq = intel_pxfreq(pxvidfreq);
6132 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6133 PXVFREQ_PX_SHIFT;
6134 unsigned long val;
6135
6136 val = vid * vid;
6137 val *= (freq / 1000);
6138 val *= 255;
6139 val /= (127*127*900);
6140 if (val > 0xff)
6141 DRM_ERROR("bad pxval: %ld\n", val);
6142 pxw[i] = val;
6143 }
6144 /* Render standby states get 0 weight */
6145 pxw[14] = 0;
6146 pxw[15] = 0;
6147
6148 for (i = 0; i < 4; i++) {
6149 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6150 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6151 I915_WRITE(PXW(i), val);
6152 }
6153
6154 /* Adjust magic regs to magic values (more experimental results) */
6155 I915_WRITE(OGW0, 0);
6156 I915_WRITE(OGW1, 0);
6157 I915_WRITE(EG0, 0x00007f00);
6158 I915_WRITE(EG1, 0x0000000e);
6159 I915_WRITE(EG2, 0x000e0000);
6160 I915_WRITE(EG3, 0x68000300);
6161 I915_WRITE(EG4, 0x42000000);
6162 I915_WRITE(EG5, 0x00140031);
6163 I915_WRITE(EG6, 0);
6164 I915_WRITE(EG7, 0);
6165
6166 for (i = 0; i < 8; i++)
6167 I915_WRITE(PXWL(i), 0);
6168
6169 /* Enable PMON + select events */
6170 I915_WRITE(ECR, 0x80000019);
6171
6172 lcfuse = I915_READ(LCFUSE02);
6173
6174 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6175 }
6176
6177 void intel_init_gt_powersave(struct drm_device *dev)
6178 {
6179 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6180
6181 if (IS_CHERRYVIEW(dev))
6182 cherryview_init_gt_powersave(dev);
6183 else if (IS_VALLEYVIEW(dev))
6184 valleyview_init_gt_powersave(dev);
6185 }
6186
6187 void intel_cleanup_gt_powersave(struct drm_device *dev)
6188 {
6189 if (IS_CHERRYVIEW(dev))
6190 return;
6191 else if (IS_VALLEYVIEW(dev))
6192 valleyview_cleanup_gt_powersave(dev);
6193 }
6194
6195 static void gen6_suspend_rps(struct drm_device *dev)
6196 {
6197 struct drm_i915_private *dev_priv = dev->dev_private;
6198
6199 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6200
6201 gen6_disable_rps_interrupts(dev);
6202 }
6203
6204 /**
6205 * intel_suspend_gt_powersave - suspend PM work and helper threads
6206 * @dev: drm device
6207 *
6208 * We don't want to disable RC6 or other features here, we just want
6209 * to make sure any work we've queued has finished and won't bother
6210 * us while we're suspended.
6211 */
6212 void intel_suspend_gt_powersave(struct drm_device *dev)
6213 {
6214 struct drm_i915_private *dev_priv = dev->dev_private;
6215
6216 if (INTEL_INFO(dev)->gen < 6)
6217 return;
6218
6219 gen6_suspend_rps(dev);
6220
6221 /* Force GPU to min freq during suspend */
6222 gen6_rps_idle(dev_priv);
6223 }
6224
6225 void intel_disable_gt_powersave(struct drm_device *dev)
6226 {
6227 struct drm_i915_private *dev_priv = dev->dev_private;
6228
6229 if (IS_IRONLAKE_M(dev)) {
6230 ironlake_disable_drps(dev);
6231 } else if (INTEL_INFO(dev)->gen >= 6) {
6232 intel_suspend_gt_powersave(dev);
6233
6234 mutex_lock(&dev_priv->rps.hw_lock);
6235 if (INTEL_INFO(dev)->gen >= 9)
6236 gen9_disable_rps(dev);
6237 else if (IS_CHERRYVIEW(dev))
6238 cherryview_disable_rps(dev);
6239 else if (IS_VALLEYVIEW(dev))
6240 valleyview_disable_rps(dev);
6241 else
6242 gen6_disable_rps(dev);
6243
6244 dev_priv->rps.enabled = false;
6245 mutex_unlock(&dev_priv->rps.hw_lock);
6246 }
6247 }
6248
6249 static void intel_gen6_powersave_work(struct work_struct *work)
6250 {
6251 struct drm_i915_private *dev_priv =
6252 container_of(work, struct drm_i915_private,
6253 rps.delayed_resume_work.work);
6254 struct drm_device *dev = dev_priv->dev;
6255
6256 mutex_lock(&dev_priv->rps.hw_lock);
6257
6258 gen6_reset_rps_interrupts(dev);
6259
6260 if (IS_CHERRYVIEW(dev)) {
6261 cherryview_enable_rps(dev);
6262 } else if (IS_VALLEYVIEW(dev)) {
6263 valleyview_enable_rps(dev);
6264 } else if (INTEL_INFO(dev)->gen >= 9) {
6265 gen9_enable_rc6(dev);
6266 gen9_enable_rps(dev);
6267 if (IS_SKYLAKE(dev))
6268 __gen6_update_ring_freq(dev);
6269 } else if (IS_BROADWELL(dev)) {
6270 gen8_enable_rps(dev);
6271 __gen6_update_ring_freq(dev);
6272 } else {
6273 gen6_enable_rps(dev);
6274 __gen6_update_ring_freq(dev);
6275 }
6276
6277 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6278 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6279
6280 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6281 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6282
6283 dev_priv->rps.enabled = true;
6284
6285 gen6_enable_rps_interrupts(dev);
6286
6287 mutex_unlock(&dev_priv->rps.hw_lock);
6288
6289 intel_runtime_pm_put(dev_priv);
6290 }
6291
6292 void intel_enable_gt_powersave(struct drm_device *dev)
6293 {
6294 struct drm_i915_private *dev_priv = dev->dev_private;
6295
6296 /* Powersaving is controlled by the host when inside a VM */
6297 if (intel_vgpu_active(dev))
6298 return;
6299
6300 if (IS_IRONLAKE_M(dev)) {
6301 mutex_lock(&dev->struct_mutex);
6302 ironlake_enable_drps(dev);
6303 intel_init_emon(dev);
6304 mutex_unlock(&dev->struct_mutex);
6305 } else if (INTEL_INFO(dev)->gen >= 6) {
6306 /*
6307 * PCU communication is slow and this doesn't need to be
6308 * done at any specific time, so do this out of our fast path
6309 * to make resume and init faster.
6310 *
6311 * We depend on the HW RC6 power context save/restore
6312 * mechanism when entering D3 through runtime PM suspend. So
6313 * disable RPM until RPS/RC6 is properly setup. We can only
6314 * get here via the driver load/system resume/runtime resume
6315 * paths, so the _noresume version is enough (and in case of
6316 * runtime resume it's necessary).
6317 */
6318 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6319 round_jiffies_up_relative(HZ)))
6320 intel_runtime_pm_get_noresume(dev_priv);
6321 }
6322 }
6323
6324 void intel_reset_gt_powersave(struct drm_device *dev)
6325 {
6326 struct drm_i915_private *dev_priv = dev->dev_private;
6327
6328 if (INTEL_INFO(dev)->gen < 6)
6329 return;
6330
6331 gen6_suspend_rps(dev);
6332 dev_priv->rps.enabled = false;
6333 }
6334
6335 static void ibx_init_clock_gating(struct drm_device *dev)
6336 {
6337 struct drm_i915_private *dev_priv = dev->dev_private;
6338
6339 /*
6340 * On Ibex Peak and Cougar Point, we need to disable clock
6341 * gating for the panel power sequencer or it will fail to
6342 * start up when no ports are active.
6343 */
6344 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6345 }
6346
6347 static void g4x_disable_trickle_feed(struct drm_device *dev)
6348 {
6349 struct drm_i915_private *dev_priv = dev->dev_private;
6350 enum pipe pipe;
6351
6352 for_each_pipe(dev_priv, pipe) {
6353 I915_WRITE(DSPCNTR(pipe),
6354 I915_READ(DSPCNTR(pipe)) |
6355 DISPPLANE_TRICKLE_FEED_DISABLE);
6356
6357 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6358 POSTING_READ(DSPSURF(pipe));
6359 }
6360 }
6361
6362 static void ilk_init_lp_watermarks(struct drm_device *dev)
6363 {
6364 struct drm_i915_private *dev_priv = dev->dev_private;
6365
6366 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6367 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6368 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6369
6370 /*
6371 * Don't touch WM1S_LP_EN here.
6372 * Doing so could cause underruns.
6373 */
6374 }
6375
6376 static void ironlake_init_clock_gating(struct drm_device *dev)
6377 {
6378 struct drm_i915_private *dev_priv = dev->dev_private;
6379 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6380
6381 /*
6382 * Required for FBC
6383 * WaFbcDisableDpfcClockGating:ilk
6384 */
6385 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6386 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6387 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6388
6389 I915_WRITE(PCH_3DCGDIS0,
6390 MARIUNIT_CLOCK_GATE_DISABLE |
6391 SVSMUNIT_CLOCK_GATE_DISABLE);
6392 I915_WRITE(PCH_3DCGDIS1,
6393 VFMUNIT_CLOCK_GATE_DISABLE);
6394
6395 /*
6396 * According to the spec the following bits should be set in
6397 * order to enable memory self-refresh
6398 * The bit 22/21 of 0x42004
6399 * The bit 5 of 0x42020
6400 * The bit 15 of 0x45000
6401 */
6402 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6403 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6404 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6405 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6406 I915_WRITE(DISP_ARB_CTL,
6407 (I915_READ(DISP_ARB_CTL) |
6408 DISP_FBC_WM_DIS));
6409
6410 ilk_init_lp_watermarks(dev);
6411
6412 /*
6413 * Based on the document from hardware guys the following bits
6414 * should be set unconditionally in order to enable FBC.
6415 * The bit 22 of 0x42000
6416 * The bit 22 of 0x42004
6417 * The bit 7,8,9 of 0x42020.
6418 */
6419 if (IS_IRONLAKE_M(dev)) {
6420 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6421 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6422 I915_READ(ILK_DISPLAY_CHICKEN1) |
6423 ILK_FBCQ_DIS);
6424 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6425 I915_READ(ILK_DISPLAY_CHICKEN2) |
6426 ILK_DPARB_GATE);
6427 }
6428
6429 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6430
6431 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6432 I915_READ(ILK_DISPLAY_CHICKEN2) |
6433 ILK_ELPIN_409_SELECT);
6434 I915_WRITE(_3D_CHICKEN2,
6435 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6436 _3D_CHICKEN2_WM_READ_PIPELINED);
6437
6438 /* WaDisableRenderCachePipelinedFlush:ilk */
6439 I915_WRITE(CACHE_MODE_0,
6440 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6441
6442 /* WaDisable_RenderCache_OperationalFlush:ilk */
6443 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6444
6445 g4x_disable_trickle_feed(dev);
6446
6447 ibx_init_clock_gating(dev);
6448 }
6449
6450 static void cpt_init_clock_gating(struct drm_device *dev)
6451 {
6452 struct drm_i915_private *dev_priv = dev->dev_private;
6453 int pipe;
6454 uint32_t val;
6455
6456 /*
6457 * On Ibex Peak and Cougar Point, we need to disable clock
6458 * gating for the panel power sequencer or it will fail to
6459 * start up when no ports are active.
6460 */
6461 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6462 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6463 PCH_CPUNIT_CLOCK_GATE_DISABLE);
6464 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6465 DPLS_EDP_PPS_FIX_DIS);
6466 /* The below fixes the weird display corruption, a few pixels shifted
6467 * downward, on (only) LVDS of some HP laptops with IVY.
6468 */
6469 for_each_pipe(dev_priv, pipe) {
6470 val = I915_READ(TRANS_CHICKEN2(pipe));
6471 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6472 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6473 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6474 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6475 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6476 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6477 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6478 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6479 }
6480 /* WADP0ClockGatingDisable */
6481 for_each_pipe(dev_priv, pipe) {
6482 I915_WRITE(TRANS_CHICKEN1(pipe),
6483 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6484 }
6485 }
6486
6487 static void gen6_check_mch_setup(struct drm_device *dev)
6488 {
6489 struct drm_i915_private *dev_priv = dev->dev_private;
6490 uint32_t tmp;
6491
6492 tmp = I915_READ(MCH_SSKPD);
6493 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6494 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6495 tmp);
6496 }
6497
6498 static void gen6_init_clock_gating(struct drm_device *dev)
6499 {
6500 struct drm_i915_private *dev_priv = dev->dev_private;
6501 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6502
6503 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6504
6505 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6506 I915_READ(ILK_DISPLAY_CHICKEN2) |
6507 ILK_ELPIN_409_SELECT);
6508
6509 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6510 I915_WRITE(_3D_CHICKEN,
6511 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6512
6513 /* WaDisable_RenderCache_OperationalFlush:snb */
6514 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6515
6516 /*
6517 * BSpec recoomends 8x4 when MSAA is used,
6518 * however in practice 16x4 seems fastest.
6519 *
6520 * Note that PS/WM thread counts depend on the WIZ hashing
6521 * disable bit, which we don't touch here, but it's good
6522 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6523 */
6524 I915_WRITE(GEN6_GT_MODE,
6525 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6526
6527 ilk_init_lp_watermarks(dev);
6528
6529 I915_WRITE(CACHE_MODE_0,
6530 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6531
6532 I915_WRITE(GEN6_UCGCTL1,
6533 I915_READ(GEN6_UCGCTL1) |
6534 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6535 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6536
6537 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6538 * gating disable must be set. Failure to set it results in
6539 * flickering pixels due to Z write ordering failures after
6540 * some amount of runtime in the Mesa "fire" demo, and Unigine
6541 * Sanctuary and Tropics, and apparently anything else with
6542 * alpha test or pixel discard.
6543 *
6544 * According to the spec, bit 11 (RCCUNIT) must also be set,
6545 * but we didn't debug actual testcases to find it out.
6546 *
6547 * WaDisableRCCUnitClockGating:snb
6548 * WaDisableRCPBUnitClockGating:snb
6549 */
6550 I915_WRITE(GEN6_UCGCTL2,
6551 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6552 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6553
6554 /* WaStripsFansDisableFastClipPerformanceFix:snb */
6555 I915_WRITE(_3D_CHICKEN3,
6556 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6557
6558 /*
6559 * Bspec says:
6560 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6561 * 3DSTATE_SF number of SF output attributes is more than 16."
6562 */
6563 I915_WRITE(_3D_CHICKEN3,
6564 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6565
6566 /*
6567 * According to the spec the following bits should be
6568 * set in order to enable memory self-refresh and fbc:
6569 * The bit21 and bit22 of 0x42000
6570 * The bit21 and bit22 of 0x42004
6571 * The bit5 and bit7 of 0x42020
6572 * The bit14 of 0x70180
6573 * The bit14 of 0x71180
6574 *
6575 * WaFbcAsynchFlipDisableFbcQueue:snb
6576 */
6577 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6578 I915_READ(ILK_DISPLAY_CHICKEN1) |
6579 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6580 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6581 I915_READ(ILK_DISPLAY_CHICKEN2) |
6582 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6583 I915_WRITE(ILK_DSPCLK_GATE_D,
6584 I915_READ(ILK_DSPCLK_GATE_D) |
6585 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6586 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6587
6588 g4x_disable_trickle_feed(dev);
6589
6590 cpt_init_clock_gating(dev);
6591
6592 gen6_check_mch_setup(dev);
6593 }
6594
6595 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6596 {
6597 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6598
6599 /*
6600 * WaVSThreadDispatchOverride:ivb,vlv
6601 *
6602 * This actually overrides the dispatch
6603 * mode for all thread types.
6604 */
6605 reg &= ~GEN7_FF_SCHED_MASK;
6606 reg |= GEN7_FF_TS_SCHED_HW;
6607 reg |= GEN7_FF_VS_SCHED_HW;
6608 reg |= GEN7_FF_DS_SCHED_HW;
6609
6610 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6611 }
6612
6613 static void lpt_init_clock_gating(struct drm_device *dev)
6614 {
6615 struct drm_i915_private *dev_priv = dev->dev_private;
6616
6617 /*
6618 * TODO: this bit should only be enabled when really needed, then
6619 * disabled when not needed anymore in order to save power.
6620 */
6621 if (HAS_PCH_LPT_LP(dev))
6622 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6623 I915_READ(SOUTH_DSPCLK_GATE_D) |
6624 PCH_LP_PARTITION_LEVEL_DISABLE);
6625
6626 /* WADPOClockGatingDisable:hsw */
6627 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6628 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6629 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6630 }
6631
6632 static void lpt_suspend_hw(struct drm_device *dev)
6633 {
6634 struct drm_i915_private *dev_priv = dev->dev_private;
6635
6636 if (HAS_PCH_LPT_LP(dev)) {
6637 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6638
6639 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6640 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6641 }
6642 }
6643
6644 static void broadwell_init_clock_gating(struct drm_device *dev)
6645 {
6646 struct drm_i915_private *dev_priv = dev->dev_private;
6647 enum pipe pipe;
6648 uint32_t misccpctl;
6649
6650 ilk_init_lp_watermarks(dev);
6651
6652 /* WaSwitchSolVfFArbitrationPriority:bdw */
6653 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6654
6655 /* WaPsrDPAMaskVBlankInSRD:bdw */
6656 I915_WRITE(CHICKEN_PAR1_1,
6657 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6658
6659 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6660 for_each_pipe(dev_priv, pipe) {
6661 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6662 I915_READ(CHICKEN_PIPESL_1(pipe)) |
6663 BDW_DPRS_MASK_VBLANK_SRD);
6664 }
6665
6666 /* WaVSRefCountFullforceMissDisable:bdw */
6667 /* WaDSRefCountFullforceMissDisable:bdw */
6668 I915_WRITE(GEN7_FF_THREAD_MODE,
6669 I915_READ(GEN7_FF_THREAD_MODE) &
6670 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6671
6672 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6673 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6674
6675 /* WaDisableSDEUnitClockGating:bdw */
6676 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6677 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6678
6679 /*
6680 * WaProgramL3SqcReg1Default:bdw
6681 * WaTempDisableDOPClkGating:bdw
6682 */
6683 misccpctl = I915_READ(GEN7_MISCCPCTL);
6684 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6685 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6686 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6687
6688 /*
6689 * WaGttCachingOffByDefault:bdw
6690 * GTT cache may not work with big pages, so if those
6691 * are ever enabled GTT cache may need to be disabled.
6692 */
6693 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6694
6695 lpt_init_clock_gating(dev);
6696 }
6697
6698 static void haswell_init_clock_gating(struct drm_device *dev)
6699 {
6700 struct drm_i915_private *dev_priv = dev->dev_private;
6701
6702 ilk_init_lp_watermarks(dev);
6703
6704 /* L3 caching of data atomics doesn't work -- disable it. */
6705 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6706 I915_WRITE(HSW_ROW_CHICKEN3,
6707 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6708
6709 /* This is required by WaCatErrorRejectionIssue:hsw */
6710 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6711 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6712 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6713
6714 /* WaVSRefCountFullforceMissDisable:hsw */
6715 I915_WRITE(GEN7_FF_THREAD_MODE,
6716 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6717
6718 /* WaDisable_RenderCache_OperationalFlush:hsw */
6719 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6720
6721 /* enable HiZ Raw Stall Optimization */
6722 I915_WRITE(CACHE_MODE_0_GEN7,
6723 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6724
6725 /* WaDisable4x2SubspanOptimization:hsw */
6726 I915_WRITE(CACHE_MODE_1,
6727 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6728
6729 /*
6730 * BSpec recommends 8x4 when MSAA is used,
6731 * however in practice 16x4 seems fastest.
6732 *
6733 * Note that PS/WM thread counts depend on the WIZ hashing
6734 * disable bit, which we don't touch here, but it's good
6735 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6736 */
6737 I915_WRITE(GEN7_GT_MODE,
6738 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6739
6740 /* WaSampleCChickenBitEnable:hsw */
6741 I915_WRITE(HALF_SLICE_CHICKEN3,
6742 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6743
6744 /* WaSwitchSolVfFArbitrationPriority:hsw */
6745 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6746
6747 /* WaRsPkgCStateDisplayPMReq:hsw */
6748 I915_WRITE(CHICKEN_PAR1_1,
6749 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6750
6751 lpt_init_clock_gating(dev);
6752 }
6753
6754 static void ivybridge_init_clock_gating(struct drm_device *dev)
6755 {
6756 struct drm_i915_private *dev_priv = dev->dev_private;
6757 uint32_t snpcr;
6758
6759 ilk_init_lp_watermarks(dev);
6760
6761 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6762
6763 /* WaDisableEarlyCull:ivb */
6764 I915_WRITE(_3D_CHICKEN3,
6765 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6766
6767 /* WaDisableBackToBackFlipFix:ivb */
6768 I915_WRITE(IVB_CHICKEN3,
6769 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6770 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6771
6772 /* WaDisablePSDDualDispatchEnable:ivb */
6773 if (IS_IVB_GT1(dev))
6774 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6775 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6776
6777 /* WaDisable_RenderCache_OperationalFlush:ivb */
6778 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6779
6780 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6781 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6782 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6783
6784 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6785 I915_WRITE(GEN7_L3CNTLREG1,
6786 GEN7_WA_FOR_GEN7_L3_CONTROL);
6787 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6788 GEN7_WA_L3_CHICKEN_MODE);
6789 if (IS_IVB_GT1(dev))
6790 I915_WRITE(GEN7_ROW_CHICKEN2,
6791 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6792 else {
6793 /* must write both registers */
6794 I915_WRITE(GEN7_ROW_CHICKEN2,
6795 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6796 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6797 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6798 }
6799
6800 /* WaForceL3Serialization:ivb */
6801 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6802 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6803
6804 /*
6805 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6806 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6807 */
6808 I915_WRITE(GEN6_UCGCTL2,
6809 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6810
6811 /* This is required by WaCatErrorRejectionIssue:ivb */
6812 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6813 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6814 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6815
6816 g4x_disable_trickle_feed(dev);
6817
6818 gen7_setup_fixed_func_scheduler(dev_priv);
6819
6820 if (0) { /* causes HiZ corruption on ivb:gt1 */
6821 /* enable HiZ Raw Stall Optimization */
6822 I915_WRITE(CACHE_MODE_0_GEN7,
6823 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6824 }
6825
6826 /* WaDisable4x2SubspanOptimization:ivb */
6827 I915_WRITE(CACHE_MODE_1,
6828 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6829
6830 /*
6831 * BSpec recommends 8x4 when MSAA is used,
6832 * however in practice 16x4 seems fastest.
6833 *
6834 * Note that PS/WM thread counts depend on the WIZ hashing
6835 * disable bit, which we don't touch here, but it's good
6836 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6837 */
6838 I915_WRITE(GEN7_GT_MODE,
6839 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6840
6841 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6842 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6843 snpcr |= GEN6_MBC_SNPCR_MED;
6844 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6845
6846 if (!HAS_PCH_NOP(dev))
6847 cpt_init_clock_gating(dev);
6848
6849 gen6_check_mch_setup(dev);
6850 }
6851
6852 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6853 {
6854 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6855
6856 /*
6857 * Disable trickle feed and enable pnd deadline calculation
6858 */
6859 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6860 I915_WRITE(CBR1_VLV, 0);
6861 }
6862
6863 static void valleyview_init_clock_gating(struct drm_device *dev)
6864 {
6865 struct drm_i915_private *dev_priv = dev->dev_private;
6866
6867 vlv_init_display_clock_gating(dev_priv);
6868
6869 /* WaDisableEarlyCull:vlv */
6870 I915_WRITE(_3D_CHICKEN3,
6871 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6872
6873 /* WaDisableBackToBackFlipFix:vlv */
6874 I915_WRITE(IVB_CHICKEN3,
6875 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6876 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6877
6878 /* WaPsdDispatchEnable:vlv */
6879 /* WaDisablePSDDualDispatchEnable:vlv */
6880 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6881 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6882 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6883
6884 /* WaDisable_RenderCache_OperationalFlush:vlv */
6885 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6886
6887 /* WaForceL3Serialization:vlv */
6888 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6889 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6890
6891 /* WaDisableDopClockGating:vlv */
6892 I915_WRITE(GEN7_ROW_CHICKEN2,
6893 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6894
6895 /* This is required by WaCatErrorRejectionIssue:vlv */
6896 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6897 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6898 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6899
6900 gen7_setup_fixed_func_scheduler(dev_priv);
6901
6902 /*
6903 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6904 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6905 */
6906 I915_WRITE(GEN6_UCGCTL2,
6907 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6908
6909 /* WaDisableL3Bank2xClockGate:vlv
6910 * Disabling L3 clock gating- MMIO 940c[25] = 1
6911 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6912 I915_WRITE(GEN7_UCGCTL4,
6913 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6914
6915 /*
6916 * BSpec says this must be set, even though
6917 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6918 */
6919 I915_WRITE(CACHE_MODE_1,
6920 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6921
6922 /*
6923 * BSpec recommends 8x4 when MSAA is used,
6924 * however in practice 16x4 seems fastest.
6925 *
6926 * Note that PS/WM thread counts depend on the WIZ hashing
6927 * disable bit, which we don't touch here, but it's good
6928 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6929 */
6930 I915_WRITE(GEN7_GT_MODE,
6931 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6932
6933 /*
6934 * WaIncreaseL3CreditsForVLVB0:vlv
6935 * This is the hardware default actually.
6936 */
6937 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6938
6939 /*
6940 * WaDisableVLVClockGating_VBIIssue:vlv
6941 * Disable clock gating on th GCFG unit to prevent a delay
6942 * in the reporting of vblank events.
6943 */
6944 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6945 }
6946
6947 static void cherryview_init_clock_gating(struct drm_device *dev)
6948 {
6949 struct drm_i915_private *dev_priv = dev->dev_private;
6950
6951 vlv_init_display_clock_gating(dev_priv);
6952
6953 /* WaVSRefCountFullforceMissDisable:chv */
6954 /* WaDSRefCountFullforceMissDisable:chv */
6955 I915_WRITE(GEN7_FF_THREAD_MODE,
6956 I915_READ(GEN7_FF_THREAD_MODE) &
6957 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6958
6959 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6960 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6961 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6962
6963 /* WaDisableCSUnitClockGating:chv */
6964 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6965 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6966
6967 /* WaDisableSDEUnitClockGating:chv */
6968 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6969 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6970
6971 /*
6972 * GTT cache may not work with big pages, so if those
6973 * are ever enabled GTT cache may need to be disabled.
6974 */
6975 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6976 }
6977
6978 static void g4x_init_clock_gating(struct drm_device *dev)
6979 {
6980 struct drm_i915_private *dev_priv = dev->dev_private;
6981 uint32_t dspclk_gate;
6982
6983 I915_WRITE(RENCLK_GATE_D1, 0);
6984 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6985 GS_UNIT_CLOCK_GATE_DISABLE |
6986 CL_UNIT_CLOCK_GATE_DISABLE);
6987 I915_WRITE(RAMCLK_GATE_D, 0);
6988 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6989 OVRUNIT_CLOCK_GATE_DISABLE |
6990 OVCUNIT_CLOCK_GATE_DISABLE;
6991 if (IS_GM45(dev))
6992 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6993 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6994
6995 /* WaDisableRenderCachePipelinedFlush */
6996 I915_WRITE(CACHE_MODE_0,
6997 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6998
6999 /* WaDisable_RenderCache_OperationalFlush:g4x */
7000 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7001
7002 g4x_disable_trickle_feed(dev);
7003 }
7004
7005 static void crestline_init_clock_gating(struct drm_device *dev)
7006 {
7007 struct drm_i915_private *dev_priv = dev->dev_private;
7008
7009 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7010 I915_WRITE(RENCLK_GATE_D2, 0);
7011 I915_WRITE(DSPCLK_GATE_D, 0);
7012 I915_WRITE(RAMCLK_GATE_D, 0);
7013 I915_WRITE16(DEUC, 0);
7014 I915_WRITE(MI_ARB_STATE,
7015 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7016
7017 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7018 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7019 }
7020
7021 static void broadwater_init_clock_gating(struct drm_device *dev)
7022 {
7023 struct drm_i915_private *dev_priv = dev->dev_private;
7024
7025 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7026 I965_RCC_CLOCK_GATE_DISABLE |
7027 I965_RCPB_CLOCK_GATE_DISABLE |
7028 I965_ISC_CLOCK_GATE_DISABLE |
7029 I965_FBC_CLOCK_GATE_DISABLE);
7030 I915_WRITE(RENCLK_GATE_D2, 0);
7031 I915_WRITE(MI_ARB_STATE,
7032 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7033
7034 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7035 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7036 }
7037
7038 static void gen3_init_clock_gating(struct drm_device *dev)
7039 {
7040 struct drm_i915_private *dev_priv = dev->dev_private;
7041 u32 dstate = I915_READ(D_STATE);
7042
7043 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7044 DSTATE_DOT_CLOCK_GATING;
7045 I915_WRITE(D_STATE, dstate);
7046
7047 if (IS_PINEVIEW(dev))
7048 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7049
7050 /* IIR "flip pending" means done if this bit is set */
7051 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7052
7053 /* interrupts should cause a wake up from C3 */
7054 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7055
7056 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7057 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7058
7059 I915_WRITE(MI_ARB_STATE,
7060 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7061 }
7062
7063 static void i85x_init_clock_gating(struct drm_device *dev)
7064 {
7065 struct drm_i915_private *dev_priv = dev->dev_private;
7066
7067 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7068
7069 /* interrupts should cause a wake up from C3 */
7070 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7071 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7072
7073 I915_WRITE(MEM_MODE,
7074 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7075 }
7076
7077 static void i830_init_clock_gating(struct drm_device *dev)
7078 {
7079 struct drm_i915_private *dev_priv = dev->dev_private;
7080
7081 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7082
7083 I915_WRITE(MEM_MODE,
7084 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7085 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7086 }
7087
7088 void intel_init_clock_gating(struct drm_device *dev)
7089 {
7090 struct drm_i915_private *dev_priv = dev->dev_private;
7091
7092 if (dev_priv->display.init_clock_gating)
7093 dev_priv->display.init_clock_gating(dev);
7094 }
7095
7096 void intel_suspend_hw(struct drm_device *dev)
7097 {
7098 if (HAS_PCH_LPT(dev))
7099 lpt_suspend_hw(dev);
7100 }
7101
7102 /* Set up chip specific power management-related functions */
7103 void intel_init_pm(struct drm_device *dev)
7104 {
7105 struct drm_i915_private *dev_priv = dev->dev_private;
7106
7107 intel_fbc_init(dev_priv);
7108
7109 /* For cxsr */
7110 if (IS_PINEVIEW(dev))
7111 i915_pineview_get_mem_freq(dev);
7112 else if (IS_GEN5(dev))
7113 i915_ironlake_get_mem_freq(dev);
7114
7115 /* For FIFO watermark updates */
7116 if (INTEL_INFO(dev)->gen >= 9) {
7117 skl_setup_wm_latency(dev);
7118
7119 if (IS_BROXTON(dev))
7120 dev_priv->display.init_clock_gating =
7121 bxt_init_clock_gating;
7122 else if (IS_SKYLAKE(dev))
7123 dev_priv->display.init_clock_gating =
7124 skl_init_clock_gating;
7125 dev_priv->display.update_wm = skl_update_wm;
7126 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
7127 } else if (HAS_PCH_SPLIT(dev)) {
7128 ilk_setup_wm_latency(dev);
7129
7130 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7131 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7132 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7133 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7134 dev_priv->display.update_wm = ilk_update_wm;
7135 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7136 } else {
7137 DRM_DEBUG_KMS("Failed to read display plane latency. "
7138 "Disable CxSR\n");
7139 }
7140
7141 if (IS_GEN5(dev))
7142 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7143 else if (IS_GEN6(dev))
7144 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7145 else if (IS_IVYBRIDGE(dev))
7146 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7147 else if (IS_HASWELL(dev))
7148 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7149 else if (INTEL_INFO(dev)->gen == 8)
7150 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7151 } else if (IS_CHERRYVIEW(dev)) {
7152 vlv_setup_wm_latency(dev);
7153
7154 dev_priv->display.update_wm = vlv_update_wm;
7155 dev_priv->display.init_clock_gating =
7156 cherryview_init_clock_gating;
7157 } else if (IS_VALLEYVIEW(dev)) {
7158 vlv_setup_wm_latency(dev);
7159
7160 dev_priv->display.update_wm = vlv_update_wm;
7161 dev_priv->display.init_clock_gating =
7162 valleyview_init_clock_gating;
7163 } else if (IS_PINEVIEW(dev)) {
7164 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7165 dev_priv->is_ddr3,
7166 dev_priv->fsb_freq,
7167 dev_priv->mem_freq)) {
7168 DRM_INFO("failed to find known CxSR latency "
7169 "(found ddr%s fsb freq %d, mem freq %d), "
7170 "disabling CxSR\n",
7171 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7172 dev_priv->fsb_freq, dev_priv->mem_freq);
7173 /* Disable CxSR and never update its watermark again */
7174 intel_set_memory_cxsr(dev_priv, false);
7175 dev_priv->display.update_wm = NULL;
7176 } else
7177 dev_priv->display.update_wm = pineview_update_wm;
7178 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7179 } else if (IS_G4X(dev)) {
7180 dev_priv->display.update_wm = g4x_update_wm;
7181 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7182 } else if (IS_GEN4(dev)) {
7183 dev_priv->display.update_wm = i965_update_wm;
7184 if (IS_CRESTLINE(dev))
7185 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7186 else if (IS_BROADWATER(dev))
7187 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7188 } else if (IS_GEN3(dev)) {
7189 dev_priv->display.update_wm = i9xx_update_wm;
7190 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7191 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7192 } else if (IS_GEN2(dev)) {
7193 if (INTEL_INFO(dev)->num_pipes == 1) {
7194 dev_priv->display.update_wm = i845_update_wm;
7195 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7196 } else {
7197 dev_priv->display.update_wm = i9xx_update_wm;
7198 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7199 }
7200
7201 if (IS_I85X(dev) || IS_I865G(dev))
7202 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7203 else
7204 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7205 } else {
7206 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7207 }
7208 }
7209
7210 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7211 {
7212 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7213
7214 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7215 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7216 return -EAGAIN;
7217 }
7218
7219 I915_WRITE(GEN6_PCODE_DATA, *val);
7220 I915_WRITE(GEN6_PCODE_DATA1, 0);
7221 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7222
7223 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7224 500)) {
7225 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7226 return -ETIMEDOUT;
7227 }
7228
7229 *val = I915_READ(GEN6_PCODE_DATA);
7230 I915_WRITE(GEN6_PCODE_DATA, 0);
7231
7232 return 0;
7233 }
7234
7235 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7236 {
7237 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7238
7239 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7240 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7241 return -EAGAIN;
7242 }
7243
7244 I915_WRITE(GEN6_PCODE_DATA, val);
7245 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7246
7247 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7248 500)) {
7249 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7250 return -ETIMEDOUT;
7251 }
7252
7253 I915_WRITE(GEN6_PCODE_DATA, 0);
7254
7255 return 0;
7256 }
7257
7258 static int vlv_gpu_freq_div(unsigned int czclk_freq)
7259 {
7260 switch (czclk_freq) {
7261 case 200:
7262 return 10;
7263 case 267:
7264 return 12;
7265 case 320:
7266 case 333:
7267 return 16;
7268 case 400:
7269 return 20;
7270 default:
7271 return -1;
7272 }
7273 }
7274
7275 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7276 {
7277 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7278
7279 div = vlv_gpu_freq_div(czclk_freq);
7280 if (div < 0)
7281 return div;
7282
7283 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7284 }
7285
7286 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7287 {
7288 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7289
7290 mul = vlv_gpu_freq_div(czclk_freq);
7291 if (mul < 0)
7292 return mul;
7293
7294 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7295 }
7296
7297 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7298 {
7299 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7300
7301 div = vlv_gpu_freq_div(czclk_freq) / 2;
7302 if (div < 0)
7303 return div;
7304
7305 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7306 }
7307
7308 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7309 {
7310 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7311
7312 mul = vlv_gpu_freq_div(czclk_freq) / 2;
7313 if (mul < 0)
7314 return mul;
7315
7316 /* CHV needs even values */
7317 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7318 }
7319
7320 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7321 {
7322 if (IS_GEN9(dev_priv->dev))
7323 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
7324 else if (IS_CHERRYVIEW(dev_priv->dev))
7325 return chv_gpu_freq(dev_priv, val);
7326 else if (IS_VALLEYVIEW(dev_priv->dev))
7327 return byt_gpu_freq(dev_priv, val);
7328 else
7329 return val * GT_FREQUENCY_MULTIPLIER;
7330 }
7331
7332 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7333 {
7334 if (IS_GEN9(dev_priv->dev))
7335 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
7336 else if (IS_CHERRYVIEW(dev_priv->dev))
7337 return chv_freq_opcode(dev_priv, val);
7338 else if (IS_VALLEYVIEW(dev_priv->dev))
7339 return byt_freq_opcode(dev_priv, val);
7340 else
7341 return val / GT_FREQUENCY_MULTIPLIER;
7342 }
7343
7344 struct request_boost {
7345 struct work_struct work;
7346 struct drm_i915_gem_request *req;
7347 };
7348
7349 static void __intel_rps_boost_work(struct work_struct *work)
7350 {
7351 struct request_boost *boost = container_of(work, struct request_boost, work);
7352 struct drm_i915_gem_request *req = boost->req;
7353
7354 if (!i915_gem_request_completed(req, true))
7355 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7356 req->emitted_jiffies);
7357
7358 i915_gem_request_unreference__unlocked(req);
7359 kfree(boost);
7360 }
7361
7362 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7363 struct drm_i915_gem_request *req)
7364 {
7365 struct request_boost *boost;
7366
7367 if (req == NULL || INTEL_INFO(dev)->gen < 6)
7368 return;
7369
7370 if (i915_gem_request_completed(req, true))
7371 return;
7372
7373 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7374 if (boost == NULL)
7375 return;
7376
7377 i915_gem_request_reference(req);
7378 boost->req = req;
7379
7380 INIT_WORK(&boost->work, __intel_rps_boost_work);
7381 queue_work(to_i915(dev)->wq, &boost->work);
7382 }
7383
7384 void intel_pm_setup(struct drm_device *dev)
7385 {
7386 struct drm_i915_private *dev_priv = dev->dev_private;
7387
7388 mutex_init(&dev_priv->rps.hw_lock);
7389 spin_lock_init(&dev_priv->rps.client_lock);
7390
7391 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7392 intel_gen6_powersave_work);
7393 INIT_LIST_HEAD(&dev_priv->rps.clients);
7394 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7395 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7396
7397 dev_priv->pm.suspended = false;
7398 }
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