2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
29 #include <drm/drm_plane_helper.h>
31 #include "intel_drv.h"
32 #include "../../../platform/x86/intel_ips.h"
33 #include <linux/module.h>
34 #include <drm/drm_atomic_helper.h>
39 * RC6 is a special power stage which allows the GPU to enter an very
40 * low-voltage mode when idle, using down to 0V while at this stage. This
41 * stage is entered automatically when the GPU is idle when RC6 support is
42 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
44 * There are different RC6 modes available in Intel GPU, which differentiate
45 * among each other with the latency required to enter and leave RC6 and
46 * voltage consumed by the GPU in different states.
48 * The combination of the following flags define which states GPU is allowed
49 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
50 * RC6pp is deepest RC6. Their support by hardware varies according to the
51 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
52 * which brings the most power savings; deeper states save more power, but
53 * require higher latency to switch to and wake up.
55 #define INTEL_RC6_ENABLE (1<<0)
56 #define INTEL_RC6p_ENABLE (1<<1)
57 #define INTEL_RC6pp_ENABLE (1<<2)
59 static void gen9_init_clock_gating(struct drm_i915_private
*dev_priv
)
61 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
62 I915_WRITE(CHICKEN_PAR1_1
,
63 I915_READ(CHICKEN_PAR1_1
) | SKL_EDP_PSR_FIX_RDWRAP
);
65 I915_WRITE(GEN8_CONFIG0
,
66 I915_READ(GEN8_CONFIG0
) | GEN9_DEFAULT_FIXES
);
68 /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
69 I915_WRITE(GEN8_CHICKEN_DCPR_1
,
70 I915_READ(GEN8_CHICKEN_DCPR_1
) | MASK_WAKEMEM
);
72 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
73 /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
74 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
76 DISP_FBC_MEMORY_WAKE
);
78 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
79 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
80 ILK_DPFC_DISABLE_DUMMY0
);
83 static void bxt_init_clock_gating(struct drm_i915_private
*dev_priv
)
85 gen9_init_clock_gating(dev_priv
);
87 /* WaDisableSDEUnitClockGating:bxt */
88 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
89 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
93 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
95 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
96 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ
);
99 * Wa: Backlight PWM may stop in the asserted state, causing backlight
102 I915_WRITE(GEN9_CLKGATE_DIS_0
, I915_READ(GEN9_CLKGATE_DIS_0
) |
103 PWM1_GATING_DIS
| PWM2_GATING_DIS
);
106 static void glk_init_clock_gating(struct drm_i915_private
*dev_priv
)
108 gen9_init_clock_gating(dev_priv
);
111 * WaDisablePWMClockGating:glk
112 * Backlight PWM may stop in the asserted state, causing backlight
115 I915_WRITE(GEN9_CLKGATE_DIS_0
, I915_READ(GEN9_CLKGATE_DIS_0
) |
116 PWM1_GATING_DIS
| PWM2_GATING_DIS
);
118 /* WaDDIIOTimeout:glk */
119 if (IS_GLK_REVID(dev_priv
, 0, GLK_REVID_A1
)) {
120 u32 val
= I915_READ(CHICKEN_MISC_2
);
121 val
&= ~(GLK_CL0_PWR_DOWN
|
124 I915_WRITE(CHICKEN_MISC_2
, val
);
129 static void i915_pineview_get_mem_freq(struct drm_i915_private
*dev_priv
)
133 tmp
= I915_READ(CLKCFG
);
135 switch (tmp
& CLKCFG_FSB_MASK
) {
137 dev_priv
->fsb_freq
= 533; /* 133*4 */
140 dev_priv
->fsb_freq
= 800; /* 200*4 */
143 dev_priv
->fsb_freq
= 667; /* 167*4 */
146 dev_priv
->fsb_freq
= 400; /* 100*4 */
150 switch (tmp
& CLKCFG_MEM_MASK
) {
152 dev_priv
->mem_freq
= 533;
155 dev_priv
->mem_freq
= 667;
158 dev_priv
->mem_freq
= 800;
162 /* detect pineview DDR3 setting */
163 tmp
= I915_READ(CSHRDDR3CTL
);
164 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
167 static void i915_ironlake_get_mem_freq(struct drm_i915_private
*dev_priv
)
171 ddrpll
= I915_READ16(DDRMPLL1
);
172 csipll
= I915_READ16(CSIPLL0
);
174 switch (ddrpll
& 0xff) {
176 dev_priv
->mem_freq
= 800;
179 dev_priv
->mem_freq
= 1066;
182 dev_priv
->mem_freq
= 1333;
185 dev_priv
->mem_freq
= 1600;
188 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
190 dev_priv
->mem_freq
= 0;
194 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
196 switch (csipll
& 0x3ff) {
198 dev_priv
->fsb_freq
= 3200;
201 dev_priv
->fsb_freq
= 3733;
204 dev_priv
->fsb_freq
= 4266;
207 dev_priv
->fsb_freq
= 4800;
210 dev_priv
->fsb_freq
= 5333;
213 dev_priv
->fsb_freq
= 5866;
216 dev_priv
->fsb_freq
= 6400;
219 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
221 dev_priv
->fsb_freq
= 0;
225 if (dev_priv
->fsb_freq
== 3200) {
226 dev_priv
->ips
.c_m
= 0;
227 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
228 dev_priv
->ips
.c_m
= 1;
230 dev_priv
->ips
.c_m
= 2;
234 static const struct cxsr_latency cxsr_latency_table
[] = {
235 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
236 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
237 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
238 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
239 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
241 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
242 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
243 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
244 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
245 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
247 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
248 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
249 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
250 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
251 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
253 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
254 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
255 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
256 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
257 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
259 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
260 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
261 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
262 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
263 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
265 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
266 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
267 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
268 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
269 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
272 static const struct cxsr_latency
*intel_get_cxsr_latency(bool is_desktop
,
277 const struct cxsr_latency
*latency
;
280 if (fsb
== 0 || mem
== 0)
283 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
284 latency
= &cxsr_latency_table
[i
];
285 if (is_desktop
== latency
->is_desktop
&&
286 is_ddr3
== latency
->is_ddr3
&&
287 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
291 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
296 static void chv_set_memory_dvfs(struct drm_i915_private
*dev_priv
, bool enable
)
300 mutex_lock(&dev_priv
->rps
.hw_lock
);
302 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
304 val
&= ~FORCE_DDR_HIGH_FREQ
;
306 val
|= FORCE_DDR_HIGH_FREQ
;
307 val
&= ~FORCE_DDR_LOW_FREQ
;
308 val
|= FORCE_DDR_FREQ_REQ_ACK
;
309 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
311 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
312 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3))
313 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
315 mutex_unlock(&dev_priv
->rps
.hw_lock
);
318 static void chv_set_memory_pm5(struct drm_i915_private
*dev_priv
, bool enable
)
322 mutex_lock(&dev_priv
->rps
.hw_lock
);
324 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
326 val
|= DSP_MAXFIFO_PM5_ENABLE
;
328 val
&= ~DSP_MAXFIFO_PM5_ENABLE
;
329 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
331 mutex_unlock(&dev_priv
->rps
.hw_lock
);
334 #define FW_WM(value, plane) \
335 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
337 static bool _intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
342 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
343 was_enabled
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
344 I915_WRITE(FW_BLC_SELF_VLV
, enable
? FW_CSPWRDWNEN
: 0);
345 POSTING_READ(FW_BLC_SELF_VLV
);
346 } else if (IS_G4X(dev_priv
) || IS_I965GM(dev_priv
)) {
347 was_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
348 I915_WRITE(FW_BLC_SELF
, enable
? FW_BLC_SELF_EN
: 0);
349 POSTING_READ(FW_BLC_SELF
);
350 } else if (IS_PINEVIEW(dev_priv
)) {
351 val
= I915_READ(DSPFW3
);
352 was_enabled
= val
& PINEVIEW_SELF_REFRESH_EN
;
354 val
|= PINEVIEW_SELF_REFRESH_EN
;
356 val
&= ~PINEVIEW_SELF_REFRESH_EN
;
357 I915_WRITE(DSPFW3
, val
);
358 POSTING_READ(DSPFW3
);
359 } else if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
)) {
360 was_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
361 val
= enable
? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN
) :
362 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN
);
363 I915_WRITE(FW_BLC_SELF
, val
);
364 POSTING_READ(FW_BLC_SELF
);
365 } else if (IS_I915GM(dev_priv
)) {
367 * FIXME can't find a bit like this for 915G, and
368 * and yet it does have the related watermark in
369 * FW_BLC_SELF. What's going on?
371 was_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
372 val
= enable
? _MASKED_BIT_ENABLE(INSTPM_SELF_EN
) :
373 _MASKED_BIT_DISABLE(INSTPM_SELF_EN
);
374 I915_WRITE(INSTPM
, val
);
375 POSTING_READ(INSTPM
);
380 trace_intel_memory_cxsr(dev_priv
, was_enabled
, enable
);
382 DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
383 enableddisabled(enable
),
384 enableddisabled(was_enabled
));
390 * intel_set_memory_cxsr - Configure CxSR state
391 * @dev_priv: i915 device
392 * @enable: Allow vs. disallow CxSR
394 * Allow or disallow the system to enter a special CxSR
395 * (C-state self refresh) state. What typically happens in CxSR mode
396 * is that several display FIFOs may get combined into a single larger
397 * FIFO for a particular plane (so called max FIFO mode) to allow the
398 * system to defer memory fetches longer, and the memory will enter
401 * Note that enabling CxSR does not guarantee that the system enter
402 * this special mode, nor does it guarantee that the system stays
403 * in that mode once entered. So this just allows/disallows the system
404 * to autonomously utilize the CxSR mode. Other factors such as core
405 * C-states will affect when/if the system actually enters/exits the
408 * Note that on VLV/CHV this actually only controls the max FIFO mode,
409 * and the system is free to enter/exit memory self refresh at any time
410 * even when the use of CxSR has been disallowed.
412 * While the system is actually in the CxSR/max FIFO mode, some plane
413 * control registers will not get latched on vblank. Thus in order to
414 * guarantee the system will respond to changes in the plane registers
415 * we must always disallow CxSR prior to making changes to those registers.
416 * Unfortunately the system will re-evaluate the CxSR conditions at
417 * frame start which happens after vblank start (which is when the plane
418 * registers would get latched), so we can't proceed with the plane update
419 * during the same frame where we disallowed CxSR.
421 * Certain platforms also have a deeper HPLL SR mode. Fortunately the
422 * HPLL SR mode depends on CxSR itself, so we don't have to hand hold
423 * the hardware w.r.t. HPLL SR when writing to plane registers.
424 * Disallowing just CxSR is sufficient.
426 bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
430 mutex_lock(&dev_priv
->wm
.wm_mutex
);
431 ret
= _intel_set_memory_cxsr(dev_priv
, enable
);
432 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
433 dev_priv
->wm
.vlv
.cxsr
= enable
;
434 else if (IS_G4X(dev_priv
))
435 dev_priv
->wm
.g4x
.cxsr
= enable
;
436 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
442 * Latency for FIFO fetches is dependent on several factors:
443 * - memory configuration (speed, channels)
445 * - current MCH state
446 * It can be fairly high in some situations, so here we assume a fairly
447 * pessimal value. It's a tradeoff between extra memory fetches (if we
448 * set this value too high, the FIFO will fetch frequently to stay full)
449 * and power consumption (set it too low to save power and we might see
450 * FIFO underruns and display "flicker").
452 * A value of 5us seems to be a good balance; safe for very low end
453 * platforms but not overly aggressive on lower latency configs.
455 static const int pessimal_latency_ns
= 5000;
457 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
458 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
460 static void vlv_get_fifo_size(struct intel_crtc_state
*crtc_state
)
462 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
463 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
464 struct vlv_fifo_state
*fifo_state
= &crtc_state
->wm
.vlv
.fifo_state
;
465 enum pipe pipe
= crtc
->pipe
;
466 int sprite0_start
, sprite1_start
;
469 uint32_t dsparb
, dsparb2
, dsparb3
;
471 dsparb
= I915_READ(DSPARB
);
472 dsparb2
= I915_READ(DSPARB2
);
473 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 0, 0);
474 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 8, 4);
477 dsparb
= I915_READ(DSPARB
);
478 dsparb2
= I915_READ(DSPARB2
);
479 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 16, 8);
480 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 24, 12);
483 dsparb2
= I915_READ(DSPARB2
);
484 dsparb3
= I915_READ(DSPARB3
);
485 sprite0_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 0, 16);
486 sprite1_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 8, 20);
493 fifo_state
->plane
[PLANE_PRIMARY
] = sprite0_start
;
494 fifo_state
->plane
[PLANE_SPRITE0
] = sprite1_start
- sprite0_start
;
495 fifo_state
->plane
[PLANE_SPRITE1
] = 511 - sprite1_start
;
496 fifo_state
->plane
[PLANE_CURSOR
] = 63;
499 static int i9xx_get_fifo_size(struct drm_i915_private
*dev_priv
, int plane
)
501 uint32_t dsparb
= I915_READ(DSPARB
);
504 size
= dsparb
& 0x7f;
506 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
508 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
509 plane
? "B" : "A", size
);
514 static int i830_get_fifo_size(struct drm_i915_private
*dev_priv
, int plane
)
516 uint32_t dsparb
= I915_READ(DSPARB
);
519 size
= dsparb
& 0x1ff;
521 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
522 size
>>= 1; /* Convert to cachelines */
524 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
525 plane
? "B" : "A", size
);
530 static int i845_get_fifo_size(struct drm_i915_private
*dev_priv
, int plane
)
532 uint32_t dsparb
= I915_READ(DSPARB
);
535 size
= dsparb
& 0x7f;
536 size
>>= 2; /* Convert to cachelines */
538 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
545 /* Pineview has different values for various configs */
546 static const struct intel_watermark_params pineview_display_wm
= {
547 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
548 .max_wm
= PINEVIEW_MAX_WM
,
549 .default_wm
= PINEVIEW_DFT_WM
,
550 .guard_size
= PINEVIEW_GUARD_WM
,
551 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
553 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
554 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
555 .max_wm
= PINEVIEW_MAX_WM
,
556 .default_wm
= PINEVIEW_DFT_HPLLOFF_WM
,
557 .guard_size
= PINEVIEW_GUARD_WM
,
558 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
560 static const struct intel_watermark_params pineview_cursor_wm
= {
561 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
562 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
563 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
564 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
565 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
567 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
568 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
569 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
570 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
571 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
572 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
574 static const struct intel_watermark_params i965_cursor_wm_info
= {
575 .fifo_size
= I965_CURSOR_FIFO
,
576 .max_wm
= I965_CURSOR_MAX_WM
,
577 .default_wm
= I965_CURSOR_DFT_WM
,
579 .cacheline_size
= I915_FIFO_LINE_SIZE
,
581 static const struct intel_watermark_params i945_wm_info
= {
582 .fifo_size
= I945_FIFO_SIZE
,
583 .max_wm
= I915_MAX_WM
,
586 .cacheline_size
= I915_FIFO_LINE_SIZE
,
588 static const struct intel_watermark_params i915_wm_info
= {
589 .fifo_size
= I915_FIFO_SIZE
,
590 .max_wm
= I915_MAX_WM
,
593 .cacheline_size
= I915_FIFO_LINE_SIZE
,
595 static const struct intel_watermark_params i830_a_wm_info
= {
596 .fifo_size
= I855GM_FIFO_SIZE
,
597 .max_wm
= I915_MAX_WM
,
600 .cacheline_size
= I830_FIFO_LINE_SIZE
,
602 static const struct intel_watermark_params i830_bc_wm_info
= {
603 .fifo_size
= I855GM_FIFO_SIZE
,
604 .max_wm
= I915_MAX_WM
/2,
607 .cacheline_size
= I830_FIFO_LINE_SIZE
,
609 static const struct intel_watermark_params i845_wm_info
= {
610 .fifo_size
= I830_FIFO_SIZE
,
611 .max_wm
= I915_MAX_WM
,
614 .cacheline_size
= I830_FIFO_LINE_SIZE
,
618 * intel_wm_method1 - Method 1 / "small buffer" watermark formula
619 * @pixel_rate: Pipe pixel rate in kHz
620 * @cpp: Plane bytes per pixel
621 * @latency: Memory wakeup latency in 0.1us units
623 * Compute the watermark using the method 1 or "small buffer"
624 * formula. The caller may additonally add extra cachelines
625 * to account for TLB misses and clock crossings.
627 * This method is concerned with the short term drain rate
628 * of the FIFO, ie. it does not account for blanking periods
629 * which would effectively reduce the average drain rate across
630 * a longer period. The name "small" refers to the fact the
631 * FIFO is relatively small compared to the amount of data
634 * The FIFO level vs. time graph might look something like:
638 * __---__---__ (- plane active, _ blanking)
641 * or perhaps like this:
644 * __----__----__ (- plane active, _ blanking)
648 * The watermark in bytes
650 static unsigned int intel_wm_method1(unsigned int pixel_rate
,
652 unsigned int latency
)
656 ret
= (uint64_t) pixel_rate
* cpp
* latency
;
657 ret
= DIV_ROUND_UP_ULL(ret
, 10000);
663 * intel_wm_method2 - Method 2 / "large buffer" watermark formula
664 * @pixel_rate: Pipe pixel rate in kHz
665 * @htotal: Pipe horizontal total
666 * @width: Plane width in pixels
667 * @cpp: Plane bytes per pixel
668 * @latency: Memory wakeup latency in 0.1us units
670 * Compute the watermark using the method 2 or "large buffer"
671 * formula. The caller may additonally add extra cachelines
672 * to account for TLB misses and clock crossings.
674 * This method is concerned with the long term drain rate
675 * of the FIFO, ie. it does account for blanking periods
676 * which effectively reduce the average drain rate across
677 * a longer period. The name "large" refers to the fact the
678 * FIFO is relatively large compared to the amount of data
681 * The FIFO level vs. time graph might look something like:
686 * __ --__--__--__--__--__--__ (- plane active, _ blanking)
690 * The watermark in bytes
692 static unsigned int intel_wm_method2(unsigned int pixel_rate
,
696 unsigned int latency
)
701 * FIXME remove once all users are computing
702 * watermarks in the correct place.
704 if (WARN_ON_ONCE(htotal
== 0))
707 ret
= (latency
* pixel_rate
) / (htotal
* 10000);
708 ret
= (ret
+ 1) * width
* cpp
;
714 * intel_calculate_wm - calculate watermark level
715 * @pixel_rate: pixel clock
716 * @wm: chip FIFO params
717 * @cpp: bytes per pixel
718 * @latency_ns: memory latency for the platform
720 * Calculate the watermark level (the level at which the display plane will
721 * start fetching from memory again). Each chip has a different display
722 * FIFO size and allocation, so the caller needs to figure that out and pass
723 * in the correct intel_watermark_params structure.
725 * As the pixel clock runs, the FIFO will be drained at a rate that depends
726 * on the pixel size. When it reaches the watermark level, it'll start
727 * fetching FIFO line sized based chunks from memory until the FIFO fills
728 * past the watermark point. If the FIFO drains completely, a FIFO underrun
729 * will occur, and a display engine hang could result.
731 static unsigned int intel_calculate_wm(int pixel_rate
,
732 const struct intel_watermark_params
*wm
,
733 int fifo_size
, int cpp
,
734 unsigned int latency_ns
)
736 int entries
, wm_size
;
739 * Note: we need to make sure we don't overflow for various clock &
741 * clocks go from a few thousand to several hundred thousand.
742 * latency is usually a few thousand
744 entries
= intel_wm_method1(pixel_rate
, cpp
,
746 entries
= DIV_ROUND_UP(entries
, wm
->cacheline_size
) +
748 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries
);
750 wm_size
= fifo_size
- entries
;
751 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size
);
753 /* Don't promote wm_size to unsigned... */
754 if (wm_size
> wm
->max_wm
)
755 wm_size
= wm
->max_wm
;
757 wm_size
= wm
->default_wm
;
760 * Bspec seems to indicate that the value shouldn't be lower than
761 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
762 * Lets go for 8 which is the burst size since certain platforms
763 * already use a hardcoded 8 (which is what the spec says should be
772 static bool is_disabling(int old
, int new, int threshold
)
774 return old
>= threshold
&& new < threshold
;
777 static bool is_enabling(int old
, int new, int threshold
)
779 return old
< threshold
&& new >= threshold
;
782 static int intel_wm_num_levels(struct drm_i915_private
*dev_priv
)
784 return dev_priv
->wm
.max_level
+ 1;
787 static bool intel_wm_plane_visible(const struct intel_crtc_state
*crtc_state
,
788 const struct intel_plane_state
*plane_state
)
790 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
792 /* FIXME check the 'enable' instead */
793 if (!crtc_state
->base
.active
)
797 * Treat cursor with fb as always visible since cursor updates
798 * can happen faster than the vrefresh rate, and the current
799 * watermark code doesn't handle that correctly. Cursor updates
800 * which set/clear the fb or change the cursor size are going
801 * to get throttled by intel_legacy_cursor_update() to work
802 * around this problem with the watermark code.
804 if (plane
->id
== PLANE_CURSOR
)
805 return plane_state
->base
.fb
!= NULL
;
807 return plane_state
->base
.visible
;
810 static struct intel_crtc
*single_enabled_crtc(struct drm_i915_private
*dev_priv
)
812 struct intel_crtc
*crtc
, *enabled
= NULL
;
814 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
815 if (intel_crtc_active(crtc
)) {
825 static void pineview_update_wm(struct intel_crtc
*unused_crtc
)
827 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
828 struct intel_crtc
*crtc
;
829 const struct cxsr_latency
*latency
;
833 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv
),
838 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
839 intel_set_memory_cxsr(dev_priv
, false);
843 crtc
= single_enabled_crtc(dev_priv
);
845 const struct drm_display_mode
*adjusted_mode
=
846 &crtc
->config
->base
.adjusted_mode
;
847 const struct drm_framebuffer
*fb
=
848 crtc
->base
.primary
->state
->fb
;
849 int cpp
= fb
->format
->cpp
[0];
850 int clock
= adjusted_mode
->crtc_clock
;
853 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
854 pineview_display_wm
.fifo_size
,
855 cpp
, latency
->display_sr
);
856 reg
= I915_READ(DSPFW1
);
857 reg
&= ~DSPFW_SR_MASK
;
858 reg
|= FW_WM(wm
, SR
);
859 I915_WRITE(DSPFW1
, reg
);
860 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
863 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
864 pineview_display_wm
.fifo_size
,
865 4, latency
->cursor_sr
);
866 reg
= I915_READ(DSPFW3
);
867 reg
&= ~DSPFW_CURSOR_SR_MASK
;
868 reg
|= FW_WM(wm
, CURSOR_SR
);
869 I915_WRITE(DSPFW3
, reg
);
871 /* Display HPLL off SR */
872 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
873 pineview_display_hplloff_wm
.fifo_size
,
874 cpp
, latency
->display_hpll_disable
);
875 reg
= I915_READ(DSPFW3
);
876 reg
&= ~DSPFW_HPLL_SR_MASK
;
877 reg
|= FW_WM(wm
, HPLL_SR
);
878 I915_WRITE(DSPFW3
, reg
);
880 /* cursor HPLL off SR */
881 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
882 pineview_display_hplloff_wm
.fifo_size
,
883 4, latency
->cursor_hpll_disable
);
884 reg
= I915_READ(DSPFW3
);
885 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
886 reg
|= FW_WM(wm
, HPLL_CURSOR
);
887 I915_WRITE(DSPFW3
, reg
);
888 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
890 intel_set_memory_cxsr(dev_priv
, true);
892 intel_set_memory_cxsr(dev_priv
, false);
897 * Documentation says:
898 * "If the line size is small, the TLB fetches can get in the way of the
899 * data fetches, causing some lag in the pixel data return which is not
900 * accounted for in the above formulas. The following adjustment only
901 * needs to be applied if eight whole lines fit in the buffer at once.
902 * The WM is adjusted upwards by the difference between the FIFO size
903 * and the size of 8 whole lines. This adjustment is always performed
904 * in the actual pixel depth regardless of whether FBC is enabled or not."
906 static int g4x_tlb_miss_wa(int fifo_size
, int width
, int cpp
)
908 int tlb_miss
= fifo_size
* 64 - width
* cpp
* 8;
910 return max(0, tlb_miss
);
913 static void g4x_write_wm_values(struct drm_i915_private
*dev_priv
,
914 const struct g4x_wm_values
*wm
)
918 for_each_pipe(dev_priv
, pipe
)
919 trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv
, pipe
), wm
);
922 FW_WM(wm
->sr
.plane
, SR
) |
923 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_CURSOR
], CURSORB
) |
924 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
], PLANEB
) |
925 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
], PLANEA
));
927 (wm
->fbc_en
? DSPFW_FBC_SR_EN
: 0) |
928 FW_WM(wm
->sr
.fbc
, FBC_SR
) |
929 FW_WM(wm
->hpll
.fbc
, FBC_HPLL_SR
) |
930 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
], SPRITEB
) |
931 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_CURSOR
], CURSORA
) |
932 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
], SPRITEA
));
934 (wm
->hpll_en
? DSPFW_HPLL_SR_EN
: 0) |
935 FW_WM(wm
->sr
.cursor
, CURSOR_SR
) |
936 FW_WM(wm
->hpll
.cursor
, HPLL_CURSOR
) |
937 FW_WM(wm
->hpll
.plane
, HPLL_SR
));
939 POSTING_READ(DSPFW1
);
942 #define FW_WM_VLV(value, plane) \
943 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
945 static void vlv_write_wm_values(struct drm_i915_private
*dev_priv
,
946 const struct vlv_wm_values
*wm
)
950 for_each_pipe(dev_priv
, pipe
) {
951 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv
, pipe
), wm
);
953 I915_WRITE(VLV_DDL(pipe
),
954 (wm
->ddl
[pipe
].plane
[PLANE_CURSOR
] << DDL_CURSOR_SHIFT
) |
955 (wm
->ddl
[pipe
].plane
[PLANE_SPRITE1
] << DDL_SPRITE_SHIFT(1)) |
956 (wm
->ddl
[pipe
].plane
[PLANE_SPRITE0
] << DDL_SPRITE_SHIFT(0)) |
957 (wm
->ddl
[pipe
].plane
[PLANE_PRIMARY
] << DDL_PLANE_SHIFT
));
961 * Zero the (unused) WM1 watermarks, and also clear all the
962 * high order bits so that there are no out of bounds values
963 * present in the registers during the reprogramming.
965 I915_WRITE(DSPHOWM
, 0);
966 I915_WRITE(DSPHOWM1
, 0);
967 I915_WRITE(DSPFW4
, 0);
968 I915_WRITE(DSPFW5
, 0);
969 I915_WRITE(DSPFW6
, 0);
972 FW_WM(wm
->sr
.plane
, SR
) |
973 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_CURSOR
], CURSORB
) |
974 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
], PLANEB
) |
975 FW_WM_VLV(wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
], PLANEA
));
977 FW_WM_VLV(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
], SPRITEB
) |
978 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_CURSOR
], CURSORA
) |
979 FW_WM_VLV(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
], SPRITEA
));
981 FW_WM(wm
->sr
.cursor
, CURSOR_SR
));
983 if (IS_CHERRYVIEW(dev_priv
)) {
984 I915_WRITE(DSPFW7_CHV
,
985 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
], SPRITED
) |
986 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
], SPRITEC
));
987 I915_WRITE(DSPFW8_CHV
,
988 FW_WM_VLV(wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE1
], SPRITEF
) |
989 FW_WM_VLV(wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE0
], SPRITEE
));
990 I915_WRITE(DSPFW9_CHV
,
991 FW_WM_VLV(wm
->pipe
[PIPE_C
].plane
[PLANE_PRIMARY
], PLANEC
) |
992 FW_WM(wm
->pipe
[PIPE_C
].plane
[PLANE_CURSOR
], CURSORC
));
994 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
995 FW_WM(wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE1
] >> 8, SPRITEF_HI
) |
996 FW_WM(wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE0
] >> 8, SPRITEE_HI
) |
997 FW_WM(wm
->pipe
[PIPE_C
].plane
[PLANE_PRIMARY
] >> 8, PLANEC_HI
) |
998 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] >> 8, SPRITED_HI
) |
999 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] >> 8, SPRITEC_HI
) |
1000 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] >> 8, PLANEB_HI
) |
1001 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] >> 8, SPRITEB_HI
) |
1002 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] >> 8, SPRITEA_HI
) |
1003 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] >> 8, PLANEA_HI
));
1006 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
], SPRITED
) |
1007 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
], SPRITEC
));
1009 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
1010 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] >> 8, SPRITED_HI
) |
1011 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] >> 8, SPRITEC_HI
) |
1012 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] >> 8, PLANEB_HI
) |
1013 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] >> 8, SPRITEB_HI
) |
1014 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] >> 8, SPRITEA_HI
) |
1015 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] >> 8, PLANEA_HI
));
1018 POSTING_READ(DSPFW1
);
1023 static void g4x_setup_wm_latency(struct drm_i915_private
*dev_priv
)
1025 /* all latencies in usec */
1026 dev_priv
->wm
.pri_latency
[G4X_WM_LEVEL_NORMAL
] = 5;
1027 dev_priv
->wm
.pri_latency
[G4X_WM_LEVEL_SR
] = 12;
1028 dev_priv
->wm
.pri_latency
[G4X_WM_LEVEL_HPLL
] = 35;
1030 dev_priv
->wm
.max_level
= G4X_WM_LEVEL_HPLL
;
1033 static int g4x_plane_fifo_size(enum plane_id plane_id
, int level
)
1036 * DSPCNTR[13] supposedly controls whether the
1037 * primary plane can use the FIFO space otherwise
1038 * reserved for the sprite plane. It's not 100% clear
1039 * what the actual FIFO size is, but it looks like we
1040 * can happily set both primary and sprite watermarks
1041 * up to 127 cachelines. So that would seem to mean
1042 * that either DSPCNTR[13] doesn't do anything, or that
1043 * the total FIFO is >= 256 cachelines in size. Either
1044 * way, we don't seem to have to worry about this
1045 * repartitioning as the maximum watermark value the
1046 * register can hold for each plane is lower than the
1047 * minimum FIFO size.
1053 return level
== G4X_WM_LEVEL_NORMAL
? 127 : 511;
1055 return level
== G4X_WM_LEVEL_NORMAL
? 127 : 0;
1057 MISSING_CASE(plane_id
);
1062 static int g4x_fbc_fifo_size(int level
)
1065 case G4X_WM_LEVEL_SR
:
1067 case G4X_WM_LEVEL_HPLL
:
1070 MISSING_CASE(level
);
1075 static uint16_t g4x_compute_wm(const struct intel_crtc_state
*crtc_state
,
1076 const struct intel_plane_state
*plane_state
,
1079 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
1080 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
1081 const struct drm_display_mode
*adjusted_mode
=
1082 &crtc_state
->base
.adjusted_mode
;
1083 int clock
, htotal
, cpp
, width
, wm
;
1084 int latency
= dev_priv
->wm
.pri_latency
[level
] * 10;
1089 if (!intel_wm_plane_visible(crtc_state
, plane_state
))
1093 * Not 100% sure which way ELK should go here as the
1094 * spec only says CL/CTG should assume 32bpp and BW
1095 * doesn't need to. But as these things followed the
1096 * mobile vs. desktop lines on gen3 as well, let's
1097 * assume ELK doesn't need this.
1099 * The spec also fails to list such a restriction for
1100 * the HPLL watermark, which seems a little strange.
1101 * Let's use 32bpp for the HPLL watermark as well.
1103 if (IS_GM45(dev_priv
) && plane
->id
== PLANE_PRIMARY
&&
1104 level
!= G4X_WM_LEVEL_NORMAL
)
1107 cpp
= plane_state
->base
.fb
->format
->cpp
[0];
1109 clock
= adjusted_mode
->crtc_clock
;
1110 htotal
= adjusted_mode
->crtc_htotal
;
1112 if (plane
->id
== PLANE_CURSOR
)
1113 width
= plane_state
->base
.crtc_w
;
1115 width
= drm_rect_width(&plane_state
->base
.dst
);
1117 if (plane
->id
== PLANE_CURSOR
) {
1118 wm
= intel_wm_method2(clock
, htotal
, width
, cpp
, latency
);
1119 } else if (plane
->id
== PLANE_PRIMARY
&&
1120 level
== G4X_WM_LEVEL_NORMAL
) {
1121 wm
= intel_wm_method1(clock
, cpp
, latency
);
1125 small
= intel_wm_method1(clock
, cpp
, latency
);
1126 large
= intel_wm_method2(clock
, htotal
, width
, cpp
, latency
);
1128 wm
= min(small
, large
);
1131 wm
+= g4x_tlb_miss_wa(g4x_plane_fifo_size(plane
->id
, level
),
1134 wm
= DIV_ROUND_UP(wm
, 64) + 2;
1136 return min_t(int, wm
, USHRT_MAX
);
1139 static bool g4x_raw_plane_wm_set(struct intel_crtc_state
*crtc_state
,
1140 int level
, enum plane_id plane_id
, u16 value
)
1142 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1145 for (; level
< intel_wm_num_levels(dev_priv
); level
++) {
1146 struct g4x_pipe_wm
*raw
= &crtc_state
->wm
.g4x
.raw
[level
];
1148 dirty
|= raw
->plane
[plane_id
] != value
;
1149 raw
->plane
[plane_id
] = value
;
1155 static bool g4x_raw_fbc_wm_set(struct intel_crtc_state
*crtc_state
,
1156 int level
, u16 value
)
1158 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1161 /* NORMAL level doesn't have an FBC watermark */
1162 level
= max(level
, G4X_WM_LEVEL_SR
);
1164 for (; level
< intel_wm_num_levels(dev_priv
); level
++) {
1165 struct g4x_pipe_wm
*raw
= &crtc_state
->wm
.g4x
.raw
[level
];
1167 dirty
|= raw
->fbc
!= value
;
1174 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state
*cstate
,
1175 const struct intel_plane_state
*pstate
,
1178 static bool g4x_raw_plane_wm_compute(struct intel_crtc_state
*crtc_state
,
1179 const struct intel_plane_state
*plane_state
)
1181 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
1182 int num_levels
= intel_wm_num_levels(to_i915(plane
->base
.dev
));
1183 enum plane_id plane_id
= plane
->id
;
1187 if (!intel_wm_plane_visible(crtc_state
, plane_state
)) {
1188 dirty
|= g4x_raw_plane_wm_set(crtc_state
, 0, plane_id
, 0);
1189 if (plane_id
== PLANE_PRIMARY
)
1190 dirty
|= g4x_raw_fbc_wm_set(crtc_state
, 0, 0);
1194 for (level
= 0; level
< num_levels
; level
++) {
1195 struct g4x_pipe_wm
*raw
= &crtc_state
->wm
.g4x
.raw
[level
];
1198 wm
= g4x_compute_wm(crtc_state
, plane_state
, level
);
1199 max_wm
= g4x_plane_fifo_size(plane_id
, level
);
1204 dirty
|= raw
->plane
[plane_id
] != wm
;
1205 raw
->plane
[plane_id
] = wm
;
1207 if (plane_id
!= PLANE_PRIMARY
||
1208 level
== G4X_WM_LEVEL_NORMAL
)
1211 wm
= ilk_compute_fbc_wm(crtc_state
, plane_state
,
1212 raw
->plane
[plane_id
]);
1213 max_wm
= g4x_fbc_fifo_size(level
);
1216 * FBC wm is not mandatory as we
1217 * can always just disable its use.
1222 dirty
|= raw
->fbc
!= wm
;
1226 /* mark watermarks as invalid */
1227 dirty
|= g4x_raw_plane_wm_set(crtc_state
, level
, plane_id
, USHRT_MAX
);
1229 if (plane_id
== PLANE_PRIMARY
)
1230 dirty
|= g4x_raw_fbc_wm_set(crtc_state
, level
, USHRT_MAX
);
1234 DRM_DEBUG_KMS("%s watermarks: normal=%d, SR=%d, HPLL=%d\n",
1236 crtc_state
->wm
.g4x
.raw
[G4X_WM_LEVEL_NORMAL
].plane
[plane_id
],
1237 crtc_state
->wm
.g4x
.raw
[G4X_WM_LEVEL_SR
].plane
[plane_id
],
1238 crtc_state
->wm
.g4x
.raw
[G4X_WM_LEVEL_HPLL
].plane
[plane_id
]);
1240 if (plane_id
== PLANE_PRIMARY
)
1241 DRM_DEBUG_KMS("FBC watermarks: SR=%d, HPLL=%d\n",
1242 crtc_state
->wm
.g4x
.raw
[G4X_WM_LEVEL_SR
].fbc
,
1243 crtc_state
->wm
.g4x
.raw
[G4X_WM_LEVEL_HPLL
].fbc
);
1249 static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state
*crtc_state
,
1250 enum plane_id plane_id
, int level
)
1252 const struct g4x_pipe_wm
*raw
= &crtc_state
->wm
.g4x
.raw
[level
];
1254 return raw
->plane
[plane_id
] <= g4x_plane_fifo_size(plane_id
, level
);
1257 static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state
*crtc_state
,
1260 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1262 if (level
> dev_priv
->wm
.max_level
)
1265 return g4x_raw_plane_wm_is_valid(crtc_state
, PLANE_PRIMARY
, level
) &&
1266 g4x_raw_plane_wm_is_valid(crtc_state
, PLANE_SPRITE0
, level
) &&
1267 g4x_raw_plane_wm_is_valid(crtc_state
, PLANE_CURSOR
, level
);
1270 /* mark all levels starting from 'level' as invalid */
1271 static void g4x_invalidate_wms(struct intel_crtc
*crtc
,
1272 struct g4x_wm_state
*wm_state
, int level
)
1274 if (level
<= G4X_WM_LEVEL_NORMAL
) {
1275 enum plane_id plane_id
;
1277 for_each_plane_id_on_crtc(crtc
, plane_id
)
1278 wm_state
->wm
.plane
[plane_id
] = USHRT_MAX
;
1281 if (level
<= G4X_WM_LEVEL_SR
) {
1282 wm_state
->cxsr
= false;
1283 wm_state
->sr
.cursor
= USHRT_MAX
;
1284 wm_state
->sr
.plane
= USHRT_MAX
;
1285 wm_state
->sr
.fbc
= USHRT_MAX
;
1288 if (level
<= G4X_WM_LEVEL_HPLL
) {
1289 wm_state
->hpll_en
= false;
1290 wm_state
->hpll
.cursor
= USHRT_MAX
;
1291 wm_state
->hpll
.plane
= USHRT_MAX
;
1292 wm_state
->hpll
.fbc
= USHRT_MAX
;
1296 static int g4x_compute_pipe_wm(struct intel_crtc_state
*crtc_state
)
1298 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1299 struct intel_atomic_state
*state
=
1300 to_intel_atomic_state(crtc_state
->base
.state
);
1301 struct g4x_wm_state
*wm_state
= &crtc_state
->wm
.g4x
.optimal
;
1302 int num_active_planes
= hweight32(crtc_state
->active_planes
&
1303 ~BIT(PLANE_CURSOR
));
1304 const struct g4x_pipe_wm
*raw
;
1305 struct intel_plane_state
*plane_state
;
1306 struct intel_plane
*plane
;
1307 enum plane_id plane_id
;
1309 unsigned int dirty
= 0;
1311 for_each_intel_plane_in_state(state
, plane
, plane_state
, i
) {
1312 const struct intel_plane_state
*old_plane_state
=
1313 to_intel_plane_state(plane
->base
.state
);
1315 if (plane_state
->base
.crtc
!= &crtc
->base
&&
1316 old_plane_state
->base
.crtc
!= &crtc
->base
)
1319 if (g4x_raw_plane_wm_compute(crtc_state
, plane_state
))
1320 dirty
|= BIT(plane
->id
);
1326 level
= G4X_WM_LEVEL_NORMAL
;
1327 if (!g4x_raw_crtc_wm_is_valid(crtc_state
, level
))
1330 raw
= &crtc_state
->wm
.g4x
.raw
[level
];
1331 for_each_plane_id_on_crtc(crtc
, plane_id
)
1332 wm_state
->wm
.plane
[plane_id
] = raw
->plane
[plane_id
];
1334 level
= G4X_WM_LEVEL_SR
;
1336 if (!g4x_raw_crtc_wm_is_valid(crtc_state
, level
))
1339 raw
= &crtc_state
->wm
.g4x
.raw
[level
];
1340 wm_state
->sr
.plane
= raw
->plane
[PLANE_PRIMARY
];
1341 wm_state
->sr
.cursor
= raw
->plane
[PLANE_CURSOR
];
1342 wm_state
->sr
.fbc
= raw
->fbc
;
1344 wm_state
->cxsr
= num_active_planes
== BIT(PLANE_PRIMARY
);
1346 level
= G4X_WM_LEVEL_HPLL
;
1348 if (!g4x_raw_crtc_wm_is_valid(crtc_state
, level
))
1351 raw
= &crtc_state
->wm
.g4x
.raw
[level
];
1352 wm_state
->hpll
.plane
= raw
->plane
[PLANE_PRIMARY
];
1353 wm_state
->hpll
.cursor
= raw
->plane
[PLANE_CURSOR
];
1354 wm_state
->hpll
.fbc
= raw
->fbc
;
1356 wm_state
->hpll_en
= wm_state
->cxsr
;
1361 if (level
== G4X_WM_LEVEL_NORMAL
)
1364 /* invalidate the higher levels */
1365 g4x_invalidate_wms(crtc
, wm_state
, level
);
1368 * Determine if the FBC watermark(s) can be used. IF
1369 * this isn't the case we prefer to disable the FBC
1370 ( watermark(s) rather than disable the SR/HPLL
1371 * level(s) entirely.
1373 wm_state
->fbc_en
= level
> G4X_WM_LEVEL_NORMAL
;
1375 if (level
>= G4X_WM_LEVEL_SR
&&
1376 wm_state
->sr
.fbc
> g4x_fbc_fifo_size(G4X_WM_LEVEL_SR
))
1377 wm_state
->fbc_en
= false;
1378 else if (level
>= G4X_WM_LEVEL_HPLL
&&
1379 wm_state
->hpll
.fbc
> g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL
))
1380 wm_state
->fbc_en
= false;
1385 static int g4x_compute_intermediate_wm(struct drm_device
*dev
,
1386 struct intel_crtc
*crtc
,
1387 struct intel_crtc_state
*crtc_state
)
1389 struct g4x_wm_state
*intermediate
= &crtc_state
->wm
.g4x
.intermediate
;
1390 const struct g4x_wm_state
*optimal
= &crtc_state
->wm
.g4x
.optimal
;
1391 const struct g4x_wm_state
*active
= &crtc
->wm
.active
.g4x
;
1392 enum plane_id plane_id
;
1394 intermediate
->cxsr
= optimal
->cxsr
&& active
->cxsr
&&
1395 !crtc_state
->disable_cxsr
;
1396 intermediate
->hpll_en
= optimal
->hpll_en
&& active
->hpll_en
&&
1397 !crtc_state
->disable_cxsr
;
1398 intermediate
->fbc_en
= optimal
->fbc_en
&& active
->fbc_en
;
1400 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1401 intermediate
->wm
.plane
[plane_id
] =
1402 max(optimal
->wm
.plane
[plane_id
],
1403 active
->wm
.plane
[plane_id
]);
1405 WARN_ON(intermediate
->wm
.plane
[plane_id
] >
1406 g4x_plane_fifo_size(plane_id
, G4X_WM_LEVEL_NORMAL
));
1409 intermediate
->sr
.plane
= max(optimal
->sr
.plane
,
1411 intermediate
->sr
.cursor
= max(optimal
->sr
.cursor
,
1413 intermediate
->sr
.fbc
= max(optimal
->sr
.fbc
,
1416 intermediate
->hpll
.plane
= max(optimal
->hpll
.plane
,
1417 active
->hpll
.plane
);
1418 intermediate
->hpll
.cursor
= max(optimal
->hpll
.cursor
,
1419 active
->hpll
.cursor
);
1420 intermediate
->hpll
.fbc
= max(optimal
->hpll
.fbc
,
1423 WARN_ON((intermediate
->sr
.plane
>
1424 g4x_plane_fifo_size(PLANE_PRIMARY
, G4X_WM_LEVEL_SR
) ||
1425 intermediate
->sr
.cursor
>
1426 g4x_plane_fifo_size(PLANE_CURSOR
, G4X_WM_LEVEL_SR
)) &&
1427 intermediate
->cxsr
);
1428 WARN_ON((intermediate
->sr
.plane
>
1429 g4x_plane_fifo_size(PLANE_PRIMARY
, G4X_WM_LEVEL_HPLL
) ||
1430 intermediate
->sr
.cursor
>
1431 g4x_plane_fifo_size(PLANE_CURSOR
, G4X_WM_LEVEL_HPLL
)) &&
1432 intermediate
->hpll_en
);
1434 WARN_ON(intermediate
->sr
.fbc
> g4x_fbc_fifo_size(1) &&
1435 intermediate
->fbc_en
&& intermediate
->cxsr
);
1436 WARN_ON(intermediate
->hpll
.fbc
> g4x_fbc_fifo_size(2) &&
1437 intermediate
->fbc_en
&& intermediate
->hpll_en
);
1440 * If our intermediate WM are identical to the final WM, then we can
1441 * omit the post-vblank programming; only update if it's different.
1443 if (memcmp(intermediate
, optimal
, sizeof(*intermediate
)) != 0)
1444 crtc_state
->wm
.need_postvbl_update
= true;
1449 static void g4x_merge_wm(struct drm_i915_private
*dev_priv
,
1450 struct g4x_wm_values
*wm
)
1452 struct intel_crtc
*crtc
;
1453 int num_active_crtcs
= 0;
1459 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
1460 const struct g4x_wm_state
*wm_state
= &crtc
->wm
.active
.g4x
;
1465 if (!wm_state
->cxsr
)
1467 if (!wm_state
->hpll_en
)
1468 wm
->hpll_en
= false;
1469 if (!wm_state
->fbc_en
)
1475 if (num_active_crtcs
!= 1) {
1477 wm
->hpll_en
= false;
1481 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
1482 const struct g4x_wm_state
*wm_state
= &crtc
->wm
.active
.g4x
;
1483 enum pipe pipe
= crtc
->pipe
;
1485 wm
->pipe
[pipe
] = wm_state
->wm
;
1486 if (crtc
->active
&& wm
->cxsr
)
1487 wm
->sr
= wm_state
->sr
;
1488 if (crtc
->active
&& wm
->hpll_en
)
1489 wm
->hpll
= wm_state
->hpll
;
1493 static void g4x_program_watermarks(struct drm_i915_private
*dev_priv
)
1495 struct g4x_wm_values
*old_wm
= &dev_priv
->wm
.g4x
;
1496 struct g4x_wm_values new_wm
= {};
1498 g4x_merge_wm(dev_priv
, &new_wm
);
1500 if (memcmp(old_wm
, &new_wm
, sizeof(new_wm
)) == 0)
1503 if (is_disabling(old_wm
->cxsr
, new_wm
.cxsr
, true))
1504 _intel_set_memory_cxsr(dev_priv
, false);
1506 g4x_write_wm_values(dev_priv
, &new_wm
);
1508 if (is_enabling(old_wm
->cxsr
, new_wm
.cxsr
, true))
1509 _intel_set_memory_cxsr(dev_priv
, true);
1514 static void g4x_initial_watermarks(struct intel_atomic_state
*state
,
1515 struct intel_crtc_state
*crtc_state
)
1517 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1518 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1520 mutex_lock(&dev_priv
->wm
.wm_mutex
);
1521 crtc
->wm
.active
.g4x
= crtc_state
->wm
.g4x
.intermediate
;
1522 g4x_program_watermarks(dev_priv
);
1523 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
1526 static void g4x_optimize_watermarks(struct intel_atomic_state
*state
,
1527 struct intel_crtc_state
*crtc_state
)
1529 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1530 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1532 if (!crtc_state
->wm
.need_postvbl_update
)
1535 mutex_lock(&dev_priv
->wm
.wm_mutex
);
1536 intel_crtc
->wm
.active
.g4x
= crtc_state
->wm
.g4x
.optimal
;
1537 g4x_program_watermarks(dev_priv
);
1538 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
1541 /* latency must be in 0.1us units. */
1542 static unsigned int vlv_wm_method2(unsigned int pixel_rate
,
1543 unsigned int htotal
,
1546 unsigned int latency
)
1550 ret
= intel_wm_method2(pixel_rate
, htotal
,
1551 width
, cpp
, latency
);
1552 ret
= DIV_ROUND_UP(ret
, 64);
1557 static void vlv_setup_wm_latency(struct drm_i915_private
*dev_priv
)
1559 /* all latencies in usec */
1560 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM2
] = 3;
1562 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM2
;
1564 if (IS_CHERRYVIEW(dev_priv
)) {
1565 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM5
] = 12;
1566 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_DDR_DVFS
] = 33;
1568 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_DDR_DVFS
;
1572 static uint16_t vlv_compute_wm_level(const struct intel_crtc_state
*crtc_state
,
1573 const struct intel_plane_state
*plane_state
,
1576 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
1577 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
1578 const struct drm_display_mode
*adjusted_mode
=
1579 &crtc_state
->base
.adjusted_mode
;
1580 int clock
, htotal
, cpp
, width
, wm
;
1582 if (dev_priv
->wm
.pri_latency
[level
] == 0)
1585 if (!intel_wm_plane_visible(crtc_state
, plane_state
))
1588 cpp
= plane_state
->base
.fb
->format
->cpp
[0];
1589 clock
= adjusted_mode
->crtc_clock
;
1590 htotal
= adjusted_mode
->crtc_htotal
;
1591 width
= crtc_state
->pipe_src_w
;
1593 if (plane
->id
== PLANE_CURSOR
) {
1595 * FIXME the formula gives values that are
1596 * too big for the cursor FIFO, and hence we
1597 * would never be able to use cursors. For
1598 * now just hardcode the watermark.
1602 wm
= vlv_wm_method2(clock
, htotal
, width
, cpp
,
1603 dev_priv
->wm
.pri_latency
[level
] * 10);
1606 return min_t(int, wm
, USHRT_MAX
);
1609 static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes
)
1611 return (active_planes
& (BIT(PLANE_SPRITE0
) |
1612 BIT(PLANE_SPRITE1
))) == BIT(PLANE_SPRITE1
);
1615 static int vlv_compute_fifo(struct intel_crtc_state
*crtc_state
)
1617 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1618 const struct g4x_pipe_wm
*raw
=
1619 &crtc_state
->wm
.vlv
.raw
[VLV_WM_LEVEL_PM2
];
1620 struct vlv_fifo_state
*fifo_state
= &crtc_state
->wm
.vlv
.fifo_state
;
1621 unsigned int active_planes
= crtc_state
->active_planes
& ~BIT(PLANE_CURSOR
);
1622 int num_active_planes
= hweight32(active_planes
);
1623 const int fifo_size
= 511;
1624 int fifo_extra
, fifo_left
= fifo_size
;
1625 int sprite0_fifo_extra
= 0;
1626 unsigned int total_rate
;
1627 enum plane_id plane_id
;
1630 * When enabling sprite0 after sprite1 has already been enabled
1631 * we tend to get an underrun unless sprite0 already has some
1632 * FIFO space allcoated. Hence we always allocate at least one
1633 * cacheline for sprite0 whenever sprite1 is enabled.
1635 * All other plane enable sequences appear immune to this problem.
1637 if (vlv_need_sprite0_fifo_workaround(active_planes
))
1638 sprite0_fifo_extra
= 1;
1640 total_rate
= raw
->plane
[PLANE_PRIMARY
] +
1641 raw
->plane
[PLANE_SPRITE0
] +
1642 raw
->plane
[PLANE_SPRITE1
] +
1645 if (total_rate
> fifo_size
)
1648 if (total_rate
== 0)
1651 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1654 if ((active_planes
& BIT(plane_id
)) == 0) {
1655 fifo_state
->plane
[plane_id
] = 0;
1659 rate
= raw
->plane
[plane_id
];
1660 fifo_state
->plane
[plane_id
] = fifo_size
* rate
/ total_rate
;
1661 fifo_left
-= fifo_state
->plane
[plane_id
];
1664 fifo_state
->plane
[PLANE_SPRITE0
] += sprite0_fifo_extra
;
1665 fifo_left
-= sprite0_fifo_extra
;
1667 fifo_state
->plane
[PLANE_CURSOR
] = 63;
1669 fifo_extra
= DIV_ROUND_UP(fifo_left
, num_active_planes
?: 1);
1671 /* spread the remainder evenly */
1672 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1678 if ((active_planes
& BIT(plane_id
)) == 0)
1681 plane_extra
= min(fifo_extra
, fifo_left
);
1682 fifo_state
->plane
[plane_id
] += plane_extra
;
1683 fifo_left
-= plane_extra
;
1686 WARN_ON(active_planes
!= 0 && fifo_left
!= 0);
1688 /* give it all to the first plane if none are active */
1689 if (active_planes
== 0) {
1690 WARN_ON(fifo_left
!= fifo_size
);
1691 fifo_state
->plane
[PLANE_PRIMARY
] = fifo_left
;
1697 /* mark all levels starting from 'level' as invalid */
1698 static void vlv_invalidate_wms(struct intel_crtc
*crtc
,
1699 struct vlv_wm_state
*wm_state
, int level
)
1701 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1703 for (; level
< intel_wm_num_levels(dev_priv
); level
++) {
1704 enum plane_id plane_id
;
1706 for_each_plane_id_on_crtc(crtc
, plane_id
)
1707 wm_state
->wm
[level
].plane
[plane_id
] = USHRT_MAX
;
1709 wm_state
->sr
[level
].cursor
= USHRT_MAX
;
1710 wm_state
->sr
[level
].plane
= USHRT_MAX
;
1714 static u16
vlv_invert_wm_value(u16 wm
, u16 fifo_size
)
1719 return fifo_size
- wm
;
1723 * Starting from 'level' set all higher
1724 * levels to 'value' in the "raw" watermarks.
1726 static bool vlv_raw_plane_wm_set(struct intel_crtc_state
*crtc_state
,
1727 int level
, enum plane_id plane_id
, u16 value
)
1729 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1730 int num_levels
= intel_wm_num_levels(dev_priv
);
1733 for (; level
< num_levels
; level
++) {
1734 struct g4x_pipe_wm
*raw
= &crtc_state
->wm
.vlv
.raw
[level
];
1736 dirty
|= raw
->plane
[plane_id
] != value
;
1737 raw
->plane
[plane_id
] = value
;
1743 static bool vlv_raw_plane_wm_compute(struct intel_crtc_state
*crtc_state
,
1744 const struct intel_plane_state
*plane_state
)
1746 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
1747 enum plane_id plane_id
= plane
->id
;
1748 int num_levels
= intel_wm_num_levels(to_i915(plane
->base
.dev
));
1752 if (!intel_wm_plane_visible(crtc_state
, plane_state
)) {
1753 dirty
|= vlv_raw_plane_wm_set(crtc_state
, 0, plane_id
, 0);
1757 for (level
= 0; level
< num_levels
; level
++) {
1758 struct g4x_pipe_wm
*raw
= &crtc_state
->wm
.vlv
.raw
[level
];
1759 int wm
= vlv_compute_wm_level(crtc_state
, plane_state
, level
);
1760 int max_wm
= plane_id
== PLANE_CURSOR
? 63 : 511;
1765 dirty
|= raw
->plane
[plane_id
] != wm
;
1766 raw
->plane
[plane_id
] = wm
;
1769 /* mark all higher levels as invalid */
1770 dirty
|= vlv_raw_plane_wm_set(crtc_state
, level
, plane_id
, USHRT_MAX
);
1774 DRM_DEBUG_KMS("%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n",
1776 crtc_state
->wm
.vlv
.raw
[VLV_WM_LEVEL_PM2
].plane
[plane_id
],
1777 crtc_state
->wm
.vlv
.raw
[VLV_WM_LEVEL_PM5
].plane
[plane_id
],
1778 crtc_state
->wm
.vlv
.raw
[VLV_WM_LEVEL_DDR_DVFS
].plane
[plane_id
]);
1783 static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state
*crtc_state
,
1784 enum plane_id plane_id
, int level
)
1786 const struct g4x_pipe_wm
*raw
=
1787 &crtc_state
->wm
.vlv
.raw
[level
];
1788 const struct vlv_fifo_state
*fifo_state
=
1789 &crtc_state
->wm
.vlv
.fifo_state
;
1791 return raw
->plane
[plane_id
] <= fifo_state
->plane
[plane_id
];
1794 static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state
*crtc_state
, int level
)
1796 return vlv_raw_plane_wm_is_valid(crtc_state
, PLANE_PRIMARY
, level
) &&
1797 vlv_raw_plane_wm_is_valid(crtc_state
, PLANE_SPRITE0
, level
) &&
1798 vlv_raw_plane_wm_is_valid(crtc_state
, PLANE_SPRITE1
, level
) &&
1799 vlv_raw_plane_wm_is_valid(crtc_state
, PLANE_CURSOR
, level
);
1802 static int vlv_compute_pipe_wm(struct intel_crtc_state
*crtc_state
)
1804 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1805 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1806 struct intel_atomic_state
*state
=
1807 to_intel_atomic_state(crtc_state
->base
.state
);
1808 struct vlv_wm_state
*wm_state
= &crtc_state
->wm
.vlv
.optimal
;
1809 const struct vlv_fifo_state
*fifo_state
=
1810 &crtc_state
->wm
.vlv
.fifo_state
;
1811 int num_active_planes
= hweight32(crtc_state
->active_planes
&
1812 ~BIT(PLANE_CURSOR
));
1813 bool needs_modeset
= drm_atomic_crtc_needs_modeset(&crtc_state
->base
);
1814 struct intel_plane_state
*plane_state
;
1815 struct intel_plane
*plane
;
1816 enum plane_id plane_id
;
1818 unsigned int dirty
= 0;
1820 for_each_intel_plane_in_state(state
, plane
, plane_state
, i
) {
1821 const struct intel_plane_state
*old_plane_state
=
1822 to_intel_plane_state(plane
->base
.state
);
1824 if (plane_state
->base
.crtc
!= &crtc
->base
&&
1825 old_plane_state
->base
.crtc
!= &crtc
->base
)
1828 if (vlv_raw_plane_wm_compute(crtc_state
, plane_state
))
1829 dirty
|= BIT(plane
->id
);
1833 * DSPARB registers may have been reset due to the
1834 * power well being turned off. Make sure we restore
1835 * them to a consistent state even if no primary/sprite
1836 * planes are initially active.
1839 crtc_state
->fifo_changed
= true;
1844 /* cursor changes don't warrant a FIFO recompute */
1845 if (dirty
& ~BIT(PLANE_CURSOR
)) {
1846 const struct intel_crtc_state
*old_crtc_state
=
1847 to_intel_crtc_state(crtc
->base
.state
);
1848 const struct vlv_fifo_state
*old_fifo_state
=
1849 &old_crtc_state
->wm
.vlv
.fifo_state
;
1851 ret
= vlv_compute_fifo(crtc_state
);
1855 if (needs_modeset
||
1856 memcmp(old_fifo_state
, fifo_state
,
1857 sizeof(*fifo_state
)) != 0)
1858 crtc_state
->fifo_changed
= true;
1861 /* initially allow all levels */
1862 wm_state
->num_levels
= intel_wm_num_levels(dev_priv
);
1864 * Note that enabling cxsr with no primary/sprite planes
1865 * enabled can wedge the pipe. Hence we only allow cxsr
1866 * with exactly one enabled primary/sprite plane.
1868 wm_state
->cxsr
= crtc
->pipe
!= PIPE_C
&& num_active_planes
== 1;
1870 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1871 const struct g4x_pipe_wm
*raw
= &crtc_state
->wm
.vlv
.raw
[level
];
1872 const int sr_fifo_size
= INTEL_INFO(dev_priv
)->num_pipes
* 512 - 1;
1874 if (!vlv_raw_crtc_wm_is_valid(crtc_state
, level
))
1877 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1878 wm_state
->wm
[level
].plane
[plane_id
] =
1879 vlv_invert_wm_value(raw
->plane
[plane_id
],
1880 fifo_state
->plane
[plane_id
]);
1883 wm_state
->sr
[level
].plane
=
1884 vlv_invert_wm_value(max3(raw
->plane
[PLANE_PRIMARY
],
1885 raw
->plane
[PLANE_SPRITE0
],
1886 raw
->plane
[PLANE_SPRITE1
]),
1889 wm_state
->sr
[level
].cursor
=
1890 vlv_invert_wm_value(raw
->plane
[PLANE_CURSOR
],
1897 /* limit to only levels we can actually handle */
1898 wm_state
->num_levels
= level
;
1900 /* invalidate the higher levels */
1901 vlv_invalidate_wms(crtc
, wm_state
, level
);
1906 #define VLV_FIFO(plane, value) \
1907 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1909 static void vlv_atomic_update_fifo(struct intel_atomic_state
*state
,
1910 struct intel_crtc_state
*crtc_state
)
1912 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1913 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1914 const struct vlv_fifo_state
*fifo_state
=
1915 &crtc_state
->wm
.vlv
.fifo_state
;
1916 int sprite0_start
, sprite1_start
, fifo_size
;
1918 if (!crtc_state
->fifo_changed
)
1921 sprite0_start
= fifo_state
->plane
[PLANE_PRIMARY
];
1922 sprite1_start
= fifo_state
->plane
[PLANE_SPRITE0
] + sprite0_start
;
1923 fifo_size
= fifo_state
->plane
[PLANE_SPRITE1
] + sprite1_start
;
1925 WARN_ON(fifo_state
->plane
[PLANE_CURSOR
] != 63);
1926 WARN_ON(fifo_size
!= 511);
1928 trace_vlv_fifo_size(crtc
, sprite0_start
, sprite1_start
, fifo_size
);
1931 * uncore.lock serves a double purpose here. It allows us to
1932 * use the less expensive I915_{READ,WRITE}_FW() functions, and
1933 * it protects the DSPARB registers from getting clobbered by
1934 * parallel updates from multiple pipes.
1936 * intel_pipe_update_start() has already disabled interrupts
1937 * for us, so a plain spin_lock() is sufficient here.
1939 spin_lock(&dev_priv
->uncore
.lock
);
1941 switch (crtc
->pipe
) {
1942 uint32_t dsparb
, dsparb2
, dsparb3
;
1944 dsparb
= I915_READ_FW(DSPARB
);
1945 dsparb2
= I915_READ_FW(DSPARB2
);
1947 dsparb
&= ~(VLV_FIFO(SPRITEA
, 0xff) |
1948 VLV_FIFO(SPRITEB
, 0xff));
1949 dsparb
|= (VLV_FIFO(SPRITEA
, sprite0_start
) |
1950 VLV_FIFO(SPRITEB
, sprite1_start
));
1952 dsparb2
&= ~(VLV_FIFO(SPRITEA_HI
, 0x1) |
1953 VLV_FIFO(SPRITEB_HI
, 0x1));
1954 dsparb2
|= (VLV_FIFO(SPRITEA_HI
, sprite0_start
>> 8) |
1955 VLV_FIFO(SPRITEB_HI
, sprite1_start
>> 8));
1957 I915_WRITE_FW(DSPARB
, dsparb
);
1958 I915_WRITE_FW(DSPARB2
, dsparb2
);
1961 dsparb
= I915_READ_FW(DSPARB
);
1962 dsparb2
= I915_READ_FW(DSPARB2
);
1964 dsparb
&= ~(VLV_FIFO(SPRITEC
, 0xff) |
1965 VLV_FIFO(SPRITED
, 0xff));
1966 dsparb
|= (VLV_FIFO(SPRITEC
, sprite0_start
) |
1967 VLV_FIFO(SPRITED
, sprite1_start
));
1969 dsparb2
&= ~(VLV_FIFO(SPRITEC_HI
, 0xff) |
1970 VLV_FIFO(SPRITED_HI
, 0xff));
1971 dsparb2
|= (VLV_FIFO(SPRITEC_HI
, sprite0_start
>> 8) |
1972 VLV_FIFO(SPRITED_HI
, sprite1_start
>> 8));
1974 I915_WRITE_FW(DSPARB
, dsparb
);
1975 I915_WRITE_FW(DSPARB2
, dsparb2
);
1978 dsparb3
= I915_READ_FW(DSPARB3
);
1979 dsparb2
= I915_READ_FW(DSPARB2
);
1981 dsparb3
&= ~(VLV_FIFO(SPRITEE
, 0xff) |
1982 VLV_FIFO(SPRITEF
, 0xff));
1983 dsparb3
|= (VLV_FIFO(SPRITEE
, sprite0_start
) |
1984 VLV_FIFO(SPRITEF
, sprite1_start
));
1986 dsparb2
&= ~(VLV_FIFO(SPRITEE_HI
, 0xff) |
1987 VLV_FIFO(SPRITEF_HI
, 0xff));
1988 dsparb2
|= (VLV_FIFO(SPRITEE_HI
, sprite0_start
>> 8) |
1989 VLV_FIFO(SPRITEF_HI
, sprite1_start
>> 8));
1991 I915_WRITE_FW(DSPARB3
, dsparb3
);
1992 I915_WRITE_FW(DSPARB2
, dsparb2
);
1998 POSTING_READ_FW(DSPARB
);
2000 spin_unlock(&dev_priv
->uncore
.lock
);
2005 static int vlv_compute_intermediate_wm(struct drm_device
*dev
,
2006 struct intel_crtc
*crtc
,
2007 struct intel_crtc_state
*crtc_state
)
2009 struct vlv_wm_state
*intermediate
= &crtc_state
->wm
.vlv
.intermediate
;
2010 const struct vlv_wm_state
*optimal
= &crtc_state
->wm
.vlv
.optimal
;
2011 const struct vlv_wm_state
*active
= &crtc
->wm
.active
.vlv
;
2014 intermediate
->num_levels
= min(optimal
->num_levels
, active
->num_levels
);
2015 intermediate
->cxsr
= optimal
->cxsr
&& active
->cxsr
&&
2016 !crtc_state
->disable_cxsr
;
2018 for (level
= 0; level
< intermediate
->num_levels
; level
++) {
2019 enum plane_id plane_id
;
2021 for_each_plane_id_on_crtc(crtc
, plane_id
) {
2022 intermediate
->wm
[level
].plane
[plane_id
] =
2023 min(optimal
->wm
[level
].plane
[plane_id
],
2024 active
->wm
[level
].plane
[plane_id
]);
2027 intermediate
->sr
[level
].plane
= min(optimal
->sr
[level
].plane
,
2028 active
->sr
[level
].plane
);
2029 intermediate
->sr
[level
].cursor
= min(optimal
->sr
[level
].cursor
,
2030 active
->sr
[level
].cursor
);
2033 vlv_invalidate_wms(crtc
, intermediate
, level
);
2036 * If our intermediate WM are identical to the final WM, then we can
2037 * omit the post-vblank programming; only update if it's different.
2039 if (memcmp(intermediate
, optimal
, sizeof(*intermediate
)) != 0)
2040 crtc_state
->wm
.need_postvbl_update
= true;
2045 static void vlv_merge_wm(struct drm_i915_private
*dev_priv
,
2046 struct vlv_wm_values
*wm
)
2048 struct intel_crtc
*crtc
;
2049 int num_active_crtcs
= 0;
2051 wm
->level
= dev_priv
->wm
.max_level
;
2054 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
2055 const struct vlv_wm_state
*wm_state
= &crtc
->wm
.active
.vlv
;
2060 if (!wm_state
->cxsr
)
2064 wm
->level
= min_t(int, wm
->level
, wm_state
->num_levels
- 1);
2067 if (num_active_crtcs
!= 1)
2070 if (num_active_crtcs
> 1)
2071 wm
->level
= VLV_WM_LEVEL_PM2
;
2073 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
2074 const struct vlv_wm_state
*wm_state
= &crtc
->wm
.active
.vlv
;
2075 enum pipe pipe
= crtc
->pipe
;
2077 wm
->pipe
[pipe
] = wm_state
->wm
[wm
->level
];
2078 if (crtc
->active
&& wm
->cxsr
)
2079 wm
->sr
= wm_state
->sr
[wm
->level
];
2081 wm
->ddl
[pipe
].plane
[PLANE_PRIMARY
] = DDL_PRECISION_HIGH
| 2;
2082 wm
->ddl
[pipe
].plane
[PLANE_SPRITE0
] = DDL_PRECISION_HIGH
| 2;
2083 wm
->ddl
[pipe
].plane
[PLANE_SPRITE1
] = DDL_PRECISION_HIGH
| 2;
2084 wm
->ddl
[pipe
].plane
[PLANE_CURSOR
] = DDL_PRECISION_HIGH
| 2;
2088 static void vlv_program_watermarks(struct drm_i915_private
*dev_priv
)
2090 struct vlv_wm_values
*old_wm
= &dev_priv
->wm
.vlv
;
2091 struct vlv_wm_values new_wm
= {};
2093 vlv_merge_wm(dev_priv
, &new_wm
);
2095 if (memcmp(old_wm
, &new_wm
, sizeof(new_wm
)) == 0)
2098 if (is_disabling(old_wm
->level
, new_wm
.level
, VLV_WM_LEVEL_DDR_DVFS
))
2099 chv_set_memory_dvfs(dev_priv
, false);
2101 if (is_disabling(old_wm
->level
, new_wm
.level
, VLV_WM_LEVEL_PM5
))
2102 chv_set_memory_pm5(dev_priv
, false);
2104 if (is_disabling(old_wm
->cxsr
, new_wm
.cxsr
, true))
2105 _intel_set_memory_cxsr(dev_priv
, false);
2107 vlv_write_wm_values(dev_priv
, &new_wm
);
2109 if (is_enabling(old_wm
->cxsr
, new_wm
.cxsr
, true))
2110 _intel_set_memory_cxsr(dev_priv
, true);
2112 if (is_enabling(old_wm
->level
, new_wm
.level
, VLV_WM_LEVEL_PM5
))
2113 chv_set_memory_pm5(dev_priv
, true);
2115 if (is_enabling(old_wm
->level
, new_wm
.level
, VLV_WM_LEVEL_DDR_DVFS
))
2116 chv_set_memory_dvfs(dev_priv
, true);
2121 static void vlv_initial_watermarks(struct intel_atomic_state
*state
,
2122 struct intel_crtc_state
*crtc_state
)
2124 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
2125 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
2127 mutex_lock(&dev_priv
->wm
.wm_mutex
);
2128 crtc
->wm
.active
.vlv
= crtc_state
->wm
.vlv
.intermediate
;
2129 vlv_program_watermarks(dev_priv
);
2130 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
2133 static void vlv_optimize_watermarks(struct intel_atomic_state
*state
,
2134 struct intel_crtc_state
*crtc_state
)
2136 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
2137 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
2139 if (!crtc_state
->wm
.need_postvbl_update
)
2142 mutex_lock(&dev_priv
->wm
.wm_mutex
);
2143 intel_crtc
->wm
.active
.vlv
= crtc_state
->wm
.vlv
.optimal
;
2144 vlv_program_watermarks(dev_priv
);
2145 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
2148 static void i965_update_wm(struct intel_crtc
*unused_crtc
)
2150 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
2151 struct intel_crtc
*crtc
;
2156 /* Calc sr entries for one plane configs */
2157 crtc
= single_enabled_crtc(dev_priv
);
2159 /* self-refresh has much higher latency */
2160 static const int sr_latency_ns
= 12000;
2161 const struct drm_display_mode
*adjusted_mode
=
2162 &crtc
->config
->base
.adjusted_mode
;
2163 const struct drm_framebuffer
*fb
=
2164 crtc
->base
.primary
->state
->fb
;
2165 int clock
= adjusted_mode
->crtc_clock
;
2166 int htotal
= adjusted_mode
->crtc_htotal
;
2167 int hdisplay
= crtc
->config
->pipe_src_w
;
2168 int cpp
= fb
->format
->cpp
[0];
2171 entries
= intel_wm_method2(clock
, htotal
,
2172 hdisplay
, cpp
, sr_latency_ns
/ 100);
2173 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
2174 srwm
= I965_FIFO_SIZE
- entries
;
2178 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
2181 entries
= intel_wm_method2(clock
, htotal
,
2182 crtc
->base
.cursor
->state
->crtc_w
, 4,
2183 sr_latency_ns
/ 100);
2184 entries
= DIV_ROUND_UP(entries
,
2185 i965_cursor_wm_info
.cacheline_size
) +
2186 i965_cursor_wm_info
.guard_size
;
2188 cursor_sr
= i965_cursor_wm_info
.fifo_size
- entries
;
2189 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
2190 cursor_sr
= i965_cursor_wm_info
.max_wm
;
2192 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
2193 "cursor %d\n", srwm
, cursor_sr
);
2195 cxsr_enabled
= true;
2197 cxsr_enabled
= false;
2198 /* Turn off self refresh if both pipes are enabled */
2199 intel_set_memory_cxsr(dev_priv
, false);
2202 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2205 /* 965 has limitations... */
2206 I915_WRITE(DSPFW1
, FW_WM(srwm
, SR
) |
2210 I915_WRITE(DSPFW2
, FW_WM(8, CURSORA
) |
2211 FW_WM(8, PLANEC_OLD
));
2212 /* update cursor SR watermark */
2213 I915_WRITE(DSPFW3
, FW_WM(cursor_sr
, CURSOR_SR
));
2216 intel_set_memory_cxsr(dev_priv
, true);
2221 static void i9xx_update_wm(struct intel_crtc
*unused_crtc
)
2223 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
2224 const struct intel_watermark_params
*wm_info
;
2229 int planea_wm
, planeb_wm
;
2230 struct intel_crtc
*crtc
, *enabled
= NULL
;
2232 if (IS_I945GM(dev_priv
))
2233 wm_info
= &i945_wm_info
;
2234 else if (!IS_GEN2(dev_priv
))
2235 wm_info
= &i915_wm_info
;
2237 wm_info
= &i830_a_wm_info
;
2239 fifo_size
= dev_priv
->display
.get_fifo_size(dev_priv
, 0);
2240 crtc
= intel_get_crtc_for_plane(dev_priv
, 0);
2241 if (intel_crtc_active(crtc
)) {
2242 const struct drm_display_mode
*adjusted_mode
=
2243 &crtc
->config
->base
.adjusted_mode
;
2244 const struct drm_framebuffer
*fb
=
2245 crtc
->base
.primary
->state
->fb
;
2248 if (IS_GEN2(dev_priv
))
2251 cpp
= fb
->format
->cpp
[0];
2253 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
2254 wm_info
, fifo_size
, cpp
,
2255 pessimal_latency_ns
);
2258 planea_wm
= fifo_size
- wm_info
->guard_size
;
2259 if (planea_wm
> (long)wm_info
->max_wm
)
2260 planea_wm
= wm_info
->max_wm
;
2263 if (IS_GEN2(dev_priv
))
2264 wm_info
= &i830_bc_wm_info
;
2266 fifo_size
= dev_priv
->display
.get_fifo_size(dev_priv
, 1);
2267 crtc
= intel_get_crtc_for_plane(dev_priv
, 1);
2268 if (intel_crtc_active(crtc
)) {
2269 const struct drm_display_mode
*adjusted_mode
=
2270 &crtc
->config
->base
.adjusted_mode
;
2271 const struct drm_framebuffer
*fb
=
2272 crtc
->base
.primary
->state
->fb
;
2275 if (IS_GEN2(dev_priv
))
2278 cpp
= fb
->format
->cpp
[0];
2280 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
2281 wm_info
, fifo_size
, cpp
,
2282 pessimal_latency_ns
);
2283 if (enabled
== NULL
)
2288 planeb_wm
= fifo_size
- wm_info
->guard_size
;
2289 if (planeb_wm
> (long)wm_info
->max_wm
)
2290 planeb_wm
= wm_info
->max_wm
;
2293 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
2295 if (IS_I915GM(dev_priv
) && enabled
) {
2296 struct drm_i915_gem_object
*obj
;
2298 obj
= intel_fb_obj(enabled
->base
.primary
->state
->fb
);
2300 /* self-refresh seems busted with untiled */
2301 if (!i915_gem_object_is_tiled(obj
))
2306 * Overlay gets an aggressive default since video jitter is bad.
2310 /* Play safe and disable self-refresh before adjusting watermarks. */
2311 intel_set_memory_cxsr(dev_priv
, false);
2313 /* Calc sr entries for one plane configs */
2314 if (HAS_FW_BLC(dev_priv
) && enabled
) {
2315 /* self-refresh has much higher latency */
2316 static const int sr_latency_ns
= 6000;
2317 const struct drm_display_mode
*adjusted_mode
=
2318 &enabled
->config
->base
.adjusted_mode
;
2319 const struct drm_framebuffer
*fb
=
2320 enabled
->base
.primary
->state
->fb
;
2321 int clock
= adjusted_mode
->crtc_clock
;
2322 int htotal
= adjusted_mode
->crtc_htotal
;
2323 int hdisplay
= enabled
->config
->pipe_src_w
;
2327 if (IS_I915GM(dev_priv
) || IS_I945GM(dev_priv
))
2330 cpp
= fb
->format
->cpp
[0];
2332 entries
= intel_wm_method2(clock
, htotal
, hdisplay
, cpp
,
2333 sr_latency_ns
/ 100);
2334 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
2335 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
2336 srwm
= wm_info
->fifo_size
- entries
;
2340 if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
))
2341 I915_WRITE(FW_BLC_SELF
,
2342 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
2344 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
2347 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2348 planea_wm
, planeb_wm
, cwm
, srwm
);
2350 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
2351 fwater_hi
= (cwm
& 0x1f);
2353 /* Set request length to 8 cachelines per fetch */
2354 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
2355 fwater_hi
= fwater_hi
| (1 << 8);
2357 I915_WRITE(FW_BLC
, fwater_lo
);
2358 I915_WRITE(FW_BLC2
, fwater_hi
);
2361 intel_set_memory_cxsr(dev_priv
, true);
2364 static void i845_update_wm(struct intel_crtc
*unused_crtc
)
2366 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
2367 struct intel_crtc
*crtc
;
2368 const struct drm_display_mode
*adjusted_mode
;
2372 crtc
= single_enabled_crtc(dev_priv
);
2376 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
2377 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
2379 dev_priv
->display
.get_fifo_size(dev_priv
, 0),
2380 4, pessimal_latency_ns
);
2381 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
2382 fwater_lo
|= (3<<8) | planea_wm
;
2384 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
2386 I915_WRITE(FW_BLC
, fwater_lo
);
2389 /* latency must be in 0.1us units. */
2390 static unsigned int ilk_wm_method1(unsigned int pixel_rate
,
2392 unsigned int latency
)
2396 ret
= intel_wm_method1(pixel_rate
, cpp
, latency
);
2397 ret
= DIV_ROUND_UP(ret
, 64) + 2;
2402 /* latency must be in 0.1us units. */
2403 static unsigned int ilk_wm_method2(unsigned int pixel_rate
,
2404 unsigned int htotal
,
2407 unsigned int latency
)
2411 ret
= intel_wm_method2(pixel_rate
, htotal
,
2412 width
, cpp
, latency
);
2413 ret
= DIV_ROUND_UP(ret
, 64) + 2;
2418 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
2422 * Neither of these should be possible since this function shouldn't be
2423 * called if the CRTC is off or the plane is invisible. But let's be
2424 * extra paranoid to avoid a potential divide-by-zero if we screw up
2425 * elsewhere in the driver.
2429 if (WARN_ON(!horiz_pixels
))
2432 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* cpp
) + 2;
2435 struct ilk_wm_maximums
{
2443 * For both WM_PIPE and WM_LP.
2444 * mem_value must be in 0.1us units.
2446 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state
*cstate
,
2447 const struct intel_plane_state
*pstate
,
2451 uint32_t method1
, method2
;
2454 if (!intel_wm_plane_visible(cstate
, pstate
))
2457 cpp
= pstate
->base
.fb
->format
->cpp
[0];
2459 method1
= ilk_wm_method1(cstate
->pixel_rate
, cpp
, mem_value
);
2464 method2
= ilk_wm_method2(cstate
->pixel_rate
,
2465 cstate
->base
.adjusted_mode
.crtc_htotal
,
2466 drm_rect_width(&pstate
->base
.dst
),
2469 return min(method1
, method2
);
2473 * For both WM_PIPE and WM_LP.
2474 * mem_value must be in 0.1us units.
2476 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state
*cstate
,
2477 const struct intel_plane_state
*pstate
,
2480 uint32_t method1
, method2
;
2483 if (!intel_wm_plane_visible(cstate
, pstate
))
2486 cpp
= pstate
->base
.fb
->format
->cpp
[0];
2488 method1
= ilk_wm_method1(cstate
->pixel_rate
, cpp
, mem_value
);
2489 method2
= ilk_wm_method2(cstate
->pixel_rate
,
2490 cstate
->base
.adjusted_mode
.crtc_htotal
,
2491 drm_rect_width(&pstate
->base
.dst
),
2493 return min(method1
, method2
);
2497 * For both WM_PIPE and WM_LP.
2498 * mem_value must be in 0.1us units.
2500 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state
*cstate
,
2501 const struct intel_plane_state
*pstate
,
2506 if (!intel_wm_plane_visible(cstate
, pstate
))
2509 cpp
= pstate
->base
.fb
->format
->cpp
[0];
2511 return ilk_wm_method2(cstate
->pixel_rate
,
2512 cstate
->base
.adjusted_mode
.crtc_htotal
,
2513 pstate
->base
.crtc_w
, cpp
, mem_value
);
2516 /* Only for WM_LP. */
2517 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state
*cstate
,
2518 const struct intel_plane_state
*pstate
,
2523 if (!intel_wm_plane_visible(cstate
, pstate
))
2526 cpp
= pstate
->base
.fb
->format
->cpp
[0];
2528 return ilk_wm_fbc(pri_val
, drm_rect_width(&pstate
->base
.dst
), cpp
);
2532 ilk_display_fifo_size(const struct drm_i915_private
*dev_priv
)
2534 if (INTEL_GEN(dev_priv
) >= 8)
2536 else if (INTEL_GEN(dev_priv
) >= 7)
2543 ilk_plane_wm_reg_max(const struct drm_i915_private
*dev_priv
,
2544 int level
, bool is_sprite
)
2546 if (INTEL_GEN(dev_priv
) >= 8)
2547 /* BDW primary/sprite plane watermarks */
2548 return level
== 0 ? 255 : 2047;
2549 else if (INTEL_GEN(dev_priv
) >= 7)
2550 /* IVB/HSW primary/sprite plane watermarks */
2551 return level
== 0 ? 127 : 1023;
2552 else if (!is_sprite
)
2553 /* ILK/SNB primary plane watermarks */
2554 return level
== 0 ? 127 : 511;
2556 /* ILK/SNB sprite plane watermarks */
2557 return level
== 0 ? 63 : 255;
2561 ilk_cursor_wm_reg_max(const struct drm_i915_private
*dev_priv
, int level
)
2563 if (INTEL_GEN(dev_priv
) >= 7)
2564 return level
== 0 ? 63 : 255;
2566 return level
== 0 ? 31 : 63;
2569 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private
*dev_priv
)
2571 if (INTEL_GEN(dev_priv
) >= 8)
2577 /* Calculate the maximum primary/sprite plane watermark */
2578 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
2580 const struct intel_wm_config
*config
,
2581 enum intel_ddb_partitioning ddb_partitioning
,
2584 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2585 unsigned int fifo_size
= ilk_display_fifo_size(dev_priv
);
2587 /* if sprites aren't enabled, sprites get nothing */
2588 if (is_sprite
&& !config
->sprites_enabled
)
2591 /* HSW allows LP1+ watermarks even with multiple pipes */
2592 if (level
== 0 || config
->num_pipes_active
> 1) {
2593 fifo_size
/= INTEL_INFO(dev_priv
)->num_pipes
;
2596 * For some reason the non self refresh
2597 * FIFO size is only half of the self
2598 * refresh FIFO size on ILK/SNB.
2600 if (INTEL_GEN(dev_priv
) <= 6)
2604 if (config
->sprites_enabled
) {
2605 /* level 0 is always calculated with 1:1 split */
2606 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
2615 /* clamp to max that the registers can hold */
2616 return min(fifo_size
, ilk_plane_wm_reg_max(dev_priv
, level
, is_sprite
));
2619 /* Calculate the maximum cursor plane watermark */
2620 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
2622 const struct intel_wm_config
*config
)
2624 /* HSW LP1+ watermarks w/ multiple pipes */
2625 if (level
> 0 && config
->num_pipes_active
> 1)
2628 /* otherwise just report max that registers can hold */
2629 return ilk_cursor_wm_reg_max(to_i915(dev
), level
);
2632 static void ilk_compute_wm_maximums(const struct drm_device
*dev
,
2634 const struct intel_wm_config
*config
,
2635 enum intel_ddb_partitioning ddb_partitioning
,
2636 struct ilk_wm_maximums
*max
)
2638 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
2639 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
2640 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
2641 max
->fbc
= ilk_fbc_wm_reg_max(to_i915(dev
));
2644 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private
*dev_priv
,
2646 struct ilk_wm_maximums
*max
)
2648 max
->pri
= ilk_plane_wm_reg_max(dev_priv
, level
, false);
2649 max
->spr
= ilk_plane_wm_reg_max(dev_priv
, level
, true);
2650 max
->cur
= ilk_cursor_wm_reg_max(dev_priv
, level
);
2651 max
->fbc
= ilk_fbc_wm_reg_max(dev_priv
);
2654 static bool ilk_validate_wm_level(int level
,
2655 const struct ilk_wm_maximums
*max
,
2656 struct intel_wm_level
*result
)
2660 /* already determined to be invalid? */
2661 if (!result
->enable
)
2664 result
->enable
= result
->pri_val
<= max
->pri
&&
2665 result
->spr_val
<= max
->spr
&&
2666 result
->cur_val
<= max
->cur
;
2668 ret
= result
->enable
;
2671 * HACK until we can pre-compute everything,
2672 * and thus fail gracefully if LP0 watermarks
2675 if (level
== 0 && !result
->enable
) {
2676 if (result
->pri_val
> max
->pri
)
2677 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2678 level
, result
->pri_val
, max
->pri
);
2679 if (result
->spr_val
> max
->spr
)
2680 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2681 level
, result
->spr_val
, max
->spr
);
2682 if (result
->cur_val
> max
->cur
)
2683 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2684 level
, result
->cur_val
, max
->cur
);
2686 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
2687 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
2688 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
2689 result
->enable
= true;
2695 static void ilk_compute_wm_level(const struct drm_i915_private
*dev_priv
,
2696 const struct intel_crtc
*intel_crtc
,
2698 struct intel_crtc_state
*cstate
,
2699 const struct intel_plane_state
*pristate
,
2700 const struct intel_plane_state
*sprstate
,
2701 const struct intel_plane_state
*curstate
,
2702 struct intel_wm_level
*result
)
2704 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
2705 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
2706 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
2708 /* WM1+ latency values stored in 0.5us units */
2716 result
->pri_val
= ilk_compute_pri_wm(cstate
, pristate
,
2717 pri_latency
, level
);
2718 result
->fbc_val
= ilk_compute_fbc_wm(cstate
, pristate
, result
->pri_val
);
2722 result
->spr_val
= ilk_compute_spr_wm(cstate
, sprstate
, spr_latency
);
2725 result
->cur_val
= ilk_compute_cur_wm(cstate
, curstate
, cur_latency
);
2727 result
->enable
= true;
2731 hsw_compute_linetime_wm(const struct intel_crtc_state
*cstate
)
2733 const struct intel_atomic_state
*intel_state
=
2734 to_intel_atomic_state(cstate
->base
.state
);
2735 const struct drm_display_mode
*adjusted_mode
=
2736 &cstate
->base
.adjusted_mode
;
2737 u32 linetime
, ips_linetime
;
2739 if (!cstate
->base
.active
)
2741 if (WARN_ON(adjusted_mode
->crtc_clock
== 0))
2743 if (WARN_ON(intel_state
->cdclk
.logical
.cdclk
== 0))
2746 /* The WM are computed with base on how long it takes to fill a single
2747 * row at the given clock rate, multiplied by 8.
2749 linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2750 adjusted_mode
->crtc_clock
);
2751 ips_linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2752 intel_state
->cdclk
.logical
.cdclk
);
2754 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2755 PIPE_WM_LINETIME_TIME(linetime
);
2758 static void intel_read_wm_latency(struct drm_i915_private
*dev_priv
,
2761 if (IS_GEN9(dev_priv
)) {
2764 int level
, max_level
= ilk_wm_max_level(dev_priv
);
2766 /* read the first set of memory latencies[0:3] */
2767 val
= 0; /* data0 to be programmed to 0 for first set */
2768 mutex_lock(&dev_priv
->rps
.hw_lock
);
2769 ret
= sandybridge_pcode_read(dev_priv
,
2770 GEN9_PCODE_READ_MEM_LATENCY
,
2772 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2775 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2779 wm
[0] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2780 wm
[1] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2781 GEN9_MEM_LATENCY_LEVEL_MASK
;
2782 wm
[2] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2783 GEN9_MEM_LATENCY_LEVEL_MASK
;
2784 wm
[3] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2785 GEN9_MEM_LATENCY_LEVEL_MASK
;
2787 /* read the second set of memory latencies[4:7] */
2788 val
= 1; /* data0 to be programmed to 1 for second set */
2789 mutex_lock(&dev_priv
->rps
.hw_lock
);
2790 ret
= sandybridge_pcode_read(dev_priv
,
2791 GEN9_PCODE_READ_MEM_LATENCY
,
2793 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2795 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2799 wm
[4] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2800 wm
[5] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2801 GEN9_MEM_LATENCY_LEVEL_MASK
;
2802 wm
[6] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2803 GEN9_MEM_LATENCY_LEVEL_MASK
;
2804 wm
[7] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2805 GEN9_MEM_LATENCY_LEVEL_MASK
;
2808 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2809 * need to be disabled. We make sure to sanitize the values out
2810 * of the punit to satisfy this requirement.
2812 for (level
= 1; level
<= max_level
; level
++) {
2813 if (wm
[level
] == 0) {
2814 for (i
= level
+ 1; i
<= max_level
; i
++)
2821 * WaWmMemoryReadLatency:skl,glk
2823 * punit doesn't take into account the read latency so we need
2824 * to add 2us to the various latency levels we retrieve from the
2825 * punit when level 0 response data us 0us.
2829 for (level
= 1; level
<= max_level
; level
++) {
2836 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2837 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2839 wm
[0] = (sskpd
>> 56) & 0xFF;
2841 wm
[0] = sskpd
& 0xF;
2842 wm
[1] = (sskpd
>> 4) & 0xFF;
2843 wm
[2] = (sskpd
>> 12) & 0xFF;
2844 wm
[3] = (sskpd
>> 20) & 0x1FF;
2845 wm
[4] = (sskpd
>> 32) & 0x1FF;
2846 } else if (INTEL_GEN(dev_priv
) >= 6) {
2847 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
2849 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
2850 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
2851 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
2852 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
2853 } else if (INTEL_GEN(dev_priv
) >= 5) {
2854 uint32_t mltr
= I915_READ(MLTR_ILK
);
2856 /* ILK primary LP0 latency is 700 ns */
2858 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
2859 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
2863 static void intel_fixup_spr_wm_latency(struct drm_i915_private
*dev_priv
,
2866 /* ILK sprite LP0 latency is 1300 ns */
2867 if (IS_GEN5(dev_priv
))
2871 static void intel_fixup_cur_wm_latency(struct drm_i915_private
*dev_priv
,
2874 /* ILK cursor LP0 latency is 1300 ns */
2875 if (IS_GEN5(dev_priv
))
2878 /* WaDoubleCursorLP3Latency:ivb */
2879 if (IS_IVYBRIDGE(dev_priv
))
2883 int ilk_wm_max_level(const struct drm_i915_private
*dev_priv
)
2885 /* how many WM levels are we expecting */
2886 if (INTEL_GEN(dev_priv
) >= 9)
2888 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
2890 else if (INTEL_GEN(dev_priv
) >= 6)
2896 static void intel_print_wm_latency(struct drm_i915_private
*dev_priv
,
2898 const uint16_t wm
[8])
2900 int level
, max_level
= ilk_wm_max_level(dev_priv
);
2902 for (level
= 0; level
<= max_level
; level
++) {
2903 unsigned int latency
= wm
[level
];
2906 DRM_ERROR("%s WM%d latency not provided\n",
2912 * - latencies are in us on gen9.
2913 * - before then, WM1+ latency values are in 0.5us units
2915 if (IS_GEN9(dev_priv
))
2920 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2921 name
, level
, wm
[level
],
2922 latency
/ 10, latency
% 10);
2926 static bool ilk_increase_wm_latency(struct drm_i915_private
*dev_priv
,
2927 uint16_t wm
[5], uint16_t min
)
2929 int level
, max_level
= ilk_wm_max_level(dev_priv
);
2934 wm
[0] = max(wm
[0], min
);
2935 for (level
= 1; level
<= max_level
; level
++)
2936 wm
[level
] = max_t(uint16_t, wm
[level
], DIV_ROUND_UP(min
, 5));
2941 static void snb_wm_latency_quirk(struct drm_i915_private
*dev_priv
)
2946 * The BIOS provided WM memory latency values are often
2947 * inadequate for high resolution displays. Adjust them.
2949 changed
= ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
, 12) |
2950 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
, 12) |
2951 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
, 12);
2956 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2957 intel_print_wm_latency(dev_priv
, "Primary", dev_priv
->wm
.pri_latency
);
2958 intel_print_wm_latency(dev_priv
, "Sprite", dev_priv
->wm
.spr_latency
);
2959 intel_print_wm_latency(dev_priv
, "Cursor", dev_priv
->wm
.cur_latency
);
2962 static void ilk_setup_wm_latency(struct drm_i915_private
*dev_priv
)
2964 intel_read_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
);
2966 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
2967 sizeof(dev_priv
->wm
.pri_latency
));
2968 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
2969 sizeof(dev_priv
->wm
.pri_latency
));
2971 intel_fixup_spr_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
);
2972 intel_fixup_cur_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
);
2974 intel_print_wm_latency(dev_priv
, "Primary", dev_priv
->wm
.pri_latency
);
2975 intel_print_wm_latency(dev_priv
, "Sprite", dev_priv
->wm
.spr_latency
);
2976 intel_print_wm_latency(dev_priv
, "Cursor", dev_priv
->wm
.cur_latency
);
2978 if (IS_GEN6(dev_priv
))
2979 snb_wm_latency_quirk(dev_priv
);
2982 static void skl_setup_wm_latency(struct drm_i915_private
*dev_priv
)
2984 intel_read_wm_latency(dev_priv
, dev_priv
->wm
.skl_latency
);
2985 intel_print_wm_latency(dev_priv
, "Gen9 Plane", dev_priv
->wm
.skl_latency
);
2988 static bool ilk_validate_pipe_wm(struct drm_device
*dev
,
2989 struct intel_pipe_wm
*pipe_wm
)
2991 /* LP0 watermark maximums depend on this pipe alone */
2992 const struct intel_wm_config config
= {
2993 .num_pipes_active
= 1,
2994 .sprites_enabled
= pipe_wm
->sprites_enabled
,
2995 .sprites_scaled
= pipe_wm
->sprites_scaled
,
2997 struct ilk_wm_maximums max
;
2999 /* LP0 watermarks always use 1/2 DDB partitioning */
3000 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
3002 /* At least LP0 must be valid */
3003 if (!ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0])) {
3004 DRM_DEBUG_KMS("LP0 watermark invalid\n");
3011 /* Compute new watermarks for the pipe */
3012 static int ilk_compute_pipe_wm(struct intel_crtc_state
*cstate
)
3014 struct drm_atomic_state
*state
= cstate
->base
.state
;
3015 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
3016 struct intel_pipe_wm
*pipe_wm
;
3017 struct drm_device
*dev
= state
->dev
;
3018 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
3019 struct drm_plane
*plane
;
3020 const struct drm_plane_state
*plane_state
;
3021 const struct intel_plane_state
*pristate
= NULL
;
3022 const struct intel_plane_state
*sprstate
= NULL
;
3023 const struct intel_plane_state
*curstate
= NULL
;
3024 int level
, max_level
= ilk_wm_max_level(dev_priv
), usable_level
;
3025 struct ilk_wm_maximums max
;
3027 pipe_wm
= &cstate
->wm
.ilk
.optimal
;
3029 drm_atomic_crtc_state_for_each_plane_state(plane
, plane_state
, &cstate
->base
) {
3030 const struct intel_plane_state
*ps
= to_intel_plane_state(plane_state
);
3032 if (plane
->type
== DRM_PLANE_TYPE_PRIMARY
)
3034 else if (plane
->type
== DRM_PLANE_TYPE_OVERLAY
)
3036 else if (plane
->type
== DRM_PLANE_TYPE_CURSOR
)
3040 pipe_wm
->pipe_enabled
= cstate
->base
.active
;
3042 pipe_wm
->sprites_enabled
= sprstate
->base
.visible
;
3043 pipe_wm
->sprites_scaled
= sprstate
->base
.visible
&&
3044 (drm_rect_width(&sprstate
->base
.dst
) != drm_rect_width(&sprstate
->base
.src
) >> 16 ||
3045 drm_rect_height(&sprstate
->base
.dst
) != drm_rect_height(&sprstate
->base
.src
) >> 16);
3048 usable_level
= max_level
;
3050 /* ILK/SNB: LP2+ watermarks only w/o sprites */
3051 if (INTEL_GEN(dev_priv
) <= 6 && pipe_wm
->sprites_enabled
)
3054 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
3055 if (pipe_wm
->sprites_scaled
)
3058 memset(&pipe_wm
->wm
, 0, sizeof(pipe_wm
->wm
));
3059 ilk_compute_wm_level(dev_priv
, intel_crtc
, 0, cstate
,
3060 pristate
, sprstate
, curstate
, &pipe_wm
->wm
[0]);
3062 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
3063 pipe_wm
->linetime
= hsw_compute_linetime_wm(cstate
);
3065 if (!ilk_validate_pipe_wm(dev
, pipe_wm
))
3068 ilk_compute_wm_reg_maximums(dev_priv
, 1, &max
);
3070 for (level
= 1; level
<= usable_level
; level
++) {
3071 struct intel_wm_level
*wm
= &pipe_wm
->wm
[level
];
3073 ilk_compute_wm_level(dev_priv
, intel_crtc
, level
, cstate
,
3074 pristate
, sprstate
, curstate
, wm
);
3077 * Disable any watermark level that exceeds the
3078 * register maximums since such watermarks are
3081 if (!ilk_validate_wm_level(level
, &max
, wm
)) {
3082 memset(wm
, 0, sizeof(*wm
));
3091 * Build a set of 'intermediate' watermark values that satisfy both the old
3092 * state and the new state. These can be programmed to the hardware
3095 static int ilk_compute_intermediate_wm(struct drm_device
*dev
,
3096 struct intel_crtc
*intel_crtc
,
3097 struct intel_crtc_state
*newstate
)
3099 struct intel_pipe_wm
*a
= &newstate
->wm
.ilk
.intermediate
;
3100 struct intel_pipe_wm
*b
= &intel_crtc
->wm
.active
.ilk
;
3101 int level
, max_level
= ilk_wm_max_level(to_i915(dev
));
3104 * Start with the final, target watermarks, then combine with the
3105 * currently active watermarks to get values that are safe both before
3106 * and after the vblank.
3108 *a
= newstate
->wm
.ilk
.optimal
;
3109 a
->pipe_enabled
|= b
->pipe_enabled
;
3110 a
->sprites_enabled
|= b
->sprites_enabled
;
3111 a
->sprites_scaled
|= b
->sprites_scaled
;
3113 for (level
= 0; level
<= max_level
; level
++) {
3114 struct intel_wm_level
*a_wm
= &a
->wm
[level
];
3115 const struct intel_wm_level
*b_wm
= &b
->wm
[level
];
3117 a_wm
->enable
&= b_wm
->enable
;
3118 a_wm
->pri_val
= max(a_wm
->pri_val
, b_wm
->pri_val
);
3119 a_wm
->spr_val
= max(a_wm
->spr_val
, b_wm
->spr_val
);
3120 a_wm
->cur_val
= max(a_wm
->cur_val
, b_wm
->cur_val
);
3121 a_wm
->fbc_val
= max(a_wm
->fbc_val
, b_wm
->fbc_val
);
3125 * We need to make sure that these merged watermark values are
3126 * actually a valid configuration themselves. If they're not,
3127 * there's no safe way to transition from the old state to
3128 * the new state, so we need to fail the atomic transaction.
3130 if (!ilk_validate_pipe_wm(dev
, a
))
3134 * If our intermediate WM are identical to the final WM, then we can
3135 * omit the post-vblank programming; only update if it's different.
3137 if (memcmp(a
, &newstate
->wm
.ilk
.optimal
, sizeof(*a
)) != 0)
3138 newstate
->wm
.need_postvbl_update
= true;
3144 * Merge the watermarks from all active pipes for a specific level.
3146 static void ilk_merge_wm_level(struct drm_device
*dev
,
3148 struct intel_wm_level
*ret_wm
)
3150 const struct intel_crtc
*intel_crtc
;
3152 ret_wm
->enable
= true;
3154 for_each_intel_crtc(dev
, intel_crtc
) {
3155 const struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
.ilk
;
3156 const struct intel_wm_level
*wm
= &active
->wm
[level
];
3158 if (!active
->pipe_enabled
)
3162 * The watermark values may have been used in the past,
3163 * so we must maintain them in the registers for some
3164 * time even if the level is now disabled.
3167 ret_wm
->enable
= false;
3169 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
3170 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
3171 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
3172 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
3177 * Merge all low power watermarks for all active pipes.
3179 static void ilk_wm_merge(struct drm_device
*dev
,
3180 const struct intel_wm_config
*config
,
3181 const struct ilk_wm_maximums
*max
,
3182 struct intel_pipe_wm
*merged
)
3184 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3185 int level
, max_level
= ilk_wm_max_level(dev_priv
);
3186 int last_enabled_level
= max_level
;
3188 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
3189 if ((INTEL_GEN(dev_priv
) <= 6 || IS_IVYBRIDGE(dev_priv
)) &&
3190 config
->num_pipes_active
> 1)
3191 last_enabled_level
= 0;
3193 /* ILK: FBC WM must be disabled always */
3194 merged
->fbc_wm_enabled
= INTEL_GEN(dev_priv
) >= 6;
3196 /* merge each WM1+ level */
3197 for (level
= 1; level
<= max_level
; level
++) {
3198 struct intel_wm_level
*wm
= &merged
->wm
[level
];
3200 ilk_merge_wm_level(dev
, level
, wm
);
3202 if (level
> last_enabled_level
)
3204 else if (!ilk_validate_wm_level(level
, max
, wm
))
3205 /* make sure all following levels get disabled */
3206 last_enabled_level
= level
- 1;
3209 * The spec says it is preferred to disable
3210 * FBC WMs instead of disabling a WM level.
3212 if (wm
->fbc_val
> max
->fbc
) {
3214 merged
->fbc_wm_enabled
= false;
3219 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
3221 * FIXME this is racy. FBC might get enabled later.
3222 * What we should check here is whether FBC can be
3223 * enabled sometime later.
3225 if (IS_GEN5(dev_priv
) && !merged
->fbc_wm_enabled
&&
3226 intel_fbc_is_active(dev_priv
)) {
3227 for (level
= 2; level
<= max_level
; level
++) {
3228 struct intel_wm_level
*wm
= &merged
->wm
[level
];
3235 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
3237 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
3238 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
3241 /* The value we need to program into the WM_LPx latency field */
3242 static unsigned int ilk_wm_lp_latency(struct drm_device
*dev
, int level
)
3244 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3246 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
3249 return dev_priv
->wm
.pri_latency
[level
];
3252 static void ilk_compute_wm_results(struct drm_device
*dev
,
3253 const struct intel_pipe_wm
*merged
,
3254 enum intel_ddb_partitioning partitioning
,
3255 struct ilk_wm_values
*results
)
3257 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3258 struct intel_crtc
*intel_crtc
;
3261 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
3262 results
->partitioning
= partitioning
;
3264 /* LP1+ register values */
3265 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
3266 const struct intel_wm_level
*r
;
3268 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
3270 r
= &merged
->wm
[level
];
3273 * Maintain the watermark values even if the level is
3274 * disabled. Doing otherwise could cause underruns.
3276 results
->wm_lp
[wm_lp
- 1] =
3277 (ilk_wm_lp_latency(dev
, level
) << WM1_LP_LATENCY_SHIFT
) |
3278 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
3282 results
->wm_lp
[wm_lp
- 1] |= WM1_LP_SR_EN
;
3284 if (INTEL_GEN(dev_priv
) >= 8)
3285 results
->wm_lp
[wm_lp
- 1] |=
3286 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
3288 results
->wm_lp
[wm_lp
- 1] |=
3289 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
3292 * Always set WM1S_LP_EN when spr_val != 0, even if the
3293 * level is disabled. Doing otherwise could cause underruns.
3295 if (INTEL_GEN(dev_priv
) <= 6 && r
->spr_val
) {
3296 WARN_ON(wm_lp
!= 1);
3297 results
->wm_lp_spr
[wm_lp
- 1] = WM1S_LP_EN
| r
->spr_val
;
3299 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
3302 /* LP0 register values */
3303 for_each_intel_crtc(dev
, intel_crtc
) {
3304 enum pipe pipe
= intel_crtc
->pipe
;
3305 const struct intel_wm_level
*r
=
3306 &intel_crtc
->wm
.active
.ilk
.wm
[0];
3308 if (WARN_ON(!r
->enable
))
3311 results
->wm_linetime
[pipe
] = intel_crtc
->wm
.active
.ilk
.linetime
;
3313 results
->wm_pipe
[pipe
] =
3314 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
3315 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
3320 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
3321 * case both are at the same level. Prefer r1 in case they're the same. */
3322 static struct intel_pipe_wm
*ilk_find_best_result(struct drm_device
*dev
,
3323 struct intel_pipe_wm
*r1
,
3324 struct intel_pipe_wm
*r2
)
3326 int level
, max_level
= ilk_wm_max_level(to_i915(dev
));
3327 int level1
= 0, level2
= 0;
3329 for (level
= 1; level
<= max_level
; level
++) {
3330 if (r1
->wm
[level
].enable
)
3332 if (r2
->wm
[level
].enable
)
3336 if (level1
== level2
) {
3337 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
3341 } else if (level1
> level2
) {
3348 /* dirty bits used to track which watermarks need changes */
3349 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
3350 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
3351 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
3352 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
3353 #define WM_DIRTY_FBC (1 << 24)
3354 #define WM_DIRTY_DDB (1 << 25)
3356 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private
*dev_priv
,
3357 const struct ilk_wm_values
*old
,
3358 const struct ilk_wm_values
*new)
3360 unsigned int dirty
= 0;
3364 for_each_pipe(dev_priv
, pipe
) {
3365 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
3366 dirty
|= WM_DIRTY_LINETIME(pipe
);
3367 /* Must disable LP1+ watermarks too */
3368 dirty
|= WM_DIRTY_LP_ALL
;
3371 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
3372 dirty
|= WM_DIRTY_PIPE(pipe
);
3373 /* Must disable LP1+ watermarks too */
3374 dirty
|= WM_DIRTY_LP_ALL
;
3378 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
3379 dirty
|= WM_DIRTY_FBC
;
3380 /* Must disable LP1+ watermarks too */
3381 dirty
|= WM_DIRTY_LP_ALL
;
3384 if (old
->partitioning
!= new->partitioning
) {
3385 dirty
|= WM_DIRTY_DDB
;
3386 /* Must disable LP1+ watermarks too */
3387 dirty
|= WM_DIRTY_LP_ALL
;
3390 /* LP1+ watermarks already deemed dirty, no need to continue */
3391 if (dirty
& WM_DIRTY_LP_ALL
)
3394 /* Find the lowest numbered LP1+ watermark in need of an update... */
3395 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
3396 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
3397 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
3401 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
3402 for (; wm_lp
<= 3; wm_lp
++)
3403 dirty
|= WM_DIRTY_LP(wm_lp
);
3408 static bool _ilk_disable_lp_wm(struct drm_i915_private
*dev_priv
,
3411 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
3412 bool changed
= false;
3414 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] & WM1_LP_SR_EN
) {
3415 previous
->wm_lp
[2] &= ~WM1_LP_SR_EN
;
3416 I915_WRITE(WM3_LP_ILK
, previous
->wm_lp
[2]);
3419 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] & WM1_LP_SR_EN
) {
3420 previous
->wm_lp
[1] &= ~WM1_LP_SR_EN
;
3421 I915_WRITE(WM2_LP_ILK
, previous
->wm_lp
[1]);
3424 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] & WM1_LP_SR_EN
) {
3425 previous
->wm_lp
[0] &= ~WM1_LP_SR_EN
;
3426 I915_WRITE(WM1_LP_ILK
, previous
->wm_lp
[0]);
3431 * Don't touch WM1S_LP_EN here.
3432 * Doing so could cause underruns.
3439 * The spec says we shouldn't write when we don't need, because every write
3440 * causes WMs to be re-evaluated, expending some power.
3442 static void ilk_write_wm_values(struct drm_i915_private
*dev_priv
,
3443 struct ilk_wm_values
*results
)
3445 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
3449 dirty
= ilk_compute_wm_dirty(dev_priv
, previous
, results
);
3453 _ilk_disable_lp_wm(dev_priv
, dirty
);
3455 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
3456 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
3457 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
3458 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
3459 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
3460 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
3462 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
3463 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
3464 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
3465 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
3466 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
3467 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
3469 if (dirty
& WM_DIRTY_DDB
) {
3470 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3471 val
= I915_READ(WM_MISC
);
3472 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
3473 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
3475 val
|= WM_MISC_DATA_PARTITION_5_6
;
3476 I915_WRITE(WM_MISC
, val
);
3478 val
= I915_READ(DISP_ARB_CTL2
);
3479 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
3480 val
&= ~DISP_DATA_PARTITION_5_6
;
3482 val
|= DISP_DATA_PARTITION_5_6
;
3483 I915_WRITE(DISP_ARB_CTL2
, val
);
3487 if (dirty
& WM_DIRTY_FBC
) {
3488 val
= I915_READ(DISP_ARB_CTL
);
3489 if (results
->enable_fbc_wm
)
3490 val
&= ~DISP_FBC_WM_DIS
;
3492 val
|= DISP_FBC_WM_DIS
;
3493 I915_WRITE(DISP_ARB_CTL
, val
);
3496 if (dirty
& WM_DIRTY_LP(1) &&
3497 previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
3498 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
3500 if (INTEL_GEN(dev_priv
) >= 7) {
3501 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
3502 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
3503 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
3504 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
3507 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != results
->wm_lp
[0])
3508 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
3509 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != results
->wm_lp
[1])
3510 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
3511 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != results
->wm_lp
[2])
3512 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
3514 dev_priv
->wm
.hw
= *results
;
3517 bool ilk_disable_lp_wm(struct drm_device
*dev
)
3519 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3521 return _ilk_disable_lp_wm(dev_priv
, WM_DIRTY_LP_ALL
);
3524 #define SKL_SAGV_BLOCK_TIME 30 /* µs */
3527 * FIXME: We still don't have the proper code detect if we need to apply the WA,
3528 * so assume we'll always need it in order to avoid underruns.
3530 static bool skl_needs_memory_bw_wa(struct intel_atomic_state
*state
)
3532 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
3534 if (IS_GEN9_BC(dev_priv
) || IS_BROXTON(dev_priv
))
3541 intel_has_sagv(struct drm_i915_private
*dev_priv
)
3543 if (IS_KABYLAKE(dev_priv
) || IS_COFFEELAKE(dev_priv
))
3546 if (IS_SKYLAKE(dev_priv
) &&
3547 dev_priv
->sagv_status
!= I915_SAGV_NOT_CONTROLLED
)
3554 * SAGV dynamically adjusts the system agent voltage and clock frequencies
3555 * depending on power and performance requirements. The display engine access
3556 * to system memory is blocked during the adjustment time. Because of the
3557 * blocking time, having this enabled can cause full system hangs and/or pipe
3558 * underruns if we don't meet all of the following requirements:
3560 * - <= 1 pipe enabled
3561 * - All planes can enable watermarks for latencies >= SAGV engine block time
3562 * - We're not using an interlaced display configuration
3565 intel_enable_sagv(struct drm_i915_private
*dev_priv
)
3569 if (!intel_has_sagv(dev_priv
))
3572 if (dev_priv
->sagv_status
== I915_SAGV_ENABLED
)
3575 DRM_DEBUG_KMS("Enabling the SAGV\n");
3576 mutex_lock(&dev_priv
->rps
.hw_lock
);
3578 ret
= sandybridge_pcode_write(dev_priv
, GEN9_PCODE_SAGV_CONTROL
,
3581 /* We don't need to wait for the SAGV when enabling */
3582 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3585 * Some skl systems, pre-release machines in particular,
3586 * don't actually have an SAGV.
3588 if (IS_SKYLAKE(dev_priv
) && ret
== -ENXIO
) {
3589 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3590 dev_priv
->sagv_status
= I915_SAGV_NOT_CONTROLLED
;
3592 } else if (ret
< 0) {
3593 DRM_ERROR("Failed to enable the SAGV\n");
3597 dev_priv
->sagv_status
= I915_SAGV_ENABLED
;
3602 intel_disable_sagv(struct drm_i915_private
*dev_priv
)
3606 if (!intel_has_sagv(dev_priv
))
3609 if (dev_priv
->sagv_status
== I915_SAGV_DISABLED
)
3612 DRM_DEBUG_KMS("Disabling the SAGV\n");
3613 mutex_lock(&dev_priv
->rps
.hw_lock
);
3615 /* bspec says to keep retrying for at least 1 ms */
3616 ret
= skl_pcode_request(dev_priv
, GEN9_PCODE_SAGV_CONTROL
,
3618 GEN9_SAGV_IS_DISABLED
, GEN9_SAGV_IS_DISABLED
,
3620 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3623 * Some skl systems, pre-release machines in particular,
3624 * don't actually have an SAGV.
3626 if (IS_SKYLAKE(dev_priv
) && ret
== -ENXIO
) {
3627 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3628 dev_priv
->sagv_status
= I915_SAGV_NOT_CONTROLLED
;
3630 } else if (ret
< 0) {
3631 DRM_ERROR("Failed to disable the SAGV (%d)\n", ret
);
3635 dev_priv
->sagv_status
= I915_SAGV_DISABLED
;
3639 bool intel_can_enable_sagv(struct drm_atomic_state
*state
)
3641 struct drm_device
*dev
= state
->dev
;
3642 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3643 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
3644 struct intel_crtc
*crtc
;
3645 struct intel_plane
*plane
;
3646 struct intel_crtc_state
*cstate
;
3650 if (!intel_has_sagv(dev_priv
))
3654 * SKL workaround: bspec recommends we disable the SAGV when we have
3655 * more then one pipe enabled
3657 * If there are no active CRTCs, no additional checks need be performed
3659 if (hweight32(intel_state
->active_crtcs
) == 0)
3661 else if (hweight32(intel_state
->active_crtcs
) > 1)
3664 /* Since we're now guaranteed to only have one active CRTC... */
3665 pipe
= ffs(intel_state
->active_crtcs
) - 1;
3666 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
3667 cstate
= to_intel_crtc_state(crtc
->base
.state
);
3669 if (crtc
->base
.state
->adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
3672 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
3673 struct skl_plane_wm
*wm
=
3674 &cstate
->wm
.skl
.optimal
.planes
[plane
->id
];
3676 /* Skip this plane if it's not enabled */
3677 if (!wm
->wm
[0].plane_en
)
3680 /* Find the highest enabled wm level for this plane */
3681 for (level
= ilk_wm_max_level(dev_priv
);
3682 !wm
->wm
[level
].plane_en
; --level
)
3685 latency
= dev_priv
->wm
.skl_latency
[level
];
3687 if (skl_needs_memory_bw_wa(intel_state
) &&
3688 plane
->base
.state
->fb
->modifier
==
3689 I915_FORMAT_MOD_X_TILED
)
3693 * If any of the planes on this pipe don't enable wm levels
3694 * that incur memory latencies higher then 30µs we can't enable
3697 if (latency
< SKL_SAGV_BLOCK_TIME
)
3705 skl_ddb_get_pipe_allocation_limits(struct drm_device
*dev
,
3706 const struct intel_crtc_state
*cstate
,
3707 struct skl_ddb_entry
*alloc
, /* out */
3708 int *num_active
/* out */)
3710 struct drm_atomic_state
*state
= cstate
->base
.state
;
3711 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
3712 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3713 struct drm_crtc
*for_crtc
= cstate
->base
.crtc
;
3714 unsigned int pipe_size
, ddb_size
;
3715 int nth_active_pipe
;
3717 if (WARN_ON(!state
) || !cstate
->base
.active
) {
3720 *num_active
= hweight32(dev_priv
->active_crtcs
);
3724 if (intel_state
->active_pipe_changes
)
3725 *num_active
= hweight32(intel_state
->active_crtcs
);
3727 *num_active
= hweight32(dev_priv
->active_crtcs
);
3729 ddb_size
= INTEL_INFO(dev_priv
)->ddb_size
;
3730 WARN_ON(ddb_size
== 0);
3732 ddb_size
-= 4; /* 4 blocks for bypass path allocation */
3735 * If the state doesn't change the active CRTC's, then there's
3736 * no need to recalculate; the existing pipe allocation limits
3737 * should remain unchanged. Note that we're safe from racing
3738 * commits since any racing commit that changes the active CRTC
3739 * list would need to grab _all_ crtc locks, including the one
3740 * we currently hold.
3742 if (!intel_state
->active_pipe_changes
) {
3744 * alloc may be cleared by clear_intel_crtc_state,
3745 * copy from old state to be sure
3747 *alloc
= to_intel_crtc_state(for_crtc
->state
)->wm
.skl
.ddb
;
3751 nth_active_pipe
= hweight32(intel_state
->active_crtcs
&
3752 (drm_crtc_mask(for_crtc
) - 1));
3753 pipe_size
= ddb_size
/ hweight32(intel_state
->active_crtcs
);
3754 alloc
->start
= nth_active_pipe
* ddb_size
/ *num_active
;
3755 alloc
->end
= alloc
->start
+ pipe_size
;
3758 static unsigned int skl_cursor_allocation(int num_active
)
3760 if (num_active
== 1)
3766 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry
*entry
, u32 reg
)
3768 entry
->start
= reg
& 0x3ff;
3769 entry
->end
= (reg
>> 16) & 0x3ff;
3774 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
3775 struct skl_ddb_allocation
*ddb
/* out */)
3777 struct intel_crtc
*crtc
;
3779 memset(ddb
, 0, sizeof(*ddb
));
3781 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
3782 enum intel_display_power_domain power_domain
;
3783 enum plane_id plane_id
;
3784 enum pipe pipe
= crtc
->pipe
;
3786 power_domain
= POWER_DOMAIN_PIPE(pipe
);
3787 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
3790 for_each_plane_id_on_crtc(crtc
, plane_id
) {
3793 if (plane_id
!= PLANE_CURSOR
)
3794 val
= I915_READ(PLANE_BUF_CFG(pipe
, plane_id
));
3796 val
= I915_READ(CUR_BUF_CFG(pipe
));
3798 skl_ddb_entry_init_from_hw(&ddb
->plane
[pipe
][plane_id
], val
);
3801 intel_display_power_put(dev_priv
, power_domain
);
3806 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3807 * The bspec defines downscale amount as:
3810 * Horizontal down scale amount = maximum[1, Horizontal source size /
3811 * Horizontal destination size]
3812 * Vertical down scale amount = maximum[1, Vertical source size /
3813 * Vertical destination size]
3814 * Total down scale amount = Horizontal down scale amount *
3815 * Vertical down scale amount
3818 * Return value is provided in 16.16 fixed point form to retain fractional part.
3819 * Caller should take care of dividing & rounding off the value.
3821 static uint_fixed_16_16_t
3822 skl_plane_downscale_amount(const struct intel_crtc_state
*cstate
,
3823 const struct intel_plane_state
*pstate
)
3825 struct intel_plane
*plane
= to_intel_plane(pstate
->base
.plane
);
3826 uint32_t src_w
, src_h
, dst_w
, dst_h
;
3827 uint_fixed_16_16_t fp_w_ratio
, fp_h_ratio
;
3828 uint_fixed_16_16_t downscale_h
, downscale_w
;
3830 if (WARN_ON(!intel_wm_plane_visible(cstate
, pstate
)))
3831 return u32_to_fixed_16_16(0);
3833 /* n.b., src is 16.16 fixed point, dst is whole integer */
3834 if (plane
->id
== PLANE_CURSOR
) {
3836 * Cursors only support 0/180 degree rotation,
3837 * hence no need to account for rotation here.
3839 src_w
= pstate
->base
.src_w
>> 16;
3840 src_h
= pstate
->base
.src_h
>> 16;
3841 dst_w
= pstate
->base
.crtc_w
;
3842 dst_h
= pstate
->base
.crtc_h
;
3845 * Src coordinates are already rotated by 270 degrees for
3846 * the 90/270 degree plane rotation cases (to match the
3847 * GTT mapping), hence no need to account for rotation here.
3849 src_w
= drm_rect_width(&pstate
->base
.src
) >> 16;
3850 src_h
= drm_rect_height(&pstate
->base
.src
) >> 16;
3851 dst_w
= drm_rect_width(&pstate
->base
.dst
);
3852 dst_h
= drm_rect_height(&pstate
->base
.dst
);
3855 fp_w_ratio
= fixed_16_16_div(src_w
, dst_w
);
3856 fp_h_ratio
= fixed_16_16_div(src_h
, dst_h
);
3857 downscale_w
= max_fixed_16_16(fp_w_ratio
, u32_to_fixed_16_16(1));
3858 downscale_h
= max_fixed_16_16(fp_h_ratio
, u32_to_fixed_16_16(1));
3860 return mul_fixed16(downscale_w
, downscale_h
);
3863 static uint_fixed_16_16_t
3864 skl_pipe_downscale_amount(const struct intel_crtc_state
*crtc_state
)
3866 uint_fixed_16_16_t pipe_downscale
= u32_to_fixed_16_16(1);
3868 if (!crtc_state
->base
.enable
)
3869 return pipe_downscale
;
3871 if (crtc_state
->pch_pfit
.enabled
) {
3872 uint32_t src_w
, src_h
, dst_w
, dst_h
;
3873 uint32_t pfit_size
= crtc_state
->pch_pfit
.size
;
3874 uint_fixed_16_16_t fp_w_ratio
, fp_h_ratio
;
3875 uint_fixed_16_16_t downscale_h
, downscale_w
;
3877 src_w
= crtc_state
->pipe_src_w
;
3878 src_h
= crtc_state
->pipe_src_h
;
3879 dst_w
= pfit_size
>> 16;
3880 dst_h
= pfit_size
& 0xffff;
3882 if (!dst_w
|| !dst_h
)
3883 return pipe_downscale
;
3885 fp_w_ratio
= fixed_16_16_div(src_w
, dst_w
);
3886 fp_h_ratio
= fixed_16_16_div(src_h
, dst_h
);
3887 downscale_w
= max_fixed_16_16(fp_w_ratio
, u32_to_fixed_16_16(1));
3888 downscale_h
= max_fixed_16_16(fp_h_ratio
, u32_to_fixed_16_16(1));
3890 pipe_downscale
= mul_fixed16(downscale_w
, downscale_h
);
3893 return pipe_downscale
;
3896 int skl_check_pipe_max_pixel_rate(struct intel_crtc
*intel_crtc
,
3897 struct intel_crtc_state
*cstate
)
3899 struct drm_crtc_state
*crtc_state
= &cstate
->base
;
3900 struct drm_atomic_state
*state
= crtc_state
->state
;
3901 struct drm_plane
*plane
;
3902 const struct drm_plane_state
*pstate
;
3903 struct intel_plane_state
*intel_pstate
;
3904 int crtc_clock
, dotclk
;
3905 uint32_t pipe_max_pixel_rate
;
3906 uint_fixed_16_16_t pipe_downscale
;
3907 uint_fixed_16_16_t max_downscale
= u32_to_fixed_16_16(1);
3909 if (!cstate
->base
.enable
)
3912 drm_atomic_crtc_state_for_each_plane_state(plane
, pstate
, crtc_state
) {
3913 uint_fixed_16_16_t plane_downscale
;
3914 uint_fixed_16_16_t fp_9_div_8
= fixed_16_16_div(9, 8);
3917 if (!intel_wm_plane_visible(cstate
,
3918 to_intel_plane_state(pstate
)))
3921 if (WARN_ON(!pstate
->fb
))
3924 intel_pstate
= to_intel_plane_state(pstate
);
3925 plane_downscale
= skl_plane_downscale_amount(cstate
,
3927 bpp
= pstate
->fb
->format
->cpp
[0] * 8;
3929 plane_downscale
= mul_fixed16(plane_downscale
,
3932 max_downscale
= max_fixed_16_16(plane_downscale
, max_downscale
);
3934 pipe_downscale
= skl_pipe_downscale_amount(cstate
);
3936 pipe_downscale
= mul_fixed16(pipe_downscale
, max_downscale
);
3938 crtc_clock
= crtc_state
->adjusted_mode
.crtc_clock
;
3939 dotclk
= to_intel_atomic_state(state
)->cdclk
.logical
.cdclk
;
3941 if (IS_GEMINILAKE(to_i915(intel_crtc
->base
.dev
)))
3944 pipe_max_pixel_rate
= div_round_up_u32_fixed16(dotclk
, pipe_downscale
);
3946 if (pipe_max_pixel_rate
< crtc_clock
) {
3947 DRM_DEBUG_KMS("Max supported pixel clock with scaling exceeded\n");
3955 skl_plane_relative_data_rate(const struct intel_crtc_state
*cstate
,
3956 const struct drm_plane_state
*pstate
,
3959 struct intel_plane
*plane
= to_intel_plane(pstate
->plane
);
3960 struct intel_plane_state
*intel_pstate
= to_intel_plane_state(pstate
);
3962 uint32_t width
= 0, height
= 0;
3963 struct drm_framebuffer
*fb
;
3965 uint_fixed_16_16_t down_scale_amount
;
3967 if (!intel_pstate
->base
.visible
)
3971 format
= fb
->format
->format
;
3973 if (plane
->id
== PLANE_CURSOR
)
3975 if (y
&& format
!= DRM_FORMAT_NV12
)
3979 * Src coordinates are already rotated by 270 degrees for
3980 * the 90/270 degree plane rotation cases (to match the
3981 * GTT mapping), hence no need to account for rotation here.
3983 width
= drm_rect_width(&intel_pstate
->base
.src
) >> 16;
3984 height
= drm_rect_height(&intel_pstate
->base
.src
) >> 16;
3986 /* for planar format */
3987 if (format
== DRM_FORMAT_NV12
) {
3988 if (y
) /* y-plane data rate */
3989 data_rate
= width
* height
*
3991 else /* uv-plane data rate */
3992 data_rate
= (width
/ 2) * (height
/ 2) *
3995 /* for packed formats */
3996 data_rate
= width
* height
* fb
->format
->cpp
[0];
3999 down_scale_amount
= skl_plane_downscale_amount(cstate
, intel_pstate
);
4001 return mul_round_up_u32_fixed16(data_rate
, down_scale_amount
);
4005 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
4006 * a 8192x4096@32bpp framebuffer:
4007 * 3 * 4096 * 8192 * 4 < 2^32
4010 skl_get_total_relative_data_rate(struct intel_crtc_state
*intel_cstate
,
4011 unsigned *plane_data_rate
,
4012 unsigned *plane_y_data_rate
)
4014 struct drm_crtc_state
*cstate
= &intel_cstate
->base
;
4015 struct drm_atomic_state
*state
= cstate
->state
;
4016 struct drm_plane
*plane
;
4017 const struct drm_plane_state
*pstate
;
4018 unsigned int total_data_rate
= 0;
4020 if (WARN_ON(!state
))
4023 /* Calculate and cache data rate for each plane */
4024 drm_atomic_crtc_state_for_each_plane_state(plane
, pstate
, cstate
) {
4025 enum plane_id plane_id
= to_intel_plane(plane
)->id
;
4029 rate
= skl_plane_relative_data_rate(intel_cstate
,
4031 plane_data_rate
[plane_id
] = rate
;
4033 total_data_rate
+= rate
;
4036 rate
= skl_plane_relative_data_rate(intel_cstate
,
4038 plane_y_data_rate
[plane_id
] = rate
;
4040 total_data_rate
+= rate
;
4043 return total_data_rate
;
4047 skl_ddb_min_alloc(const struct drm_plane_state
*pstate
,
4050 struct drm_framebuffer
*fb
= pstate
->fb
;
4051 struct intel_plane_state
*intel_pstate
= to_intel_plane_state(pstate
);
4052 uint32_t src_w
, src_h
;
4053 uint32_t min_scanlines
= 8;
4059 /* For packed formats, no y-plane, return 0 */
4060 if (y
&& fb
->format
->format
!= DRM_FORMAT_NV12
)
4063 /* For Non Y-tile return 8-blocks */
4064 if (fb
->modifier
!= I915_FORMAT_MOD_Y_TILED
&&
4065 fb
->modifier
!= I915_FORMAT_MOD_Yf_TILED
)
4069 * Src coordinates are already rotated by 270 degrees for
4070 * the 90/270 degree plane rotation cases (to match the
4071 * GTT mapping), hence no need to account for rotation here.
4073 src_w
= drm_rect_width(&intel_pstate
->base
.src
) >> 16;
4074 src_h
= drm_rect_height(&intel_pstate
->base
.src
) >> 16;
4076 /* Halve UV plane width and height for NV12 */
4077 if (fb
->format
->format
== DRM_FORMAT_NV12
&& !y
) {
4082 if (fb
->format
->format
== DRM_FORMAT_NV12
&& !y
)
4083 plane_bpp
= fb
->format
->cpp
[1];
4085 plane_bpp
= fb
->format
->cpp
[0];
4087 if (drm_rotation_90_or_270(pstate
->rotation
)) {
4088 switch (plane_bpp
) {
4102 WARN(1, "Unsupported pixel depth %u for rotation",
4108 return DIV_ROUND_UP((4 * src_w
* plane_bpp
), 512) * min_scanlines
/4 + 3;
4112 skl_ddb_calc_min(const struct intel_crtc_state
*cstate
, int num_active
,
4113 uint16_t *minimum
, uint16_t *y_minimum
)
4115 const struct drm_plane_state
*pstate
;
4116 struct drm_plane
*plane
;
4118 drm_atomic_crtc_state_for_each_plane_state(plane
, pstate
, &cstate
->base
) {
4119 enum plane_id plane_id
= to_intel_plane(plane
)->id
;
4121 if (plane_id
== PLANE_CURSOR
)
4124 if (!pstate
->visible
)
4127 minimum
[plane_id
] = skl_ddb_min_alloc(pstate
, 0);
4128 y_minimum
[plane_id
] = skl_ddb_min_alloc(pstate
, 1);
4131 minimum
[PLANE_CURSOR
] = skl_cursor_allocation(num_active
);
4135 skl_allocate_pipe_ddb(struct intel_crtc_state
*cstate
,
4136 struct skl_ddb_allocation
*ddb
/* out */)
4138 struct drm_atomic_state
*state
= cstate
->base
.state
;
4139 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
4140 struct drm_device
*dev
= crtc
->dev
;
4141 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4142 enum pipe pipe
= intel_crtc
->pipe
;
4143 struct skl_ddb_entry
*alloc
= &cstate
->wm
.skl
.ddb
;
4144 uint16_t alloc_size
, start
;
4145 uint16_t minimum
[I915_MAX_PLANES
] = {};
4146 uint16_t y_minimum
[I915_MAX_PLANES
] = {};
4147 unsigned int total_data_rate
;
4148 enum plane_id plane_id
;
4150 unsigned plane_data_rate
[I915_MAX_PLANES
] = {};
4151 unsigned plane_y_data_rate
[I915_MAX_PLANES
] = {};
4152 uint16_t total_min_blocks
= 0;
4154 /* Clear the partitioning for disabled planes. */
4155 memset(ddb
->plane
[pipe
], 0, sizeof(ddb
->plane
[pipe
]));
4156 memset(ddb
->y_plane
[pipe
], 0, sizeof(ddb
->y_plane
[pipe
]));
4158 if (WARN_ON(!state
))
4161 if (!cstate
->base
.active
) {
4162 alloc
->start
= alloc
->end
= 0;
4166 skl_ddb_get_pipe_allocation_limits(dev
, cstate
, alloc
, &num_active
);
4167 alloc_size
= skl_ddb_entry_size(alloc
);
4168 if (alloc_size
== 0)
4171 skl_ddb_calc_min(cstate
, num_active
, minimum
, y_minimum
);
4174 * 1. Allocate the mininum required blocks for each active plane
4175 * and allocate the cursor, it doesn't require extra allocation
4176 * proportional to the data rate.
4179 for_each_plane_id_on_crtc(intel_crtc
, plane_id
) {
4180 total_min_blocks
+= minimum
[plane_id
];
4181 total_min_blocks
+= y_minimum
[plane_id
];
4184 if (total_min_blocks
> alloc_size
) {
4185 DRM_DEBUG_KMS("Requested display configuration exceeds system DDB limitations");
4186 DRM_DEBUG_KMS("minimum required %d/%d\n", total_min_blocks
,
4191 alloc_size
-= total_min_blocks
;
4192 ddb
->plane
[pipe
][PLANE_CURSOR
].start
= alloc
->end
- minimum
[PLANE_CURSOR
];
4193 ddb
->plane
[pipe
][PLANE_CURSOR
].end
= alloc
->end
;
4196 * 2. Distribute the remaining space in proportion to the amount of
4197 * data each plane needs to fetch from memory.
4199 * FIXME: we may not allocate every single block here.
4201 total_data_rate
= skl_get_total_relative_data_rate(cstate
,
4204 if (total_data_rate
== 0)
4207 start
= alloc
->start
;
4208 for_each_plane_id_on_crtc(intel_crtc
, plane_id
) {
4209 unsigned int data_rate
, y_data_rate
;
4210 uint16_t plane_blocks
, y_plane_blocks
= 0;
4212 if (plane_id
== PLANE_CURSOR
)
4215 data_rate
= plane_data_rate
[plane_id
];
4218 * allocation for (packed formats) or (uv-plane part of planar format):
4219 * promote the expression to 64 bits to avoid overflowing, the
4220 * result is < available as data_rate / total_data_rate < 1
4222 plane_blocks
= minimum
[plane_id
];
4223 plane_blocks
+= div_u64((uint64_t)alloc_size
* data_rate
,
4226 /* Leave disabled planes at (0,0) */
4228 ddb
->plane
[pipe
][plane_id
].start
= start
;
4229 ddb
->plane
[pipe
][plane_id
].end
= start
+ plane_blocks
;
4232 start
+= plane_blocks
;
4235 * allocation for y_plane part of planar format:
4237 y_data_rate
= plane_y_data_rate
[plane_id
];
4239 y_plane_blocks
= y_minimum
[plane_id
];
4240 y_plane_blocks
+= div_u64((uint64_t)alloc_size
* y_data_rate
,
4244 ddb
->y_plane
[pipe
][plane_id
].start
= start
;
4245 ddb
->y_plane
[pipe
][plane_id
].end
= start
+ y_plane_blocks
;
4248 start
+= y_plane_blocks
;
4255 * The max latency should be 257 (max the punit can code is 255 and we add 2us
4256 * for the read latency) and cpp should always be <= 8, so that
4257 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
4258 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
4260 static uint_fixed_16_16_t
skl_wm_method1(uint32_t pixel_rate
, uint8_t cpp
,
4263 uint32_t wm_intermediate_val
;
4264 uint_fixed_16_16_t ret
;
4267 return FP_16_16_MAX
;
4269 wm_intermediate_val
= latency
* pixel_rate
* cpp
;
4270 ret
= fixed_16_16_div_u64(wm_intermediate_val
, 1000 * 512);
4274 static uint_fixed_16_16_t
skl_wm_method2(uint32_t pixel_rate
,
4275 uint32_t pipe_htotal
,
4277 uint_fixed_16_16_t plane_blocks_per_line
)
4279 uint32_t wm_intermediate_val
;
4280 uint_fixed_16_16_t ret
;
4283 return FP_16_16_MAX
;
4285 wm_intermediate_val
= latency
* pixel_rate
;
4286 wm_intermediate_val
= DIV_ROUND_UP(wm_intermediate_val
,
4287 pipe_htotal
* 1000);
4288 ret
= mul_u32_fixed_16_16(wm_intermediate_val
, plane_blocks_per_line
);
4292 static uint_fixed_16_16_t
4293 intel_get_linetime_us(struct intel_crtc_state
*cstate
)
4295 uint32_t pixel_rate
;
4296 uint32_t crtc_htotal
;
4297 uint_fixed_16_16_t linetime_us
;
4299 if (!cstate
->base
.active
)
4300 return u32_to_fixed_16_16(0);
4302 pixel_rate
= cstate
->pixel_rate
;
4304 if (WARN_ON(pixel_rate
== 0))
4305 return u32_to_fixed_16_16(0);
4307 crtc_htotal
= cstate
->base
.adjusted_mode
.crtc_htotal
;
4308 linetime_us
= fixed_16_16_div_u64(crtc_htotal
* 1000, pixel_rate
);
4314 skl_adjusted_plane_pixel_rate(const struct intel_crtc_state
*cstate
,
4315 const struct intel_plane_state
*pstate
)
4317 uint64_t adjusted_pixel_rate
;
4318 uint_fixed_16_16_t downscale_amount
;
4320 /* Shouldn't reach here on disabled planes... */
4321 if (WARN_ON(!intel_wm_plane_visible(cstate
, pstate
)))
4325 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
4326 * with additional adjustments for plane-specific scaling.
4328 adjusted_pixel_rate
= cstate
->pixel_rate
;
4329 downscale_amount
= skl_plane_downscale_amount(cstate
, pstate
);
4331 return mul_round_up_u32_fixed16(adjusted_pixel_rate
,
4335 static int skl_compute_plane_wm(const struct drm_i915_private
*dev_priv
,
4336 struct intel_crtc_state
*cstate
,
4337 const struct intel_plane_state
*intel_pstate
,
4338 uint16_t ddb_allocation
,
4340 uint16_t *out_blocks
, /* out */
4341 uint8_t *out_lines
, /* out */
4342 bool *enabled
/* out */)
4344 struct intel_plane
*plane
= to_intel_plane(intel_pstate
->base
.plane
);
4345 const struct drm_plane_state
*pstate
= &intel_pstate
->base
;
4346 const struct drm_framebuffer
*fb
= pstate
->fb
;
4347 uint32_t latency
= dev_priv
->wm
.skl_latency
[level
];
4348 uint_fixed_16_16_t method1
, method2
;
4349 uint_fixed_16_16_t plane_blocks_per_line
;
4350 uint_fixed_16_16_t selected_result
;
4351 uint32_t interm_pbpl
;
4352 uint32_t plane_bytes_per_line
;
4353 uint32_t res_blocks
, res_lines
;
4355 uint32_t width
= 0, height
= 0;
4356 uint32_t plane_pixel_rate
;
4357 uint_fixed_16_16_t y_tile_minimum
;
4358 uint32_t y_min_scanlines
;
4359 struct intel_atomic_state
*state
=
4360 to_intel_atomic_state(cstate
->base
.state
);
4361 bool apply_memory_bw_wa
= skl_needs_memory_bw_wa(state
);
4362 bool y_tiled
, x_tiled
;
4365 !intel_wm_plane_visible(cstate
, intel_pstate
)) {
4370 y_tiled
= fb
->modifier
== I915_FORMAT_MOD_Y_TILED
||
4371 fb
->modifier
== I915_FORMAT_MOD_Yf_TILED
;
4372 x_tiled
= fb
->modifier
== I915_FORMAT_MOD_X_TILED
;
4374 /* Display WA #1141: kbl,cfl */
4375 if ((IS_KABYLAKE(dev_priv
) || IS_COFFEELAKE(dev_priv
)) &&
4376 dev_priv
->ipc_enabled
)
4379 if (apply_memory_bw_wa
&& x_tiled
)
4382 if (plane
->id
== PLANE_CURSOR
) {
4383 width
= intel_pstate
->base
.crtc_w
;
4384 height
= intel_pstate
->base
.crtc_h
;
4387 * Src coordinates are already rotated by 270 degrees for
4388 * the 90/270 degree plane rotation cases (to match the
4389 * GTT mapping), hence no need to account for rotation here.
4391 width
= drm_rect_width(&intel_pstate
->base
.src
) >> 16;
4392 height
= drm_rect_height(&intel_pstate
->base
.src
) >> 16;
4395 cpp
= fb
->format
->cpp
[0];
4396 plane_pixel_rate
= skl_adjusted_plane_pixel_rate(cstate
, intel_pstate
);
4398 if (drm_rotation_90_or_270(pstate
->rotation
)) {
4399 int cpp
= (fb
->format
->format
== DRM_FORMAT_NV12
) ?
4400 fb
->format
->cpp
[1] :
4405 y_min_scanlines
= 16;
4408 y_min_scanlines
= 8;
4411 y_min_scanlines
= 4;
4418 y_min_scanlines
= 4;
4421 if (apply_memory_bw_wa
)
4422 y_min_scanlines
*= 2;
4424 plane_bytes_per_line
= width
* cpp
;
4426 interm_pbpl
= DIV_ROUND_UP(plane_bytes_per_line
*
4427 y_min_scanlines
, 512);
4428 plane_blocks_per_line
= fixed_16_16_div(interm_pbpl
,
4430 } else if (x_tiled
) {
4431 interm_pbpl
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
4432 plane_blocks_per_line
= u32_to_fixed_16_16(interm_pbpl
);
4434 interm_pbpl
= DIV_ROUND_UP(plane_bytes_per_line
, 512) + 1;
4435 plane_blocks_per_line
= u32_to_fixed_16_16(interm_pbpl
);
4438 method1
= skl_wm_method1(plane_pixel_rate
, cpp
, latency
);
4439 method2
= skl_wm_method2(plane_pixel_rate
,
4440 cstate
->base
.adjusted_mode
.crtc_htotal
,
4442 plane_blocks_per_line
);
4444 y_tile_minimum
= mul_u32_fixed_16_16(y_min_scanlines
,
4445 plane_blocks_per_line
);
4448 selected_result
= max_fixed_16_16(method2
, y_tile_minimum
);
4450 uint32_t linetime_us
;
4452 linetime_us
= fixed_16_16_to_u32_round_up(
4453 intel_get_linetime_us(cstate
));
4454 if ((cpp
* cstate
->base
.adjusted_mode
.crtc_htotal
/ 512 < 1) &&
4455 (plane_bytes_per_line
/ 512 < 1))
4456 selected_result
= method2
;
4457 else if (ddb_allocation
>=
4458 fixed_16_16_to_u32_round_up(plane_blocks_per_line
))
4459 selected_result
= min_fixed_16_16(method1
, method2
);
4460 else if (latency
>= linetime_us
)
4461 selected_result
= min_fixed_16_16(method1
, method2
);
4463 selected_result
= method1
;
4466 res_blocks
= fixed_16_16_to_u32_round_up(selected_result
) + 1;
4467 res_lines
= div_round_up_fixed16(selected_result
,
4468 plane_blocks_per_line
);
4470 if (level
>= 1 && level
<= 7) {
4472 res_blocks
+= fixed_16_16_to_u32_round_up(y_tile_minimum
);
4473 res_lines
+= y_min_scanlines
;
4479 if (res_blocks
>= ddb_allocation
|| res_lines
> 31) {
4483 * If there are no valid level 0 watermarks, then we can't
4484 * support this display configuration.
4489 struct drm_plane
*plane
= pstate
->plane
;
4491 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
4492 DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n",
4493 plane
->base
.id
, plane
->name
,
4494 res_blocks
, ddb_allocation
, res_lines
);
4499 *out_blocks
= res_blocks
;
4500 *out_lines
= res_lines
;
4507 skl_compute_wm_levels(const struct drm_i915_private
*dev_priv
,
4508 struct skl_ddb_allocation
*ddb
,
4509 struct intel_crtc_state
*cstate
,
4510 const struct intel_plane_state
*intel_pstate
,
4511 struct skl_plane_wm
*wm
)
4513 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
4514 struct drm_plane
*plane
= intel_pstate
->base
.plane
;
4515 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
4516 uint16_t ddb_blocks
;
4517 enum pipe pipe
= intel_crtc
->pipe
;
4518 int level
, max_level
= ilk_wm_max_level(dev_priv
);
4521 if (WARN_ON(!intel_pstate
->base
.fb
))
4524 ddb_blocks
= skl_ddb_entry_size(&ddb
->plane
[pipe
][intel_plane
->id
]);
4526 for (level
= 0; level
<= max_level
; level
++) {
4527 struct skl_wm_level
*result
= &wm
->wm
[level
];
4529 ret
= skl_compute_plane_wm(dev_priv
,
4534 &result
->plane_res_b
,
4535 &result
->plane_res_l
,
4545 skl_compute_linetime_wm(struct intel_crtc_state
*cstate
)
4547 struct drm_atomic_state
*state
= cstate
->base
.state
;
4548 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
4549 uint_fixed_16_16_t linetime_us
;
4550 uint32_t linetime_wm
;
4552 linetime_us
= intel_get_linetime_us(cstate
);
4554 if (is_fixed16_zero(linetime_us
))
4557 linetime_wm
= fixed_16_16_to_u32_round_up(mul_u32_fixed_16_16(8,
4560 /* Display WA #1135: bxt. */
4561 if (IS_BROXTON(dev_priv
) && dev_priv
->ipc_enabled
)
4562 linetime_wm
= DIV_ROUND_UP(linetime_wm
, 2);
4567 static void skl_compute_transition_wm(struct intel_crtc_state
*cstate
,
4568 struct skl_wm_level
*trans_wm
/* out */)
4570 if (!cstate
->base
.active
)
4573 /* Until we know more, just disable transition WMs */
4574 trans_wm
->plane_en
= false;
4577 static int skl_build_pipe_wm(struct intel_crtc_state
*cstate
,
4578 struct skl_ddb_allocation
*ddb
,
4579 struct skl_pipe_wm
*pipe_wm
)
4581 struct drm_device
*dev
= cstate
->base
.crtc
->dev
;
4582 struct drm_crtc_state
*crtc_state
= &cstate
->base
;
4583 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
4584 struct drm_plane
*plane
;
4585 const struct drm_plane_state
*pstate
;
4586 struct skl_plane_wm
*wm
;
4590 * We'll only calculate watermarks for planes that are actually
4591 * enabled, so make sure all other planes are set as disabled.
4593 memset(pipe_wm
->planes
, 0, sizeof(pipe_wm
->planes
));
4595 drm_atomic_crtc_state_for_each_plane_state(plane
, pstate
, crtc_state
) {
4596 const struct intel_plane_state
*intel_pstate
=
4597 to_intel_plane_state(pstate
);
4598 enum plane_id plane_id
= to_intel_plane(plane
)->id
;
4600 wm
= &pipe_wm
->planes
[plane_id
];
4602 ret
= skl_compute_wm_levels(dev_priv
, ddb
, cstate
,
4606 skl_compute_transition_wm(cstate
, &wm
->trans_wm
);
4608 pipe_wm
->linetime
= skl_compute_linetime_wm(cstate
);
4613 static void skl_ddb_entry_write(struct drm_i915_private
*dev_priv
,
4615 const struct skl_ddb_entry
*entry
)
4618 I915_WRITE(reg
, (entry
->end
- 1) << 16 | entry
->start
);
4623 static void skl_write_wm_level(struct drm_i915_private
*dev_priv
,
4625 const struct skl_wm_level
*level
)
4629 if (level
->plane_en
) {
4631 val
|= level
->plane_res_b
;
4632 val
|= level
->plane_res_l
<< PLANE_WM_LINES_SHIFT
;
4635 I915_WRITE(reg
, val
);
4638 static void skl_write_plane_wm(struct intel_crtc
*intel_crtc
,
4639 const struct skl_plane_wm
*wm
,
4640 const struct skl_ddb_allocation
*ddb
,
4641 enum plane_id plane_id
)
4643 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4644 struct drm_device
*dev
= crtc
->dev
;
4645 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4646 int level
, max_level
= ilk_wm_max_level(dev_priv
);
4647 enum pipe pipe
= intel_crtc
->pipe
;
4649 for (level
= 0; level
<= max_level
; level
++) {
4650 skl_write_wm_level(dev_priv
, PLANE_WM(pipe
, plane_id
, level
),
4653 skl_write_wm_level(dev_priv
, PLANE_WM_TRANS(pipe
, plane_id
),
4656 skl_ddb_entry_write(dev_priv
, PLANE_BUF_CFG(pipe
, plane_id
),
4657 &ddb
->plane
[pipe
][plane_id
]);
4658 skl_ddb_entry_write(dev_priv
, PLANE_NV12_BUF_CFG(pipe
, plane_id
),
4659 &ddb
->y_plane
[pipe
][plane_id
]);
4662 static void skl_write_cursor_wm(struct intel_crtc
*intel_crtc
,
4663 const struct skl_plane_wm
*wm
,
4664 const struct skl_ddb_allocation
*ddb
)
4666 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4667 struct drm_device
*dev
= crtc
->dev
;
4668 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4669 int level
, max_level
= ilk_wm_max_level(dev_priv
);
4670 enum pipe pipe
= intel_crtc
->pipe
;
4672 for (level
= 0; level
<= max_level
; level
++) {
4673 skl_write_wm_level(dev_priv
, CUR_WM(pipe
, level
),
4676 skl_write_wm_level(dev_priv
, CUR_WM_TRANS(pipe
), &wm
->trans_wm
);
4678 skl_ddb_entry_write(dev_priv
, CUR_BUF_CFG(pipe
),
4679 &ddb
->plane
[pipe
][PLANE_CURSOR
]);
4682 bool skl_wm_level_equals(const struct skl_wm_level
*l1
,
4683 const struct skl_wm_level
*l2
)
4685 if (l1
->plane_en
!= l2
->plane_en
)
4688 /* If both planes aren't enabled, the rest shouldn't matter */
4692 return (l1
->plane_res_l
== l2
->plane_res_l
&&
4693 l1
->plane_res_b
== l2
->plane_res_b
);
4696 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry
*a
,
4697 const struct skl_ddb_entry
*b
)
4699 return a
->start
< b
->end
&& b
->start
< a
->end
;
4702 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry
**entries
,
4703 const struct skl_ddb_entry
*ddb
,
4708 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
4709 if (i
!= ignore
&& entries
[i
] &&
4710 skl_ddb_entries_overlap(ddb
, entries
[i
]))
4716 static int skl_update_pipe_wm(struct drm_crtc_state
*cstate
,
4717 const struct skl_pipe_wm
*old_pipe_wm
,
4718 struct skl_pipe_wm
*pipe_wm
, /* out */
4719 struct skl_ddb_allocation
*ddb
, /* out */
4720 bool *changed
/* out */)
4722 struct intel_crtc_state
*intel_cstate
= to_intel_crtc_state(cstate
);
4725 ret
= skl_build_pipe_wm(intel_cstate
, ddb
, pipe_wm
);
4729 if (!memcmp(old_pipe_wm
, pipe_wm
, sizeof(*pipe_wm
)))
4738 pipes_modified(struct drm_atomic_state
*state
)
4740 struct drm_crtc
*crtc
;
4741 struct drm_crtc_state
*cstate
;
4742 uint32_t i
, ret
= 0;
4744 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
)
4745 ret
|= drm_crtc_mask(crtc
);
4751 skl_ddb_add_affected_planes(struct intel_crtc_state
*cstate
)
4753 struct drm_atomic_state
*state
= cstate
->base
.state
;
4754 struct drm_device
*dev
= state
->dev
;
4755 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
4756 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4757 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4758 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
4759 struct skl_ddb_allocation
*new_ddb
= &intel_state
->wm_results
.ddb
;
4760 struct skl_ddb_allocation
*cur_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
4761 struct drm_plane_state
*plane_state
;
4762 struct drm_plane
*plane
;
4763 enum pipe pipe
= intel_crtc
->pipe
;
4765 WARN_ON(!drm_atomic_get_existing_crtc_state(state
, crtc
));
4767 drm_for_each_plane_mask(plane
, dev
, cstate
->base
.plane_mask
) {
4768 enum plane_id plane_id
= to_intel_plane(plane
)->id
;
4770 if (skl_ddb_entry_equal(&cur_ddb
->plane
[pipe
][plane_id
],
4771 &new_ddb
->plane
[pipe
][plane_id
]) &&
4772 skl_ddb_entry_equal(&cur_ddb
->y_plane
[pipe
][plane_id
],
4773 &new_ddb
->y_plane
[pipe
][plane_id
]))
4776 plane_state
= drm_atomic_get_plane_state(state
, plane
);
4777 if (IS_ERR(plane_state
))
4778 return PTR_ERR(plane_state
);
4785 skl_compute_ddb(struct drm_atomic_state
*state
)
4787 struct drm_device
*dev
= state
->dev
;
4788 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4789 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
4790 struct intel_crtc
*intel_crtc
;
4791 struct skl_ddb_allocation
*ddb
= &intel_state
->wm_results
.ddb
;
4792 uint32_t realloc_pipes
= pipes_modified(state
);
4796 * If this is our first atomic update following hardware readout,
4797 * we can't trust the DDB that the BIOS programmed for us. Let's
4798 * pretend that all pipes switched active status so that we'll
4799 * ensure a full DDB recompute.
4801 if (dev_priv
->wm
.distrust_bios_wm
) {
4802 ret
= drm_modeset_lock(&dev
->mode_config
.connection_mutex
,
4803 state
->acquire_ctx
);
4807 intel_state
->active_pipe_changes
= ~0;
4810 * We usually only initialize intel_state->active_crtcs if we
4811 * we're doing a modeset; make sure this field is always
4812 * initialized during the sanitization process that happens
4813 * on the first commit too.
4815 if (!intel_state
->modeset
)
4816 intel_state
->active_crtcs
= dev_priv
->active_crtcs
;
4820 * If the modeset changes which CRTC's are active, we need to
4821 * recompute the DDB allocation for *all* active pipes, even
4822 * those that weren't otherwise being modified in any way by this
4823 * atomic commit. Due to the shrinking of the per-pipe allocations
4824 * when new active CRTC's are added, it's possible for a pipe that
4825 * we were already using and aren't changing at all here to suddenly
4826 * become invalid if its DDB needs exceeds its new allocation.
4828 * Note that if we wind up doing a full DDB recompute, we can't let
4829 * any other display updates race with this transaction, so we need
4830 * to grab the lock on *all* CRTC's.
4832 if (intel_state
->active_pipe_changes
) {
4834 intel_state
->wm_results
.dirty_pipes
= ~0;
4838 * We're not recomputing for the pipes not included in the commit, so
4839 * make sure we start with the current state.
4841 memcpy(ddb
, &dev_priv
->wm
.skl_hw
.ddb
, sizeof(*ddb
));
4843 for_each_intel_crtc_mask(dev
, intel_crtc
, realloc_pipes
) {
4844 struct intel_crtc_state
*cstate
;
4846 cstate
= intel_atomic_get_crtc_state(state
, intel_crtc
);
4848 return PTR_ERR(cstate
);
4850 ret
= skl_allocate_pipe_ddb(cstate
, ddb
);
4854 ret
= skl_ddb_add_affected_planes(cstate
);
4863 skl_copy_wm_for_pipe(struct skl_wm_values
*dst
,
4864 struct skl_wm_values
*src
,
4867 memcpy(dst
->ddb
.y_plane
[pipe
], src
->ddb
.y_plane
[pipe
],
4868 sizeof(dst
->ddb
.y_plane
[pipe
]));
4869 memcpy(dst
->ddb
.plane
[pipe
], src
->ddb
.plane
[pipe
],
4870 sizeof(dst
->ddb
.plane
[pipe
]));
4874 skl_print_wm_changes(const struct drm_atomic_state
*state
)
4876 const struct drm_device
*dev
= state
->dev
;
4877 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
4878 const struct intel_atomic_state
*intel_state
=
4879 to_intel_atomic_state(state
);
4880 const struct drm_crtc
*crtc
;
4881 const struct drm_crtc_state
*cstate
;
4882 const struct intel_plane
*intel_plane
;
4883 const struct skl_ddb_allocation
*old_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
4884 const struct skl_ddb_allocation
*new_ddb
= &intel_state
->wm_results
.ddb
;
4887 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
) {
4888 const struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4889 enum pipe pipe
= intel_crtc
->pipe
;
4891 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
4892 enum plane_id plane_id
= intel_plane
->id
;
4893 const struct skl_ddb_entry
*old
, *new;
4895 old
= &old_ddb
->plane
[pipe
][plane_id
];
4896 new = &new_ddb
->plane
[pipe
][plane_id
];
4898 if (skl_ddb_entry_equal(old
, new))
4901 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4902 intel_plane
->base
.base
.id
,
4903 intel_plane
->base
.name
,
4904 old
->start
, old
->end
,
4905 new->start
, new->end
);
4911 skl_compute_wm(struct drm_atomic_state
*state
)
4913 struct drm_crtc
*crtc
;
4914 struct drm_crtc_state
*cstate
;
4915 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
4916 struct skl_wm_values
*results
= &intel_state
->wm_results
;
4917 struct drm_device
*dev
= state
->dev
;
4918 struct skl_pipe_wm
*pipe_wm
;
4919 bool changed
= false;
4923 * When we distrust bios wm we always need to recompute to set the
4924 * expected DDB allocations for each CRTC.
4926 if (to_i915(dev
)->wm
.distrust_bios_wm
)
4930 * If this transaction isn't actually touching any CRTC's, don't
4931 * bother with watermark calculation. Note that if we pass this
4932 * test, we're guaranteed to hold at least one CRTC state mutex,
4933 * which means we can safely use values like dev_priv->active_crtcs
4934 * since any racing commits that want to update them would need to
4935 * hold _all_ CRTC state mutexes.
4937 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
)
4943 /* Clear all dirty flags */
4944 results
->dirty_pipes
= 0;
4946 ret
= skl_compute_ddb(state
);
4951 * Calculate WM's for all pipes that are part of this transaction.
4952 * Note that the DDB allocation above may have added more CRTC's that
4953 * weren't otherwise being modified (and set bits in dirty_pipes) if
4954 * pipe allocations had to change.
4956 * FIXME: Now that we're doing this in the atomic check phase, we
4957 * should allow skl_update_pipe_wm() to return failure in cases where
4958 * no suitable watermark values can be found.
4960 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
) {
4961 struct intel_crtc_state
*intel_cstate
=
4962 to_intel_crtc_state(cstate
);
4963 const struct skl_pipe_wm
*old_pipe_wm
=
4964 &to_intel_crtc_state(crtc
->state
)->wm
.skl
.optimal
;
4966 pipe_wm
= &intel_cstate
->wm
.skl
.optimal
;
4967 ret
= skl_update_pipe_wm(cstate
, old_pipe_wm
, pipe_wm
,
4968 &results
->ddb
, &changed
);
4973 results
->dirty_pipes
|= drm_crtc_mask(crtc
);
4975 if ((results
->dirty_pipes
& drm_crtc_mask(crtc
)) == 0)
4976 /* This pipe's WM's did not change */
4979 intel_cstate
->update_wm_pre
= true;
4982 skl_print_wm_changes(state
);
4987 static void skl_atomic_update_crtc_wm(struct intel_atomic_state
*state
,
4988 struct intel_crtc_state
*cstate
)
4990 struct intel_crtc
*crtc
= to_intel_crtc(cstate
->base
.crtc
);
4991 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
4992 struct skl_pipe_wm
*pipe_wm
= &cstate
->wm
.skl
.optimal
;
4993 const struct skl_ddb_allocation
*ddb
= &state
->wm_results
.ddb
;
4994 enum pipe pipe
= crtc
->pipe
;
4995 enum plane_id plane_id
;
4997 if (!(state
->wm_results
.dirty_pipes
& drm_crtc_mask(&crtc
->base
)))
5000 I915_WRITE(PIPE_WM_LINETIME(pipe
), pipe_wm
->linetime
);
5002 for_each_plane_id_on_crtc(crtc
, plane_id
) {
5003 if (plane_id
!= PLANE_CURSOR
)
5004 skl_write_plane_wm(crtc
, &pipe_wm
->planes
[plane_id
],
5007 skl_write_cursor_wm(crtc
, &pipe_wm
->planes
[plane_id
],
5012 static void skl_initial_wm(struct intel_atomic_state
*state
,
5013 struct intel_crtc_state
*cstate
)
5015 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
5016 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5017 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5018 struct skl_wm_values
*results
= &state
->wm_results
;
5019 struct skl_wm_values
*hw_vals
= &dev_priv
->wm
.skl_hw
;
5020 enum pipe pipe
= intel_crtc
->pipe
;
5022 if ((results
->dirty_pipes
& drm_crtc_mask(&intel_crtc
->base
)) == 0)
5025 mutex_lock(&dev_priv
->wm
.wm_mutex
);
5027 if (cstate
->base
.active_changed
)
5028 skl_atomic_update_crtc_wm(state
, cstate
);
5030 skl_copy_wm_for_pipe(hw_vals
, results
, pipe
);
5032 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
5035 static void ilk_compute_wm_config(struct drm_device
*dev
,
5036 struct intel_wm_config
*config
)
5038 struct intel_crtc
*crtc
;
5040 /* Compute the currently _active_ config */
5041 for_each_intel_crtc(dev
, crtc
) {
5042 const struct intel_pipe_wm
*wm
= &crtc
->wm
.active
.ilk
;
5044 if (!wm
->pipe_enabled
)
5047 config
->sprites_enabled
|= wm
->sprites_enabled
;
5048 config
->sprites_scaled
|= wm
->sprites_scaled
;
5049 config
->num_pipes_active
++;
5053 static void ilk_program_watermarks(struct drm_i915_private
*dev_priv
)
5055 struct drm_device
*dev
= &dev_priv
->drm
;
5056 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
5057 struct ilk_wm_maximums max
;
5058 struct intel_wm_config config
= {};
5059 struct ilk_wm_values results
= {};
5060 enum intel_ddb_partitioning partitioning
;
5062 ilk_compute_wm_config(dev
, &config
);
5064 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_1_2
, &max
);
5065 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_1_2
);
5067 /* 5/6 split only in single pipe config on IVB+ */
5068 if (INTEL_GEN(dev_priv
) >= 7 &&
5069 config
.num_pipes_active
== 1 && config
.sprites_enabled
) {
5070 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_5_6
, &max
);
5071 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_5_6
);
5073 best_lp_wm
= ilk_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
5075 best_lp_wm
= &lp_wm_1_2
;
5078 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
5079 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
5081 ilk_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
5083 ilk_write_wm_values(dev_priv
, &results
);
5086 static void ilk_initial_watermarks(struct intel_atomic_state
*state
,
5087 struct intel_crtc_state
*cstate
)
5089 struct drm_i915_private
*dev_priv
= to_i915(cstate
->base
.crtc
->dev
);
5090 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
5092 mutex_lock(&dev_priv
->wm
.wm_mutex
);
5093 intel_crtc
->wm
.active
.ilk
= cstate
->wm
.ilk
.intermediate
;
5094 ilk_program_watermarks(dev_priv
);
5095 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
5098 static void ilk_optimize_watermarks(struct intel_atomic_state
*state
,
5099 struct intel_crtc_state
*cstate
)
5101 struct drm_i915_private
*dev_priv
= to_i915(cstate
->base
.crtc
->dev
);
5102 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
5104 mutex_lock(&dev_priv
->wm
.wm_mutex
);
5105 if (cstate
->wm
.need_postvbl_update
) {
5106 intel_crtc
->wm
.active
.ilk
= cstate
->wm
.ilk
.optimal
;
5107 ilk_program_watermarks(dev_priv
);
5109 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
5112 static inline void skl_wm_level_from_reg_val(uint32_t val
,
5113 struct skl_wm_level
*level
)
5115 level
->plane_en
= val
& PLANE_WM_EN
;
5116 level
->plane_res_b
= val
& PLANE_WM_BLOCKS_MASK
;
5117 level
->plane_res_l
= (val
>> PLANE_WM_LINES_SHIFT
) &
5118 PLANE_WM_LINES_MASK
;
5121 void skl_pipe_wm_get_hw_state(struct drm_crtc
*crtc
,
5122 struct skl_pipe_wm
*out
)
5124 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
5125 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5126 enum pipe pipe
= intel_crtc
->pipe
;
5127 int level
, max_level
;
5128 enum plane_id plane_id
;
5131 max_level
= ilk_wm_max_level(dev_priv
);
5133 for_each_plane_id_on_crtc(intel_crtc
, plane_id
) {
5134 struct skl_plane_wm
*wm
= &out
->planes
[plane_id
];
5136 for (level
= 0; level
<= max_level
; level
++) {
5137 if (plane_id
!= PLANE_CURSOR
)
5138 val
= I915_READ(PLANE_WM(pipe
, plane_id
, level
));
5140 val
= I915_READ(CUR_WM(pipe
, level
));
5142 skl_wm_level_from_reg_val(val
, &wm
->wm
[level
]);
5145 if (plane_id
!= PLANE_CURSOR
)
5146 val
= I915_READ(PLANE_WM_TRANS(pipe
, plane_id
));
5148 val
= I915_READ(CUR_WM_TRANS(pipe
));
5150 skl_wm_level_from_reg_val(val
, &wm
->trans_wm
);
5153 if (!intel_crtc
->active
)
5156 out
->linetime
= I915_READ(PIPE_WM_LINETIME(pipe
));
5159 void skl_wm_get_hw_state(struct drm_device
*dev
)
5161 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5162 struct skl_wm_values
*hw
= &dev_priv
->wm
.skl_hw
;
5163 struct skl_ddb_allocation
*ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
5164 struct drm_crtc
*crtc
;
5165 struct intel_crtc
*intel_crtc
;
5166 struct intel_crtc_state
*cstate
;
5168 skl_ddb_get_hw_state(dev_priv
, ddb
);
5169 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
5170 intel_crtc
= to_intel_crtc(crtc
);
5171 cstate
= to_intel_crtc_state(crtc
->state
);
5173 skl_pipe_wm_get_hw_state(crtc
, &cstate
->wm
.skl
.optimal
);
5175 if (intel_crtc
->active
)
5176 hw
->dirty_pipes
|= drm_crtc_mask(crtc
);
5179 if (dev_priv
->active_crtcs
) {
5180 /* Fully recompute DDB on first atomic commit */
5181 dev_priv
->wm
.distrust_bios_wm
= true;
5183 /* Easy/common case; just sanitize DDB now if everything off */
5184 memset(ddb
, 0, sizeof(*ddb
));
5188 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
5190 struct drm_device
*dev
= crtc
->dev
;
5191 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5192 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
5193 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5194 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
5195 struct intel_pipe_wm
*active
= &cstate
->wm
.ilk
.optimal
;
5196 enum pipe pipe
= intel_crtc
->pipe
;
5197 static const i915_reg_t wm0_pipe_reg
[] = {
5198 [PIPE_A
] = WM0_PIPEA_ILK
,
5199 [PIPE_B
] = WM0_PIPEB_ILK
,
5200 [PIPE_C
] = WM0_PIPEC_IVB
,
5203 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
5204 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5205 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
5207 memset(active
, 0, sizeof(*active
));
5209 active
->pipe_enabled
= intel_crtc
->active
;
5211 if (active
->pipe_enabled
) {
5212 u32 tmp
= hw
->wm_pipe
[pipe
];
5215 * For active pipes LP0 watermark is marked as
5216 * enabled, and LP1+ watermaks as disabled since
5217 * we can't really reverse compute them in case
5218 * multiple pipes are active.
5220 active
->wm
[0].enable
= true;
5221 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
5222 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
5223 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
5224 active
->linetime
= hw
->wm_linetime
[pipe
];
5226 int level
, max_level
= ilk_wm_max_level(dev_priv
);
5229 * For inactive pipes, all watermark levels
5230 * should be marked as enabled but zeroed,
5231 * which is what we'd compute them to.
5233 for (level
= 0; level
<= max_level
; level
++)
5234 active
->wm
[level
].enable
= true;
5237 intel_crtc
->wm
.active
.ilk
= *active
;
5240 #define _FW_WM(value, plane) \
5241 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
5242 #define _FW_WM_VLV(value, plane) \
5243 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
5245 static void g4x_read_wm_values(struct drm_i915_private
*dev_priv
,
5246 struct g4x_wm_values
*wm
)
5250 tmp
= I915_READ(DSPFW1
);
5251 wm
->sr
.plane
= _FW_WM(tmp
, SR
);
5252 wm
->pipe
[PIPE_B
].plane
[PLANE_CURSOR
] = _FW_WM(tmp
, CURSORB
);
5253 wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] = _FW_WM(tmp
, PLANEB
);
5254 wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] = _FW_WM(tmp
, PLANEA
);
5256 tmp
= I915_READ(DSPFW2
);
5257 wm
->fbc_en
= tmp
& DSPFW_FBC_SR_EN
;
5258 wm
->sr
.fbc
= _FW_WM(tmp
, FBC_SR
);
5259 wm
->hpll
.fbc
= _FW_WM(tmp
, FBC_HPLL_SR
);
5260 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] = _FW_WM(tmp
, SPRITEB
);
5261 wm
->pipe
[PIPE_A
].plane
[PLANE_CURSOR
] = _FW_WM(tmp
, CURSORA
);
5262 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] = _FW_WM(tmp
, SPRITEA
);
5264 tmp
= I915_READ(DSPFW3
);
5265 wm
->hpll_en
= tmp
& DSPFW_HPLL_SR_EN
;
5266 wm
->sr
.cursor
= _FW_WM(tmp
, CURSOR_SR
);
5267 wm
->hpll
.cursor
= _FW_WM(tmp
, HPLL_CURSOR
);
5268 wm
->hpll
.plane
= _FW_WM(tmp
, HPLL_SR
);
5271 static void vlv_read_wm_values(struct drm_i915_private
*dev_priv
,
5272 struct vlv_wm_values
*wm
)
5277 for_each_pipe(dev_priv
, pipe
) {
5278 tmp
= I915_READ(VLV_DDL(pipe
));
5280 wm
->ddl
[pipe
].plane
[PLANE_PRIMARY
] =
5281 (tmp
>> DDL_PLANE_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
5282 wm
->ddl
[pipe
].plane
[PLANE_CURSOR
] =
5283 (tmp
>> DDL_CURSOR_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
5284 wm
->ddl
[pipe
].plane
[PLANE_SPRITE0
] =
5285 (tmp
>> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
5286 wm
->ddl
[pipe
].plane
[PLANE_SPRITE1
] =
5287 (tmp
>> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
5290 tmp
= I915_READ(DSPFW1
);
5291 wm
->sr
.plane
= _FW_WM(tmp
, SR
);
5292 wm
->pipe
[PIPE_B
].plane
[PLANE_CURSOR
] = _FW_WM(tmp
, CURSORB
);
5293 wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] = _FW_WM_VLV(tmp
, PLANEB
);
5294 wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] = _FW_WM_VLV(tmp
, PLANEA
);
5296 tmp
= I915_READ(DSPFW2
);
5297 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] = _FW_WM_VLV(tmp
, SPRITEB
);
5298 wm
->pipe
[PIPE_A
].plane
[PLANE_CURSOR
] = _FW_WM(tmp
, CURSORA
);
5299 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] = _FW_WM_VLV(tmp
, SPRITEA
);
5301 tmp
= I915_READ(DSPFW3
);
5302 wm
->sr
.cursor
= _FW_WM(tmp
, CURSOR_SR
);
5304 if (IS_CHERRYVIEW(dev_priv
)) {
5305 tmp
= I915_READ(DSPFW7_CHV
);
5306 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] = _FW_WM_VLV(tmp
, SPRITED
);
5307 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] = _FW_WM_VLV(tmp
, SPRITEC
);
5309 tmp
= I915_READ(DSPFW8_CHV
);
5310 wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE1
] = _FW_WM_VLV(tmp
, SPRITEF
);
5311 wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE0
] = _FW_WM_VLV(tmp
, SPRITEE
);
5313 tmp
= I915_READ(DSPFW9_CHV
);
5314 wm
->pipe
[PIPE_C
].plane
[PLANE_PRIMARY
] = _FW_WM_VLV(tmp
, PLANEC
);
5315 wm
->pipe
[PIPE_C
].plane
[PLANE_CURSOR
] = _FW_WM(tmp
, CURSORC
);
5317 tmp
= I915_READ(DSPHOWM
);
5318 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
5319 wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITEF_HI
) << 8;
5320 wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEE_HI
) << 8;
5321 wm
->pipe
[PIPE_C
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEC_HI
) << 8;
5322 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
5323 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
5324 wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEB_HI
) << 8;
5325 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
5326 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
5327 wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEA_HI
) << 8;
5329 tmp
= I915_READ(DSPFW7
);
5330 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] = _FW_WM_VLV(tmp
, SPRITED
);
5331 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] = _FW_WM_VLV(tmp
, SPRITEC
);
5333 tmp
= I915_READ(DSPHOWM
);
5334 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
5335 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
5336 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
5337 wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEB_HI
) << 8;
5338 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
5339 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
5340 wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEA_HI
) << 8;
5347 void g4x_wm_get_hw_state(struct drm_device
*dev
)
5349 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5350 struct g4x_wm_values
*wm
= &dev_priv
->wm
.g4x
;
5351 struct intel_crtc
*crtc
;
5353 g4x_read_wm_values(dev_priv
, wm
);
5355 wm
->cxsr
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
5357 for_each_intel_crtc(dev
, crtc
) {
5358 struct intel_crtc_state
*crtc_state
=
5359 to_intel_crtc_state(crtc
->base
.state
);
5360 struct g4x_wm_state
*active
= &crtc
->wm
.active
.g4x
;
5361 struct g4x_pipe_wm
*raw
;
5362 enum pipe pipe
= crtc
->pipe
;
5363 enum plane_id plane_id
;
5364 int level
, max_level
;
5366 active
->cxsr
= wm
->cxsr
;
5367 active
->hpll_en
= wm
->hpll_en
;
5368 active
->fbc_en
= wm
->fbc_en
;
5370 active
->sr
= wm
->sr
;
5371 active
->hpll
= wm
->hpll
;
5373 for_each_plane_id_on_crtc(crtc
, plane_id
) {
5374 active
->wm
.plane
[plane_id
] =
5375 wm
->pipe
[pipe
].plane
[plane_id
];
5378 if (wm
->cxsr
&& wm
->hpll_en
)
5379 max_level
= G4X_WM_LEVEL_HPLL
;
5381 max_level
= G4X_WM_LEVEL_SR
;
5383 max_level
= G4X_WM_LEVEL_NORMAL
;
5385 level
= G4X_WM_LEVEL_NORMAL
;
5386 raw
= &crtc_state
->wm
.g4x
.raw
[level
];
5387 for_each_plane_id_on_crtc(crtc
, plane_id
)
5388 raw
->plane
[plane_id
] = active
->wm
.plane
[plane_id
];
5390 if (++level
> max_level
)
5393 raw
= &crtc_state
->wm
.g4x
.raw
[level
];
5394 raw
->plane
[PLANE_PRIMARY
] = active
->sr
.plane
;
5395 raw
->plane
[PLANE_CURSOR
] = active
->sr
.cursor
;
5396 raw
->plane
[PLANE_SPRITE0
] = 0;
5397 raw
->fbc
= active
->sr
.fbc
;
5399 if (++level
> max_level
)
5402 raw
= &crtc_state
->wm
.g4x
.raw
[level
];
5403 raw
->plane
[PLANE_PRIMARY
] = active
->hpll
.plane
;
5404 raw
->plane
[PLANE_CURSOR
] = active
->hpll
.cursor
;
5405 raw
->plane
[PLANE_SPRITE0
] = 0;
5406 raw
->fbc
= active
->hpll
.fbc
;
5409 for_each_plane_id_on_crtc(crtc
, plane_id
)
5410 g4x_raw_plane_wm_set(crtc_state
, level
,
5411 plane_id
, USHRT_MAX
);
5412 g4x_raw_fbc_wm_set(crtc_state
, level
, USHRT_MAX
);
5414 crtc_state
->wm
.g4x
.optimal
= *active
;
5415 crtc_state
->wm
.g4x
.intermediate
= *active
;
5417 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n",
5419 wm
->pipe
[pipe
].plane
[PLANE_PRIMARY
],
5420 wm
->pipe
[pipe
].plane
[PLANE_CURSOR
],
5421 wm
->pipe
[pipe
].plane
[PLANE_SPRITE0
]);
5424 DRM_DEBUG_KMS("Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n",
5425 wm
->sr
.plane
, wm
->sr
.cursor
, wm
->sr
.fbc
);
5426 DRM_DEBUG_KMS("Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n",
5427 wm
->hpll
.plane
, wm
->hpll
.cursor
, wm
->hpll
.fbc
);
5428 DRM_DEBUG_KMS("Initial SR=%s HPLL=%s FBC=%s\n",
5429 yesno(wm
->cxsr
), yesno(wm
->hpll_en
), yesno(wm
->fbc_en
));
5432 void g4x_wm_sanitize(struct drm_i915_private
*dev_priv
)
5434 struct intel_plane
*plane
;
5435 struct intel_crtc
*crtc
;
5437 mutex_lock(&dev_priv
->wm
.wm_mutex
);
5439 for_each_intel_plane(&dev_priv
->drm
, plane
) {
5440 struct intel_crtc
*crtc
=
5441 intel_get_crtc_for_pipe(dev_priv
, plane
->pipe
);
5442 struct intel_crtc_state
*crtc_state
=
5443 to_intel_crtc_state(crtc
->base
.state
);
5444 struct intel_plane_state
*plane_state
=
5445 to_intel_plane_state(plane
->base
.state
);
5446 struct g4x_wm_state
*wm_state
= &crtc_state
->wm
.g4x
.optimal
;
5447 enum plane_id plane_id
= plane
->id
;
5450 if (plane_state
->base
.visible
)
5453 for (level
= 0; level
< 3; level
++) {
5454 struct g4x_pipe_wm
*raw
=
5455 &crtc_state
->wm
.g4x
.raw
[level
];
5457 raw
->plane
[plane_id
] = 0;
5458 wm_state
->wm
.plane
[plane_id
] = 0;
5461 if (plane_id
== PLANE_PRIMARY
) {
5462 for (level
= 0; level
< 3; level
++) {
5463 struct g4x_pipe_wm
*raw
=
5464 &crtc_state
->wm
.g4x
.raw
[level
];
5468 wm_state
->sr
.fbc
= 0;
5469 wm_state
->hpll
.fbc
= 0;
5470 wm_state
->fbc_en
= false;
5474 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
5475 struct intel_crtc_state
*crtc_state
=
5476 to_intel_crtc_state(crtc
->base
.state
);
5478 crtc_state
->wm
.g4x
.intermediate
=
5479 crtc_state
->wm
.g4x
.optimal
;
5480 crtc
->wm
.active
.g4x
= crtc_state
->wm
.g4x
.optimal
;
5483 g4x_program_watermarks(dev_priv
);
5485 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
5488 void vlv_wm_get_hw_state(struct drm_device
*dev
)
5490 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5491 struct vlv_wm_values
*wm
= &dev_priv
->wm
.vlv
;
5492 struct intel_crtc
*crtc
;
5495 vlv_read_wm_values(dev_priv
, wm
);
5497 wm
->cxsr
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
5498 wm
->level
= VLV_WM_LEVEL_PM2
;
5500 if (IS_CHERRYVIEW(dev_priv
)) {
5501 mutex_lock(&dev_priv
->rps
.hw_lock
);
5503 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5504 if (val
& DSP_MAXFIFO_PM5_ENABLE
)
5505 wm
->level
= VLV_WM_LEVEL_PM5
;
5508 * If DDR DVFS is disabled in the BIOS, Punit
5509 * will never ack the request. So if that happens
5510 * assume we don't have to enable/disable DDR DVFS
5511 * dynamically. To test that just set the REQ_ACK
5512 * bit to poke the Punit, but don't change the
5513 * HIGH/LOW bits so that we don't actually change
5514 * the current state.
5516 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
5517 val
|= FORCE_DDR_FREQ_REQ_ACK
;
5518 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
5520 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
5521 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3)) {
5522 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
5523 "assuming DDR DVFS is disabled\n");
5524 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM5
;
5526 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
5527 if ((val
& FORCE_DDR_HIGH_FREQ
) == 0)
5528 wm
->level
= VLV_WM_LEVEL_DDR_DVFS
;
5531 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5534 for_each_intel_crtc(dev
, crtc
) {
5535 struct intel_crtc_state
*crtc_state
=
5536 to_intel_crtc_state(crtc
->base
.state
);
5537 struct vlv_wm_state
*active
= &crtc
->wm
.active
.vlv
;
5538 const struct vlv_fifo_state
*fifo_state
=
5539 &crtc_state
->wm
.vlv
.fifo_state
;
5540 enum pipe pipe
= crtc
->pipe
;
5541 enum plane_id plane_id
;
5544 vlv_get_fifo_size(crtc_state
);
5546 active
->num_levels
= wm
->level
+ 1;
5547 active
->cxsr
= wm
->cxsr
;
5549 for (level
= 0; level
< active
->num_levels
; level
++) {
5550 struct g4x_pipe_wm
*raw
=
5551 &crtc_state
->wm
.vlv
.raw
[level
];
5553 active
->sr
[level
].plane
= wm
->sr
.plane
;
5554 active
->sr
[level
].cursor
= wm
->sr
.cursor
;
5556 for_each_plane_id_on_crtc(crtc
, plane_id
) {
5557 active
->wm
[level
].plane
[plane_id
] =
5558 wm
->pipe
[pipe
].plane
[plane_id
];
5560 raw
->plane
[plane_id
] =
5561 vlv_invert_wm_value(active
->wm
[level
].plane
[plane_id
],
5562 fifo_state
->plane
[plane_id
]);
5566 for_each_plane_id_on_crtc(crtc
, plane_id
)
5567 vlv_raw_plane_wm_set(crtc_state
, level
,
5568 plane_id
, USHRT_MAX
);
5569 vlv_invalidate_wms(crtc
, active
, level
);
5571 crtc_state
->wm
.vlv
.optimal
= *active
;
5572 crtc_state
->wm
.vlv
.intermediate
= *active
;
5574 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
5576 wm
->pipe
[pipe
].plane
[PLANE_PRIMARY
],
5577 wm
->pipe
[pipe
].plane
[PLANE_CURSOR
],
5578 wm
->pipe
[pipe
].plane
[PLANE_SPRITE0
],
5579 wm
->pipe
[pipe
].plane
[PLANE_SPRITE1
]);
5582 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
5583 wm
->sr
.plane
, wm
->sr
.cursor
, wm
->level
, wm
->cxsr
);
5586 void vlv_wm_sanitize(struct drm_i915_private
*dev_priv
)
5588 struct intel_plane
*plane
;
5589 struct intel_crtc
*crtc
;
5591 mutex_lock(&dev_priv
->wm
.wm_mutex
);
5593 for_each_intel_plane(&dev_priv
->drm
, plane
) {
5594 struct intel_crtc
*crtc
=
5595 intel_get_crtc_for_pipe(dev_priv
, plane
->pipe
);
5596 struct intel_crtc_state
*crtc_state
=
5597 to_intel_crtc_state(crtc
->base
.state
);
5598 struct intel_plane_state
*plane_state
=
5599 to_intel_plane_state(plane
->base
.state
);
5600 struct vlv_wm_state
*wm_state
= &crtc_state
->wm
.vlv
.optimal
;
5601 const struct vlv_fifo_state
*fifo_state
=
5602 &crtc_state
->wm
.vlv
.fifo_state
;
5603 enum plane_id plane_id
= plane
->id
;
5606 if (plane_state
->base
.visible
)
5609 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
5610 struct g4x_pipe_wm
*raw
=
5611 &crtc_state
->wm
.vlv
.raw
[level
];
5613 raw
->plane
[plane_id
] = 0;
5615 wm_state
->wm
[level
].plane
[plane_id
] =
5616 vlv_invert_wm_value(raw
->plane
[plane_id
],
5617 fifo_state
->plane
[plane_id
]);
5621 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
5622 struct intel_crtc_state
*crtc_state
=
5623 to_intel_crtc_state(crtc
->base
.state
);
5625 crtc_state
->wm
.vlv
.intermediate
=
5626 crtc_state
->wm
.vlv
.optimal
;
5627 crtc
->wm
.active
.vlv
= crtc_state
->wm
.vlv
.optimal
;
5630 vlv_program_watermarks(dev_priv
);
5632 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
5635 void ilk_wm_get_hw_state(struct drm_device
*dev
)
5637 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5638 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
5639 struct drm_crtc
*crtc
;
5641 for_each_crtc(dev
, crtc
)
5642 ilk_pipe_wm_get_hw_state(crtc
);
5644 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
5645 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
5646 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
5648 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
5649 if (INTEL_GEN(dev_priv
) >= 7) {
5650 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
5651 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
5654 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5655 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
5656 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
5657 else if (IS_IVYBRIDGE(dev_priv
))
5658 hw
->partitioning
= (I915_READ(DISP_ARB_CTL2
) & DISP_DATA_PARTITION_5_6
) ?
5659 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
5662 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
5666 * intel_update_watermarks - update FIFO watermark values based on current modes
5668 * Calculate watermark values for the various WM regs based on current mode
5669 * and plane configuration.
5671 * There are several cases to deal with here:
5672 * - normal (i.e. non-self-refresh)
5673 * - self-refresh (SR) mode
5674 * - lines are large relative to FIFO size (buffer can hold up to 2)
5675 * - lines are small relative to FIFO size (buffer can hold more than 2
5676 * lines), so need to account for TLB latency
5678 * The normal calculation is:
5679 * watermark = dotclock * bytes per pixel * latency
5680 * where latency is platform & configuration dependent (we assume pessimal
5683 * The SR calculation is:
5684 * watermark = (trunc(latency/line time)+1) * surface width *
5687 * line time = htotal / dotclock
5688 * surface width = hdisplay for normal plane and 64 for cursor
5689 * and latency is assumed to be high, as above.
5691 * The final value programmed to the register should always be rounded up,
5692 * and include an extra 2 entries to account for clock crossings.
5694 * We don't use the sprite, so we can ignore that. And on Crestline we have
5695 * to set the non-SR watermarks to 8.
5697 void intel_update_watermarks(struct intel_crtc
*crtc
)
5699 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5701 if (dev_priv
->display
.update_wm
)
5702 dev_priv
->display
.update_wm(crtc
);
5706 * Lock protecting IPS related data structures
5708 DEFINE_SPINLOCK(mchdev_lock
);
5710 /* Global for IPS driver to get at the current i915 device. Protected by
5712 static struct drm_i915_private
*i915_mch_dev
;
5714 bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
)
5718 lockdep_assert_held(&mchdev_lock
);
5720 rgvswctl
= I915_READ16(MEMSWCTL
);
5721 if (rgvswctl
& MEMCTL_CMD_STS
) {
5722 DRM_DEBUG("gpu busy, RCS change rejected\n");
5723 return false; /* still busy with another command */
5726 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
5727 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
5728 I915_WRITE16(MEMSWCTL
, rgvswctl
);
5729 POSTING_READ16(MEMSWCTL
);
5731 rgvswctl
|= MEMCTL_CMD_STS
;
5732 I915_WRITE16(MEMSWCTL
, rgvswctl
);
5737 static void ironlake_enable_drps(struct drm_i915_private
*dev_priv
)
5740 u8 fmax
, fmin
, fstart
, vstart
;
5742 spin_lock_irq(&mchdev_lock
);
5744 rgvmodectl
= I915_READ(MEMMODECTL
);
5746 /* Enable temp reporting */
5747 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
5748 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
5750 /* 100ms RC evaluation intervals */
5751 I915_WRITE(RCUPEI
, 100000);
5752 I915_WRITE(RCDNEI
, 100000);
5754 /* Set max/min thresholds to 90ms and 80ms respectively */
5755 I915_WRITE(RCBMAXAVG
, 90000);
5756 I915_WRITE(RCBMINAVG
, 80000);
5758 I915_WRITE(MEMIHYST
, 1);
5760 /* Set up min, max, and cur for interrupt handling */
5761 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
5762 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
5763 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
5764 MEMMODE_FSTART_SHIFT
;
5766 vstart
= (I915_READ(PXVFREQ(fstart
)) & PXVFREQ_PX_MASK
) >>
5769 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
5770 dev_priv
->ips
.fstart
= fstart
;
5772 dev_priv
->ips
.max_delay
= fstart
;
5773 dev_priv
->ips
.min_delay
= fmin
;
5774 dev_priv
->ips
.cur_delay
= fstart
;
5776 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5777 fmax
, fmin
, fstart
);
5779 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
5782 * Interrupts will be enabled in ironlake_irq_postinstall
5785 I915_WRITE(VIDSTART
, vstart
);
5786 POSTING_READ(VIDSTART
);
5788 rgvmodectl
|= MEMMODE_SWMODE_EN
;
5789 I915_WRITE(MEMMODECTL
, rgvmodectl
);
5791 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
5792 DRM_ERROR("stuck trying to change perf mode\n");
5795 ironlake_set_drps(dev_priv
, fstart
);
5797 dev_priv
->ips
.last_count1
= I915_READ(DMIEC
) +
5798 I915_READ(DDREC
) + I915_READ(CSIEC
);
5799 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
5800 dev_priv
->ips
.last_count2
= I915_READ(GFXEC
);
5801 dev_priv
->ips
.last_time2
= ktime_get_raw_ns();
5803 spin_unlock_irq(&mchdev_lock
);
5806 static void ironlake_disable_drps(struct drm_i915_private
*dev_priv
)
5810 spin_lock_irq(&mchdev_lock
);
5812 rgvswctl
= I915_READ16(MEMSWCTL
);
5814 /* Ack interrupts, disable EFC interrupt */
5815 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
5816 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
5817 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
5818 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
5819 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
5821 /* Go back to the starting frequency */
5822 ironlake_set_drps(dev_priv
, dev_priv
->ips
.fstart
);
5824 rgvswctl
|= MEMCTL_CMD_STS
;
5825 I915_WRITE(MEMSWCTL
, rgvswctl
);
5828 spin_unlock_irq(&mchdev_lock
);
5831 /* There's a funny hw issue where the hw returns all 0 when reading from
5832 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
5833 * ourselves, instead of doing a rmw cycle (which might result in us clearing
5834 * all limits and the gpu stuck at whatever frequency it is at atm).
5836 static u32
intel_rps_limits(struct drm_i915_private
*dev_priv
, u8 val
)
5840 /* Only set the down limit when we've reached the lowest level to avoid
5841 * getting more interrupts, otherwise leave this clear. This prevents a
5842 * race in the hw when coming out of rc6: There's a tiny window where
5843 * the hw runs at the minimal clock before selecting the desired
5844 * frequency, if the down threshold expires in that window we will not
5845 * receive a down interrupt. */
5846 if (IS_GEN9(dev_priv
)) {
5847 limits
= (dev_priv
->rps
.max_freq_softlimit
) << 23;
5848 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
5849 limits
|= (dev_priv
->rps
.min_freq_softlimit
) << 14;
5851 limits
= dev_priv
->rps
.max_freq_softlimit
<< 24;
5852 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
5853 limits
|= dev_priv
->rps
.min_freq_softlimit
<< 16;
5859 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
5862 u32 threshold_up
= 0, threshold_down
= 0; /* in % */
5863 u32 ei_up
= 0, ei_down
= 0;
5865 new_power
= dev_priv
->rps
.power
;
5866 switch (dev_priv
->rps
.power
) {
5868 if (val
> dev_priv
->rps
.efficient_freq
+ 1 &&
5869 val
> dev_priv
->rps
.cur_freq
)
5870 new_power
= BETWEEN
;
5874 if (val
<= dev_priv
->rps
.efficient_freq
&&
5875 val
< dev_priv
->rps
.cur_freq
)
5876 new_power
= LOW_POWER
;
5877 else if (val
>= dev_priv
->rps
.rp0_freq
&&
5878 val
> dev_priv
->rps
.cur_freq
)
5879 new_power
= HIGH_POWER
;
5883 if (val
< (dev_priv
->rps
.rp1_freq
+ dev_priv
->rps
.rp0_freq
) >> 1 &&
5884 val
< dev_priv
->rps
.cur_freq
)
5885 new_power
= BETWEEN
;
5888 /* Max/min bins are special */
5889 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
5890 new_power
= LOW_POWER
;
5891 if (val
>= dev_priv
->rps
.max_freq_softlimit
)
5892 new_power
= HIGH_POWER
;
5893 if (new_power
== dev_priv
->rps
.power
)
5896 /* Note the units here are not exactly 1us, but 1280ns. */
5897 switch (new_power
) {
5899 /* Upclock if more than 95% busy over 16ms */
5903 /* Downclock if less than 85% busy over 32ms */
5905 threshold_down
= 85;
5909 /* Upclock if more than 90% busy over 13ms */
5913 /* Downclock if less than 75% busy over 32ms */
5915 threshold_down
= 75;
5919 /* Upclock if more than 85% busy over 10ms */
5923 /* Downclock if less than 60% busy over 32ms */
5925 threshold_down
= 60;
5929 /* When byt can survive without system hang with dynamic
5930 * sw freq adjustments, this restriction can be lifted.
5932 if (IS_VALLEYVIEW(dev_priv
))
5935 I915_WRITE(GEN6_RP_UP_EI
,
5936 GT_INTERVAL_FROM_US(dev_priv
, ei_up
));
5937 I915_WRITE(GEN6_RP_UP_THRESHOLD
,
5938 GT_INTERVAL_FROM_US(dev_priv
,
5939 ei_up
* threshold_up
/ 100));
5941 I915_WRITE(GEN6_RP_DOWN_EI
,
5942 GT_INTERVAL_FROM_US(dev_priv
, ei_down
));
5943 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
,
5944 GT_INTERVAL_FROM_US(dev_priv
,
5945 ei_down
* threshold_down
/ 100));
5947 I915_WRITE(GEN6_RP_CONTROL
,
5948 GEN6_RP_MEDIA_TURBO
|
5949 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
5950 GEN6_RP_MEDIA_IS_GFX
|
5952 GEN6_RP_UP_BUSY_AVG
|
5953 GEN6_RP_DOWN_IDLE_AVG
);
5956 dev_priv
->rps
.power
= new_power
;
5957 dev_priv
->rps
.up_threshold
= threshold_up
;
5958 dev_priv
->rps
.down_threshold
= threshold_down
;
5959 dev_priv
->rps
.last_adj
= 0;
5962 static u32
gen6_rps_pm_mask(struct drm_i915_private
*dev_priv
, u8 val
)
5966 /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
5967 if (val
> dev_priv
->rps
.min_freq_softlimit
)
5968 mask
|= GEN6_PM_RP_UP_EI_EXPIRED
| GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT
;
5969 if (val
< dev_priv
->rps
.max_freq_softlimit
)
5970 mask
|= GEN6_PM_RP_UP_EI_EXPIRED
| GEN6_PM_RP_UP_THRESHOLD
;
5972 mask
&= dev_priv
->pm_rps_events
;
5974 return gen6_sanitize_rps_pm_mask(dev_priv
, ~mask
);
5977 /* gen6_set_rps is called to update the frequency request, but should also be
5978 * called when the range (min_delay and max_delay) is modified so that we can
5979 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
5980 static int gen6_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
5982 /* min/max delay may still have been modified so be sure to
5983 * write the limits value.
5985 if (val
!= dev_priv
->rps
.cur_freq
) {
5986 gen6_set_rps_thresholds(dev_priv
, val
);
5988 if (IS_GEN9(dev_priv
))
5989 I915_WRITE(GEN6_RPNSWREQ
,
5990 GEN9_FREQUENCY(val
));
5991 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5992 I915_WRITE(GEN6_RPNSWREQ
,
5993 HSW_FREQUENCY(val
));
5995 I915_WRITE(GEN6_RPNSWREQ
,
5996 GEN6_FREQUENCY(val
) |
5998 GEN6_AGGRESSIVE_TURBO
);
6001 /* Make sure we continue to get interrupts
6002 * until we hit the minimum or maximum frequencies.
6004 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, intel_rps_limits(dev_priv
, val
));
6005 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
6007 dev_priv
->rps
.cur_freq
= val
;
6008 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
6013 static int valleyview_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
6017 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv
) && (val
& 1),
6018 "Odd GPU freq value\n"))
6021 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
6023 if (val
!= dev_priv
->rps
.cur_freq
) {
6024 err
= vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
6028 gen6_set_rps_thresholds(dev_priv
, val
);
6031 dev_priv
->rps
.cur_freq
= val
;
6032 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
6037 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
6039 * * If Gfx is Idle, then
6040 * 1. Forcewake Media well.
6041 * 2. Request idle freq.
6042 * 3. Release Forcewake of Media well.
6044 static void vlv_set_rps_idle(struct drm_i915_private
*dev_priv
)
6046 u32 val
= dev_priv
->rps
.idle_freq
;
6049 if (dev_priv
->rps
.cur_freq
<= val
)
6052 /* The punit delays the write of the frequency and voltage until it
6053 * determines the GPU is awake. During normal usage we don't want to
6054 * waste power changing the frequency if the GPU is sleeping (rc6).
6055 * However, the GPU and driver is now idle and we do not want to delay
6056 * switching to minimum voltage (reducing power whilst idle) as we do
6057 * not expect to be woken in the near future and so must flush the
6058 * change by waking the device.
6060 * We choose to take the media powerwell (either would do to trick the
6061 * punit into committing the voltage change) as that takes a lot less
6062 * power than the render powerwell.
6064 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_MEDIA
);
6065 err
= valleyview_set_rps(dev_priv
, val
);
6066 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_MEDIA
);
6069 DRM_ERROR("Failed to set RPS for idle\n");
6072 void gen6_rps_busy(struct drm_i915_private
*dev_priv
)
6074 mutex_lock(&dev_priv
->rps
.hw_lock
);
6075 if (dev_priv
->rps
.enabled
) {
6078 if (dev_priv
->pm_rps_events
& GEN6_PM_RP_UP_EI_EXPIRED
)
6079 gen6_rps_reset_ei(dev_priv
);
6080 I915_WRITE(GEN6_PMINTRMSK
,
6081 gen6_rps_pm_mask(dev_priv
, dev_priv
->rps
.cur_freq
));
6083 gen6_enable_rps_interrupts(dev_priv
);
6085 /* Use the user's desired frequency as a guide, but for better
6086 * performance, jump directly to RPe as our starting frequency.
6088 freq
= max(dev_priv
->rps
.cur_freq
,
6089 dev_priv
->rps
.efficient_freq
);
6091 if (intel_set_rps(dev_priv
,
6093 dev_priv
->rps
.min_freq_softlimit
,
6094 dev_priv
->rps
.max_freq_softlimit
)))
6095 DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
6097 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6100 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
6102 /* Flush our bottom-half so that it does not race with us
6103 * setting the idle frequency and so that it is bounded by
6104 * our rpm wakeref. And then disable the interrupts to stop any
6105 * futher RPS reclocking whilst we are asleep.
6107 gen6_disable_rps_interrupts(dev_priv
);
6109 mutex_lock(&dev_priv
->rps
.hw_lock
);
6110 if (dev_priv
->rps
.enabled
) {
6111 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
6112 vlv_set_rps_idle(dev_priv
);
6114 gen6_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
6115 dev_priv
->rps
.last_adj
= 0;
6116 I915_WRITE(GEN6_PMINTRMSK
,
6117 gen6_sanitize_rps_pm_mask(dev_priv
, ~0));
6119 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6121 spin_lock(&dev_priv
->rps
.client_lock
);
6122 while (!list_empty(&dev_priv
->rps
.clients
))
6123 list_del_init(dev_priv
->rps
.clients
.next
);
6124 spin_unlock(&dev_priv
->rps
.client_lock
);
6127 void gen6_rps_boost(struct drm_i915_private
*dev_priv
,
6128 struct intel_rps_client
*rps
,
6129 unsigned long submitted
)
6131 /* This is intentionally racy! We peek at the state here, then
6132 * validate inside the RPS worker.
6134 if (!(dev_priv
->gt
.awake
&&
6135 dev_priv
->rps
.enabled
&&
6136 dev_priv
->rps
.cur_freq
< dev_priv
->rps
.boost_freq
))
6139 /* Force a RPS boost (and don't count it against the client) if
6140 * the GPU is severely congested.
6142 if (rps
&& time_after(jiffies
, submitted
+ DRM_I915_THROTTLE_JIFFIES
))
6145 spin_lock(&dev_priv
->rps
.client_lock
);
6146 if (rps
== NULL
|| list_empty(&rps
->link
)) {
6147 spin_lock_irq(&dev_priv
->irq_lock
);
6148 if (dev_priv
->rps
.interrupts_enabled
) {
6149 dev_priv
->rps
.client_boost
= true;
6150 schedule_work(&dev_priv
->rps
.work
);
6152 spin_unlock_irq(&dev_priv
->irq_lock
);
6155 list_add(&rps
->link
, &dev_priv
->rps
.clients
);
6158 dev_priv
->rps
.boosts
++;
6160 spin_unlock(&dev_priv
->rps
.client_lock
);
6163 int intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
6167 lockdep_assert_held(&dev_priv
->rps
.hw_lock
);
6168 GEM_BUG_ON(val
> dev_priv
->rps
.max_freq
);
6169 GEM_BUG_ON(val
< dev_priv
->rps
.min_freq
);
6171 if (!dev_priv
->rps
.enabled
) {
6172 dev_priv
->rps
.cur_freq
= val
;
6176 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
6177 err
= valleyview_set_rps(dev_priv
, val
);
6179 err
= gen6_set_rps(dev_priv
, val
);
6184 static void gen9_disable_rc6(struct drm_i915_private
*dev_priv
)
6186 I915_WRITE(GEN6_RC_CONTROL
, 0);
6187 I915_WRITE(GEN9_PG_ENABLE
, 0);
6190 static void gen9_disable_rps(struct drm_i915_private
*dev_priv
)
6192 I915_WRITE(GEN6_RP_CONTROL
, 0);
6195 static void gen6_disable_rps(struct drm_i915_private
*dev_priv
)
6197 I915_WRITE(GEN6_RC_CONTROL
, 0);
6198 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
6199 I915_WRITE(GEN6_RP_CONTROL
, 0);
6202 static void cherryview_disable_rps(struct drm_i915_private
*dev_priv
)
6204 I915_WRITE(GEN6_RC_CONTROL
, 0);
6207 static void valleyview_disable_rps(struct drm_i915_private
*dev_priv
)
6209 /* we're doing forcewake before Disabling RC6,
6210 * This what the BIOS expects when going into suspend */
6211 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6213 I915_WRITE(GEN6_RC_CONTROL
, 0);
6215 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6218 static void intel_print_rc6_info(struct drm_i915_private
*dev_priv
, u32 mode
)
6220 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
6221 if (mode
& (GEN7_RC_CTL_TO_MODE
| GEN6_RC_CTL_EI_MODE(1)))
6222 mode
= GEN6_RC_CTL_RC6_ENABLE
;
6226 if (HAS_RC6p(dev_priv
))
6227 DRM_DEBUG_DRIVER("Enabling RC6 states: "
6228 "RC6 %s RC6p %s RC6pp %s\n",
6229 onoff(mode
& GEN6_RC_CTL_RC6_ENABLE
),
6230 onoff(mode
& GEN6_RC_CTL_RC6p_ENABLE
),
6231 onoff(mode
& GEN6_RC_CTL_RC6pp_ENABLE
));
6234 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
6235 onoff(mode
& GEN6_RC_CTL_RC6_ENABLE
));
6238 static bool bxt_check_bios_rc6_setup(struct drm_i915_private
*dev_priv
)
6240 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
6241 bool enable_rc6
= true;
6242 unsigned long rc6_ctx_base
;
6246 rc_ctl
= I915_READ(GEN6_RC_CONTROL
);
6247 rc_sw_target
= (I915_READ(GEN6_RC_STATE
) & RC_SW_TARGET_STATE_MASK
) >>
6248 RC_SW_TARGET_STATE_SHIFT
;
6249 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
6250 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
6251 onoff(rc_ctl
& GEN6_RC_CTL_HW_ENABLE
),
6252 onoff(rc_ctl
& GEN6_RC_CTL_RC6_ENABLE
),
6255 if (!(I915_READ(RC6_LOCATION
) & RC6_CTX_IN_DRAM
)) {
6256 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
6261 * The exact context size is not known for BXT, so assume a page size
6264 rc6_ctx_base
= I915_READ(RC6_CTX_BASE
) & RC6_CTX_BASE_MASK
;
6265 if (!((rc6_ctx_base
>= ggtt
->stolen_reserved_base
) &&
6266 (rc6_ctx_base
+ PAGE_SIZE
<= ggtt
->stolen_reserved_base
+
6267 ggtt
->stolen_reserved_size
))) {
6268 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
6272 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT
) & IDLE_TIME_MASK
) > 1) &&
6273 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0
) & IDLE_TIME_MASK
) > 1) &&
6274 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT
) & IDLE_TIME_MASK
) > 1) &&
6275 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT
) & IDLE_TIME_MASK
) > 1))) {
6276 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
6280 if (!I915_READ(GEN8_PUSHBUS_CONTROL
) ||
6281 !I915_READ(GEN8_PUSHBUS_ENABLE
) ||
6282 !I915_READ(GEN8_PUSHBUS_SHIFT
)) {
6283 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
6287 if (!I915_READ(GEN6_GFXPAUSE
)) {
6288 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
6292 if (!I915_READ(GEN8_MISC_CTRL0
)) {
6293 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
6300 int sanitize_rc6_option(struct drm_i915_private
*dev_priv
, int enable_rc6
)
6302 /* No RC6 before Ironlake and code is gone for ilk. */
6303 if (INTEL_INFO(dev_priv
)->gen
< 6)
6309 if (IS_GEN9_LP(dev_priv
) && !bxt_check_bios_rc6_setup(dev_priv
)) {
6310 DRM_INFO("RC6 disabled by BIOS\n");
6314 /* Respect the kernel parameter if it is set */
6315 if (enable_rc6
>= 0) {
6318 if (HAS_RC6p(dev_priv
))
6319 mask
= INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
|
6322 mask
= INTEL_RC6_ENABLE
;
6324 if ((enable_rc6
& mask
) != enable_rc6
)
6325 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
6326 "(requested %d, valid %d)\n",
6327 enable_rc6
& mask
, enable_rc6
, mask
);
6329 return enable_rc6
& mask
;
6332 if (IS_IVYBRIDGE(dev_priv
))
6333 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
6335 return INTEL_RC6_ENABLE
;
6338 static void gen6_init_rps_frequencies(struct drm_i915_private
*dev_priv
)
6340 /* All of these values are in units of 50MHz */
6342 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
6343 if (IS_GEN9_LP(dev_priv
)) {
6344 u32 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
6345 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 16) & 0xff;
6346 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
6347 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 0) & 0xff;
6349 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
6350 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 0) & 0xff;
6351 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
6352 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 16) & 0xff;
6354 /* hw_max = RP0 until we check for overclocking */
6355 dev_priv
->rps
.max_freq
= dev_priv
->rps
.rp0_freq
;
6357 dev_priv
->rps
.efficient_freq
= dev_priv
->rps
.rp1_freq
;
6358 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
) ||
6359 IS_GEN9_BC(dev_priv
)) {
6360 u32 ddcc_status
= 0;
6362 if (sandybridge_pcode_read(dev_priv
,
6363 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL
,
6365 dev_priv
->rps
.efficient_freq
=
6367 ((ddcc_status
>> 8) & 0xff),
6368 dev_priv
->rps
.min_freq
,
6369 dev_priv
->rps
.max_freq
);
6372 if (IS_GEN9_BC(dev_priv
)) {
6373 /* Store the frequency values in 16.66 MHZ units, which is
6374 * the natural hardware unit for SKL
6376 dev_priv
->rps
.rp0_freq
*= GEN9_FREQ_SCALER
;
6377 dev_priv
->rps
.rp1_freq
*= GEN9_FREQ_SCALER
;
6378 dev_priv
->rps
.min_freq
*= GEN9_FREQ_SCALER
;
6379 dev_priv
->rps
.max_freq
*= GEN9_FREQ_SCALER
;
6380 dev_priv
->rps
.efficient_freq
*= GEN9_FREQ_SCALER
;
6384 static void reset_rps(struct drm_i915_private
*dev_priv
,
6385 int (*set
)(struct drm_i915_private
*, u8
))
6387 u8 freq
= dev_priv
->rps
.cur_freq
;
6390 dev_priv
->rps
.power
= -1;
6391 dev_priv
->rps
.cur_freq
= -1;
6393 if (set(dev_priv
, freq
))
6394 DRM_ERROR("Failed to reset RPS to initial values\n");
6397 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
6398 static void gen9_enable_rps(struct drm_i915_private
*dev_priv
)
6400 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6402 /* Program defaults and thresholds for RPS*/
6403 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
6404 GEN9_FREQUENCY(dev_priv
->rps
.rp1_freq
));
6406 /* 1 second timeout*/
6407 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,
6408 GT_INTERVAL_FROM_US(dev_priv
, 1000000));
6410 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 0xa);
6412 /* Leaning on the below call to gen6_set_rps to program/setup the
6413 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
6414 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
6415 reset_rps(dev_priv
, gen6_set_rps
);
6417 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6420 static void gen9_enable_rc6(struct drm_i915_private
*dev_priv
)
6422 struct intel_engine_cs
*engine
;
6423 enum intel_engine_id id
;
6424 uint32_t rc6_mask
= 0;
6426 /* 1a: Software RC state - RC0 */
6427 I915_WRITE(GEN6_RC_STATE
, 0);
6429 /* 1b: Get forcewake during program sequence. Although the driver
6430 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6431 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6433 /* 2a: Disable RC states. */
6434 I915_WRITE(GEN6_RC_CONTROL
, 0);
6436 /* 2b: Program RC6 thresholds.*/
6438 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
6439 if (IS_SKYLAKE(dev_priv
))
6440 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 108 << 16);
6442 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 54 << 16);
6443 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
6444 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
6445 for_each_engine(engine
, dev_priv
, id
)
6446 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
6448 if (HAS_GUC(dev_priv
))
6449 I915_WRITE(GUC_MAX_IDLE_COUNT
, 0xA);
6451 I915_WRITE(GEN6_RC_SLEEP
, 0);
6453 /* 2c: Program Coarse Power Gating Policies. */
6454 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS
, 25);
6455 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS
, 25);
6457 /* 3a: Enable RC6 */
6458 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
6459 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
6460 DRM_INFO("RC6 %s\n", onoff(rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
));
6461 I915_WRITE(GEN6_RC6_THRESHOLD
, 37500); /* 37.5/125ms per EI */
6462 I915_WRITE(GEN6_RC_CONTROL
,
6463 GEN6_RC_CTL_HW_ENABLE
| GEN6_RC_CTL_EI_MODE(1) | rc6_mask
);
6466 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
6467 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
6469 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv
))
6470 I915_WRITE(GEN9_PG_ENABLE
, 0);
6472 I915_WRITE(GEN9_PG_ENABLE
, (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ?
6473 (GEN9_RENDER_PG_ENABLE
| GEN9_MEDIA_PG_ENABLE
) : 0);
6475 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6478 static void gen8_enable_rps(struct drm_i915_private
*dev_priv
)
6480 struct intel_engine_cs
*engine
;
6481 enum intel_engine_id id
;
6482 uint32_t rc6_mask
= 0;
6484 /* 1a: Software RC state - RC0 */
6485 I915_WRITE(GEN6_RC_STATE
, 0);
6487 /* 1c & 1d: Get forcewake during program sequence. Although the driver
6488 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6489 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6491 /* 2a: Disable RC states. */
6492 I915_WRITE(GEN6_RC_CONTROL
, 0);
6494 /* 2b: Program RC6 thresholds.*/
6495 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
6496 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
6497 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
6498 for_each_engine(engine
, dev_priv
, id
)
6499 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
6500 I915_WRITE(GEN6_RC_SLEEP
, 0);
6501 if (IS_BROADWELL(dev_priv
))
6502 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us/1.28 for TO */
6504 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
6507 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
6508 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
6509 intel_print_rc6_info(dev_priv
, rc6_mask
);
6510 if (IS_BROADWELL(dev_priv
))
6511 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
6512 GEN7_RC_CTL_TO_MODE
|
6515 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
6516 GEN6_RC_CTL_EI_MODE(1) |
6519 /* 4 Program defaults and thresholds for RPS*/
6520 I915_WRITE(GEN6_RPNSWREQ
,
6521 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
6522 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
6523 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
6524 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
6525 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 100000000 / 128); /* 1 second timeout */
6527 /* Docs recommend 900MHz, and 300 MHz respectively */
6528 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
6529 dev_priv
->rps
.max_freq_softlimit
<< 24 |
6530 dev_priv
->rps
.min_freq_softlimit
<< 16);
6532 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 7600000 / 128); /* 76ms busyness per EI, 90% */
6533 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 31300000 / 128); /* 313ms busyness per EI, 70%*/
6534 I915_WRITE(GEN6_RP_UP_EI
, 66000); /* 84.48ms, XXX: random? */
6535 I915_WRITE(GEN6_RP_DOWN_EI
, 350000); /* 448ms, XXX: random? */
6537 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
6540 I915_WRITE(GEN6_RP_CONTROL
,
6541 GEN6_RP_MEDIA_TURBO
|
6542 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
6543 GEN6_RP_MEDIA_IS_GFX
|
6545 GEN6_RP_UP_BUSY_AVG
|
6546 GEN6_RP_DOWN_IDLE_AVG
);
6548 /* 6: Ring frequency + overclocking (our driver does this later */
6550 reset_rps(dev_priv
, gen6_set_rps
);
6552 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6555 static void gen6_enable_rps(struct drm_i915_private
*dev_priv
)
6557 struct intel_engine_cs
*engine
;
6558 enum intel_engine_id id
;
6559 u32 rc6vids
, rc6_mask
= 0;
6564 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6566 /* Here begins a magic sequence of register writes to enable
6567 * auto-downclocking.
6569 * Perhaps there might be some value in exposing these to
6572 I915_WRITE(GEN6_RC_STATE
, 0);
6574 /* Clear the DBG now so we don't confuse earlier errors */
6575 gtfifodbg
= I915_READ(GTFIFODBG
);
6577 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
6578 I915_WRITE(GTFIFODBG
, gtfifodbg
);
6581 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6583 /* disable the counters and set deterministic thresholds */
6584 I915_WRITE(GEN6_RC_CONTROL
, 0);
6586 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
6587 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
6588 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
6589 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
6590 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
6592 for_each_engine(engine
, dev_priv
, id
)
6593 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
6595 I915_WRITE(GEN6_RC_SLEEP
, 0);
6596 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
6597 if (IS_IVYBRIDGE(dev_priv
))
6598 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
6600 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
6601 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
6602 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
6604 /* Check if we are enabling RC6 */
6605 rc6_mode
= intel_enable_rc6();
6606 if (rc6_mode
& INTEL_RC6_ENABLE
)
6607 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
6609 /* We don't use those on Haswell */
6610 if (!IS_HASWELL(dev_priv
)) {
6611 if (rc6_mode
& INTEL_RC6p_ENABLE
)
6612 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
6614 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
6615 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
6618 intel_print_rc6_info(dev_priv
, rc6_mask
);
6620 I915_WRITE(GEN6_RC_CONTROL
,
6622 GEN6_RC_CTL_EI_MODE(1) |
6623 GEN6_RC_CTL_HW_ENABLE
);
6625 /* Power down if completely idle for over 50ms */
6626 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
6627 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
6629 reset_rps(dev_priv
, gen6_set_rps
);
6632 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
6633 if (IS_GEN6(dev_priv
) && ret
) {
6634 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
6635 } else if (IS_GEN6(dev_priv
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
6636 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
6637 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
6638 rc6vids
&= 0xffff00;
6639 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
6640 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
6642 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
6645 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6648 static void gen6_update_ring_freq(struct drm_i915_private
*dev_priv
)
6651 unsigned int gpu_freq
;
6652 unsigned int max_ia_freq
, min_ring_freq
;
6653 unsigned int max_gpu_freq
, min_gpu_freq
;
6654 int scaling_factor
= 180;
6655 struct cpufreq_policy
*policy
;
6657 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6659 policy
= cpufreq_cpu_get(0);
6661 max_ia_freq
= policy
->cpuinfo
.max_freq
;
6662 cpufreq_cpu_put(policy
);
6665 * Default to measured freq if none found, PCU will ensure we
6668 max_ia_freq
= tsc_khz
;
6671 /* Convert from kHz to MHz */
6672 max_ia_freq
/= 1000;
6674 min_ring_freq
= I915_READ(DCLK
) & 0xf;
6675 /* convert DDR frequency from units of 266.6MHz to bandwidth */
6676 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
6678 if (IS_GEN9_BC(dev_priv
)) {
6679 /* Convert GT frequency to 50 HZ units */
6680 min_gpu_freq
= dev_priv
->rps
.min_freq
/ GEN9_FREQ_SCALER
;
6681 max_gpu_freq
= dev_priv
->rps
.max_freq
/ GEN9_FREQ_SCALER
;
6683 min_gpu_freq
= dev_priv
->rps
.min_freq
;
6684 max_gpu_freq
= dev_priv
->rps
.max_freq
;
6688 * For each potential GPU frequency, load a ring frequency we'd like
6689 * to use for memory access. We do this by specifying the IA frequency
6690 * the PCU should use as a reference to determine the ring frequency.
6692 for (gpu_freq
= max_gpu_freq
; gpu_freq
>= min_gpu_freq
; gpu_freq
--) {
6693 int diff
= max_gpu_freq
- gpu_freq
;
6694 unsigned int ia_freq
= 0, ring_freq
= 0;
6696 if (IS_GEN9_BC(dev_priv
)) {
6698 * ring_freq = 2 * GT. ring_freq is in 100MHz units
6699 * No floor required for ring frequency on SKL.
6701 ring_freq
= gpu_freq
;
6702 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
6703 /* max(2 * GT, DDR). NB: GT is 50MHz units */
6704 ring_freq
= max(min_ring_freq
, gpu_freq
);
6705 } else if (IS_HASWELL(dev_priv
)) {
6706 ring_freq
= mult_frac(gpu_freq
, 5, 4);
6707 ring_freq
= max(min_ring_freq
, ring_freq
);
6708 /* leave ia_freq as the default, chosen by cpufreq */
6710 /* On older processors, there is no separate ring
6711 * clock domain, so in order to boost the bandwidth
6712 * of the ring, we need to upclock the CPU (ia_freq).
6714 * For GPU frequencies less than 750MHz,
6715 * just use the lowest ring freq.
6717 if (gpu_freq
< min_freq
)
6720 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
6721 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
6724 sandybridge_pcode_write(dev_priv
,
6725 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
6726 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
6727 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
6732 static int cherryview_rps_max_freq(struct drm_i915_private
*dev_priv
)
6736 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
6738 switch (INTEL_INFO(dev_priv
)->sseu
.eu_total
) {
6740 /* (2 * 4) config */
6741 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT
);
6744 /* (2 * 6) config */
6745 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT
);
6748 /* (2 * 8) config */
6750 /* Setting (2 * 8) Min RP0 for any other combination */
6751 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT
);
6755 rp0
= (rp0
& FB_GFX_FREQ_FUSE_MASK
);
6760 static int cherryview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
6764 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_DUTYCYCLE_REG
);
6765 rpe
= (val
>> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT
) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK
;
6770 static int cherryview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
6774 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
6775 rp1
= (val
& FB_GFX_FREQ_FUSE_MASK
);
6780 static u32
cherryview_rps_min_freq(struct drm_i915_private
*dev_priv
)
6784 val
= vlv_punit_read(dev_priv
, FB_GFX_FMIN_AT_VMIN_FUSE
);
6785 rpn
= ((val
>> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT
) &
6786 FB_GFX_FREQ_FUSE_MASK
);
6791 static int valleyview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
6795 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
6797 rp1
= (val
& FB_GFX_FGUARANTEED_FREQ_FUSE_MASK
) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT
;
6802 static int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
6806 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
6808 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
6810 rp0
= min_t(u32
, rp0
, 0xea);
6815 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
6819 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
6820 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
6821 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
6822 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
6827 static int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
6831 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
6833 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
6834 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
6835 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
6836 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
6837 * to make sure it matches what Punit accepts.
6839 return max_t(u32
, val
, 0xc0);
6842 /* Check that the pctx buffer wasn't move under us. */
6843 static void valleyview_check_pctx(struct drm_i915_private
*dev_priv
)
6845 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
6847 WARN_ON(pctx_addr
!= dev_priv
->mm
.stolen_base
+
6848 dev_priv
->vlv_pctx
->stolen
->start
);
6852 /* Check that the pcbr address is not empty. */
6853 static void cherryview_check_pctx(struct drm_i915_private
*dev_priv
)
6855 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
6857 WARN_ON((pctx_addr
>> VLV_PCBR_ADDR_SHIFT
) == 0);
6860 static void cherryview_setup_pctx(struct drm_i915_private
*dev_priv
)
6862 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
6863 unsigned long pctx_paddr
, paddr
;
6865 int pctx_size
= 32*1024;
6867 pcbr
= I915_READ(VLV_PCBR
);
6868 if ((pcbr
>> VLV_PCBR_ADDR_SHIFT
) == 0) {
6869 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
6870 paddr
= (dev_priv
->mm
.stolen_base
+
6871 (ggtt
->stolen_size
- pctx_size
));
6873 pctx_paddr
= (paddr
& (~4095));
6874 I915_WRITE(VLV_PCBR
, pctx_paddr
);
6877 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
6880 static void valleyview_setup_pctx(struct drm_i915_private
*dev_priv
)
6882 struct drm_i915_gem_object
*pctx
;
6883 unsigned long pctx_paddr
;
6885 int pctx_size
= 24*1024;
6887 pcbr
= I915_READ(VLV_PCBR
);
6889 /* BIOS set it up already, grab the pre-alloc'd space */
6892 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
6893 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
,
6895 I915_GTT_OFFSET_NONE
,
6900 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
6903 * From the Gunit register HAS:
6904 * The Gfx driver is expected to program this register and ensure
6905 * proper allocation within Gfx stolen memory. For example, this
6906 * register should be programmed such than the PCBR range does not
6907 * overlap with other ranges, such as the frame buffer, protected
6908 * memory, or any other relevant ranges.
6910 pctx
= i915_gem_object_create_stolen(dev_priv
, pctx_size
);
6912 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
6916 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
6917 I915_WRITE(VLV_PCBR
, pctx_paddr
);
6920 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
6921 dev_priv
->vlv_pctx
= pctx
;
6924 static void valleyview_cleanup_pctx(struct drm_i915_private
*dev_priv
)
6926 if (WARN_ON(!dev_priv
->vlv_pctx
))
6929 i915_gem_object_put(dev_priv
->vlv_pctx
);
6930 dev_priv
->vlv_pctx
= NULL
;
6933 static void vlv_init_gpll_ref_freq(struct drm_i915_private
*dev_priv
)
6935 dev_priv
->rps
.gpll_ref_freq
=
6936 vlv_get_cck_clock(dev_priv
, "GPLL ref",
6937 CCK_GPLL_CLOCK_CONTROL
,
6938 dev_priv
->czclk_freq
);
6940 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
6941 dev_priv
->rps
.gpll_ref_freq
);
6944 static void valleyview_init_gt_powersave(struct drm_i915_private
*dev_priv
)
6948 valleyview_setup_pctx(dev_priv
);
6950 vlv_init_gpll_ref_freq(dev_priv
);
6952 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
6953 switch ((val
>> 6) & 3) {
6956 dev_priv
->mem_freq
= 800;
6959 dev_priv
->mem_freq
= 1066;
6962 dev_priv
->mem_freq
= 1333;
6965 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
6967 dev_priv
->rps
.max_freq
= valleyview_rps_max_freq(dev_priv
);
6968 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
6969 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
6970 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
6971 dev_priv
->rps
.max_freq
);
6973 dev_priv
->rps
.efficient_freq
= valleyview_rps_rpe_freq(dev_priv
);
6974 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
6975 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
6976 dev_priv
->rps
.efficient_freq
);
6978 dev_priv
->rps
.rp1_freq
= valleyview_rps_guar_freq(dev_priv
);
6979 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
6980 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
6981 dev_priv
->rps
.rp1_freq
);
6983 dev_priv
->rps
.min_freq
= valleyview_rps_min_freq(dev_priv
);
6984 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
6985 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
6986 dev_priv
->rps
.min_freq
);
6989 static void cherryview_init_gt_powersave(struct drm_i915_private
*dev_priv
)
6993 cherryview_setup_pctx(dev_priv
);
6995 vlv_init_gpll_ref_freq(dev_priv
);
6997 mutex_lock(&dev_priv
->sb_lock
);
6998 val
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
);
6999 mutex_unlock(&dev_priv
->sb_lock
);
7001 switch ((val
>> 2) & 0x7) {
7003 dev_priv
->mem_freq
= 2000;
7006 dev_priv
->mem_freq
= 1600;
7009 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
7011 dev_priv
->rps
.max_freq
= cherryview_rps_max_freq(dev_priv
);
7012 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
7013 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7014 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
7015 dev_priv
->rps
.max_freq
);
7017 dev_priv
->rps
.efficient_freq
= cherryview_rps_rpe_freq(dev_priv
);
7018 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7019 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
7020 dev_priv
->rps
.efficient_freq
);
7022 dev_priv
->rps
.rp1_freq
= cherryview_rps_guar_freq(dev_priv
);
7023 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7024 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
7025 dev_priv
->rps
.rp1_freq
);
7027 dev_priv
->rps
.min_freq
= cherryview_rps_min_freq(dev_priv
);
7028 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7029 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
7030 dev_priv
->rps
.min_freq
);
7032 WARN_ONCE((dev_priv
->rps
.max_freq
|
7033 dev_priv
->rps
.efficient_freq
|
7034 dev_priv
->rps
.rp1_freq
|
7035 dev_priv
->rps
.min_freq
) & 1,
7036 "Odd GPU freq values\n");
7039 static void valleyview_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
)
7041 valleyview_cleanup_pctx(dev_priv
);
7044 static void cherryview_enable_rps(struct drm_i915_private
*dev_priv
)
7046 struct intel_engine_cs
*engine
;
7047 enum intel_engine_id id
;
7048 u32 gtfifodbg
, val
, rc6_mode
= 0, pcbr
;
7050 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7052 gtfifodbg
= I915_READ(GTFIFODBG
) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV
|
7053 GT_FIFO_FREE_ENTRIES_CHV
);
7055 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
7057 I915_WRITE(GTFIFODBG
, gtfifodbg
);
7060 cherryview_check_pctx(dev_priv
);
7062 /* 1a & 1b: Get forcewake during program sequence. Although the driver
7063 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
7064 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
7066 /* Disable RC states. */
7067 I915_WRITE(GEN6_RC_CONTROL
, 0);
7069 /* 2a: Program RC6 thresholds.*/
7070 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
7071 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
7072 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
7074 for_each_engine(engine
, dev_priv
, id
)
7075 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
7076 I915_WRITE(GEN6_RC_SLEEP
, 0);
7078 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
7079 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x186);
7081 /* allows RC6 residency counter to work */
7082 I915_WRITE(VLV_COUNTER_CONTROL
,
7083 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
7084 VLV_MEDIA_RC6_COUNT_EN
|
7085 VLV_RENDER_RC6_COUNT_EN
));
7087 /* For now we assume BIOS is allocating and populating the PCBR */
7088 pcbr
= I915_READ(VLV_PCBR
);
7091 if ((intel_enable_rc6() & INTEL_RC6_ENABLE
) &&
7092 (pcbr
>> VLV_PCBR_ADDR_SHIFT
))
7093 rc6_mode
= GEN7_RC_CTL_TO_MODE
;
7095 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
7097 /* 4 Program defaults and thresholds for RPS*/
7098 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
7099 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
7100 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
7101 I915_WRITE(GEN6_RP_UP_EI
, 66000);
7102 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
7104 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
7107 I915_WRITE(GEN6_RP_CONTROL
,
7108 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
7109 GEN6_RP_MEDIA_IS_GFX
|
7111 GEN6_RP_UP_BUSY_AVG
|
7112 GEN6_RP_DOWN_IDLE_AVG
);
7114 /* Setting Fixed Bias */
7115 val
= VLV_OVERRIDE_EN
|
7117 CHV_BIAS_CPU_50_SOC_50
;
7118 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
7120 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
7122 /* RPS code assumes GPLL is used */
7123 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
7125 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
7126 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
7128 reset_rps(dev_priv
, valleyview_set_rps
);
7130 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
7133 static void valleyview_enable_rps(struct drm_i915_private
*dev_priv
)
7135 struct intel_engine_cs
*engine
;
7136 enum intel_engine_id id
;
7137 u32 gtfifodbg
, val
, rc6_mode
= 0;
7139 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7141 valleyview_check_pctx(dev_priv
);
7143 gtfifodbg
= I915_READ(GTFIFODBG
);
7145 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
7147 I915_WRITE(GTFIFODBG
, gtfifodbg
);
7150 /* If VLV, Forcewake all wells, else re-direct to regular path */
7151 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
7153 /* Disable RC states. */
7154 I915_WRITE(GEN6_RC_CONTROL
, 0);
7156 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
7157 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
7158 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
7159 I915_WRITE(GEN6_RP_UP_EI
, 66000);
7160 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
7162 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
7164 I915_WRITE(GEN6_RP_CONTROL
,
7165 GEN6_RP_MEDIA_TURBO
|
7166 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
7167 GEN6_RP_MEDIA_IS_GFX
|
7169 GEN6_RP_UP_BUSY_AVG
|
7170 GEN6_RP_DOWN_IDLE_CONT
);
7172 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
7173 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
7174 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
7176 for_each_engine(engine
, dev_priv
, id
)
7177 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
7179 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
7181 /* allows RC6 residency counter to work */
7182 I915_WRITE(VLV_COUNTER_CONTROL
,
7183 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
7184 VLV_MEDIA_RC0_COUNT_EN
|
7185 VLV_RENDER_RC0_COUNT_EN
|
7186 VLV_MEDIA_RC6_COUNT_EN
|
7187 VLV_RENDER_RC6_COUNT_EN
));
7189 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
7190 rc6_mode
= GEN7_RC_CTL_TO_MODE
| VLV_RC_CTL_CTX_RST_PARALLEL
;
7192 intel_print_rc6_info(dev_priv
, rc6_mode
);
7194 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
7196 /* Setting Fixed Bias */
7197 val
= VLV_OVERRIDE_EN
|
7199 VLV_BIAS_CPU_125_SOC_875
;
7200 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
7202 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
7204 /* RPS code assumes GPLL is used */
7205 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
7207 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
7208 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
7210 reset_rps(dev_priv
, valleyview_set_rps
);
7212 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
7215 static unsigned long intel_pxfreq(u32 vidfreq
)
7218 int div
= (vidfreq
& 0x3f0000) >> 16;
7219 int post
= (vidfreq
& 0x3000) >> 12;
7220 int pre
= (vidfreq
& 0x7);
7225 freq
= ((div
* 133333) / ((1<<post
) * pre
));
7230 static const struct cparams
{
7236 { 1, 1333, 301, 28664 },
7237 { 1, 1066, 294, 24460 },
7238 { 1, 800, 294, 25192 },
7239 { 0, 1333, 276, 27605 },
7240 { 0, 1066, 276, 27605 },
7241 { 0, 800, 231, 23784 },
7244 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
7246 u64 total_count
, diff
, ret
;
7247 u32 count1
, count2
, count3
, m
= 0, c
= 0;
7248 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
7251 lockdep_assert_held(&mchdev_lock
);
7253 diff1
= now
- dev_priv
->ips
.last_time1
;
7255 /* Prevent division-by-zero if we are asking too fast.
7256 * Also, we don't get interesting results if we are polling
7257 * faster than once in 10ms, so just return the saved value
7261 return dev_priv
->ips
.chipset_power
;
7263 count1
= I915_READ(DMIEC
);
7264 count2
= I915_READ(DDREC
);
7265 count3
= I915_READ(CSIEC
);
7267 total_count
= count1
+ count2
+ count3
;
7269 /* FIXME: handle per-counter overflow */
7270 if (total_count
< dev_priv
->ips
.last_count1
) {
7271 diff
= ~0UL - dev_priv
->ips
.last_count1
;
7272 diff
+= total_count
;
7274 diff
= total_count
- dev_priv
->ips
.last_count1
;
7277 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
7278 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
7279 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
7286 diff
= div_u64(diff
, diff1
);
7287 ret
= ((m
* diff
) + c
);
7288 ret
= div_u64(ret
, 10);
7290 dev_priv
->ips
.last_count1
= total_count
;
7291 dev_priv
->ips
.last_time1
= now
;
7293 dev_priv
->ips
.chipset_power
= ret
;
7298 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
7302 if (INTEL_INFO(dev_priv
)->gen
!= 5)
7305 spin_lock_irq(&mchdev_lock
);
7307 val
= __i915_chipset_val(dev_priv
);
7309 spin_unlock_irq(&mchdev_lock
);
7314 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
7316 unsigned long m
, x
, b
;
7319 tsfs
= I915_READ(TSFS
);
7321 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
7322 x
= I915_READ8(TR1
);
7324 b
= tsfs
& TSFS_INTR_MASK
;
7326 return ((m
* x
) / 127) - b
;
7329 static int _pxvid_to_vd(u8 pxvid
)
7334 if (pxvid
>= 8 && pxvid
< 31)
7337 return (pxvid
+ 2) * 125;
7340 static u32
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
7342 const int vd
= _pxvid_to_vd(pxvid
);
7343 const int vm
= vd
- 1125;
7345 if (INTEL_INFO(dev_priv
)->is_mobile
)
7346 return vm
> 0 ? vm
: 0;
7351 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
7353 u64 now
, diff
, diffms
;
7356 lockdep_assert_held(&mchdev_lock
);
7358 now
= ktime_get_raw_ns();
7359 diffms
= now
- dev_priv
->ips
.last_time2
;
7360 do_div(diffms
, NSEC_PER_MSEC
);
7362 /* Don't divide by 0 */
7366 count
= I915_READ(GFXEC
);
7368 if (count
< dev_priv
->ips
.last_count2
) {
7369 diff
= ~0UL - dev_priv
->ips
.last_count2
;
7372 diff
= count
- dev_priv
->ips
.last_count2
;
7375 dev_priv
->ips
.last_count2
= count
;
7376 dev_priv
->ips
.last_time2
= now
;
7378 /* More magic constants... */
7380 diff
= div_u64(diff
, diffms
* 10);
7381 dev_priv
->ips
.gfx_power
= diff
;
7384 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
7386 if (INTEL_INFO(dev_priv
)->gen
!= 5)
7389 spin_lock_irq(&mchdev_lock
);
7391 __i915_update_gfx_val(dev_priv
);
7393 spin_unlock_irq(&mchdev_lock
);
7396 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
7398 unsigned long t
, corr
, state1
, corr2
, state2
;
7401 lockdep_assert_held(&mchdev_lock
);
7403 pxvid
= I915_READ(PXVFREQ(dev_priv
->rps
.cur_freq
));
7404 pxvid
= (pxvid
>> 24) & 0x7f;
7405 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
7409 t
= i915_mch_val(dev_priv
);
7411 /* Revel in the empirically derived constants */
7413 /* Correction factor in 1/100000 units */
7415 corr
= ((t
* 2349) + 135940);
7417 corr
= ((t
* 964) + 29317);
7419 corr
= ((t
* 301) + 1004);
7421 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
7423 corr2
= (corr
* dev_priv
->ips
.corr
);
7425 state2
= (corr2
* state1
) / 10000;
7426 state2
/= 100; /* convert to mW */
7428 __i915_update_gfx_val(dev_priv
);
7430 return dev_priv
->ips
.gfx_power
+ state2
;
7433 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
7437 if (INTEL_INFO(dev_priv
)->gen
!= 5)
7440 spin_lock_irq(&mchdev_lock
);
7442 val
= __i915_gfx_val(dev_priv
);
7444 spin_unlock_irq(&mchdev_lock
);
7450 * i915_read_mch_val - return value for IPS use
7452 * Calculate and return a value for the IPS driver to use when deciding whether
7453 * we have thermal and power headroom to increase CPU or GPU power budget.
7455 unsigned long i915_read_mch_val(void)
7457 struct drm_i915_private
*dev_priv
;
7458 unsigned long chipset_val
, graphics_val
, ret
= 0;
7460 spin_lock_irq(&mchdev_lock
);
7463 dev_priv
= i915_mch_dev
;
7465 chipset_val
= __i915_chipset_val(dev_priv
);
7466 graphics_val
= __i915_gfx_val(dev_priv
);
7468 ret
= chipset_val
+ graphics_val
;
7471 spin_unlock_irq(&mchdev_lock
);
7475 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
7478 * i915_gpu_raise - raise GPU frequency limit
7480 * Raise the limit; IPS indicates we have thermal headroom.
7482 bool i915_gpu_raise(void)
7484 struct drm_i915_private
*dev_priv
;
7487 spin_lock_irq(&mchdev_lock
);
7488 if (!i915_mch_dev
) {
7492 dev_priv
= i915_mch_dev
;
7494 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
7495 dev_priv
->ips
.max_delay
--;
7498 spin_unlock_irq(&mchdev_lock
);
7502 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
7505 * i915_gpu_lower - lower GPU frequency limit
7507 * IPS indicates we're close to a thermal limit, so throttle back the GPU
7508 * frequency maximum.
7510 bool i915_gpu_lower(void)
7512 struct drm_i915_private
*dev_priv
;
7515 spin_lock_irq(&mchdev_lock
);
7516 if (!i915_mch_dev
) {
7520 dev_priv
= i915_mch_dev
;
7522 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
7523 dev_priv
->ips
.max_delay
++;
7526 spin_unlock_irq(&mchdev_lock
);
7530 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
7533 * i915_gpu_busy - indicate GPU business to IPS
7535 * Tell the IPS driver whether or not the GPU is busy.
7537 bool i915_gpu_busy(void)
7541 spin_lock_irq(&mchdev_lock
);
7543 ret
= i915_mch_dev
->gt
.awake
;
7544 spin_unlock_irq(&mchdev_lock
);
7548 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
7551 * i915_gpu_turbo_disable - disable graphics turbo
7553 * Disable graphics turbo by resetting the max frequency and setting the
7554 * current frequency to the default.
7556 bool i915_gpu_turbo_disable(void)
7558 struct drm_i915_private
*dev_priv
;
7561 spin_lock_irq(&mchdev_lock
);
7562 if (!i915_mch_dev
) {
7566 dev_priv
= i915_mch_dev
;
7568 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
7570 if (!ironlake_set_drps(dev_priv
, dev_priv
->ips
.fstart
))
7574 spin_unlock_irq(&mchdev_lock
);
7578 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
7581 * Tells the intel_ips driver that the i915 driver is now loaded, if
7582 * IPS got loaded first.
7584 * This awkward dance is so that neither module has to depend on the
7585 * other in order for IPS to do the appropriate communication of
7586 * GPU turbo limits to i915.
7589 ips_ping_for_i915_load(void)
7593 link
= symbol_get(ips_link_to_i915_driver
);
7596 symbol_put(ips_link_to_i915_driver
);
7600 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
7602 /* We only register the i915 ips part with intel-ips once everything is
7603 * set up, to avoid intel-ips sneaking in and reading bogus values. */
7604 spin_lock_irq(&mchdev_lock
);
7605 i915_mch_dev
= dev_priv
;
7606 spin_unlock_irq(&mchdev_lock
);
7608 ips_ping_for_i915_load();
7611 void intel_gpu_ips_teardown(void)
7613 spin_lock_irq(&mchdev_lock
);
7614 i915_mch_dev
= NULL
;
7615 spin_unlock_irq(&mchdev_lock
);
7618 static void intel_init_emon(struct drm_i915_private
*dev_priv
)
7624 /* Disable to program */
7628 /* Program energy weights for various events */
7629 I915_WRITE(SDEW
, 0x15040d00);
7630 I915_WRITE(CSIEW0
, 0x007f0000);
7631 I915_WRITE(CSIEW1
, 0x1e220004);
7632 I915_WRITE(CSIEW2
, 0x04000004);
7634 for (i
= 0; i
< 5; i
++)
7635 I915_WRITE(PEW(i
), 0);
7636 for (i
= 0; i
< 3; i
++)
7637 I915_WRITE(DEW(i
), 0);
7639 /* Program P-state weights to account for frequency power adjustment */
7640 for (i
= 0; i
< 16; i
++) {
7641 u32 pxvidfreq
= I915_READ(PXVFREQ(i
));
7642 unsigned long freq
= intel_pxfreq(pxvidfreq
);
7643 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
7648 val
*= (freq
/ 1000);
7650 val
/= (127*127*900);
7652 DRM_ERROR("bad pxval: %ld\n", val
);
7655 /* Render standby states get 0 weight */
7659 for (i
= 0; i
< 4; i
++) {
7660 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
7661 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
7662 I915_WRITE(PXW(i
), val
);
7665 /* Adjust magic regs to magic values (more experimental results) */
7666 I915_WRITE(OGW0
, 0);
7667 I915_WRITE(OGW1
, 0);
7668 I915_WRITE(EG0
, 0x00007f00);
7669 I915_WRITE(EG1
, 0x0000000e);
7670 I915_WRITE(EG2
, 0x000e0000);
7671 I915_WRITE(EG3
, 0x68000300);
7672 I915_WRITE(EG4
, 0x42000000);
7673 I915_WRITE(EG5
, 0x00140031);
7677 for (i
= 0; i
< 8; i
++)
7678 I915_WRITE(PXWL(i
), 0);
7680 /* Enable PMON + select events */
7681 I915_WRITE(ECR
, 0x80000019);
7683 lcfuse
= I915_READ(LCFUSE02
);
7685 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
7688 void intel_init_gt_powersave(struct drm_i915_private
*dev_priv
)
7691 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7694 if (!i915
.enable_rc6
) {
7695 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7696 intel_runtime_pm_get(dev_priv
);
7699 mutex_lock(&dev_priv
->drm
.struct_mutex
);
7700 mutex_lock(&dev_priv
->rps
.hw_lock
);
7702 /* Initialize RPS limits (for userspace) */
7703 if (IS_CHERRYVIEW(dev_priv
))
7704 cherryview_init_gt_powersave(dev_priv
);
7705 else if (IS_VALLEYVIEW(dev_priv
))
7706 valleyview_init_gt_powersave(dev_priv
);
7707 else if (INTEL_GEN(dev_priv
) >= 6)
7708 gen6_init_rps_frequencies(dev_priv
);
7710 /* Derive initial user preferences/limits from the hardware limits */
7711 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
7712 dev_priv
->rps
.cur_freq
= dev_priv
->rps
.idle_freq
;
7714 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
7715 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
7717 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
7718 dev_priv
->rps
.min_freq_softlimit
=
7720 dev_priv
->rps
.efficient_freq
,
7721 intel_freq_opcode(dev_priv
, 450));
7723 /* After setting max-softlimit, find the overclock max freq */
7724 if (IS_GEN6(dev_priv
) ||
7725 IS_IVYBRIDGE(dev_priv
) || IS_HASWELL(dev_priv
)) {
7728 sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, ¶ms
);
7729 if (params
& BIT(31)) { /* OC supported */
7730 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
7731 (dev_priv
->rps
.max_freq
& 0xff) * 50,
7732 (params
& 0xff) * 50);
7733 dev_priv
->rps
.max_freq
= params
& 0xff;
7737 /* Finally allow us to boost to max by default */
7738 dev_priv
->rps
.boost_freq
= dev_priv
->rps
.max_freq
;
7740 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7741 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
7743 intel_autoenable_gt_powersave(dev_priv
);
7746 void intel_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
)
7748 if (IS_VALLEYVIEW(dev_priv
))
7749 valleyview_cleanup_gt_powersave(dev_priv
);
7751 if (!i915
.enable_rc6
)
7752 intel_runtime_pm_put(dev_priv
);
7756 * intel_suspend_gt_powersave - suspend PM work and helper threads
7757 * @dev_priv: i915 device
7759 * We don't want to disable RC6 or other features here, we just want
7760 * to make sure any work we've queued has finished and won't bother
7761 * us while we're suspended.
7763 void intel_suspend_gt_powersave(struct drm_i915_private
*dev_priv
)
7765 if (INTEL_GEN(dev_priv
) < 6)
7768 if (cancel_delayed_work_sync(&dev_priv
->rps
.autoenable_work
))
7769 intel_runtime_pm_put(dev_priv
);
7771 /* gen6_rps_idle() will be called later to disable interrupts */
7774 void intel_sanitize_gt_powersave(struct drm_i915_private
*dev_priv
)
7776 dev_priv
->rps
.enabled
= true; /* force disabling */
7777 intel_disable_gt_powersave(dev_priv
);
7779 gen6_reset_rps_interrupts(dev_priv
);
7782 void intel_disable_gt_powersave(struct drm_i915_private
*dev_priv
)
7784 if (!READ_ONCE(dev_priv
->rps
.enabled
))
7787 mutex_lock(&dev_priv
->rps
.hw_lock
);
7789 if (INTEL_GEN(dev_priv
) >= 9) {
7790 gen9_disable_rc6(dev_priv
);
7791 gen9_disable_rps(dev_priv
);
7792 } else if (IS_CHERRYVIEW(dev_priv
)) {
7793 cherryview_disable_rps(dev_priv
);
7794 } else if (IS_VALLEYVIEW(dev_priv
)) {
7795 valleyview_disable_rps(dev_priv
);
7796 } else if (INTEL_GEN(dev_priv
) >= 6) {
7797 gen6_disable_rps(dev_priv
);
7798 } else if (IS_IRONLAKE_M(dev_priv
)) {
7799 ironlake_disable_drps(dev_priv
);
7802 dev_priv
->rps
.enabled
= false;
7803 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7806 void intel_enable_gt_powersave(struct drm_i915_private
*dev_priv
)
7808 /* We shouldn't be disabling as we submit, so this should be less
7809 * racy than it appears!
7811 if (READ_ONCE(dev_priv
->rps
.enabled
))
7814 /* Powersaving is controlled by the host when inside a VM */
7815 if (intel_vgpu_active(dev_priv
))
7818 mutex_lock(&dev_priv
->rps
.hw_lock
);
7820 if (IS_CHERRYVIEW(dev_priv
)) {
7821 cherryview_enable_rps(dev_priv
);
7822 } else if (IS_VALLEYVIEW(dev_priv
)) {
7823 valleyview_enable_rps(dev_priv
);
7824 } else if (INTEL_GEN(dev_priv
) >= 9) {
7825 gen9_enable_rc6(dev_priv
);
7826 gen9_enable_rps(dev_priv
);
7827 if (IS_GEN9_BC(dev_priv
))
7828 gen6_update_ring_freq(dev_priv
);
7829 } else if (IS_BROADWELL(dev_priv
)) {
7830 gen8_enable_rps(dev_priv
);
7831 gen6_update_ring_freq(dev_priv
);
7832 } else if (INTEL_GEN(dev_priv
) >= 6) {
7833 gen6_enable_rps(dev_priv
);
7834 gen6_update_ring_freq(dev_priv
);
7835 } else if (IS_IRONLAKE_M(dev_priv
)) {
7836 ironlake_enable_drps(dev_priv
);
7837 intel_init_emon(dev_priv
);
7840 WARN_ON(dev_priv
->rps
.max_freq
< dev_priv
->rps
.min_freq
);
7841 WARN_ON(dev_priv
->rps
.idle_freq
> dev_priv
->rps
.max_freq
);
7843 WARN_ON(dev_priv
->rps
.efficient_freq
< dev_priv
->rps
.min_freq
);
7844 WARN_ON(dev_priv
->rps
.efficient_freq
> dev_priv
->rps
.max_freq
);
7846 dev_priv
->rps
.enabled
= true;
7847 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7850 static void __intel_autoenable_gt_powersave(struct work_struct
*work
)
7852 struct drm_i915_private
*dev_priv
=
7853 container_of(work
, typeof(*dev_priv
), rps
.autoenable_work
.work
);
7854 struct intel_engine_cs
*rcs
;
7855 struct drm_i915_gem_request
*req
;
7857 if (READ_ONCE(dev_priv
->rps
.enabled
))
7860 rcs
= dev_priv
->engine
[RCS
];
7861 if (rcs
->last_retired_context
)
7864 if (!rcs
->init_context
)
7867 mutex_lock(&dev_priv
->drm
.struct_mutex
);
7869 req
= i915_gem_request_alloc(rcs
, dev_priv
->kernel_context
);
7873 if (!i915
.enable_execlists
&& i915_switch_context(req
) == 0)
7874 rcs
->init_context(req
);
7876 /* Mark the device busy, calling intel_enable_gt_powersave() */
7877 i915_add_request(req
);
7880 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
7882 intel_runtime_pm_put(dev_priv
);
7885 void intel_autoenable_gt_powersave(struct drm_i915_private
*dev_priv
)
7887 if (READ_ONCE(dev_priv
->rps
.enabled
))
7890 if (IS_IRONLAKE_M(dev_priv
)) {
7891 ironlake_enable_drps(dev_priv
);
7892 intel_init_emon(dev_priv
);
7893 } else if (INTEL_INFO(dev_priv
)->gen
>= 6) {
7895 * PCU communication is slow and this doesn't need to be
7896 * done at any specific time, so do this out of our fast path
7897 * to make resume and init faster.
7899 * We depend on the HW RC6 power context save/restore
7900 * mechanism when entering D3 through runtime PM suspend. So
7901 * disable RPM until RPS/RC6 is properly setup. We can only
7902 * get here via the driver load/system resume/runtime resume
7903 * paths, so the _noresume version is enough (and in case of
7904 * runtime resume it's necessary).
7906 if (queue_delayed_work(dev_priv
->wq
,
7907 &dev_priv
->rps
.autoenable_work
,
7908 round_jiffies_up_relative(HZ
)))
7909 intel_runtime_pm_get_noresume(dev_priv
);
7913 static void ibx_init_clock_gating(struct drm_i915_private
*dev_priv
)
7916 * On Ibex Peak and Cougar Point, we need to disable clock
7917 * gating for the panel power sequencer or it will fail to
7918 * start up when no ports are active.
7920 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
7923 static void g4x_disable_trickle_feed(struct drm_i915_private
*dev_priv
)
7927 for_each_pipe(dev_priv
, pipe
) {
7928 I915_WRITE(DSPCNTR(pipe
),
7929 I915_READ(DSPCNTR(pipe
)) |
7930 DISPPLANE_TRICKLE_FEED_DISABLE
);
7932 I915_WRITE(DSPSURF(pipe
), I915_READ(DSPSURF(pipe
)));
7933 POSTING_READ(DSPSURF(pipe
));
7937 static void ilk_init_lp_watermarks(struct drm_i915_private
*dev_priv
)
7939 I915_WRITE(WM3_LP_ILK
, I915_READ(WM3_LP_ILK
) & ~WM1_LP_SR_EN
);
7940 I915_WRITE(WM2_LP_ILK
, I915_READ(WM2_LP_ILK
) & ~WM1_LP_SR_EN
);
7941 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
7944 * Don't touch WM1S_LP_EN here.
7945 * Doing so could cause underruns.
7949 static void ironlake_init_clock_gating(struct drm_i915_private
*dev_priv
)
7951 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
7955 * WaFbcDisableDpfcClockGating:ilk
7957 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
7958 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
7959 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
7961 I915_WRITE(PCH_3DCGDIS0
,
7962 MARIUNIT_CLOCK_GATE_DISABLE
|
7963 SVSMUNIT_CLOCK_GATE_DISABLE
);
7964 I915_WRITE(PCH_3DCGDIS1
,
7965 VFMUNIT_CLOCK_GATE_DISABLE
);
7968 * According to the spec the following bits should be set in
7969 * order to enable memory self-refresh
7970 * The bit 22/21 of 0x42004
7971 * The bit 5 of 0x42020
7972 * The bit 15 of 0x45000
7974 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7975 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
7976 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
7977 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
7978 I915_WRITE(DISP_ARB_CTL
,
7979 (I915_READ(DISP_ARB_CTL
) |
7982 ilk_init_lp_watermarks(dev_priv
);
7985 * Based on the document from hardware guys the following bits
7986 * should be set unconditionally in order to enable FBC.
7987 * The bit 22 of 0x42000
7988 * The bit 22 of 0x42004
7989 * The bit 7,8,9 of 0x42020.
7991 if (IS_IRONLAKE_M(dev_priv
)) {
7992 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
7993 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
7994 I915_READ(ILK_DISPLAY_CHICKEN1
) |
7996 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7997 I915_READ(ILK_DISPLAY_CHICKEN2
) |
8001 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
8003 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8004 I915_READ(ILK_DISPLAY_CHICKEN2
) |
8005 ILK_ELPIN_409_SELECT
);
8006 I915_WRITE(_3D_CHICKEN2
,
8007 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
8008 _3D_CHICKEN2_WM_READ_PIPELINED
);
8010 /* WaDisableRenderCachePipelinedFlush:ilk */
8011 I915_WRITE(CACHE_MODE_0
,
8012 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
8014 /* WaDisable_RenderCache_OperationalFlush:ilk */
8015 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8017 g4x_disable_trickle_feed(dev_priv
);
8019 ibx_init_clock_gating(dev_priv
);
8022 static void cpt_init_clock_gating(struct drm_i915_private
*dev_priv
)
8028 * On Ibex Peak and Cougar Point, we need to disable clock
8029 * gating for the panel power sequencer or it will fail to
8030 * start up when no ports are active.
8032 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
8033 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
8034 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
8035 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
8036 DPLS_EDP_PPS_FIX_DIS
);
8037 /* The below fixes the weird display corruption, a few pixels shifted
8038 * downward, on (only) LVDS of some HP laptops with IVY.
8040 for_each_pipe(dev_priv
, pipe
) {
8041 val
= I915_READ(TRANS_CHICKEN2(pipe
));
8042 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
8043 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
8044 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
8045 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
8046 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
8047 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
8048 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
8049 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
8051 /* WADP0ClockGatingDisable */
8052 for_each_pipe(dev_priv
, pipe
) {
8053 I915_WRITE(TRANS_CHICKEN1(pipe
),
8054 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
8058 static void gen6_check_mch_setup(struct drm_i915_private
*dev_priv
)
8062 tmp
= I915_READ(MCH_SSKPD
);
8063 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
)
8064 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
8068 static void gen6_init_clock_gating(struct drm_i915_private
*dev_priv
)
8070 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
8072 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
8074 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8075 I915_READ(ILK_DISPLAY_CHICKEN2
) |
8076 ILK_ELPIN_409_SELECT
);
8078 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
8079 I915_WRITE(_3D_CHICKEN
,
8080 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
8082 /* WaDisable_RenderCache_OperationalFlush:snb */
8083 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8086 * BSpec recoomends 8x4 when MSAA is used,
8087 * however in practice 16x4 seems fastest.
8089 * Note that PS/WM thread counts depend on the WIZ hashing
8090 * disable bit, which we don't touch here, but it's good
8091 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8093 I915_WRITE(GEN6_GT_MODE
,
8094 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
8096 ilk_init_lp_watermarks(dev_priv
);
8098 I915_WRITE(CACHE_MODE_0
,
8099 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
8101 I915_WRITE(GEN6_UCGCTL1
,
8102 I915_READ(GEN6_UCGCTL1
) |
8103 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
8104 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
8106 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8107 * gating disable must be set. Failure to set it results in
8108 * flickering pixels due to Z write ordering failures after
8109 * some amount of runtime in the Mesa "fire" demo, and Unigine
8110 * Sanctuary and Tropics, and apparently anything else with
8111 * alpha test or pixel discard.
8113 * According to the spec, bit 11 (RCCUNIT) must also be set,
8114 * but we didn't debug actual testcases to find it out.
8116 * WaDisableRCCUnitClockGating:snb
8117 * WaDisableRCPBUnitClockGating:snb
8119 I915_WRITE(GEN6_UCGCTL2
,
8120 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
8121 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
8123 /* WaStripsFansDisableFastClipPerformanceFix:snb */
8124 I915_WRITE(_3D_CHICKEN3
,
8125 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
));
8129 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
8130 * 3DSTATE_SF number of SF output attributes is more than 16."
8132 I915_WRITE(_3D_CHICKEN3
,
8133 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH
));
8136 * According to the spec the following bits should be
8137 * set in order to enable memory self-refresh and fbc:
8138 * The bit21 and bit22 of 0x42000
8139 * The bit21 and bit22 of 0x42004
8140 * The bit5 and bit7 of 0x42020
8141 * The bit14 of 0x70180
8142 * The bit14 of 0x71180
8144 * WaFbcAsynchFlipDisableFbcQueue:snb
8146 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
8147 I915_READ(ILK_DISPLAY_CHICKEN1
) |
8148 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
8149 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8150 I915_READ(ILK_DISPLAY_CHICKEN2
) |
8151 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
8152 I915_WRITE(ILK_DSPCLK_GATE_D
,
8153 I915_READ(ILK_DSPCLK_GATE_D
) |
8154 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
8155 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
8157 g4x_disable_trickle_feed(dev_priv
);
8159 cpt_init_clock_gating(dev_priv
);
8161 gen6_check_mch_setup(dev_priv
);
8164 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
8166 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
8169 * WaVSThreadDispatchOverride:ivb,vlv
8171 * This actually overrides the dispatch
8172 * mode for all thread types.
8174 reg
&= ~GEN7_FF_SCHED_MASK
;
8175 reg
|= GEN7_FF_TS_SCHED_HW
;
8176 reg
|= GEN7_FF_VS_SCHED_HW
;
8177 reg
|= GEN7_FF_DS_SCHED_HW
;
8179 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
8182 static void lpt_init_clock_gating(struct drm_i915_private
*dev_priv
)
8185 * TODO: this bit should only be enabled when really needed, then
8186 * disabled when not needed anymore in order to save power.
8188 if (HAS_PCH_LPT_LP(dev_priv
))
8189 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
8190 I915_READ(SOUTH_DSPCLK_GATE_D
) |
8191 PCH_LP_PARTITION_LEVEL_DISABLE
);
8193 /* WADPOClockGatingDisable:hsw */
8194 I915_WRITE(TRANS_CHICKEN1(PIPE_A
),
8195 I915_READ(TRANS_CHICKEN1(PIPE_A
)) |
8196 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
8199 static void lpt_suspend_hw(struct drm_i915_private
*dev_priv
)
8201 if (HAS_PCH_LPT_LP(dev_priv
)) {
8202 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
8204 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
8205 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
8209 static void gen8_set_l3sqc_credits(struct drm_i915_private
*dev_priv
,
8210 int general_prio_credits
,
8211 int high_prio_credits
)
8215 /* WaTempDisableDOPClkGating:bdw */
8216 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
8217 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
8219 I915_WRITE(GEN8_L3SQCREG1
,
8220 L3_GENERAL_PRIO_CREDITS(general_prio_credits
) |
8221 L3_HIGH_PRIO_CREDITS(high_prio_credits
));
8224 * Wait at least 100 clocks before re-enabling clock gating.
8225 * See the definition of L3SQCREG1 in BSpec.
8227 POSTING_READ(GEN8_L3SQCREG1
);
8229 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
8232 static void kabylake_init_clock_gating(struct drm_i915_private
*dev_priv
)
8234 gen9_init_clock_gating(dev_priv
);
8236 /* WaDisableSDEUnitClockGating:kbl */
8237 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
8238 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
8239 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
8241 /* WaDisableGamClockGating:kbl */
8242 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
8243 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
8244 GEN6_GAMUNIT_CLOCK_GATE_DISABLE
);
8246 /* WaFbcNukeOnHostModify:kbl,cfl */
8247 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
8248 ILK_DPFC_NUKE_ON_ANY_MODIFICATION
);
8251 static void skylake_init_clock_gating(struct drm_i915_private
*dev_priv
)
8253 gen9_init_clock_gating(dev_priv
);
8255 /* WAC6entrylatency:skl */
8256 I915_WRITE(FBC_LLC_READ_CTRL
, I915_READ(FBC_LLC_READ_CTRL
) |
8257 FBC_LLC_FULLY_OPEN
);
8259 /* WaFbcNukeOnHostModify:skl */
8260 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
8261 ILK_DPFC_NUKE_ON_ANY_MODIFICATION
);
8264 static void broadwell_init_clock_gating(struct drm_i915_private
*dev_priv
)
8268 ilk_init_lp_watermarks(dev_priv
);
8270 /* WaSwitchSolVfFArbitrationPriority:bdw */
8271 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
8273 /* WaPsrDPAMaskVBlankInSRD:bdw */
8274 I915_WRITE(CHICKEN_PAR1_1
,
8275 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
8277 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
8278 for_each_pipe(dev_priv
, pipe
) {
8279 I915_WRITE(CHICKEN_PIPESL_1(pipe
),
8280 I915_READ(CHICKEN_PIPESL_1(pipe
)) |
8281 BDW_DPRS_MASK_VBLANK_SRD
);
8284 /* WaVSRefCountFullforceMissDisable:bdw */
8285 /* WaDSRefCountFullforceMissDisable:bdw */
8286 I915_WRITE(GEN7_FF_THREAD_MODE
,
8287 I915_READ(GEN7_FF_THREAD_MODE
) &
8288 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
8290 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
8291 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
8293 /* WaDisableSDEUnitClockGating:bdw */
8294 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
8295 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
8297 /* WaProgramL3SqcReg1Default:bdw */
8298 gen8_set_l3sqc_credits(dev_priv
, 30, 2);
8301 * WaGttCachingOffByDefault:bdw
8302 * GTT cache may not work with big pages, so if those
8303 * are ever enabled GTT cache may need to be disabled.
8305 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
8307 /* WaKVMNotificationOnConfigChange:bdw */
8308 I915_WRITE(CHICKEN_PAR2_1
, I915_READ(CHICKEN_PAR2_1
)
8309 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT
);
8311 lpt_init_clock_gating(dev_priv
);
8313 /* WaDisableDopClockGating:bdw
8315 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
8318 I915_WRITE(GEN6_UCGCTL1
,
8319 I915_READ(GEN6_UCGCTL1
) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE
);
8322 static void haswell_init_clock_gating(struct drm_i915_private
*dev_priv
)
8324 ilk_init_lp_watermarks(dev_priv
);
8326 /* L3 caching of data atomics doesn't work -- disable it. */
8327 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
8328 I915_WRITE(HSW_ROW_CHICKEN3
,
8329 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
8331 /* This is required by WaCatErrorRejectionIssue:hsw */
8332 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
8333 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
8334 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
8336 /* WaVSRefCountFullforceMissDisable:hsw */
8337 I915_WRITE(GEN7_FF_THREAD_MODE
,
8338 I915_READ(GEN7_FF_THREAD_MODE
) & ~GEN7_FF_VS_REF_CNT_FFME
);
8340 /* WaDisable_RenderCache_OperationalFlush:hsw */
8341 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8343 /* enable HiZ Raw Stall Optimization */
8344 I915_WRITE(CACHE_MODE_0_GEN7
,
8345 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
8347 /* WaDisable4x2SubspanOptimization:hsw */
8348 I915_WRITE(CACHE_MODE_1
,
8349 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
8352 * BSpec recommends 8x4 when MSAA is used,
8353 * however in practice 16x4 seems fastest.
8355 * Note that PS/WM thread counts depend on the WIZ hashing
8356 * disable bit, which we don't touch here, but it's good
8357 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8359 I915_WRITE(GEN7_GT_MODE
,
8360 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
8362 /* WaSampleCChickenBitEnable:hsw */
8363 I915_WRITE(HALF_SLICE_CHICKEN3
,
8364 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE
));
8366 /* WaSwitchSolVfFArbitrationPriority:hsw */
8367 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
8369 /* WaRsPkgCStateDisplayPMReq:hsw */
8370 I915_WRITE(CHICKEN_PAR1_1
,
8371 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
8373 lpt_init_clock_gating(dev_priv
);
8376 static void ivybridge_init_clock_gating(struct drm_i915_private
*dev_priv
)
8380 ilk_init_lp_watermarks(dev_priv
);
8382 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
8384 /* WaDisableEarlyCull:ivb */
8385 I915_WRITE(_3D_CHICKEN3
,
8386 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
8388 /* WaDisableBackToBackFlipFix:ivb */
8389 I915_WRITE(IVB_CHICKEN3
,
8390 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
8391 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
8393 /* WaDisablePSDDualDispatchEnable:ivb */
8394 if (IS_IVB_GT1(dev_priv
))
8395 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
8396 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
8398 /* WaDisable_RenderCache_OperationalFlush:ivb */
8399 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8401 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
8402 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
8403 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
8405 /* WaApplyL3ControlAndL3ChickenMode:ivb */
8406 I915_WRITE(GEN7_L3CNTLREG1
,
8407 GEN7_WA_FOR_GEN7_L3_CONTROL
);
8408 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
8409 GEN7_WA_L3_CHICKEN_MODE
);
8410 if (IS_IVB_GT1(dev_priv
))
8411 I915_WRITE(GEN7_ROW_CHICKEN2
,
8412 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
8414 /* must write both registers */
8415 I915_WRITE(GEN7_ROW_CHICKEN2
,
8416 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
8417 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
8418 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
8421 /* WaForceL3Serialization:ivb */
8422 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
8423 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
8426 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8427 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
8429 I915_WRITE(GEN6_UCGCTL2
,
8430 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
8432 /* This is required by WaCatErrorRejectionIssue:ivb */
8433 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
8434 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
8435 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
8437 g4x_disable_trickle_feed(dev_priv
);
8439 gen7_setup_fixed_func_scheduler(dev_priv
);
8441 if (0) { /* causes HiZ corruption on ivb:gt1 */
8442 /* enable HiZ Raw Stall Optimization */
8443 I915_WRITE(CACHE_MODE_0_GEN7
,
8444 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
8447 /* WaDisable4x2SubspanOptimization:ivb */
8448 I915_WRITE(CACHE_MODE_1
,
8449 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
8452 * BSpec recommends 8x4 when MSAA is used,
8453 * however in practice 16x4 seems fastest.
8455 * Note that PS/WM thread counts depend on the WIZ hashing
8456 * disable bit, which we don't touch here, but it's good
8457 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8459 I915_WRITE(GEN7_GT_MODE
,
8460 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
8462 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
8463 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
8464 snpcr
|= GEN6_MBC_SNPCR_MED
;
8465 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
8467 if (!HAS_PCH_NOP(dev_priv
))
8468 cpt_init_clock_gating(dev_priv
);
8470 gen6_check_mch_setup(dev_priv
);
8473 static void valleyview_init_clock_gating(struct drm_i915_private
*dev_priv
)
8475 /* WaDisableEarlyCull:vlv */
8476 I915_WRITE(_3D_CHICKEN3
,
8477 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
8479 /* WaDisableBackToBackFlipFix:vlv */
8480 I915_WRITE(IVB_CHICKEN3
,
8481 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
8482 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
8484 /* WaPsdDispatchEnable:vlv */
8485 /* WaDisablePSDDualDispatchEnable:vlv */
8486 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
8487 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
8488 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
8490 /* WaDisable_RenderCache_OperationalFlush:vlv */
8491 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8493 /* WaForceL3Serialization:vlv */
8494 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
8495 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
8497 /* WaDisableDopClockGating:vlv */
8498 I915_WRITE(GEN7_ROW_CHICKEN2
,
8499 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
8501 /* This is required by WaCatErrorRejectionIssue:vlv */
8502 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
8503 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
8504 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
8506 gen7_setup_fixed_func_scheduler(dev_priv
);
8509 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8510 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
8512 I915_WRITE(GEN6_UCGCTL2
,
8513 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
8515 /* WaDisableL3Bank2xClockGate:vlv
8516 * Disabling L3 clock gating- MMIO 940c[25] = 1
8517 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
8518 I915_WRITE(GEN7_UCGCTL4
,
8519 I915_READ(GEN7_UCGCTL4
) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
8522 * BSpec says this must be set, even though
8523 * WaDisable4x2SubspanOptimization isn't listed for VLV.
8525 I915_WRITE(CACHE_MODE_1
,
8526 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
8529 * BSpec recommends 8x4 when MSAA is used,
8530 * however in practice 16x4 seems fastest.
8532 * Note that PS/WM thread counts depend on the WIZ hashing
8533 * disable bit, which we don't touch here, but it's good
8534 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8536 I915_WRITE(GEN7_GT_MODE
,
8537 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
8540 * WaIncreaseL3CreditsForVLVB0:vlv
8541 * This is the hardware default actually.
8543 I915_WRITE(GEN7_L3SQCREG1
, VLV_B0_WA_L3SQCREG1_VALUE
);
8546 * WaDisableVLVClockGating_VBIIssue:vlv
8547 * Disable clock gating on th GCFG unit to prevent a delay
8548 * in the reporting of vblank events.
8550 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, GCFG_DIS
);
8553 static void cherryview_init_clock_gating(struct drm_i915_private
*dev_priv
)
8555 /* WaVSRefCountFullforceMissDisable:chv */
8556 /* WaDSRefCountFullforceMissDisable:chv */
8557 I915_WRITE(GEN7_FF_THREAD_MODE
,
8558 I915_READ(GEN7_FF_THREAD_MODE
) &
8559 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
8561 /* WaDisableSemaphoreAndSyncFlipWait:chv */
8562 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
8563 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
8565 /* WaDisableCSUnitClockGating:chv */
8566 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
8567 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
8569 /* WaDisableSDEUnitClockGating:chv */
8570 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
8571 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
8574 * WaProgramL3SqcReg1Default:chv
8575 * See gfxspecs/Related Documents/Performance Guide/
8576 * LSQC Setting Recommendations.
8578 gen8_set_l3sqc_credits(dev_priv
, 38, 2);
8581 * GTT cache may not work with big pages, so if those
8582 * are ever enabled GTT cache may need to be disabled.
8584 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
8587 static void g4x_init_clock_gating(struct drm_i915_private
*dev_priv
)
8589 uint32_t dspclk_gate
;
8591 I915_WRITE(RENCLK_GATE_D1
, 0);
8592 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
8593 GS_UNIT_CLOCK_GATE_DISABLE
|
8594 CL_UNIT_CLOCK_GATE_DISABLE
);
8595 I915_WRITE(RAMCLK_GATE_D
, 0);
8596 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
8597 OVRUNIT_CLOCK_GATE_DISABLE
|
8598 OVCUNIT_CLOCK_GATE_DISABLE
;
8599 if (IS_GM45(dev_priv
))
8600 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
8601 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
8603 /* WaDisableRenderCachePipelinedFlush */
8604 I915_WRITE(CACHE_MODE_0
,
8605 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
8607 /* WaDisable_RenderCache_OperationalFlush:g4x */
8608 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8610 g4x_disable_trickle_feed(dev_priv
);
8613 static void crestline_init_clock_gating(struct drm_i915_private
*dev_priv
)
8615 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
8616 I915_WRITE(RENCLK_GATE_D2
, 0);
8617 I915_WRITE(DSPCLK_GATE_D
, 0);
8618 I915_WRITE(RAMCLK_GATE_D
, 0);
8619 I915_WRITE16(DEUC
, 0);
8620 I915_WRITE(MI_ARB_STATE
,
8621 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
8623 /* WaDisable_RenderCache_OperationalFlush:gen4 */
8624 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8627 static void broadwater_init_clock_gating(struct drm_i915_private
*dev_priv
)
8629 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
8630 I965_RCC_CLOCK_GATE_DISABLE
|
8631 I965_RCPB_CLOCK_GATE_DISABLE
|
8632 I965_ISC_CLOCK_GATE_DISABLE
|
8633 I965_FBC_CLOCK_GATE_DISABLE
);
8634 I915_WRITE(RENCLK_GATE_D2
, 0);
8635 I915_WRITE(MI_ARB_STATE
,
8636 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
8638 /* WaDisable_RenderCache_OperationalFlush:gen4 */
8639 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8642 static void gen3_init_clock_gating(struct drm_i915_private
*dev_priv
)
8644 u32 dstate
= I915_READ(D_STATE
);
8646 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
8647 DSTATE_DOT_CLOCK_GATING
;
8648 I915_WRITE(D_STATE
, dstate
);
8650 if (IS_PINEVIEW(dev_priv
))
8651 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
8653 /* IIR "flip pending" means done if this bit is set */
8654 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
8656 /* interrupts should cause a wake up from C3 */
8657 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN
));
8659 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
8660 I915_WRITE(MI_ARB_STATE
, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
8662 I915_WRITE(MI_ARB_STATE
,
8663 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
8666 static void i85x_init_clock_gating(struct drm_i915_private
*dev_priv
)
8668 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
8670 /* interrupts should cause a wake up from C3 */
8671 I915_WRITE(MI_STATE
, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN
) |
8672 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE
));
8674 I915_WRITE(MEM_MODE
,
8675 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE
));
8678 static void i830_init_clock_gating(struct drm_i915_private
*dev_priv
)
8680 I915_WRITE(MEM_MODE
,
8681 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE
) |
8682 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE
));
8685 void intel_init_clock_gating(struct drm_i915_private
*dev_priv
)
8687 dev_priv
->display
.init_clock_gating(dev_priv
);
8690 void intel_suspend_hw(struct drm_i915_private
*dev_priv
)
8692 if (HAS_PCH_LPT(dev_priv
))
8693 lpt_suspend_hw(dev_priv
);
8696 static void nop_init_clock_gating(struct drm_i915_private
*dev_priv
)
8698 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
8702 * intel_init_clock_gating_hooks - setup the clock gating hooks
8703 * @dev_priv: device private
8705 * Setup the hooks that configure which clocks of a given platform can be
8706 * gated and also apply various GT and display specific workarounds for these
8707 * platforms. Note that some GT specific workarounds are applied separately
8708 * when GPU contexts or batchbuffers start their execution.
8710 void intel_init_clock_gating_hooks(struct drm_i915_private
*dev_priv
)
8712 if (IS_SKYLAKE(dev_priv
))
8713 dev_priv
->display
.init_clock_gating
= skylake_init_clock_gating
;
8714 else if (IS_KABYLAKE(dev_priv
) || IS_COFFEELAKE(dev_priv
))
8715 dev_priv
->display
.init_clock_gating
= kabylake_init_clock_gating
;
8716 else if (IS_BROXTON(dev_priv
))
8717 dev_priv
->display
.init_clock_gating
= bxt_init_clock_gating
;
8718 else if (IS_GEMINILAKE(dev_priv
))
8719 dev_priv
->display
.init_clock_gating
= glk_init_clock_gating
;
8720 else if (IS_BROADWELL(dev_priv
))
8721 dev_priv
->display
.init_clock_gating
= broadwell_init_clock_gating
;
8722 else if (IS_CHERRYVIEW(dev_priv
))
8723 dev_priv
->display
.init_clock_gating
= cherryview_init_clock_gating
;
8724 else if (IS_HASWELL(dev_priv
))
8725 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
8726 else if (IS_IVYBRIDGE(dev_priv
))
8727 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
8728 else if (IS_VALLEYVIEW(dev_priv
))
8729 dev_priv
->display
.init_clock_gating
= valleyview_init_clock_gating
;
8730 else if (IS_GEN6(dev_priv
))
8731 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
8732 else if (IS_GEN5(dev_priv
))
8733 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
8734 else if (IS_G4X(dev_priv
))
8735 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
8736 else if (IS_I965GM(dev_priv
))
8737 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
8738 else if (IS_I965G(dev_priv
))
8739 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
8740 else if (IS_GEN3(dev_priv
))
8741 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
8742 else if (IS_I85X(dev_priv
) || IS_I865G(dev_priv
))
8743 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
8744 else if (IS_GEN2(dev_priv
))
8745 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
8747 MISSING_CASE(INTEL_DEVID(dev_priv
));
8748 dev_priv
->display
.init_clock_gating
= nop_init_clock_gating
;
8752 /* Set up chip specific power management-related functions */
8753 void intel_init_pm(struct drm_i915_private
*dev_priv
)
8755 intel_fbc_init(dev_priv
);
8758 if (IS_PINEVIEW(dev_priv
))
8759 i915_pineview_get_mem_freq(dev_priv
);
8760 else if (IS_GEN5(dev_priv
))
8761 i915_ironlake_get_mem_freq(dev_priv
);
8763 /* For FIFO watermark updates */
8764 if (INTEL_GEN(dev_priv
) >= 9) {
8765 skl_setup_wm_latency(dev_priv
);
8766 dev_priv
->display
.initial_watermarks
= skl_initial_wm
;
8767 dev_priv
->display
.atomic_update_watermarks
= skl_atomic_update_crtc_wm
;
8768 dev_priv
->display
.compute_global_watermarks
= skl_compute_wm
;
8769 } else if (HAS_PCH_SPLIT(dev_priv
)) {
8770 ilk_setup_wm_latency(dev_priv
);
8772 if ((IS_GEN5(dev_priv
) && dev_priv
->wm
.pri_latency
[1] &&
8773 dev_priv
->wm
.spr_latency
[1] && dev_priv
->wm
.cur_latency
[1]) ||
8774 (!IS_GEN5(dev_priv
) && dev_priv
->wm
.pri_latency
[0] &&
8775 dev_priv
->wm
.spr_latency
[0] && dev_priv
->wm
.cur_latency
[0])) {
8776 dev_priv
->display
.compute_pipe_wm
= ilk_compute_pipe_wm
;
8777 dev_priv
->display
.compute_intermediate_wm
=
8778 ilk_compute_intermediate_wm
;
8779 dev_priv
->display
.initial_watermarks
=
8780 ilk_initial_watermarks
;
8781 dev_priv
->display
.optimize_watermarks
=
8782 ilk_optimize_watermarks
;
8784 DRM_DEBUG_KMS("Failed to read display plane latency. "
8787 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
8788 vlv_setup_wm_latency(dev_priv
);
8789 dev_priv
->display
.compute_pipe_wm
= vlv_compute_pipe_wm
;
8790 dev_priv
->display
.compute_intermediate_wm
= vlv_compute_intermediate_wm
;
8791 dev_priv
->display
.initial_watermarks
= vlv_initial_watermarks
;
8792 dev_priv
->display
.optimize_watermarks
= vlv_optimize_watermarks
;
8793 dev_priv
->display
.atomic_update_watermarks
= vlv_atomic_update_fifo
;
8794 } else if (IS_G4X(dev_priv
)) {
8795 g4x_setup_wm_latency(dev_priv
);
8796 dev_priv
->display
.compute_pipe_wm
= g4x_compute_pipe_wm
;
8797 dev_priv
->display
.compute_intermediate_wm
= g4x_compute_intermediate_wm
;
8798 dev_priv
->display
.initial_watermarks
= g4x_initial_watermarks
;
8799 dev_priv
->display
.optimize_watermarks
= g4x_optimize_watermarks
;
8800 } else if (IS_PINEVIEW(dev_priv
)) {
8801 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv
),
8804 dev_priv
->mem_freq
)) {
8805 DRM_INFO("failed to find known CxSR latency "
8806 "(found ddr%s fsb freq %d, mem freq %d), "
8808 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
8809 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
8810 /* Disable CxSR and never update its watermark again */
8811 intel_set_memory_cxsr(dev_priv
, false);
8812 dev_priv
->display
.update_wm
= NULL
;
8814 dev_priv
->display
.update_wm
= pineview_update_wm
;
8815 } else if (IS_GEN4(dev_priv
)) {
8816 dev_priv
->display
.update_wm
= i965_update_wm
;
8817 } else if (IS_GEN3(dev_priv
)) {
8818 dev_priv
->display
.update_wm
= i9xx_update_wm
;
8819 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
8820 } else if (IS_GEN2(dev_priv
)) {
8821 if (INTEL_INFO(dev_priv
)->num_pipes
== 1) {
8822 dev_priv
->display
.update_wm
= i845_update_wm
;
8823 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
8825 dev_priv
->display
.update_wm
= i9xx_update_wm
;
8826 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
8829 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
8833 static inline int gen6_check_mailbox_status(struct drm_i915_private
*dev_priv
)
8836 I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_ERROR_MASK
;
8839 case GEN6_PCODE_SUCCESS
:
8841 case GEN6_PCODE_UNIMPLEMENTED_CMD
:
8842 case GEN6_PCODE_ILLEGAL_CMD
:
8844 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
:
8845 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
:
8847 case GEN6_PCODE_TIMEOUT
:
8850 MISSING_CASE(flags
);
8855 static inline int gen7_check_mailbox_status(struct drm_i915_private
*dev_priv
)
8858 I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_ERROR_MASK
;
8861 case GEN6_PCODE_SUCCESS
:
8863 case GEN6_PCODE_ILLEGAL_CMD
:
8865 case GEN7_PCODE_TIMEOUT
:
8867 case GEN7_PCODE_ILLEGAL_DATA
:
8869 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
:
8872 MISSING_CASE(flags
);
8877 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
)
8881 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
8883 /* GEN6_PCODE_* are outside of the forcewake domain, we can
8884 * use te fw I915_READ variants to reduce the amount of work
8885 * required when reading/writing.
8888 if (I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
8889 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
8893 I915_WRITE_FW(GEN6_PCODE_DATA
, *val
);
8894 I915_WRITE_FW(GEN6_PCODE_DATA1
, 0);
8895 I915_WRITE_FW(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
8897 if (__intel_wait_for_register_fw(dev_priv
,
8898 GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
, 0,
8900 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
8904 *val
= I915_READ_FW(GEN6_PCODE_DATA
);
8905 I915_WRITE_FW(GEN6_PCODE_DATA
, 0);
8907 if (INTEL_GEN(dev_priv
) > 6)
8908 status
= gen7_check_mailbox_status(dev_priv
);
8910 status
= gen6_check_mailbox_status(dev_priv
);
8913 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
8921 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
,
8926 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
8928 /* GEN6_PCODE_* are outside of the forcewake domain, we can
8929 * use te fw I915_READ variants to reduce the amount of work
8930 * required when reading/writing.
8933 if (I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
8934 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
8938 I915_WRITE_FW(GEN6_PCODE_DATA
, val
);
8939 I915_WRITE_FW(GEN6_PCODE_DATA1
, 0);
8940 I915_WRITE_FW(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
8942 if (__intel_wait_for_register_fw(dev_priv
,
8943 GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
, 0,
8945 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
8949 I915_WRITE_FW(GEN6_PCODE_DATA
, 0);
8951 if (INTEL_GEN(dev_priv
) > 6)
8952 status
= gen7_check_mailbox_status(dev_priv
);
8954 status
= gen6_check_mailbox_status(dev_priv
);
8957 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
8965 static bool skl_pcode_try_request(struct drm_i915_private
*dev_priv
, u32 mbox
,
8966 u32 request
, u32 reply_mask
, u32 reply
,
8971 *status
= sandybridge_pcode_read(dev_priv
, mbox
, &val
);
8973 return *status
|| ((val
& reply_mask
) == reply
);
8977 * skl_pcode_request - send PCODE request until acknowledgment
8978 * @dev_priv: device private
8979 * @mbox: PCODE mailbox ID the request is targeted for
8980 * @request: request ID
8981 * @reply_mask: mask used to check for request acknowledgment
8982 * @reply: value used to check for request acknowledgment
8983 * @timeout_base_ms: timeout for polling with preemption enabled
8985 * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
8986 * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
8987 * The request is acknowledged once the PCODE reply dword equals @reply after
8988 * applying @reply_mask. Polling is first attempted with preemption enabled
8989 * for @timeout_base_ms and if this times out for another 50 ms with
8990 * preemption disabled.
8992 * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
8993 * other error as reported by PCODE.
8995 int skl_pcode_request(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 request
,
8996 u32 reply_mask
, u32 reply
, int timeout_base_ms
)
9001 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
9003 #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
9007 * Prime the PCODE by doing a request first. Normally it guarantees
9008 * that a subsequent request, at most @timeout_base_ms later, succeeds.
9009 * _wait_for() doesn't guarantee when its passed condition is evaluated
9010 * first, so send the first request explicitly.
9016 ret
= _wait_for(COND
, timeout_base_ms
* 1000, 10);
9021 * The above can time out if the number of requests was low (2 in the
9022 * worst case) _and_ PCODE was busy for some reason even after a
9023 * (queued) request and @timeout_base_ms delay. As a workaround retry
9024 * the poll with preemption disabled to maximize the number of
9025 * requests. Increase the timeout from @timeout_base_ms to 50ms to
9026 * account for interrupts that could reduce the number of these
9027 * requests, and for any quirks of the PCODE firmware that delays
9028 * the request completion.
9030 DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
9031 WARN_ON_ONCE(timeout_base_ms
> 3);
9033 ret
= wait_for_atomic(COND
, 50);
9037 return ret
? ret
: status
;
9041 static int byt_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
9045 * Slow = Fast = GPLL ref * N
9047 return DIV_ROUND_CLOSEST(dev_priv
->rps
.gpll_ref_freq
* (val
- 0xb7), 1000);
9050 static int byt_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
9052 return DIV_ROUND_CLOSEST(1000 * val
, dev_priv
->rps
.gpll_ref_freq
) + 0xb7;
9055 static int chv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
9059 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
9061 return DIV_ROUND_CLOSEST(dev_priv
->rps
.gpll_ref_freq
* val
, 2 * 2 * 1000);
9064 static int chv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
9066 /* CHV needs even values */
9067 return DIV_ROUND_CLOSEST(2 * 1000 * val
, dev_priv
->rps
.gpll_ref_freq
) * 2;
9070 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
9072 if (IS_GEN9(dev_priv
))
9073 return DIV_ROUND_CLOSEST(val
* GT_FREQUENCY_MULTIPLIER
,
9075 else if (IS_CHERRYVIEW(dev_priv
))
9076 return chv_gpu_freq(dev_priv
, val
);
9077 else if (IS_VALLEYVIEW(dev_priv
))
9078 return byt_gpu_freq(dev_priv
, val
);
9080 return val
* GT_FREQUENCY_MULTIPLIER
;
9083 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
9085 if (IS_GEN9(dev_priv
))
9086 return DIV_ROUND_CLOSEST(val
* GEN9_FREQ_SCALER
,
9087 GT_FREQUENCY_MULTIPLIER
);
9088 else if (IS_CHERRYVIEW(dev_priv
))
9089 return chv_freq_opcode(dev_priv
, val
);
9090 else if (IS_VALLEYVIEW(dev_priv
))
9091 return byt_freq_opcode(dev_priv
, val
);
9093 return DIV_ROUND_CLOSEST(val
, GT_FREQUENCY_MULTIPLIER
);
9096 struct request_boost
{
9097 struct work_struct work
;
9098 struct drm_i915_gem_request
*req
;
9101 static void __intel_rps_boost_work(struct work_struct
*work
)
9103 struct request_boost
*boost
= container_of(work
, struct request_boost
, work
);
9104 struct drm_i915_gem_request
*req
= boost
->req
;
9106 if (!i915_gem_request_completed(req
))
9107 gen6_rps_boost(req
->i915
, NULL
, req
->emitted_jiffies
);
9109 i915_gem_request_put(req
);
9113 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request
*req
)
9115 struct request_boost
*boost
;
9117 if (req
== NULL
|| INTEL_GEN(req
->i915
) < 6)
9120 if (i915_gem_request_completed(req
))
9123 boost
= kmalloc(sizeof(*boost
), GFP_ATOMIC
);
9127 boost
->req
= i915_gem_request_get(req
);
9129 INIT_WORK(&boost
->work
, __intel_rps_boost_work
);
9130 queue_work(req
->i915
->wq
, &boost
->work
);
9133 void intel_pm_setup(struct drm_i915_private
*dev_priv
)
9135 mutex_init(&dev_priv
->rps
.hw_lock
);
9136 spin_lock_init(&dev_priv
->rps
.client_lock
);
9138 INIT_DELAYED_WORK(&dev_priv
->rps
.autoenable_work
,
9139 __intel_autoenable_gt_powersave
);
9140 INIT_LIST_HEAD(&dev_priv
->rps
.clients
);
9142 dev_priv
->pm
.suspended
= false;
9143 atomic_set(&dev_priv
->pm
.wakeref_count
, 0);
9146 static u64
vlv_residency_raw(struct drm_i915_private
*dev_priv
,
9147 const i915_reg_t reg
)
9149 u32 lower
, upper
, tmp
;
9152 /* The register accessed do not need forcewake. We borrow
9153 * uncore lock to prevent concurrent access to range reg.
9155 spin_lock_irq(&dev_priv
->uncore
.lock
);
9157 /* vlv and chv residency counters are 40 bits in width.
9158 * With a control bit, we can choose between upper or lower
9159 * 32bit window into this counter.
9161 * Although we always use the counter in high-range mode elsewhere,
9162 * userspace may attempt to read the value before rc6 is initialised,
9163 * before we have set the default VLV_COUNTER_CONTROL value. So always
9164 * set the high bit to be safe.
9166 I915_WRITE_FW(VLV_COUNTER_CONTROL
,
9167 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
));
9168 upper
= I915_READ_FW(reg
);
9172 I915_WRITE_FW(VLV_COUNTER_CONTROL
,
9173 _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH
));
9174 lower
= I915_READ_FW(reg
);
9176 I915_WRITE_FW(VLV_COUNTER_CONTROL
,
9177 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
));
9178 upper
= I915_READ_FW(reg
);
9179 } while (upper
!= tmp
&& --loop
);
9181 /* Everywhere else we always use VLV_COUNTER_CONTROL with the
9182 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
9186 spin_unlock_irq(&dev_priv
->uncore
.lock
);
9188 return lower
| (u64
)upper
<< 8;
9191 u64
intel_rc6_residency_us(struct drm_i915_private
*dev_priv
,
9192 const i915_reg_t reg
)
9194 u64 time_hw
, units
, div
;
9196 if (!intel_enable_rc6())
9199 intel_runtime_pm_get(dev_priv
);
9201 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
9202 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
9204 div
= dev_priv
->czclk_freq
;
9206 time_hw
= vlv_residency_raw(dev_priv
, reg
);
9207 } else if (IS_GEN9_LP(dev_priv
)) {
9209 div
= 1200; /* 833.33ns */
9211 time_hw
= I915_READ(reg
);
9213 units
= 128000; /* 1.28us */
9216 time_hw
= I915_READ(reg
);
9219 intel_runtime_pm_put(dev_priv
);
9220 return DIV_ROUND_UP_ULL(time_hw
* units
, div
);