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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33
34 /**
35 * DOC: RC6
36 *
37 * RC6 is a special power stage which allows the GPU to enter an very
38 * low-voltage mode when idle, using down to 0V while at this stage. This
39 * stage is entered automatically when the GPU is idle when RC6 support is
40 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
41 *
42 * There are different RC6 modes available in Intel GPU, which differentiate
43 * among each other with the latency required to enter and leave RC6 and
44 * voltage consumed by the GPU in different states.
45 *
46 * The combination of the following flags define which states GPU is allowed
47 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
48 * RC6pp is deepest RC6. Their support by hardware varies according to the
49 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
50 * which brings the most power savings; deeper states save more power, but
51 * require higher latency to switch to and wake up.
52 */
53 #define INTEL_RC6_ENABLE (1<<0)
54 #define INTEL_RC6p_ENABLE (1<<1)
55 #define INTEL_RC6pp_ENABLE (1<<2)
56
57 static void bxt_init_clock_gating(struct drm_device *dev)
58 {
59 struct drm_i915_private *dev_priv = dev->dev_private;
60
61 /* WaDisableSDEUnitClockGating:bxt */
62 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
63 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
64
65 /*
66 * FIXME:
67 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
68 */
69 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
70 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
71
72 /*
73 * Wa: Backlight PWM may stop in the asserted state, causing backlight
74 * to stay fully on.
75 */
76 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
77 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
78 PWM1_GATING_DIS | PWM2_GATING_DIS);
79 }
80
81 static void i915_pineview_get_mem_freq(struct drm_device *dev)
82 {
83 struct drm_i915_private *dev_priv = dev->dev_private;
84 u32 tmp;
85
86 tmp = I915_READ(CLKCFG);
87
88 switch (tmp & CLKCFG_FSB_MASK) {
89 case CLKCFG_FSB_533:
90 dev_priv->fsb_freq = 533; /* 133*4 */
91 break;
92 case CLKCFG_FSB_800:
93 dev_priv->fsb_freq = 800; /* 200*4 */
94 break;
95 case CLKCFG_FSB_667:
96 dev_priv->fsb_freq = 667; /* 167*4 */
97 break;
98 case CLKCFG_FSB_400:
99 dev_priv->fsb_freq = 400; /* 100*4 */
100 break;
101 }
102
103 switch (tmp & CLKCFG_MEM_MASK) {
104 case CLKCFG_MEM_533:
105 dev_priv->mem_freq = 533;
106 break;
107 case CLKCFG_MEM_667:
108 dev_priv->mem_freq = 667;
109 break;
110 case CLKCFG_MEM_800:
111 dev_priv->mem_freq = 800;
112 break;
113 }
114
115 /* detect pineview DDR3 setting */
116 tmp = I915_READ(CSHRDDR3CTL);
117 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
118 }
119
120 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
121 {
122 struct drm_i915_private *dev_priv = dev->dev_private;
123 u16 ddrpll, csipll;
124
125 ddrpll = I915_READ16(DDRMPLL1);
126 csipll = I915_READ16(CSIPLL0);
127
128 switch (ddrpll & 0xff) {
129 case 0xc:
130 dev_priv->mem_freq = 800;
131 break;
132 case 0x10:
133 dev_priv->mem_freq = 1066;
134 break;
135 case 0x14:
136 dev_priv->mem_freq = 1333;
137 break;
138 case 0x18:
139 dev_priv->mem_freq = 1600;
140 break;
141 default:
142 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
143 ddrpll & 0xff);
144 dev_priv->mem_freq = 0;
145 break;
146 }
147
148 dev_priv->ips.r_t = dev_priv->mem_freq;
149
150 switch (csipll & 0x3ff) {
151 case 0x00c:
152 dev_priv->fsb_freq = 3200;
153 break;
154 case 0x00e:
155 dev_priv->fsb_freq = 3733;
156 break;
157 case 0x010:
158 dev_priv->fsb_freq = 4266;
159 break;
160 case 0x012:
161 dev_priv->fsb_freq = 4800;
162 break;
163 case 0x014:
164 dev_priv->fsb_freq = 5333;
165 break;
166 case 0x016:
167 dev_priv->fsb_freq = 5866;
168 break;
169 case 0x018:
170 dev_priv->fsb_freq = 6400;
171 break;
172 default:
173 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
174 csipll & 0x3ff);
175 dev_priv->fsb_freq = 0;
176 break;
177 }
178
179 if (dev_priv->fsb_freq == 3200) {
180 dev_priv->ips.c_m = 0;
181 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
182 dev_priv->ips.c_m = 1;
183 } else {
184 dev_priv->ips.c_m = 2;
185 }
186 }
187
188 static const struct cxsr_latency cxsr_latency_table[] = {
189 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
190 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
191 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
192 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
193 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
194
195 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
196 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
197 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
198 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
199 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
200
201 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
202 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
203 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
204 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
205 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
206
207 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
208 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
209 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
210 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
211 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
212
213 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
214 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
215 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
216 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
217 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
218
219 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
220 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
221 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
222 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
223 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
224 };
225
226 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
227 int is_ddr3,
228 int fsb,
229 int mem)
230 {
231 const struct cxsr_latency *latency;
232 int i;
233
234 if (fsb == 0 || mem == 0)
235 return NULL;
236
237 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
238 latency = &cxsr_latency_table[i];
239 if (is_desktop == latency->is_desktop &&
240 is_ddr3 == latency->is_ddr3 &&
241 fsb == latency->fsb_freq && mem == latency->mem_freq)
242 return latency;
243 }
244
245 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
246
247 return NULL;
248 }
249
250 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
251 {
252 u32 val;
253
254 mutex_lock(&dev_priv->rps.hw_lock);
255
256 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
257 if (enable)
258 val &= ~FORCE_DDR_HIGH_FREQ;
259 else
260 val |= FORCE_DDR_HIGH_FREQ;
261 val &= ~FORCE_DDR_LOW_FREQ;
262 val |= FORCE_DDR_FREQ_REQ_ACK;
263 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
264
265 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
266 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
267 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
268
269 mutex_unlock(&dev_priv->rps.hw_lock);
270 }
271
272 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
273 {
274 u32 val;
275
276 mutex_lock(&dev_priv->rps.hw_lock);
277
278 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
279 if (enable)
280 val |= DSP_MAXFIFO_PM5_ENABLE;
281 else
282 val &= ~DSP_MAXFIFO_PM5_ENABLE;
283 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
284
285 mutex_unlock(&dev_priv->rps.hw_lock);
286 }
287
288 #define FW_WM(value, plane) \
289 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
290
291 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
292 {
293 struct drm_device *dev = dev_priv->dev;
294 u32 val;
295
296 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
297 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
298 POSTING_READ(FW_BLC_SELF_VLV);
299 dev_priv->wm.vlv.cxsr = enable;
300 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
301 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
302 POSTING_READ(FW_BLC_SELF);
303 } else if (IS_PINEVIEW(dev)) {
304 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
305 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
306 I915_WRITE(DSPFW3, val);
307 POSTING_READ(DSPFW3);
308 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
309 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
310 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
311 I915_WRITE(FW_BLC_SELF, val);
312 POSTING_READ(FW_BLC_SELF);
313 } else if (IS_I915GM(dev)) {
314 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
315 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
316 I915_WRITE(INSTPM, val);
317 POSTING_READ(INSTPM);
318 } else {
319 return;
320 }
321
322 DRM_DEBUG_KMS("memory self-refresh is %s\n",
323 enable ? "enabled" : "disabled");
324 }
325
326
327 /*
328 * Latency for FIFO fetches is dependent on several factors:
329 * - memory configuration (speed, channels)
330 * - chipset
331 * - current MCH state
332 * It can be fairly high in some situations, so here we assume a fairly
333 * pessimal value. It's a tradeoff between extra memory fetches (if we
334 * set this value too high, the FIFO will fetch frequently to stay full)
335 * and power consumption (set it too low to save power and we might see
336 * FIFO underruns and display "flicker").
337 *
338 * A value of 5us seems to be a good balance; safe for very low end
339 * platforms but not overly aggressive on lower latency configs.
340 */
341 static const int pessimal_latency_ns = 5000;
342
343 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
344 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
345
346 static int vlv_get_fifo_size(struct drm_device *dev,
347 enum pipe pipe, int plane)
348 {
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 int sprite0_start, sprite1_start, size;
351
352 switch (pipe) {
353 uint32_t dsparb, dsparb2, dsparb3;
354 case PIPE_A:
355 dsparb = I915_READ(DSPARB);
356 dsparb2 = I915_READ(DSPARB2);
357 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
358 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
359 break;
360 case PIPE_B:
361 dsparb = I915_READ(DSPARB);
362 dsparb2 = I915_READ(DSPARB2);
363 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
364 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
365 break;
366 case PIPE_C:
367 dsparb2 = I915_READ(DSPARB2);
368 dsparb3 = I915_READ(DSPARB3);
369 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
370 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
371 break;
372 default:
373 return 0;
374 }
375
376 switch (plane) {
377 case 0:
378 size = sprite0_start;
379 break;
380 case 1:
381 size = sprite1_start - sprite0_start;
382 break;
383 case 2:
384 size = 512 - 1 - sprite1_start;
385 break;
386 default:
387 return 0;
388 }
389
390 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
391 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
392 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
393 size);
394
395 return size;
396 }
397
398 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
399 {
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t dsparb = I915_READ(DSPARB);
402 int size;
403
404 size = dsparb & 0x7f;
405 if (plane)
406 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
407
408 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
409 plane ? "B" : "A", size);
410
411 return size;
412 }
413
414 static int i830_get_fifo_size(struct drm_device *dev, int plane)
415 {
416 struct drm_i915_private *dev_priv = dev->dev_private;
417 uint32_t dsparb = I915_READ(DSPARB);
418 int size;
419
420 size = dsparb & 0x1ff;
421 if (plane)
422 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
423 size >>= 1; /* Convert to cachelines */
424
425 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
426 plane ? "B" : "A", size);
427
428 return size;
429 }
430
431 static int i845_get_fifo_size(struct drm_device *dev, int plane)
432 {
433 struct drm_i915_private *dev_priv = dev->dev_private;
434 uint32_t dsparb = I915_READ(DSPARB);
435 int size;
436
437 size = dsparb & 0x7f;
438 size >>= 2; /* Convert to cachelines */
439
440 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
441 plane ? "B" : "A",
442 size);
443
444 return size;
445 }
446
447 /* Pineview has different values for various configs */
448 static const struct intel_watermark_params pineview_display_wm = {
449 .fifo_size = PINEVIEW_DISPLAY_FIFO,
450 .max_wm = PINEVIEW_MAX_WM,
451 .default_wm = PINEVIEW_DFT_WM,
452 .guard_size = PINEVIEW_GUARD_WM,
453 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
454 };
455 static const struct intel_watermark_params pineview_display_hplloff_wm = {
456 .fifo_size = PINEVIEW_DISPLAY_FIFO,
457 .max_wm = PINEVIEW_MAX_WM,
458 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
459 .guard_size = PINEVIEW_GUARD_WM,
460 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
461 };
462 static const struct intel_watermark_params pineview_cursor_wm = {
463 .fifo_size = PINEVIEW_CURSOR_FIFO,
464 .max_wm = PINEVIEW_CURSOR_MAX_WM,
465 .default_wm = PINEVIEW_CURSOR_DFT_WM,
466 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
467 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
468 };
469 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
470 .fifo_size = PINEVIEW_CURSOR_FIFO,
471 .max_wm = PINEVIEW_CURSOR_MAX_WM,
472 .default_wm = PINEVIEW_CURSOR_DFT_WM,
473 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
474 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
475 };
476 static const struct intel_watermark_params g4x_wm_info = {
477 .fifo_size = G4X_FIFO_SIZE,
478 .max_wm = G4X_MAX_WM,
479 .default_wm = G4X_MAX_WM,
480 .guard_size = 2,
481 .cacheline_size = G4X_FIFO_LINE_SIZE,
482 };
483 static const struct intel_watermark_params g4x_cursor_wm_info = {
484 .fifo_size = I965_CURSOR_FIFO,
485 .max_wm = I965_CURSOR_MAX_WM,
486 .default_wm = I965_CURSOR_DFT_WM,
487 .guard_size = 2,
488 .cacheline_size = G4X_FIFO_LINE_SIZE,
489 };
490 static const struct intel_watermark_params i965_cursor_wm_info = {
491 .fifo_size = I965_CURSOR_FIFO,
492 .max_wm = I965_CURSOR_MAX_WM,
493 .default_wm = I965_CURSOR_DFT_WM,
494 .guard_size = 2,
495 .cacheline_size = I915_FIFO_LINE_SIZE,
496 };
497 static const struct intel_watermark_params i945_wm_info = {
498 .fifo_size = I945_FIFO_SIZE,
499 .max_wm = I915_MAX_WM,
500 .default_wm = 1,
501 .guard_size = 2,
502 .cacheline_size = I915_FIFO_LINE_SIZE,
503 };
504 static const struct intel_watermark_params i915_wm_info = {
505 .fifo_size = I915_FIFO_SIZE,
506 .max_wm = I915_MAX_WM,
507 .default_wm = 1,
508 .guard_size = 2,
509 .cacheline_size = I915_FIFO_LINE_SIZE,
510 };
511 static const struct intel_watermark_params i830_a_wm_info = {
512 .fifo_size = I855GM_FIFO_SIZE,
513 .max_wm = I915_MAX_WM,
514 .default_wm = 1,
515 .guard_size = 2,
516 .cacheline_size = I830_FIFO_LINE_SIZE,
517 };
518 static const struct intel_watermark_params i830_bc_wm_info = {
519 .fifo_size = I855GM_FIFO_SIZE,
520 .max_wm = I915_MAX_WM/2,
521 .default_wm = 1,
522 .guard_size = 2,
523 .cacheline_size = I830_FIFO_LINE_SIZE,
524 };
525 static const struct intel_watermark_params i845_wm_info = {
526 .fifo_size = I830_FIFO_SIZE,
527 .max_wm = I915_MAX_WM,
528 .default_wm = 1,
529 .guard_size = 2,
530 .cacheline_size = I830_FIFO_LINE_SIZE,
531 };
532
533 /**
534 * intel_calculate_wm - calculate watermark level
535 * @clock_in_khz: pixel clock
536 * @wm: chip FIFO params
537 * @cpp: bytes per pixel
538 * @latency_ns: memory latency for the platform
539 *
540 * Calculate the watermark level (the level at which the display plane will
541 * start fetching from memory again). Each chip has a different display
542 * FIFO size and allocation, so the caller needs to figure that out and pass
543 * in the correct intel_watermark_params structure.
544 *
545 * As the pixel clock runs, the FIFO will be drained at a rate that depends
546 * on the pixel size. When it reaches the watermark level, it'll start
547 * fetching FIFO line sized based chunks from memory until the FIFO fills
548 * past the watermark point. If the FIFO drains completely, a FIFO underrun
549 * will occur, and a display engine hang could result.
550 */
551 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
552 const struct intel_watermark_params *wm,
553 int fifo_size, int cpp,
554 unsigned long latency_ns)
555 {
556 long entries_required, wm_size;
557
558 /*
559 * Note: we need to make sure we don't overflow for various clock &
560 * latency values.
561 * clocks go from a few thousand to several hundred thousand.
562 * latency is usually a few thousand
563 */
564 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
565 1000;
566 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
567
568 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
569
570 wm_size = fifo_size - (entries_required + wm->guard_size);
571
572 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
573
574 /* Don't promote wm_size to unsigned... */
575 if (wm_size > (long)wm->max_wm)
576 wm_size = wm->max_wm;
577 if (wm_size <= 0)
578 wm_size = wm->default_wm;
579
580 /*
581 * Bspec seems to indicate that the value shouldn't be lower than
582 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
583 * Lets go for 8 which is the burst size since certain platforms
584 * already use a hardcoded 8 (which is what the spec says should be
585 * done).
586 */
587 if (wm_size <= 8)
588 wm_size = 8;
589
590 return wm_size;
591 }
592
593 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
594 {
595 struct drm_crtc *crtc, *enabled = NULL;
596
597 for_each_crtc(dev, crtc) {
598 if (intel_crtc_active(crtc)) {
599 if (enabled)
600 return NULL;
601 enabled = crtc;
602 }
603 }
604
605 return enabled;
606 }
607
608 static void pineview_update_wm(struct drm_crtc *unused_crtc)
609 {
610 struct drm_device *dev = unused_crtc->dev;
611 struct drm_i915_private *dev_priv = dev->dev_private;
612 struct drm_crtc *crtc;
613 const struct cxsr_latency *latency;
614 u32 reg;
615 unsigned long wm;
616
617 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
618 dev_priv->fsb_freq, dev_priv->mem_freq);
619 if (!latency) {
620 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
621 intel_set_memory_cxsr(dev_priv, false);
622 return;
623 }
624
625 crtc = single_enabled_crtc(dev);
626 if (crtc) {
627 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
628 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
629 int clock = adjusted_mode->crtc_clock;
630
631 /* Display SR */
632 wm = intel_calculate_wm(clock, &pineview_display_wm,
633 pineview_display_wm.fifo_size,
634 cpp, latency->display_sr);
635 reg = I915_READ(DSPFW1);
636 reg &= ~DSPFW_SR_MASK;
637 reg |= FW_WM(wm, SR);
638 I915_WRITE(DSPFW1, reg);
639 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
640
641 /* cursor SR */
642 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
643 pineview_display_wm.fifo_size,
644 cpp, latency->cursor_sr);
645 reg = I915_READ(DSPFW3);
646 reg &= ~DSPFW_CURSOR_SR_MASK;
647 reg |= FW_WM(wm, CURSOR_SR);
648 I915_WRITE(DSPFW3, reg);
649
650 /* Display HPLL off SR */
651 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
652 pineview_display_hplloff_wm.fifo_size,
653 cpp, latency->display_hpll_disable);
654 reg = I915_READ(DSPFW3);
655 reg &= ~DSPFW_HPLL_SR_MASK;
656 reg |= FW_WM(wm, HPLL_SR);
657 I915_WRITE(DSPFW3, reg);
658
659 /* cursor HPLL off SR */
660 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
661 pineview_display_hplloff_wm.fifo_size,
662 cpp, latency->cursor_hpll_disable);
663 reg = I915_READ(DSPFW3);
664 reg &= ~DSPFW_HPLL_CURSOR_MASK;
665 reg |= FW_WM(wm, HPLL_CURSOR);
666 I915_WRITE(DSPFW3, reg);
667 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
668
669 intel_set_memory_cxsr(dev_priv, true);
670 } else {
671 intel_set_memory_cxsr(dev_priv, false);
672 }
673 }
674
675 static bool g4x_compute_wm0(struct drm_device *dev,
676 int plane,
677 const struct intel_watermark_params *display,
678 int display_latency_ns,
679 const struct intel_watermark_params *cursor,
680 int cursor_latency_ns,
681 int *plane_wm,
682 int *cursor_wm)
683 {
684 struct drm_crtc *crtc;
685 const struct drm_display_mode *adjusted_mode;
686 int htotal, hdisplay, clock, cpp;
687 int line_time_us, line_count;
688 int entries, tlb_miss;
689
690 crtc = intel_get_crtc_for_plane(dev, plane);
691 if (!intel_crtc_active(crtc)) {
692 *cursor_wm = cursor->guard_size;
693 *plane_wm = display->guard_size;
694 return false;
695 }
696
697 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
698 clock = adjusted_mode->crtc_clock;
699 htotal = adjusted_mode->crtc_htotal;
700 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
701 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
702
703 /* Use the small buffer method to calculate plane watermark */
704 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
705 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
706 if (tlb_miss > 0)
707 entries += tlb_miss;
708 entries = DIV_ROUND_UP(entries, display->cacheline_size);
709 *plane_wm = entries + display->guard_size;
710 if (*plane_wm > (int)display->max_wm)
711 *plane_wm = display->max_wm;
712
713 /* Use the large buffer method to calculate cursor watermark */
714 line_time_us = max(htotal * 1000 / clock, 1);
715 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
716 entries = line_count * crtc->cursor->state->crtc_w * cpp;
717 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
718 if (tlb_miss > 0)
719 entries += tlb_miss;
720 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
721 *cursor_wm = entries + cursor->guard_size;
722 if (*cursor_wm > (int)cursor->max_wm)
723 *cursor_wm = (int)cursor->max_wm;
724
725 return true;
726 }
727
728 /*
729 * Check the wm result.
730 *
731 * If any calculated watermark values is larger than the maximum value that
732 * can be programmed into the associated watermark register, that watermark
733 * must be disabled.
734 */
735 static bool g4x_check_srwm(struct drm_device *dev,
736 int display_wm, int cursor_wm,
737 const struct intel_watermark_params *display,
738 const struct intel_watermark_params *cursor)
739 {
740 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
741 display_wm, cursor_wm);
742
743 if (display_wm > display->max_wm) {
744 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
745 display_wm, display->max_wm);
746 return false;
747 }
748
749 if (cursor_wm > cursor->max_wm) {
750 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
751 cursor_wm, cursor->max_wm);
752 return false;
753 }
754
755 if (!(display_wm || cursor_wm)) {
756 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
757 return false;
758 }
759
760 return true;
761 }
762
763 static bool g4x_compute_srwm(struct drm_device *dev,
764 int plane,
765 int latency_ns,
766 const struct intel_watermark_params *display,
767 const struct intel_watermark_params *cursor,
768 int *display_wm, int *cursor_wm)
769 {
770 struct drm_crtc *crtc;
771 const struct drm_display_mode *adjusted_mode;
772 int hdisplay, htotal, cpp, clock;
773 unsigned long line_time_us;
774 int line_count, line_size;
775 int small, large;
776 int entries;
777
778 if (!latency_ns) {
779 *display_wm = *cursor_wm = 0;
780 return false;
781 }
782
783 crtc = intel_get_crtc_for_plane(dev, plane);
784 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
785 clock = adjusted_mode->crtc_clock;
786 htotal = adjusted_mode->crtc_htotal;
787 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
788 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
789
790 line_time_us = max(htotal * 1000 / clock, 1);
791 line_count = (latency_ns / line_time_us + 1000) / 1000;
792 line_size = hdisplay * cpp;
793
794 /* Use the minimum of the small and large buffer method for primary */
795 small = ((clock * cpp / 1000) * latency_ns) / 1000;
796 large = line_count * line_size;
797
798 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
799 *display_wm = entries + display->guard_size;
800
801 /* calculate the self-refresh watermark for display cursor */
802 entries = line_count * cpp * crtc->cursor->state->crtc_w;
803 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
804 *cursor_wm = entries + cursor->guard_size;
805
806 return g4x_check_srwm(dev,
807 *display_wm, *cursor_wm,
808 display, cursor);
809 }
810
811 #define FW_WM_VLV(value, plane) \
812 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
813
814 static void vlv_write_wm_values(struct intel_crtc *crtc,
815 const struct vlv_wm_values *wm)
816 {
817 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
818 enum pipe pipe = crtc->pipe;
819
820 I915_WRITE(VLV_DDL(pipe),
821 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
822 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
823 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
824 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
825
826 I915_WRITE(DSPFW1,
827 FW_WM(wm->sr.plane, SR) |
828 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
829 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
830 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
831 I915_WRITE(DSPFW2,
832 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
833 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
834 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
835 I915_WRITE(DSPFW3,
836 FW_WM(wm->sr.cursor, CURSOR_SR));
837
838 if (IS_CHERRYVIEW(dev_priv)) {
839 I915_WRITE(DSPFW7_CHV,
840 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
841 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
842 I915_WRITE(DSPFW8_CHV,
843 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
844 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
845 I915_WRITE(DSPFW9_CHV,
846 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
847 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
848 I915_WRITE(DSPHOWM,
849 FW_WM(wm->sr.plane >> 9, SR_HI) |
850 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
851 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
852 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
853 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
854 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
855 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
856 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
857 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
858 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
859 } else {
860 I915_WRITE(DSPFW7,
861 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
862 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
863 I915_WRITE(DSPHOWM,
864 FW_WM(wm->sr.plane >> 9, SR_HI) |
865 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
866 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
867 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
868 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
869 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
870 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
871 }
872
873 /* zero (unused) WM1 watermarks */
874 I915_WRITE(DSPFW4, 0);
875 I915_WRITE(DSPFW5, 0);
876 I915_WRITE(DSPFW6, 0);
877 I915_WRITE(DSPHOWM1, 0);
878
879 POSTING_READ(DSPFW1);
880 }
881
882 #undef FW_WM_VLV
883
884 enum vlv_wm_level {
885 VLV_WM_LEVEL_PM2,
886 VLV_WM_LEVEL_PM5,
887 VLV_WM_LEVEL_DDR_DVFS,
888 };
889
890 /* latency must be in 0.1us units. */
891 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
892 unsigned int pipe_htotal,
893 unsigned int horiz_pixels,
894 unsigned int cpp,
895 unsigned int latency)
896 {
897 unsigned int ret;
898
899 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
900 ret = (ret + 1) * horiz_pixels * cpp;
901 ret = DIV_ROUND_UP(ret, 64);
902
903 return ret;
904 }
905
906 static void vlv_setup_wm_latency(struct drm_device *dev)
907 {
908 struct drm_i915_private *dev_priv = dev->dev_private;
909
910 /* all latencies in usec */
911 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
912
913 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
914
915 if (IS_CHERRYVIEW(dev_priv)) {
916 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
917 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
918
919 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
920 }
921 }
922
923 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
924 struct intel_crtc *crtc,
925 const struct intel_plane_state *state,
926 int level)
927 {
928 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
929 int clock, htotal, cpp, width, wm;
930
931 if (dev_priv->wm.pri_latency[level] == 0)
932 return USHRT_MAX;
933
934 if (!state->visible)
935 return 0;
936
937 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
938 clock = crtc->config->base.adjusted_mode.crtc_clock;
939 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
940 width = crtc->config->pipe_src_w;
941 if (WARN_ON(htotal == 0))
942 htotal = 1;
943
944 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
945 /*
946 * FIXME the formula gives values that are
947 * too big for the cursor FIFO, and hence we
948 * would never be able to use cursors. For
949 * now just hardcode the watermark.
950 */
951 wm = 63;
952 } else {
953 wm = vlv_wm_method2(clock, htotal, width, cpp,
954 dev_priv->wm.pri_latency[level] * 10);
955 }
956
957 return min_t(int, wm, USHRT_MAX);
958 }
959
960 static void vlv_compute_fifo(struct intel_crtc *crtc)
961 {
962 struct drm_device *dev = crtc->base.dev;
963 struct vlv_wm_state *wm_state = &crtc->wm_state;
964 struct intel_plane *plane;
965 unsigned int total_rate = 0;
966 const int fifo_size = 512 - 1;
967 int fifo_extra, fifo_left = fifo_size;
968
969 for_each_intel_plane_on_crtc(dev, crtc, plane) {
970 struct intel_plane_state *state =
971 to_intel_plane_state(plane->base.state);
972
973 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
974 continue;
975
976 if (state->visible) {
977 wm_state->num_active_planes++;
978 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
979 }
980 }
981
982 for_each_intel_plane_on_crtc(dev, crtc, plane) {
983 struct intel_plane_state *state =
984 to_intel_plane_state(plane->base.state);
985 unsigned int rate;
986
987 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
988 plane->wm.fifo_size = 63;
989 continue;
990 }
991
992 if (!state->visible) {
993 plane->wm.fifo_size = 0;
994 continue;
995 }
996
997 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
998 plane->wm.fifo_size = fifo_size * rate / total_rate;
999 fifo_left -= plane->wm.fifo_size;
1000 }
1001
1002 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1003
1004 /* spread the remainder evenly */
1005 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1006 int plane_extra;
1007
1008 if (fifo_left == 0)
1009 break;
1010
1011 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1012 continue;
1013
1014 /* give it all to the first plane if none are active */
1015 if (plane->wm.fifo_size == 0 &&
1016 wm_state->num_active_planes)
1017 continue;
1018
1019 plane_extra = min(fifo_extra, fifo_left);
1020 plane->wm.fifo_size += plane_extra;
1021 fifo_left -= plane_extra;
1022 }
1023
1024 WARN_ON(fifo_left != 0);
1025 }
1026
1027 static void vlv_invert_wms(struct intel_crtc *crtc)
1028 {
1029 struct vlv_wm_state *wm_state = &crtc->wm_state;
1030 int level;
1031
1032 for (level = 0; level < wm_state->num_levels; level++) {
1033 struct drm_device *dev = crtc->base.dev;
1034 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1035 struct intel_plane *plane;
1036
1037 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1038 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1039
1040 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1041 switch (plane->base.type) {
1042 int sprite;
1043 case DRM_PLANE_TYPE_CURSOR:
1044 wm_state->wm[level].cursor = plane->wm.fifo_size -
1045 wm_state->wm[level].cursor;
1046 break;
1047 case DRM_PLANE_TYPE_PRIMARY:
1048 wm_state->wm[level].primary = plane->wm.fifo_size -
1049 wm_state->wm[level].primary;
1050 break;
1051 case DRM_PLANE_TYPE_OVERLAY:
1052 sprite = plane->plane;
1053 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1054 wm_state->wm[level].sprite[sprite];
1055 break;
1056 }
1057 }
1058 }
1059 }
1060
1061 static void vlv_compute_wm(struct intel_crtc *crtc)
1062 {
1063 struct drm_device *dev = crtc->base.dev;
1064 struct vlv_wm_state *wm_state = &crtc->wm_state;
1065 struct intel_plane *plane;
1066 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1067 int level;
1068
1069 memset(wm_state, 0, sizeof(*wm_state));
1070
1071 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1072 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1073
1074 wm_state->num_active_planes = 0;
1075
1076 vlv_compute_fifo(crtc);
1077
1078 if (wm_state->num_active_planes != 1)
1079 wm_state->cxsr = false;
1080
1081 if (wm_state->cxsr) {
1082 for (level = 0; level < wm_state->num_levels; level++) {
1083 wm_state->sr[level].plane = sr_fifo_size;
1084 wm_state->sr[level].cursor = 63;
1085 }
1086 }
1087
1088 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1089 struct intel_plane_state *state =
1090 to_intel_plane_state(plane->base.state);
1091
1092 if (!state->visible)
1093 continue;
1094
1095 /* normal watermarks */
1096 for (level = 0; level < wm_state->num_levels; level++) {
1097 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1098 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1099
1100 /* hack */
1101 if (WARN_ON(level == 0 && wm > max_wm))
1102 wm = max_wm;
1103
1104 if (wm > plane->wm.fifo_size)
1105 break;
1106
1107 switch (plane->base.type) {
1108 int sprite;
1109 case DRM_PLANE_TYPE_CURSOR:
1110 wm_state->wm[level].cursor = wm;
1111 break;
1112 case DRM_PLANE_TYPE_PRIMARY:
1113 wm_state->wm[level].primary = wm;
1114 break;
1115 case DRM_PLANE_TYPE_OVERLAY:
1116 sprite = plane->plane;
1117 wm_state->wm[level].sprite[sprite] = wm;
1118 break;
1119 }
1120 }
1121
1122 wm_state->num_levels = level;
1123
1124 if (!wm_state->cxsr)
1125 continue;
1126
1127 /* maxfifo watermarks */
1128 switch (plane->base.type) {
1129 int sprite, level;
1130 case DRM_PLANE_TYPE_CURSOR:
1131 for (level = 0; level < wm_state->num_levels; level++)
1132 wm_state->sr[level].cursor =
1133 wm_state->wm[level].cursor;
1134 break;
1135 case DRM_PLANE_TYPE_PRIMARY:
1136 for (level = 0; level < wm_state->num_levels; level++)
1137 wm_state->sr[level].plane =
1138 min(wm_state->sr[level].plane,
1139 wm_state->wm[level].primary);
1140 break;
1141 case DRM_PLANE_TYPE_OVERLAY:
1142 sprite = plane->plane;
1143 for (level = 0; level < wm_state->num_levels; level++)
1144 wm_state->sr[level].plane =
1145 min(wm_state->sr[level].plane,
1146 wm_state->wm[level].sprite[sprite]);
1147 break;
1148 }
1149 }
1150
1151 /* clear any (partially) filled invalid levels */
1152 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1153 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1154 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1155 }
1156
1157 vlv_invert_wms(crtc);
1158 }
1159
1160 #define VLV_FIFO(plane, value) \
1161 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1162
1163 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1164 {
1165 struct drm_device *dev = crtc->base.dev;
1166 struct drm_i915_private *dev_priv = to_i915(dev);
1167 struct intel_plane *plane;
1168 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1169
1170 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1171 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1172 WARN_ON(plane->wm.fifo_size != 63);
1173 continue;
1174 }
1175
1176 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1177 sprite0_start = plane->wm.fifo_size;
1178 else if (plane->plane == 0)
1179 sprite1_start = sprite0_start + plane->wm.fifo_size;
1180 else
1181 fifo_size = sprite1_start + plane->wm.fifo_size;
1182 }
1183
1184 WARN_ON(fifo_size != 512 - 1);
1185
1186 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1187 pipe_name(crtc->pipe), sprite0_start,
1188 sprite1_start, fifo_size);
1189
1190 switch (crtc->pipe) {
1191 uint32_t dsparb, dsparb2, dsparb3;
1192 case PIPE_A:
1193 dsparb = I915_READ(DSPARB);
1194 dsparb2 = I915_READ(DSPARB2);
1195
1196 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1197 VLV_FIFO(SPRITEB, 0xff));
1198 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1199 VLV_FIFO(SPRITEB, sprite1_start));
1200
1201 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1202 VLV_FIFO(SPRITEB_HI, 0x1));
1203 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1204 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1205
1206 I915_WRITE(DSPARB, dsparb);
1207 I915_WRITE(DSPARB2, dsparb2);
1208 break;
1209 case PIPE_B:
1210 dsparb = I915_READ(DSPARB);
1211 dsparb2 = I915_READ(DSPARB2);
1212
1213 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1214 VLV_FIFO(SPRITED, 0xff));
1215 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1216 VLV_FIFO(SPRITED, sprite1_start));
1217
1218 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1219 VLV_FIFO(SPRITED_HI, 0xff));
1220 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1221 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1222
1223 I915_WRITE(DSPARB, dsparb);
1224 I915_WRITE(DSPARB2, dsparb2);
1225 break;
1226 case PIPE_C:
1227 dsparb3 = I915_READ(DSPARB3);
1228 dsparb2 = I915_READ(DSPARB2);
1229
1230 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1231 VLV_FIFO(SPRITEF, 0xff));
1232 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1233 VLV_FIFO(SPRITEF, sprite1_start));
1234
1235 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1236 VLV_FIFO(SPRITEF_HI, 0xff));
1237 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1238 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1239
1240 I915_WRITE(DSPARB3, dsparb3);
1241 I915_WRITE(DSPARB2, dsparb2);
1242 break;
1243 default:
1244 break;
1245 }
1246 }
1247
1248 #undef VLV_FIFO
1249
1250 static void vlv_merge_wm(struct drm_device *dev,
1251 struct vlv_wm_values *wm)
1252 {
1253 struct intel_crtc *crtc;
1254 int num_active_crtcs = 0;
1255
1256 wm->level = to_i915(dev)->wm.max_level;
1257 wm->cxsr = true;
1258
1259 for_each_intel_crtc(dev, crtc) {
1260 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1261
1262 if (!crtc->active)
1263 continue;
1264
1265 if (!wm_state->cxsr)
1266 wm->cxsr = false;
1267
1268 num_active_crtcs++;
1269 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1270 }
1271
1272 if (num_active_crtcs != 1)
1273 wm->cxsr = false;
1274
1275 if (num_active_crtcs > 1)
1276 wm->level = VLV_WM_LEVEL_PM2;
1277
1278 for_each_intel_crtc(dev, crtc) {
1279 struct vlv_wm_state *wm_state = &crtc->wm_state;
1280 enum pipe pipe = crtc->pipe;
1281
1282 if (!crtc->active)
1283 continue;
1284
1285 wm->pipe[pipe] = wm_state->wm[wm->level];
1286 if (wm->cxsr)
1287 wm->sr = wm_state->sr[wm->level];
1288
1289 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1290 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1291 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1292 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1293 }
1294 }
1295
1296 static void vlv_update_wm(struct drm_crtc *crtc)
1297 {
1298 struct drm_device *dev = crtc->dev;
1299 struct drm_i915_private *dev_priv = dev->dev_private;
1300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1301 enum pipe pipe = intel_crtc->pipe;
1302 struct vlv_wm_values wm = {};
1303
1304 vlv_compute_wm(intel_crtc);
1305 vlv_merge_wm(dev, &wm);
1306
1307 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1308 /* FIXME should be part of crtc atomic commit */
1309 vlv_pipe_set_fifo_size(intel_crtc);
1310 return;
1311 }
1312
1313 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1314 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1315 chv_set_memory_dvfs(dev_priv, false);
1316
1317 if (wm.level < VLV_WM_LEVEL_PM5 &&
1318 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1319 chv_set_memory_pm5(dev_priv, false);
1320
1321 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1322 intel_set_memory_cxsr(dev_priv, false);
1323
1324 /* FIXME should be part of crtc atomic commit */
1325 vlv_pipe_set_fifo_size(intel_crtc);
1326
1327 vlv_write_wm_values(intel_crtc, &wm);
1328
1329 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1330 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1331 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1332 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1333 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1334
1335 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1336 intel_set_memory_cxsr(dev_priv, true);
1337
1338 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1339 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1340 chv_set_memory_pm5(dev_priv, true);
1341
1342 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1343 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1344 chv_set_memory_dvfs(dev_priv, true);
1345
1346 dev_priv->wm.vlv = wm;
1347 }
1348
1349 #define single_plane_enabled(mask) is_power_of_2(mask)
1350
1351 static void g4x_update_wm(struct drm_crtc *crtc)
1352 {
1353 struct drm_device *dev = crtc->dev;
1354 static const int sr_latency_ns = 12000;
1355 struct drm_i915_private *dev_priv = dev->dev_private;
1356 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1357 int plane_sr, cursor_sr;
1358 unsigned int enabled = 0;
1359 bool cxsr_enabled;
1360
1361 if (g4x_compute_wm0(dev, PIPE_A,
1362 &g4x_wm_info, pessimal_latency_ns,
1363 &g4x_cursor_wm_info, pessimal_latency_ns,
1364 &planea_wm, &cursora_wm))
1365 enabled |= 1 << PIPE_A;
1366
1367 if (g4x_compute_wm0(dev, PIPE_B,
1368 &g4x_wm_info, pessimal_latency_ns,
1369 &g4x_cursor_wm_info, pessimal_latency_ns,
1370 &planeb_wm, &cursorb_wm))
1371 enabled |= 1 << PIPE_B;
1372
1373 if (single_plane_enabled(enabled) &&
1374 g4x_compute_srwm(dev, ffs(enabled) - 1,
1375 sr_latency_ns,
1376 &g4x_wm_info,
1377 &g4x_cursor_wm_info,
1378 &plane_sr, &cursor_sr)) {
1379 cxsr_enabled = true;
1380 } else {
1381 cxsr_enabled = false;
1382 intel_set_memory_cxsr(dev_priv, false);
1383 plane_sr = cursor_sr = 0;
1384 }
1385
1386 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1387 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1388 planea_wm, cursora_wm,
1389 planeb_wm, cursorb_wm,
1390 plane_sr, cursor_sr);
1391
1392 I915_WRITE(DSPFW1,
1393 FW_WM(plane_sr, SR) |
1394 FW_WM(cursorb_wm, CURSORB) |
1395 FW_WM(planeb_wm, PLANEB) |
1396 FW_WM(planea_wm, PLANEA));
1397 I915_WRITE(DSPFW2,
1398 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1399 FW_WM(cursora_wm, CURSORA));
1400 /* HPLL off in SR has some issues on G4x... disable it */
1401 I915_WRITE(DSPFW3,
1402 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1403 FW_WM(cursor_sr, CURSOR_SR));
1404
1405 if (cxsr_enabled)
1406 intel_set_memory_cxsr(dev_priv, true);
1407 }
1408
1409 static void i965_update_wm(struct drm_crtc *unused_crtc)
1410 {
1411 struct drm_device *dev = unused_crtc->dev;
1412 struct drm_i915_private *dev_priv = dev->dev_private;
1413 struct drm_crtc *crtc;
1414 int srwm = 1;
1415 int cursor_sr = 16;
1416 bool cxsr_enabled;
1417
1418 /* Calc sr entries for one plane configs */
1419 crtc = single_enabled_crtc(dev);
1420 if (crtc) {
1421 /* self-refresh has much higher latency */
1422 static const int sr_latency_ns = 12000;
1423 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1424 int clock = adjusted_mode->crtc_clock;
1425 int htotal = adjusted_mode->crtc_htotal;
1426 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1427 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1428 unsigned long line_time_us;
1429 int entries;
1430
1431 line_time_us = max(htotal * 1000 / clock, 1);
1432
1433 /* Use ns/us then divide to preserve precision */
1434 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1435 cpp * hdisplay;
1436 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1437 srwm = I965_FIFO_SIZE - entries;
1438 if (srwm < 0)
1439 srwm = 1;
1440 srwm &= 0x1ff;
1441 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1442 entries, srwm);
1443
1444 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1445 cpp * crtc->cursor->state->crtc_w;
1446 entries = DIV_ROUND_UP(entries,
1447 i965_cursor_wm_info.cacheline_size);
1448 cursor_sr = i965_cursor_wm_info.fifo_size -
1449 (entries + i965_cursor_wm_info.guard_size);
1450
1451 if (cursor_sr > i965_cursor_wm_info.max_wm)
1452 cursor_sr = i965_cursor_wm_info.max_wm;
1453
1454 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1455 "cursor %d\n", srwm, cursor_sr);
1456
1457 cxsr_enabled = true;
1458 } else {
1459 cxsr_enabled = false;
1460 /* Turn off self refresh if both pipes are enabled */
1461 intel_set_memory_cxsr(dev_priv, false);
1462 }
1463
1464 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1465 srwm);
1466
1467 /* 965 has limitations... */
1468 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1469 FW_WM(8, CURSORB) |
1470 FW_WM(8, PLANEB) |
1471 FW_WM(8, PLANEA));
1472 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1473 FW_WM(8, PLANEC_OLD));
1474 /* update cursor SR watermark */
1475 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1476
1477 if (cxsr_enabled)
1478 intel_set_memory_cxsr(dev_priv, true);
1479 }
1480
1481 #undef FW_WM
1482
1483 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1484 {
1485 struct drm_device *dev = unused_crtc->dev;
1486 struct drm_i915_private *dev_priv = dev->dev_private;
1487 const struct intel_watermark_params *wm_info;
1488 uint32_t fwater_lo;
1489 uint32_t fwater_hi;
1490 int cwm, srwm = 1;
1491 int fifo_size;
1492 int planea_wm, planeb_wm;
1493 struct drm_crtc *crtc, *enabled = NULL;
1494
1495 if (IS_I945GM(dev))
1496 wm_info = &i945_wm_info;
1497 else if (!IS_GEN2(dev))
1498 wm_info = &i915_wm_info;
1499 else
1500 wm_info = &i830_a_wm_info;
1501
1502 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1503 crtc = intel_get_crtc_for_plane(dev, 0);
1504 if (intel_crtc_active(crtc)) {
1505 const struct drm_display_mode *adjusted_mode;
1506 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1507 if (IS_GEN2(dev))
1508 cpp = 4;
1509
1510 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1511 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1512 wm_info, fifo_size, cpp,
1513 pessimal_latency_ns);
1514 enabled = crtc;
1515 } else {
1516 planea_wm = fifo_size - wm_info->guard_size;
1517 if (planea_wm > (long)wm_info->max_wm)
1518 planea_wm = wm_info->max_wm;
1519 }
1520
1521 if (IS_GEN2(dev))
1522 wm_info = &i830_bc_wm_info;
1523
1524 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1525 crtc = intel_get_crtc_for_plane(dev, 1);
1526 if (intel_crtc_active(crtc)) {
1527 const struct drm_display_mode *adjusted_mode;
1528 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1529 if (IS_GEN2(dev))
1530 cpp = 4;
1531
1532 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1533 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1534 wm_info, fifo_size, cpp,
1535 pessimal_latency_ns);
1536 if (enabled == NULL)
1537 enabled = crtc;
1538 else
1539 enabled = NULL;
1540 } else {
1541 planeb_wm = fifo_size - wm_info->guard_size;
1542 if (planeb_wm > (long)wm_info->max_wm)
1543 planeb_wm = wm_info->max_wm;
1544 }
1545
1546 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547
1548 if (IS_I915GM(dev) && enabled) {
1549 struct drm_i915_gem_object *obj;
1550
1551 obj = intel_fb_obj(enabled->primary->state->fb);
1552
1553 /* self-refresh seems busted with untiled */
1554 if (obj->tiling_mode == I915_TILING_NONE)
1555 enabled = NULL;
1556 }
1557
1558 /*
1559 * Overlay gets an aggressive default since video jitter is bad.
1560 */
1561 cwm = 2;
1562
1563 /* Play safe and disable self-refresh before adjusting watermarks. */
1564 intel_set_memory_cxsr(dev_priv, false);
1565
1566 /* Calc sr entries for one plane configs */
1567 if (HAS_FW_BLC(dev) && enabled) {
1568 /* self-refresh has much higher latency */
1569 static const int sr_latency_ns = 6000;
1570 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1571 int clock = adjusted_mode->crtc_clock;
1572 int htotal = adjusted_mode->crtc_htotal;
1573 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1574 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1575 unsigned long line_time_us;
1576 int entries;
1577
1578 line_time_us = max(htotal * 1000 / clock, 1);
1579
1580 /* Use ns/us then divide to preserve precision */
1581 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1582 cpp * hdisplay;
1583 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1584 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1585 srwm = wm_info->fifo_size - entries;
1586 if (srwm < 0)
1587 srwm = 1;
1588
1589 if (IS_I945G(dev) || IS_I945GM(dev))
1590 I915_WRITE(FW_BLC_SELF,
1591 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1592 else if (IS_I915GM(dev))
1593 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1594 }
1595
1596 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1597 planea_wm, planeb_wm, cwm, srwm);
1598
1599 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1600 fwater_hi = (cwm & 0x1f);
1601
1602 /* Set request length to 8 cachelines per fetch */
1603 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1604 fwater_hi = fwater_hi | (1 << 8);
1605
1606 I915_WRITE(FW_BLC, fwater_lo);
1607 I915_WRITE(FW_BLC2, fwater_hi);
1608
1609 if (enabled)
1610 intel_set_memory_cxsr(dev_priv, true);
1611 }
1612
1613 static void i845_update_wm(struct drm_crtc *unused_crtc)
1614 {
1615 struct drm_device *dev = unused_crtc->dev;
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 struct drm_crtc *crtc;
1618 const struct drm_display_mode *adjusted_mode;
1619 uint32_t fwater_lo;
1620 int planea_wm;
1621
1622 crtc = single_enabled_crtc(dev);
1623 if (crtc == NULL)
1624 return;
1625
1626 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1627 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1628 &i845_wm_info,
1629 dev_priv->display.get_fifo_size(dev, 0),
1630 4, pessimal_latency_ns);
1631 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1632 fwater_lo |= (3<<8) | planea_wm;
1633
1634 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1635
1636 I915_WRITE(FW_BLC, fwater_lo);
1637 }
1638
1639 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1640 {
1641 uint32_t pixel_rate;
1642
1643 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1644
1645 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1646 * adjust the pixel_rate here. */
1647
1648 if (pipe_config->pch_pfit.enabled) {
1649 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1650 uint32_t pfit_size = pipe_config->pch_pfit.size;
1651
1652 pipe_w = pipe_config->pipe_src_w;
1653 pipe_h = pipe_config->pipe_src_h;
1654
1655 pfit_w = (pfit_size >> 16) & 0xFFFF;
1656 pfit_h = pfit_size & 0xFFFF;
1657 if (pipe_w < pfit_w)
1658 pipe_w = pfit_w;
1659 if (pipe_h < pfit_h)
1660 pipe_h = pfit_h;
1661
1662 if (WARN_ON(!pfit_w || !pfit_h))
1663 return pixel_rate;
1664
1665 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1666 pfit_w * pfit_h);
1667 }
1668
1669 return pixel_rate;
1670 }
1671
1672 /* latency must be in 0.1us units. */
1673 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1674 {
1675 uint64_t ret;
1676
1677 if (WARN(latency == 0, "Latency value missing\n"))
1678 return UINT_MAX;
1679
1680 ret = (uint64_t) pixel_rate * cpp * latency;
1681 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1682
1683 return ret;
1684 }
1685
1686 /* latency must be in 0.1us units. */
1687 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1688 uint32_t horiz_pixels, uint8_t cpp,
1689 uint32_t latency)
1690 {
1691 uint32_t ret;
1692
1693 if (WARN(latency == 0, "Latency value missing\n"))
1694 return UINT_MAX;
1695 if (WARN_ON(!pipe_htotal))
1696 return UINT_MAX;
1697
1698 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1699 ret = (ret + 1) * horiz_pixels * cpp;
1700 ret = DIV_ROUND_UP(ret, 64) + 2;
1701 return ret;
1702 }
1703
1704 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1705 uint8_t cpp)
1706 {
1707 /*
1708 * Neither of these should be possible since this function shouldn't be
1709 * called if the CRTC is off or the plane is invisible. But let's be
1710 * extra paranoid to avoid a potential divide-by-zero if we screw up
1711 * elsewhere in the driver.
1712 */
1713 if (WARN_ON(!cpp))
1714 return 0;
1715 if (WARN_ON(!horiz_pixels))
1716 return 0;
1717
1718 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1719 }
1720
1721 struct ilk_wm_maximums {
1722 uint16_t pri;
1723 uint16_t spr;
1724 uint16_t cur;
1725 uint16_t fbc;
1726 };
1727
1728 /*
1729 * For both WM_PIPE and WM_LP.
1730 * mem_value must be in 0.1us units.
1731 */
1732 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1733 const struct intel_plane_state *pstate,
1734 uint32_t mem_value,
1735 bool is_lp)
1736 {
1737 int cpp = pstate->base.fb ?
1738 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1739 uint32_t method1, method2;
1740
1741 if (!cstate->base.active || !pstate->visible)
1742 return 0;
1743
1744 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1745
1746 if (!is_lp)
1747 return method1;
1748
1749 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1750 cstate->base.adjusted_mode.crtc_htotal,
1751 drm_rect_width(&pstate->dst),
1752 cpp, mem_value);
1753
1754 return min(method1, method2);
1755 }
1756
1757 /*
1758 * For both WM_PIPE and WM_LP.
1759 * mem_value must be in 0.1us units.
1760 */
1761 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1762 const struct intel_plane_state *pstate,
1763 uint32_t mem_value)
1764 {
1765 int cpp = pstate->base.fb ?
1766 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1767 uint32_t method1, method2;
1768
1769 if (!cstate->base.active || !pstate->visible)
1770 return 0;
1771
1772 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1773 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1774 cstate->base.adjusted_mode.crtc_htotal,
1775 drm_rect_width(&pstate->dst),
1776 cpp, mem_value);
1777 return min(method1, method2);
1778 }
1779
1780 /*
1781 * For both WM_PIPE and WM_LP.
1782 * mem_value must be in 0.1us units.
1783 */
1784 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1785 const struct intel_plane_state *pstate,
1786 uint32_t mem_value)
1787 {
1788 /*
1789 * We treat the cursor plane as always-on for the purposes of watermark
1790 * calculation. Until we have two-stage watermark programming merged,
1791 * this is necessary to avoid flickering.
1792 */
1793 int cpp = 4;
1794 int width = pstate->visible ? pstate->base.crtc_w : 64;
1795
1796 if (!cstate->base.active)
1797 return 0;
1798
1799 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1800 cstate->base.adjusted_mode.crtc_htotal,
1801 width, cpp, mem_value);
1802 }
1803
1804 /* Only for WM_LP. */
1805 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1806 const struct intel_plane_state *pstate,
1807 uint32_t pri_val)
1808 {
1809 int cpp = pstate->base.fb ?
1810 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1811
1812 if (!cstate->base.active || !pstate->visible)
1813 return 0;
1814
1815 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
1816 }
1817
1818 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1819 {
1820 if (INTEL_INFO(dev)->gen >= 8)
1821 return 3072;
1822 else if (INTEL_INFO(dev)->gen >= 7)
1823 return 768;
1824 else
1825 return 512;
1826 }
1827
1828 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1829 int level, bool is_sprite)
1830 {
1831 if (INTEL_INFO(dev)->gen >= 8)
1832 /* BDW primary/sprite plane watermarks */
1833 return level == 0 ? 255 : 2047;
1834 else if (INTEL_INFO(dev)->gen >= 7)
1835 /* IVB/HSW primary/sprite plane watermarks */
1836 return level == 0 ? 127 : 1023;
1837 else if (!is_sprite)
1838 /* ILK/SNB primary plane watermarks */
1839 return level == 0 ? 127 : 511;
1840 else
1841 /* ILK/SNB sprite plane watermarks */
1842 return level == 0 ? 63 : 255;
1843 }
1844
1845 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1846 int level)
1847 {
1848 if (INTEL_INFO(dev)->gen >= 7)
1849 return level == 0 ? 63 : 255;
1850 else
1851 return level == 0 ? 31 : 63;
1852 }
1853
1854 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1855 {
1856 if (INTEL_INFO(dev)->gen >= 8)
1857 return 31;
1858 else
1859 return 15;
1860 }
1861
1862 /* Calculate the maximum primary/sprite plane watermark */
1863 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1864 int level,
1865 const struct intel_wm_config *config,
1866 enum intel_ddb_partitioning ddb_partitioning,
1867 bool is_sprite)
1868 {
1869 unsigned int fifo_size = ilk_display_fifo_size(dev);
1870
1871 /* if sprites aren't enabled, sprites get nothing */
1872 if (is_sprite && !config->sprites_enabled)
1873 return 0;
1874
1875 /* HSW allows LP1+ watermarks even with multiple pipes */
1876 if (level == 0 || config->num_pipes_active > 1) {
1877 fifo_size /= INTEL_INFO(dev)->num_pipes;
1878
1879 /*
1880 * For some reason the non self refresh
1881 * FIFO size is only half of the self
1882 * refresh FIFO size on ILK/SNB.
1883 */
1884 if (INTEL_INFO(dev)->gen <= 6)
1885 fifo_size /= 2;
1886 }
1887
1888 if (config->sprites_enabled) {
1889 /* level 0 is always calculated with 1:1 split */
1890 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1891 if (is_sprite)
1892 fifo_size *= 5;
1893 fifo_size /= 6;
1894 } else {
1895 fifo_size /= 2;
1896 }
1897 }
1898
1899 /* clamp to max that the registers can hold */
1900 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1901 }
1902
1903 /* Calculate the maximum cursor plane watermark */
1904 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1905 int level,
1906 const struct intel_wm_config *config)
1907 {
1908 /* HSW LP1+ watermarks w/ multiple pipes */
1909 if (level > 0 && config->num_pipes_active > 1)
1910 return 64;
1911
1912 /* otherwise just report max that registers can hold */
1913 return ilk_cursor_wm_reg_max(dev, level);
1914 }
1915
1916 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1917 int level,
1918 const struct intel_wm_config *config,
1919 enum intel_ddb_partitioning ddb_partitioning,
1920 struct ilk_wm_maximums *max)
1921 {
1922 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1923 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1924 max->cur = ilk_cursor_wm_max(dev, level, config);
1925 max->fbc = ilk_fbc_wm_reg_max(dev);
1926 }
1927
1928 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1929 int level,
1930 struct ilk_wm_maximums *max)
1931 {
1932 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1933 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1934 max->cur = ilk_cursor_wm_reg_max(dev, level);
1935 max->fbc = ilk_fbc_wm_reg_max(dev);
1936 }
1937
1938 static bool ilk_validate_wm_level(int level,
1939 const struct ilk_wm_maximums *max,
1940 struct intel_wm_level *result)
1941 {
1942 bool ret;
1943
1944 /* already determined to be invalid? */
1945 if (!result->enable)
1946 return false;
1947
1948 result->enable = result->pri_val <= max->pri &&
1949 result->spr_val <= max->spr &&
1950 result->cur_val <= max->cur;
1951
1952 ret = result->enable;
1953
1954 /*
1955 * HACK until we can pre-compute everything,
1956 * and thus fail gracefully if LP0 watermarks
1957 * are exceeded...
1958 */
1959 if (level == 0 && !result->enable) {
1960 if (result->pri_val > max->pri)
1961 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1962 level, result->pri_val, max->pri);
1963 if (result->spr_val > max->spr)
1964 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1965 level, result->spr_val, max->spr);
1966 if (result->cur_val > max->cur)
1967 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1968 level, result->cur_val, max->cur);
1969
1970 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1971 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1972 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1973 result->enable = true;
1974 }
1975
1976 return ret;
1977 }
1978
1979 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1980 const struct intel_crtc *intel_crtc,
1981 int level,
1982 struct intel_crtc_state *cstate,
1983 struct intel_plane_state *pristate,
1984 struct intel_plane_state *sprstate,
1985 struct intel_plane_state *curstate,
1986 struct intel_wm_level *result)
1987 {
1988 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1989 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1990 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1991
1992 /* WM1+ latency values stored in 0.5us units */
1993 if (level > 0) {
1994 pri_latency *= 5;
1995 spr_latency *= 5;
1996 cur_latency *= 5;
1997 }
1998
1999 if (pristate) {
2000 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2001 pri_latency, level);
2002 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2003 }
2004
2005 if (sprstate)
2006 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2007
2008 if (curstate)
2009 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2010
2011 result->enable = true;
2012 }
2013
2014 static uint32_t
2015 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2016 {
2017 const struct intel_atomic_state *intel_state =
2018 to_intel_atomic_state(cstate->base.state);
2019 const struct drm_display_mode *adjusted_mode =
2020 &cstate->base.adjusted_mode;
2021 u32 linetime, ips_linetime;
2022
2023 if (!cstate->base.active)
2024 return 0;
2025 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2026 return 0;
2027 if (WARN_ON(intel_state->cdclk == 0))
2028 return 0;
2029
2030 /* The WM are computed with base on how long it takes to fill a single
2031 * row at the given clock rate, multiplied by 8.
2032 * */
2033 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2034 adjusted_mode->crtc_clock);
2035 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2036 intel_state->cdclk);
2037
2038 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2039 PIPE_WM_LINETIME_TIME(linetime);
2040 }
2041
2042 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2043 {
2044 struct drm_i915_private *dev_priv = dev->dev_private;
2045
2046 if (IS_GEN9(dev)) {
2047 uint32_t val;
2048 int ret, i;
2049 int level, max_level = ilk_wm_max_level(dev);
2050
2051 /* read the first set of memory latencies[0:3] */
2052 val = 0; /* data0 to be programmed to 0 for first set */
2053 mutex_lock(&dev_priv->rps.hw_lock);
2054 ret = sandybridge_pcode_read(dev_priv,
2055 GEN9_PCODE_READ_MEM_LATENCY,
2056 &val);
2057 mutex_unlock(&dev_priv->rps.hw_lock);
2058
2059 if (ret) {
2060 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2061 return;
2062 }
2063
2064 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2065 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2066 GEN9_MEM_LATENCY_LEVEL_MASK;
2067 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2068 GEN9_MEM_LATENCY_LEVEL_MASK;
2069 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2070 GEN9_MEM_LATENCY_LEVEL_MASK;
2071
2072 /* read the second set of memory latencies[4:7] */
2073 val = 1; /* data0 to be programmed to 1 for second set */
2074 mutex_lock(&dev_priv->rps.hw_lock);
2075 ret = sandybridge_pcode_read(dev_priv,
2076 GEN9_PCODE_READ_MEM_LATENCY,
2077 &val);
2078 mutex_unlock(&dev_priv->rps.hw_lock);
2079 if (ret) {
2080 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2081 return;
2082 }
2083
2084 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2085 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2086 GEN9_MEM_LATENCY_LEVEL_MASK;
2087 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2088 GEN9_MEM_LATENCY_LEVEL_MASK;
2089 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2090 GEN9_MEM_LATENCY_LEVEL_MASK;
2091
2092 /*
2093 * WaWmMemoryReadLatency:skl
2094 *
2095 * punit doesn't take into account the read latency so we need
2096 * to add 2us to the various latency levels we retrieve from
2097 * the punit.
2098 * - W0 is a bit special in that it's the only level that
2099 * can't be disabled if we want to have display working, so
2100 * we always add 2us there.
2101 * - For levels >=1, punit returns 0us latency when they are
2102 * disabled, so we respect that and don't add 2us then
2103 *
2104 * Additionally, if a level n (n > 1) has a 0us latency, all
2105 * levels m (m >= n) need to be disabled. We make sure to
2106 * sanitize the values out of the punit to satisfy this
2107 * requirement.
2108 */
2109 wm[0] += 2;
2110 for (level = 1; level <= max_level; level++)
2111 if (wm[level] != 0)
2112 wm[level] += 2;
2113 else {
2114 for (i = level + 1; i <= max_level; i++)
2115 wm[i] = 0;
2116
2117 break;
2118 }
2119 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2120 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2121
2122 wm[0] = (sskpd >> 56) & 0xFF;
2123 if (wm[0] == 0)
2124 wm[0] = sskpd & 0xF;
2125 wm[1] = (sskpd >> 4) & 0xFF;
2126 wm[2] = (sskpd >> 12) & 0xFF;
2127 wm[3] = (sskpd >> 20) & 0x1FF;
2128 wm[4] = (sskpd >> 32) & 0x1FF;
2129 } else if (INTEL_INFO(dev)->gen >= 6) {
2130 uint32_t sskpd = I915_READ(MCH_SSKPD);
2131
2132 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2133 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2134 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2135 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2136 } else if (INTEL_INFO(dev)->gen >= 5) {
2137 uint32_t mltr = I915_READ(MLTR_ILK);
2138
2139 /* ILK primary LP0 latency is 700 ns */
2140 wm[0] = 7;
2141 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2142 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2143 }
2144 }
2145
2146 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2147 {
2148 /* ILK sprite LP0 latency is 1300 ns */
2149 if (IS_GEN5(dev))
2150 wm[0] = 13;
2151 }
2152
2153 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2154 {
2155 /* ILK cursor LP0 latency is 1300 ns */
2156 if (IS_GEN5(dev))
2157 wm[0] = 13;
2158
2159 /* WaDoubleCursorLP3Latency:ivb */
2160 if (IS_IVYBRIDGE(dev))
2161 wm[3] *= 2;
2162 }
2163
2164 int ilk_wm_max_level(const struct drm_device *dev)
2165 {
2166 /* how many WM levels are we expecting */
2167 if (INTEL_INFO(dev)->gen >= 9)
2168 return 7;
2169 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2170 return 4;
2171 else if (INTEL_INFO(dev)->gen >= 6)
2172 return 3;
2173 else
2174 return 2;
2175 }
2176
2177 static void intel_print_wm_latency(struct drm_device *dev,
2178 const char *name,
2179 const uint16_t wm[8])
2180 {
2181 int level, max_level = ilk_wm_max_level(dev);
2182
2183 for (level = 0; level <= max_level; level++) {
2184 unsigned int latency = wm[level];
2185
2186 if (latency == 0) {
2187 DRM_ERROR("%s WM%d latency not provided\n",
2188 name, level);
2189 continue;
2190 }
2191
2192 /*
2193 * - latencies are in us on gen9.
2194 * - before then, WM1+ latency values are in 0.5us units
2195 */
2196 if (IS_GEN9(dev))
2197 latency *= 10;
2198 else if (level > 0)
2199 latency *= 5;
2200
2201 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2202 name, level, wm[level],
2203 latency / 10, latency % 10);
2204 }
2205 }
2206
2207 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2208 uint16_t wm[5], uint16_t min)
2209 {
2210 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2211
2212 if (wm[0] >= min)
2213 return false;
2214
2215 wm[0] = max(wm[0], min);
2216 for (level = 1; level <= max_level; level++)
2217 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2218
2219 return true;
2220 }
2221
2222 static void snb_wm_latency_quirk(struct drm_device *dev)
2223 {
2224 struct drm_i915_private *dev_priv = dev->dev_private;
2225 bool changed;
2226
2227 /*
2228 * The BIOS provided WM memory latency values are often
2229 * inadequate for high resolution displays. Adjust them.
2230 */
2231 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2232 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2233 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2234
2235 if (!changed)
2236 return;
2237
2238 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2239 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2240 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2241 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2242 }
2243
2244 static void ilk_setup_wm_latency(struct drm_device *dev)
2245 {
2246 struct drm_i915_private *dev_priv = dev->dev_private;
2247
2248 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2249
2250 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2251 sizeof(dev_priv->wm.pri_latency));
2252 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2253 sizeof(dev_priv->wm.pri_latency));
2254
2255 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2256 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2257
2258 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2259 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2260 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2261
2262 if (IS_GEN6(dev))
2263 snb_wm_latency_quirk(dev);
2264 }
2265
2266 static void skl_setup_wm_latency(struct drm_device *dev)
2267 {
2268 struct drm_i915_private *dev_priv = dev->dev_private;
2269
2270 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2271 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2272 }
2273
2274 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2275 struct intel_pipe_wm *pipe_wm)
2276 {
2277 /* LP0 watermark maximums depend on this pipe alone */
2278 const struct intel_wm_config config = {
2279 .num_pipes_active = 1,
2280 .sprites_enabled = pipe_wm->sprites_enabled,
2281 .sprites_scaled = pipe_wm->sprites_scaled,
2282 };
2283 struct ilk_wm_maximums max;
2284
2285 /* LP0 watermarks always use 1/2 DDB partitioning */
2286 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2287
2288 /* At least LP0 must be valid */
2289 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2290 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2291 return false;
2292 }
2293
2294 return true;
2295 }
2296
2297 /* Compute new watermarks for the pipe */
2298 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2299 {
2300 struct drm_atomic_state *state = cstate->base.state;
2301 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2302 struct intel_pipe_wm *pipe_wm;
2303 struct drm_device *dev = state->dev;
2304 const struct drm_i915_private *dev_priv = dev->dev_private;
2305 struct intel_plane *intel_plane;
2306 struct intel_plane_state *pristate = NULL;
2307 struct intel_plane_state *sprstate = NULL;
2308 struct intel_plane_state *curstate = NULL;
2309 int level, max_level = ilk_wm_max_level(dev), usable_level;
2310 struct ilk_wm_maximums max;
2311
2312 pipe_wm = &cstate->wm.ilk.optimal;
2313
2314 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2315 struct intel_plane_state *ps;
2316
2317 ps = intel_atomic_get_existing_plane_state(state,
2318 intel_plane);
2319 if (!ps)
2320 continue;
2321
2322 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2323 pristate = ps;
2324 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2325 sprstate = ps;
2326 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2327 curstate = ps;
2328 }
2329
2330 pipe_wm->pipe_enabled = cstate->base.active;
2331 if (sprstate) {
2332 pipe_wm->sprites_enabled = sprstate->visible;
2333 pipe_wm->sprites_scaled = sprstate->visible &&
2334 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2335 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2336 }
2337
2338 usable_level = max_level;
2339
2340 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2341 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2342 usable_level = 1;
2343
2344 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2345 if (pipe_wm->sprites_scaled)
2346 usable_level = 0;
2347
2348 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2349 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2350
2351 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2352 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2353
2354 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2355 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2356
2357 if (!ilk_validate_pipe_wm(dev, pipe_wm))
2358 return -EINVAL;
2359
2360 ilk_compute_wm_reg_maximums(dev, 1, &max);
2361
2362 for (level = 1; level <= max_level; level++) {
2363 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2364
2365 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2366 pristate, sprstate, curstate, wm);
2367
2368 /*
2369 * Disable any watermark level that exceeds the
2370 * register maximums since such watermarks are
2371 * always invalid.
2372 */
2373 if (level > usable_level)
2374 continue;
2375
2376 if (ilk_validate_wm_level(level, &max, wm))
2377 pipe_wm->wm[level] = *wm;
2378 else
2379 usable_level = level;
2380 }
2381
2382 return 0;
2383 }
2384
2385 /*
2386 * Build a set of 'intermediate' watermark values that satisfy both the old
2387 * state and the new state. These can be programmed to the hardware
2388 * immediately.
2389 */
2390 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2391 struct intel_crtc *intel_crtc,
2392 struct intel_crtc_state *newstate)
2393 {
2394 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2395 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2396 int level, max_level = ilk_wm_max_level(dev);
2397
2398 /*
2399 * Start with the final, target watermarks, then combine with the
2400 * currently active watermarks to get values that are safe both before
2401 * and after the vblank.
2402 */
2403 *a = newstate->wm.ilk.optimal;
2404 a->pipe_enabled |= b->pipe_enabled;
2405 a->sprites_enabled |= b->sprites_enabled;
2406 a->sprites_scaled |= b->sprites_scaled;
2407
2408 for (level = 0; level <= max_level; level++) {
2409 struct intel_wm_level *a_wm = &a->wm[level];
2410 const struct intel_wm_level *b_wm = &b->wm[level];
2411
2412 a_wm->enable &= b_wm->enable;
2413 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2414 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2415 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2416 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2417 }
2418
2419 /*
2420 * We need to make sure that these merged watermark values are
2421 * actually a valid configuration themselves. If they're not,
2422 * there's no safe way to transition from the old state to
2423 * the new state, so we need to fail the atomic transaction.
2424 */
2425 if (!ilk_validate_pipe_wm(dev, a))
2426 return -EINVAL;
2427
2428 /*
2429 * If our intermediate WM are identical to the final WM, then we can
2430 * omit the post-vblank programming; only update if it's different.
2431 */
2432 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2433 newstate->wm.need_postvbl_update = false;
2434
2435 return 0;
2436 }
2437
2438 /*
2439 * Merge the watermarks from all active pipes for a specific level.
2440 */
2441 static void ilk_merge_wm_level(struct drm_device *dev,
2442 int level,
2443 struct intel_wm_level *ret_wm)
2444 {
2445 const struct intel_crtc *intel_crtc;
2446
2447 ret_wm->enable = true;
2448
2449 for_each_intel_crtc(dev, intel_crtc) {
2450 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2451 const struct intel_wm_level *wm = &active->wm[level];
2452
2453 if (!active->pipe_enabled)
2454 continue;
2455
2456 /*
2457 * The watermark values may have been used in the past,
2458 * so we must maintain them in the registers for some
2459 * time even if the level is now disabled.
2460 */
2461 if (!wm->enable)
2462 ret_wm->enable = false;
2463
2464 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2465 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2466 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2467 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2468 }
2469 }
2470
2471 /*
2472 * Merge all low power watermarks for all active pipes.
2473 */
2474 static void ilk_wm_merge(struct drm_device *dev,
2475 const struct intel_wm_config *config,
2476 const struct ilk_wm_maximums *max,
2477 struct intel_pipe_wm *merged)
2478 {
2479 struct drm_i915_private *dev_priv = dev->dev_private;
2480 int level, max_level = ilk_wm_max_level(dev);
2481 int last_enabled_level = max_level;
2482
2483 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2484 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2485 config->num_pipes_active > 1)
2486 last_enabled_level = 0;
2487
2488 /* ILK: FBC WM must be disabled always */
2489 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2490
2491 /* merge each WM1+ level */
2492 for (level = 1; level <= max_level; level++) {
2493 struct intel_wm_level *wm = &merged->wm[level];
2494
2495 ilk_merge_wm_level(dev, level, wm);
2496
2497 if (level > last_enabled_level)
2498 wm->enable = false;
2499 else if (!ilk_validate_wm_level(level, max, wm))
2500 /* make sure all following levels get disabled */
2501 last_enabled_level = level - 1;
2502
2503 /*
2504 * The spec says it is preferred to disable
2505 * FBC WMs instead of disabling a WM level.
2506 */
2507 if (wm->fbc_val > max->fbc) {
2508 if (wm->enable)
2509 merged->fbc_wm_enabled = false;
2510 wm->fbc_val = 0;
2511 }
2512 }
2513
2514 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2515 /*
2516 * FIXME this is racy. FBC might get enabled later.
2517 * What we should check here is whether FBC can be
2518 * enabled sometime later.
2519 */
2520 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2521 intel_fbc_is_active(dev_priv)) {
2522 for (level = 2; level <= max_level; level++) {
2523 struct intel_wm_level *wm = &merged->wm[level];
2524
2525 wm->enable = false;
2526 }
2527 }
2528 }
2529
2530 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2531 {
2532 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2533 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2534 }
2535
2536 /* The value we need to program into the WM_LPx latency field */
2537 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2538 {
2539 struct drm_i915_private *dev_priv = dev->dev_private;
2540
2541 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2542 return 2 * level;
2543 else
2544 return dev_priv->wm.pri_latency[level];
2545 }
2546
2547 static void ilk_compute_wm_results(struct drm_device *dev,
2548 const struct intel_pipe_wm *merged,
2549 enum intel_ddb_partitioning partitioning,
2550 struct ilk_wm_values *results)
2551 {
2552 struct intel_crtc *intel_crtc;
2553 int level, wm_lp;
2554
2555 results->enable_fbc_wm = merged->fbc_wm_enabled;
2556 results->partitioning = partitioning;
2557
2558 /* LP1+ register values */
2559 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2560 const struct intel_wm_level *r;
2561
2562 level = ilk_wm_lp_to_level(wm_lp, merged);
2563
2564 r = &merged->wm[level];
2565
2566 /*
2567 * Maintain the watermark values even if the level is
2568 * disabled. Doing otherwise could cause underruns.
2569 */
2570 results->wm_lp[wm_lp - 1] =
2571 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2572 (r->pri_val << WM1_LP_SR_SHIFT) |
2573 r->cur_val;
2574
2575 if (r->enable)
2576 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2577
2578 if (INTEL_INFO(dev)->gen >= 8)
2579 results->wm_lp[wm_lp - 1] |=
2580 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2581 else
2582 results->wm_lp[wm_lp - 1] |=
2583 r->fbc_val << WM1_LP_FBC_SHIFT;
2584
2585 /*
2586 * Always set WM1S_LP_EN when spr_val != 0, even if the
2587 * level is disabled. Doing otherwise could cause underruns.
2588 */
2589 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2590 WARN_ON(wm_lp != 1);
2591 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2592 } else
2593 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2594 }
2595
2596 /* LP0 register values */
2597 for_each_intel_crtc(dev, intel_crtc) {
2598 enum pipe pipe = intel_crtc->pipe;
2599 const struct intel_wm_level *r =
2600 &intel_crtc->wm.active.ilk.wm[0];
2601
2602 if (WARN_ON(!r->enable))
2603 continue;
2604
2605 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2606
2607 results->wm_pipe[pipe] =
2608 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2609 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2610 r->cur_val;
2611 }
2612 }
2613
2614 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2615 * case both are at the same level. Prefer r1 in case they're the same. */
2616 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2617 struct intel_pipe_wm *r1,
2618 struct intel_pipe_wm *r2)
2619 {
2620 int level, max_level = ilk_wm_max_level(dev);
2621 int level1 = 0, level2 = 0;
2622
2623 for (level = 1; level <= max_level; level++) {
2624 if (r1->wm[level].enable)
2625 level1 = level;
2626 if (r2->wm[level].enable)
2627 level2 = level;
2628 }
2629
2630 if (level1 == level2) {
2631 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2632 return r2;
2633 else
2634 return r1;
2635 } else if (level1 > level2) {
2636 return r1;
2637 } else {
2638 return r2;
2639 }
2640 }
2641
2642 /* dirty bits used to track which watermarks need changes */
2643 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2644 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2645 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2646 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2647 #define WM_DIRTY_FBC (1 << 24)
2648 #define WM_DIRTY_DDB (1 << 25)
2649
2650 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2651 const struct ilk_wm_values *old,
2652 const struct ilk_wm_values *new)
2653 {
2654 unsigned int dirty = 0;
2655 enum pipe pipe;
2656 int wm_lp;
2657
2658 for_each_pipe(dev_priv, pipe) {
2659 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2660 dirty |= WM_DIRTY_LINETIME(pipe);
2661 /* Must disable LP1+ watermarks too */
2662 dirty |= WM_DIRTY_LP_ALL;
2663 }
2664
2665 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2666 dirty |= WM_DIRTY_PIPE(pipe);
2667 /* Must disable LP1+ watermarks too */
2668 dirty |= WM_DIRTY_LP_ALL;
2669 }
2670 }
2671
2672 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2673 dirty |= WM_DIRTY_FBC;
2674 /* Must disable LP1+ watermarks too */
2675 dirty |= WM_DIRTY_LP_ALL;
2676 }
2677
2678 if (old->partitioning != new->partitioning) {
2679 dirty |= WM_DIRTY_DDB;
2680 /* Must disable LP1+ watermarks too */
2681 dirty |= WM_DIRTY_LP_ALL;
2682 }
2683
2684 /* LP1+ watermarks already deemed dirty, no need to continue */
2685 if (dirty & WM_DIRTY_LP_ALL)
2686 return dirty;
2687
2688 /* Find the lowest numbered LP1+ watermark in need of an update... */
2689 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2690 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2691 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2692 break;
2693 }
2694
2695 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2696 for (; wm_lp <= 3; wm_lp++)
2697 dirty |= WM_DIRTY_LP(wm_lp);
2698
2699 return dirty;
2700 }
2701
2702 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2703 unsigned int dirty)
2704 {
2705 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2706 bool changed = false;
2707
2708 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2709 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2710 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2711 changed = true;
2712 }
2713 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2714 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2715 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2716 changed = true;
2717 }
2718 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2719 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2720 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2721 changed = true;
2722 }
2723
2724 /*
2725 * Don't touch WM1S_LP_EN here.
2726 * Doing so could cause underruns.
2727 */
2728
2729 return changed;
2730 }
2731
2732 /*
2733 * The spec says we shouldn't write when we don't need, because every write
2734 * causes WMs to be re-evaluated, expending some power.
2735 */
2736 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2737 struct ilk_wm_values *results)
2738 {
2739 struct drm_device *dev = dev_priv->dev;
2740 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2741 unsigned int dirty;
2742 uint32_t val;
2743
2744 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2745 if (!dirty)
2746 return;
2747
2748 _ilk_disable_lp_wm(dev_priv, dirty);
2749
2750 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2751 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2752 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2753 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2754 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2755 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2756
2757 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2758 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2759 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2760 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2761 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2762 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2763
2764 if (dirty & WM_DIRTY_DDB) {
2765 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2766 val = I915_READ(WM_MISC);
2767 if (results->partitioning == INTEL_DDB_PART_1_2)
2768 val &= ~WM_MISC_DATA_PARTITION_5_6;
2769 else
2770 val |= WM_MISC_DATA_PARTITION_5_6;
2771 I915_WRITE(WM_MISC, val);
2772 } else {
2773 val = I915_READ(DISP_ARB_CTL2);
2774 if (results->partitioning == INTEL_DDB_PART_1_2)
2775 val &= ~DISP_DATA_PARTITION_5_6;
2776 else
2777 val |= DISP_DATA_PARTITION_5_6;
2778 I915_WRITE(DISP_ARB_CTL2, val);
2779 }
2780 }
2781
2782 if (dirty & WM_DIRTY_FBC) {
2783 val = I915_READ(DISP_ARB_CTL);
2784 if (results->enable_fbc_wm)
2785 val &= ~DISP_FBC_WM_DIS;
2786 else
2787 val |= DISP_FBC_WM_DIS;
2788 I915_WRITE(DISP_ARB_CTL, val);
2789 }
2790
2791 if (dirty & WM_DIRTY_LP(1) &&
2792 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2793 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2794
2795 if (INTEL_INFO(dev)->gen >= 7) {
2796 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2797 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2798 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2799 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2800 }
2801
2802 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2803 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2804 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2805 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2806 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2807 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2808
2809 dev_priv->wm.hw = *results;
2810 }
2811
2812 bool ilk_disable_lp_wm(struct drm_device *dev)
2813 {
2814 struct drm_i915_private *dev_priv = dev->dev_private;
2815
2816 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2817 }
2818
2819 /*
2820 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2821 * different active planes.
2822 */
2823
2824 #define SKL_DDB_SIZE 896 /* in blocks */
2825 #define BXT_DDB_SIZE 512
2826
2827 /*
2828 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2829 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2830 * other universal planes are in indices 1..n. Note that this may leave unused
2831 * indices between the top "sprite" plane and the cursor.
2832 */
2833 static int
2834 skl_wm_plane_id(const struct intel_plane *plane)
2835 {
2836 switch (plane->base.type) {
2837 case DRM_PLANE_TYPE_PRIMARY:
2838 return 0;
2839 case DRM_PLANE_TYPE_CURSOR:
2840 return PLANE_CURSOR;
2841 case DRM_PLANE_TYPE_OVERLAY:
2842 return plane->plane + 1;
2843 default:
2844 MISSING_CASE(plane->base.type);
2845 return plane->plane;
2846 }
2847 }
2848
2849 static void
2850 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2851 const struct intel_crtc_state *cstate,
2852 struct skl_ddb_entry *alloc, /* out */
2853 int *num_active /* out */)
2854 {
2855 struct drm_atomic_state *state = cstate->base.state;
2856 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2857 struct drm_i915_private *dev_priv = to_i915(dev);
2858 struct drm_crtc *for_crtc = cstate->base.crtc;
2859 unsigned int pipe_size, ddb_size;
2860 int nth_active_pipe;
2861 int pipe = to_intel_crtc(for_crtc)->pipe;
2862
2863 if (WARN_ON(!state) || !cstate->base.active) {
2864 alloc->start = 0;
2865 alloc->end = 0;
2866 *num_active = hweight32(dev_priv->active_crtcs);
2867 return;
2868 }
2869
2870 if (intel_state->active_pipe_changes)
2871 *num_active = hweight32(intel_state->active_crtcs);
2872 else
2873 *num_active = hweight32(dev_priv->active_crtcs);
2874
2875 if (IS_BROXTON(dev))
2876 ddb_size = BXT_DDB_SIZE;
2877 else
2878 ddb_size = SKL_DDB_SIZE;
2879
2880 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2881
2882 /*
2883 * If the state doesn't change the active CRTC's, then there's
2884 * no need to recalculate; the existing pipe allocation limits
2885 * should remain unchanged. Note that we're safe from racing
2886 * commits since any racing commit that changes the active CRTC
2887 * list would need to grab _all_ crtc locks, including the one
2888 * we currently hold.
2889 */
2890 if (!intel_state->active_pipe_changes) {
2891 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
2892 return;
2893 }
2894
2895 nth_active_pipe = hweight32(intel_state->active_crtcs &
2896 (drm_crtc_mask(for_crtc) - 1));
2897 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
2898 alloc->start = nth_active_pipe * ddb_size / *num_active;
2899 alloc->end = alloc->start + pipe_size;
2900 }
2901
2902 static unsigned int skl_cursor_allocation(int num_active)
2903 {
2904 if (num_active == 1)
2905 return 32;
2906
2907 return 8;
2908 }
2909
2910 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2911 {
2912 entry->start = reg & 0x3ff;
2913 entry->end = (reg >> 16) & 0x3ff;
2914 if (entry->end)
2915 entry->end += 1;
2916 }
2917
2918 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2919 struct skl_ddb_allocation *ddb /* out */)
2920 {
2921 enum pipe pipe;
2922 int plane;
2923 u32 val;
2924
2925 memset(ddb, 0, sizeof(*ddb));
2926
2927 for_each_pipe(dev_priv, pipe) {
2928 enum intel_display_power_domain power_domain;
2929
2930 power_domain = POWER_DOMAIN_PIPE(pipe);
2931 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2932 continue;
2933
2934 for_each_plane(dev_priv, pipe, plane) {
2935 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2936 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2937 val);
2938 }
2939
2940 val = I915_READ(CUR_BUF_CFG(pipe));
2941 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2942 val);
2943
2944 intel_display_power_put(dev_priv, power_domain);
2945 }
2946 }
2947
2948 static unsigned int
2949 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2950 const struct drm_plane_state *pstate,
2951 int y)
2952 {
2953 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
2954 struct drm_framebuffer *fb = pstate->fb;
2955 uint32_t width = 0, height = 0;
2956 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
2957
2958 if (!intel_pstate->visible)
2959 return 0;
2960 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
2961 return 0;
2962 if (y && format != DRM_FORMAT_NV12)
2963 return 0;
2964
2965 width = drm_rect_width(&intel_pstate->src) >> 16;
2966 height = drm_rect_height(&intel_pstate->src) >> 16;
2967
2968 if (intel_rotation_90_or_270(pstate->rotation))
2969 swap(width, height);
2970
2971 /* for planar format */
2972 if (format == DRM_FORMAT_NV12) {
2973 if (y) /* y-plane data rate */
2974 return width * height *
2975 drm_format_plane_cpp(format, 0);
2976 else /* uv-plane data rate */
2977 return (width / 2) * (height / 2) *
2978 drm_format_plane_cpp(format, 1);
2979 }
2980
2981 /* for packed formats */
2982 return width * height * drm_format_plane_cpp(format, 0);
2983 }
2984
2985 /*
2986 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2987 * a 8192x4096@32bpp framebuffer:
2988 * 3 * 4096 * 8192 * 4 < 2^32
2989 */
2990 static unsigned int
2991 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
2992 {
2993 struct drm_crtc_state *cstate = &intel_cstate->base;
2994 struct drm_atomic_state *state = cstate->state;
2995 struct drm_crtc *crtc = cstate->crtc;
2996 struct drm_device *dev = crtc->dev;
2997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2998 const struct drm_plane *plane;
2999 const struct intel_plane *intel_plane;
3000 struct drm_plane_state *pstate;
3001 unsigned int rate, total_data_rate = 0;
3002 int id;
3003 int i;
3004
3005 if (WARN_ON(!state))
3006 return 0;
3007
3008 /* Calculate and cache data rate for each plane */
3009 for_each_plane_in_state(state, plane, pstate, i) {
3010 id = skl_wm_plane_id(to_intel_plane(plane));
3011 intel_plane = to_intel_plane(plane);
3012
3013 if (intel_plane->pipe != intel_crtc->pipe)
3014 continue;
3015
3016 /* packed/uv */
3017 rate = skl_plane_relative_data_rate(intel_cstate,
3018 pstate, 0);
3019 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3020
3021 /* y-plane */
3022 rate = skl_plane_relative_data_rate(intel_cstate,
3023 pstate, 1);
3024 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
3025 }
3026
3027 /* Calculate CRTC's total data rate from cached values */
3028 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3029 int id = skl_wm_plane_id(intel_plane);
3030
3031 /* packed/uv */
3032 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3033 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
3034 }
3035
3036 WARN_ON(cstate->plane_mask && total_data_rate == 0);
3037
3038 return total_data_rate;
3039 }
3040
3041 static int
3042 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3043 struct skl_ddb_allocation *ddb /* out */)
3044 {
3045 struct drm_atomic_state *state = cstate->base.state;
3046 struct drm_crtc *crtc = cstate->base.crtc;
3047 struct drm_device *dev = crtc->dev;
3048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3049 struct intel_plane *intel_plane;
3050 struct drm_plane *plane;
3051 struct drm_plane_state *pstate;
3052 enum pipe pipe = intel_crtc->pipe;
3053 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
3054 uint16_t alloc_size, start, cursor_blocks;
3055 uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3056 uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
3057 unsigned int total_data_rate;
3058 int num_active;
3059 int id, i;
3060
3061 if (WARN_ON(!state))
3062 return 0;
3063
3064 if (!cstate->base.active) {
3065 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3066 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3067 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3068 return 0;
3069 }
3070
3071 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3072 alloc_size = skl_ddb_entry_size(alloc);
3073 if (alloc_size == 0) {
3074 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3075 return 0;
3076 }
3077
3078 cursor_blocks = skl_cursor_allocation(num_active);
3079 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3080 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3081
3082 alloc_size -= cursor_blocks;
3083
3084 /* 1. Allocate the mininum required blocks for each active plane */
3085 for_each_plane_in_state(state, plane, pstate, i) {
3086 intel_plane = to_intel_plane(plane);
3087 id = skl_wm_plane_id(intel_plane);
3088
3089 if (intel_plane->pipe != pipe)
3090 continue;
3091
3092 if (!to_intel_plane_state(pstate)->visible) {
3093 minimum[id] = 0;
3094 y_minimum[id] = 0;
3095 continue;
3096 }
3097 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3098 minimum[id] = 0;
3099 y_minimum[id] = 0;
3100 continue;
3101 }
3102
3103 minimum[id] = 8;
3104 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
3105 y_minimum[id] = 8;
3106 else
3107 y_minimum[id] = 0;
3108 }
3109
3110 for (i = 0; i < PLANE_CURSOR; i++) {
3111 alloc_size -= minimum[i];
3112 alloc_size -= y_minimum[i];
3113 }
3114
3115 /*
3116 * 2. Distribute the remaining space in proportion to the amount of
3117 * data each plane needs to fetch from memory.
3118 *
3119 * FIXME: we may not allocate every single block here.
3120 */
3121 total_data_rate = skl_get_total_relative_data_rate(cstate);
3122 if (total_data_rate == 0)
3123 return 0;
3124
3125 start = alloc->start;
3126 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3127 unsigned int data_rate, y_data_rate;
3128 uint16_t plane_blocks, y_plane_blocks = 0;
3129 int id = skl_wm_plane_id(intel_plane);
3130
3131 data_rate = cstate->wm.skl.plane_data_rate[id];
3132
3133 /*
3134 * allocation for (packed formats) or (uv-plane part of planar format):
3135 * promote the expression to 64 bits to avoid overflowing, the
3136 * result is < available as data_rate / total_data_rate < 1
3137 */
3138 plane_blocks = minimum[id];
3139 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3140 total_data_rate);
3141
3142 /* Leave disabled planes at (0,0) */
3143 if (data_rate) {
3144 ddb->plane[pipe][id].start = start;
3145 ddb->plane[pipe][id].end = start + plane_blocks;
3146 }
3147
3148 start += plane_blocks;
3149
3150 /*
3151 * allocation for y_plane part of planar format:
3152 */
3153 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3154
3155 y_plane_blocks = y_minimum[id];
3156 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3157 total_data_rate);
3158
3159 if (y_data_rate) {
3160 ddb->y_plane[pipe][id].start = start;
3161 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3162 }
3163
3164 start += y_plane_blocks;
3165 }
3166
3167 return 0;
3168 }
3169
3170 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3171 {
3172 /* TODO: Take into account the scalers once we support them */
3173 return config->base.adjusted_mode.crtc_clock;
3174 }
3175
3176 /*
3177 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3178 * for the read latency) and cpp should always be <= 8, so that
3179 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3180 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3181 */
3182 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3183 {
3184 uint32_t wm_intermediate_val, ret;
3185
3186 if (latency == 0)
3187 return UINT_MAX;
3188
3189 wm_intermediate_val = latency * pixel_rate * cpp / 512;
3190 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3191
3192 return ret;
3193 }
3194
3195 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3196 uint32_t horiz_pixels, uint8_t cpp,
3197 uint64_t tiling, uint32_t latency)
3198 {
3199 uint32_t ret;
3200 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3201 uint32_t wm_intermediate_val;
3202
3203 if (latency == 0)
3204 return UINT_MAX;
3205
3206 plane_bytes_per_line = horiz_pixels * cpp;
3207
3208 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3209 tiling == I915_FORMAT_MOD_Yf_TILED) {
3210 plane_bytes_per_line *= 4;
3211 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3212 plane_blocks_per_line /= 4;
3213 } else {
3214 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3215 }
3216
3217 wm_intermediate_val = latency * pixel_rate;
3218 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3219 plane_blocks_per_line;
3220
3221 return ret;
3222 }
3223
3224 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3225 const struct intel_crtc *intel_crtc)
3226 {
3227 struct drm_device *dev = intel_crtc->base.dev;
3228 struct drm_i915_private *dev_priv = dev->dev_private;
3229 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3230
3231 /*
3232 * If ddb allocation of pipes changed, it may require recalculation of
3233 * watermarks
3234 */
3235 if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
3236 return true;
3237
3238 return false;
3239 }
3240
3241 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3242 struct intel_crtc_state *cstate,
3243 struct intel_plane_state *intel_pstate,
3244 uint16_t ddb_allocation,
3245 int level,
3246 uint16_t *out_blocks, /* out */
3247 uint8_t *out_lines /* out */)
3248 {
3249 struct drm_plane_state *pstate = &intel_pstate->base;
3250 struct drm_framebuffer *fb = pstate->fb;
3251 uint32_t latency = dev_priv->wm.skl_latency[level];
3252 uint32_t method1, method2;
3253 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3254 uint32_t res_blocks, res_lines;
3255 uint32_t selected_result;
3256 uint8_t cpp;
3257 uint32_t width = 0, height = 0;
3258
3259 if (latency == 0 || !cstate->base.active || !intel_pstate->visible)
3260 return false;
3261
3262 width = drm_rect_width(&intel_pstate->src) >> 16;
3263 height = drm_rect_height(&intel_pstate->src) >> 16;
3264
3265 if (intel_rotation_90_or_270(pstate->rotation))
3266 swap(width, height);
3267
3268 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3269 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
3270 cpp, latency);
3271 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3272 cstate->base.adjusted_mode.crtc_htotal,
3273 width,
3274 cpp,
3275 fb->modifier[0],
3276 latency);
3277
3278 plane_bytes_per_line = width * cpp;
3279 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3280
3281 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3282 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3283 uint32_t min_scanlines = 4;
3284 uint32_t y_tile_minimum;
3285 if (intel_rotation_90_or_270(pstate->rotation)) {
3286 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3287 drm_format_plane_cpp(fb->pixel_format, 1) :
3288 drm_format_plane_cpp(fb->pixel_format, 0);
3289
3290 switch (cpp) {
3291 case 1:
3292 min_scanlines = 16;
3293 break;
3294 case 2:
3295 min_scanlines = 8;
3296 break;
3297 case 8:
3298 WARN(1, "Unsupported pixel depth for rotation");
3299 }
3300 }
3301 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3302 selected_result = max(method2, y_tile_minimum);
3303 } else {
3304 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3305 selected_result = min(method1, method2);
3306 else
3307 selected_result = method1;
3308 }
3309
3310 res_blocks = selected_result + 1;
3311 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3312
3313 if (level >= 1 && level <= 7) {
3314 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3315 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3316 res_lines += 4;
3317 else
3318 res_blocks++;
3319 }
3320
3321 if (res_blocks >= ddb_allocation || res_lines > 31)
3322 return false;
3323
3324 *out_blocks = res_blocks;
3325 *out_lines = res_lines;
3326
3327 return true;
3328 }
3329
3330 static int
3331 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3332 struct skl_ddb_allocation *ddb,
3333 struct intel_crtc_state *cstate,
3334 int level,
3335 struct skl_wm_level *result)
3336 {
3337 struct drm_device *dev = dev_priv->dev;
3338 struct drm_atomic_state *state = cstate->base.state;
3339 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3340 struct drm_plane *plane;
3341 struct intel_plane *intel_plane;
3342 struct intel_plane_state *intel_pstate;
3343 uint16_t ddb_blocks;
3344 enum pipe pipe = intel_crtc->pipe;
3345
3346 /*
3347 * We'll only calculate watermarks for planes that are actually
3348 * enabled, so make sure all other planes are set as disabled.
3349 */
3350 memset(result, 0, sizeof(*result));
3351
3352 for_each_intel_plane_mask(dev, intel_plane, cstate->base.plane_mask) {
3353 int i = skl_wm_plane_id(intel_plane);
3354
3355 plane = &intel_plane->base;
3356 intel_pstate = NULL;
3357 if (state)
3358 intel_pstate =
3359 intel_atomic_get_existing_plane_state(state,
3360 intel_plane);
3361
3362 /*
3363 * Note: If we start supporting multiple pending atomic commits
3364 * against the same planes/CRTC's in the future, plane->state
3365 * will no longer be the correct pre-state to use for the
3366 * calculations here and we'll need to change where we get the
3367 * 'unchanged' plane data from.
3368 *
3369 * For now this is fine because we only allow one queued commit
3370 * against a CRTC. Even if the plane isn't modified by this
3371 * transaction and we don't have a plane lock, we still have
3372 * the CRTC's lock, so we know that no other transactions are
3373 * racing with us to update it.
3374 */
3375 if (!intel_pstate)
3376 intel_pstate = to_intel_plane_state(plane->state);
3377
3378 WARN_ON(!intel_pstate->base.fb);
3379
3380 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3381
3382 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3383 cstate,
3384 intel_pstate,
3385 ddb_blocks,
3386 level,
3387 &result->plane_res_b[i],
3388 &result->plane_res_l[i]);
3389 }
3390
3391 return 0;
3392 }
3393
3394 static uint32_t
3395 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3396 {
3397 if (!cstate->base.active)
3398 return 0;
3399
3400 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3401 return 0;
3402
3403 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3404 skl_pipe_pixel_rate(cstate));
3405 }
3406
3407 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3408 struct skl_wm_level *trans_wm /* out */)
3409 {
3410 struct drm_crtc *crtc = cstate->base.crtc;
3411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3412 struct intel_plane *intel_plane;
3413
3414 if (!cstate->base.active)
3415 return;
3416
3417 /* Until we know more, just disable transition WMs */
3418 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3419 int i = skl_wm_plane_id(intel_plane);
3420
3421 trans_wm->plane_en[i] = false;
3422 }
3423 }
3424
3425 static void skl_build_pipe_wm(struct intel_crtc_state *cstate,
3426 struct skl_ddb_allocation *ddb,
3427 struct skl_pipe_wm *pipe_wm)
3428 {
3429 struct drm_device *dev = cstate->base.crtc->dev;
3430 const struct drm_i915_private *dev_priv = dev->dev_private;
3431 int level, max_level = ilk_wm_max_level(dev);
3432
3433 for (level = 0; level <= max_level; level++) {
3434 skl_compute_wm_level(dev_priv, ddb, cstate,
3435 level, &pipe_wm->wm[level]);
3436 }
3437 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3438
3439 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3440 }
3441
3442 static void skl_compute_wm_results(struct drm_device *dev,
3443 struct skl_pipe_wm *p_wm,
3444 struct skl_wm_values *r,
3445 struct intel_crtc *intel_crtc)
3446 {
3447 int level, max_level = ilk_wm_max_level(dev);
3448 enum pipe pipe = intel_crtc->pipe;
3449 uint32_t temp;
3450 int i;
3451
3452 for (level = 0; level <= max_level; level++) {
3453 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3454 temp = 0;
3455
3456 temp |= p_wm->wm[level].plane_res_l[i] <<
3457 PLANE_WM_LINES_SHIFT;
3458 temp |= p_wm->wm[level].plane_res_b[i];
3459 if (p_wm->wm[level].plane_en[i])
3460 temp |= PLANE_WM_EN;
3461
3462 r->plane[pipe][i][level] = temp;
3463 }
3464
3465 temp = 0;
3466
3467 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3468 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3469
3470 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3471 temp |= PLANE_WM_EN;
3472
3473 r->plane[pipe][PLANE_CURSOR][level] = temp;
3474
3475 }
3476
3477 /* transition WMs */
3478 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3479 temp = 0;
3480 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3481 temp |= p_wm->trans_wm.plane_res_b[i];
3482 if (p_wm->trans_wm.plane_en[i])
3483 temp |= PLANE_WM_EN;
3484
3485 r->plane_trans[pipe][i] = temp;
3486 }
3487
3488 temp = 0;
3489 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3490 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3491 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3492 temp |= PLANE_WM_EN;
3493
3494 r->plane_trans[pipe][PLANE_CURSOR] = temp;
3495
3496 r->wm_linetime[pipe] = p_wm->linetime;
3497 }
3498
3499 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3500 i915_reg_t reg,
3501 const struct skl_ddb_entry *entry)
3502 {
3503 if (entry->end)
3504 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3505 else
3506 I915_WRITE(reg, 0);
3507 }
3508
3509 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3510 const struct skl_wm_values *new)
3511 {
3512 struct drm_device *dev = dev_priv->dev;
3513 struct intel_crtc *crtc;
3514
3515 for_each_intel_crtc(dev, crtc) {
3516 int i, level, max_level = ilk_wm_max_level(dev);
3517 enum pipe pipe = crtc->pipe;
3518
3519 if ((new->dirty_pipes & drm_crtc_mask(&crtc->base)) == 0)
3520 continue;
3521
3522 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3523
3524 for (level = 0; level <= max_level; level++) {
3525 for (i = 0; i < intel_num_planes(crtc); i++)
3526 I915_WRITE(PLANE_WM(pipe, i, level),
3527 new->plane[pipe][i][level]);
3528 I915_WRITE(CUR_WM(pipe, level),
3529 new->plane[pipe][PLANE_CURSOR][level]);
3530 }
3531 for (i = 0; i < intel_num_planes(crtc); i++)
3532 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3533 new->plane_trans[pipe][i]);
3534 I915_WRITE(CUR_WM_TRANS(pipe),
3535 new->plane_trans[pipe][PLANE_CURSOR]);
3536
3537 for (i = 0; i < intel_num_planes(crtc); i++) {
3538 skl_ddb_entry_write(dev_priv,
3539 PLANE_BUF_CFG(pipe, i),
3540 &new->ddb.plane[pipe][i]);
3541 skl_ddb_entry_write(dev_priv,
3542 PLANE_NV12_BUF_CFG(pipe, i),
3543 &new->ddb.y_plane[pipe][i]);
3544 }
3545
3546 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3547 &new->ddb.plane[pipe][PLANE_CURSOR]);
3548 }
3549 }
3550
3551 /*
3552 * When setting up a new DDB allocation arrangement, we need to correctly
3553 * sequence the times at which the new allocations for the pipes are taken into
3554 * account or we'll have pipes fetching from space previously allocated to
3555 * another pipe.
3556 *
3557 * Roughly the sequence looks like:
3558 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3559 * overlapping with a previous light-up pipe (another way to put it is:
3560 * pipes with their new allocation strickly included into their old ones).
3561 * 2. re-allocate the other pipes that get their allocation reduced
3562 * 3. allocate the pipes having their allocation increased
3563 *
3564 * Steps 1. and 2. are here to take care of the following case:
3565 * - Initially DDB looks like this:
3566 * | B | C |
3567 * - enable pipe A.
3568 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3569 * allocation
3570 * | A | B | C |
3571 *
3572 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3573 */
3574
3575 static void
3576 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3577 {
3578 int plane;
3579
3580 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3581
3582 for_each_plane(dev_priv, pipe, plane) {
3583 I915_WRITE(PLANE_SURF(pipe, plane),
3584 I915_READ(PLANE_SURF(pipe, plane)));
3585 }
3586 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3587 }
3588
3589 static bool
3590 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3591 const struct skl_ddb_allocation *new,
3592 enum pipe pipe)
3593 {
3594 uint16_t old_size, new_size;
3595
3596 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3597 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3598
3599 return old_size != new_size &&
3600 new->pipe[pipe].start >= old->pipe[pipe].start &&
3601 new->pipe[pipe].end <= old->pipe[pipe].end;
3602 }
3603
3604 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3605 struct skl_wm_values *new_values)
3606 {
3607 struct drm_device *dev = dev_priv->dev;
3608 struct skl_ddb_allocation *cur_ddb, *new_ddb;
3609 bool reallocated[I915_MAX_PIPES] = {};
3610 struct intel_crtc *crtc;
3611 enum pipe pipe;
3612
3613 new_ddb = &new_values->ddb;
3614 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3615
3616 /*
3617 * First pass: flush the pipes with the new allocation contained into
3618 * the old space.
3619 *
3620 * We'll wait for the vblank on those pipes to ensure we can safely
3621 * re-allocate the freed space without this pipe fetching from it.
3622 */
3623 for_each_intel_crtc(dev, crtc) {
3624 if (!crtc->active)
3625 continue;
3626
3627 pipe = crtc->pipe;
3628
3629 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3630 continue;
3631
3632 skl_wm_flush_pipe(dev_priv, pipe, 1);
3633 intel_wait_for_vblank(dev, pipe);
3634
3635 reallocated[pipe] = true;
3636 }
3637
3638
3639 /*
3640 * Second pass: flush the pipes that are having their allocation
3641 * reduced, but overlapping with a previous allocation.
3642 *
3643 * Here as well we need to wait for the vblank to make sure the freed
3644 * space is not used anymore.
3645 */
3646 for_each_intel_crtc(dev, crtc) {
3647 if (!crtc->active)
3648 continue;
3649
3650 pipe = crtc->pipe;
3651
3652 if (reallocated[pipe])
3653 continue;
3654
3655 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3656 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3657 skl_wm_flush_pipe(dev_priv, pipe, 2);
3658 intel_wait_for_vblank(dev, pipe);
3659 reallocated[pipe] = true;
3660 }
3661 }
3662
3663 /*
3664 * Third pass: flush the pipes that got more space allocated.
3665 *
3666 * We don't need to actively wait for the update here, next vblank
3667 * will just get more DDB space with the correct WM values.
3668 */
3669 for_each_intel_crtc(dev, crtc) {
3670 if (!crtc->active)
3671 continue;
3672
3673 pipe = crtc->pipe;
3674
3675 /*
3676 * At this point, only the pipes more space than before are
3677 * left to re-allocate.
3678 */
3679 if (reallocated[pipe])
3680 continue;
3681
3682 skl_wm_flush_pipe(dev_priv, pipe, 3);
3683 }
3684 }
3685
3686 static bool skl_update_pipe_wm(struct drm_crtc_state *cstate,
3687 struct skl_ddb_allocation *ddb, /* out */
3688 struct skl_pipe_wm *pipe_wm /* out */)
3689 {
3690 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3691 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3692
3693 skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3694
3695 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3696 return false;
3697
3698 intel_crtc->wm.active.skl = *pipe_wm;
3699
3700 return true;
3701 }
3702
3703 static void skl_update_other_pipe_wm(struct drm_device *dev,
3704 struct drm_crtc *crtc,
3705 struct skl_wm_values *r)
3706 {
3707 struct intel_crtc *intel_crtc;
3708 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3709
3710 /*
3711 * If the WM update hasn't changed the allocation for this_crtc (the
3712 * crtc we are currently computing the new WM values for), other
3713 * enabled crtcs will keep the same allocation and we don't need to
3714 * recompute anything for them.
3715 */
3716 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3717 return;
3718
3719 /*
3720 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3721 * other active pipes need new DDB allocation and WM values.
3722 */
3723 for_each_intel_crtc(dev, intel_crtc) {
3724 struct skl_pipe_wm pipe_wm = {};
3725 bool wm_changed;
3726
3727 if (this_crtc->pipe == intel_crtc->pipe)
3728 continue;
3729
3730 if (!intel_crtc->active)
3731 continue;
3732
3733 wm_changed = skl_update_pipe_wm(intel_crtc->base.state,
3734 &r->ddb, &pipe_wm);
3735
3736 /*
3737 * If we end up re-computing the other pipe WM values, it's
3738 * because it was really needed, so we expect the WM values to
3739 * be different.
3740 */
3741 WARN_ON(!wm_changed);
3742
3743 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
3744 r->dirty_pipes |= drm_crtc_mask(&intel_crtc->base);
3745 }
3746 }
3747
3748 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3749 {
3750 watermarks->wm_linetime[pipe] = 0;
3751 memset(watermarks->plane[pipe], 0,
3752 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3753 memset(watermarks->plane_trans[pipe],
3754 0, sizeof(uint32_t) * I915_MAX_PLANES);
3755 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3756 }
3757
3758 static int
3759 skl_compute_ddb(struct drm_atomic_state *state)
3760 {
3761 struct drm_device *dev = state->dev;
3762 struct drm_i915_private *dev_priv = to_i915(dev);
3763 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3764 struct intel_crtc *intel_crtc;
3765 unsigned realloc_pipes = dev_priv->active_crtcs;
3766 int ret;
3767
3768 /*
3769 * If this is our first atomic update following hardware readout,
3770 * we can't trust the DDB that the BIOS programmed for us. Let's
3771 * pretend that all pipes switched active status so that we'll
3772 * ensure a full DDB recompute.
3773 */
3774 if (dev_priv->wm.distrust_bios_wm)
3775 intel_state->active_pipe_changes = ~0;
3776
3777 /*
3778 * If the modeset changes which CRTC's are active, we need to
3779 * recompute the DDB allocation for *all* active pipes, even
3780 * those that weren't otherwise being modified in any way by this
3781 * atomic commit. Due to the shrinking of the per-pipe allocations
3782 * when new active CRTC's are added, it's possible for a pipe that
3783 * we were already using and aren't changing at all here to suddenly
3784 * become invalid if its DDB needs exceeds its new allocation.
3785 *
3786 * Note that if we wind up doing a full DDB recompute, we can't let
3787 * any other display updates race with this transaction, so we need
3788 * to grab the lock on *all* CRTC's.
3789 */
3790 if (intel_state->active_pipe_changes)
3791 realloc_pipes = ~0;
3792
3793 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
3794 struct intel_crtc_state *cstate;
3795
3796 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
3797 if (IS_ERR(cstate))
3798 return PTR_ERR(cstate);
3799
3800 ret = skl_allocate_pipe_ddb(cstate, &intel_state->ddb);
3801 if (ret)
3802 return ret;
3803 }
3804
3805 return 0;
3806 }
3807
3808 static int
3809 skl_compute_wm(struct drm_atomic_state *state)
3810 {
3811 struct drm_crtc *crtc;
3812 struct drm_crtc_state *cstate;
3813 int ret, i;
3814 bool changed = false;
3815
3816 /*
3817 * If this transaction isn't actually touching any CRTC's, don't
3818 * bother with watermark calculation. Note that if we pass this
3819 * test, we're guaranteed to hold at least one CRTC state mutex,
3820 * which means we can safely use values like dev_priv->active_crtcs
3821 * since any racing commits that want to update them would need to
3822 * hold _all_ CRTC state mutexes.
3823 */
3824 for_each_crtc_in_state(state, crtc, cstate, i)
3825 changed = true;
3826 if (!changed)
3827 return 0;
3828
3829 ret = skl_compute_ddb(state);
3830 if (ret)
3831 return ret;
3832
3833 return 0;
3834 }
3835
3836 static void skl_update_wm(struct drm_crtc *crtc)
3837 {
3838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3839 struct drm_device *dev = crtc->dev;
3840 struct drm_i915_private *dev_priv = dev->dev_private;
3841 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3842 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3843 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
3844
3845
3846 /* Clear all dirty flags */
3847 results->dirty_pipes = 0;
3848
3849 skl_clear_wm(results, intel_crtc->pipe);
3850
3851 if (!skl_update_pipe_wm(crtc->state, &results->ddb, pipe_wm))
3852 return;
3853
3854 skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
3855 results->dirty_pipes |= drm_crtc_mask(&intel_crtc->base);
3856
3857 skl_update_other_pipe_wm(dev, crtc, results);
3858 skl_write_wm_values(dev_priv, results);
3859 skl_flush_wm_values(dev_priv, results);
3860
3861 /* store the new configuration */
3862 dev_priv->wm.skl_hw = *results;
3863 }
3864
3865 static void ilk_compute_wm_config(struct drm_device *dev,
3866 struct intel_wm_config *config)
3867 {
3868 struct intel_crtc *crtc;
3869
3870 /* Compute the currently _active_ config */
3871 for_each_intel_crtc(dev, crtc) {
3872 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3873
3874 if (!wm->pipe_enabled)
3875 continue;
3876
3877 config->sprites_enabled |= wm->sprites_enabled;
3878 config->sprites_scaled |= wm->sprites_scaled;
3879 config->num_pipes_active++;
3880 }
3881 }
3882
3883 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
3884 {
3885 struct drm_device *dev = dev_priv->dev;
3886 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3887 struct ilk_wm_maximums max;
3888 struct intel_wm_config config = {};
3889 struct ilk_wm_values results = {};
3890 enum intel_ddb_partitioning partitioning;
3891
3892 ilk_compute_wm_config(dev, &config);
3893
3894 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3895 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3896
3897 /* 5/6 split only in single pipe config on IVB+ */
3898 if (INTEL_INFO(dev)->gen >= 7 &&
3899 config.num_pipes_active == 1 && config.sprites_enabled) {
3900 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3901 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3902
3903 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3904 } else {
3905 best_lp_wm = &lp_wm_1_2;
3906 }
3907
3908 partitioning = (best_lp_wm == &lp_wm_1_2) ?
3909 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3910
3911 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3912
3913 ilk_write_wm_values(dev_priv, &results);
3914 }
3915
3916 static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
3917 {
3918 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3919 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3920
3921 mutex_lock(&dev_priv->wm.wm_mutex);
3922 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
3923 ilk_program_watermarks(dev_priv);
3924 mutex_unlock(&dev_priv->wm.wm_mutex);
3925 }
3926
3927 static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
3928 {
3929 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3930 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3931
3932 mutex_lock(&dev_priv->wm.wm_mutex);
3933 if (cstate->wm.need_postvbl_update) {
3934 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
3935 ilk_program_watermarks(dev_priv);
3936 }
3937 mutex_unlock(&dev_priv->wm.wm_mutex);
3938 }
3939
3940 static void skl_pipe_wm_active_state(uint32_t val,
3941 struct skl_pipe_wm *active,
3942 bool is_transwm,
3943 bool is_cursor,
3944 int i,
3945 int level)
3946 {
3947 bool is_enabled = (val & PLANE_WM_EN) != 0;
3948
3949 if (!is_transwm) {
3950 if (!is_cursor) {
3951 active->wm[level].plane_en[i] = is_enabled;
3952 active->wm[level].plane_res_b[i] =
3953 val & PLANE_WM_BLOCKS_MASK;
3954 active->wm[level].plane_res_l[i] =
3955 (val >> PLANE_WM_LINES_SHIFT) &
3956 PLANE_WM_LINES_MASK;
3957 } else {
3958 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3959 active->wm[level].plane_res_b[PLANE_CURSOR] =
3960 val & PLANE_WM_BLOCKS_MASK;
3961 active->wm[level].plane_res_l[PLANE_CURSOR] =
3962 (val >> PLANE_WM_LINES_SHIFT) &
3963 PLANE_WM_LINES_MASK;
3964 }
3965 } else {
3966 if (!is_cursor) {
3967 active->trans_wm.plane_en[i] = is_enabled;
3968 active->trans_wm.plane_res_b[i] =
3969 val & PLANE_WM_BLOCKS_MASK;
3970 active->trans_wm.plane_res_l[i] =
3971 (val >> PLANE_WM_LINES_SHIFT) &
3972 PLANE_WM_LINES_MASK;
3973 } else {
3974 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3975 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3976 val & PLANE_WM_BLOCKS_MASK;
3977 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3978 (val >> PLANE_WM_LINES_SHIFT) &
3979 PLANE_WM_LINES_MASK;
3980 }
3981 }
3982 }
3983
3984 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3985 {
3986 struct drm_device *dev = crtc->dev;
3987 struct drm_i915_private *dev_priv = dev->dev_private;
3988 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3990 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3991 struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
3992 enum pipe pipe = intel_crtc->pipe;
3993 int level, i, max_level;
3994 uint32_t temp;
3995
3996 max_level = ilk_wm_max_level(dev);
3997
3998 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3999
4000 for (level = 0; level <= max_level; level++) {
4001 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4002 hw->plane[pipe][i][level] =
4003 I915_READ(PLANE_WM(pipe, i, level));
4004 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
4005 }
4006
4007 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4008 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4009 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
4010
4011 if (!intel_crtc->active)
4012 return;
4013
4014 hw->dirty_pipes |= drm_crtc_mask(crtc);
4015
4016 active->linetime = hw->wm_linetime[pipe];
4017
4018 for (level = 0; level <= max_level; level++) {
4019 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4020 temp = hw->plane[pipe][i][level];
4021 skl_pipe_wm_active_state(temp, active, false,
4022 false, i, level);
4023 }
4024 temp = hw->plane[pipe][PLANE_CURSOR][level];
4025 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4026 }
4027
4028 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4029 temp = hw->plane_trans[pipe][i];
4030 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4031 }
4032
4033 temp = hw->plane_trans[pipe][PLANE_CURSOR];
4034 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4035
4036 intel_crtc->wm.active.skl = *active;
4037 }
4038
4039 void skl_wm_get_hw_state(struct drm_device *dev)
4040 {
4041 struct drm_i915_private *dev_priv = dev->dev_private;
4042 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4043 struct drm_crtc *crtc;
4044 struct intel_crtc *intel_crtc;
4045
4046 skl_ddb_get_hw_state(dev_priv, ddb);
4047 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4048 skl_pipe_wm_get_hw_state(crtc);
4049
4050 if (dev_priv->active_crtcs) {
4051 /* Fully recompute DDB on first atomic commit */
4052 dev_priv->wm.distrust_bios_wm = true;
4053 } else {
4054 /* Easy/common case; just sanitize DDB now if everything off */
4055 memset(ddb, 0, sizeof(*ddb));
4056 }
4057
4058 /* Calculate plane data rates */
4059 for_each_intel_crtc(dev, intel_crtc) {
4060 struct intel_crtc_state *cstate = intel_crtc->config;
4061 struct intel_plane *intel_plane;
4062
4063 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4064 const struct drm_plane_state *pstate =
4065 intel_plane->base.state;
4066 int id = skl_wm_plane_id(intel_plane);
4067
4068 cstate->wm.skl.plane_data_rate[id] =
4069 skl_plane_relative_data_rate(cstate, pstate, 0);
4070 cstate->wm.skl.plane_y_data_rate[id] =
4071 skl_plane_relative_data_rate(cstate, pstate, 1);
4072 }
4073 }
4074 }
4075
4076 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4077 {
4078 struct drm_device *dev = crtc->dev;
4079 struct drm_i915_private *dev_priv = dev->dev_private;
4080 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4082 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4083 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4084 enum pipe pipe = intel_crtc->pipe;
4085 static const i915_reg_t wm0_pipe_reg[] = {
4086 [PIPE_A] = WM0_PIPEA_ILK,
4087 [PIPE_B] = WM0_PIPEB_ILK,
4088 [PIPE_C] = WM0_PIPEC_IVB,
4089 };
4090
4091 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4092 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4093 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4094
4095 active->pipe_enabled = intel_crtc->active;
4096
4097 if (active->pipe_enabled) {
4098 u32 tmp = hw->wm_pipe[pipe];
4099
4100 /*
4101 * For active pipes LP0 watermark is marked as
4102 * enabled, and LP1+ watermaks as disabled since
4103 * we can't really reverse compute them in case
4104 * multiple pipes are active.
4105 */
4106 active->wm[0].enable = true;
4107 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4108 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4109 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4110 active->linetime = hw->wm_linetime[pipe];
4111 } else {
4112 int level, max_level = ilk_wm_max_level(dev);
4113
4114 /*
4115 * For inactive pipes, all watermark levels
4116 * should be marked as enabled but zeroed,
4117 * which is what we'd compute them to.
4118 */
4119 for (level = 0; level <= max_level; level++)
4120 active->wm[level].enable = true;
4121 }
4122
4123 intel_crtc->wm.active.ilk = *active;
4124 }
4125
4126 #define _FW_WM(value, plane) \
4127 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4128 #define _FW_WM_VLV(value, plane) \
4129 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4130
4131 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4132 struct vlv_wm_values *wm)
4133 {
4134 enum pipe pipe;
4135 uint32_t tmp;
4136
4137 for_each_pipe(dev_priv, pipe) {
4138 tmp = I915_READ(VLV_DDL(pipe));
4139
4140 wm->ddl[pipe].primary =
4141 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4142 wm->ddl[pipe].cursor =
4143 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4144 wm->ddl[pipe].sprite[0] =
4145 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4146 wm->ddl[pipe].sprite[1] =
4147 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4148 }
4149
4150 tmp = I915_READ(DSPFW1);
4151 wm->sr.plane = _FW_WM(tmp, SR);
4152 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4153 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4154 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4155
4156 tmp = I915_READ(DSPFW2);
4157 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4158 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4159 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4160
4161 tmp = I915_READ(DSPFW3);
4162 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4163
4164 if (IS_CHERRYVIEW(dev_priv)) {
4165 tmp = I915_READ(DSPFW7_CHV);
4166 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4167 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4168
4169 tmp = I915_READ(DSPFW8_CHV);
4170 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4171 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4172
4173 tmp = I915_READ(DSPFW9_CHV);
4174 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4175 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4176
4177 tmp = I915_READ(DSPHOWM);
4178 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4179 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4180 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4181 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4182 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4183 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4184 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4185 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4186 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4187 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4188 } else {
4189 tmp = I915_READ(DSPFW7);
4190 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4191 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4192
4193 tmp = I915_READ(DSPHOWM);
4194 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4195 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4196 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4197 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4198 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4199 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4200 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4201 }
4202 }
4203
4204 #undef _FW_WM
4205 #undef _FW_WM_VLV
4206
4207 void vlv_wm_get_hw_state(struct drm_device *dev)
4208 {
4209 struct drm_i915_private *dev_priv = to_i915(dev);
4210 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4211 struct intel_plane *plane;
4212 enum pipe pipe;
4213 u32 val;
4214
4215 vlv_read_wm_values(dev_priv, wm);
4216
4217 for_each_intel_plane(dev, plane) {
4218 switch (plane->base.type) {
4219 int sprite;
4220 case DRM_PLANE_TYPE_CURSOR:
4221 plane->wm.fifo_size = 63;
4222 break;
4223 case DRM_PLANE_TYPE_PRIMARY:
4224 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4225 break;
4226 case DRM_PLANE_TYPE_OVERLAY:
4227 sprite = plane->plane;
4228 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4229 break;
4230 }
4231 }
4232
4233 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4234 wm->level = VLV_WM_LEVEL_PM2;
4235
4236 if (IS_CHERRYVIEW(dev_priv)) {
4237 mutex_lock(&dev_priv->rps.hw_lock);
4238
4239 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4240 if (val & DSP_MAXFIFO_PM5_ENABLE)
4241 wm->level = VLV_WM_LEVEL_PM5;
4242
4243 /*
4244 * If DDR DVFS is disabled in the BIOS, Punit
4245 * will never ack the request. So if that happens
4246 * assume we don't have to enable/disable DDR DVFS
4247 * dynamically. To test that just set the REQ_ACK
4248 * bit to poke the Punit, but don't change the
4249 * HIGH/LOW bits so that we don't actually change
4250 * the current state.
4251 */
4252 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4253 val |= FORCE_DDR_FREQ_REQ_ACK;
4254 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4255
4256 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4257 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4258 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4259 "assuming DDR DVFS is disabled\n");
4260 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4261 } else {
4262 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4263 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4264 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4265 }
4266
4267 mutex_unlock(&dev_priv->rps.hw_lock);
4268 }
4269
4270 for_each_pipe(dev_priv, pipe)
4271 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4272 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4273 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4274
4275 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4276 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4277 }
4278
4279 void ilk_wm_get_hw_state(struct drm_device *dev)
4280 {
4281 struct drm_i915_private *dev_priv = dev->dev_private;
4282 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4283 struct drm_crtc *crtc;
4284
4285 for_each_crtc(dev, crtc)
4286 ilk_pipe_wm_get_hw_state(crtc);
4287
4288 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4289 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4290 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4291
4292 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4293 if (INTEL_INFO(dev)->gen >= 7) {
4294 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4295 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4296 }
4297
4298 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4299 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4300 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4301 else if (IS_IVYBRIDGE(dev))
4302 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4303 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4304
4305 hw->enable_fbc_wm =
4306 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4307 }
4308
4309 /**
4310 * intel_update_watermarks - update FIFO watermark values based on current modes
4311 *
4312 * Calculate watermark values for the various WM regs based on current mode
4313 * and plane configuration.
4314 *
4315 * There are several cases to deal with here:
4316 * - normal (i.e. non-self-refresh)
4317 * - self-refresh (SR) mode
4318 * - lines are large relative to FIFO size (buffer can hold up to 2)
4319 * - lines are small relative to FIFO size (buffer can hold more than 2
4320 * lines), so need to account for TLB latency
4321 *
4322 * The normal calculation is:
4323 * watermark = dotclock * bytes per pixel * latency
4324 * where latency is platform & configuration dependent (we assume pessimal
4325 * values here).
4326 *
4327 * The SR calculation is:
4328 * watermark = (trunc(latency/line time)+1) * surface width *
4329 * bytes per pixel
4330 * where
4331 * line time = htotal / dotclock
4332 * surface width = hdisplay for normal plane and 64 for cursor
4333 * and latency is assumed to be high, as above.
4334 *
4335 * The final value programmed to the register should always be rounded up,
4336 * and include an extra 2 entries to account for clock crossings.
4337 *
4338 * We don't use the sprite, so we can ignore that. And on Crestline we have
4339 * to set the non-SR watermarks to 8.
4340 */
4341 void intel_update_watermarks(struct drm_crtc *crtc)
4342 {
4343 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4344
4345 if (dev_priv->display.update_wm)
4346 dev_priv->display.update_wm(crtc);
4347 }
4348
4349 /*
4350 * Lock protecting IPS related data structures
4351 */
4352 DEFINE_SPINLOCK(mchdev_lock);
4353
4354 /* Global for IPS driver to get at the current i915 device. Protected by
4355 * mchdev_lock. */
4356 static struct drm_i915_private *i915_mch_dev;
4357
4358 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4359 {
4360 u16 rgvswctl;
4361
4362 assert_spin_locked(&mchdev_lock);
4363
4364 rgvswctl = I915_READ16(MEMSWCTL);
4365 if (rgvswctl & MEMCTL_CMD_STS) {
4366 DRM_DEBUG("gpu busy, RCS change rejected\n");
4367 return false; /* still busy with another command */
4368 }
4369
4370 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4371 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4372 I915_WRITE16(MEMSWCTL, rgvswctl);
4373 POSTING_READ16(MEMSWCTL);
4374
4375 rgvswctl |= MEMCTL_CMD_STS;
4376 I915_WRITE16(MEMSWCTL, rgvswctl);
4377
4378 return true;
4379 }
4380
4381 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4382 {
4383 u32 rgvmodectl;
4384 u8 fmax, fmin, fstart, vstart;
4385
4386 spin_lock_irq(&mchdev_lock);
4387
4388 rgvmodectl = I915_READ(MEMMODECTL);
4389
4390 /* Enable temp reporting */
4391 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4392 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4393
4394 /* 100ms RC evaluation intervals */
4395 I915_WRITE(RCUPEI, 100000);
4396 I915_WRITE(RCDNEI, 100000);
4397
4398 /* Set max/min thresholds to 90ms and 80ms respectively */
4399 I915_WRITE(RCBMAXAVG, 90000);
4400 I915_WRITE(RCBMINAVG, 80000);
4401
4402 I915_WRITE(MEMIHYST, 1);
4403
4404 /* Set up min, max, and cur for interrupt handling */
4405 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4406 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4407 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4408 MEMMODE_FSTART_SHIFT;
4409
4410 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4411 PXVFREQ_PX_SHIFT;
4412
4413 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4414 dev_priv->ips.fstart = fstart;
4415
4416 dev_priv->ips.max_delay = fstart;
4417 dev_priv->ips.min_delay = fmin;
4418 dev_priv->ips.cur_delay = fstart;
4419
4420 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4421 fmax, fmin, fstart);
4422
4423 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4424
4425 /*
4426 * Interrupts will be enabled in ironlake_irq_postinstall
4427 */
4428
4429 I915_WRITE(VIDSTART, vstart);
4430 POSTING_READ(VIDSTART);
4431
4432 rgvmodectl |= MEMMODE_SWMODE_EN;
4433 I915_WRITE(MEMMODECTL, rgvmodectl);
4434
4435 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4436 DRM_ERROR("stuck trying to change perf mode\n");
4437 mdelay(1);
4438
4439 ironlake_set_drps(dev_priv, fstart);
4440
4441 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4442 I915_READ(DDREC) + I915_READ(CSIEC);
4443 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4444 dev_priv->ips.last_count2 = I915_READ(GFXEC);
4445 dev_priv->ips.last_time2 = ktime_get_raw_ns();
4446
4447 spin_unlock_irq(&mchdev_lock);
4448 }
4449
4450 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4451 {
4452 u16 rgvswctl;
4453
4454 spin_lock_irq(&mchdev_lock);
4455
4456 rgvswctl = I915_READ16(MEMSWCTL);
4457
4458 /* Ack interrupts, disable EFC interrupt */
4459 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4460 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4461 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4462 I915_WRITE(DEIIR, DE_PCU_EVENT);
4463 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4464
4465 /* Go back to the starting frequency */
4466 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4467 mdelay(1);
4468 rgvswctl |= MEMCTL_CMD_STS;
4469 I915_WRITE(MEMSWCTL, rgvswctl);
4470 mdelay(1);
4471
4472 spin_unlock_irq(&mchdev_lock);
4473 }
4474
4475 /* There's a funny hw issue where the hw returns all 0 when reading from
4476 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4477 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4478 * all limits and the gpu stuck at whatever frequency it is at atm).
4479 */
4480 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4481 {
4482 u32 limits;
4483
4484 /* Only set the down limit when we've reached the lowest level to avoid
4485 * getting more interrupts, otherwise leave this clear. This prevents a
4486 * race in the hw when coming out of rc6: There's a tiny window where
4487 * the hw runs at the minimal clock before selecting the desired
4488 * frequency, if the down threshold expires in that window we will not
4489 * receive a down interrupt. */
4490 if (IS_GEN9(dev_priv)) {
4491 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4492 if (val <= dev_priv->rps.min_freq_softlimit)
4493 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4494 } else {
4495 limits = dev_priv->rps.max_freq_softlimit << 24;
4496 if (val <= dev_priv->rps.min_freq_softlimit)
4497 limits |= dev_priv->rps.min_freq_softlimit << 16;
4498 }
4499
4500 return limits;
4501 }
4502
4503 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4504 {
4505 int new_power;
4506 u32 threshold_up = 0, threshold_down = 0; /* in % */
4507 u32 ei_up = 0, ei_down = 0;
4508
4509 new_power = dev_priv->rps.power;
4510 switch (dev_priv->rps.power) {
4511 case LOW_POWER:
4512 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4513 new_power = BETWEEN;
4514 break;
4515
4516 case BETWEEN:
4517 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4518 new_power = LOW_POWER;
4519 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4520 new_power = HIGH_POWER;
4521 break;
4522
4523 case HIGH_POWER:
4524 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4525 new_power = BETWEEN;
4526 break;
4527 }
4528 /* Max/min bins are special */
4529 if (val <= dev_priv->rps.min_freq_softlimit)
4530 new_power = LOW_POWER;
4531 if (val >= dev_priv->rps.max_freq_softlimit)
4532 new_power = HIGH_POWER;
4533 if (new_power == dev_priv->rps.power)
4534 return;
4535
4536 /* Note the units here are not exactly 1us, but 1280ns. */
4537 switch (new_power) {
4538 case LOW_POWER:
4539 /* Upclock if more than 95% busy over 16ms */
4540 ei_up = 16000;
4541 threshold_up = 95;
4542
4543 /* Downclock if less than 85% busy over 32ms */
4544 ei_down = 32000;
4545 threshold_down = 85;
4546 break;
4547
4548 case BETWEEN:
4549 /* Upclock if more than 90% busy over 13ms */
4550 ei_up = 13000;
4551 threshold_up = 90;
4552
4553 /* Downclock if less than 75% busy over 32ms */
4554 ei_down = 32000;
4555 threshold_down = 75;
4556 break;
4557
4558 case HIGH_POWER:
4559 /* Upclock if more than 85% busy over 10ms */
4560 ei_up = 10000;
4561 threshold_up = 85;
4562
4563 /* Downclock if less than 60% busy over 32ms */
4564 ei_down = 32000;
4565 threshold_down = 60;
4566 break;
4567 }
4568
4569 I915_WRITE(GEN6_RP_UP_EI,
4570 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4571 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4572 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4573
4574 I915_WRITE(GEN6_RP_DOWN_EI,
4575 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4576 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4577 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4578
4579 I915_WRITE(GEN6_RP_CONTROL,
4580 GEN6_RP_MEDIA_TURBO |
4581 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4582 GEN6_RP_MEDIA_IS_GFX |
4583 GEN6_RP_ENABLE |
4584 GEN6_RP_UP_BUSY_AVG |
4585 GEN6_RP_DOWN_IDLE_AVG);
4586
4587 dev_priv->rps.power = new_power;
4588 dev_priv->rps.up_threshold = threshold_up;
4589 dev_priv->rps.down_threshold = threshold_down;
4590 dev_priv->rps.last_adj = 0;
4591 }
4592
4593 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4594 {
4595 u32 mask = 0;
4596
4597 if (val > dev_priv->rps.min_freq_softlimit)
4598 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4599 if (val < dev_priv->rps.max_freq_softlimit)
4600 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4601
4602 mask &= dev_priv->pm_rps_events;
4603
4604 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4605 }
4606
4607 /* gen6_set_rps is called to update the frequency request, but should also be
4608 * called when the range (min_delay and max_delay) is modified so that we can
4609 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4610 static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4611 {
4612 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4613 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4614 return;
4615
4616 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4617 WARN_ON(val > dev_priv->rps.max_freq);
4618 WARN_ON(val < dev_priv->rps.min_freq);
4619
4620 /* min/max delay may still have been modified so be sure to
4621 * write the limits value.
4622 */
4623 if (val != dev_priv->rps.cur_freq) {
4624 gen6_set_rps_thresholds(dev_priv, val);
4625
4626 if (IS_GEN9(dev_priv))
4627 I915_WRITE(GEN6_RPNSWREQ,
4628 GEN9_FREQUENCY(val));
4629 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4630 I915_WRITE(GEN6_RPNSWREQ,
4631 HSW_FREQUENCY(val));
4632 else
4633 I915_WRITE(GEN6_RPNSWREQ,
4634 GEN6_FREQUENCY(val) |
4635 GEN6_OFFSET(0) |
4636 GEN6_AGGRESSIVE_TURBO);
4637 }
4638
4639 /* Make sure we continue to get interrupts
4640 * until we hit the minimum or maximum frequencies.
4641 */
4642 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4643 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4644
4645 POSTING_READ(GEN6_RPNSWREQ);
4646
4647 dev_priv->rps.cur_freq = val;
4648 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4649 }
4650
4651 static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4652 {
4653 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4654 WARN_ON(val > dev_priv->rps.max_freq);
4655 WARN_ON(val < dev_priv->rps.min_freq);
4656
4657 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4658 "Odd GPU freq value\n"))
4659 val &= ~1;
4660
4661 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4662
4663 if (val != dev_priv->rps.cur_freq) {
4664 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4665 if (!IS_CHERRYVIEW(dev_priv))
4666 gen6_set_rps_thresholds(dev_priv, val);
4667 }
4668
4669 dev_priv->rps.cur_freq = val;
4670 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4671 }
4672
4673 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4674 *
4675 * * If Gfx is Idle, then
4676 * 1. Forcewake Media well.
4677 * 2. Request idle freq.
4678 * 3. Release Forcewake of Media well.
4679 */
4680 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4681 {
4682 u32 val = dev_priv->rps.idle_freq;
4683
4684 if (dev_priv->rps.cur_freq <= val)
4685 return;
4686
4687 /* Wake up the media well, as that takes a lot less
4688 * power than the Render well. */
4689 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4690 valleyview_set_rps(dev_priv, val);
4691 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4692 }
4693
4694 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4695 {
4696 mutex_lock(&dev_priv->rps.hw_lock);
4697 if (dev_priv->rps.enabled) {
4698 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4699 gen6_rps_reset_ei(dev_priv);
4700 I915_WRITE(GEN6_PMINTRMSK,
4701 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4702 }
4703 mutex_unlock(&dev_priv->rps.hw_lock);
4704 }
4705
4706 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4707 {
4708 mutex_lock(&dev_priv->rps.hw_lock);
4709 if (dev_priv->rps.enabled) {
4710 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4711 vlv_set_rps_idle(dev_priv);
4712 else
4713 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
4714 dev_priv->rps.last_adj = 0;
4715 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4716 }
4717 mutex_unlock(&dev_priv->rps.hw_lock);
4718
4719 spin_lock(&dev_priv->rps.client_lock);
4720 while (!list_empty(&dev_priv->rps.clients))
4721 list_del_init(dev_priv->rps.clients.next);
4722 spin_unlock(&dev_priv->rps.client_lock);
4723 }
4724
4725 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4726 struct intel_rps_client *rps,
4727 unsigned long submitted)
4728 {
4729 /* This is intentionally racy! We peek at the state here, then
4730 * validate inside the RPS worker.
4731 */
4732 if (!(dev_priv->mm.busy &&
4733 dev_priv->rps.enabled &&
4734 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4735 return;
4736
4737 /* Force a RPS boost (and don't count it against the client) if
4738 * the GPU is severely congested.
4739 */
4740 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4741 rps = NULL;
4742
4743 spin_lock(&dev_priv->rps.client_lock);
4744 if (rps == NULL || list_empty(&rps->link)) {
4745 spin_lock_irq(&dev_priv->irq_lock);
4746 if (dev_priv->rps.interrupts_enabled) {
4747 dev_priv->rps.client_boost = true;
4748 queue_work(dev_priv->wq, &dev_priv->rps.work);
4749 }
4750 spin_unlock_irq(&dev_priv->irq_lock);
4751
4752 if (rps != NULL) {
4753 list_add(&rps->link, &dev_priv->rps.clients);
4754 rps->boosts++;
4755 } else
4756 dev_priv->rps.boosts++;
4757 }
4758 spin_unlock(&dev_priv->rps.client_lock);
4759 }
4760
4761 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
4762 {
4763 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4764 valleyview_set_rps(dev_priv, val);
4765 else
4766 gen6_set_rps(dev_priv, val);
4767 }
4768
4769 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
4770 {
4771 I915_WRITE(GEN6_RC_CONTROL, 0);
4772 I915_WRITE(GEN9_PG_ENABLE, 0);
4773 }
4774
4775 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
4776 {
4777 I915_WRITE(GEN6_RP_CONTROL, 0);
4778 }
4779
4780 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
4781 {
4782 I915_WRITE(GEN6_RC_CONTROL, 0);
4783 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4784 I915_WRITE(GEN6_RP_CONTROL, 0);
4785 }
4786
4787 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
4788 {
4789 I915_WRITE(GEN6_RC_CONTROL, 0);
4790 }
4791
4792 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
4793 {
4794 /* we're doing forcewake before Disabling RC6,
4795 * This what the BIOS expects when going into suspend */
4796 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4797
4798 I915_WRITE(GEN6_RC_CONTROL, 0);
4799
4800 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4801 }
4802
4803 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
4804 {
4805 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4806 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4807 mode = GEN6_RC_CTL_RC6_ENABLE;
4808 else
4809 mode = 0;
4810 }
4811 if (HAS_RC6p(dev_priv))
4812 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4813 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4814 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4815 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
4816
4817 else
4818 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4819 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
4820 }
4821
4822 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
4823 {
4824 struct i915_ggtt *ggtt = &dev_priv->ggtt;
4825 bool enable_rc6 = true;
4826 unsigned long rc6_ctx_base;
4827
4828 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4829 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4830 enable_rc6 = false;
4831 }
4832
4833 /*
4834 * The exact context size is not known for BXT, so assume a page size
4835 * for this check.
4836 */
4837 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
4838 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
4839 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
4840 ggtt->stolen_reserved_size))) {
4841 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4842 enable_rc6 = false;
4843 }
4844
4845 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4846 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4847 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4848 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4849 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4850 enable_rc6 = false;
4851 }
4852
4853 if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4854 GEN6_RC_CTL_HW_ENABLE)) &&
4855 ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4856 !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4857 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4858 enable_rc6 = false;
4859 }
4860
4861 return enable_rc6;
4862 }
4863
4864 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
4865 {
4866 /* No RC6 before Ironlake and code is gone for ilk. */
4867 if (INTEL_INFO(dev_priv)->gen < 6)
4868 return 0;
4869
4870 if (!enable_rc6)
4871 return 0;
4872
4873 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
4874 DRM_INFO("RC6 disabled by BIOS\n");
4875 return 0;
4876 }
4877
4878 /* Respect the kernel parameter if it is set */
4879 if (enable_rc6 >= 0) {
4880 int mask;
4881
4882 if (HAS_RC6p(dev_priv))
4883 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4884 INTEL_RC6pp_ENABLE;
4885 else
4886 mask = INTEL_RC6_ENABLE;
4887
4888 if ((enable_rc6 & mask) != enable_rc6)
4889 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4890 enable_rc6 & mask, enable_rc6, mask);
4891
4892 return enable_rc6 & mask;
4893 }
4894
4895 if (IS_IVYBRIDGE(dev_priv))
4896 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4897
4898 return INTEL_RC6_ENABLE;
4899 }
4900
4901 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
4902 {
4903 uint32_t rp_state_cap;
4904 u32 ddcc_status = 0;
4905 int ret;
4906
4907 /* All of these values are in units of 50MHz */
4908 dev_priv->rps.cur_freq = 0;
4909 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4910 if (IS_BROXTON(dev_priv)) {
4911 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4912 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4913 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4914 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4915 } else {
4916 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4917 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4918 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4919 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4920 }
4921
4922 /* hw_max = RP0 until we check for overclocking */
4923 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4924
4925 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4926 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
4927 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4928 ret = sandybridge_pcode_read(dev_priv,
4929 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4930 &ddcc_status);
4931 if (0 == ret)
4932 dev_priv->rps.efficient_freq =
4933 clamp_t(u8,
4934 ((ddcc_status >> 8) & 0xff),
4935 dev_priv->rps.min_freq,
4936 dev_priv->rps.max_freq);
4937 }
4938
4939 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4940 /* Store the frequency values in 16.66 MHZ units, which is
4941 the natural hardware unit for SKL */
4942 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4943 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4944 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4945 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4946 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4947 }
4948
4949 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4950
4951 /* Preserve min/max settings in case of re-init */
4952 if (dev_priv->rps.max_freq_softlimit == 0)
4953 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4954
4955 if (dev_priv->rps.min_freq_softlimit == 0) {
4956 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4957 dev_priv->rps.min_freq_softlimit =
4958 max_t(int, dev_priv->rps.efficient_freq,
4959 intel_freq_opcode(dev_priv, 450));
4960 else
4961 dev_priv->rps.min_freq_softlimit =
4962 dev_priv->rps.min_freq;
4963 }
4964 }
4965
4966 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4967 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
4968 {
4969 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4970
4971 gen6_init_rps_frequencies(dev_priv);
4972
4973 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4974 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
4975 /*
4976 * BIOS could leave the Hw Turbo enabled, so need to explicitly
4977 * clear out the Control register just to avoid inconsitency
4978 * with debugfs interface, which will show Turbo as enabled
4979 * only and that is not expected by the User after adding the
4980 * WaGsvDisableTurbo. Apart from this there is no problem even
4981 * if the Turbo is left enabled in the Control register, as the
4982 * Up/Down interrupts would remain masked.
4983 */
4984 gen9_disable_rps(dev_priv);
4985 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4986 return;
4987 }
4988
4989 /* Program defaults and thresholds for RPS*/
4990 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4991 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4992
4993 /* 1 second timeout*/
4994 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4995 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4996
4997 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4998
4999 /* Leaning on the below call to gen6_set_rps to program/setup the
5000 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5001 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5002 dev_priv->rps.power = HIGH_POWER; /* force a reset */
5003 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5004
5005 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5006 }
5007
5008 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5009 {
5010 struct intel_engine_cs *engine;
5011 uint32_t rc6_mask = 0;
5012
5013 /* 1a: Software RC state - RC0 */
5014 I915_WRITE(GEN6_RC_STATE, 0);
5015
5016 /* 1b: Get forcewake during program sequence. Although the driver
5017 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5018 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5019
5020 /* 2a: Disable RC states. */
5021 I915_WRITE(GEN6_RC_CONTROL, 0);
5022
5023 /* 2b: Program RC6 thresholds.*/
5024
5025 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5026 if (IS_SKYLAKE(dev_priv))
5027 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5028 else
5029 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5030 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5031 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5032 for_each_engine(engine, dev_priv)
5033 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5034
5035 if (HAS_GUC_UCODE(dev_priv))
5036 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5037
5038 I915_WRITE(GEN6_RC_SLEEP, 0);
5039
5040 /* 2c: Program Coarse Power Gating Policies. */
5041 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5042 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5043
5044 /* 3a: Enable RC6 */
5045 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5046 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5047 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5048 /* WaRsUseTimeoutMode */
5049 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
5050 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5051 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5052 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5053 GEN7_RC_CTL_TO_MODE |
5054 rc6_mask);
5055 } else {
5056 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5057 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5058 GEN6_RC_CTL_EI_MODE(1) |
5059 rc6_mask);
5060 }
5061
5062 /*
5063 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5064 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5065 */
5066 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5067 I915_WRITE(GEN9_PG_ENABLE, 0);
5068 else
5069 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5070 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5071
5072 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5073 }
5074
5075 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5076 {
5077 struct intel_engine_cs *engine;
5078 uint32_t rc6_mask = 0;
5079
5080 /* 1a: Software RC state - RC0 */
5081 I915_WRITE(GEN6_RC_STATE, 0);
5082
5083 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5084 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5085 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5086
5087 /* 2a: Disable RC states. */
5088 I915_WRITE(GEN6_RC_CONTROL, 0);
5089
5090 /* Initialize rps frequencies */
5091 gen6_init_rps_frequencies(dev_priv);
5092
5093 /* 2b: Program RC6 thresholds.*/
5094 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5095 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5096 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5097 for_each_engine(engine, dev_priv)
5098 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5099 I915_WRITE(GEN6_RC_SLEEP, 0);
5100 if (IS_BROADWELL(dev_priv))
5101 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5102 else
5103 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5104
5105 /* 3: Enable RC6 */
5106 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5107 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5108 intel_print_rc6_info(dev_priv, rc6_mask);
5109 if (IS_BROADWELL(dev_priv))
5110 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5111 GEN7_RC_CTL_TO_MODE |
5112 rc6_mask);
5113 else
5114 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5115 GEN6_RC_CTL_EI_MODE(1) |
5116 rc6_mask);
5117
5118 /* 4 Program defaults and thresholds for RPS*/
5119 I915_WRITE(GEN6_RPNSWREQ,
5120 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5121 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5122 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5123 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5124 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5125
5126 /* Docs recommend 900MHz, and 300 MHz respectively */
5127 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5128 dev_priv->rps.max_freq_softlimit << 24 |
5129 dev_priv->rps.min_freq_softlimit << 16);
5130
5131 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5132 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5133 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5134 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5135
5136 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5137
5138 /* 5: Enable RPS */
5139 I915_WRITE(GEN6_RP_CONTROL,
5140 GEN6_RP_MEDIA_TURBO |
5141 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5142 GEN6_RP_MEDIA_IS_GFX |
5143 GEN6_RP_ENABLE |
5144 GEN6_RP_UP_BUSY_AVG |
5145 GEN6_RP_DOWN_IDLE_AVG);
5146
5147 /* 6: Ring frequency + overclocking (our driver does this later */
5148
5149 dev_priv->rps.power = HIGH_POWER; /* force a reset */
5150 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5151
5152 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5153 }
5154
5155 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5156 {
5157 struct intel_engine_cs *engine;
5158 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
5159 u32 gtfifodbg;
5160 int rc6_mode;
5161 int ret;
5162
5163 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5164
5165 /* Here begins a magic sequence of register writes to enable
5166 * auto-downclocking.
5167 *
5168 * Perhaps there might be some value in exposing these to
5169 * userspace...
5170 */
5171 I915_WRITE(GEN6_RC_STATE, 0);
5172
5173 /* Clear the DBG now so we don't confuse earlier errors */
5174 gtfifodbg = I915_READ(GTFIFODBG);
5175 if (gtfifodbg) {
5176 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5177 I915_WRITE(GTFIFODBG, gtfifodbg);
5178 }
5179
5180 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5181
5182 /* Initialize rps frequencies */
5183 gen6_init_rps_frequencies(dev_priv);
5184
5185 /* disable the counters and set deterministic thresholds */
5186 I915_WRITE(GEN6_RC_CONTROL, 0);
5187
5188 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5189 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5190 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5191 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5192 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5193
5194 for_each_engine(engine, dev_priv)
5195 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5196
5197 I915_WRITE(GEN6_RC_SLEEP, 0);
5198 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5199 if (IS_IVYBRIDGE(dev_priv))
5200 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5201 else
5202 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5203 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5204 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5205
5206 /* Check if we are enabling RC6 */
5207 rc6_mode = intel_enable_rc6();
5208 if (rc6_mode & INTEL_RC6_ENABLE)
5209 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5210
5211 /* We don't use those on Haswell */
5212 if (!IS_HASWELL(dev_priv)) {
5213 if (rc6_mode & INTEL_RC6p_ENABLE)
5214 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5215
5216 if (rc6_mode & INTEL_RC6pp_ENABLE)
5217 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5218 }
5219
5220 intel_print_rc6_info(dev_priv, rc6_mask);
5221
5222 I915_WRITE(GEN6_RC_CONTROL,
5223 rc6_mask |
5224 GEN6_RC_CTL_EI_MODE(1) |
5225 GEN6_RC_CTL_HW_ENABLE);
5226
5227 /* Power down if completely idle for over 50ms */
5228 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5229 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5230
5231 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5232 if (ret)
5233 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5234
5235 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5236 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5237 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5238 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5239 (pcu_mbox & 0xff) * 50);
5240 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5241 }
5242
5243 dev_priv->rps.power = HIGH_POWER; /* force a reset */
5244 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5245
5246 rc6vids = 0;
5247 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5248 if (IS_GEN6(dev_priv) && ret) {
5249 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5250 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5251 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5252 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5253 rc6vids &= 0xffff00;
5254 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5255 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5256 if (ret)
5257 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5258 }
5259
5260 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5261 }
5262
5263 static void __gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5264 {
5265 int min_freq = 15;
5266 unsigned int gpu_freq;
5267 unsigned int max_ia_freq, min_ring_freq;
5268 unsigned int max_gpu_freq, min_gpu_freq;
5269 int scaling_factor = 180;
5270 struct cpufreq_policy *policy;
5271
5272 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5273
5274 policy = cpufreq_cpu_get(0);
5275 if (policy) {
5276 max_ia_freq = policy->cpuinfo.max_freq;
5277 cpufreq_cpu_put(policy);
5278 } else {
5279 /*
5280 * Default to measured freq if none found, PCU will ensure we
5281 * don't go over
5282 */
5283 max_ia_freq = tsc_khz;
5284 }
5285
5286 /* Convert from kHz to MHz */
5287 max_ia_freq /= 1000;
5288
5289 min_ring_freq = I915_READ(DCLK) & 0xf;
5290 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5291 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5292
5293 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5294 /* Convert GT frequency to 50 HZ units */
5295 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5296 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5297 } else {
5298 min_gpu_freq = dev_priv->rps.min_freq;
5299 max_gpu_freq = dev_priv->rps.max_freq;
5300 }
5301
5302 /*
5303 * For each potential GPU frequency, load a ring frequency we'd like
5304 * to use for memory access. We do this by specifying the IA frequency
5305 * the PCU should use as a reference to determine the ring frequency.
5306 */
5307 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5308 int diff = max_gpu_freq - gpu_freq;
5309 unsigned int ia_freq = 0, ring_freq = 0;
5310
5311 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5312 /*
5313 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5314 * No floor required for ring frequency on SKL.
5315 */
5316 ring_freq = gpu_freq;
5317 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5318 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5319 ring_freq = max(min_ring_freq, gpu_freq);
5320 } else if (IS_HASWELL(dev_priv)) {
5321 ring_freq = mult_frac(gpu_freq, 5, 4);
5322 ring_freq = max(min_ring_freq, ring_freq);
5323 /* leave ia_freq as the default, chosen by cpufreq */
5324 } else {
5325 /* On older processors, there is no separate ring
5326 * clock domain, so in order to boost the bandwidth
5327 * of the ring, we need to upclock the CPU (ia_freq).
5328 *
5329 * For GPU frequencies less than 750MHz,
5330 * just use the lowest ring freq.
5331 */
5332 if (gpu_freq < min_freq)
5333 ia_freq = 800;
5334 else
5335 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5336 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5337 }
5338
5339 sandybridge_pcode_write(dev_priv,
5340 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5341 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5342 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5343 gpu_freq);
5344 }
5345 }
5346
5347 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5348 {
5349 if (!HAS_CORE_RING_FREQ(dev_priv))
5350 return;
5351
5352 mutex_lock(&dev_priv->rps.hw_lock);
5353 __gen6_update_ring_freq(dev_priv);
5354 mutex_unlock(&dev_priv->rps.hw_lock);
5355 }
5356
5357 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5358 {
5359 u32 val, rp0;
5360
5361 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5362
5363 switch (INTEL_INFO(dev_priv)->eu_total) {
5364 case 8:
5365 /* (2 * 4) config */
5366 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5367 break;
5368 case 12:
5369 /* (2 * 6) config */
5370 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5371 break;
5372 case 16:
5373 /* (2 * 8) config */
5374 default:
5375 /* Setting (2 * 8) Min RP0 for any other combination */
5376 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5377 break;
5378 }
5379
5380 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5381
5382 return rp0;
5383 }
5384
5385 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5386 {
5387 u32 val, rpe;
5388
5389 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5390 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5391
5392 return rpe;
5393 }
5394
5395 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5396 {
5397 u32 val, rp1;
5398
5399 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5400 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5401
5402 return rp1;
5403 }
5404
5405 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5406 {
5407 u32 val, rp1;
5408
5409 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5410
5411 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5412
5413 return rp1;
5414 }
5415
5416 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5417 {
5418 u32 val, rp0;
5419
5420 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5421
5422 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5423 /* Clamp to max */
5424 rp0 = min_t(u32, rp0, 0xea);
5425
5426 return rp0;
5427 }
5428
5429 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5430 {
5431 u32 val, rpe;
5432
5433 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5434 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5435 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5436 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5437
5438 return rpe;
5439 }
5440
5441 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5442 {
5443 u32 val;
5444
5445 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5446 /*
5447 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5448 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5449 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5450 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5451 * to make sure it matches what Punit accepts.
5452 */
5453 return max_t(u32, val, 0xc0);
5454 }
5455
5456 /* Check that the pctx buffer wasn't move under us. */
5457 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5458 {
5459 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5460
5461 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5462 dev_priv->vlv_pctx->stolen->start);
5463 }
5464
5465
5466 /* Check that the pcbr address is not empty. */
5467 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5468 {
5469 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5470
5471 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5472 }
5473
5474 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5475 {
5476 struct i915_ggtt *ggtt = &dev_priv->ggtt;
5477 unsigned long pctx_paddr, paddr;
5478 u32 pcbr;
5479 int pctx_size = 32*1024;
5480
5481 pcbr = I915_READ(VLV_PCBR);
5482 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5483 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5484 paddr = (dev_priv->mm.stolen_base +
5485 (ggtt->stolen_size - pctx_size));
5486
5487 pctx_paddr = (paddr & (~4095));
5488 I915_WRITE(VLV_PCBR, pctx_paddr);
5489 }
5490
5491 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5492 }
5493
5494 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5495 {
5496 struct drm_i915_gem_object *pctx;
5497 unsigned long pctx_paddr;
5498 u32 pcbr;
5499 int pctx_size = 24*1024;
5500
5501 mutex_lock(&dev_priv->dev->struct_mutex);
5502
5503 pcbr = I915_READ(VLV_PCBR);
5504 if (pcbr) {
5505 /* BIOS set it up already, grab the pre-alloc'd space */
5506 int pcbr_offset;
5507
5508 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5509 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5510 pcbr_offset,
5511 I915_GTT_OFFSET_NONE,
5512 pctx_size);
5513 goto out;
5514 }
5515
5516 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5517
5518 /*
5519 * From the Gunit register HAS:
5520 * The Gfx driver is expected to program this register and ensure
5521 * proper allocation within Gfx stolen memory. For example, this
5522 * register should be programmed such than the PCBR range does not
5523 * overlap with other ranges, such as the frame buffer, protected
5524 * memory, or any other relevant ranges.
5525 */
5526 pctx = i915_gem_object_create_stolen(dev_priv->dev, pctx_size);
5527 if (!pctx) {
5528 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5529 goto out;
5530 }
5531
5532 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5533 I915_WRITE(VLV_PCBR, pctx_paddr);
5534
5535 out:
5536 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5537 dev_priv->vlv_pctx = pctx;
5538 mutex_unlock(&dev_priv->dev->struct_mutex);
5539 }
5540
5541 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5542 {
5543 if (WARN_ON(!dev_priv->vlv_pctx))
5544 return;
5545
5546 drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
5547 dev_priv->vlv_pctx = NULL;
5548 }
5549
5550 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5551 {
5552 dev_priv->rps.gpll_ref_freq =
5553 vlv_get_cck_clock(dev_priv, "GPLL ref",
5554 CCK_GPLL_CLOCK_CONTROL,
5555 dev_priv->czclk_freq);
5556
5557 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5558 dev_priv->rps.gpll_ref_freq);
5559 }
5560
5561 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5562 {
5563 u32 val;
5564
5565 valleyview_setup_pctx(dev_priv);
5566
5567 vlv_init_gpll_ref_freq(dev_priv);
5568
5569 mutex_lock(&dev_priv->rps.hw_lock);
5570
5571 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5572 switch ((val >> 6) & 3) {
5573 case 0:
5574 case 1:
5575 dev_priv->mem_freq = 800;
5576 break;
5577 case 2:
5578 dev_priv->mem_freq = 1066;
5579 break;
5580 case 3:
5581 dev_priv->mem_freq = 1333;
5582 break;
5583 }
5584 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5585
5586 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5587 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5588 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5589 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5590 dev_priv->rps.max_freq);
5591
5592 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5593 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5594 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5595 dev_priv->rps.efficient_freq);
5596
5597 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5598 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5599 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5600 dev_priv->rps.rp1_freq);
5601
5602 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5603 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5604 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5605 dev_priv->rps.min_freq);
5606
5607 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5608
5609 /* Preserve min/max settings in case of re-init */
5610 if (dev_priv->rps.max_freq_softlimit == 0)
5611 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5612
5613 if (dev_priv->rps.min_freq_softlimit == 0)
5614 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5615
5616 mutex_unlock(&dev_priv->rps.hw_lock);
5617 }
5618
5619 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5620 {
5621 u32 val;
5622
5623 cherryview_setup_pctx(dev_priv);
5624
5625 vlv_init_gpll_ref_freq(dev_priv);
5626
5627 mutex_lock(&dev_priv->rps.hw_lock);
5628
5629 mutex_lock(&dev_priv->sb_lock);
5630 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5631 mutex_unlock(&dev_priv->sb_lock);
5632
5633 switch ((val >> 2) & 0x7) {
5634 case 3:
5635 dev_priv->mem_freq = 2000;
5636 break;
5637 default:
5638 dev_priv->mem_freq = 1600;
5639 break;
5640 }
5641 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5642
5643 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5644 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5645 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5646 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5647 dev_priv->rps.max_freq);
5648
5649 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5650 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5651 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5652 dev_priv->rps.efficient_freq);
5653
5654 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5655 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5656 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5657 dev_priv->rps.rp1_freq);
5658
5659 /* PUnit validated range is only [RPe, RP0] */
5660 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5661 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5662 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5663 dev_priv->rps.min_freq);
5664
5665 WARN_ONCE((dev_priv->rps.max_freq |
5666 dev_priv->rps.efficient_freq |
5667 dev_priv->rps.rp1_freq |
5668 dev_priv->rps.min_freq) & 1,
5669 "Odd GPU freq values\n");
5670
5671 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5672
5673 /* Preserve min/max settings in case of re-init */
5674 if (dev_priv->rps.max_freq_softlimit == 0)
5675 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5676
5677 if (dev_priv->rps.min_freq_softlimit == 0)
5678 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5679
5680 mutex_unlock(&dev_priv->rps.hw_lock);
5681 }
5682
5683 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5684 {
5685 valleyview_cleanup_pctx(dev_priv);
5686 }
5687
5688 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5689 {
5690 struct intel_engine_cs *engine;
5691 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5692
5693 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5694
5695 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5696 GT_FIFO_FREE_ENTRIES_CHV);
5697 if (gtfifodbg) {
5698 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5699 gtfifodbg);
5700 I915_WRITE(GTFIFODBG, gtfifodbg);
5701 }
5702
5703 cherryview_check_pctx(dev_priv);
5704
5705 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5706 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5707 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5708
5709 /* Disable RC states. */
5710 I915_WRITE(GEN6_RC_CONTROL, 0);
5711
5712 /* 2a: Program RC6 thresholds.*/
5713 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5714 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5715 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5716
5717 for_each_engine(engine, dev_priv)
5718 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5719 I915_WRITE(GEN6_RC_SLEEP, 0);
5720
5721 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5722 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5723
5724 /* allows RC6 residency counter to work */
5725 I915_WRITE(VLV_COUNTER_CONTROL,
5726 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5727 VLV_MEDIA_RC6_COUNT_EN |
5728 VLV_RENDER_RC6_COUNT_EN));
5729
5730 /* For now we assume BIOS is allocating and populating the PCBR */
5731 pcbr = I915_READ(VLV_PCBR);
5732
5733 /* 3: Enable RC6 */
5734 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
5735 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5736 rc6_mode = GEN7_RC_CTL_TO_MODE;
5737
5738 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5739
5740 /* 4 Program defaults and thresholds for RPS*/
5741 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5742 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5743 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5744 I915_WRITE(GEN6_RP_UP_EI, 66000);
5745 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5746
5747 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5748
5749 /* 5: Enable RPS */
5750 I915_WRITE(GEN6_RP_CONTROL,
5751 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5752 GEN6_RP_MEDIA_IS_GFX |
5753 GEN6_RP_ENABLE |
5754 GEN6_RP_UP_BUSY_AVG |
5755 GEN6_RP_DOWN_IDLE_AVG);
5756
5757 /* Setting Fixed Bias */
5758 val = VLV_OVERRIDE_EN |
5759 VLV_SOC_TDP_EN |
5760 CHV_BIAS_CPU_50_SOC_50;
5761 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5762
5763 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5764
5765 /* RPS code assumes GPLL is used */
5766 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5767
5768 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5769 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5770
5771 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5772 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5773 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5774 dev_priv->rps.cur_freq);
5775
5776 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5777 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5778 dev_priv->rps.idle_freq);
5779
5780 valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
5781
5782 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5783 }
5784
5785 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
5786 {
5787 struct intel_engine_cs *engine;
5788 u32 gtfifodbg, val, rc6_mode = 0;
5789
5790 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5791
5792 valleyview_check_pctx(dev_priv);
5793
5794 gtfifodbg = I915_READ(GTFIFODBG);
5795 if (gtfifodbg) {
5796 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5797 gtfifodbg);
5798 I915_WRITE(GTFIFODBG, gtfifodbg);
5799 }
5800
5801 /* If VLV, Forcewake all wells, else re-direct to regular path */
5802 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5803
5804 /* Disable RC states. */
5805 I915_WRITE(GEN6_RC_CONTROL, 0);
5806
5807 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5808 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5809 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5810 I915_WRITE(GEN6_RP_UP_EI, 66000);
5811 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5812
5813 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5814
5815 I915_WRITE(GEN6_RP_CONTROL,
5816 GEN6_RP_MEDIA_TURBO |
5817 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5818 GEN6_RP_MEDIA_IS_GFX |
5819 GEN6_RP_ENABLE |
5820 GEN6_RP_UP_BUSY_AVG |
5821 GEN6_RP_DOWN_IDLE_CONT);
5822
5823 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5824 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5825 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5826
5827 for_each_engine(engine, dev_priv)
5828 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5829
5830 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5831
5832 /* allows RC6 residency counter to work */
5833 I915_WRITE(VLV_COUNTER_CONTROL,
5834 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5835 VLV_RENDER_RC0_COUNT_EN |
5836 VLV_MEDIA_RC6_COUNT_EN |
5837 VLV_RENDER_RC6_COUNT_EN));
5838
5839 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5840 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5841
5842 intel_print_rc6_info(dev_priv, rc6_mode);
5843
5844 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5845
5846 /* Setting Fixed Bias */
5847 val = VLV_OVERRIDE_EN |
5848 VLV_SOC_TDP_EN |
5849 VLV_BIAS_CPU_125_SOC_875;
5850 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5851
5852 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5853
5854 /* RPS code assumes GPLL is used */
5855 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5856
5857 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5858 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5859
5860 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5861 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5862 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5863 dev_priv->rps.cur_freq);
5864
5865 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5866 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5867 dev_priv->rps.idle_freq);
5868
5869 valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
5870
5871 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5872 }
5873
5874 static unsigned long intel_pxfreq(u32 vidfreq)
5875 {
5876 unsigned long freq;
5877 int div = (vidfreq & 0x3f0000) >> 16;
5878 int post = (vidfreq & 0x3000) >> 12;
5879 int pre = (vidfreq & 0x7);
5880
5881 if (!pre)
5882 return 0;
5883
5884 freq = ((div * 133333) / ((1<<post) * pre));
5885
5886 return freq;
5887 }
5888
5889 static const struct cparams {
5890 u16 i;
5891 u16 t;
5892 u16 m;
5893 u16 c;
5894 } cparams[] = {
5895 { 1, 1333, 301, 28664 },
5896 { 1, 1066, 294, 24460 },
5897 { 1, 800, 294, 25192 },
5898 { 0, 1333, 276, 27605 },
5899 { 0, 1066, 276, 27605 },
5900 { 0, 800, 231, 23784 },
5901 };
5902
5903 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5904 {
5905 u64 total_count, diff, ret;
5906 u32 count1, count2, count3, m = 0, c = 0;
5907 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5908 int i;
5909
5910 assert_spin_locked(&mchdev_lock);
5911
5912 diff1 = now - dev_priv->ips.last_time1;
5913
5914 /* Prevent division-by-zero if we are asking too fast.
5915 * Also, we don't get interesting results if we are polling
5916 * faster than once in 10ms, so just return the saved value
5917 * in such cases.
5918 */
5919 if (diff1 <= 10)
5920 return dev_priv->ips.chipset_power;
5921
5922 count1 = I915_READ(DMIEC);
5923 count2 = I915_READ(DDREC);
5924 count3 = I915_READ(CSIEC);
5925
5926 total_count = count1 + count2 + count3;
5927
5928 /* FIXME: handle per-counter overflow */
5929 if (total_count < dev_priv->ips.last_count1) {
5930 diff = ~0UL - dev_priv->ips.last_count1;
5931 diff += total_count;
5932 } else {
5933 diff = total_count - dev_priv->ips.last_count1;
5934 }
5935
5936 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5937 if (cparams[i].i == dev_priv->ips.c_m &&
5938 cparams[i].t == dev_priv->ips.r_t) {
5939 m = cparams[i].m;
5940 c = cparams[i].c;
5941 break;
5942 }
5943 }
5944
5945 diff = div_u64(diff, diff1);
5946 ret = ((m * diff) + c);
5947 ret = div_u64(ret, 10);
5948
5949 dev_priv->ips.last_count1 = total_count;
5950 dev_priv->ips.last_time1 = now;
5951
5952 dev_priv->ips.chipset_power = ret;
5953
5954 return ret;
5955 }
5956
5957 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5958 {
5959 unsigned long val;
5960
5961 if (INTEL_INFO(dev_priv)->gen != 5)
5962 return 0;
5963
5964 spin_lock_irq(&mchdev_lock);
5965
5966 val = __i915_chipset_val(dev_priv);
5967
5968 spin_unlock_irq(&mchdev_lock);
5969
5970 return val;
5971 }
5972
5973 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5974 {
5975 unsigned long m, x, b;
5976 u32 tsfs;
5977
5978 tsfs = I915_READ(TSFS);
5979
5980 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5981 x = I915_READ8(TR1);
5982
5983 b = tsfs & TSFS_INTR_MASK;
5984
5985 return ((m * x) / 127) - b;
5986 }
5987
5988 static int _pxvid_to_vd(u8 pxvid)
5989 {
5990 if (pxvid == 0)
5991 return 0;
5992
5993 if (pxvid >= 8 && pxvid < 31)
5994 pxvid = 31;
5995
5996 return (pxvid + 2) * 125;
5997 }
5998
5999 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6000 {
6001 const int vd = _pxvid_to_vd(pxvid);
6002 const int vm = vd - 1125;
6003
6004 if (INTEL_INFO(dev_priv)->is_mobile)
6005 return vm > 0 ? vm : 0;
6006
6007 return vd;
6008 }
6009
6010 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6011 {
6012 u64 now, diff, diffms;
6013 u32 count;
6014
6015 assert_spin_locked(&mchdev_lock);
6016
6017 now = ktime_get_raw_ns();
6018 diffms = now - dev_priv->ips.last_time2;
6019 do_div(diffms, NSEC_PER_MSEC);
6020
6021 /* Don't divide by 0 */
6022 if (!diffms)
6023 return;
6024
6025 count = I915_READ(GFXEC);
6026
6027 if (count < dev_priv->ips.last_count2) {
6028 diff = ~0UL - dev_priv->ips.last_count2;
6029 diff += count;
6030 } else {
6031 diff = count - dev_priv->ips.last_count2;
6032 }
6033
6034 dev_priv->ips.last_count2 = count;
6035 dev_priv->ips.last_time2 = now;
6036
6037 /* More magic constants... */
6038 diff = diff * 1181;
6039 diff = div_u64(diff, diffms * 10);
6040 dev_priv->ips.gfx_power = diff;
6041 }
6042
6043 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6044 {
6045 if (INTEL_INFO(dev_priv)->gen != 5)
6046 return;
6047
6048 spin_lock_irq(&mchdev_lock);
6049
6050 __i915_update_gfx_val(dev_priv);
6051
6052 spin_unlock_irq(&mchdev_lock);
6053 }
6054
6055 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6056 {
6057 unsigned long t, corr, state1, corr2, state2;
6058 u32 pxvid, ext_v;
6059
6060 assert_spin_locked(&mchdev_lock);
6061
6062 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6063 pxvid = (pxvid >> 24) & 0x7f;
6064 ext_v = pvid_to_extvid(dev_priv, pxvid);
6065
6066 state1 = ext_v;
6067
6068 t = i915_mch_val(dev_priv);
6069
6070 /* Revel in the empirically derived constants */
6071
6072 /* Correction factor in 1/100000 units */
6073 if (t > 80)
6074 corr = ((t * 2349) + 135940);
6075 else if (t >= 50)
6076 corr = ((t * 964) + 29317);
6077 else /* < 50 */
6078 corr = ((t * 301) + 1004);
6079
6080 corr = corr * ((150142 * state1) / 10000 - 78642);
6081 corr /= 100000;
6082 corr2 = (corr * dev_priv->ips.corr);
6083
6084 state2 = (corr2 * state1) / 10000;
6085 state2 /= 100; /* convert to mW */
6086
6087 __i915_update_gfx_val(dev_priv);
6088
6089 return dev_priv->ips.gfx_power + state2;
6090 }
6091
6092 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6093 {
6094 unsigned long val;
6095
6096 if (INTEL_INFO(dev_priv)->gen != 5)
6097 return 0;
6098
6099 spin_lock_irq(&mchdev_lock);
6100
6101 val = __i915_gfx_val(dev_priv);
6102
6103 spin_unlock_irq(&mchdev_lock);
6104
6105 return val;
6106 }
6107
6108 /**
6109 * i915_read_mch_val - return value for IPS use
6110 *
6111 * Calculate and return a value for the IPS driver to use when deciding whether
6112 * we have thermal and power headroom to increase CPU or GPU power budget.
6113 */
6114 unsigned long i915_read_mch_val(void)
6115 {
6116 struct drm_i915_private *dev_priv;
6117 unsigned long chipset_val, graphics_val, ret = 0;
6118
6119 spin_lock_irq(&mchdev_lock);
6120 if (!i915_mch_dev)
6121 goto out_unlock;
6122 dev_priv = i915_mch_dev;
6123
6124 chipset_val = __i915_chipset_val(dev_priv);
6125 graphics_val = __i915_gfx_val(dev_priv);
6126
6127 ret = chipset_val + graphics_val;
6128
6129 out_unlock:
6130 spin_unlock_irq(&mchdev_lock);
6131
6132 return ret;
6133 }
6134 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6135
6136 /**
6137 * i915_gpu_raise - raise GPU frequency limit
6138 *
6139 * Raise the limit; IPS indicates we have thermal headroom.
6140 */
6141 bool i915_gpu_raise(void)
6142 {
6143 struct drm_i915_private *dev_priv;
6144 bool ret = true;
6145
6146 spin_lock_irq(&mchdev_lock);
6147 if (!i915_mch_dev) {
6148 ret = false;
6149 goto out_unlock;
6150 }
6151 dev_priv = i915_mch_dev;
6152
6153 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6154 dev_priv->ips.max_delay--;
6155
6156 out_unlock:
6157 spin_unlock_irq(&mchdev_lock);
6158
6159 return ret;
6160 }
6161 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6162
6163 /**
6164 * i915_gpu_lower - lower GPU frequency limit
6165 *
6166 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6167 * frequency maximum.
6168 */
6169 bool i915_gpu_lower(void)
6170 {
6171 struct drm_i915_private *dev_priv;
6172 bool ret = true;
6173
6174 spin_lock_irq(&mchdev_lock);
6175 if (!i915_mch_dev) {
6176 ret = false;
6177 goto out_unlock;
6178 }
6179 dev_priv = i915_mch_dev;
6180
6181 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6182 dev_priv->ips.max_delay++;
6183
6184 out_unlock:
6185 spin_unlock_irq(&mchdev_lock);
6186
6187 return ret;
6188 }
6189 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6190
6191 /**
6192 * i915_gpu_busy - indicate GPU business to IPS
6193 *
6194 * Tell the IPS driver whether or not the GPU is busy.
6195 */
6196 bool i915_gpu_busy(void)
6197 {
6198 struct drm_i915_private *dev_priv;
6199 struct intel_engine_cs *engine;
6200 bool ret = false;
6201
6202 spin_lock_irq(&mchdev_lock);
6203 if (!i915_mch_dev)
6204 goto out_unlock;
6205 dev_priv = i915_mch_dev;
6206
6207 for_each_engine(engine, dev_priv)
6208 ret |= !list_empty(&engine->request_list);
6209
6210 out_unlock:
6211 spin_unlock_irq(&mchdev_lock);
6212
6213 return ret;
6214 }
6215 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6216
6217 /**
6218 * i915_gpu_turbo_disable - disable graphics turbo
6219 *
6220 * Disable graphics turbo by resetting the max frequency and setting the
6221 * current frequency to the default.
6222 */
6223 bool i915_gpu_turbo_disable(void)
6224 {
6225 struct drm_i915_private *dev_priv;
6226 bool ret = true;
6227
6228 spin_lock_irq(&mchdev_lock);
6229 if (!i915_mch_dev) {
6230 ret = false;
6231 goto out_unlock;
6232 }
6233 dev_priv = i915_mch_dev;
6234
6235 dev_priv->ips.max_delay = dev_priv->ips.fstart;
6236
6237 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6238 ret = false;
6239
6240 out_unlock:
6241 spin_unlock_irq(&mchdev_lock);
6242
6243 return ret;
6244 }
6245 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6246
6247 /**
6248 * Tells the intel_ips driver that the i915 driver is now loaded, if
6249 * IPS got loaded first.
6250 *
6251 * This awkward dance is so that neither module has to depend on the
6252 * other in order for IPS to do the appropriate communication of
6253 * GPU turbo limits to i915.
6254 */
6255 static void
6256 ips_ping_for_i915_load(void)
6257 {
6258 void (*link)(void);
6259
6260 link = symbol_get(ips_link_to_i915_driver);
6261 if (link) {
6262 link();
6263 symbol_put(ips_link_to_i915_driver);
6264 }
6265 }
6266
6267 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6268 {
6269 /* We only register the i915 ips part with intel-ips once everything is
6270 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6271 spin_lock_irq(&mchdev_lock);
6272 i915_mch_dev = dev_priv;
6273 spin_unlock_irq(&mchdev_lock);
6274
6275 ips_ping_for_i915_load();
6276 }
6277
6278 void intel_gpu_ips_teardown(void)
6279 {
6280 spin_lock_irq(&mchdev_lock);
6281 i915_mch_dev = NULL;
6282 spin_unlock_irq(&mchdev_lock);
6283 }
6284
6285 static void intel_init_emon(struct drm_i915_private *dev_priv)
6286 {
6287 u32 lcfuse;
6288 u8 pxw[16];
6289 int i;
6290
6291 /* Disable to program */
6292 I915_WRITE(ECR, 0);
6293 POSTING_READ(ECR);
6294
6295 /* Program energy weights for various events */
6296 I915_WRITE(SDEW, 0x15040d00);
6297 I915_WRITE(CSIEW0, 0x007f0000);
6298 I915_WRITE(CSIEW1, 0x1e220004);
6299 I915_WRITE(CSIEW2, 0x04000004);
6300
6301 for (i = 0; i < 5; i++)
6302 I915_WRITE(PEW(i), 0);
6303 for (i = 0; i < 3; i++)
6304 I915_WRITE(DEW(i), 0);
6305
6306 /* Program P-state weights to account for frequency power adjustment */
6307 for (i = 0; i < 16; i++) {
6308 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6309 unsigned long freq = intel_pxfreq(pxvidfreq);
6310 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6311 PXVFREQ_PX_SHIFT;
6312 unsigned long val;
6313
6314 val = vid * vid;
6315 val *= (freq / 1000);
6316 val *= 255;
6317 val /= (127*127*900);
6318 if (val > 0xff)
6319 DRM_ERROR("bad pxval: %ld\n", val);
6320 pxw[i] = val;
6321 }
6322 /* Render standby states get 0 weight */
6323 pxw[14] = 0;
6324 pxw[15] = 0;
6325
6326 for (i = 0; i < 4; i++) {
6327 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6328 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6329 I915_WRITE(PXW(i), val);
6330 }
6331
6332 /* Adjust magic regs to magic values (more experimental results) */
6333 I915_WRITE(OGW0, 0);
6334 I915_WRITE(OGW1, 0);
6335 I915_WRITE(EG0, 0x00007f00);
6336 I915_WRITE(EG1, 0x0000000e);
6337 I915_WRITE(EG2, 0x000e0000);
6338 I915_WRITE(EG3, 0x68000300);
6339 I915_WRITE(EG4, 0x42000000);
6340 I915_WRITE(EG5, 0x00140031);
6341 I915_WRITE(EG6, 0);
6342 I915_WRITE(EG7, 0);
6343
6344 for (i = 0; i < 8; i++)
6345 I915_WRITE(PXWL(i), 0);
6346
6347 /* Enable PMON + select events */
6348 I915_WRITE(ECR, 0x80000019);
6349
6350 lcfuse = I915_READ(LCFUSE02);
6351
6352 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6353 }
6354
6355 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6356 {
6357 /*
6358 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6359 * requirement.
6360 */
6361 if (!i915.enable_rc6) {
6362 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6363 intel_runtime_pm_get(dev_priv);
6364 }
6365
6366 if (IS_CHERRYVIEW(dev_priv))
6367 cherryview_init_gt_powersave(dev_priv);
6368 else if (IS_VALLEYVIEW(dev_priv))
6369 valleyview_init_gt_powersave(dev_priv);
6370 }
6371
6372 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6373 {
6374 if (IS_CHERRYVIEW(dev_priv))
6375 return;
6376 else if (IS_VALLEYVIEW(dev_priv))
6377 valleyview_cleanup_gt_powersave(dev_priv);
6378
6379 if (!i915.enable_rc6)
6380 intel_runtime_pm_put(dev_priv);
6381 }
6382
6383 static void gen6_suspend_rps(struct drm_i915_private *dev_priv)
6384 {
6385 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6386
6387 gen6_disable_rps_interrupts(dev_priv);
6388 }
6389
6390 /**
6391 * intel_suspend_gt_powersave - suspend PM work and helper threads
6392 * @dev_priv: i915 device
6393 *
6394 * We don't want to disable RC6 or other features here, we just want
6395 * to make sure any work we've queued has finished and won't bother
6396 * us while we're suspended.
6397 */
6398 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6399 {
6400 if (INTEL_GEN(dev_priv) < 6)
6401 return;
6402
6403 gen6_suspend_rps(dev_priv);
6404
6405 /* Force GPU to min freq during suspend */
6406 gen6_rps_idle(dev_priv);
6407 }
6408
6409 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6410 {
6411 if (IS_IRONLAKE_M(dev_priv)) {
6412 ironlake_disable_drps(dev_priv);
6413 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6414 intel_suspend_gt_powersave(dev_priv);
6415
6416 mutex_lock(&dev_priv->rps.hw_lock);
6417 if (INTEL_INFO(dev_priv)->gen >= 9) {
6418 gen9_disable_rc6(dev_priv);
6419 gen9_disable_rps(dev_priv);
6420 } else if (IS_CHERRYVIEW(dev_priv))
6421 cherryview_disable_rps(dev_priv);
6422 else if (IS_VALLEYVIEW(dev_priv))
6423 valleyview_disable_rps(dev_priv);
6424 else
6425 gen6_disable_rps(dev_priv);
6426
6427 dev_priv->rps.enabled = false;
6428 mutex_unlock(&dev_priv->rps.hw_lock);
6429 }
6430 }
6431
6432 static void intel_gen6_powersave_work(struct work_struct *work)
6433 {
6434 struct drm_i915_private *dev_priv =
6435 container_of(work, struct drm_i915_private,
6436 rps.delayed_resume_work.work);
6437
6438 mutex_lock(&dev_priv->rps.hw_lock);
6439
6440 gen6_reset_rps_interrupts(dev_priv);
6441
6442 if (IS_CHERRYVIEW(dev_priv)) {
6443 cherryview_enable_rps(dev_priv);
6444 } else if (IS_VALLEYVIEW(dev_priv)) {
6445 valleyview_enable_rps(dev_priv);
6446 } else if (INTEL_INFO(dev_priv)->gen >= 9) {
6447 gen9_enable_rc6(dev_priv);
6448 gen9_enable_rps(dev_priv);
6449 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6450 __gen6_update_ring_freq(dev_priv);
6451 } else if (IS_BROADWELL(dev_priv)) {
6452 gen8_enable_rps(dev_priv);
6453 __gen6_update_ring_freq(dev_priv);
6454 } else {
6455 gen6_enable_rps(dev_priv);
6456 __gen6_update_ring_freq(dev_priv);
6457 }
6458
6459 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6460 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6461
6462 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6463 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6464
6465 dev_priv->rps.enabled = true;
6466
6467 gen6_enable_rps_interrupts(dev_priv);
6468
6469 mutex_unlock(&dev_priv->rps.hw_lock);
6470
6471 intel_runtime_pm_put(dev_priv);
6472 }
6473
6474 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6475 {
6476 /* Powersaving is controlled by the host when inside a VM */
6477 if (intel_vgpu_active(dev_priv))
6478 return;
6479
6480 if (IS_IRONLAKE_M(dev_priv)) {
6481 ironlake_enable_drps(dev_priv);
6482 mutex_lock(&dev_priv->dev->struct_mutex);
6483 intel_init_emon(dev_priv);
6484 mutex_unlock(&dev_priv->dev->struct_mutex);
6485 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6486 /*
6487 * PCU communication is slow and this doesn't need to be
6488 * done at any specific time, so do this out of our fast path
6489 * to make resume and init faster.
6490 *
6491 * We depend on the HW RC6 power context save/restore
6492 * mechanism when entering D3 through runtime PM suspend. So
6493 * disable RPM until RPS/RC6 is properly setup. We can only
6494 * get here via the driver load/system resume/runtime resume
6495 * paths, so the _noresume version is enough (and in case of
6496 * runtime resume it's necessary).
6497 */
6498 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6499 round_jiffies_up_relative(HZ)))
6500 intel_runtime_pm_get_noresume(dev_priv);
6501 }
6502 }
6503
6504 void intel_reset_gt_powersave(struct drm_i915_private *dev_priv)
6505 {
6506 if (INTEL_INFO(dev_priv)->gen < 6)
6507 return;
6508
6509 gen6_suspend_rps(dev_priv);
6510 dev_priv->rps.enabled = false;
6511 }
6512
6513 static void ibx_init_clock_gating(struct drm_device *dev)
6514 {
6515 struct drm_i915_private *dev_priv = dev->dev_private;
6516
6517 /*
6518 * On Ibex Peak and Cougar Point, we need to disable clock
6519 * gating for the panel power sequencer or it will fail to
6520 * start up when no ports are active.
6521 */
6522 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6523 }
6524
6525 static void g4x_disable_trickle_feed(struct drm_device *dev)
6526 {
6527 struct drm_i915_private *dev_priv = dev->dev_private;
6528 enum pipe pipe;
6529
6530 for_each_pipe(dev_priv, pipe) {
6531 I915_WRITE(DSPCNTR(pipe),
6532 I915_READ(DSPCNTR(pipe)) |
6533 DISPPLANE_TRICKLE_FEED_DISABLE);
6534
6535 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6536 POSTING_READ(DSPSURF(pipe));
6537 }
6538 }
6539
6540 static void ilk_init_lp_watermarks(struct drm_device *dev)
6541 {
6542 struct drm_i915_private *dev_priv = dev->dev_private;
6543
6544 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6545 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6546 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6547
6548 /*
6549 * Don't touch WM1S_LP_EN here.
6550 * Doing so could cause underruns.
6551 */
6552 }
6553
6554 static void ironlake_init_clock_gating(struct drm_device *dev)
6555 {
6556 struct drm_i915_private *dev_priv = dev->dev_private;
6557 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6558
6559 /*
6560 * Required for FBC
6561 * WaFbcDisableDpfcClockGating:ilk
6562 */
6563 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6564 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6565 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6566
6567 I915_WRITE(PCH_3DCGDIS0,
6568 MARIUNIT_CLOCK_GATE_DISABLE |
6569 SVSMUNIT_CLOCK_GATE_DISABLE);
6570 I915_WRITE(PCH_3DCGDIS1,
6571 VFMUNIT_CLOCK_GATE_DISABLE);
6572
6573 /*
6574 * According to the spec the following bits should be set in
6575 * order to enable memory self-refresh
6576 * The bit 22/21 of 0x42004
6577 * The bit 5 of 0x42020
6578 * The bit 15 of 0x45000
6579 */
6580 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6581 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6582 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6583 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6584 I915_WRITE(DISP_ARB_CTL,
6585 (I915_READ(DISP_ARB_CTL) |
6586 DISP_FBC_WM_DIS));
6587
6588 ilk_init_lp_watermarks(dev);
6589
6590 /*
6591 * Based on the document from hardware guys the following bits
6592 * should be set unconditionally in order to enable FBC.
6593 * The bit 22 of 0x42000
6594 * The bit 22 of 0x42004
6595 * The bit 7,8,9 of 0x42020.
6596 */
6597 if (IS_IRONLAKE_M(dev)) {
6598 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6599 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6600 I915_READ(ILK_DISPLAY_CHICKEN1) |
6601 ILK_FBCQ_DIS);
6602 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6603 I915_READ(ILK_DISPLAY_CHICKEN2) |
6604 ILK_DPARB_GATE);
6605 }
6606
6607 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6608
6609 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6610 I915_READ(ILK_DISPLAY_CHICKEN2) |
6611 ILK_ELPIN_409_SELECT);
6612 I915_WRITE(_3D_CHICKEN2,
6613 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6614 _3D_CHICKEN2_WM_READ_PIPELINED);
6615
6616 /* WaDisableRenderCachePipelinedFlush:ilk */
6617 I915_WRITE(CACHE_MODE_0,
6618 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6619
6620 /* WaDisable_RenderCache_OperationalFlush:ilk */
6621 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6622
6623 g4x_disable_trickle_feed(dev);
6624
6625 ibx_init_clock_gating(dev);
6626 }
6627
6628 static void cpt_init_clock_gating(struct drm_device *dev)
6629 {
6630 struct drm_i915_private *dev_priv = dev->dev_private;
6631 int pipe;
6632 uint32_t val;
6633
6634 /*
6635 * On Ibex Peak and Cougar Point, we need to disable clock
6636 * gating for the panel power sequencer or it will fail to
6637 * start up when no ports are active.
6638 */
6639 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6640 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6641 PCH_CPUNIT_CLOCK_GATE_DISABLE);
6642 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6643 DPLS_EDP_PPS_FIX_DIS);
6644 /* The below fixes the weird display corruption, a few pixels shifted
6645 * downward, on (only) LVDS of some HP laptops with IVY.
6646 */
6647 for_each_pipe(dev_priv, pipe) {
6648 val = I915_READ(TRANS_CHICKEN2(pipe));
6649 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6650 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6651 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6652 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6653 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6654 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6655 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6656 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6657 }
6658 /* WADP0ClockGatingDisable */
6659 for_each_pipe(dev_priv, pipe) {
6660 I915_WRITE(TRANS_CHICKEN1(pipe),
6661 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6662 }
6663 }
6664
6665 static void gen6_check_mch_setup(struct drm_device *dev)
6666 {
6667 struct drm_i915_private *dev_priv = dev->dev_private;
6668 uint32_t tmp;
6669
6670 tmp = I915_READ(MCH_SSKPD);
6671 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6672 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6673 tmp);
6674 }
6675
6676 static void gen6_init_clock_gating(struct drm_device *dev)
6677 {
6678 struct drm_i915_private *dev_priv = dev->dev_private;
6679 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6680
6681 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6682
6683 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6684 I915_READ(ILK_DISPLAY_CHICKEN2) |
6685 ILK_ELPIN_409_SELECT);
6686
6687 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6688 I915_WRITE(_3D_CHICKEN,
6689 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6690
6691 /* WaDisable_RenderCache_OperationalFlush:snb */
6692 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6693
6694 /*
6695 * BSpec recoomends 8x4 when MSAA is used,
6696 * however in practice 16x4 seems fastest.
6697 *
6698 * Note that PS/WM thread counts depend on the WIZ hashing
6699 * disable bit, which we don't touch here, but it's good
6700 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6701 */
6702 I915_WRITE(GEN6_GT_MODE,
6703 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6704
6705 ilk_init_lp_watermarks(dev);
6706
6707 I915_WRITE(CACHE_MODE_0,
6708 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6709
6710 I915_WRITE(GEN6_UCGCTL1,
6711 I915_READ(GEN6_UCGCTL1) |
6712 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6713 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6714
6715 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6716 * gating disable must be set. Failure to set it results in
6717 * flickering pixels due to Z write ordering failures after
6718 * some amount of runtime in the Mesa "fire" demo, and Unigine
6719 * Sanctuary and Tropics, and apparently anything else with
6720 * alpha test or pixel discard.
6721 *
6722 * According to the spec, bit 11 (RCCUNIT) must also be set,
6723 * but we didn't debug actual testcases to find it out.
6724 *
6725 * WaDisableRCCUnitClockGating:snb
6726 * WaDisableRCPBUnitClockGating:snb
6727 */
6728 I915_WRITE(GEN6_UCGCTL2,
6729 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6730 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6731
6732 /* WaStripsFansDisableFastClipPerformanceFix:snb */
6733 I915_WRITE(_3D_CHICKEN3,
6734 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6735
6736 /*
6737 * Bspec says:
6738 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6739 * 3DSTATE_SF number of SF output attributes is more than 16."
6740 */
6741 I915_WRITE(_3D_CHICKEN3,
6742 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6743
6744 /*
6745 * According to the spec the following bits should be
6746 * set in order to enable memory self-refresh and fbc:
6747 * The bit21 and bit22 of 0x42000
6748 * The bit21 and bit22 of 0x42004
6749 * The bit5 and bit7 of 0x42020
6750 * The bit14 of 0x70180
6751 * The bit14 of 0x71180
6752 *
6753 * WaFbcAsynchFlipDisableFbcQueue:snb
6754 */
6755 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6756 I915_READ(ILK_DISPLAY_CHICKEN1) |
6757 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6758 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6759 I915_READ(ILK_DISPLAY_CHICKEN2) |
6760 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6761 I915_WRITE(ILK_DSPCLK_GATE_D,
6762 I915_READ(ILK_DSPCLK_GATE_D) |
6763 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6764 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6765
6766 g4x_disable_trickle_feed(dev);
6767
6768 cpt_init_clock_gating(dev);
6769
6770 gen6_check_mch_setup(dev);
6771 }
6772
6773 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6774 {
6775 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6776
6777 /*
6778 * WaVSThreadDispatchOverride:ivb,vlv
6779 *
6780 * This actually overrides the dispatch
6781 * mode for all thread types.
6782 */
6783 reg &= ~GEN7_FF_SCHED_MASK;
6784 reg |= GEN7_FF_TS_SCHED_HW;
6785 reg |= GEN7_FF_VS_SCHED_HW;
6786 reg |= GEN7_FF_DS_SCHED_HW;
6787
6788 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6789 }
6790
6791 static void lpt_init_clock_gating(struct drm_device *dev)
6792 {
6793 struct drm_i915_private *dev_priv = dev->dev_private;
6794
6795 /*
6796 * TODO: this bit should only be enabled when really needed, then
6797 * disabled when not needed anymore in order to save power.
6798 */
6799 if (HAS_PCH_LPT_LP(dev))
6800 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6801 I915_READ(SOUTH_DSPCLK_GATE_D) |
6802 PCH_LP_PARTITION_LEVEL_DISABLE);
6803
6804 /* WADPOClockGatingDisable:hsw */
6805 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6806 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6807 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6808 }
6809
6810 static void lpt_suspend_hw(struct drm_device *dev)
6811 {
6812 struct drm_i915_private *dev_priv = dev->dev_private;
6813
6814 if (HAS_PCH_LPT_LP(dev)) {
6815 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6816
6817 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6818 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6819 }
6820 }
6821
6822 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
6823 int general_prio_credits,
6824 int high_prio_credits)
6825 {
6826 u32 misccpctl;
6827
6828 /* WaTempDisableDOPClkGating:bdw */
6829 misccpctl = I915_READ(GEN7_MISCCPCTL);
6830 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6831
6832 I915_WRITE(GEN8_L3SQCREG1,
6833 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
6834 L3_HIGH_PRIO_CREDITS(high_prio_credits));
6835
6836 /*
6837 * Wait at least 100 clocks before re-enabling clock gating.
6838 * See the definition of L3SQCREG1 in BSpec.
6839 */
6840 POSTING_READ(GEN8_L3SQCREG1);
6841 udelay(1);
6842 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6843 }
6844
6845 static void broadwell_init_clock_gating(struct drm_device *dev)
6846 {
6847 struct drm_i915_private *dev_priv = dev->dev_private;
6848 enum pipe pipe;
6849
6850 ilk_init_lp_watermarks(dev);
6851
6852 /* WaSwitchSolVfFArbitrationPriority:bdw */
6853 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6854
6855 /* WaPsrDPAMaskVBlankInSRD:bdw */
6856 I915_WRITE(CHICKEN_PAR1_1,
6857 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6858
6859 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6860 for_each_pipe(dev_priv, pipe) {
6861 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6862 I915_READ(CHICKEN_PIPESL_1(pipe)) |
6863 BDW_DPRS_MASK_VBLANK_SRD);
6864 }
6865
6866 /* WaVSRefCountFullforceMissDisable:bdw */
6867 /* WaDSRefCountFullforceMissDisable:bdw */
6868 I915_WRITE(GEN7_FF_THREAD_MODE,
6869 I915_READ(GEN7_FF_THREAD_MODE) &
6870 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6871
6872 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6873 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6874
6875 /* WaDisableSDEUnitClockGating:bdw */
6876 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6877 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6878
6879 /* WaProgramL3SqcReg1Default:bdw */
6880 gen8_set_l3sqc_credits(dev_priv, 30, 2);
6881
6882 /*
6883 * WaGttCachingOffByDefault:bdw
6884 * GTT cache may not work with big pages, so if those
6885 * are ever enabled GTT cache may need to be disabled.
6886 */
6887 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6888
6889 lpt_init_clock_gating(dev);
6890 }
6891
6892 static void haswell_init_clock_gating(struct drm_device *dev)
6893 {
6894 struct drm_i915_private *dev_priv = dev->dev_private;
6895
6896 ilk_init_lp_watermarks(dev);
6897
6898 /* L3 caching of data atomics doesn't work -- disable it. */
6899 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6900 I915_WRITE(HSW_ROW_CHICKEN3,
6901 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6902
6903 /* This is required by WaCatErrorRejectionIssue:hsw */
6904 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6905 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6906 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6907
6908 /* WaVSRefCountFullforceMissDisable:hsw */
6909 I915_WRITE(GEN7_FF_THREAD_MODE,
6910 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6911
6912 /* WaDisable_RenderCache_OperationalFlush:hsw */
6913 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6914
6915 /* enable HiZ Raw Stall Optimization */
6916 I915_WRITE(CACHE_MODE_0_GEN7,
6917 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6918
6919 /* WaDisable4x2SubspanOptimization:hsw */
6920 I915_WRITE(CACHE_MODE_1,
6921 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6922
6923 /*
6924 * BSpec recommends 8x4 when MSAA is used,
6925 * however in practice 16x4 seems fastest.
6926 *
6927 * Note that PS/WM thread counts depend on the WIZ hashing
6928 * disable bit, which we don't touch here, but it's good
6929 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6930 */
6931 I915_WRITE(GEN7_GT_MODE,
6932 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6933
6934 /* WaSampleCChickenBitEnable:hsw */
6935 I915_WRITE(HALF_SLICE_CHICKEN3,
6936 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6937
6938 /* WaSwitchSolVfFArbitrationPriority:hsw */
6939 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6940
6941 /* WaRsPkgCStateDisplayPMReq:hsw */
6942 I915_WRITE(CHICKEN_PAR1_1,
6943 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6944
6945 lpt_init_clock_gating(dev);
6946 }
6947
6948 static void ivybridge_init_clock_gating(struct drm_device *dev)
6949 {
6950 struct drm_i915_private *dev_priv = dev->dev_private;
6951 uint32_t snpcr;
6952
6953 ilk_init_lp_watermarks(dev);
6954
6955 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6956
6957 /* WaDisableEarlyCull:ivb */
6958 I915_WRITE(_3D_CHICKEN3,
6959 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6960
6961 /* WaDisableBackToBackFlipFix:ivb */
6962 I915_WRITE(IVB_CHICKEN3,
6963 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6964 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6965
6966 /* WaDisablePSDDualDispatchEnable:ivb */
6967 if (IS_IVB_GT1(dev))
6968 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6969 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6970
6971 /* WaDisable_RenderCache_OperationalFlush:ivb */
6972 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6973
6974 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6975 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6976 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6977
6978 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6979 I915_WRITE(GEN7_L3CNTLREG1,
6980 GEN7_WA_FOR_GEN7_L3_CONTROL);
6981 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6982 GEN7_WA_L3_CHICKEN_MODE);
6983 if (IS_IVB_GT1(dev))
6984 I915_WRITE(GEN7_ROW_CHICKEN2,
6985 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6986 else {
6987 /* must write both registers */
6988 I915_WRITE(GEN7_ROW_CHICKEN2,
6989 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6990 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6991 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6992 }
6993
6994 /* WaForceL3Serialization:ivb */
6995 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6996 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6997
6998 /*
6999 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7000 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7001 */
7002 I915_WRITE(GEN6_UCGCTL2,
7003 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7004
7005 /* This is required by WaCatErrorRejectionIssue:ivb */
7006 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7007 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7008 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7009
7010 g4x_disable_trickle_feed(dev);
7011
7012 gen7_setup_fixed_func_scheduler(dev_priv);
7013
7014 if (0) { /* causes HiZ corruption on ivb:gt1 */
7015 /* enable HiZ Raw Stall Optimization */
7016 I915_WRITE(CACHE_MODE_0_GEN7,
7017 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7018 }
7019
7020 /* WaDisable4x2SubspanOptimization:ivb */
7021 I915_WRITE(CACHE_MODE_1,
7022 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7023
7024 /*
7025 * BSpec recommends 8x4 when MSAA is used,
7026 * however in practice 16x4 seems fastest.
7027 *
7028 * Note that PS/WM thread counts depend on the WIZ hashing
7029 * disable bit, which we don't touch here, but it's good
7030 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7031 */
7032 I915_WRITE(GEN7_GT_MODE,
7033 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7034
7035 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7036 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7037 snpcr |= GEN6_MBC_SNPCR_MED;
7038 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7039
7040 if (!HAS_PCH_NOP(dev))
7041 cpt_init_clock_gating(dev);
7042
7043 gen6_check_mch_setup(dev);
7044 }
7045
7046 static void valleyview_init_clock_gating(struct drm_device *dev)
7047 {
7048 struct drm_i915_private *dev_priv = dev->dev_private;
7049
7050 /* WaDisableEarlyCull:vlv */
7051 I915_WRITE(_3D_CHICKEN3,
7052 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7053
7054 /* WaDisableBackToBackFlipFix:vlv */
7055 I915_WRITE(IVB_CHICKEN3,
7056 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7057 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7058
7059 /* WaPsdDispatchEnable:vlv */
7060 /* WaDisablePSDDualDispatchEnable:vlv */
7061 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7062 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7063 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7064
7065 /* WaDisable_RenderCache_OperationalFlush:vlv */
7066 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7067
7068 /* WaForceL3Serialization:vlv */
7069 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7070 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7071
7072 /* WaDisableDopClockGating:vlv */
7073 I915_WRITE(GEN7_ROW_CHICKEN2,
7074 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7075
7076 /* This is required by WaCatErrorRejectionIssue:vlv */
7077 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7078 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7079 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7080
7081 gen7_setup_fixed_func_scheduler(dev_priv);
7082
7083 /*
7084 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7085 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7086 */
7087 I915_WRITE(GEN6_UCGCTL2,
7088 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7089
7090 /* WaDisableL3Bank2xClockGate:vlv
7091 * Disabling L3 clock gating- MMIO 940c[25] = 1
7092 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7093 I915_WRITE(GEN7_UCGCTL4,
7094 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7095
7096 /*
7097 * BSpec says this must be set, even though
7098 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7099 */
7100 I915_WRITE(CACHE_MODE_1,
7101 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7102
7103 /*
7104 * BSpec recommends 8x4 when MSAA is used,
7105 * however in practice 16x4 seems fastest.
7106 *
7107 * Note that PS/WM thread counts depend on the WIZ hashing
7108 * disable bit, which we don't touch here, but it's good
7109 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7110 */
7111 I915_WRITE(GEN7_GT_MODE,
7112 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7113
7114 /*
7115 * WaIncreaseL3CreditsForVLVB0:vlv
7116 * This is the hardware default actually.
7117 */
7118 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7119
7120 /*
7121 * WaDisableVLVClockGating_VBIIssue:vlv
7122 * Disable clock gating on th GCFG unit to prevent a delay
7123 * in the reporting of vblank events.
7124 */
7125 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7126 }
7127
7128 static void cherryview_init_clock_gating(struct drm_device *dev)
7129 {
7130 struct drm_i915_private *dev_priv = dev->dev_private;
7131
7132 /* WaVSRefCountFullforceMissDisable:chv */
7133 /* WaDSRefCountFullforceMissDisable:chv */
7134 I915_WRITE(GEN7_FF_THREAD_MODE,
7135 I915_READ(GEN7_FF_THREAD_MODE) &
7136 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7137
7138 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7139 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7140 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7141
7142 /* WaDisableCSUnitClockGating:chv */
7143 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7144 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7145
7146 /* WaDisableSDEUnitClockGating:chv */
7147 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7148 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7149
7150 /*
7151 * WaProgramL3SqcReg1Default:chv
7152 * See gfxspecs/Related Documents/Performance Guide/
7153 * LSQC Setting Recommendations.
7154 */
7155 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7156
7157 /*
7158 * GTT cache may not work with big pages, so if those
7159 * are ever enabled GTT cache may need to be disabled.
7160 */
7161 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7162 }
7163
7164 static void g4x_init_clock_gating(struct drm_device *dev)
7165 {
7166 struct drm_i915_private *dev_priv = dev->dev_private;
7167 uint32_t dspclk_gate;
7168
7169 I915_WRITE(RENCLK_GATE_D1, 0);
7170 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7171 GS_UNIT_CLOCK_GATE_DISABLE |
7172 CL_UNIT_CLOCK_GATE_DISABLE);
7173 I915_WRITE(RAMCLK_GATE_D, 0);
7174 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7175 OVRUNIT_CLOCK_GATE_DISABLE |
7176 OVCUNIT_CLOCK_GATE_DISABLE;
7177 if (IS_GM45(dev))
7178 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7179 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7180
7181 /* WaDisableRenderCachePipelinedFlush */
7182 I915_WRITE(CACHE_MODE_0,
7183 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7184
7185 /* WaDisable_RenderCache_OperationalFlush:g4x */
7186 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7187
7188 g4x_disable_trickle_feed(dev);
7189 }
7190
7191 static void crestline_init_clock_gating(struct drm_device *dev)
7192 {
7193 struct drm_i915_private *dev_priv = dev->dev_private;
7194
7195 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7196 I915_WRITE(RENCLK_GATE_D2, 0);
7197 I915_WRITE(DSPCLK_GATE_D, 0);
7198 I915_WRITE(RAMCLK_GATE_D, 0);
7199 I915_WRITE16(DEUC, 0);
7200 I915_WRITE(MI_ARB_STATE,
7201 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7202
7203 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7204 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7205 }
7206
7207 static void broadwater_init_clock_gating(struct drm_device *dev)
7208 {
7209 struct drm_i915_private *dev_priv = dev->dev_private;
7210
7211 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7212 I965_RCC_CLOCK_GATE_DISABLE |
7213 I965_RCPB_CLOCK_GATE_DISABLE |
7214 I965_ISC_CLOCK_GATE_DISABLE |
7215 I965_FBC_CLOCK_GATE_DISABLE);
7216 I915_WRITE(RENCLK_GATE_D2, 0);
7217 I915_WRITE(MI_ARB_STATE,
7218 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7219
7220 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7221 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7222 }
7223
7224 static void gen3_init_clock_gating(struct drm_device *dev)
7225 {
7226 struct drm_i915_private *dev_priv = dev->dev_private;
7227 u32 dstate = I915_READ(D_STATE);
7228
7229 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7230 DSTATE_DOT_CLOCK_GATING;
7231 I915_WRITE(D_STATE, dstate);
7232
7233 if (IS_PINEVIEW(dev))
7234 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7235
7236 /* IIR "flip pending" means done if this bit is set */
7237 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7238
7239 /* interrupts should cause a wake up from C3 */
7240 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7241
7242 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7243 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7244
7245 I915_WRITE(MI_ARB_STATE,
7246 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7247 }
7248
7249 static void i85x_init_clock_gating(struct drm_device *dev)
7250 {
7251 struct drm_i915_private *dev_priv = dev->dev_private;
7252
7253 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7254
7255 /* interrupts should cause a wake up from C3 */
7256 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7257 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7258
7259 I915_WRITE(MEM_MODE,
7260 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7261 }
7262
7263 static void i830_init_clock_gating(struct drm_device *dev)
7264 {
7265 struct drm_i915_private *dev_priv = dev->dev_private;
7266
7267 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7268
7269 I915_WRITE(MEM_MODE,
7270 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7271 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7272 }
7273
7274 void intel_init_clock_gating(struct drm_device *dev)
7275 {
7276 struct drm_i915_private *dev_priv = dev->dev_private;
7277
7278 dev_priv->display.init_clock_gating(dev);
7279 }
7280
7281 void intel_suspend_hw(struct drm_device *dev)
7282 {
7283 if (HAS_PCH_LPT(dev))
7284 lpt_suspend_hw(dev);
7285 }
7286
7287 static void nop_init_clock_gating(struct drm_device *dev)
7288 {
7289 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7290 }
7291
7292 /**
7293 * intel_init_clock_gating_hooks - setup the clock gating hooks
7294 * @dev_priv: device private
7295 *
7296 * Setup the hooks that configure which clocks of a given platform can be
7297 * gated and also apply various GT and display specific workarounds for these
7298 * platforms. Note that some GT specific workarounds are applied separately
7299 * when GPU contexts or batchbuffers start their execution.
7300 */
7301 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7302 {
7303 if (IS_SKYLAKE(dev_priv))
7304 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7305 else if (IS_KABYLAKE(dev_priv))
7306 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7307 else if (IS_BROXTON(dev_priv))
7308 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7309 else if (IS_BROADWELL(dev_priv))
7310 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7311 else if (IS_CHERRYVIEW(dev_priv))
7312 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7313 else if (IS_HASWELL(dev_priv))
7314 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7315 else if (IS_IVYBRIDGE(dev_priv))
7316 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7317 else if (IS_VALLEYVIEW(dev_priv))
7318 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7319 else if (IS_GEN6(dev_priv))
7320 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7321 else if (IS_GEN5(dev_priv))
7322 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7323 else if (IS_G4X(dev_priv))
7324 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7325 else if (IS_CRESTLINE(dev_priv))
7326 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7327 else if (IS_BROADWATER(dev_priv))
7328 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7329 else if (IS_GEN3(dev_priv))
7330 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7331 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7332 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7333 else if (IS_GEN2(dev_priv))
7334 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7335 else {
7336 MISSING_CASE(INTEL_DEVID(dev_priv));
7337 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7338 }
7339 }
7340
7341 /* Set up chip specific power management-related functions */
7342 void intel_init_pm(struct drm_device *dev)
7343 {
7344 struct drm_i915_private *dev_priv = dev->dev_private;
7345
7346 intel_fbc_init(dev_priv);
7347
7348 /* For cxsr */
7349 if (IS_PINEVIEW(dev))
7350 i915_pineview_get_mem_freq(dev);
7351 else if (IS_GEN5(dev))
7352 i915_ironlake_get_mem_freq(dev);
7353
7354 /* For FIFO watermark updates */
7355 if (INTEL_INFO(dev)->gen >= 9) {
7356 skl_setup_wm_latency(dev);
7357 dev_priv->display.update_wm = skl_update_wm;
7358 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7359 } else if (HAS_PCH_SPLIT(dev)) {
7360 ilk_setup_wm_latency(dev);
7361
7362 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7363 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7364 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7365 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7366 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7367 dev_priv->display.compute_intermediate_wm =
7368 ilk_compute_intermediate_wm;
7369 dev_priv->display.initial_watermarks =
7370 ilk_initial_watermarks;
7371 dev_priv->display.optimize_watermarks =
7372 ilk_optimize_watermarks;
7373 } else {
7374 DRM_DEBUG_KMS("Failed to read display plane latency. "
7375 "Disable CxSR\n");
7376 }
7377 } else if (IS_CHERRYVIEW(dev)) {
7378 vlv_setup_wm_latency(dev);
7379 dev_priv->display.update_wm = vlv_update_wm;
7380 } else if (IS_VALLEYVIEW(dev)) {
7381 vlv_setup_wm_latency(dev);
7382 dev_priv->display.update_wm = vlv_update_wm;
7383 } else if (IS_PINEVIEW(dev)) {
7384 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7385 dev_priv->is_ddr3,
7386 dev_priv->fsb_freq,
7387 dev_priv->mem_freq)) {
7388 DRM_INFO("failed to find known CxSR latency "
7389 "(found ddr%s fsb freq %d, mem freq %d), "
7390 "disabling CxSR\n",
7391 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7392 dev_priv->fsb_freq, dev_priv->mem_freq);
7393 /* Disable CxSR and never update its watermark again */
7394 intel_set_memory_cxsr(dev_priv, false);
7395 dev_priv->display.update_wm = NULL;
7396 } else
7397 dev_priv->display.update_wm = pineview_update_wm;
7398 } else if (IS_G4X(dev)) {
7399 dev_priv->display.update_wm = g4x_update_wm;
7400 } else if (IS_GEN4(dev)) {
7401 dev_priv->display.update_wm = i965_update_wm;
7402 } else if (IS_GEN3(dev)) {
7403 dev_priv->display.update_wm = i9xx_update_wm;
7404 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7405 } else if (IS_GEN2(dev)) {
7406 if (INTEL_INFO(dev)->num_pipes == 1) {
7407 dev_priv->display.update_wm = i845_update_wm;
7408 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7409 } else {
7410 dev_priv->display.update_wm = i9xx_update_wm;
7411 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7412 }
7413 } else {
7414 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7415 }
7416 }
7417
7418 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7419 {
7420 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7421
7422 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7423 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7424 return -EAGAIN;
7425 }
7426
7427 I915_WRITE(GEN6_PCODE_DATA, *val);
7428 I915_WRITE(GEN6_PCODE_DATA1, 0);
7429 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7430
7431 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7432 500)) {
7433 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7434 return -ETIMEDOUT;
7435 }
7436
7437 *val = I915_READ(GEN6_PCODE_DATA);
7438 I915_WRITE(GEN6_PCODE_DATA, 0);
7439
7440 return 0;
7441 }
7442
7443 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7444 {
7445 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7446
7447 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7448 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7449 return -EAGAIN;
7450 }
7451
7452 I915_WRITE(GEN6_PCODE_DATA, val);
7453 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7454
7455 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7456 500)) {
7457 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7458 return -ETIMEDOUT;
7459 }
7460
7461 I915_WRITE(GEN6_PCODE_DATA, 0);
7462
7463 return 0;
7464 }
7465
7466 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7467 {
7468 /*
7469 * N = val - 0xb7
7470 * Slow = Fast = GPLL ref * N
7471 */
7472 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7473 }
7474
7475 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7476 {
7477 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7478 }
7479
7480 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7481 {
7482 /*
7483 * N = val / 2
7484 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7485 */
7486 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7487 }
7488
7489 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7490 {
7491 /* CHV needs even values */
7492 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7493 }
7494
7495 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7496 {
7497 if (IS_GEN9(dev_priv))
7498 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7499 GEN9_FREQ_SCALER);
7500 else if (IS_CHERRYVIEW(dev_priv))
7501 return chv_gpu_freq(dev_priv, val);
7502 else if (IS_VALLEYVIEW(dev_priv))
7503 return byt_gpu_freq(dev_priv, val);
7504 else
7505 return val * GT_FREQUENCY_MULTIPLIER;
7506 }
7507
7508 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7509 {
7510 if (IS_GEN9(dev_priv))
7511 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7512 GT_FREQUENCY_MULTIPLIER);
7513 else if (IS_CHERRYVIEW(dev_priv))
7514 return chv_freq_opcode(dev_priv, val);
7515 else if (IS_VALLEYVIEW(dev_priv))
7516 return byt_freq_opcode(dev_priv, val);
7517 else
7518 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7519 }
7520
7521 struct request_boost {
7522 struct work_struct work;
7523 struct drm_i915_gem_request *req;
7524 };
7525
7526 static void __intel_rps_boost_work(struct work_struct *work)
7527 {
7528 struct request_boost *boost = container_of(work, struct request_boost, work);
7529 struct drm_i915_gem_request *req = boost->req;
7530
7531 if (!i915_gem_request_completed(req, true))
7532 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
7533
7534 i915_gem_request_unreference(req);
7535 kfree(boost);
7536 }
7537
7538 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
7539 {
7540 struct request_boost *boost;
7541
7542 if (req == NULL || INTEL_GEN(req->i915) < 6)
7543 return;
7544
7545 if (i915_gem_request_completed(req, true))
7546 return;
7547
7548 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7549 if (boost == NULL)
7550 return;
7551
7552 i915_gem_request_reference(req);
7553 boost->req = req;
7554
7555 INIT_WORK(&boost->work, __intel_rps_boost_work);
7556 queue_work(req->i915->wq, &boost->work);
7557 }
7558
7559 void intel_pm_setup(struct drm_device *dev)
7560 {
7561 struct drm_i915_private *dev_priv = dev->dev_private;
7562
7563 mutex_init(&dev_priv->rps.hw_lock);
7564 spin_lock_init(&dev_priv->rps.client_lock);
7565
7566 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7567 intel_gen6_powersave_work);
7568 INIT_LIST_HEAD(&dev_priv->rps.clients);
7569 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7570 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7571
7572 dev_priv->pm.suspended = false;
7573 atomic_set(&dev_priv->pm.wakeref_count, 0);
7574 atomic_set(&dev_priv->pm.atomic_seq, 0);
7575 }
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