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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
36
37 /**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
57
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
61 *
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
64 *
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
67 */
68
69 static void i8xx_disable_fbc(struct drm_device *dev)
70 {
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89 }
90
91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
92 {
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
95 struct drm_framebuffer *fb = crtc->fb;
96 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
97 struct drm_i915_gem_object *obj = intel_fb->obj;
98 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
99 int cfb_pitch;
100 int plane, i;
101 u32 fbc_ctl;
102
103 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
104 if (fb->pitches[0] < cfb_pitch)
105 cfb_pitch = fb->pitches[0];
106
107 /* FBC_CTL wants 32B or 64B units */
108 if (IS_GEN2(dev))
109 cfb_pitch = (cfb_pitch / 32) - 1;
110 else
111 cfb_pitch = (cfb_pitch / 64) - 1;
112 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
113
114 /* Clear old tags */
115 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
116 I915_WRITE(FBC_TAG + (i * 4), 0);
117
118 if (IS_GEN4(dev)) {
119 u32 fbc_ctl2;
120
121 /* Set it up... */
122 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
123 fbc_ctl2 |= plane;
124 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
125 I915_WRITE(FBC_FENCE_OFF, crtc->y);
126 }
127
128 /* enable it... */
129 fbc_ctl = I915_READ(FBC_CONTROL);
130 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
131 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
132 if (IS_I945GM(dev))
133 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
134 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
135 fbc_ctl |= obj->fence_reg;
136 I915_WRITE(FBC_CONTROL, fbc_ctl);
137
138 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
139 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
140 }
141
142 static bool i8xx_fbc_enabled(struct drm_device *dev)
143 {
144 struct drm_i915_private *dev_priv = dev->dev_private;
145
146 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
147 }
148
149 static void g4x_enable_fbc(struct drm_crtc *crtc)
150 {
151 struct drm_device *dev = crtc->dev;
152 struct drm_i915_private *dev_priv = dev->dev_private;
153 struct drm_framebuffer *fb = crtc->fb;
154 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
155 struct drm_i915_gem_object *obj = intel_fb->obj;
156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
157 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
158 u32 dpfc_ctl;
159
160 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
161 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
162 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
163
164 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
165
166 /* enable it... */
167 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
168
169 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
170 }
171
172 static void g4x_disable_fbc(struct drm_device *dev)
173 {
174 struct drm_i915_private *dev_priv = dev->dev_private;
175 u32 dpfc_ctl;
176
177 /* Disable compression */
178 dpfc_ctl = I915_READ(DPFC_CONTROL);
179 if (dpfc_ctl & DPFC_CTL_EN) {
180 dpfc_ctl &= ~DPFC_CTL_EN;
181 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
182
183 DRM_DEBUG_KMS("disabled FBC\n");
184 }
185 }
186
187 static bool g4x_fbc_enabled(struct drm_device *dev)
188 {
189 struct drm_i915_private *dev_priv = dev->dev_private;
190
191 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
192 }
193
194 static void sandybridge_blit_fbc_update(struct drm_device *dev)
195 {
196 struct drm_i915_private *dev_priv = dev->dev_private;
197 u32 blt_ecoskpd;
198
199 /* Make sure blitter notifies FBC of writes */
200
201 /* Blitter is part of Media powerwell on VLV. No impact of
202 * his param in other platforms for now */
203 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
204
205 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
206 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
207 GEN6_BLITTER_LOCK_SHIFT;
208 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
209 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
210 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
211 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
212 GEN6_BLITTER_LOCK_SHIFT);
213 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
214 POSTING_READ(GEN6_BLITTER_ECOSKPD);
215
216 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
217 }
218
219 static void ironlake_enable_fbc(struct drm_crtc *crtc)
220 {
221 struct drm_device *dev = crtc->dev;
222 struct drm_i915_private *dev_priv = dev->dev_private;
223 struct drm_framebuffer *fb = crtc->fb;
224 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
225 struct drm_i915_gem_object *obj = intel_fb->obj;
226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
227 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
228 u32 dpfc_ctl;
229
230 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
231 dpfc_ctl &= DPFC_RESERVED;
232 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
233 /* Set persistent mode for front-buffer rendering, ala X. */
234 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
235 dpfc_ctl |= DPFC_CTL_FENCE_EN;
236 if (IS_GEN5(dev))
237 dpfc_ctl |= obj->fence_reg;
238 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
239
240 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
241 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
242 /* enable it... */
243 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
244
245 if (IS_GEN6(dev)) {
246 I915_WRITE(SNB_DPFC_CTL_SA,
247 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
248 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
249 sandybridge_blit_fbc_update(dev);
250 }
251
252 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
253 }
254
255 static void ironlake_disable_fbc(struct drm_device *dev)
256 {
257 struct drm_i915_private *dev_priv = dev->dev_private;
258 u32 dpfc_ctl;
259
260 /* Disable compression */
261 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
262 if (dpfc_ctl & DPFC_CTL_EN) {
263 dpfc_ctl &= ~DPFC_CTL_EN;
264 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
265
266 DRM_DEBUG_KMS("disabled FBC\n");
267 }
268 }
269
270 static bool ironlake_fbc_enabled(struct drm_device *dev)
271 {
272 struct drm_i915_private *dev_priv = dev->dev_private;
273
274 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
275 }
276
277 static void gen7_enable_fbc(struct drm_crtc *crtc)
278 {
279 struct drm_device *dev = crtc->dev;
280 struct drm_i915_private *dev_priv = dev->dev_private;
281 struct drm_framebuffer *fb = crtc->fb;
282 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
283 struct drm_i915_gem_object *obj = intel_fb->obj;
284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
285
286 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
287
288 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
289 IVB_DPFC_CTL_FENCE_EN |
290 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
291
292 if (IS_IVYBRIDGE(dev)) {
293 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
294 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
295 } else {
296 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
297 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
298 HSW_BYPASS_FBC_QUEUE);
299 }
300
301 I915_WRITE(SNB_DPFC_CTL_SA,
302 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
303 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
304
305 sandybridge_blit_fbc_update(dev);
306
307 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
308 }
309
310 bool intel_fbc_enabled(struct drm_device *dev)
311 {
312 struct drm_i915_private *dev_priv = dev->dev_private;
313
314 if (!dev_priv->display.fbc_enabled)
315 return false;
316
317 return dev_priv->display.fbc_enabled(dev);
318 }
319
320 static void intel_fbc_work_fn(struct work_struct *__work)
321 {
322 struct intel_fbc_work *work =
323 container_of(to_delayed_work(__work),
324 struct intel_fbc_work, work);
325 struct drm_device *dev = work->crtc->dev;
326 struct drm_i915_private *dev_priv = dev->dev_private;
327
328 mutex_lock(&dev->struct_mutex);
329 if (work == dev_priv->fbc.fbc_work) {
330 /* Double check that we haven't switched fb without cancelling
331 * the prior work.
332 */
333 if (work->crtc->fb == work->fb) {
334 dev_priv->display.enable_fbc(work->crtc);
335
336 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
337 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
338 dev_priv->fbc.y = work->crtc->y;
339 }
340
341 dev_priv->fbc.fbc_work = NULL;
342 }
343 mutex_unlock(&dev->struct_mutex);
344
345 kfree(work);
346 }
347
348 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
349 {
350 if (dev_priv->fbc.fbc_work == NULL)
351 return;
352
353 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
354
355 /* Synchronisation is provided by struct_mutex and checking of
356 * dev_priv->fbc.fbc_work, so we can perform the cancellation
357 * entirely asynchronously.
358 */
359 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
360 /* tasklet was killed before being run, clean up */
361 kfree(dev_priv->fbc.fbc_work);
362
363 /* Mark the work as no longer wanted so that if it does
364 * wake-up (because the work was already running and waiting
365 * for our mutex), it will discover that is no longer
366 * necessary to run.
367 */
368 dev_priv->fbc.fbc_work = NULL;
369 }
370
371 static void intel_enable_fbc(struct drm_crtc *crtc)
372 {
373 struct intel_fbc_work *work;
374 struct drm_device *dev = crtc->dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
376
377 if (!dev_priv->display.enable_fbc)
378 return;
379
380 intel_cancel_fbc_work(dev_priv);
381
382 work = kzalloc(sizeof(*work), GFP_KERNEL);
383 if (work == NULL) {
384 DRM_ERROR("Failed to allocate FBC work structure\n");
385 dev_priv->display.enable_fbc(crtc);
386 return;
387 }
388
389 work->crtc = crtc;
390 work->fb = crtc->fb;
391 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
392
393 dev_priv->fbc.fbc_work = work;
394
395 /* Delay the actual enabling to let pageflipping cease and the
396 * display to settle before starting the compression. Note that
397 * this delay also serves a second purpose: it allows for a
398 * vblank to pass after disabling the FBC before we attempt
399 * to modify the control registers.
400 *
401 * A more complicated solution would involve tracking vblanks
402 * following the termination of the page-flipping sequence
403 * and indeed performing the enable as a co-routine and not
404 * waiting synchronously upon the vblank.
405 *
406 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
407 */
408 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
409 }
410
411 void intel_disable_fbc(struct drm_device *dev)
412 {
413 struct drm_i915_private *dev_priv = dev->dev_private;
414
415 intel_cancel_fbc_work(dev_priv);
416
417 if (!dev_priv->display.disable_fbc)
418 return;
419
420 dev_priv->display.disable_fbc(dev);
421 dev_priv->fbc.plane = -1;
422 }
423
424 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
425 enum no_fbc_reason reason)
426 {
427 if (dev_priv->fbc.no_fbc_reason == reason)
428 return false;
429
430 dev_priv->fbc.no_fbc_reason = reason;
431 return true;
432 }
433
434 /**
435 * intel_update_fbc - enable/disable FBC as needed
436 * @dev: the drm_device
437 *
438 * Set up the framebuffer compression hardware at mode set time. We
439 * enable it if possible:
440 * - plane A only (on pre-965)
441 * - no pixel mulitply/line duplication
442 * - no alpha buffer discard
443 * - no dual wide
444 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
445 *
446 * We can't assume that any compression will take place (worst case),
447 * so the compressed buffer has to be the same size as the uncompressed
448 * one. It also must reside (along with the line length buffer) in
449 * stolen memory.
450 *
451 * We need to enable/disable FBC on a global basis.
452 */
453 void intel_update_fbc(struct drm_device *dev)
454 {
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 struct drm_crtc *crtc = NULL, *tmp_crtc;
457 struct intel_crtc *intel_crtc;
458 struct drm_framebuffer *fb;
459 struct intel_framebuffer *intel_fb;
460 struct drm_i915_gem_object *obj;
461 const struct drm_display_mode *adjusted_mode;
462 unsigned int max_width, max_height;
463
464 if (!I915_HAS_FBC(dev)) {
465 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
466 return;
467 }
468
469 if (!i915_powersave) {
470 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
471 DRM_DEBUG_KMS("fbc disabled per module param\n");
472 return;
473 }
474
475 /*
476 * If FBC is already on, we just have to verify that we can
477 * keep it that way...
478 * Need to disable if:
479 * - more than one pipe is active
480 * - changing FBC params (stride, fence, mode)
481 * - new fb is too large to fit in compressed buffer
482 * - going to an unsupported config (interlace, pixel multiply, etc.)
483 */
484 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
485 if (intel_crtc_active(tmp_crtc) &&
486 to_intel_crtc(tmp_crtc)->primary_enabled) {
487 if (crtc) {
488 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
489 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
490 goto out_disable;
491 }
492 crtc = tmp_crtc;
493 }
494 }
495
496 if (!crtc || crtc->fb == NULL) {
497 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
498 DRM_DEBUG_KMS("no output, disabling\n");
499 goto out_disable;
500 }
501
502 intel_crtc = to_intel_crtc(crtc);
503 fb = crtc->fb;
504 intel_fb = to_intel_framebuffer(fb);
505 obj = intel_fb->obj;
506 adjusted_mode = &intel_crtc->config.adjusted_mode;
507
508 if (i915_enable_fbc < 0 &&
509 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
510 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
511 DRM_DEBUG_KMS("disabled per chip default\n");
512 goto out_disable;
513 }
514 if (!i915_enable_fbc) {
515 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
516 DRM_DEBUG_KMS("fbc disabled per module param\n");
517 goto out_disable;
518 }
519 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
520 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
521 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
522 DRM_DEBUG_KMS("mode incompatible with compression, "
523 "disabling\n");
524 goto out_disable;
525 }
526
527 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
528 max_width = 4096;
529 max_height = 2048;
530 } else {
531 max_width = 2048;
532 max_height = 1536;
533 }
534 if (intel_crtc->config.pipe_src_w > max_width ||
535 intel_crtc->config.pipe_src_h > max_height) {
536 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
537 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
538 goto out_disable;
539 }
540 if ((INTEL_INFO(dev)->gen < 4 || IS_HASWELL(dev)) &&
541 intel_crtc->plane != PLANE_A) {
542 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
543 DRM_DEBUG_KMS("plane not A, disabling compression\n");
544 goto out_disable;
545 }
546
547 /* The use of a CPU fence is mandatory in order to detect writes
548 * by the CPU to the scanout and trigger updates to the FBC.
549 */
550 if (obj->tiling_mode != I915_TILING_X ||
551 obj->fence_reg == I915_FENCE_REG_NONE) {
552 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
553 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
554 goto out_disable;
555 }
556
557 /* If the kernel debugger is active, always disable compression */
558 if (in_dbg_master())
559 goto out_disable;
560
561 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
562 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
563 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
564 goto out_disable;
565 }
566
567 /* If the scanout has not changed, don't modify the FBC settings.
568 * Note that we make the fundamental assumption that the fb->obj
569 * cannot be unpinned (and have its GTT offset and fence revoked)
570 * without first being decoupled from the scanout and FBC disabled.
571 */
572 if (dev_priv->fbc.plane == intel_crtc->plane &&
573 dev_priv->fbc.fb_id == fb->base.id &&
574 dev_priv->fbc.y == crtc->y)
575 return;
576
577 if (intel_fbc_enabled(dev)) {
578 /* We update FBC along two paths, after changing fb/crtc
579 * configuration (modeswitching) and after page-flipping
580 * finishes. For the latter, we know that not only did
581 * we disable the FBC at the start of the page-flip
582 * sequence, but also more than one vblank has passed.
583 *
584 * For the former case of modeswitching, it is possible
585 * to switch between two FBC valid configurations
586 * instantaneously so we do need to disable the FBC
587 * before we can modify its control registers. We also
588 * have to wait for the next vblank for that to take
589 * effect. However, since we delay enabling FBC we can
590 * assume that a vblank has passed since disabling and
591 * that we can safely alter the registers in the deferred
592 * callback.
593 *
594 * In the scenario that we go from a valid to invalid
595 * and then back to valid FBC configuration we have
596 * no strict enforcement that a vblank occurred since
597 * disabling the FBC. However, along all current pipe
598 * disabling paths we do need to wait for a vblank at
599 * some point. And we wait before enabling FBC anyway.
600 */
601 DRM_DEBUG_KMS("disabling active FBC for update\n");
602 intel_disable_fbc(dev);
603 }
604
605 intel_enable_fbc(crtc);
606 dev_priv->fbc.no_fbc_reason = FBC_OK;
607 return;
608
609 out_disable:
610 /* Multiple disables should be harmless */
611 if (intel_fbc_enabled(dev)) {
612 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
613 intel_disable_fbc(dev);
614 }
615 i915_gem_stolen_cleanup_compression(dev);
616 }
617
618 static void i915_pineview_get_mem_freq(struct drm_device *dev)
619 {
620 drm_i915_private_t *dev_priv = dev->dev_private;
621 u32 tmp;
622
623 tmp = I915_READ(CLKCFG);
624
625 switch (tmp & CLKCFG_FSB_MASK) {
626 case CLKCFG_FSB_533:
627 dev_priv->fsb_freq = 533; /* 133*4 */
628 break;
629 case CLKCFG_FSB_800:
630 dev_priv->fsb_freq = 800; /* 200*4 */
631 break;
632 case CLKCFG_FSB_667:
633 dev_priv->fsb_freq = 667; /* 167*4 */
634 break;
635 case CLKCFG_FSB_400:
636 dev_priv->fsb_freq = 400; /* 100*4 */
637 break;
638 }
639
640 switch (tmp & CLKCFG_MEM_MASK) {
641 case CLKCFG_MEM_533:
642 dev_priv->mem_freq = 533;
643 break;
644 case CLKCFG_MEM_667:
645 dev_priv->mem_freq = 667;
646 break;
647 case CLKCFG_MEM_800:
648 dev_priv->mem_freq = 800;
649 break;
650 }
651
652 /* detect pineview DDR3 setting */
653 tmp = I915_READ(CSHRDDR3CTL);
654 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
655 }
656
657 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
658 {
659 drm_i915_private_t *dev_priv = dev->dev_private;
660 u16 ddrpll, csipll;
661
662 ddrpll = I915_READ16(DDRMPLL1);
663 csipll = I915_READ16(CSIPLL0);
664
665 switch (ddrpll & 0xff) {
666 case 0xc:
667 dev_priv->mem_freq = 800;
668 break;
669 case 0x10:
670 dev_priv->mem_freq = 1066;
671 break;
672 case 0x14:
673 dev_priv->mem_freq = 1333;
674 break;
675 case 0x18:
676 dev_priv->mem_freq = 1600;
677 break;
678 default:
679 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
680 ddrpll & 0xff);
681 dev_priv->mem_freq = 0;
682 break;
683 }
684
685 dev_priv->ips.r_t = dev_priv->mem_freq;
686
687 switch (csipll & 0x3ff) {
688 case 0x00c:
689 dev_priv->fsb_freq = 3200;
690 break;
691 case 0x00e:
692 dev_priv->fsb_freq = 3733;
693 break;
694 case 0x010:
695 dev_priv->fsb_freq = 4266;
696 break;
697 case 0x012:
698 dev_priv->fsb_freq = 4800;
699 break;
700 case 0x014:
701 dev_priv->fsb_freq = 5333;
702 break;
703 case 0x016:
704 dev_priv->fsb_freq = 5866;
705 break;
706 case 0x018:
707 dev_priv->fsb_freq = 6400;
708 break;
709 default:
710 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
711 csipll & 0x3ff);
712 dev_priv->fsb_freq = 0;
713 break;
714 }
715
716 if (dev_priv->fsb_freq == 3200) {
717 dev_priv->ips.c_m = 0;
718 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
719 dev_priv->ips.c_m = 1;
720 } else {
721 dev_priv->ips.c_m = 2;
722 }
723 }
724
725 static const struct cxsr_latency cxsr_latency_table[] = {
726 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
727 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
728 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
729 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
730 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
731
732 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
733 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
734 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
735 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
736 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
737
738 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
739 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
740 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
741 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
742 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
743
744 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
745 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
746 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
747 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
748 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
749
750 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
751 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
752 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
753 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
754 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
755
756 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
757 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
758 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
759 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
760 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
761 };
762
763 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
764 int is_ddr3,
765 int fsb,
766 int mem)
767 {
768 const struct cxsr_latency *latency;
769 int i;
770
771 if (fsb == 0 || mem == 0)
772 return NULL;
773
774 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
775 latency = &cxsr_latency_table[i];
776 if (is_desktop == latency->is_desktop &&
777 is_ddr3 == latency->is_ddr3 &&
778 fsb == latency->fsb_freq && mem == latency->mem_freq)
779 return latency;
780 }
781
782 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
783
784 return NULL;
785 }
786
787 static void pineview_disable_cxsr(struct drm_device *dev)
788 {
789 struct drm_i915_private *dev_priv = dev->dev_private;
790
791 /* deactivate cxsr */
792 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
793 }
794
795 /*
796 * Latency for FIFO fetches is dependent on several factors:
797 * - memory configuration (speed, channels)
798 * - chipset
799 * - current MCH state
800 * It can be fairly high in some situations, so here we assume a fairly
801 * pessimal value. It's a tradeoff between extra memory fetches (if we
802 * set this value too high, the FIFO will fetch frequently to stay full)
803 * and power consumption (set it too low to save power and we might see
804 * FIFO underruns and display "flicker").
805 *
806 * A value of 5us seems to be a good balance; safe for very low end
807 * platforms but not overly aggressive on lower latency configs.
808 */
809 static const int latency_ns = 5000;
810
811 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
812 {
813 struct drm_i915_private *dev_priv = dev->dev_private;
814 uint32_t dsparb = I915_READ(DSPARB);
815 int size;
816
817 size = dsparb & 0x7f;
818 if (plane)
819 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
820
821 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
822 plane ? "B" : "A", size);
823
824 return size;
825 }
826
827 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
828 {
829 struct drm_i915_private *dev_priv = dev->dev_private;
830 uint32_t dsparb = I915_READ(DSPARB);
831 int size;
832
833 size = dsparb & 0x1ff;
834 if (plane)
835 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
836 size >>= 1; /* Convert to cachelines */
837
838 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
839 plane ? "B" : "A", size);
840
841 return size;
842 }
843
844 static int i845_get_fifo_size(struct drm_device *dev, int plane)
845 {
846 struct drm_i915_private *dev_priv = dev->dev_private;
847 uint32_t dsparb = I915_READ(DSPARB);
848 int size;
849
850 size = dsparb & 0x7f;
851 size >>= 2; /* Convert to cachelines */
852
853 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
854 plane ? "B" : "A",
855 size);
856
857 return size;
858 }
859
860 static int i830_get_fifo_size(struct drm_device *dev, int plane)
861 {
862 struct drm_i915_private *dev_priv = dev->dev_private;
863 uint32_t dsparb = I915_READ(DSPARB);
864 int size;
865
866 size = dsparb & 0x7f;
867 size >>= 1; /* Convert to cachelines */
868
869 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
870 plane ? "B" : "A", size);
871
872 return size;
873 }
874
875 /* Pineview has different values for various configs */
876 static const struct intel_watermark_params pineview_display_wm = {
877 PINEVIEW_DISPLAY_FIFO,
878 PINEVIEW_MAX_WM,
879 PINEVIEW_DFT_WM,
880 PINEVIEW_GUARD_WM,
881 PINEVIEW_FIFO_LINE_SIZE
882 };
883 static const struct intel_watermark_params pineview_display_hplloff_wm = {
884 PINEVIEW_DISPLAY_FIFO,
885 PINEVIEW_MAX_WM,
886 PINEVIEW_DFT_HPLLOFF_WM,
887 PINEVIEW_GUARD_WM,
888 PINEVIEW_FIFO_LINE_SIZE
889 };
890 static const struct intel_watermark_params pineview_cursor_wm = {
891 PINEVIEW_CURSOR_FIFO,
892 PINEVIEW_CURSOR_MAX_WM,
893 PINEVIEW_CURSOR_DFT_WM,
894 PINEVIEW_CURSOR_GUARD_WM,
895 PINEVIEW_FIFO_LINE_SIZE,
896 };
897 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
898 PINEVIEW_CURSOR_FIFO,
899 PINEVIEW_CURSOR_MAX_WM,
900 PINEVIEW_CURSOR_DFT_WM,
901 PINEVIEW_CURSOR_GUARD_WM,
902 PINEVIEW_FIFO_LINE_SIZE
903 };
904 static const struct intel_watermark_params g4x_wm_info = {
905 G4X_FIFO_SIZE,
906 G4X_MAX_WM,
907 G4X_MAX_WM,
908 2,
909 G4X_FIFO_LINE_SIZE,
910 };
911 static const struct intel_watermark_params g4x_cursor_wm_info = {
912 I965_CURSOR_FIFO,
913 I965_CURSOR_MAX_WM,
914 I965_CURSOR_DFT_WM,
915 2,
916 G4X_FIFO_LINE_SIZE,
917 };
918 static const struct intel_watermark_params valleyview_wm_info = {
919 VALLEYVIEW_FIFO_SIZE,
920 VALLEYVIEW_MAX_WM,
921 VALLEYVIEW_MAX_WM,
922 2,
923 G4X_FIFO_LINE_SIZE,
924 };
925 static const struct intel_watermark_params valleyview_cursor_wm_info = {
926 I965_CURSOR_FIFO,
927 VALLEYVIEW_CURSOR_MAX_WM,
928 I965_CURSOR_DFT_WM,
929 2,
930 G4X_FIFO_LINE_SIZE,
931 };
932 static const struct intel_watermark_params i965_cursor_wm_info = {
933 I965_CURSOR_FIFO,
934 I965_CURSOR_MAX_WM,
935 I965_CURSOR_DFT_WM,
936 2,
937 I915_FIFO_LINE_SIZE,
938 };
939 static const struct intel_watermark_params i945_wm_info = {
940 I945_FIFO_SIZE,
941 I915_MAX_WM,
942 1,
943 2,
944 I915_FIFO_LINE_SIZE
945 };
946 static const struct intel_watermark_params i915_wm_info = {
947 I915_FIFO_SIZE,
948 I915_MAX_WM,
949 1,
950 2,
951 I915_FIFO_LINE_SIZE
952 };
953 static const struct intel_watermark_params i855_wm_info = {
954 I855GM_FIFO_SIZE,
955 I915_MAX_WM,
956 1,
957 2,
958 I830_FIFO_LINE_SIZE
959 };
960 static const struct intel_watermark_params i830_wm_info = {
961 I830_FIFO_SIZE,
962 I915_MAX_WM,
963 1,
964 2,
965 I830_FIFO_LINE_SIZE
966 };
967
968 static const struct intel_watermark_params ironlake_display_wm_info = {
969 ILK_DISPLAY_FIFO,
970 ILK_DISPLAY_MAXWM,
971 ILK_DISPLAY_DFTWM,
972 2,
973 ILK_FIFO_LINE_SIZE
974 };
975 static const struct intel_watermark_params ironlake_cursor_wm_info = {
976 ILK_CURSOR_FIFO,
977 ILK_CURSOR_MAXWM,
978 ILK_CURSOR_DFTWM,
979 2,
980 ILK_FIFO_LINE_SIZE
981 };
982 static const struct intel_watermark_params ironlake_display_srwm_info = {
983 ILK_DISPLAY_SR_FIFO,
984 ILK_DISPLAY_MAX_SRWM,
985 ILK_DISPLAY_DFT_SRWM,
986 2,
987 ILK_FIFO_LINE_SIZE
988 };
989 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
990 ILK_CURSOR_SR_FIFO,
991 ILK_CURSOR_MAX_SRWM,
992 ILK_CURSOR_DFT_SRWM,
993 2,
994 ILK_FIFO_LINE_SIZE
995 };
996
997 static const struct intel_watermark_params sandybridge_display_wm_info = {
998 SNB_DISPLAY_FIFO,
999 SNB_DISPLAY_MAXWM,
1000 SNB_DISPLAY_DFTWM,
1001 2,
1002 SNB_FIFO_LINE_SIZE
1003 };
1004 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1005 SNB_CURSOR_FIFO,
1006 SNB_CURSOR_MAXWM,
1007 SNB_CURSOR_DFTWM,
1008 2,
1009 SNB_FIFO_LINE_SIZE
1010 };
1011 static const struct intel_watermark_params sandybridge_display_srwm_info = {
1012 SNB_DISPLAY_SR_FIFO,
1013 SNB_DISPLAY_MAX_SRWM,
1014 SNB_DISPLAY_DFT_SRWM,
1015 2,
1016 SNB_FIFO_LINE_SIZE
1017 };
1018 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1019 SNB_CURSOR_SR_FIFO,
1020 SNB_CURSOR_MAX_SRWM,
1021 SNB_CURSOR_DFT_SRWM,
1022 2,
1023 SNB_FIFO_LINE_SIZE
1024 };
1025
1026
1027 /**
1028 * intel_calculate_wm - calculate watermark level
1029 * @clock_in_khz: pixel clock
1030 * @wm: chip FIFO params
1031 * @pixel_size: display pixel size
1032 * @latency_ns: memory latency for the platform
1033 *
1034 * Calculate the watermark level (the level at which the display plane will
1035 * start fetching from memory again). Each chip has a different display
1036 * FIFO size and allocation, so the caller needs to figure that out and pass
1037 * in the correct intel_watermark_params structure.
1038 *
1039 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1040 * on the pixel size. When it reaches the watermark level, it'll start
1041 * fetching FIFO line sized based chunks from memory until the FIFO fills
1042 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1043 * will occur, and a display engine hang could result.
1044 */
1045 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1046 const struct intel_watermark_params *wm,
1047 int fifo_size,
1048 int pixel_size,
1049 unsigned long latency_ns)
1050 {
1051 long entries_required, wm_size;
1052
1053 /*
1054 * Note: we need to make sure we don't overflow for various clock &
1055 * latency values.
1056 * clocks go from a few thousand to several hundred thousand.
1057 * latency is usually a few thousand
1058 */
1059 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1060 1000;
1061 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1062
1063 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1064
1065 wm_size = fifo_size - (entries_required + wm->guard_size);
1066
1067 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1068
1069 /* Don't promote wm_size to unsigned... */
1070 if (wm_size > (long)wm->max_wm)
1071 wm_size = wm->max_wm;
1072 if (wm_size <= 0)
1073 wm_size = wm->default_wm;
1074 return wm_size;
1075 }
1076
1077 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1078 {
1079 struct drm_crtc *crtc, *enabled = NULL;
1080
1081 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1082 if (intel_crtc_active(crtc)) {
1083 if (enabled)
1084 return NULL;
1085 enabled = crtc;
1086 }
1087 }
1088
1089 return enabled;
1090 }
1091
1092 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1093 {
1094 struct drm_device *dev = unused_crtc->dev;
1095 struct drm_i915_private *dev_priv = dev->dev_private;
1096 struct drm_crtc *crtc;
1097 const struct cxsr_latency *latency;
1098 u32 reg;
1099 unsigned long wm;
1100
1101 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1102 dev_priv->fsb_freq, dev_priv->mem_freq);
1103 if (!latency) {
1104 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1105 pineview_disable_cxsr(dev);
1106 return;
1107 }
1108
1109 crtc = single_enabled_crtc(dev);
1110 if (crtc) {
1111 const struct drm_display_mode *adjusted_mode;
1112 int pixel_size = crtc->fb->bits_per_pixel / 8;
1113 int clock;
1114
1115 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1116 clock = adjusted_mode->crtc_clock;
1117
1118 /* Display SR */
1119 wm = intel_calculate_wm(clock, &pineview_display_wm,
1120 pineview_display_wm.fifo_size,
1121 pixel_size, latency->display_sr);
1122 reg = I915_READ(DSPFW1);
1123 reg &= ~DSPFW_SR_MASK;
1124 reg |= wm << DSPFW_SR_SHIFT;
1125 I915_WRITE(DSPFW1, reg);
1126 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1127
1128 /* cursor SR */
1129 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1130 pineview_display_wm.fifo_size,
1131 pixel_size, latency->cursor_sr);
1132 reg = I915_READ(DSPFW3);
1133 reg &= ~DSPFW_CURSOR_SR_MASK;
1134 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1135 I915_WRITE(DSPFW3, reg);
1136
1137 /* Display HPLL off SR */
1138 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1139 pineview_display_hplloff_wm.fifo_size,
1140 pixel_size, latency->display_hpll_disable);
1141 reg = I915_READ(DSPFW3);
1142 reg &= ~DSPFW_HPLL_SR_MASK;
1143 reg |= wm & DSPFW_HPLL_SR_MASK;
1144 I915_WRITE(DSPFW3, reg);
1145
1146 /* cursor HPLL off SR */
1147 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1148 pineview_display_hplloff_wm.fifo_size,
1149 pixel_size, latency->cursor_hpll_disable);
1150 reg = I915_READ(DSPFW3);
1151 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1152 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1153 I915_WRITE(DSPFW3, reg);
1154 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1155
1156 /* activate cxsr */
1157 I915_WRITE(DSPFW3,
1158 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1159 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1160 } else {
1161 pineview_disable_cxsr(dev);
1162 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1163 }
1164 }
1165
1166 static bool g4x_compute_wm0(struct drm_device *dev,
1167 int plane,
1168 const struct intel_watermark_params *display,
1169 int display_latency_ns,
1170 const struct intel_watermark_params *cursor,
1171 int cursor_latency_ns,
1172 int *plane_wm,
1173 int *cursor_wm)
1174 {
1175 struct drm_crtc *crtc;
1176 const struct drm_display_mode *adjusted_mode;
1177 int htotal, hdisplay, clock, pixel_size;
1178 int line_time_us, line_count;
1179 int entries, tlb_miss;
1180
1181 crtc = intel_get_crtc_for_plane(dev, plane);
1182 if (!intel_crtc_active(crtc)) {
1183 *cursor_wm = cursor->guard_size;
1184 *plane_wm = display->guard_size;
1185 return false;
1186 }
1187
1188 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1189 clock = adjusted_mode->crtc_clock;
1190 htotal = adjusted_mode->htotal;
1191 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1192 pixel_size = crtc->fb->bits_per_pixel / 8;
1193
1194 /* Use the small buffer method to calculate plane watermark */
1195 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1196 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1197 if (tlb_miss > 0)
1198 entries += tlb_miss;
1199 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1200 *plane_wm = entries + display->guard_size;
1201 if (*plane_wm > (int)display->max_wm)
1202 *plane_wm = display->max_wm;
1203
1204 /* Use the large buffer method to calculate cursor watermark */
1205 line_time_us = ((htotal * 1000) / clock);
1206 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1207 entries = line_count * 64 * pixel_size;
1208 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1209 if (tlb_miss > 0)
1210 entries += tlb_miss;
1211 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1212 *cursor_wm = entries + cursor->guard_size;
1213 if (*cursor_wm > (int)cursor->max_wm)
1214 *cursor_wm = (int)cursor->max_wm;
1215
1216 return true;
1217 }
1218
1219 /*
1220 * Check the wm result.
1221 *
1222 * If any calculated watermark values is larger than the maximum value that
1223 * can be programmed into the associated watermark register, that watermark
1224 * must be disabled.
1225 */
1226 static bool g4x_check_srwm(struct drm_device *dev,
1227 int display_wm, int cursor_wm,
1228 const struct intel_watermark_params *display,
1229 const struct intel_watermark_params *cursor)
1230 {
1231 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1232 display_wm, cursor_wm);
1233
1234 if (display_wm > display->max_wm) {
1235 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1236 display_wm, display->max_wm);
1237 return false;
1238 }
1239
1240 if (cursor_wm > cursor->max_wm) {
1241 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1242 cursor_wm, cursor->max_wm);
1243 return false;
1244 }
1245
1246 if (!(display_wm || cursor_wm)) {
1247 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1248 return false;
1249 }
1250
1251 return true;
1252 }
1253
1254 static bool g4x_compute_srwm(struct drm_device *dev,
1255 int plane,
1256 int latency_ns,
1257 const struct intel_watermark_params *display,
1258 const struct intel_watermark_params *cursor,
1259 int *display_wm, int *cursor_wm)
1260 {
1261 struct drm_crtc *crtc;
1262 const struct drm_display_mode *adjusted_mode;
1263 int hdisplay, htotal, pixel_size, clock;
1264 unsigned long line_time_us;
1265 int line_count, line_size;
1266 int small, large;
1267 int entries;
1268
1269 if (!latency_ns) {
1270 *display_wm = *cursor_wm = 0;
1271 return false;
1272 }
1273
1274 crtc = intel_get_crtc_for_plane(dev, plane);
1275 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1276 clock = adjusted_mode->crtc_clock;
1277 htotal = adjusted_mode->htotal;
1278 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1279 pixel_size = crtc->fb->bits_per_pixel / 8;
1280
1281 line_time_us = (htotal * 1000) / clock;
1282 line_count = (latency_ns / line_time_us + 1000) / 1000;
1283 line_size = hdisplay * pixel_size;
1284
1285 /* Use the minimum of the small and large buffer method for primary */
1286 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1287 large = line_count * line_size;
1288
1289 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1290 *display_wm = entries + display->guard_size;
1291
1292 /* calculate the self-refresh watermark for display cursor */
1293 entries = line_count * pixel_size * 64;
1294 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1295 *cursor_wm = entries + cursor->guard_size;
1296
1297 return g4x_check_srwm(dev,
1298 *display_wm, *cursor_wm,
1299 display, cursor);
1300 }
1301
1302 static bool vlv_compute_drain_latency(struct drm_device *dev,
1303 int plane,
1304 int *plane_prec_mult,
1305 int *plane_dl,
1306 int *cursor_prec_mult,
1307 int *cursor_dl)
1308 {
1309 struct drm_crtc *crtc;
1310 int clock, pixel_size;
1311 int entries;
1312
1313 crtc = intel_get_crtc_for_plane(dev, plane);
1314 if (!intel_crtc_active(crtc))
1315 return false;
1316
1317 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1318 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1319
1320 entries = (clock / 1000) * pixel_size;
1321 *plane_prec_mult = (entries > 256) ?
1322 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1323 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1324 pixel_size);
1325
1326 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1327 *cursor_prec_mult = (entries > 256) ?
1328 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1329 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1330
1331 return true;
1332 }
1333
1334 /*
1335 * Update drain latency registers of memory arbiter
1336 *
1337 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1338 * to be programmed. Each plane has a drain latency multiplier and a drain
1339 * latency value.
1340 */
1341
1342 static void vlv_update_drain_latency(struct drm_device *dev)
1343 {
1344 struct drm_i915_private *dev_priv = dev->dev_private;
1345 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1346 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1347 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1348 either 16 or 32 */
1349
1350 /* For plane A, Cursor A */
1351 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1352 &cursor_prec_mult, &cursora_dl)) {
1353 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1354 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1355 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1356 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1357
1358 I915_WRITE(VLV_DDL1, cursora_prec |
1359 (cursora_dl << DDL_CURSORA_SHIFT) |
1360 planea_prec | planea_dl);
1361 }
1362
1363 /* For plane B, Cursor B */
1364 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1365 &cursor_prec_mult, &cursorb_dl)) {
1366 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1367 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1368 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1369 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1370
1371 I915_WRITE(VLV_DDL2, cursorb_prec |
1372 (cursorb_dl << DDL_CURSORB_SHIFT) |
1373 planeb_prec | planeb_dl);
1374 }
1375 }
1376
1377 #define single_plane_enabled(mask) is_power_of_2(mask)
1378
1379 static void valleyview_update_wm(struct drm_crtc *crtc)
1380 {
1381 struct drm_device *dev = crtc->dev;
1382 static const int sr_latency_ns = 12000;
1383 struct drm_i915_private *dev_priv = dev->dev_private;
1384 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1385 int plane_sr, cursor_sr;
1386 int ignore_plane_sr, ignore_cursor_sr;
1387 unsigned int enabled = 0;
1388
1389 vlv_update_drain_latency(dev);
1390
1391 if (g4x_compute_wm0(dev, PIPE_A,
1392 &valleyview_wm_info, latency_ns,
1393 &valleyview_cursor_wm_info, latency_ns,
1394 &planea_wm, &cursora_wm))
1395 enabled |= 1 << PIPE_A;
1396
1397 if (g4x_compute_wm0(dev, PIPE_B,
1398 &valleyview_wm_info, latency_ns,
1399 &valleyview_cursor_wm_info, latency_ns,
1400 &planeb_wm, &cursorb_wm))
1401 enabled |= 1 << PIPE_B;
1402
1403 if (single_plane_enabled(enabled) &&
1404 g4x_compute_srwm(dev, ffs(enabled) - 1,
1405 sr_latency_ns,
1406 &valleyview_wm_info,
1407 &valleyview_cursor_wm_info,
1408 &plane_sr, &ignore_cursor_sr) &&
1409 g4x_compute_srwm(dev, ffs(enabled) - 1,
1410 2*sr_latency_ns,
1411 &valleyview_wm_info,
1412 &valleyview_cursor_wm_info,
1413 &ignore_plane_sr, &cursor_sr)) {
1414 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1415 } else {
1416 I915_WRITE(FW_BLC_SELF_VLV,
1417 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1418 plane_sr = cursor_sr = 0;
1419 }
1420
1421 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1422 planea_wm, cursora_wm,
1423 planeb_wm, cursorb_wm,
1424 plane_sr, cursor_sr);
1425
1426 I915_WRITE(DSPFW1,
1427 (plane_sr << DSPFW_SR_SHIFT) |
1428 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1429 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1430 planea_wm);
1431 I915_WRITE(DSPFW2,
1432 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1433 (cursora_wm << DSPFW_CURSORA_SHIFT));
1434 I915_WRITE(DSPFW3,
1435 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1436 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1437 }
1438
1439 static void g4x_update_wm(struct drm_crtc *crtc)
1440 {
1441 struct drm_device *dev = crtc->dev;
1442 static const int sr_latency_ns = 12000;
1443 struct drm_i915_private *dev_priv = dev->dev_private;
1444 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1445 int plane_sr, cursor_sr;
1446 unsigned int enabled = 0;
1447
1448 if (g4x_compute_wm0(dev, PIPE_A,
1449 &g4x_wm_info, latency_ns,
1450 &g4x_cursor_wm_info, latency_ns,
1451 &planea_wm, &cursora_wm))
1452 enabled |= 1 << PIPE_A;
1453
1454 if (g4x_compute_wm0(dev, PIPE_B,
1455 &g4x_wm_info, latency_ns,
1456 &g4x_cursor_wm_info, latency_ns,
1457 &planeb_wm, &cursorb_wm))
1458 enabled |= 1 << PIPE_B;
1459
1460 if (single_plane_enabled(enabled) &&
1461 g4x_compute_srwm(dev, ffs(enabled) - 1,
1462 sr_latency_ns,
1463 &g4x_wm_info,
1464 &g4x_cursor_wm_info,
1465 &plane_sr, &cursor_sr)) {
1466 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1467 } else {
1468 I915_WRITE(FW_BLC_SELF,
1469 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1470 plane_sr = cursor_sr = 0;
1471 }
1472
1473 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1474 planea_wm, cursora_wm,
1475 planeb_wm, cursorb_wm,
1476 plane_sr, cursor_sr);
1477
1478 I915_WRITE(DSPFW1,
1479 (plane_sr << DSPFW_SR_SHIFT) |
1480 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1481 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1482 planea_wm);
1483 I915_WRITE(DSPFW2,
1484 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1485 (cursora_wm << DSPFW_CURSORA_SHIFT));
1486 /* HPLL off in SR has some issues on G4x... disable it */
1487 I915_WRITE(DSPFW3,
1488 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1489 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1490 }
1491
1492 static void i965_update_wm(struct drm_crtc *unused_crtc)
1493 {
1494 struct drm_device *dev = unused_crtc->dev;
1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 struct drm_crtc *crtc;
1497 int srwm = 1;
1498 int cursor_sr = 16;
1499
1500 /* Calc sr entries for one plane configs */
1501 crtc = single_enabled_crtc(dev);
1502 if (crtc) {
1503 /* self-refresh has much higher latency */
1504 static const int sr_latency_ns = 12000;
1505 const struct drm_display_mode *adjusted_mode =
1506 &to_intel_crtc(crtc)->config.adjusted_mode;
1507 int clock = adjusted_mode->crtc_clock;
1508 int htotal = adjusted_mode->htotal;
1509 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1510 int pixel_size = crtc->fb->bits_per_pixel / 8;
1511 unsigned long line_time_us;
1512 int entries;
1513
1514 line_time_us = ((htotal * 1000) / clock);
1515
1516 /* Use ns/us then divide to preserve precision */
1517 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1518 pixel_size * hdisplay;
1519 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1520 srwm = I965_FIFO_SIZE - entries;
1521 if (srwm < 0)
1522 srwm = 1;
1523 srwm &= 0x1ff;
1524 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1525 entries, srwm);
1526
1527 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1528 pixel_size * 64;
1529 entries = DIV_ROUND_UP(entries,
1530 i965_cursor_wm_info.cacheline_size);
1531 cursor_sr = i965_cursor_wm_info.fifo_size -
1532 (entries + i965_cursor_wm_info.guard_size);
1533
1534 if (cursor_sr > i965_cursor_wm_info.max_wm)
1535 cursor_sr = i965_cursor_wm_info.max_wm;
1536
1537 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1538 "cursor %d\n", srwm, cursor_sr);
1539
1540 if (IS_CRESTLINE(dev))
1541 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1542 } else {
1543 /* Turn off self refresh if both pipes are enabled */
1544 if (IS_CRESTLINE(dev))
1545 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1546 & ~FW_BLC_SELF_EN);
1547 }
1548
1549 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1550 srwm);
1551
1552 /* 965 has limitations... */
1553 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1554 (8 << 16) | (8 << 8) | (8 << 0));
1555 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1556 /* update cursor SR watermark */
1557 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1558 }
1559
1560 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1561 {
1562 struct drm_device *dev = unused_crtc->dev;
1563 struct drm_i915_private *dev_priv = dev->dev_private;
1564 const struct intel_watermark_params *wm_info;
1565 uint32_t fwater_lo;
1566 uint32_t fwater_hi;
1567 int cwm, srwm = 1;
1568 int fifo_size;
1569 int planea_wm, planeb_wm;
1570 struct drm_crtc *crtc, *enabled = NULL;
1571
1572 if (IS_I945GM(dev))
1573 wm_info = &i945_wm_info;
1574 else if (!IS_GEN2(dev))
1575 wm_info = &i915_wm_info;
1576 else
1577 wm_info = &i855_wm_info;
1578
1579 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1580 crtc = intel_get_crtc_for_plane(dev, 0);
1581 if (intel_crtc_active(crtc)) {
1582 const struct drm_display_mode *adjusted_mode;
1583 int cpp = crtc->fb->bits_per_pixel / 8;
1584 if (IS_GEN2(dev))
1585 cpp = 4;
1586
1587 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1588 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1589 wm_info, fifo_size, cpp,
1590 latency_ns);
1591 enabled = crtc;
1592 } else
1593 planea_wm = fifo_size - wm_info->guard_size;
1594
1595 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1596 crtc = intel_get_crtc_for_plane(dev, 1);
1597 if (intel_crtc_active(crtc)) {
1598 const struct drm_display_mode *adjusted_mode;
1599 int cpp = crtc->fb->bits_per_pixel / 8;
1600 if (IS_GEN2(dev))
1601 cpp = 4;
1602
1603 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1604 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1605 wm_info, fifo_size, cpp,
1606 latency_ns);
1607 if (enabled == NULL)
1608 enabled = crtc;
1609 else
1610 enabled = NULL;
1611 } else
1612 planeb_wm = fifo_size - wm_info->guard_size;
1613
1614 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1615
1616 /*
1617 * Overlay gets an aggressive default since video jitter is bad.
1618 */
1619 cwm = 2;
1620
1621 /* Play safe and disable self-refresh before adjusting watermarks. */
1622 if (IS_I945G(dev) || IS_I945GM(dev))
1623 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1624 else if (IS_I915GM(dev))
1625 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1626
1627 /* Calc sr entries for one plane configs */
1628 if (HAS_FW_BLC(dev) && enabled) {
1629 /* self-refresh has much higher latency */
1630 static const int sr_latency_ns = 6000;
1631 const struct drm_display_mode *adjusted_mode =
1632 &to_intel_crtc(enabled)->config.adjusted_mode;
1633 int clock = adjusted_mode->crtc_clock;
1634 int htotal = adjusted_mode->htotal;
1635 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1636 int pixel_size = enabled->fb->bits_per_pixel / 8;
1637 unsigned long line_time_us;
1638 int entries;
1639
1640 line_time_us = (htotal * 1000) / clock;
1641
1642 /* Use ns/us then divide to preserve precision */
1643 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1644 pixel_size * hdisplay;
1645 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1646 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1647 srwm = wm_info->fifo_size - entries;
1648 if (srwm < 0)
1649 srwm = 1;
1650
1651 if (IS_I945G(dev) || IS_I945GM(dev))
1652 I915_WRITE(FW_BLC_SELF,
1653 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1654 else if (IS_I915GM(dev))
1655 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1656 }
1657
1658 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1659 planea_wm, planeb_wm, cwm, srwm);
1660
1661 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1662 fwater_hi = (cwm & 0x1f);
1663
1664 /* Set request length to 8 cachelines per fetch */
1665 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1666 fwater_hi = fwater_hi | (1 << 8);
1667
1668 I915_WRITE(FW_BLC, fwater_lo);
1669 I915_WRITE(FW_BLC2, fwater_hi);
1670
1671 if (HAS_FW_BLC(dev)) {
1672 if (enabled) {
1673 if (IS_I945G(dev) || IS_I945GM(dev))
1674 I915_WRITE(FW_BLC_SELF,
1675 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1676 else if (IS_I915GM(dev))
1677 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1678 DRM_DEBUG_KMS("memory self refresh enabled\n");
1679 } else
1680 DRM_DEBUG_KMS("memory self refresh disabled\n");
1681 }
1682 }
1683
1684 static void i830_update_wm(struct drm_crtc *unused_crtc)
1685 {
1686 struct drm_device *dev = unused_crtc->dev;
1687 struct drm_i915_private *dev_priv = dev->dev_private;
1688 struct drm_crtc *crtc;
1689 const struct drm_display_mode *adjusted_mode;
1690 uint32_t fwater_lo;
1691 int planea_wm;
1692
1693 crtc = single_enabled_crtc(dev);
1694 if (crtc == NULL)
1695 return;
1696
1697 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1698 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1699 &i830_wm_info,
1700 dev_priv->display.get_fifo_size(dev, 0),
1701 4, latency_ns);
1702 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1703 fwater_lo |= (3<<8) | planea_wm;
1704
1705 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1706
1707 I915_WRITE(FW_BLC, fwater_lo);
1708 }
1709
1710 /*
1711 * Check the wm result.
1712 *
1713 * If any calculated watermark values is larger than the maximum value that
1714 * can be programmed into the associated watermark register, that watermark
1715 * must be disabled.
1716 */
1717 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1718 int fbc_wm, int display_wm, int cursor_wm,
1719 const struct intel_watermark_params *display,
1720 const struct intel_watermark_params *cursor)
1721 {
1722 struct drm_i915_private *dev_priv = dev->dev_private;
1723
1724 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1725 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1726
1727 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1728 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1729 fbc_wm, SNB_FBC_MAX_SRWM, level);
1730
1731 /* fbc has it's own way to disable FBC WM */
1732 I915_WRITE(DISP_ARB_CTL,
1733 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1734 return false;
1735 } else if (INTEL_INFO(dev)->gen >= 6) {
1736 /* enable FBC WM (except on ILK, where it must remain off) */
1737 I915_WRITE(DISP_ARB_CTL,
1738 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1739 }
1740
1741 if (display_wm > display->max_wm) {
1742 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1743 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1744 return false;
1745 }
1746
1747 if (cursor_wm > cursor->max_wm) {
1748 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1749 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1750 return false;
1751 }
1752
1753 if (!(fbc_wm || display_wm || cursor_wm)) {
1754 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1755 return false;
1756 }
1757
1758 return true;
1759 }
1760
1761 /*
1762 * Compute watermark values of WM[1-3],
1763 */
1764 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1765 int latency_ns,
1766 const struct intel_watermark_params *display,
1767 const struct intel_watermark_params *cursor,
1768 int *fbc_wm, int *display_wm, int *cursor_wm)
1769 {
1770 struct drm_crtc *crtc;
1771 const struct drm_display_mode *adjusted_mode;
1772 unsigned long line_time_us;
1773 int hdisplay, htotal, pixel_size, clock;
1774 int line_count, line_size;
1775 int small, large;
1776 int entries;
1777
1778 if (!latency_ns) {
1779 *fbc_wm = *display_wm = *cursor_wm = 0;
1780 return false;
1781 }
1782
1783 crtc = intel_get_crtc_for_plane(dev, plane);
1784 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1785 clock = adjusted_mode->crtc_clock;
1786 htotal = adjusted_mode->htotal;
1787 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1788 pixel_size = crtc->fb->bits_per_pixel / 8;
1789
1790 line_time_us = (htotal * 1000) / clock;
1791 line_count = (latency_ns / line_time_us + 1000) / 1000;
1792 line_size = hdisplay * pixel_size;
1793
1794 /* Use the minimum of the small and large buffer method for primary */
1795 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1796 large = line_count * line_size;
1797
1798 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1799 *display_wm = entries + display->guard_size;
1800
1801 /*
1802 * Spec says:
1803 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1804 */
1805 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1806
1807 /* calculate the self-refresh watermark for display cursor */
1808 entries = line_count * pixel_size * 64;
1809 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1810 *cursor_wm = entries + cursor->guard_size;
1811
1812 return ironlake_check_srwm(dev, level,
1813 *fbc_wm, *display_wm, *cursor_wm,
1814 display, cursor);
1815 }
1816
1817 static void ironlake_update_wm(struct drm_crtc *crtc)
1818 {
1819 struct drm_device *dev = crtc->dev;
1820 struct drm_i915_private *dev_priv = dev->dev_private;
1821 int fbc_wm, plane_wm, cursor_wm;
1822 unsigned int enabled;
1823
1824 enabled = 0;
1825 if (g4x_compute_wm0(dev, PIPE_A,
1826 &ironlake_display_wm_info,
1827 dev_priv->wm.pri_latency[0] * 100,
1828 &ironlake_cursor_wm_info,
1829 dev_priv->wm.cur_latency[0] * 100,
1830 &plane_wm, &cursor_wm)) {
1831 I915_WRITE(WM0_PIPEA_ILK,
1832 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1833 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1834 " plane %d, " "cursor: %d\n",
1835 plane_wm, cursor_wm);
1836 enabled |= 1 << PIPE_A;
1837 }
1838
1839 if (g4x_compute_wm0(dev, PIPE_B,
1840 &ironlake_display_wm_info,
1841 dev_priv->wm.pri_latency[0] * 100,
1842 &ironlake_cursor_wm_info,
1843 dev_priv->wm.cur_latency[0] * 100,
1844 &plane_wm, &cursor_wm)) {
1845 I915_WRITE(WM0_PIPEB_ILK,
1846 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1847 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1848 " plane %d, cursor: %d\n",
1849 plane_wm, cursor_wm);
1850 enabled |= 1 << PIPE_B;
1851 }
1852
1853 /*
1854 * Calculate and update the self-refresh watermark only when one
1855 * display plane is used.
1856 */
1857 I915_WRITE(WM3_LP_ILK, 0);
1858 I915_WRITE(WM2_LP_ILK, 0);
1859 I915_WRITE(WM1_LP_ILK, 0);
1860
1861 if (!single_plane_enabled(enabled))
1862 return;
1863 enabled = ffs(enabled) - 1;
1864
1865 /* WM1 */
1866 if (!ironlake_compute_srwm(dev, 1, enabled,
1867 dev_priv->wm.pri_latency[1] * 500,
1868 &ironlake_display_srwm_info,
1869 &ironlake_cursor_srwm_info,
1870 &fbc_wm, &plane_wm, &cursor_wm))
1871 return;
1872
1873 I915_WRITE(WM1_LP_ILK,
1874 WM1_LP_SR_EN |
1875 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1876 (fbc_wm << WM1_LP_FBC_SHIFT) |
1877 (plane_wm << WM1_LP_SR_SHIFT) |
1878 cursor_wm);
1879
1880 /* WM2 */
1881 if (!ironlake_compute_srwm(dev, 2, enabled,
1882 dev_priv->wm.pri_latency[2] * 500,
1883 &ironlake_display_srwm_info,
1884 &ironlake_cursor_srwm_info,
1885 &fbc_wm, &plane_wm, &cursor_wm))
1886 return;
1887
1888 I915_WRITE(WM2_LP_ILK,
1889 WM2_LP_EN |
1890 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1891 (fbc_wm << WM1_LP_FBC_SHIFT) |
1892 (plane_wm << WM1_LP_SR_SHIFT) |
1893 cursor_wm);
1894
1895 /*
1896 * WM3 is unsupported on ILK, probably because we don't have latency
1897 * data for that power state
1898 */
1899 }
1900
1901 static void sandybridge_update_wm(struct drm_crtc *crtc)
1902 {
1903 struct drm_device *dev = crtc->dev;
1904 struct drm_i915_private *dev_priv = dev->dev_private;
1905 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
1906 u32 val;
1907 int fbc_wm, plane_wm, cursor_wm;
1908 unsigned int enabled;
1909
1910 enabled = 0;
1911 if (g4x_compute_wm0(dev, PIPE_A,
1912 &sandybridge_display_wm_info, latency,
1913 &sandybridge_cursor_wm_info, latency,
1914 &plane_wm, &cursor_wm)) {
1915 val = I915_READ(WM0_PIPEA_ILK);
1916 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1917 I915_WRITE(WM0_PIPEA_ILK, val |
1918 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1919 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1920 " plane %d, " "cursor: %d\n",
1921 plane_wm, cursor_wm);
1922 enabled |= 1 << PIPE_A;
1923 }
1924
1925 if (g4x_compute_wm0(dev, PIPE_B,
1926 &sandybridge_display_wm_info, latency,
1927 &sandybridge_cursor_wm_info, latency,
1928 &plane_wm, &cursor_wm)) {
1929 val = I915_READ(WM0_PIPEB_ILK);
1930 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1931 I915_WRITE(WM0_PIPEB_ILK, val |
1932 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1933 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1934 " plane %d, cursor: %d\n",
1935 plane_wm, cursor_wm);
1936 enabled |= 1 << PIPE_B;
1937 }
1938
1939 /*
1940 * Calculate and update the self-refresh watermark only when one
1941 * display plane is used.
1942 *
1943 * SNB support 3 levels of watermark.
1944 *
1945 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1946 * and disabled in the descending order
1947 *
1948 */
1949 I915_WRITE(WM3_LP_ILK, 0);
1950 I915_WRITE(WM2_LP_ILK, 0);
1951 I915_WRITE(WM1_LP_ILK, 0);
1952
1953 if (!single_plane_enabled(enabled) ||
1954 dev_priv->sprite_scaling_enabled)
1955 return;
1956 enabled = ffs(enabled) - 1;
1957
1958 /* WM1 */
1959 if (!ironlake_compute_srwm(dev, 1, enabled,
1960 dev_priv->wm.pri_latency[1] * 500,
1961 &sandybridge_display_srwm_info,
1962 &sandybridge_cursor_srwm_info,
1963 &fbc_wm, &plane_wm, &cursor_wm))
1964 return;
1965
1966 I915_WRITE(WM1_LP_ILK,
1967 WM1_LP_SR_EN |
1968 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1969 (fbc_wm << WM1_LP_FBC_SHIFT) |
1970 (plane_wm << WM1_LP_SR_SHIFT) |
1971 cursor_wm);
1972
1973 /* WM2 */
1974 if (!ironlake_compute_srwm(dev, 2, enabled,
1975 dev_priv->wm.pri_latency[2] * 500,
1976 &sandybridge_display_srwm_info,
1977 &sandybridge_cursor_srwm_info,
1978 &fbc_wm, &plane_wm, &cursor_wm))
1979 return;
1980
1981 I915_WRITE(WM2_LP_ILK,
1982 WM2_LP_EN |
1983 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1984 (fbc_wm << WM1_LP_FBC_SHIFT) |
1985 (plane_wm << WM1_LP_SR_SHIFT) |
1986 cursor_wm);
1987
1988 /* WM3 */
1989 if (!ironlake_compute_srwm(dev, 3, enabled,
1990 dev_priv->wm.pri_latency[3] * 500,
1991 &sandybridge_display_srwm_info,
1992 &sandybridge_cursor_srwm_info,
1993 &fbc_wm, &plane_wm, &cursor_wm))
1994 return;
1995
1996 I915_WRITE(WM3_LP_ILK,
1997 WM3_LP_EN |
1998 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
1999 (fbc_wm << WM1_LP_FBC_SHIFT) |
2000 (plane_wm << WM1_LP_SR_SHIFT) |
2001 cursor_wm);
2002 }
2003
2004 static void ivybridge_update_wm(struct drm_crtc *crtc)
2005 {
2006 struct drm_device *dev = crtc->dev;
2007 struct drm_i915_private *dev_priv = dev->dev_private;
2008 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
2009 u32 val;
2010 int fbc_wm, plane_wm, cursor_wm;
2011 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
2012 unsigned int enabled;
2013
2014 enabled = 0;
2015 if (g4x_compute_wm0(dev, PIPE_A,
2016 &sandybridge_display_wm_info, latency,
2017 &sandybridge_cursor_wm_info, latency,
2018 &plane_wm, &cursor_wm)) {
2019 val = I915_READ(WM0_PIPEA_ILK);
2020 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2021 I915_WRITE(WM0_PIPEA_ILK, val |
2022 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2023 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2024 " plane %d, " "cursor: %d\n",
2025 plane_wm, cursor_wm);
2026 enabled |= 1 << PIPE_A;
2027 }
2028
2029 if (g4x_compute_wm0(dev, PIPE_B,
2030 &sandybridge_display_wm_info, latency,
2031 &sandybridge_cursor_wm_info, latency,
2032 &plane_wm, &cursor_wm)) {
2033 val = I915_READ(WM0_PIPEB_ILK);
2034 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2035 I915_WRITE(WM0_PIPEB_ILK, val |
2036 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2037 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2038 " plane %d, cursor: %d\n",
2039 plane_wm, cursor_wm);
2040 enabled |= 1 << PIPE_B;
2041 }
2042
2043 if (g4x_compute_wm0(dev, PIPE_C,
2044 &sandybridge_display_wm_info, latency,
2045 &sandybridge_cursor_wm_info, latency,
2046 &plane_wm, &cursor_wm)) {
2047 val = I915_READ(WM0_PIPEC_IVB);
2048 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2049 I915_WRITE(WM0_PIPEC_IVB, val |
2050 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2051 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2052 " plane %d, cursor: %d\n",
2053 plane_wm, cursor_wm);
2054 enabled |= 1 << PIPE_C;
2055 }
2056
2057 /*
2058 * Calculate and update the self-refresh watermark only when one
2059 * display plane is used.
2060 *
2061 * SNB support 3 levels of watermark.
2062 *
2063 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2064 * and disabled in the descending order
2065 *
2066 */
2067 I915_WRITE(WM3_LP_ILK, 0);
2068 I915_WRITE(WM2_LP_ILK, 0);
2069 I915_WRITE(WM1_LP_ILK, 0);
2070
2071 if (!single_plane_enabled(enabled) ||
2072 dev_priv->sprite_scaling_enabled)
2073 return;
2074 enabled = ffs(enabled) - 1;
2075
2076 /* WM1 */
2077 if (!ironlake_compute_srwm(dev, 1, enabled,
2078 dev_priv->wm.pri_latency[1] * 500,
2079 &sandybridge_display_srwm_info,
2080 &sandybridge_cursor_srwm_info,
2081 &fbc_wm, &plane_wm, &cursor_wm))
2082 return;
2083
2084 I915_WRITE(WM1_LP_ILK,
2085 WM1_LP_SR_EN |
2086 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
2087 (fbc_wm << WM1_LP_FBC_SHIFT) |
2088 (plane_wm << WM1_LP_SR_SHIFT) |
2089 cursor_wm);
2090
2091 /* WM2 */
2092 if (!ironlake_compute_srwm(dev, 2, enabled,
2093 dev_priv->wm.pri_latency[2] * 500,
2094 &sandybridge_display_srwm_info,
2095 &sandybridge_cursor_srwm_info,
2096 &fbc_wm, &plane_wm, &cursor_wm))
2097 return;
2098
2099 I915_WRITE(WM2_LP_ILK,
2100 WM2_LP_EN |
2101 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
2102 (fbc_wm << WM1_LP_FBC_SHIFT) |
2103 (plane_wm << WM1_LP_SR_SHIFT) |
2104 cursor_wm);
2105
2106 /* WM3, note we have to correct the cursor latency */
2107 if (!ironlake_compute_srwm(dev, 3, enabled,
2108 dev_priv->wm.pri_latency[3] * 500,
2109 &sandybridge_display_srwm_info,
2110 &sandybridge_cursor_srwm_info,
2111 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2112 !ironlake_compute_srwm(dev, 3, enabled,
2113 dev_priv->wm.cur_latency[3] * 500,
2114 &sandybridge_display_srwm_info,
2115 &sandybridge_cursor_srwm_info,
2116 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2117 return;
2118
2119 I915_WRITE(WM3_LP_ILK,
2120 WM3_LP_EN |
2121 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
2122 (fbc_wm << WM1_LP_FBC_SHIFT) |
2123 (plane_wm << WM1_LP_SR_SHIFT) |
2124 cursor_wm);
2125 }
2126
2127 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2128 struct drm_crtc *crtc)
2129 {
2130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2131 uint32_t pixel_rate;
2132
2133 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
2134
2135 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2136 * adjust the pixel_rate here. */
2137
2138 if (intel_crtc->config.pch_pfit.enabled) {
2139 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2140 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
2141
2142 pipe_w = intel_crtc->config.pipe_src_w;
2143 pipe_h = intel_crtc->config.pipe_src_h;
2144 pfit_w = (pfit_size >> 16) & 0xFFFF;
2145 pfit_h = pfit_size & 0xFFFF;
2146 if (pipe_w < pfit_w)
2147 pipe_w = pfit_w;
2148 if (pipe_h < pfit_h)
2149 pipe_h = pfit_h;
2150
2151 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2152 pfit_w * pfit_h);
2153 }
2154
2155 return pixel_rate;
2156 }
2157
2158 /* latency must be in 0.1us units. */
2159 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2160 uint32_t latency)
2161 {
2162 uint64_t ret;
2163
2164 if (WARN(latency == 0, "Latency value missing\n"))
2165 return UINT_MAX;
2166
2167 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2168 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2169
2170 return ret;
2171 }
2172
2173 /* latency must be in 0.1us units. */
2174 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2175 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2176 uint32_t latency)
2177 {
2178 uint32_t ret;
2179
2180 if (WARN(latency == 0, "Latency value missing\n"))
2181 return UINT_MAX;
2182
2183 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2184 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2185 ret = DIV_ROUND_UP(ret, 64) + 2;
2186 return ret;
2187 }
2188
2189 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2190 uint8_t bytes_per_pixel)
2191 {
2192 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2193 }
2194
2195 struct hsw_pipe_wm_parameters {
2196 bool active;
2197 uint32_t pipe_htotal;
2198 uint32_t pixel_rate;
2199 struct intel_plane_wm_parameters pri;
2200 struct intel_plane_wm_parameters spr;
2201 struct intel_plane_wm_parameters cur;
2202 };
2203
2204 struct hsw_wm_maximums {
2205 uint16_t pri;
2206 uint16_t spr;
2207 uint16_t cur;
2208 uint16_t fbc;
2209 };
2210
2211 /* used in computing the new watermarks state */
2212 struct intel_wm_config {
2213 unsigned int num_pipes_active;
2214 bool sprites_enabled;
2215 bool sprites_scaled;
2216 };
2217
2218 /*
2219 * For both WM_PIPE and WM_LP.
2220 * mem_value must be in 0.1us units.
2221 */
2222 static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
2223 uint32_t mem_value,
2224 bool is_lp)
2225 {
2226 uint32_t method1, method2;
2227
2228 if (!params->active || !params->pri.enabled)
2229 return 0;
2230
2231 method1 = ilk_wm_method1(params->pixel_rate,
2232 params->pri.bytes_per_pixel,
2233 mem_value);
2234
2235 if (!is_lp)
2236 return method1;
2237
2238 method2 = ilk_wm_method2(params->pixel_rate,
2239 params->pipe_htotal,
2240 params->pri.horiz_pixels,
2241 params->pri.bytes_per_pixel,
2242 mem_value);
2243
2244 return min(method1, method2);
2245 }
2246
2247 /*
2248 * For both WM_PIPE and WM_LP.
2249 * mem_value must be in 0.1us units.
2250 */
2251 static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
2252 uint32_t mem_value)
2253 {
2254 uint32_t method1, method2;
2255
2256 if (!params->active || !params->spr.enabled)
2257 return 0;
2258
2259 method1 = ilk_wm_method1(params->pixel_rate,
2260 params->spr.bytes_per_pixel,
2261 mem_value);
2262 method2 = ilk_wm_method2(params->pixel_rate,
2263 params->pipe_htotal,
2264 params->spr.horiz_pixels,
2265 params->spr.bytes_per_pixel,
2266 mem_value);
2267 return min(method1, method2);
2268 }
2269
2270 /*
2271 * For both WM_PIPE and WM_LP.
2272 * mem_value must be in 0.1us units.
2273 */
2274 static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
2275 uint32_t mem_value)
2276 {
2277 if (!params->active || !params->cur.enabled)
2278 return 0;
2279
2280 return ilk_wm_method2(params->pixel_rate,
2281 params->pipe_htotal,
2282 params->cur.horiz_pixels,
2283 params->cur.bytes_per_pixel,
2284 mem_value);
2285 }
2286
2287 /* Only for WM_LP. */
2288 static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
2289 uint32_t pri_val)
2290 {
2291 if (!params->active || !params->pri.enabled)
2292 return 0;
2293
2294 return ilk_wm_fbc(pri_val,
2295 params->pri.horiz_pixels,
2296 params->pri.bytes_per_pixel);
2297 }
2298
2299 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2300 {
2301 if (INTEL_INFO(dev)->gen >= 8)
2302 return 3072;
2303 else if (INTEL_INFO(dev)->gen >= 7)
2304 return 768;
2305 else
2306 return 512;
2307 }
2308
2309 /* Calculate the maximum primary/sprite plane watermark */
2310 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2311 int level,
2312 const struct intel_wm_config *config,
2313 enum intel_ddb_partitioning ddb_partitioning,
2314 bool is_sprite)
2315 {
2316 unsigned int fifo_size = ilk_display_fifo_size(dev);
2317 unsigned int max;
2318
2319 /* if sprites aren't enabled, sprites get nothing */
2320 if (is_sprite && !config->sprites_enabled)
2321 return 0;
2322
2323 /* HSW allows LP1+ watermarks even with multiple pipes */
2324 if (level == 0 || config->num_pipes_active > 1) {
2325 fifo_size /= INTEL_INFO(dev)->num_pipes;
2326
2327 /*
2328 * For some reason the non self refresh
2329 * FIFO size is only half of the self
2330 * refresh FIFO size on ILK/SNB.
2331 */
2332 if (INTEL_INFO(dev)->gen <= 6)
2333 fifo_size /= 2;
2334 }
2335
2336 if (config->sprites_enabled) {
2337 /* level 0 is always calculated with 1:1 split */
2338 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2339 if (is_sprite)
2340 fifo_size *= 5;
2341 fifo_size /= 6;
2342 } else {
2343 fifo_size /= 2;
2344 }
2345 }
2346
2347 /* clamp to max that the registers can hold */
2348 if (INTEL_INFO(dev)->gen >= 8)
2349 max = level == 0 ? 255 : 2047;
2350 else if (INTEL_INFO(dev)->gen >= 7)
2351 /* IVB/HSW primary/sprite plane watermarks */
2352 max = level == 0 ? 127 : 1023;
2353 else if (!is_sprite)
2354 /* ILK/SNB primary plane watermarks */
2355 max = level == 0 ? 127 : 511;
2356 else
2357 /* ILK/SNB sprite plane watermarks */
2358 max = level == 0 ? 63 : 255;
2359
2360 return min(fifo_size, max);
2361 }
2362
2363 /* Calculate the maximum cursor plane watermark */
2364 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2365 int level,
2366 const struct intel_wm_config *config)
2367 {
2368 /* HSW LP1+ watermarks w/ multiple pipes */
2369 if (level > 0 && config->num_pipes_active > 1)
2370 return 64;
2371
2372 /* otherwise just report max that registers can hold */
2373 if (INTEL_INFO(dev)->gen >= 7)
2374 return level == 0 ? 63 : 255;
2375 else
2376 return level == 0 ? 31 : 63;
2377 }
2378
2379 /* Calculate the maximum FBC watermark */
2380 static unsigned int ilk_fbc_wm_max(struct drm_device *dev)
2381 {
2382 /* max that registers can hold */
2383 if (INTEL_INFO(dev)->gen >= 8)
2384 return 31;
2385 else
2386 return 15;
2387 }
2388
2389 static void ilk_compute_wm_maximums(struct drm_device *dev,
2390 int level,
2391 const struct intel_wm_config *config,
2392 enum intel_ddb_partitioning ddb_partitioning,
2393 struct hsw_wm_maximums *max)
2394 {
2395 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2396 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2397 max->cur = ilk_cursor_wm_max(dev, level, config);
2398 max->fbc = ilk_fbc_wm_max(dev);
2399 }
2400
2401 static bool ilk_validate_wm_level(int level,
2402 const struct hsw_wm_maximums *max,
2403 struct intel_wm_level *result)
2404 {
2405 bool ret;
2406
2407 /* already determined to be invalid? */
2408 if (!result->enable)
2409 return false;
2410
2411 result->enable = result->pri_val <= max->pri &&
2412 result->spr_val <= max->spr &&
2413 result->cur_val <= max->cur;
2414
2415 ret = result->enable;
2416
2417 /*
2418 * HACK until we can pre-compute everything,
2419 * and thus fail gracefully if LP0 watermarks
2420 * are exceeded...
2421 */
2422 if (level == 0 && !result->enable) {
2423 if (result->pri_val > max->pri)
2424 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2425 level, result->pri_val, max->pri);
2426 if (result->spr_val > max->spr)
2427 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2428 level, result->spr_val, max->spr);
2429 if (result->cur_val > max->cur)
2430 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2431 level, result->cur_val, max->cur);
2432
2433 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2434 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2435 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2436 result->enable = true;
2437 }
2438
2439 return ret;
2440 }
2441
2442 static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2443 int level,
2444 const struct hsw_pipe_wm_parameters *p,
2445 struct intel_wm_level *result)
2446 {
2447 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2448 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2449 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2450
2451 /* WM1+ latency values stored in 0.5us units */
2452 if (level > 0) {
2453 pri_latency *= 5;
2454 spr_latency *= 5;
2455 cur_latency *= 5;
2456 }
2457
2458 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2459 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2460 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2461 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2462 result->enable = true;
2463 }
2464
2465 static uint32_t
2466 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2467 {
2468 struct drm_i915_private *dev_priv = dev->dev_private;
2469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2470 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2471 u32 linetime, ips_linetime;
2472
2473 if (!intel_crtc_active(crtc))
2474 return 0;
2475
2476 /* The WM are computed with base on how long it takes to fill a single
2477 * row at the given clock rate, multiplied by 8.
2478 * */
2479 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2480 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2481 intel_ddi_get_cdclk_freq(dev_priv));
2482
2483 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2484 PIPE_WM_LINETIME_TIME(linetime);
2485 }
2486
2487 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2488 {
2489 struct drm_i915_private *dev_priv = dev->dev_private;
2490
2491 if (IS_HASWELL(dev)) {
2492 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2493
2494 wm[0] = (sskpd >> 56) & 0xFF;
2495 if (wm[0] == 0)
2496 wm[0] = sskpd & 0xF;
2497 wm[1] = (sskpd >> 4) & 0xFF;
2498 wm[2] = (sskpd >> 12) & 0xFF;
2499 wm[3] = (sskpd >> 20) & 0x1FF;
2500 wm[4] = (sskpd >> 32) & 0x1FF;
2501 } else if (INTEL_INFO(dev)->gen >= 6) {
2502 uint32_t sskpd = I915_READ(MCH_SSKPD);
2503
2504 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2505 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2506 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2507 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2508 } else if (INTEL_INFO(dev)->gen >= 5) {
2509 uint32_t mltr = I915_READ(MLTR_ILK);
2510
2511 /* ILK primary LP0 latency is 700 ns */
2512 wm[0] = 7;
2513 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2514 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2515 }
2516 }
2517
2518 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2519 {
2520 /* ILK sprite LP0 latency is 1300 ns */
2521 if (INTEL_INFO(dev)->gen == 5)
2522 wm[0] = 13;
2523 }
2524
2525 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2526 {
2527 /* ILK cursor LP0 latency is 1300 ns */
2528 if (INTEL_INFO(dev)->gen == 5)
2529 wm[0] = 13;
2530
2531 /* WaDoubleCursorLP3Latency:ivb */
2532 if (IS_IVYBRIDGE(dev))
2533 wm[3] *= 2;
2534 }
2535
2536 static int ilk_wm_max_level(const struct drm_device *dev)
2537 {
2538 /* how many WM levels are we expecting */
2539 if (IS_HASWELL(dev))
2540 return 4;
2541 else if (INTEL_INFO(dev)->gen >= 6)
2542 return 3;
2543 else
2544 return 2;
2545 }
2546
2547 static void intel_print_wm_latency(struct drm_device *dev,
2548 const char *name,
2549 const uint16_t wm[5])
2550 {
2551 int level, max_level = ilk_wm_max_level(dev);
2552
2553 for (level = 0; level <= max_level; level++) {
2554 unsigned int latency = wm[level];
2555
2556 if (latency == 0) {
2557 DRM_ERROR("%s WM%d latency not provided\n",
2558 name, level);
2559 continue;
2560 }
2561
2562 /* WM1+ latency values in 0.5us units */
2563 if (level > 0)
2564 latency *= 5;
2565
2566 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2567 name, level, wm[level],
2568 latency / 10, latency % 10);
2569 }
2570 }
2571
2572 static void intel_setup_wm_latency(struct drm_device *dev)
2573 {
2574 struct drm_i915_private *dev_priv = dev->dev_private;
2575
2576 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2577
2578 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2579 sizeof(dev_priv->wm.pri_latency));
2580 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2581 sizeof(dev_priv->wm.pri_latency));
2582
2583 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2584 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2585
2586 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2587 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2588 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2589 }
2590
2591 static void hsw_compute_wm_parameters(struct drm_crtc *crtc,
2592 struct hsw_pipe_wm_parameters *p,
2593 struct intel_wm_config *config)
2594 {
2595 struct drm_device *dev = crtc->dev;
2596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2597 enum pipe pipe = intel_crtc->pipe;
2598 struct drm_plane *plane;
2599
2600 p->active = intel_crtc_active(crtc);
2601 if (p->active) {
2602 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2603 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2604 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2605 p->cur.bytes_per_pixel = 4;
2606 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2607 p->cur.horiz_pixels = 64;
2608 /* TODO: for now, assume primary and cursor planes are always enabled. */
2609 p->pri.enabled = true;
2610 p->cur.enabled = true;
2611 }
2612
2613 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2614 config->num_pipes_active += intel_crtc_active(crtc);
2615
2616 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2617 struct intel_plane *intel_plane = to_intel_plane(plane);
2618
2619 if (intel_plane->pipe == pipe)
2620 p->spr = intel_plane->wm;
2621
2622 config->sprites_enabled |= intel_plane->wm.enabled;
2623 config->sprites_scaled |= intel_plane->wm.scaled;
2624 }
2625 }
2626
2627 /* Compute new watermarks for the pipe */
2628 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2629 const struct hsw_pipe_wm_parameters *params,
2630 struct intel_pipe_wm *pipe_wm)
2631 {
2632 struct drm_device *dev = crtc->dev;
2633 struct drm_i915_private *dev_priv = dev->dev_private;
2634 int level, max_level = ilk_wm_max_level(dev);
2635 /* LP0 watermark maximums depend on this pipe alone */
2636 struct intel_wm_config config = {
2637 .num_pipes_active = 1,
2638 .sprites_enabled = params->spr.enabled,
2639 .sprites_scaled = params->spr.scaled,
2640 };
2641 struct hsw_wm_maximums max;
2642
2643 /* LP0 watermarks always use 1/2 DDB partitioning */
2644 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2645
2646 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2647 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2648 max_level = 1;
2649
2650 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2651 if (params->spr.scaled)
2652 max_level = 0;
2653
2654 for (level = 0; level <= max_level; level++)
2655 ilk_compute_wm_level(dev_priv, level, params,
2656 &pipe_wm->wm[level]);
2657
2658 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2659
2660 /* At least LP0 must be valid */
2661 return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
2662 }
2663
2664 /*
2665 * Merge the watermarks from all active pipes for a specific level.
2666 */
2667 static void ilk_merge_wm_level(struct drm_device *dev,
2668 int level,
2669 struct intel_wm_level *ret_wm)
2670 {
2671 const struct intel_crtc *intel_crtc;
2672
2673 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2674 const struct intel_wm_level *wm =
2675 &intel_crtc->wm.active.wm[level];
2676
2677 if (!wm->enable)
2678 return;
2679
2680 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2681 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2682 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2683 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2684 }
2685
2686 ret_wm->enable = true;
2687 }
2688
2689 /*
2690 * Merge all low power watermarks for all active pipes.
2691 */
2692 static void ilk_wm_merge(struct drm_device *dev,
2693 const struct hsw_wm_maximums *max,
2694 struct intel_pipe_wm *merged)
2695 {
2696 int level, max_level = ilk_wm_max_level(dev);
2697
2698 merged->fbc_wm_enabled = true;
2699
2700 /* merge each WM1+ level */
2701 for (level = 1; level <= max_level; level++) {
2702 struct intel_wm_level *wm = &merged->wm[level];
2703
2704 ilk_merge_wm_level(dev, level, wm);
2705
2706 if (!ilk_validate_wm_level(level, max, wm))
2707 break;
2708
2709 /*
2710 * The spec says it is preferred to disable
2711 * FBC WMs instead of disabling a WM level.
2712 */
2713 if (wm->fbc_val > max->fbc) {
2714 merged->fbc_wm_enabled = false;
2715 wm->fbc_val = 0;
2716 }
2717 }
2718 }
2719
2720 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2721 {
2722 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2723 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2724 }
2725
2726 /* The value we need to program into the WM_LPx latency field */
2727 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2728 {
2729 struct drm_i915_private *dev_priv = dev->dev_private;
2730
2731 if (IS_HASWELL(dev))
2732 return 2 * level;
2733 else
2734 return dev_priv->wm.pri_latency[level];
2735 }
2736
2737 static void hsw_compute_wm_results(struct drm_device *dev,
2738 const struct intel_pipe_wm *merged,
2739 enum intel_ddb_partitioning partitioning,
2740 struct hsw_wm_values *results)
2741 {
2742 struct intel_crtc *intel_crtc;
2743 int level, wm_lp;
2744
2745 results->enable_fbc_wm = merged->fbc_wm_enabled;
2746 results->partitioning = partitioning;
2747
2748 /* LP1+ register values */
2749 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2750 const struct intel_wm_level *r;
2751
2752 level = ilk_wm_lp_to_level(wm_lp, merged);
2753
2754 r = &merged->wm[level];
2755 if (!r->enable)
2756 break;
2757
2758 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
2759 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2760 (r->pri_val << WM1_LP_SR_SHIFT) |
2761 r->cur_val;
2762
2763 if (INTEL_INFO(dev)->gen >= 8)
2764 results->wm_lp[wm_lp - 1] |=
2765 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2766 else
2767 results->wm_lp[wm_lp - 1] |=
2768 r->fbc_val << WM1_LP_FBC_SHIFT;
2769
2770 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2771 WARN_ON(wm_lp != 1);
2772 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2773 } else
2774 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2775 }
2776
2777 /* LP0 register values */
2778 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2779 enum pipe pipe = intel_crtc->pipe;
2780 const struct intel_wm_level *r =
2781 &intel_crtc->wm.active.wm[0];
2782
2783 if (WARN_ON(!r->enable))
2784 continue;
2785
2786 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2787
2788 results->wm_pipe[pipe] =
2789 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2790 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2791 r->cur_val;
2792 }
2793 }
2794
2795 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2796 * case both are at the same level. Prefer r1 in case they're the same. */
2797 static struct intel_pipe_wm *hsw_find_best_result(struct drm_device *dev,
2798 struct intel_pipe_wm *r1,
2799 struct intel_pipe_wm *r2)
2800 {
2801 int level, max_level = ilk_wm_max_level(dev);
2802 int level1 = 0, level2 = 0;
2803
2804 for (level = 1; level <= max_level; level++) {
2805 if (r1->wm[level].enable)
2806 level1 = level;
2807 if (r2->wm[level].enable)
2808 level2 = level;
2809 }
2810
2811 if (level1 == level2) {
2812 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2813 return r2;
2814 else
2815 return r1;
2816 } else if (level1 > level2) {
2817 return r1;
2818 } else {
2819 return r2;
2820 }
2821 }
2822
2823 /* dirty bits used to track which watermarks need changes */
2824 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2825 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2826 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2827 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2828 #define WM_DIRTY_FBC (1 << 24)
2829 #define WM_DIRTY_DDB (1 << 25)
2830
2831 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2832 const struct hsw_wm_values *old,
2833 const struct hsw_wm_values *new)
2834 {
2835 unsigned int dirty = 0;
2836 enum pipe pipe;
2837 int wm_lp;
2838
2839 for_each_pipe(pipe) {
2840 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2841 dirty |= WM_DIRTY_LINETIME(pipe);
2842 /* Must disable LP1+ watermarks too */
2843 dirty |= WM_DIRTY_LP_ALL;
2844 }
2845
2846 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2847 dirty |= WM_DIRTY_PIPE(pipe);
2848 /* Must disable LP1+ watermarks too */
2849 dirty |= WM_DIRTY_LP_ALL;
2850 }
2851 }
2852
2853 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2854 dirty |= WM_DIRTY_FBC;
2855 /* Must disable LP1+ watermarks too */
2856 dirty |= WM_DIRTY_LP_ALL;
2857 }
2858
2859 if (old->partitioning != new->partitioning) {
2860 dirty |= WM_DIRTY_DDB;
2861 /* Must disable LP1+ watermarks too */
2862 dirty |= WM_DIRTY_LP_ALL;
2863 }
2864
2865 /* LP1+ watermarks already deemed dirty, no need to continue */
2866 if (dirty & WM_DIRTY_LP_ALL)
2867 return dirty;
2868
2869 /* Find the lowest numbered LP1+ watermark in need of an update... */
2870 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2871 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2872 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2873 break;
2874 }
2875
2876 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2877 for (; wm_lp <= 3; wm_lp++)
2878 dirty |= WM_DIRTY_LP(wm_lp);
2879
2880 return dirty;
2881 }
2882
2883 /*
2884 * The spec says we shouldn't write when we don't need, because every write
2885 * causes WMs to be re-evaluated, expending some power.
2886 */
2887 static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2888 struct hsw_wm_values *results)
2889 {
2890 struct drm_device *dev = dev_priv->dev;
2891 struct hsw_wm_values *previous = &dev_priv->wm.hw;
2892 unsigned int dirty;
2893 uint32_t val;
2894
2895 dirty = ilk_compute_wm_dirty(dev_priv->dev, previous, results);
2896 if (!dirty)
2897 return;
2898
2899 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != 0)
2900 I915_WRITE(WM3_LP_ILK, 0);
2901 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != 0)
2902 I915_WRITE(WM2_LP_ILK, 0);
2903 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != 0)
2904 I915_WRITE(WM1_LP_ILK, 0);
2905
2906 if (INTEL_INFO(dev)->gen <= 6 &&
2907 dirty & WM_DIRTY_LP(1) && previous->wm_lp_spr[0] != 0)
2908 I915_WRITE(WM1S_LP_ILK, 0);
2909
2910 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2911 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2912 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2913 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2914 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2915 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2916
2917 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2918 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2919 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2920 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2921 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2922 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2923
2924 if (dirty & WM_DIRTY_DDB) {
2925 if (IS_HASWELL(dev)) {
2926 val = I915_READ(WM_MISC);
2927 if (results->partitioning == INTEL_DDB_PART_1_2)
2928 val &= ~WM_MISC_DATA_PARTITION_5_6;
2929 else
2930 val |= WM_MISC_DATA_PARTITION_5_6;
2931 I915_WRITE(WM_MISC, val);
2932 } else {
2933 val = I915_READ(DISP_ARB_CTL2);
2934 if (results->partitioning == INTEL_DDB_PART_1_2)
2935 val &= ~DISP_DATA_PARTITION_5_6;
2936 else
2937 val |= DISP_DATA_PARTITION_5_6;
2938 I915_WRITE(DISP_ARB_CTL2, val);
2939 }
2940 }
2941
2942 if (dirty & WM_DIRTY_FBC) {
2943 val = I915_READ(DISP_ARB_CTL);
2944 if (results->enable_fbc_wm)
2945 val &= ~DISP_FBC_WM_DIS;
2946 else
2947 val |= DISP_FBC_WM_DIS;
2948 I915_WRITE(DISP_ARB_CTL, val);
2949 }
2950
2951 if (INTEL_INFO(dev)->gen <= 6) {
2952 if (dirty & WM_DIRTY_LP(1) && results->wm_lp_spr[0] != 0)
2953 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2954 } else {
2955 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2956 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2957 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2958 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2959 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2960 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2961 }
2962
2963 if (dirty & WM_DIRTY_LP(1) && results->wm_lp[0] != 0)
2964 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2965 if (dirty & WM_DIRTY_LP(2) && results->wm_lp[1] != 0)
2966 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2967 if (dirty & WM_DIRTY_LP(3) && results->wm_lp[2] != 0)
2968 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2969
2970 dev_priv->wm.hw = *results;
2971 }
2972
2973 static void haswell_update_wm(struct drm_crtc *crtc)
2974 {
2975 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2976 struct drm_device *dev = crtc->dev;
2977 struct drm_i915_private *dev_priv = dev->dev_private;
2978 struct hsw_wm_maximums max;
2979 struct hsw_pipe_wm_parameters params = {};
2980 struct hsw_wm_values results = {};
2981 enum intel_ddb_partitioning partitioning;
2982 struct intel_pipe_wm pipe_wm = {};
2983 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2984 struct intel_wm_config config = {};
2985
2986 hsw_compute_wm_parameters(crtc, &params, &config);
2987
2988 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2989
2990 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2991 return;
2992
2993 intel_crtc->wm.active = pipe_wm;
2994
2995 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2996 ilk_wm_merge(dev, &max, &lp_wm_1_2);
2997
2998 /* 5/6 split only in single pipe config on IVB+ */
2999 if (INTEL_INFO(dev)->gen >= 7 &&
3000 config.num_pipes_active == 1 && config.sprites_enabled) {
3001 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3002 ilk_wm_merge(dev, &max, &lp_wm_5_6);
3003
3004 best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3005 } else {
3006 best_lp_wm = &lp_wm_1_2;
3007 }
3008
3009 partitioning = (best_lp_wm == &lp_wm_1_2) ?
3010 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3011
3012 hsw_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3013
3014 hsw_write_wm_values(dev_priv, &results);
3015 }
3016
3017 static void haswell_update_sprite_wm(struct drm_plane *plane,
3018 struct drm_crtc *crtc,
3019 uint32_t sprite_width, int pixel_size,
3020 bool enabled, bool scaled)
3021 {
3022 struct intel_plane *intel_plane = to_intel_plane(plane);
3023
3024 intel_plane->wm.enabled = enabled;
3025 intel_plane->wm.scaled = scaled;
3026 intel_plane->wm.horiz_pixels = sprite_width;
3027 intel_plane->wm.bytes_per_pixel = pixel_size;
3028
3029 haswell_update_wm(crtc);
3030 }
3031
3032 static bool
3033 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
3034 uint32_t sprite_width, int pixel_size,
3035 const struct intel_watermark_params *display,
3036 int display_latency_ns, int *sprite_wm)
3037 {
3038 struct drm_crtc *crtc;
3039 int clock;
3040 int entries, tlb_miss;
3041
3042 crtc = intel_get_crtc_for_plane(dev, plane);
3043 if (!intel_crtc_active(crtc)) {
3044 *sprite_wm = display->guard_size;
3045 return false;
3046 }
3047
3048 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3049
3050 /* Use the small buffer method to calculate the sprite watermark */
3051 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3052 tlb_miss = display->fifo_size*display->cacheline_size -
3053 sprite_width * 8;
3054 if (tlb_miss > 0)
3055 entries += tlb_miss;
3056 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3057 *sprite_wm = entries + display->guard_size;
3058 if (*sprite_wm > (int)display->max_wm)
3059 *sprite_wm = display->max_wm;
3060
3061 return true;
3062 }
3063
3064 static bool
3065 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
3066 uint32_t sprite_width, int pixel_size,
3067 const struct intel_watermark_params *display,
3068 int latency_ns, int *sprite_wm)
3069 {
3070 struct drm_crtc *crtc;
3071 unsigned long line_time_us;
3072 int clock;
3073 int line_count, line_size;
3074 int small, large;
3075 int entries;
3076
3077 if (!latency_ns) {
3078 *sprite_wm = 0;
3079 return false;
3080 }
3081
3082 crtc = intel_get_crtc_for_plane(dev, plane);
3083 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3084 if (!clock) {
3085 *sprite_wm = 0;
3086 return false;
3087 }
3088
3089 line_time_us = (sprite_width * 1000) / clock;
3090 if (!line_time_us) {
3091 *sprite_wm = 0;
3092 return false;
3093 }
3094
3095 line_count = (latency_ns / line_time_us + 1000) / 1000;
3096 line_size = sprite_width * pixel_size;
3097
3098 /* Use the minimum of the small and large buffer method for primary */
3099 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3100 large = line_count * line_size;
3101
3102 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3103 *sprite_wm = entries + display->guard_size;
3104
3105 return *sprite_wm > 0x3ff ? false : true;
3106 }
3107
3108 static void sandybridge_update_sprite_wm(struct drm_plane *plane,
3109 struct drm_crtc *crtc,
3110 uint32_t sprite_width, int pixel_size,
3111 bool enabled, bool scaled)
3112 {
3113 struct drm_device *dev = plane->dev;
3114 struct drm_i915_private *dev_priv = dev->dev_private;
3115 int pipe = to_intel_plane(plane)->pipe;
3116 int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
3117 u32 val;
3118 int sprite_wm, reg;
3119 int ret;
3120
3121 if (!enabled)
3122 return;
3123
3124 switch (pipe) {
3125 case 0:
3126 reg = WM0_PIPEA_ILK;
3127 break;
3128 case 1:
3129 reg = WM0_PIPEB_ILK;
3130 break;
3131 case 2:
3132 reg = WM0_PIPEC_IVB;
3133 break;
3134 default:
3135 return; /* bad pipe */
3136 }
3137
3138 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3139 &sandybridge_display_wm_info,
3140 latency, &sprite_wm);
3141 if (!ret) {
3142 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3143 pipe_name(pipe));
3144 return;
3145 }
3146
3147 val = I915_READ(reg);
3148 val &= ~WM0_PIPE_SPRITE_MASK;
3149 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
3150 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
3151
3152
3153 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3154 pixel_size,
3155 &sandybridge_display_srwm_info,
3156 dev_priv->wm.spr_latency[1] * 500,
3157 &sprite_wm);
3158 if (!ret) {
3159 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3160 pipe_name(pipe));
3161 return;
3162 }
3163 I915_WRITE(WM1S_LP_ILK, sprite_wm);
3164
3165 /* Only IVB has two more LP watermarks for sprite */
3166 if (!IS_IVYBRIDGE(dev))
3167 return;
3168
3169 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3170 pixel_size,
3171 &sandybridge_display_srwm_info,
3172 dev_priv->wm.spr_latency[2] * 500,
3173 &sprite_wm);
3174 if (!ret) {
3175 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3176 pipe_name(pipe));
3177 return;
3178 }
3179 I915_WRITE(WM2S_LP_IVB, sprite_wm);
3180
3181 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3182 pixel_size,
3183 &sandybridge_display_srwm_info,
3184 dev_priv->wm.spr_latency[3] * 500,
3185 &sprite_wm);
3186 if (!ret) {
3187 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3188 pipe_name(pipe));
3189 return;
3190 }
3191 I915_WRITE(WM3S_LP_IVB, sprite_wm);
3192 }
3193
3194 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3195 {
3196 struct drm_device *dev = crtc->dev;
3197 struct drm_i915_private *dev_priv = dev->dev_private;
3198 struct hsw_wm_values *hw = &dev_priv->wm.hw;
3199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3200 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3201 enum pipe pipe = intel_crtc->pipe;
3202 static const unsigned int wm0_pipe_reg[] = {
3203 [PIPE_A] = WM0_PIPEA_ILK,
3204 [PIPE_B] = WM0_PIPEB_ILK,
3205 [PIPE_C] = WM0_PIPEC_IVB,
3206 };
3207
3208 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3209 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3210
3211 if (intel_crtc_active(crtc)) {
3212 u32 tmp = hw->wm_pipe[pipe];
3213
3214 /*
3215 * For active pipes LP0 watermark is marked as
3216 * enabled, and LP1+ watermaks as disabled since
3217 * we can't really reverse compute them in case
3218 * multiple pipes are active.
3219 */
3220 active->wm[0].enable = true;
3221 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3222 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3223 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3224 active->linetime = hw->wm_linetime[pipe];
3225 } else {
3226 int level, max_level = ilk_wm_max_level(dev);
3227
3228 /*
3229 * For inactive pipes, all watermark levels
3230 * should be marked as enabled but zeroed,
3231 * which is what we'd compute them to.
3232 */
3233 for (level = 0; level <= max_level; level++)
3234 active->wm[level].enable = true;
3235 }
3236 }
3237
3238 void ilk_wm_get_hw_state(struct drm_device *dev)
3239 {
3240 struct drm_i915_private *dev_priv = dev->dev_private;
3241 struct hsw_wm_values *hw = &dev_priv->wm.hw;
3242 struct drm_crtc *crtc;
3243
3244 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3245 ilk_pipe_wm_get_hw_state(crtc);
3246
3247 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3248 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3249 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3250
3251 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3252 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3253 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3254
3255 if (IS_HASWELL(dev))
3256 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3257 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3258 else if (IS_IVYBRIDGE(dev))
3259 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3260 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3261
3262 hw->enable_fbc_wm =
3263 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3264 }
3265
3266 /**
3267 * intel_update_watermarks - update FIFO watermark values based on current modes
3268 *
3269 * Calculate watermark values for the various WM regs based on current mode
3270 * and plane configuration.
3271 *
3272 * There are several cases to deal with here:
3273 * - normal (i.e. non-self-refresh)
3274 * - self-refresh (SR) mode
3275 * - lines are large relative to FIFO size (buffer can hold up to 2)
3276 * - lines are small relative to FIFO size (buffer can hold more than 2
3277 * lines), so need to account for TLB latency
3278 *
3279 * The normal calculation is:
3280 * watermark = dotclock * bytes per pixel * latency
3281 * where latency is platform & configuration dependent (we assume pessimal
3282 * values here).
3283 *
3284 * The SR calculation is:
3285 * watermark = (trunc(latency/line time)+1) * surface width *
3286 * bytes per pixel
3287 * where
3288 * line time = htotal / dotclock
3289 * surface width = hdisplay for normal plane and 64 for cursor
3290 * and latency is assumed to be high, as above.
3291 *
3292 * The final value programmed to the register should always be rounded up,
3293 * and include an extra 2 entries to account for clock crossings.
3294 *
3295 * We don't use the sprite, so we can ignore that. And on Crestline we have
3296 * to set the non-SR watermarks to 8.
3297 */
3298 void intel_update_watermarks(struct drm_crtc *crtc)
3299 {
3300 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3301
3302 if (dev_priv->display.update_wm)
3303 dev_priv->display.update_wm(crtc);
3304 }
3305
3306 void intel_update_sprite_watermarks(struct drm_plane *plane,
3307 struct drm_crtc *crtc,
3308 uint32_t sprite_width, int pixel_size,
3309 bool enabled, bool scaled)
3310 {
3311 struct drm_i915_private *dev_priv = plane->dev->dev_private;
3312
3313 if (dev_priv->display.update_sprite_wm)
3314 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
3315 pixel_size, enabled, scaled);
3316 }
3317
3318 static struct drm_i915_gem_object *
3319 intel_alloc_context_page(struct drm_device *dev)
3320 {
3321 struct drm_i915_gem_object *ctx;
3322 int ret;
3323
3324 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3325
3326 ctx = i915_gem_alloc_object(dev, 4096);
3327 if (!ctx) {
3328 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3329 return NULL;
3330 }
3331
3332 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
3333 if (ret) {
3334 DRM_ERROR("failed to pin power context: %d\n", ret);
3335 goto err_unref;
3336 }
3337
3338 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3339 if (ret) {
3340 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3341 goto err_unpin;
3342 }
3343
3344 return ctx;
3345
3346 err_unpin:
3347 i915_gem_object_unpin(ctx);
3348 err_unref:
3349 drm_gem_object_unreference(&ctx->base);
3350 return NULL;
3351 }
3352
3353 /**
3354 * Lock protecting IPS related data structures
3355 */
3356 DEFINE_SPINLOCK(mchdev_lock);
3357
3358 /* Global for IPS driver to get at the current i915 device. Protected by
3359 * mchdev_lock. */
3360 static struct drm_i915_private *i915_mch_dev;
3361
3362 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3363 {
3364 struct drm_i915_private *dev_priv = dev->dev_private;
3365 u16 rgvswctl;
3366
3367 assert_spin_locked(&mchdev_lock);
3368
3369 rgvswctl = I915_READ16(MEMSWCTL);
3370 if (rgvswctl & MEMCTL_CMD_STS) {
3371 DRM_DEBUG("gpu busy, RCS change rejected\n");
3372 return false; /* still busy with another command */
3373 }
3374
3375 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3376 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3377 I915_WRITE16(MEMSWCTL, rgvswctl);
3378 POSTING_READ16(MEMSWCTL);
3379
3380 rgvswctl |= MEMCTL_CMD_STS;
3381 I915_WRITE16(MEMSWCTL, rgvswctl);
3382
3383 return true;
3384 }
3385
3386 static void ironlake_enable_drps(struct drm_device *dev)
3387 {
3388 struct drm_i915_private *dev_priv = dev->dev_private;
3389 u32 rgvmodectl = I915_READ(MEMMODECTL);
3390 u8 fmax, fmin, fstart, vstart;
3391
3392 spin_lock_irq(&mchdev_lock);
3393
3394 /* Enable temp reporting */
3395 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3396 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3397
3398 /* 100ms RC evaluation intervals */
3399 I915_WRITE(RCUPEI, 100000);
3400 I915_WRITE(RCDNEI, 100000);
3401
3402 /* Set max/min thresholds to 90ms and 80ms respectively */
3403 I915_WRITE(RCBMAXAVG, 90000);
3404 I915_WRITE(RCBMINAVG, 80000);
3405
3406 I915_WRITE(MEMIHYST, 1);
3407
3408 /* Set up min, max, and cur for interrupt handling */
3409 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3410 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3411 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3412 MEMMODE_FSTART_SHIFT;
3413
3414 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3415 PXVFREQ_PX_SHIFT;
3416
3417 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3418 dev_priv->ips.fstart = fstart;
3419
3420 dev_priv->ips.max_delay = fstart;
3421 dev_priv->ips.min_delay = fmin;
3422 dev_priv->ips.cur_delay = fstart;
3423
3424 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3425 fmax, fmin, fstart);
3426
3427 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3428
3429 /*
3430 * Interrupts will be enabled in ironlake_irq_postinstall
3431 */
3432
3433 I915_WRITE(VIDSTART, vstart);
3434 POSTING_READ(VIDSTART);
3435
3436 rgvmodectl |= MEMMODE_SWMODE_EN;
3437 I915_WRITE(MEMMODECTL, rgvmodectl);
3438
3439 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3440 DRM_ERROR("stuck trying to change perf mode\n");
3441 mdelay(1);
3442
3443 ironlake_set_drps(dev, fstart);
3444
3445 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3446 I915_READ(0x112e0);
3447 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3448 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3449 getrawmonotonic(&dev_priv->ips.last_time2);
3450
3451 spin_unlock_irq(&mchdev_lock);
3452 }
3453
3454 static void ironlake_disable_drps(struct drm_device *dev)
3455 {
3456 struct drm_i915_private *dev_priv = dev->dev_private;
3457 u16 rgvswctl;
3458
3459 spin_lock_irq(&mchdev_lock);
3460
3461 rgvswctl = I915_READ16(MEMSWCTL);
3462
3463 /* Ack interrupts, disable EFC interrupt */
3464 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3465 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3466 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3467 I915_WRITE(DEIIR, DE_PCU_EVENT);
3468 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3469
3470 /* Go back to the starting frequency */
3471 ironlake_set_drps(dev, dev_priv->ips.fstart);
3472 mdelay(1);
3473 rgvswctl |= MEMCTL_CMD_STS;
3474 I915_WRITE(MEMSWCTL, rgvswctl);
3475 mdelay(1);
3476
3477 spin_unlock_irq(&mchdev_lock);
3478 }
3479
3480 /* There's a funny hw issue where the hw returns all 0 when reading from
3481 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3482 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3483 * all limits and the gpu stuck at whatever frequency it is at atm).
3484 */
3485 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3486 {
3487 u32 limits;
3488
3489 /* Only set the down limit when we've reached the lowest level to avoid
3490 * getting more interrupts, otherwise leave this clear. This prevents a
3491 * race in the hw when coming out of rc6: There's a tiny window where
3492 * the hw runs at the minimal clock before selecting the desired
3493 * frequency, if the down threshold expires in that window we will not
3494 * receive a down interrupt. */
3495 limits = dev_priv->rps.max_delay << 24;
3496 if (val <= dev_priv->rps.min_delay)
3497 limits |= dev_priv->rps.min_delay << 16;
3498
3499 return limits;
3500 }
3501
3502 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3503 {
3504 int new_power;
3505
3506 new_power = dev_priv->rps.power;
3507 switch (dev_priv->rps.power) {
3508 case LOW_POWER:
3509 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
3510 new_power = BETWEEN;
3511 break;
3512
3513 case BETWEEN:
3514 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
3515 new_power = LOW_POWER;
3516 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
3517 new_power = HIGH_POWER;
3518 break;
3519
3520 case HIGH_POWER:
3521 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
3522 new_power = BETWEEN;
3523 break;
3524 }
3525 /* Max/min bins are special */
3526 if (val == dev_priv->rps.min_delay)
3527 new_power = LOW_POWER;
3528 if (val == dev_priv->rps.max_delay)
3529 new_power = HIGH_POWER;
3530 if (new_power == dev_priv->rps.power)
3531 return;
3532
3533 /* Note the units here are not exactly 1us, but 1280ns. */
3534 switch (new_power) {
3535 case LOW_POWER:
3536 /* Upclock if more than 95% busy over 16ms */
3537 I915_WRITE(GEN6_RP_UP_EI, 12500);
3538 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3539
3540 /* Downclock if less than 85% busy over 32ms */
3541 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3542 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3543
3544 I915_WRITE(GEN6_RP_CONTROL,
3545 GEN6_RP_MEDIA_TURBO |
3546 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3547 GEN6_RP_MEDIA_IS_GFX |
3548 GEN6_RP_ENABLE |
3549 GEN6_RP_UP_BUSY_AVG |
3550 GEN6_RP_DOWN_IDLE_AVG);
3551 break;
3552
3553 case BETWEEN:
3554 /* Upclock if more than 90% busy over 13ms */
3555 I915_WRITE(GEN6_RP_UP_EI, 10250);
3556 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3557
3558 /* Downclock if less than 75% busy over 32ms */
3559 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3560 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3561
3562 I915_WRITE(GEN6_RP_CONTROL,
3563 GEN6_RP_MEDIA_TURBO |
3564 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3565 GEN6_RP_MEDIA_IS_GFX |
3566 GEN6_RP_ENABLE |
3567 GEN6_RP_UP_BUSY_AVG |
3568 GEN6_RP_DOWN_IDLE_AVG);
3569 break;
3570
3571 case HIGH_POWER:
3572 /* Upclock if more than 85% busy over 10ms */
3573 I915_WRITE(GEN6_RP_UP_EI, 8000);
3574 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3575
3576 /* Downclock if less than 60% busy over 32ms */
3577 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3578 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3579
3580 I915_WRITE(GEN6_RP_CONTROL,
3581 GEN6_RP_MEDIA_TURBO |
3582 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3583 GEN6_RP_MEDIA_IS_GFX |
3584 GEN6_RP_ENABLE |
3585 GEN6_RP_UP_BUSY_AVG |
3586 GEN6_RP_DOWN_IDLE_AVG);
3587 break;
3588 }
3589
3590 dev_priv->rps.power = new_power;
3591 dev_priv->rps.last_adj = 0;
3592 }
3593
3594 void gen6_set_rps(struct drm_device *dev, u8 val)
3595 {
3596 struct drm_i915_private *dev_priv = dev->dev_private;
3597
3598 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3599 WARN_ON(val > dev_priv->rps.max_delay);
3600 WARN_ON(val < dev_priv->rps.min_delay);
3601
3602 if (val == dev_priv->rps.cur_delay)
3603 return;
3604
3605 gen6_set_rps_thresholds(dev_priv, val);
3606
3607 if (IS_HASWELL(dev))
3608 I915_WRITE(GEN6_RPNSWREQ,
3609 HSW_FREQUENCY(val));
3610 else
3611 I915_WRITE(GEN6_RPNSWREQ,
3612 GEN6_FREQUENCY(val) |
3613 GEN6_OFFSET(0) |
3614 GEN6_AGGRESSIVE_TURBO);
3615
3616 /* Make sure we continue to get interrupts
3617 * until we hit the minimum or maximum frequencies.
3618 */
3619 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3620 gen6_rps_limits(dev_priv, val));
3621
3622 POSTING_READ(GEN6_RPNSWREQ);
3623
3624 dev_priv->rps.cur_delay = val;
3625
3626 trace_intel_gpu_freq_change(val * 50);
3627 }
3628
3629 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3630 {
3631 struct drm_device *dev = dev_priv->dev;
3632
3633 mutex_lock(&dev_priv->rps.hw_lock);
3634 if (dev_priv->rps.enabled) {
3635 if (IS_VALLEYVIEW(dev))
3636 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3637 else
3638 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3639 dev_priv->rps.last_adj = 0;
3640 }
3641 mutex_unlock(&dev_priv->rps.hw_lock);
3642 }
3643
3644 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3645 {
3646 struct drm_device *dev = dev_priv->dev;
3647
3648 mutex_lock(&dev_priv->rps.hw_lock);
3649 if (dev_priv->rps.enabled) {
3650 if (IS_VALLEYVIEW(dev))
3651 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3652 else
3653 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3654 dev_priv->rps.last_adj = 0;
3655 }
3656 mutex_unlock(&dev_priv->rps.hw_lock);
3657 }
3658
3659 void valleyview_set_rps(struct drm_device *dev, u8 val)
3660 {
3661 struct drm_i915_private *dev_priv = dev->dev_private;
3662
3663 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3664 WARN_ON(val > dev_priv->rps.max_delay);
3665 WARN_ON(val < dev_priv->rps.min_delay);
3666
3667 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3668 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
3669 dev_priv->rps.cur_delay,
3670 vlv_gpu_freq(dev_priv, val), val);
3671
3672 if (val == dev_priv->rps.cur_delay)
3673 return;
3674
3675 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3676
3677 dev_priv->rps.cur_delay = val;
3678
3679 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3680 }
3681
3682 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3683 {
3684 struct drm_i915_private *dev_priv = dev->dev_private;
3685
3686 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3687 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3688 /* Complete PM interrupt masking here doesn't race with the rps work
3689 * item again unmasking PM interrupts because that is using a different
3690 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3691 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3692
3693 spin_lock_irq(&dev_priv->irq_lock);
3694 dev_priv->rps.pm_iir = 0;
3695 spin_unlock_irq(&dev_priv->irq_lock);
3696
3697 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3698 }
3699
3700 static void gen6_disable_rps(struct drm_device *dev)
3701 {
3702 struct drm_i915_private *dev_priv = dev->dev_private;
3703
3704 I915_WRITE(GEN6_RC_CONTROL, 0);
3705 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3706
3707 gen6_disable_rps_interrupts(dev);
3708 }
3709
3710 static void valleyview_disable_rps(struct drm_device *dev)
3711 {
3712 struct drm_i915_private *dev_priv = dev->dev_private;
3713
3714 I915_WRITE(GEN6_RC_CONTROL, 0);
3715
3716 gen6_disable_rps_interrupts(dev);
3717
3718 if (dev_priv->vlv_pctx) {
3719 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3720 dev_priv->vlv_pctx = NULL;
3721 }
3722 }
3723
3724 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3725 {
3726 if (IS_GEN6(dev))
3727 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3728
3729 if (IS_HASWELL(dev))
3730 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3731
3732 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3733 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3734 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3735 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3736 }
3737
3738 int intel_enable_rc6(const struct drm_device *dev)
3739 {
3740 /* No RC6 before Ironlake */
3741 if (INTEL_INFO(dev)->gen < 5)
3742 return 0;
3743
3744 /* Respect the kernel parameter if it is set */
3745 if (i915_enable_rc6 >= 0)
3746 return i915_enable_rc6;
3747
3748 /* Disable RC6 on Ironlake */
3749 if (INTEL_INFO(dev)->gen == 5)
3750 return 0;
3751
3752 if (IS_HASWELL(dev))
3753 return INTEL_RC6_ENABLE;
3754
3755 /* snb/ivb have more than one rc6 state. */
3756 if (INTEL_INFO(dev)->gen == 6)
3757 return INTEL_RC6_ENABLE;
3758
3759 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3760 }
3761
3762 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3763 {
3764 struct drm_i915_private *dev_priv = dev->dev_private;
3765 u32 enabled_intrs;
3766
3767 spin_lock_irq(&dev_priv->irq_lock);
3768 WARN_ON(dev_priv->rps.pm_iir);
3769 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
3770 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3771 spin_unlock_irq(&dev_priv->irq_lock);
3772
3773 /* only unmask PM interrupts we need. Mask all others. */
3774 enabled_intrs = GEN6_PM_RPS_EVENTS;
3775
3776 /* IVB and SNB hard hangs on looping batchbuffer
3777 * if GEN6_PM_UP_EI_EXPIRED is masked.
3778 */
3779 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3780 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3781
3782 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
3783 }
3784
3785 static void gen8_enable_rps(struct drm_device *dev)
3786 {
3787 struct drm_i915_private *dev_priv = dev->dev_private;
3788 struct intel_ring_buffer *ring;
3789 uint32_t rc6_mask = 0, rp_state_cap;
3790 int unused;
3791
3792 /* 1a: Software RC state - RC0 */
3793 I915_WRITE(GEN6_RC_STATE, 0);
3794
3795 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3796 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3797 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3798
3799 /* 2a: Disable RC states. */
3800 I915_WRITE(GEN6_RC_CONTROL, 0);
3801
3802 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3803
3804 /* 2b: Program RC6 thresholds.*/
3805 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3806 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3807 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3808 for_each_ring(ring, dev_priv, unused)
3809 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3810 I915_WRITE(GEN6_RC_SLEEP, 0);
3811 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3812
3813 /* 3: Enable RC6 */
3814 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3815 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3816 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
3817 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3818 GEN6_RC_CTL_EI_MODE(1) |
3819 rc6_mask);
3820
3821 /* 4 Program defaults and thresholds for RPS*/
3822 I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
3823 I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
3824 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3825 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3826
3827 /* Docs recommend 900MHz, and 300 MHz respectively */
3828 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3829 dev_priv->rps.max_delay << 24 |
3830 dev_priv->rps.min_delay << 16);
3831
3832 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3833 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3834 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3835 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3836
3837 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3838
3839 /* 5: Enable RPS */
3840 I915_WRITE(GEN6_RP_CONTROL,
3841 GEN6_RP_MEDIA_TURBO |
3842 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3843 GEN6_RP_MEDIA_IS_GFX |
3844 GEN6_RP_ENABLE |
3845 GEN6_RP_UP_BUSY_AVG |
3846 GEN6_RP_DOWN_IDLE_AVG);
3847
3848 /* 6: Ring frequency + overclocking (our driver does this later */
3849
3850 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3851
3852 gen6_enable_rps_interrupts(dev);
3853
3854 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3855 }
3856
3857 static void gen6_enable_rps(struct drm_device *dev)
3858 {
3859 struct drm_i915_private *dev_priv = dev->dev_private;
3860 struct intel_ring_buffer *ring;
3861 u32 rp_state_cap;
3862 u32 gt_perf_status;
3863 u32 rc6vids, pcu_mbox, rc6_mask = 0;
3864 u32 gtfifodbg;
3865 int rc6_mode;
3866 int i, ret;
3867
3868 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3869
3870 /* Here begins a magic sequence of register writes to enable
3871 * auto-downclocking.
3872 *
3873 * Perhaps there might be some value in exposing these to
3874 * userspace...
3875 */
3876 I915_WRITE(GEN6_RC_STATE, 0);
3877
3878 /* Clear the DBG now so we don't confuse earlier errors */
3879 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3880 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3881 I915_WRITE(GTFIFODBG, gtfifodbg);
3882 }
3883
3884 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3885
3886 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3887 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3888
3889 /* In units of 50MHz */
3890 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3891 dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3892 dev_priv->rps.rp1_delay = (rp_state_cap >> 8) & 0xff;
3893 dev_priv->rps.rp0_delay = (rp_state_cap >> 0) & 0xff;
3894 dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
3895 dev_priv->rps.cur_delay = 0;
3896
3897 /* disable the counters and set deterministic thresholds */
3898 I915_WRITE(GEN6_RC_CONTROL, 0);
3899
3900 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3901 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3902 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3903 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3904 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3905
3906 for_each_ring(ring, dev_priv, i)
3907 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3908
3909 I915_WRITE(GEN6_RC_SLEEP, 0);
3910 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3911 if (IS_IVYBRIDGE(dev))
3912 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3913 else
3914 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3915 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3916 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3917
3918 /* Check if we are enabling RC6 */
3919 rc6_mode = intel_enable_rc6(dev_priv->dev);
3920 if (rc6_mode & INTEL_RC6_ENABLE)
3921 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3922
3923 /* We don't use those on Haswell */
3924 if (!IS_HASWELL(dev)) {
3925 if (rc6_mode & INTEL_RC6p_ENABLE)
3926 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3927
3928 if (rc6_mode & INTEL_RC6pp_ENABLE)
3929 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3930 }
3931
3932 intel_print_rc6_info(dev, rc6_mask);
3933
3934 I915_WRITE(GEN6_RC_CONTROL,
3935 rc6_mask |
3936 GEN6_RC_CTL_EI_MODE(1) |
3937 GEN6_RC_CTL_HW_ENABLE);
3938
3939 /* Power down if completely idle for over 50ms */
3940 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3941 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3942
3943 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3944 if (!ret) {
3945 pcu_mbox = 0;
3946 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3947 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3948 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3949 (dev_priv->rps.max_delay & 0xff) * 50,
3950 (pcu_mbox & 0xff) * 50);
3951 dev_priv->rps.hw_max = pcu_mbox & 0xff;
3952 }
3953 } else {
3954 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3955 }
3956
3957 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3958 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3959
3960 gen6_enable_rps_interrupts(dev);
3961
3962 rc6vids = 0;
3963 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3964 if (IS_GEN6(dev) && ret) {
3965 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3966 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3967 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3968 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3969 rc6vids &= 0xffff00;
3970 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3971 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3972 if (ret)
3973 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3974 }
3975
3976 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3977 }
3978
3979 void gen6_update_ring_freq(struct drm_device *dev)
3980 {
3981 struct drm_i915_private *dev_priv = dev->dev_private;
3982 int min_freq = 15;
3983 unsigned int gpu_freq;
3984 unsigned int max_ia_freq, min_ring_freq;
3985 int scaling_factor = 180;
3986 struct cpufreq_policy *policy;
3987
3988 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3989
3990 policy = cpufreq_cpu_get(0);
3991 if (policy) {
3992 max_ia_freq = policy->cpuinfo.max_freq;
3993 cpufreq_cpu_put(policy);
3994 } else {
3995 /*
3996 * Default to measured freq if none found, PCU will ensure we
3997 * don't go over
3998 */
3999 max_ia_freq = tsc_khz;
4000 }
4001
4002 /* Convert from kHz to MHz */
4003 max_ia_freq /= 1000;
4004
4005 min_ring_freq = I915_READ(DCLK) & 0xf;
4006 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4007 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
4008
4009 /*
4010 * For each potential GPU frequency, load a ring frequency we'd like
4011 * to use for memory access. We do this by specifying the IA frequency
4012 * the PCU should use as a reference to determine the ring frequency.
4013 */
4014 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
4015 gpu_freq--) {
4016 int diff = dev_priv->rps.max_delay - gpu_freq;
4017 unsigned int ia_freq = 0, ring_freq = 0;
4018
4019 if (INTEL_INFO(dev)->gen >= 8) {
4020 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4021 ring_freq = max(min_ring_freq, gpu_freq);
4022 } else if (IS_HASWELL(dev)) {
4023 ring_freq = mult_frac(gpu_freq, 5, 4);
4024 ring_freq = max(min_ring_freq, ring_freq);
4025 /* leave ia_freq as the default, chosen by cpufreq */
4026 } else {
4027 /* On older processors, there is no separate ring
4028 * clock domain, so in order to boost the bandwidth
4029 * of the ring, we need to upclock the CPU (ia_freq).
4030 *
4031 * For GPU frequencies less than 750MHz,
4032 * just use the lowest ring freq.
4033 */
4034 if (gpu_freq < min_freq)
4035 ia_freq = 800;
4036 else
4037 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4038 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4039 }
4040
4041 sandybridge_pcode_write(dev_priv,
4042 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
4043 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4044 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4045 gpu_freq);
4046 }
4047 }
4048
4049 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
4050 {
4051 u32 val, rp0;
4052
4053 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4054
4055 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4056 /* Clamp to max */
4057 rp0 = min_t(u32, rp0, 0xea);
4058
4059 return rp0;
4060 }
4061
4062 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4063 {
4064 u32 val, rpe;
4065
4066 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
4067 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
4068 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
4069 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4070
4071 return rpe;
4072 }
4073
4074 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
4075 {
4076 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
4077 }
4078
4079 static void valleyview_setup_pctx(struct drm_device *dev)
4080 {
4081 struct drm_i915_private *dev_priv = dev->dev_private;
4082 struct drm_i915_gem_object *pctx;
4083 unsigned long pctx_paddr;
4084 u32 pcbr;
4085 int pctx_size = 24*1024;
4086
4087 pcbr = I915_READ(VLV_PCBR);
4088 if (pcbr) {
4089 /* BIOS set it up already, grab the pre-alloc'd space */
4090 int pcbr_offset;
4091
4092 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4093 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4094 pcbr_offset,
4095 I915_GTT_OFFSET_NONE,
4096 pctx_size);
4097 goto out;
4098 }
4099
4100 /*
4101 * From the Gunit register HAS:
4102 * The Gfx driver is expected to program this register and ensure
4103 * proper allocation within Gfx stolen memory. For example, this
4104 * register should be programmed such than the PCBR range does not
4105 * overlap with other ranges, such as the frame buffer, protected
4106 * memory, or any other relevant ranges.
4107 */
4108 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4109 if (!pctx) {
4110 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4111 return;
4112 }
4113
4114 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4115 I915_WRITE(VLV_PCBR, pctx_paddr);
4116
4117 out:
4118 dev_priv->vlv_pctx = pctx;
4119 }
4120
4121 static void valleyview_enable_rps(struct drm_device *dev)
4122 {
4123 struct drm_i915_private *dev_priv = dev->dev_private;
4124 struct intel_ring_buffer *ring;
4125 u32 gtfifodbg, val, rc6_mode = 0;
4126 int i;
4127
4128 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4129
4130 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4131 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4132 gtfifodbg);
4133 I915_WRITE(GTFIFODBG, gtfifodbg);
4134 }
4135
4136 valleyview_setup_pctx(dev);
4137
4138 /* If VLV, Forcewake all wells, else re-direct to regular path */
4139 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4140
4141 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4142 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4143 I915_WRITE(GEN6_RP_UP_EI, 66000);
4144 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4145
4146 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4147
4148 I915_WRITE(GEN6_RP_CONTROL,
4149 GEN6_RP_MEDIA_TURBO |
4150 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4151 GEN6_RP_MEDIA_IS_GFX |
4152 GEN6_RP_ENABLE |
4153 GEN6_RP_UP_BUSY_AVG |
4154 GEN6_RP_DOWN_IDLE_CONT);
4155
4156 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4157 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4158 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4159
4160 for_each_ring(ring, dev_priv, i)
4161 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4162
4163 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
4164
4165 /* allows RC6 residency counter to work */
4166 I915_WRITE(VLV_COUNTER_CONTROL,
4167 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4168 VLV_MEDIA_RC6_COUNT_EN |
4169 VLV_RENDER_RC6_COUNT_EN));
4170 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4171 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
4172
4173 intel_print_rc6_info(dev, rc6_mode);
4174
4175 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4176
4177 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4178
4179 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4180 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4181
4182 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
4183 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4184 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
4185 dev_priv->rps.cur_delay);
4186
4187 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
4188 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
4189 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4190 vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay),
4191 dev_priv->rps.max_delay);
4192
4193 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
4194 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4195 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
4196 dev_priv->rps.rpe_delay);
4197
4198 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
4199 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4200 vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay),
4201 dev_priv->rps.min_delay);
4202
4203 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4204 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
4205 dev_priv->rps.rpe_delay);
4206
4207 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
4208
4209 gen6_enable_rps_interrupts(dev);
4210
4211 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4212 }
4213
4214 void ironlake_teardown_rc6(struct drm_device *dev)
4215 {
4216 struct drm_i915_private *dev_priv = dev->dev_private;
4217
4218 if (dev_priv->ips.renderctx) {
4219 i915_gem_object_unpin(dev_priv->ips.renderctx);
4220 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4221 dev_priv->ips.renderctx = NULL;
4222 }
4223
4224 if (dev_priv->ips.pwrctx) {
4225 i915_gem_object_unpin(dev_priv->ips.pwrctx);
4226 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4227 dev_priv->ips.pwrctx = NULL;
4228 }
4229 }
4230
4231 static void ironlake_disable_rc6(struct drm_device *dev)
4232 {
4233 struct drm_i915_private *dev_priv = dev->dev_private;
4234
4235 if (I915_READ(PWRCTXA)) {
4236 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4237 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4238 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4239 50);
4240
4241 I915_WRITE(PWRCTXA, 0);
4242 POSTING_READ(PWRCTXA);
4243
4244 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4245 POSTING_READ(RSTDBYCTL);
4246 }
4247 }
4248
4249 static int ironlake_setup_rc6(struct drm_device *dev)
4250 {
4251 struct drm_i915_private *dev_priv = dev->dev_private;
4252
4253 if (dev_priv->ips.renderctx == NULL)
4254 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4255 if (!dev_priv->ips.renderctx)
4256 return -ENOMEM;
4257
4258 if (dev_priv->ips.pwrctx == NULL)
4259 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4260 if (!dev_priv->ips.pwrctx) {
4261 ironlake_teardown_rc6(dev);
4262 return -ENOMEM;
4263 }
4264
4265 return 0;
4266 }
4267
4268 static void ironlake_enable_rc6(struct drm_device *dev)
4269 {
4270 struct drm_i915_private *dev_priv = dev->dev_private;
4271 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
4272 bool was_interruptible;
4273 int ret;
4274
4275 /* rc6 disabled by default due to repeated reports of hanging during
4276 * boot and resume.
4277 */
4278 if (!intel_enable_rc6(dev))
4279 return;
4280
4281 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4282
4283 ret = ironlake_setup_rc6(dev);
4284 if (ret)
4285 return;
4286
4287 was_interruptible = dev_priv->mm.interruptible;
4288 dev_priv->mm.interruptible = false;
4289
4290 /*
4291 * GPU can automatically power down the render unit if given a page
4292 * to save state.
4293 */
4294 ret = intel_ring_begin(ring, 6);
4295 if (ret) {
4296 ironlake_teardown_rc6(dev);
4297 dev_priv->mm.interruptible = was_interruptible;
4298 return;
4299 }
4300
4301 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4302 intel_ring_emit(ring, MI_SET_CONTEXT);
4303 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4304 MI_MM_SPACE_GTT |
4305 MI_SAVE_EXT_STATE_EN |
4306 MI_RESTORE_EXT_STATE_EN |
4307 MI_RESTORE_INHIBIT);
4308 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4309 intel_ring_emit(ring, MI_NOOP);
4310 intel_ring_emit(ring, MI_FLUSH);
4311 intel_ring_advance(ring);
4312
4313 /*
4314 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4315 * does an implicit flush, combined with MI_FLUSH above, it should be
4316 * safe to assume that renderctx is valid
4317 */
4318 ret = intel_ring_idle(ring);
4319 dev_priv->mm.interruptible = was_interruptible;
4320 if (ret) {
4321 DRM_ERROR("failed to enable ironlake power savings\n");
4322 ironlake_teardown_rc6(dev);
4323 return;
4324 }
4325
4326 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4327 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4328
4329 intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
4330 }
4331
4332 static unsigned long intel_pxfreq(u32 vidfreq)
4333 {
4334 unsigned long freq;
4335 int div = (vidfreq & 0x3f0000) >> 16;
4336 int post = (vidfreq & 0x3000) >> 12;
4337 int pre = (vidfreq & 0x7);
4338
4339 if (!pre)
4340 return 0;
4341
4342 freq = ((div * 133333) / ((1<<post) * pre));
4343
4344 return freq;
4345 }
4346
4347 static const struct cparams {
4348 u16 i;
4349 u16 t;
4350 u16 m;
4351 u16 c;
4352 } cparams[] = {
4353 { 1, 1333, 301, 28664 },
4354 { 1, 1066, 294, 24460 },
4355 { 1, 800, 294, 25192 },
4356 { 0, 1333, 276, 27605 },
4357 { 0, 1066, 276, 27605 },
4358 { 0, 800, 231, 23784 },
4359 };
4360
4361 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4362 {
4363 u64 total_count, diff, ret;
4364 u32 count1, count2, count3, m = 0, c = 0;
4365 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4366 int i;
4367
4368 assert_spin_locked(&mchdev_lock);
4369
4370 diff1 = now - dev_priv->ips.last_time1;
4371
4372 /* Prevent division-by-zero if we are asking too fast.
4373 * Also, we don't get interesting results if we are polling
4374 * faster than once in 10ms, so just return the saved value
4375 * in such cases.
4376 */
4377 if (diff1 <= 10)
4378 return dev_priv->ips.chipset_power;
4379
4380 count1 = I915_READ(DMIEC);
4381 count2 = I915_READ(DDREC);
4382 count3 = I915_READ(CSIEC);
4383
4384 total_count = count1 + count2 + count3;
4385
4386 /* FIXME: handle per-counter overflow */
4387 if (total_count < dev_priv->ips.last_count1) {
4388 diff = ~0UL - dev_priv->ips.last_count1;
4389 diff += total_count;
4390 } else {
4391 diff = total_count - dev_priv->ips.last_count1;
4392 }
4393
4394 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4395 if (cparams[i].i == dev_priv->ips.c_m &&
4396 cparams[i].t == dev_priv->ips.r_t) {
4397 m = cparams[i].m;
4398 c = cparams[i].c;
4399 break;
4400 }
4401 }
4402
4403 diff = div_u64(diff, diff1);
4404 ret = ((m * diff) + c);
4405 ret = div_u64(ret, 10);
4406
4407 dev_priv->ips.last_count1 = total_count;
4408 dev_priv->ips.last_time1 = now;
4409
4410 dev_priv->ips.chipset_power = ret;
4411
4412 return ret;
4413 }
4414
4415 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4416 {
4417 unsigned long val;
4418
4419 if (dev_priv->info->gen != 5)
4420 return 0;
4421
4422 spin_lock_irq(&mchdev_lock);
4423
4424 val = __i915_chipset_val(dev_priv);
4425
4426 spin_unlock_irq(&mchdev_lock);
4427
4428 return val;
4429 }
4430
4431 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4432 {
4433 unsigned long m, x, b;
4434 u32 tsfs;
4435
4436 tsfs = I915_READ(TSFS);
4437
4438 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4439 x = I915_READ8(TR1);
4440
4441 b = tsfs & TSFS_INTR_MASK;
4442
4443 return ((m * x) / 127) - b;
4444 }
4445
4446 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4447 {
4448 static const struct v_table {
4449 u16 vd; /* in .1 mil */
4450 u16 vm; /* in .1 mil */
4451 } v_table[] = {
4452 { 0, 0, },
4453 { 375, 0, },
4454 { 500, 0, },
4455 { 625, 0, },
4456 { 750, 0, },
4457 { 875, 0, },
4458 { 1000, 0, },
4459 { 1125, 0, },
4460 { 4125, 3000, },
4461 { 4125, 3000, },
4462 { 4125, 3000, },
4463 { 4125, 3000, },
4464 { 4125, 3000, },
4465 { 4125, 3000, },
4466 { 4125, 3000, },
4467 { 4125, 3000, },
4468 { 4125, 3000, },
4469 { 4125, 3000, },
4470 { 4125, 3000, },
4471 { 4125, 3000, },
4472 { 4125, 3000, },
4473 { 4125, 3000, },
4474 { 4125, 3000, },
4475 { 4125, 3000, },
4476 { 4125, 3000, },
4477 { 4125, 3000, },
4478 { 4125, 3000, },
4479 { 4125, 3000, },
4480 { 4125, 3000, },
4481 { 4125, 3000, },
4482 { 4125, 3000, },
4483 { 4125, 3000, },
4484 { 4250, 3125, },
4485 { 4375, 3250, },
4486 { 4500, 3375, },
4487 { 4625, 3500, },
4488 { 4750, 3625, },
4489 { 4875, 3750, },
4490 { 5000, 3875, },
4491 { 5125, 4000, },
4492 { 5250, 4125, },
4493 { 5375, 4250, },
4494 { 5500, 4375, },
4495 { 5625, 4500, },
4496 { 5750, 4625, },
4497 { 5875, 4750, },
4498 { 6000, 4875, },
4499 { 6125, 5000, },
4500 { 6250, 5125, },
4501 { 6375, 5250, },
4502 { 6500, 5375, },
4503 { 6625, 5500, },
4504 { 6750, 5625, },
4505 { 6875, 5750, },
4506 { 7000, 5875, },
4507 { 7125, 6000, },
4508 { 7250, 6125, },
4509 { 7375, 6250, },
4510 { 7500, 6375, },
4511 { 7625, 6500, },
4512 { 7750, 6625, },
4513 { 7875, 6750, },
4514 { 8000, 6875, },
4515 { 8125, 7000, },
4516 { 8250, 7125, },
4517 { 8375, 7250, },
4518 { 8500, 7375, },
4519 { 8625, 7500, },
4520 { 8750, 7625, },
4521 { 8875, 7750, },
4522 { 9000, 7875, },
4523 { 9125, 8000, },
4524 { 9250, 8125, },
4525 { 9375, 8250, },
4526 { 9500, 8375, },
4527 { 9625, 8500, },
4528 { 9750, 8625, },
4529 { 9875, 8750, },
4530 { 10000, 8875, },
4531 { 10125, 9000, },
4532 { 10250, 9125, },
4533 { 10375, 9250, },
4534 { 10500, 9375, },
4535 { 10625, 9500, },
4536 { 10750, 9625, },
4537 { 10875, 9750, },
4538 { 11000, 9875, },
4539 { 11125, 10000, },
4540 { 11250, 10125, },
4541 { 11375, 10250, },
4542 { 11500, 10375, },
4543 { 11625, 10500, },
4544 { 11750, 10625, },
4545 { 11875, 10750, },
4546 { 12000, 10875, },
4547 { 12125, 11000, },
4548 { 12250, 11125, },
4549 { 12375, 11250, },
4550 { 12500, 11375, },
4551 { 12625, 11500, },
4552 { 12750, 11625, },
4553 { 12875, 11750, },
4554 { 13000, 11875, },
4555 { 13125, 12000, },
4556 { 13250, 12125, },
4557 { 13375, 12250, },
4558 { 13500, 12375, },
4559 { 13625, 12500, },
4560 { 13750, 12625, },
4561 { 13875, 12750, },
4562 { 14000, 12875, },
4563 { 14125, 13000, },
4564 { 14250, 13125, },
4565 { 14375, 13250, },
4566 { 14500, 13375, },
4567 { 14625, 13500, },
4568 { 14750, 13625, },
4569 { 14875, 13750, },
4570 { 15000, 13875, },
4571 { 15125, 14000, },
4572 { 15250, 14125, },
4573 { 15375, 14250, },
4574 { 15500, 14375, },
4575 { 15625, 14500, },
4576 { 15750, 14625, },
4577 { 15875, 14750, },
4578 { 16000, 14875, },
4579 { 16125, 15000, },
4580 };
4581 if (dev_priv->info->is_mobile)
4582 return v_table[pxvid].vm;
4583 else
4584 return v_table[pxvid].vd;
4585 }
4586
4587 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4588 {
4589 struct timespec now, diff1;
4590 u64 diff;
4591 unsigned long diffms;
4592 u32 count;
4593
4594 assert_spin_locked(&mchdev_lock);
4595
4596 getrawmonotonic(&now);
4597 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4598
4599 /* Don't divide by 0 */
4600 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4601 if (!diffms)
4602 return;
4603
4604 count = I915_READ(GFXEC);
4605
4606 if (count < dev_priv->ips.last_count2) {
4607 diff = ~0UL - dev_priv->ips.last_count2;
4608 diff += count;
4609 } else {
4610 diff = count - dev_priv->ips.last_count2;
4611 }
4612
4613 dev_priv->ips.last_count2 = count;
4614 dev_priv->ips.last_time2 = now;
4615
4616 /* More magic constants... */
4617 diff = diff * 1181;
4618 diff = div_u64(diff, diffms * 10);
4619 dev_priv->ips.gfx_power = diff;
4620 }
4621
4622 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4623 {
4624 if (dev_priv->info->gen != 5)
4625 return;
4626
4627 spin_lock_irq(&mchdev_lock);
4628
4629 __i915_update_gfx_val(dev_priv);
4630
4631 spin_unlock_irq(&mchdev_lock);
4632 }
4633
4634 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4635 {
4636 unsigned long t, corr, state1, corr2, state2;
4637 u32 pxvid, ext_v;
4638
4639 assert_spin_locked(&mchdev_lock);
4640
4641 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
4642 pxvid = (pxvid >> 24) & 0x7f;
4643 ext_v = pvid_to_extvid(dev_priv, pxvid);
4644
4645 state1 = ext_v;
4646
4647 t = i915_mch_val(dev_priv);
4648
4649 /* Revel in the empirically derived constants */
4650
4651 /* Correction factor in 1/100000 units */
4652 if (t > 80)
4653 corr = ((t * 2349) + 135940);
4654 else if (t >= 50)
4655 corr = ((t * 964) + 29317);
4656 else /* < 50 */
4657 corr = ((t * 301) + 1004);
4658
4659 corr = corr * ((150142 * state1) / 10000 - 78642);
4660 corr /= 100000;
4661 corr2 = (corr * dev_priv->ips.corr);
4662
4663 state2 = (corr2 * state1) / 10000;
4664 state2 /= 100; /* convert to mW */
4665
4666 __i915_update_gfx_val(dev_priv);
4667
4668 return dev_priv->ips.gfx_power + state2;
4669 }
4670
4671 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4672 {
4673 unsigned long val;
4674
4675 if (dev_priv->info->gen != 5)
4676 return 0;
4677
4678 spin_lock_irq(&mchdev_lock);
4679
4680 val = __i915_gfx_val(dev_priv);
4681
4682 spin_unlock_irq(&mchdev_lock);
4683
4684 return val;
4685 }
4686
4687 /**
4688 * i915_read_mch_val - return value for IPS use
4689 *
4690 * Calculate and return a value for the IPS driver to use when deciding whether
4691 * we have thermal and power headroom to increase CPU or GPU power budget.
4692 */
4693 unsigned long i915_read_mch_val(void)
4694 {
4695 struct drm_i915_private *dev_priv;
4696 unsigned long chipset_val, graphics_val, ret = 0;
4697
4698 spin_lock_irq(&mchdev_lock);
4699 if (!i915_mch_dev)
4700 goto out_unlock;
4701 dev_priv = i915_mch_dev;
4702
4703 chipset_val = __i915_chipset_val(dev_priv);
4704 graphics_val = __i915_gfx_val(dev_priv);
4705
4706 ret = chipset_val + graphics_val;
4707
4708 out_unlock:
4709 spin_unlock_irq(&mchdev_lock);
4710
4711 return ret;
4712 }
4713 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4714
4715 /**
4716 * i915_gpu_raise - raise GPU frequency limit
4717 *
4718 * Raise the limit; IPS indicates we have thermal headroom.
4719 */
4720 bool i915_gpu_raise(void)
4721 {
4722 struct drm_i915_private *dev_priv;
4723 bool ret = true;
4724
4725 spin_lock_irq(&mchdev_lock);
4726 if (!i915_mch_dev) {
4727 ret = false;
4728 goto out_unlock;
4729 }
4730 dev_priv = i915_mch_dev;
4731
4732 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4733 dev_priv->ips.max_delay--;
4734
4735 out_unlock:
4736 spin_unlock_irq(&mchdev_lock);
4737
4738 return ret;
4739 }
4740 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4741
4742 /**
4743 * i915_gpu_lower - lower GPU frequency limit
4744 *
4745 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4746 * frequency maximum.
4747 */
4748 bool i915_gpu_lower(void)
4749 {
4750 struct drm_i915_private *dev_priv;
4751 bool ret = true;
4752
4753 spin_lock_irq(&mchdev_lock);
4754 if (!i915_mch_dev) {
4755 ret = false;
4756 goto out_unlock;
4757 }
4758 dev_priv = i915_mch_dev;
4759
4760 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4761 dev_priv->ips.max_delay++;
4762
4763 out_unlock:
4764 spin_unlock_irq(&mchdev_lock);
4765
4766 return ret;
4767 }
4768 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4769
4770 /**
4771 * i915_gpu_busy - indicate GPU business to IPS
4772 *
4773 * Tell the IPS driver whether or not the GPU is busy.
4774 */
4775 bool i915_gpu_busy(void)
4776 {
4777 struct drm_i915_private *dev_priv;
4778 struct intel_ring_buffer *ring;
4779 bool ret = false;
4780 int i;
4781
4782 spin_lock_irq(&mchdev_lock);
4783 if (!i915_mch_dev)
4784 goto out_unlock;
4785 dev_priv = i915_mch_dev;
4786
4787 for_each_ring(ring, dev_priv, i)
4788 ret |= !list_empty(&ring->request_list);
4789
4790 out_unlock:
4791 spin_unlock_irq(&mchdev_lock);
4792
4793 return ret;
4794 }
4795 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4796
4797 /**
4798 * i915_gpu_turbo_disable - disable graphics turbo
4799 *
4800 * Disable graphics turbo by resetting the max frequency and setting the
4801 * current frequency to the default.
4802 */
4803 bool i915_gpu_turbo_disable(void)
4804 {
4805 struct drm_i915_private *dev_priv;
4806 bool ret = true;
4807
4808 spin_lock_irq(&mchdev_lock);
4809 if (!i915_mch_dev) {
4810 ret = false;
4811 goto out_unlock;
4812 }
4813 dev_priv = i915_mch_dev;
4814
4815 dev_priv->ips.max_delay = dev_priv->ips.fstart;
4816
4817 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4818 ret = false;
4819
4820 out_unlock:
4821 spin_unlock_irq(&mchdev_lock);
4822
4823 return ret;
4824 }
4825 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4826
4827 /**
4828 * Tells the intel_ips driver that the i915 driver is now loaded, if
4829 * IPS got loaded first.
4830 *
4831 * This awkward dance is so that neither module has to depend on the
4832 * other in order for IPS to do the appropriate communication of
4833 * GPU turbo limits to i915.
4834 */
4835 static void
4836 ips_ping_for_i915_load(void)
4837 {
4838 void (*link)(void);
4839
4840 link = symbol_get(ips_link_to_i915_driver);
4841 if (link) {
4842 link();
4843 symbol_put(ips_link_to_i915_driver);
4844 }
4845 }
4846
4847 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4848 {
4849 /* We only register the i915 ips part with intel-ips once everything is
4850 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4851 spin_lock_irq(&mchdev_lock);
4852 i915_mch_dev = dev_priv;
4853 spin_unlock_irq(&mchdev_lock);
4854
4855 ips_ping_for_i915_load();
4856 }
4857
4858 void intel_gpu_ips_teardown(void)
4859 {
4860 spin_lock_irq(&mchdev_lock);
4861 i915_mch_dev = NULL;
4862 spin_unlock_irq(&mchdev_lock);
4863 }
4864 static void intel_init_emon(struct drm_device *dev)
4865 {
4866 struct drm_i915_private *dev_priv = dev->dev_private;
4867 u32 lcfuse;
4868 u8 pxw[16];
4869 int i;
4870
4871 /* Disable to program */
4872 I915_WRITE(ECR, 0);
4873 POSTING_READ(ECR);
4874
4875 /* Program energy weights for various events */
4876 I915_WRITE(SDEW, 0x15040d00);
4877 I915_WRITE(CSIEW0, 0x007f0000);
4878 I915_WRITE(CSIEW1, 0x1e220004);
4879 I915_WRITE(CSIEW2, 0x04000004);
4880
4881 for (i = 0; i < 5; i++)
4882 I915_WRITE(PEW + (i * 4), 0);
4883 for (i = 0; i < 3; i++)
4884 I915_WRITE(DEW + (i * 4), 0);
4885
4886 /* Program P-state weights to account for frequency power adjustment */
4887 for (i = 0; i < 16; i++) {
4888 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4889 unsigned long freq = intel_pxfreq(pxvidfreq);
4890 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4891 PXVFREQ_PX_SHIFT;
4892 unsigned long val;
4893
4894 val = vid * vid;
4895 val *= (freq / 1000);
4896 val *= 255;
4897 val /= (127*127*900);
4898 if (val > 0xff)
4899 DRM_ERROR("bad pxval: %ld\n", val);
4900 pxw[i] = val;
4901 }
4902 /* Render standby states get 0 weight */
4903 pxw[14] = 0;
4904 pxw[15] = 0;
4905
4906 for (i = 0; i < 4; i++) {
4907 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4908 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4909 I915_WRITE(PXW + (i * 4), val);
4910 }
4911
4912 /* Adjust magic regs to magic values (more experimental results) */
4913 I915_WRITE(OGW0, 0);
4914 I915_WRITE(OGW1, 0);
4915 I915_WRITE(EG0, 0x00007f00);
4916 I915_WRITE(EG1, 0x0000000e);
4917 I915_WRITE(EG2, 0x000e0000);
4918 I915_WRITE(EG3, 0x68000300);
4919 I915_WRITE(EG4, 0x42000000);
4920 I915_WRITE(EG5, 0x00140031);
4921 I915_WRITE(EG6, 0);
4922 I915_WRITE(EG7, 0);
4923
4924 for (i = 0; i < 8; i++)
4925 I915_WRITE(PXWL + (i * 4), 0);
4926
4927 /* Enable PMON + select events */
4928 I915_WRITE(ECR, 0x80000019);
4929
4930 lcfuse = I915_READ(LCFUSE02);
4931
4932 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4933 }
4934
4935 void intel_disable_gt_powersave(struct drm_device *dev)
4936 {
4937 struct drm_i915_private *dev_priv = dev->dev_private;
4938
4939 /* Interrupts should be disabled already to avoid re-arming. */
4940 WARN_ON(dev->irq_enabled);
4941
4942 if (IS_IRONLAKE_M(dev)) {
4943 ironlake_disable_drps(dev);
4944 ironlake_disable_rc6(dev);
4945 } else if (INTEL_INFO(dev)->gen >= 6) {
4946 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4947 cancel_work_sync(&dev_priv->rps.work);
4948 mutex_lock(&dev_priv->rps.hw_lock);
4949 if (IS_VALLEYVIEW(dev))
4950 valleyview_disable_rps(dev);
4951 else
4952 gen6_disable_rps(dev);
4953 dev_priv->rps.enabled = false;
4954 mutex_unlock(&dev_priv->rps.hw_lock);
4955 }
4956 }
4957
4958 static void intel_gen6_powersave_work(struct work_struct *work)
4959 {
4960 struct drm_i915_private *dev_priv =
4961 container_of(work, struct drm_i915_private,
4962 rps.delayed_resume_work.work);
4963 struct drm_device *dev = dev_priv->dev;
4964
4965 mutex_lock(&dev_priv->rps.hw_lock);
4966
4967 if (IS_VALLEYVIEW(dev)) {
4968 valleyview_enable_rps(dev);
4969 } else if (IS_BROADWELL(dev)) {
4970 gen8_enable_rps(dev);
4971 gen6_update_ring_freq(dev);
4972 } else {
4973 gen6_enable_rps(dev);
4974 gen6_update_ring_freq(dev);
4975 }
4976 dev_priv->rps.enabled = true;
4977 mutex_unlock(&dev_priv->rps.hw_lock);
4978 }
4979
4980 void intel_enable_gt_powersave(struct drm_device *dev)
4981 {
4982 struct drm_i915_private *dev_priv = dev->dev_private;
4983
4984 if (IS_IRONLAKE_M(dev)) {
4985 ironlake_enable_drps(dev);
4986 ironlake_enable_rc6(dev);
4987 intel_init_emon(dev);
4988 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4989 /*
4990 * PCU communication is slow and this doesn't need to be
4991 * done at any specific time, so do this out of our fast path
4992 * to make resume and init faster.
4993 */
4994 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4995 round_jiffies_up_relative(HZ));
4996 }
4997 }
4998
4999 static void ibx_init_clock_gating(struct drm_device *dev)
5000 {
5001 struct drm_i915_private *dev_priv = dev->dev_private;
5002
5003 /*
5004 * On Ibex Peak and Cougar Point, we need to disable clock
5005 * gating for the panel power sequencer or it will fail to
5006 * start up when no ports are active.
5007 */
5008 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5009 }
5010
5011 static void g4x_disable_trickle_feed(struct drm_device *dev)
5012 {
5013 struct drm_i915_private *dev_priv = dev->dev_private;
5014 int pipe;
5015
5016 for_each_pipe(pipe) {
5017 I915_WRITE(DSPCNTR(pipe),
5018 I915_READ(DSPCNTR(pipe)) |
5019 DISPPLANE_TRICKLE_FEED_DISABLE);
5020 intel_flush_primary_plane(dev_priv, pipe);
5021 }
5022 }
5023
5024 static void ironlake_init_clock_gating(struct drm_device *dev)
5025 {
5026 struct drm_i915_private *dev_priv = dev->dev_private;
5027 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5028
5029 /*
5030 * Required for FBC
5031 * WaFbcDisableDpfcClockGating:ilk
5032 */
5033 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5034 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5035 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
5036
5037 I915_WRITE(PCH_3DCGDIS0,
5038 MARIUNIT_CLOCK_GATE_DISABLE |
5039 SVSMUNIT_CLOCK_GATE_DISABLE);
5040 I915_WRITE(PCH_3DCGDIS1,
5041 VFMUNIT_CLOCK_GATE_DISABLE);
5042
5043 /*
5044 * According to the spec the following bits should be set in
5045 * order to enable memory self-refresh
5046 * The bit 22/21 of 0x42004
5047 * The bit 5 of 0x42020
5048 * The bit 15 of 0x45000
5049 */
5050 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5051 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5052 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5053 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5054 I915_WRITE(DISP_ARB_CTL,
5055 (I915_READ(DISP_ARB_CTL) |
5056 DISP_FBC_WM_DIS));
5057 I915_WRITE(WM3_LP_ILK, 0);
5058 I915_WRITE(WM2_LP_ILK, 0);
5059 I915_WRITE(WM1_LP_ILK, 0);
5060
5061 /*
5062 * Based on the document from hardware guys the following bits
5063 * should be set unconditionally in order to enable FBC.
5064 * The bit 22 of 0x42000
5065 * The bit 22 of 0x42004
5066 * The bit 7,8,9 of 0x42020.
5067 */
5068 if (IS_IRONLAKE_M(dev)) {
5069 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5070 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5071 I915_READ(ILK_DISPLAY_CHICKEN1) |
5072 ILK_FBCQ_DIS);
5073 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5074 I915_READ(ILK_DISPLAY_CHICKEN2) |
5075 ILK_DPARB_GATE);
5076 }
5077
5078 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5079
5080 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5081 I915_READ(ILK_DISPLAY_CHICKEN2) |
5082 ILK_ELPIN_409_SELECT);
5083 I915_WRITE(_3D_CHICKEN2,
5084 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5085 _3D_CHICKEN2_WM_READ_PIPELINED);
5086
5087 /* WaDisableRenderCachePipelinedFlush:ilk */
5088 I915_WRITE(CACHE_MODE_0,
5089 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5090
5091 g4x_disable_trickle_feed(dev);
5092
5093 ibx_init_clock_gating(dev);
5094 }
5095
5096 static void cpt_init_clock_gating(struct drm_device *dev)
5097 {
5098 struct drm_i915_private *dev_priv = dev->dev_private;
5099 int pipe;
5100 uint32_t val;
5101
5102 /*
5103 * On Ibex Peak and Cougar Point, we need to disable clock
5104 * gating for the panel power sequencer or it will fail to
5105 * start up when no ports are active.
5106 */
5107 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5108 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5109 PCH_CPUNIT_CLOCK_GATE_DISABLE);
5110 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5111 DPLS_EDP_PPS_FIX_DIS);
5112 /* The below fixes the weird display corruption, a few pixels shifted
5113 * downward, on (only) LVDS of some HP laptops with IVY.
5114 */
5115 for_each_pipe(pipe) {
5116 val = I915_READ(TRANS_CHICKEN2(pipe));
5117 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5118 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5119 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5120 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5121 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5122 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5123 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5124 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5125 }
5126 /* WADP0ClockGatingDisable */
5127 for_each_pipe(pipe) {
5128 I915_WRITE(TRANS_CHICKEN1(pipe),
5129 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5130 }
5131 }
5132
5133 static void gen6_check_mch_setup(struct drm_device *dev)
5134 {
5135 struct drm_i915_private *dev_priv = dev->dev_private;
5136 uint32_t tmp;
5137
5138 tmp = I915_READ(MCH_SSKPD);
5139 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
5140 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
5141 DRM_INFO("This can cause pipe underruns and display issues.\n");
5142 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5143 }
5144 }
5145
5146 static void gen6_init_clock_gating(struct drm_device *dev)
5147 {
5148 struct drm_i915_private *dev_priv = dev->dev_private;
5149 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5150
5151 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5152
5153 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5154 I915_READ(ILK_DISPLAY_CHICKEN2) |
5155 ILK_ELPIN_409_SELECT);
5156
5157 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5158 I915_WRITE(_3D_CHICKEN,
5159 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5160
5161 /* WaSetupGtModeTdRowDispatch:snb */
5162 if (IS_SNB_GT1(dev))
5163 I915_WRITE(GEN6_GT_MODE,
5164 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5165
5166 I915_WRITE(WM3_LP_ILK, 0);
5167 I915_WRITE(WM2_LP_ILK, 0);
5168 I915_WRITE(WM1_LP_ILK, 0);
5169
5170 I915_WRITE(CACHE_MODE_0,
5171 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5172
5173 I915_WRITE(GEN6_UCGCTL1,
5174 I915_READ(GEN6_UCGCTL1) |
5175 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5176 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5177
5178 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5179 * gating disable must be set. Failure to set it results in
5180 * flickering pixels due to Z write ordering failures after
5181 * some amount of runtime in the Mesa "fire" demo, and Unigine
5182 * Sanctuary and Tropics, and apparently anything else with
5183 * alpha test or pixel discard.
5184 *
5185 * According to the spec, bit 11 (RCCUNIT) must also be set,
5186 * but we didn't debug actual testcases to find it out.
5187 *
5188 * Also apply WaDisableVDSUnitClockGating:snb and
5189 * WaDisableRCPBUnitClockGating:snb.
5190 */
5191 I915_WRITE(GEN6_UCGCTL2,
5192 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5193 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5194 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5195
5196 /* Bspec says we need to always set all mask bits. */
5197 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
5198 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
5199
5200 /*
5201 * According to the spec the following bits should be
5202 * set in order to enable memory self-refresh and fbc:
5203 * The bit21 and bit22 of 0x42000
5204 * The bit21 and bit22 of 0x42004
5205 * The bit5 and bit7 of 0x42020
5206 * The bit14 of 0x70180
5207 * The bit14 of 0x71180
5208 *
5209 * WaFbcAsynchFlipDisableFbcQueue:snb
5210 */
5211 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5212 I915_READ(ILK_DISPLAY_CHICKEN1) |
5213 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5214 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5215 I915_READ(ILK_DISPLAY_CHICKEN2) |
5216 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5217 I915_WRITE(ILK_DSPCLK_GATE_D,
5218 I915_READ(ILK_DSPCLK_GATE_D) |
5219 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5220 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5221
5222 g4x_disable_trickle_feed(dev);
5223
5224 /* The default value should be 0x200 according to docs, but the two
5225 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
5226 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
5227 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
5228
5229 cpt_init_clock_gating(dev);
5230
5231 gen6_check_mch_setup(dev);
5232 }
5233
5234 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5235 {
5236 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5237
5238 reg &= ~GEN7_FF_SCHED_MASK;
5239 reg |= GEN7_FF_TS_SCHED_HW;
5240 reg |= GEN7_FF_VS_SCHED_HW;
5241 reg |= GEN7_FF_DS_SCHED_HW;
5242
5243 if (IS_HASWELL(dev_priv->dev))
5244 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
5245
5246 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5247 }
5248
5249 static void lpt_init_clock_gating(struct drm_device *dev)
5250 {
5251 struct drm_i915_private *dev_priv = dev->dev_private;
5252
5253 /*
5254 * TODO: this bit should only be enabled when really needed, then
5255 * disabled when not needed anymore in order to save power.
5256 */
5257 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5258 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5259 I915_READ(SOUTH_DSPCLK_GATE_D) |
5260 PCH_LP_PARTITION_LEVEL_DISABLE);
5261
5262 /* WADPOClockGatingDisable:hsw */
5263 I915_WRITE(_TRANSA_CHICKEN1,
5264 I915_READ(_TRANSA_CHICKEN1) |
5265 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5266 }
5267
5268 static void lpt_suspend_hw(struct drm_device *dev)
5269 {
5270 struct drm_i915_private *dev_priv = dev->dev_private;
5271
5272 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5273 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5274
5275 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5276 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5277 }
5278 }
5279
5280 static void gen8_init_clock_gating(struct drm_device *dev)
5281 {
5282 struct drm_i915_private *dev_priv = dev->dev_private;
5283 enum pipe i;
5284
5285 I915_WRITE(WM3_LP_ILK, 0);
5286 I915_WRITE(WM2_LP_ILK, 0);
5287 I915_WRITE(WM1_LP_ILK, 0);
5288
5289 /* FIXME(BDW): Check all the w/a, some might only apply to
5290 * pre-production hw. */
5291
5292 WARN(!i915_preliminary_hw_support,
5293 "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
5294 I915_WRITE(HALF_SLICE_CHICKEN3,
5295 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
5296 I915_WRITE(HALF_SLICE_CHICKEN3,
5297 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5298 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5299
5300 I915_WRITE(_3D_CHICKEN3,
5301 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5302
5303 I915_WRITE(COMMON_SLICE_CHICKEN2,
5304 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5305
5306 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5307 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5308
5309 /* WaSwitchSolVfFArbitrationPriority:bdw */
5310 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5311
5312 /* WaPsrDPAMaskVBlankInSRD:bdw */
5313 I915_WRITE(CHICKEN_PAR1_1,
5314 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5315
5316 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5317 for_each_pipe(i) {
5318 I915_WRITE(CHICKEN_PIPESL_1(i),
5319 I915_READ(CHICKEN_PIPESL_1(i) |
5320 DPRS_MASK_VBLANK_SRD));
5321 }
5322
5323 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5324 * workaround for for a possible hang in the unlikely event a TLB
5325 * invalidation occurs during a PSD flush.
5326 */
5327 I915_WRITE(HDC_CHICKEN0,
5328 I915_READ(HDC_CHICKEN0) |
5329 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
5330
5331 /* WaVSRefCountFullforceMissDisable:bdw */
5332 /* WaDSRefCountFullforceMissDisable:bdw */
5333 I915_WRITE(GEN7_FF_THREAD_MODE,
5334 I915_READ(GEN7_FF_THREAD_MODE) &
5335 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5336 }
5337
5338 static void haswell_init_clock_gating(struct drm_device *dev)
5339 {
5340 struct drm_i915_private *dev_priv = dev->dev_private;
5341
5342 I915_WRITE(WM3_LP_ILK, 0);
5343 I915_WRITE(WM2_LP_ILK, 0);
5344 I915_WRITE(WM1_LP_ILK, 0);
5345
5346 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5347 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
5348 */
5349 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5350
5351 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
5352 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5353 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5354
5355 /* WaApplyL3ControlAndL3ChickenMode:hsw */
5356 I915_WRITE(GEN7_L3CNTLREG1,
5357 GEN7_WA_FOR_GEN7_L3_CONTROL);
5358 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5359 GEN7_WA_L3_CHICKEN_MODE);
5360
5361 /* L3 caching of data atomics doesn't work -- disable it. */
5362 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5363 I915_WRITE(HSW_ROW_CHICKEN3,
5364 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5365
5366 /* This is required by WaCatErrorRejectionIssue:hsw */
5367 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5368 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5369 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5370
5371 /* WaVSRefCountFullforceMissDisable:hsw */
5372 gen7_setup_fixed_func_scheduler(dev_priv);
5373
5374 /* WaDisable4x2SubspanOptimization:hsw */
5375 I915_WRITE(CACHE_MODE_1,
5376 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5377
5378 /* WaSwitchSolVfFArbitrationPriority:hsw */
5379 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5380
5381 /* WaRsPkgCStateDisplayPMReq:hsw */
5382 I915_WRITE(CHICKEN_PAR1_1,
5383 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5384
5385 lpt_init_clock_gating(dev);
5386 }
5387
5388 static void ivybridge_init_clock_gating(struct drm_device *dev)
5389 {
5390 struct drm_i915_private *dev_priv = dev->dev_private;
5391 uint32_t snpcr;
5392
5393 I915_WRITE(WM3_LP_ILK, 0);
5394 I915_WRITE(WM2_LP_ILK, 0);
5395 I915_WRITE(WM1_LP_ILK, 0);
5396
5397 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5398
5399 /* WaDisableEarlyCull:ivb */
5400 I915_WRITE(_3D_CHICKEN3,
5401 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5402
5403 /* WaDisableBackToBackFlipFix:ivb */
5404 I915_WRITE(IVB_CHICKEN3,
5405 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5406 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5407
5408 /* WaDisablePSDDualDispatchEnable:ivb */
5409 if (IS_IVB_GT1(dev))
5410 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5411 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5412 else
5413 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5414 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5415
5416 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5417 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5418 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5419
5420 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5421 I915_WRITE(GEN7_L3CNTLREG1,
5422 GEN7_WA_FOR_GEN7_L3_CONTROL);
5423 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5424 GEN7_WA_L3_CHICKEN_MODE);
5425 if (IS_IVB_GT1(dev))
5426 I915_WRITE(GEN7_ROW_CHICKEN2,
5427 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5428 else
5429 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5430 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5431
5432
5433 /* WaForceL3Serialization:ivb */
5434 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5435 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5436
5437 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5438 * gating disable must be set. Failure to set it results in
5439 * flickering pixels due to Z write ordering failures after
5440 * some amount of runtime in the Mesa "fire" demo, and Unigine
5441 * Sanctuary and Tropics, and apparently anything else with
5442 * alpha test or pixel discard.
5443 *
5444 * According to the spec, bit 11 (RCCUNIT) must also be set,
5445 * but we didn't debug actual testcases to find it out.
5446 *
5447 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5448 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5449 */
5450 I915_WRITE(GEN6_UCGCTL2,
5451 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5452 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5453
5454 /* This is required by WaCatErrorRejectionIssue:ivb */
5455 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5456 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5457 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5458
5459 g4x_disable_trickle_feed(dev);
5460
5461 /* WaVSRefCountFullforceMissDisable:ivb */
5462 gen7_setup_fixed_func_scheduler(dev_priv);
5463
5464 /* WaDisable4x2SubspanOptimization:ivb */
5465 I915_WRITE(CACHE_MODE_1,
5466 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5467
5468 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5469 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5470 snpcr |= GEN6_MBC_SNPCR_MED;
5471 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5472
5473 if (!HAS_PCH_NOP(dev))
5474 cpt_init_clock_gating(dev);
5475
5476 gen6_check_mch_setup(dev);
5477 }
5478
5479 static void valleyview_init_clock_gating(struct drm_device *dev)
5480 {
5481 struct drm_i915_private *dev_priv = dev->dev_private;
5482 u32 val;
5483
5484 mutex_lock(&dev_priv->rps.hw_lock);
5485 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5486 mutex_unlock(&dev_priv->rps.hw_lock);
5487 switch ((val >> 6) & 3) {
5488 case 0:
5489 dev_priv->mem_freq = 800;
5490 break;
5491 case 1:
5492 dev_priv->mem_freq = 1066;
5493 break;
5494 case 2:
5495 dev_priv->mem_freq = 1333;
5496 break;
5497 case 3:
5498 dev_priv->mem_freq = 1333;
5499 break;
5500 }
5501 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5502
5503 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5504
5505 /* WaDisableEarlyCull:vlv */
5506 I915_WRITE(_3D_CHICKEN3,
5507 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5508
5509 /* WaDisableBackToBackFlipFix:vlv */
5510 I915_WRITE(IVB_CHICKEN3,
5511 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5512 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5513
5514 /* WaDisablePSDDualDispatchEnable:vlv */
5515 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5516 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5517 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5518
5519 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
5520 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5521 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5522
5523 /* WaApplyL3ControlAndL3ChickenMode:vlv */
5524 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
5525 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5526
5527 /* WaForceL3Serialization:vlv */
5528 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5529 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5530
5531 /* WaDisableDopClockGating:vlv */
5532 I915_WRITE(GEN7_ROW_CHICKEN2,
5533 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5534
5535 /* This is required by WaCatErrorRejectionIssue:vlv */
5536 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5537 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5538 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5539
5540 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5541 * gating disable must be set. Failure to set it results in
5542 * flickering pixels due to Z write ordering failures after
5543 * some amount of runtime in the Mesa "fire" demo, and Unigine
5544 * Sanctuary and Tropics, and apparently anything else with
5545 * alpha test or pixel discard.
5546 *
5547 * According to the spec, bit 11 (RCCUNIT) must also be set,
5548 * but we didn't debug actual testcases to find it out.
5549 *
5550 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5551 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5552 *
5553 * Also apply WaDisableVDSUnitClockGating:vlv and
5554 * WaDisableRCPBUnitClockGating:vlv.
5555 */
5556 I915_WRITE(GEN6_UCGCTL2,
5557 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5558 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
5559 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5560 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5561 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5562
5563 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5564
5565 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5566
5567 I915_WRITE(CACHE_MODE_1,
5568 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5569
5570 /*
5571 * WaDisableVLVClockGating_VBIIssue:vlv
5572 * Disable clock gating on th GCFG unit to prevent a delay
5573 * in the reporting of vblank events.
5574 */
5575 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5576
5577 /* Conservative clock gating settings for now */
5578 I915_WRITE(0x9400, 0xffffffff);
5579 I915_WRITE(0x9404, 0xffffffff);
5580 I915_WRITE(0x9408, 0xffffffff);
5581 I915_WRITE(0x940c, 0xffffffff);
5582 I915_WRITE(0x9410, 0xffffffff);
5583 I915_WRITE(0x9414, 0xffffffff);
5584 I915_WRITE(0x9418, 0xffffffff);
5585 }
5586
5587 static void g4x_init_clock_gating(struct drm_device *dev)
5588 {
5589 struct drm_i915_private *dev_priv = dev->dev_private;
5590 uint32_t dspclk_gate;
5591
5592 I915_WRITE(RENCLK_GATE_D1, 0);
5593 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5594 GS_UNIT_CLOCK_GATE_DISABLE |
5595 CL_UNIT_CLOCK_GATE_DISABLE);
5596 I915_WRITE(RAMCLK_GATE_D, 0);
5597 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5598 OVRUNIT_CLOCK_GATE_DISABLE |
5599 OVCUNIT_CLOCK_GATE_DISABLE;
5600 if (IS_GM45(dev))
5601 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5602 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5603
5604 /* WaDisableRenderCachePipelinedFlush */
5605 I915_WRITE(CACHE_MODE_0,
5606 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5607
5608 g4x_disable_trickle_feed(dev);
5609 }
5610
5611 static void crestline_init_clock_gating(struct drm_device *dev)
5612 {
5613 struct drm_i915_private *dev_priv = dev->dev_private;
5614
5615 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5616 I915_WRITE(RENCLK_GATE_D2, 0);
5617 I915_WRITE(DSPCLK_GATE_D, 0);
5618 I915_WRITE(RAMCLK_GATE_D, 0);
5619 I915_WRITE16(DEUC, 0);
5620 I915_WRITE(MI_ARB_STATE,
5621 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5622 }
5623
5624 static void broadwater_init_clock_gating(struct drm_device *dev)
5625 {
5626 struct drm_i915_private *dev_priv = dev->dev_private;
5627
5628 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5629 I965_RCC_CLOCK_GATE_DISABLE |
5630 I965_RCPB_CLOCK_GATE_DISABLE |
5631 I965_ISC_CLOCK_GATE_DISABLE |
5632 I965_FBC_CLOCK_GATE_DISABLE);
5633 I915_WRITE(RENCLK_GATE_D2, 0);
5634 I915_WRITE(MI_ARB_STATE,
5635 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5636 }
5637
5638 static void gen3_init_clock_gating(struct drm_device *dev)
5639 {
5640 struct drm_i915_private *dev_priv = dev->dev_private;
5641 u32 dstate = I915_READ(D_STATE);
5642
5643 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5644 DSTATE_DOT_CLOCK_GATING;
5645 I915_WRITE(D_STATE, dstate);
5646
5647 if (IS_PINEVIEW(dev))
5648 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5649
5650 /* IIR "flip pending" means done if this bit is set */
5651 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5652 }
5653
5654 static void i85x_init_clock_gating(struct drm_device *dev)
5655 {
5656 struct drm_i915_private *dev_priv = dev->dev_private;
5657
5658 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5659 }
5660
5661 static void i830_init_clock_gating(struct drm_device *dev)
5662 {
5663 struct drm_i915_private *dev_priv = dev->dev_private;
5664
5665 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5666 }
5667
5668 void intel_init_clock_gating(struct drm_device *dev)
5669 {
5670 struct drm_i915_private *dev_priv = dev->dev_private;
5671
5672 dev_priv->display.init_clock_gating(dev);
5673 }
5674
5675 void intel_suspend_hw(struct drm_device *dev)
5676 {
5677 if (HAS_PCH_LPT(dev))
5678 lpt_suspend_hw(dev);
5679 }
5680
5681 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
5682 for (i = 0; \
5683 i < (power_domains)->power_well_count && \
5684 ((power_well) = &(power_domains)->power_wells[i]); \
5685 i++) \
5686 if ((power_well)->domains & (domain_mask))
5687
5688 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5689 for (i = (power_domains)->power_well_count - 1; \
5690 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5691 i--) \
5692 if ((power_well)->domains & (domain_mask))
5693
5694 /**
5695 * We should only use the power well if we explicitly asked the hardware to
5696 * enable it, so check if it's enabled and also check if we've requested it to
5697 * be enabled.
5698 */
5699 static bool hsw_power_well_enabled(struct drm_device *dev,
5700 struct i915_power_well *power_well)
5701 {
5702 struct drm_i915_private *dev_priv = dev->dev_private;
5703
5704 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5705 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5706 }
5707
5708 bool intel_display_power_enabled_sw(struct drm_device *dev,
5709 enum intel_display_power_domain domain)
5710 {
5711 struct drm_i915_private *dev_priv = dev->dev_private;
5712 struct i915_power_domains *power_domains;
5713
5714 power_domains = &dev_priv->power_domains;
5715
5716 return power_domains->domain_use_count[domain];
5717 }
5718
5719 bool intel_display_power_enabled(struct drm_device *dev,
5720 enum intel_display_power_domain domain)
5721 {
5722 struct drm_i915_private *dev_priv = dev->dev_private;
5723 struct i915_power_domains *power_domains;
5724 struct i915_power_well *power_well;
5725 bool is_enabled;
5726 int i;
5727
5728 power_domains = &dev_priv->power_domains;
5729
5730 is_enabled = true;
5731
5732 mutex_lock(&power_domains->lock);
5733 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5734 if (power_well->always_on)
5735 continue;
5736
5737 if (!power_well->is_enabled(dev, power_well)) {
5738 is_enabled = false;
5739 break;
5740 }
5741 }
5742 mutex_unlock(&power_domains->lock);
5743
5744 return is_enabled;
5745 }
5746
5747 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5748 {
5749 struct drm_device *dev = dev_priv->dev;
5750 unsigned long irqflags;
5751
5752 /*
5753 * After we re-enable the power well, if we touch VGA register 0x3d5
5754 * we'll get unclaimed register interrupts. This stops after we write
5755 * anything to the VGA MSR register. The vgacon module uses this
5756 * register all the time, so if we unbind our driver and, as a
5757 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5758 * console_unlock(). So make here we touch the VGA MSR register, making
5759 * sure vgacon can keep working normally without triggering interrupts
5760 * and error messages.
5761 */
5762 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5763 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5764 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5765
5766 if (IS_BROADWELL(dev)) {
5767 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5768 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5769 dev_priv->de_irq_mask[PIPE_B]);
5770 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5771 ~dev_priv->de_irq_mask[PIPE_B] |
5772 GEN8_PIPE_VBLANK);
5773 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5774 dev_priv->de_irq_mask[PIPE_C]);
5775 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5776 ~dev_priv->de_irq_mask[PIPE_C] |
5777 GEN8_PIPE_VBLANK);
5778 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5779 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5780 }
5781 }
5782
5783 static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5784 {
5785 struct drm_device *dev = dev_priv->dev;
5786 enum pipe p;
5787 unsigned long irqflags;
5788
5789 /*
5790 * After this, the registers on the pipes that are part of the power
5791 * well will become zero, so we have to adjust our counters according to
5792 * that.
5793 *
5794 * FIXME: Should we do this in general in drm_vblank_post_modeset?
5795 */
5796 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5797 for_each_pipe(p)
5798 if (p != PIPE_A)
5799 dev->vblank[p].last = 0;
5800 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5801 }
5802
5803 static void hsw_set_power_well(struct drm_device *dev,
5804 struct i915_power_well *power_well, bool enable)
5805 {
5806 struct drm_i915_private *dev_priv = dev->dev_private;
5807 bool is_enabled, enable_requested;
5808 uint32_t tmp;
5809
5810 WARN_ON(dev_priv->pc8.enabled);
5811
5812 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5813 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5814 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5815
5816 if (enable) {
5817 if (!enable_requested)
5818 I915_WRITE(HSW_PWR_WELL_DRIVER,
5819 HSW_PWR_WELL_ENABLE_REQUEST);
5820
5821 if (!is_enabled) {
5822 DRM_DEBUG_KMS("Enabling power well\n");
5823 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5824 HSW_PWR_WELL_STATE_ENABLED), 20))
5825 DRM_ERROR("Timeout enabling power well\n");
5826 }
5827
5828 hsw_power_well_post_enable(dev_priv);
5829 } else {
5830 if (enable_requested) {
5831 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5832 POSTING_READ(HSW_PWR_WELL_DRIVER);
5833 DRM_DEBUG_KMS("Requesting to disable the power well\n");
5834
5835 hsw_power_well_post_disable(dev_priv);
5836 }
5837 }
5838 }
5839
5840 static void __intel_power_well_get(struct drm_device *dev,
5841 struct i915_power_well *power_well)
5842 {
5843 struct drm_i915_private *dev_priv = dev->dev_private;
5844
5845 if (!power_well->count++ && power_well->set) {
5846 hsw_disable_package_c8(dev_priv);
5847 power_well->set(dev, power_well, true);
5848 }
5849 }
5850
5851 static void __intel_power_well_put(struct drm_device *dev,
5852 struct i915_power_well *power_well)
5853 {
5854 struct drm_i915_private *dev_priv = dev->dev_private;
5855
5856 WARN_ON(!power_well->count);
5857
5858 if (!--power_well->count && power_well->set &&
5859 i915_disable_power_well) {
5860 power_well->set(dev, power_well, false);
5861 hsw_enable_package_c8(dev_priv);
5862 }
5863 }
5864
5865 void intel_display_power_get(struct drm_device *dev,
5866 enum intel_display_power_domain domain)
5867 {
5868 struct drm_i915_private *dev_priv = dev->dev_private;
5869 struct i915_power_domains *power_domains;
5870 struct i915_power_well *power_well;
5871 int i;
5872
5873 power_domains = &dev_priv->power_domains;
5874
5875 mutex_lock(&power_domains->lock);
5876
5877 for_each_power_well(i, power_well, BIT(domain), power_domains)
5878 __intel_power_well_get(dev, power_well);
5879
5880 power_domains->domain_use_count[domain]++;
5881
5882 mutex_unlock(&power_domains->lock);
5883 }
5884
5885 void intel_display_power_put(struct drm_device *dev,
5886 enum intel_display_power_domain domain)
5887 {
5888 struct drm_i915_private *dev_priv = dev->dev_private;
5889 struct i915_power_domains *power_domains;
5890 struct i915_power_well *power_well;
5891 int i;
5892
5893 power_domains = &dev_priv->power_domains;
5894
5895 mutex_lock(&power_domains->lock);
5896
5897 WARN_ON(!power_domains->domain_use_count[domain]);
5898 power_domains->domain_use_count[domain]--;
5899
5900 for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
5901 __intel_power_well_put(dev, power_well);
5902
5903 mutex_unlock(&power_domains->lock);
5904 }
5905
5906 static struct i915_power_domains *hsw_pwr;
5907
5908 /* Display audio driver power well request */
5909 void i915_request_power_well(void)
5910 {
5911 struct drm_i915_private *dev_priv;
5912
5913 if (WARN_ON(!hsw_pwr))
5914 return;
5915
5916 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5917 power_domains);
5918 intel_display_power_get(dev_priv->dev, POWER_DOMAIN_AUDIO);
5919 }
5920 EXPORT_SYMBOL_GPL(i915_request_power_well);
5921
5922 /* Display audio driver power well release */
5923 void i915_release_power_well(void)
5924 {
5925 struct drm_i915_private *dev_priv;
5926
5927 if (WARN_ON(!hsw_pwr))
5928 return;
5929
5930 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5931 power_domains);
5932 intel_display_power_put(dev_priv->dev, POWER_DOMAIN_AUDIO);
5933 }
5934 EXPORT_SYMBOL_GPL(i915_release_power_well);
5935
5936 static struct i915_power_well i9xx_always_on_power_well[] = {
5937 {
5938 .name = "always-on",
5939 .always_on = 1,
5940 .domains = POWER_DOMAIN_MASK,
5941 },
5942 };
5943
5944 static struct i915_power_well hsw_power_wells[] = {
5945 {
5946 .name = "always-on",
5947 .always_on = 1,
5948 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5949 },
5950 {
5951 .name = "display",
5952 .domains = POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS,
5953 .is_enabled = hsw_power_well_enabled,
5954 .set = hsw_set_power_well,
5955 },
5956 };
5957
5958 static struct i915_power_well bdw_power_wells[] = {
5959 {
5960 .name = "always-on",
5961 .always_on = 1,
5962 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5963 },
5964 {
5965 .name = "display",
5966 .domains = POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS,
5967 .is_enabled = hsw_power_well_enabled,
5968 .set = hsw_set_power_well,
5969 },
5970 };
5971
5972 #define set_power_wells(power_domains, __power_wells) ({ \
5973 (power_domains)->power_wells = (__power_wells); \
5974 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
5975 })
5976
5977 int intel_power_domains_init(struct drm_device *dev)
5978 {
5979 struct drm_i915_private *dev_priv = dev->dev_private;
5980 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5981
5982 mutex_init(&power_domains->lock);
5983
5984 /*
5985 * The enabling order will be from lower to higher indexed wells,
5986 * the disabling order is reversed.
5987 */
5988 if (IS_HASWELL(dev)) {
5989 set_power_wells(power_domains, hsw_power_wells);
5990 hsw_pwr = power_domains;
5991 } else if (IS_BROADWELL(dev)) {
5992 set_power_wells(power_domains, bdw_power_wells);
5993 hsw_pwr = power_domains;
5994 } else {
5995 set_power_wells(power_domains, i9xx_always_on_power_well);
5996 }
5997
5998 return 0;
5999 }
6000
6001 void intel_power_domains_remove(struct drm_device *dev)
6002 {
6003 hsw_pwr = NULL;
6004 }
6005
6006 static void intel_power_domains_resume(struct drm_device *dev)
6007 {
6008 struct drm_i915_private *dev_priv = dev->dev_private;
6009 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6010 struct i915_power_well *power_well;
6011 int i;
6012
6013 mutex_lock(&power_domains->lock);
6014 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
6015 if (power_well->set)
6016 power_well->set(dev, power_well, power_well->count > 0);
6017 }
6018 mutex_unlock(&power_domains->lock);
6019 }
6020
6021 /*
6022 * Starting with Haswell, we have a "Power Down Well" that can be turned off
6023 * when not needed anymore. We have 4 registers that can request the power well
6024 * to be enabled, and it will only be disabled if none of the registers is
6025 * requesting it to be enabled.
6026 */
6027 void intel_power_domains_init_hw(struct drm_device *dev)
6028 {
6029 struct drm_i915_private *dev_priv = dev->dev_private;
6030
6031 /* For now, we need the power well to be always enabled. */
6032 intel_display_set_init_power(dev, true);
6033 intel_power_domains_resume(dev);
6034
6035 if (!(IS_HASWELL(dev) || IS_BROADWELL(dev)))
6036 return;
6037
6038 /* We're taking over the BIOS, so clear any requests made by it since
6039 * the driver is in charge now. */
6040 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
6041 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
6042 }
6043
6044 /* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
6045 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
6046 {
6047 hsw_disable_package_c8(dev_priv);
6048 }
6049
6050 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
6051 {
6052 hsw_enable_package_c8(dev_priv);
6053 }
6054
6055 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
6056 {
6057 struct drm_device *dev = dev_priv->dev;
6058 struct device *device = &dev->pdev->dev;
6059
6060 if (!HAS_RUNTIME_PM(dev))
6061 return;
6062
6063 pm_runtime_get_sync(device);
6064 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
6065 }
6066
6067 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
6068 {
6069 struct drm_device *dev = dev_priv->dev;
6070 struct device *device = &dev->pdev->dev;
6071
6072 if (!HAS_RUNTIME_PM(dev))
6073 return;
6074
6075 pm_runtime_mark_last_busy(device);
6076 pm_runtime_put_autosuspend(device);
6077 }
6078
6079 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
6080 {
6081 struct drm_device *dev = dev_priv->dev;
6082 struct device *device = &dev->pdev->dev;
6083
6084 dev_priv->pm.suspended = false;
6085
6086 if (!HAS_RUNTIME_PM(dev))
6087 return;
6088
6089 pm_runtime_set_active(device);
6090
6091 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6092 pm_runtime_mark_last_busy(device);
6093 pm_runtime_use_autosuspend(device);
6094 }
6095
6096 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6097 {
6098 struct drm_device *dev = dev_priv->dev;
6099 struct device *device = &dev->pdev->dev;
6100
6101 if (!HAS_RUNTIME_PM(dev))
6102 return;
6103
6104 /* Make sure we're not suspended first. */
6105 pm_runtime_get_sync(device);
6106 pm_runtime_disable(device);
6107 }
6108
6109 /* Set up chip specific power management-related functions */
6110 void intel_init_pm(struct drm_device *dev)
6111 {
6112 struct drm_i915_private *dev_priv = dev->dev_private;
6113
6114 if (I915_HAS_FBC(dev)) {
6115 if (INTEL_INFO(dev)->gen >= 7) {
6116 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6117 dev_priv->display.enable_fbc = gen7_enable_fbc;
6118 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6119 } else if (INTEL_INFO(dev)->gen >= 5) {
6120 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6121 dev_priv->display.enable_fbc = ironlake_enable_fbc;
6122 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6123 } else if (IS_GM45(dev)) {
6124 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6125 dev_priv->display.enable_fbc = g4x_enable_fbc;
6126 dev_priv->display.disable_fbc = g4x_disable_fbc;
6127 } else {
6128 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6129 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6130 dev_priv->display.disable_fbc = i8xx_disable_fbc;
6131
6132 /* This value was pulled out of someone's hat */
6133 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
6134 }
6135 }
6136
6137 /* For cxsr */
6138 if (IS_PINEVIEW(dev))
6139 i915_pineview_get_mem_freq(dev);
6140 else if (IS_GEN5(dev))
6141 i915_ironlake_get_mem_freq(dev);
6142
6143 /* For FIFO watermark updates */
6144 if (HAS_PCH_SPLIT(dev)) {
6145 intel_setup_wm_latency(dev);
6146
6147 if (IS_GEN5(dev)) {
6148 if (dev_priv->wm.pri_latency[1] &&
6149 dev_priv->wm.spr_latency[1] &&
6150 dev_priv->wm.cur_latency[1])
6151 dev_priv->display.update_wm = ironlake_update_wm;
6152 else {
6153 DRM_DEBUG_KMS("Failed to get proper latency. "
6154 "Disable CxSR\n");
6155 dev_priv->display.update_wm = NULL;
6156 }
6157 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6158 } else if (IS_GEN6(dev)) {
6159 if (dev_priv->wm.pri_latency[0] &&
6160 dev_priv->wm.spr_latency[0] &&
6161 dev_priv->wm.cur_latency[0]) {
6162 dev_priv->display.update_wm = sandybridge_update_wm;
6163 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
6164 } else {
6165 DRM_DEBUG_KMS("Failed to read display plane latency. "
6166 "Disable CxSR\n");
6167 dev_priv->display.update_wm = NULL;
6168 }
6169 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6170 } else if (IS_IVYBRIDGE(dev)) {
6171 if (dev_priv->wm.pri_latency[0] &&
6172 dev_priv->wm.spr_latency[0] &&
6173 dev_priv->wm.cur_latency[0]) {
6174 dev_priv->display.update_wm = ivybridge_update_wm;
6175 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
6176 } else {
6177 DRM_DEBUG_KMS("Failed to read display plane latency. "
6178 "Disable CxSR\n");
6179 dev_priv->display.update_wm = NULL;
6180 }
6181 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6182 } else if (IS_HASWELL(dev)) {
6183 if (dev_priv->wm.pri_latency[0] &&
6184 dev_priv->wm.spr_latency[0] &&
6185 dev_priv->wm.cur_latency[0]) {
6186 dev_priv->display.update_wm = haswell_update_wm;
6187 dev_priv->display.update_sprite_wm =
6188 haswell_update_sprite_wm;
6189 } else {
6190 DRM_DEBUG_KMS("Failed to read display plane latency. "
6191 "Disable CxSR\n");
6192 dev_priv->display.update_wm = NULL;
6193 }
6194 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6195 } else if (INTEL_INFO(dev)->gen == 8) {
6196 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
6197 } else
6198 dev_priv->display.update_wm = NULL;
6199 } else if (IS_VALLEYVIEW(dev)) {
6200 dev_priv->display.update_wm = valleyview_update_wm;
6201 dev_priv->display.init_clock_gating =
6202 valleyview_init_clock_gating;
6203 } else if (IS_PINEVIEW(dev)) {
6204 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6205 dev_priv->is_ddr3,
6206 dev_priv->fsb_freq,
6207 dev_priv->mem_freq)) {
6208 DRM_INFO("failed to find known CxSR latency "
6209 "(found ddr%s fsb freq %d, mem freq %d), "
6210 "disabling CxSR\n",
6211 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6212 dev_priv->fsb_freq, dev_priv->mem_freq);
6213 /* Disable CxSR and never update its watermark again */
6214 pineview_disable_cxsr(dev);
6215 dev_priv->display.update_wm = NULL;
6216 } else
6217 dev_priv->display.update_wm = pineview_update_wm;
6218 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6219 } else if (IS_G4X(dev)) {
6220 dev_priv->display.update_wm = g4x_update_wm;
6221 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6222 } else if (IS_GEN4(dev)) {
6223 dev_priv->display.update_wm = i965_update_wm;
6224 if (IS_CRESTLINE(dev))
6225 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6226 else if (IS_BROADWATER(dev))
6227 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6228 } else if (IS_GEN3(dev)) {
6229 dev_priv->display.update_wm = i9xx_update_wm;
6230 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6231 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6232 } else if (IS_I865G(dev)) {
6233 dev_priv->display.update_wm = i830_update_wm;
6234 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6235 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6236 } else if (IS_I85X(dev)) {
6237 dev_priv->display.update_wm = i9xx_update_wm;
6238 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6239 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6240 } else {
6241 dev_priv->display.update_wm = i830_update_wm;
6242 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6243 if (IS_845G(dev))
6244 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6245 else
6246 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6247 }
6248 }
6249
6250 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6251 {
6252 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6253
6254 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6255 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6256 return -EAGAIN;
6257 }
6258
6259 I915_WRITE(GEN6_PCODE_DATA, *val);
6260 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6261
6262 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6263 500)) {
6264 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6265 return -ETIMEDOUT;
6266 }
6267
6268 *val = I915_READ(GEN6_PCODE_DATA);
6269 I915_WRITE(GEN6_PCODE_DATA, 0);
6270
6271 return 0;
6272 }
6273
6274 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6275 {
6276 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6277
6278 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6279 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6280 return -EAGAIN;
6281 }
6282
6283 I915_WRITE(GEN6_PCODE_DATA, val);
6284 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6285
6286 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6287 500)) {
6288 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6289 return -ETIMEDOUT;
6290 }
6291
6292 I915_WRITE(GEN6_PCODE_DATA, 0);
6293
6294 return 0;
6295 }
6296
6297 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6298 {
6299 int div;
6300
6301 /* 4 x czclk */
6302 switch (dev_priv->mem_freq) {
6303 case 800:
6304 div = 10;
6305 break;
6306 case 1066:
6307 div = 12;
6308 break;
6309 case 1333:
6310 div = 16;
6311 break;
6312 default:
6313 return -1;
6314 }
6315
6316 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
6317 }
6318
6319 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6320 {
6321 int mul;
6322
6323 /* 4 x czclk */
6324 switch (dev_priv->mem_freq) {
6325 case 800:
6326 mul = 10;
6327 break;
6328 case 1066:
6329 mul = 12;
6330 break;
6331 case 1333:
6332 mul = 16;
6333 break;
6334 default:
6335 return -1;
6336 }
6337
6338 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
6339 }
6340
6341 void intel_pm_init(struct drm_device *dev)
6342 {
6343 struct drm_i915_private *dev_priv = dev->dev_private;
6344
6345 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6346 intel_gen6_powersave_work);
6347 }
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