2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
51 #define INTEL_RC6_ENABLE (1<<0)
52 #define INTEL_RC6p_ENABLE (1<<1)
53 #define INTEL_RC6pp_ENABLE (1<<2)
55 static void gen9_init_clock_gating(struct drm_device
*dev
)
57 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1
, I915_READ(BDW_SCRATCH1
) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE
);
64 static void skl_init_clock_gating(struct drm_device
*dev
)
66 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
68 gen9_init_clock_gating(dev
);
70 if (INTEL_REVID(dev
) == SKL_REVID_A0
) {
72 * WaDisableSDEUnitClockGating:skl
73 * WaSetGAPSunitClckGateDisable:skl
75 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
76 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE
|
77 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
80 if (INTEL_REVID(dev
) <= SKL_REVID_D0
) {
81 /* WaDisableHDCInvalidation:skl */
82 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
83 BDW_DISABLE_HDC_INVALIDATION
);
85 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
86 I915_WRITE(FF_SLICE_CS_CHICKEN2
,
87 I915_READ(FF_SLICE_CS_CHICKEN2
) |
88 GEN9_TSG_BARRIER_ACK_DISABLE
);
91 if (INTEL_REVID(dev
) <= SKL_REVID_E0
)
92 /* WaDisableLSQCROPERFforOCL:skl */
93 I915_WRITE(GEN8_L3SQCREG4
, I915_READ(GEN8_L3SQCREG4
) |
94 GEN8_LQSC_RO_PERF_DIS
);
97 static void i915_pineview_get_mem_freq(struct drm_device
*dev
)
99 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
102 tmp
= I915_READ(CLKCFG
);
104 switch (tmp
& CLKCFG_FSB_MASK
) {
106 dev_priv
->fsb_freq
= 533; /* 133*4 */
109 dev_priv
->fsb_freq
= 800; /* 200*4 */
112 dev_priv
->fsb_freq
= 667; /* 167*4 */
115 dev_priv
->fsb_freq
= 400; /* 100*4 */
119 switch (tmp
& CLKCFG_MEM_MASK
) {
121 dev_priv
->mem_freq
= 533;
124 dev_priv
->mem_freq
= 667;
127 dev_priv
->mem_freq
= 800;
131 /* detect pineview DDR3 setting */
132 tmp
= I915_READ(CSHRDDR3CTL
);
133 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
136 static void i915_ironlake_get_mem_freq(struct drm_device
*dev
)
138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
141 ddrpll
= I915_READ16(DDRMPLL1
);
142 csipll
= I915_READ16(CSIPLL0
);
144 switch (ddrpll
& 0xff) {
146 dev_priv
->mem_freq
= 800;
149 dev_priv
->mem_freq
= 1066;
152 dev_priv
->mem_freq
= 1333;
155 dev_priv
->mem_freq
= 1600;
158 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
160 dev_priv
->mem_freq
= 0;
164 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
166 switch (csipll
& 0x3ff) {
168 dev_priv
->fsb_freq
= 3200;
171 dev_priv
->fsb_freq
= 3733;
174 dev_priv
->fsb_freq
= 4266;
177 dev_priv
->fsb_freq
= 4800;
180 dev_priv
->fsb_freq
= 5333;
183 dev_priv
->fsb_freq
= 5866;
186 dev_priv
->fsb_freq
= 6400;
189 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
191 dev_priv
->fsb_freq
= 0;
195 if (dev_priv
->fsb_freq
== 3200) {
196 dev_priv
->ips
.c_m
= 0;
197 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
198 dev_priv
->ips
.c_m
= 1;
200 dev_priv
->ips
.c_m
= 2;
204 static const struct cxsr_latency cxsr_latency_table
[] = {
205 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
206 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
207 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
208 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
209 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
211 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
212 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
213 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
214 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
215 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
217 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
218 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
219 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
220 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
221 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
223 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
224 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
225 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
226 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
227 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
229 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
230 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
231 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
232 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
233 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
235 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
236 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
237 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
238 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
239 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
242 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
247 const struct cxsr_latency
*latency
;
250 if (fsb
== 0 || mem
== 0)
253 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
254 latency
= &cxsr_latency_table
[i
];
255 if (is_desktop
== latency
->is_desktop
&&
256 is_ddr3
== latency
->is_ddr3
&&
257 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
261 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
266 void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
268 struct drm_device
*dev
= dev_priv
->dev
;
271 if (IS_VALLEYVIEW(dev
)) {
272 I915_WRITE(FW_BLC_SELF_VLV
, enable
? FW_CSPWRDWNEN
: 0);
273 } else if (IS_G4X(dev
) || IS_CRESTLINE(dev
)) {
274 I915_WRITE(FW_BLC_SELF
, enable
? FW_BLC_SELF_EN
: 0);
275 } else if (IS_PINEVIEW(dev
)) {
276 val
= I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
;
277 val
|= enable
? PINEVIEW_SELF_REFRESH_EN
: 0;
278 I915_WRITE(DSPFW3
, val
);
279 } else if (IS_I945G(dev
) || IS_I945GM(dev
)) {
280 val
= enable
? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN
) :
281 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN
);
282 I915_WRITE(FW_BLC_SELF
, val
);
283 } else if (IS_I915GM(dev
)) {
284 val
= enable
? _MASKED_BIT_ENABLE(INSTPM_SELF_EN
) :
285 _MASKED_BIT_DISABLE(INSTPM_SELF_EN
);
286 I915_WRITE(INSTPM
, val
);
291 DRM_DEBUG_KMS("memory self-refresh is %s\n",
292 enable
? "enabled" : "disabled");
296 * Latency for FIFO fetches is dependent on several factors:
297 * - memory configuration (speed, channels)
299 * - current MCH state
300 * It can be fairly high in some situations, so here we assume a fairly
301 * pessimal value. It's a tradeoff between extra memory fetches (if we
302 * set this value too high, the FIFO will fetch frequently to stay full)
303 * and power consumption (set it too low to save power and we might see
304 * FIFO underruns and display "flicker").
306 * A value of 5us seems to be a good balance; safe for very low end
307 * platforms but not overly aggressive on lower latency configs.
309 static const int pessimal_latency_ns
= 5000;
311 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
314 uint32_t dsparb
= I915_READ(DSPARB
);
317 size
= dsparb
& 0x7f;
319 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
321 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
322 plane
? "B" : "A", size
);
327 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
330 uint32_t dsparb
= I915_READ(DSPARB
);
333 size
= dsparb
& 0x1ff;
335 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
336 size
>>= 1; /* Convert to cachelines */
338 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
339 plane
? "B" : "A", size
);
344 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
347 uint32_t dsparb
= I915_READ(DSPARB
);
350 size
= dsparb
& 0x7f;
351 size
>>= 2; /* Convert to cachelines */
353 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
360 /* Pineview has different values for various configs */
361 static const struct intel_watermark_params pineview_display_wm
= {
362 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
363 .max_wm
= PINEVIEW_MAX_WM
,
364 .default_wm
= PINEVIEW_DFT_WM
,
365 .guard_size
= PINEVIEW_GUARD_WM
,
366 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
368 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
369 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
370 .max_wm
= PINEVIEW_MAX_WM
,
371 .default_wm
= PINEVIEW_DFT_HPLLOFF_WM
,
372 .guard_size
= PINEVIEW_GUARD_WM
,
373 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
375 static const struct intel_watermark_params pineview_cursor_wm
= {
376 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
377 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
378 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
379 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
380 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
382 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
383 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
384 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
385 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
386 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
387 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
389 static const struct intel_watermark_params g4x_wm_info
= {
390 .fifo_size
= G4X_FIFO_SIZE
,
391 .max_wm
= G4X_MAX_WM
,
392 .default_wm
= G4X_MAX_WM
,
394 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
396 static const struct intel_watermark_params g4x_cursor_wm_info
= {
397 .fifo_size
= I965_CURSOR_FIFO
,
398 .max_wm
= I965_CURSOR_MAX_WM
,
399 .default_wm
= I965_CURSOR_DFT_WM
,
401 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
403 static const struct intel_watermark_params valleyview_wm_info
= {
404 .fifo_size
= VALLEYVIEW_FIFO_SIZE
,
405 .max_wm
= VALLEYVIEW_MAX_WM
,
406 .default_wm
= VALLEYVIEW_MAX_WM
,
408 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
410 static const struct intel_watermark_params valleyview_cursor_wm_info
= {
411 .fifo_size
= I965_CURSOR_FIFO
,
412 .max_wm
= VALLEYVIEW_CURSOR_MAX_WM
,
413 .default_wm
= I965_CURSOR_DFT_WM
,
415 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
417 static const struct intel_watermark_params i965_cursor_wm_info
= {
418 .fifo_size
= I965_CURSOR_FIFO
,
419 .max_wm
= I965_CURSOR_MAX_WM
,
420 .default_wm
= I965_CURSOR_DFT_WM
,
422 .cacheline_size
= I915_FIFO_LINE_SIZE
,
424 static const struct intel_watermark_params i945_wm_info
= {
425 .fifo_size
= I945_FIFO_SIZE
,
426 .max_wm
= I915_MAX_WM
,
429 .cacheline_size
= I915_FIFO_LINE_SIZE
,
431 static const struct intel_watermark_params i915_wm_info
= {
432 .fifo_size
= I915_FIFO_SIZE
,
433 .max_wm
= I915_MAX_WM
,
436 .cacheline_size
= I915_FIFO_LINE_SIZE
,
438 static const struct intel_watermark_params i830_a_wm_info
= {
439 .fifo_size
= I855GM_FIFO_SIZE
,
440 .max_wm
= I915_MAX_WM
,
443 .cacheline_size
= I830_FIFO_LINE_SIZE
,
445 static const struct intel_watermark_params i830_bc_wm_info
= {
446 .fifo_size
= I855GM_FIFO_SIZE
,
447 .max_wm
= I915_MAX_WM
/2,
450 .cacheline_size
= I830_FIFO_LINE_SIZE
,
452 static const struct intel_watermark_params i845_wm_info
= {
453 .fifo_size
= I830_FIFO_SIZE
,
454 .max_wm
= I915_MAX_WM
,
457 .cacheline_size
= I830_FIFO_LINE_SIZE
,
461 * intel_calculate_wm - calculate watermark level
462 * @clock_in_khz: pixel clock
463 * @wm: chip FIFO params
464 * @pixel_size: display pixel size
465 * @latency_ns: memory latency for the platform
467 * Calculate the watermark level (the level at which the display plane will
468 * start fetching from memory again). Each chip has a different display
469 * FIFO size and allocation, so the caller needs to figure that out and pass
470 * in the correct intel_watermark_params structure.
472 * As the pixel clock runs, the FIFO will be drained at a rate that depends
473 * on the pixel size. When it reaches the watermark level, it'll start
474 * fetching FIFO line sized based chunks from memory until the FIFO fills
475 * past the watermark point. If the FIFO drains completely, a FIFO underrun
476 * will occur, and a display engine hang could result.
478 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
479 const struct intel_watermark_params
*wm
,
482 unsigned long latency_ns
)
484 long entries_required
, wm_size
;
487 * Note: we need to make sure we don't overflow for various clock &
489 * clocks go from a few thousand to several hundred thousand.
490 * latency is usually a few thousand
492 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
494 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
496 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
498 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
500 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
502 /* Don't promote wm_size to unsigned... */
503 if (wm_size
> (long)wm
->max_wm
)
504 wm_size
= wm
->max_wm
;
506 wm_size
= wm
->default_wm
;
509 * Bspec seems to indicate that the value shouldn't be lower than
510 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
511 * Lets go for 8 which is the burst size since certain platforms
512 * already use a hardcoded 8 (which is what the spec says should be
521 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
523 struct drm_crtc
*crtc
, *enabled
= NULL
;
525 for_each_crtc(dev
, crtc
) {
526 if (intel_crtc_active(crtc
)) {
536 static void pineview_update_wm(struct drm_crtc
*unused_crtc
)
538 struct drm_device
*dev
= unused_crtc
->dev
;
539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
540 struct drm_crtc
*crtc
;
541 const struct cxsr_latency
*latency
;
545 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
546 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
548 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
549 intel_set_memory_cxsr(dev_priv
, false);
553 crtc
= single_enabled_crtc(dev
);
555 const struct drm_display_mode
*adjusted_mode
;
556 int pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
559 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
560 clock
= adjusted_mode
->crtc_clock
;
563 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
564 pineview_display_wm
.fifo_size
,
565 pixel_size
, latency
->display_sr
);
566 reg
= I915_READ(DSPFW1
);
567 reg
&= ~DSPFW_SR_MASK
;
568 reg
|= wm
<< DSPFW_SR_SHIFT
;
569 I915_WRITE(DSPFW1
, reg
);
570 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
573 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
574 pineview_display_wm
.fifo_size
,
575 pixel_size
, latency
->cursor_sr
);
576 reg
= I915_READ(DSPFW3
);
577 reg
&= ~DSPFW_CURSOR_SR_MASK
;
578 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
579 I915_WRITE(DSPFW3
, reg
);
581 /* Display HPLL off SR */
582 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
583 pineview_display_hplloff_wm
.fifo_size
,
584 pixel_size
, latency
->display_hpll_disable
);
585 reg
= I915_READ(DSPFW3
);
586 reg
&= ~DSPFW_HPLL_SR_MASK
;
587 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
588 I915_WRITE(DSPFW3
, reg
);
590 /* cursor HPLL off SR */
591 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
592 pineview_display_hplloff_wm
.fifo_size
,
593 pixel_size
, latency
->cursor_hpll_disable
);
594 reg
= I915_READ(DSPFW3
);
595 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
596 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
597 I915_WRITE(DSPFW3
, reg
);
598 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
600 intel_set_memory_cxsr(dev_priv
, true);
602 intel_set_memory_cxsr(dev_priv
, false);
606 static bool g4x_compute_wm0(struct drm_device
*dev
,
608 const struct intel_watermark_params
*display
,
609 int display_latency_ns
,
610 const struct intel_watermark_params
*cursor
,
611 int cursor_latency_ns
,
615 struct drm_crtc
*crtc
;
616 const struct drm_display_mode
*adjusted_mode
;
617 int htotal
, hdisplay
, clock
, pixel_size
;
618 int line_time_us
, line_count
;
619 int entries
, tlb_miss
;
621 crtc
= intel_get_crtc_for_plane(dev
, plane
);
622 if (!intel_crtc_active(crtc
)) {
623 *cursor_wm
= cursor
->guard_size
;
624 *plane_wm
= display
->guard_size
;
628 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
629 clock
= adjusted_mode
->crtc_clock
;
630 htotal
= adjusted_mode
->crtc_htotal
;
631 hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
632 pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
634 /* Use the small buffer method to calculate plane watermark */
635 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
636 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
639 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
640 *plane_wm
= entries
+ display
->guard_size
;
641 if (*plane_wm
> (int)display
->max_wm
)
642 *plane_wm
= display
->max_wm
;
644 /* Use the large buffer method to calculate cursor watermark */
645 line_time_us
= max(htotal
* 1000 / clock
, 1);
646 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
647 entries
= line_count
* to_intel_crtc(crtc
)->cursor_width
* pixel_size
;
648 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
651 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
652 *cursor_wm
= entries
+ cursor
->guard_size
;
653 if (*cursor_wm
> (int)cursor
->max_wm
)
654 *cursor_wm
= (int)cursor
->max_wm
;
660 * Check the wm result.
662 * If any calculated watermark values is larger than the maximum value that
663 * can be programmed into the associated watermark register, that watermark
666 static bool g4x_check_srwm(struct drm_device
*dev
,
667 int display_wm
, int cursor_wm
,
668 const struct intel_watermark_params
*display
,
669 const struct intel_watermark_params
*cursor
)
671 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
672 display_wm
, cursor_wm
);
674 if (display_wm
> display
->max_wm
) {
675 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
676 display_wm
, display
->max_wm
);
680 if (cursor_wm
> cursor
->max_wm
) {
681 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
682 cursor_wm
, cursor
->max_wm
);
686 if (!(display_wm
|| cursor_wm
)) {
687 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
694 static bool g4x_compute_srwm(struct drm_device
*dev
,
697 const struct intel_watermark_params
*display
,
698 const struct intel_watermark_params
*cursor
,
699 int *display_wm
, int *cursor_wm
)
701 struct drm_crtc
*crtc
;
702 const struct drm_display_mode
*adjusted_mode
;
703 int hdisplay
, htotal
, pixel_size
, clock
;
704 unsigned long line_time_us
;
705 int line_count
, line_size
;
710 *display_wm
= *cursor_wm
= 0;
714 crtc
= intel_get_crtc_for_plane(dev
, plane
);
715 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
716 clock
= adjusted_mode
->crtc_clock
;
717 htotal
= adjusted_mode
->crtc_htotal
;
718 hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
719 pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
721 line_time_us
= max(htotal
* 1000 / clock
, 1);
722 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
723 line_size
= hdisplay
* pixel_size
;
725 /* Use the minimum of the small and large buffer method for primary */
726 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
727 large
= line_count
* line_size
;
729 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
730 *display_wm
= entries
+ display
->guard_size
;
732 /* calculate the self-refresh watermark for display cursor */
733 entries
= line_count
* pixel_size
* to_intel_crtc(crtc
)->cursor_width
;
734 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
735 *cursor_wm
= entries
+ cursor
->guard_size
;
737 return g4x_check_srwm(dev
,
738 *display_wm
, *cursor_wm
,
742 static bool vlv_compute_drain_latency(struct drm_crtc
*crtc
,
747 struct drm_device
*dev
= crtc
->dev
;
749 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
751 if (WARN(clock
== 0, "Pixel clock is zero!\n"))
754 if (WARN(pixel_size
== 0, "Pixel size is zero!\n"))
757 entries
= DIV_ROUND_UP(clock
, 1000) * pixel_size
;
758 if (IS_CHERRYVIEW(dev
))
759 *prec_mult
= (entries
> 128) ? DRAIN_LATENCY_PRECISION_32
:
760 DRAIN_LATENCY_PRECISION_16
;
762 *prec_mult
= (entries
> 128) ? DRAIN_LATENCY_PRECISION_64
:
763 DRAIN_LATENCY_PRECISION_32
;
764 *drain_latency
= (64 * (*prec_mult
) * 4) / entries
;
766 if (*drain_latency
> DRAIN_LATENCY_MASK
)
767 *drain_latency
= DRAIN_LATENCY_MASK
;
773 * Update drain latency registers of memory arbiter
775 * Valleyview SoC has a new memory arbiter and needs drain latency registers
776 * to be programmed. Each plane has a drain latency multiplier and a drain
780 static void vlv_update_drain_latency(struct drm_crtc
*crtc
)
782 struct drm_device
*dev
= crtc
->dev
;
783 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
784 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
787 enum pipe pipe
= intel_crtc
->pipe
;
788 int plane_prec
, prec_mult
, plane_dl
;
789 const int high_precision
= IS_CHERRYVIEW(dev
) ?
790 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_64
;
792 plane_dl
= I915_READ(VLV_DDL(pipe
)) & ~(DDL_PLANE_PRECISION_HIGH
|
793 DRAIN_LATENCY_MASK
| DDL_CURSOR_PRECISION_HIGH
|
794 (DRAIN_LATENCY_MASK
<< DDL_CURSOR_SHIFT
));
796 if (!intel_crtc_active(crtc
)) {
797 I915_WRITE(VLV_DDL(pipe
), plane_dl
);
801 /* Primary plane Drain Latency */
802 pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8; /* BPP */
803 if (vlv_compute_drain_latency(crtc
, pixel_size
, &prec_mult
, &drain_latency
)) {
804 plane_prec
= (prec_mult
== high_precision
) ?
805 DDL_PLANE_PRECISION_HIGH
:
806 DDL_PLANE_PRECISION_LOW
;
807 plane_dl
|= plane_prec
| drain_latency
;
810 /* Cursor Drain Latency
811 * BPP is always 4 for cursor
815 /* Program cursor DL only if it is enabled */
816 if (intel_crtc
->cursor_base
&&
817 vlv_compute_drain_latency(crtc
, pixel_size
, &prec_mult
, &drain_latency
)) {
818 plane_prec
= (prec_mult
== high_precision
) ?
819 DDL_CURSOR_PRECISION_HIGH
:
820 DDL_CURSOR_PRECISION_LOW
;
821 plane_dl
|= plane_prec
| (drain_latency
<< DDL_CURSOR_SHIFT
);
824 I915_WRITE(VLV_DDL(pipe
), plane_dl
);
827 #define single_plane_enabled(mask) is_power_of_2(mask)
829 static void valleyview_update_wm(struct drm_crtc
*crtc
)
831 struct drm_device
*dev
= crtc
->dev
;
832 static const int sr_latency_ns
= 12000;
833 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
834 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
835 int plane_sr
, cursor_sr
;
836 int ignore_plane_sr
, ignore_cursor_sr
;
837 unsigned int enabled
= 0;
840 vlv_update_drain_latency(crtc
);
842 if (g4x_compute_wm0(dev
, PIPE_A
,
843 &valleyview_wm_info
, pessimal_latency_ns
,
844 &valleyview_cursor_wm_info
, pessimal_latency_ns
,
845 &planea_wm
, &cursora_wm
))
846 enabled
|= 1 << PIPE_A
;
848 if (g4x_compute_wm0(dev
, PIPE_B
,
849 &valleyview_wm_info
, pessimal_latency_ns
,
850 &valleyview_cursor_wm_info
, pessimal_latency_ns
,
851 &planeb_wm
, &cursorb_wm
))
852 enabled
|= 1 << PIPE_B
;
854 if (single_plane_enabled(enabled
) &&
855 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
858 &valleyview_cursor_wm_info
,
859 &plane_sr
, &ignore_cursor_sr
) &&
860 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
863 &valleyview_cursor_wm_info
,
864 &ignore_plane_sr
, &cursor_sr
)) {
867 cxsr_enabled
= false;
868 intel_set_memory_cxsr(dev_priv
, false);
869 plane_sr
= cursor_sr
= 0;
872 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
873 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
874 planea_wm
, cursora_wm
,
875 planeb_wm
, cursorb_wm
,
876 plane_sr
, cursor_sr
);
879 (plane_sr
<< DSPFW_SR_SHIFT
) |
880 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
881 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
882 (planea_wm
<< DSPFW_PLANEA_SHIFT
));
884 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
885 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
887 (I915_READ(DSPFW3
) & ~DSPFW_CURSOR_SR_MASK
) |
888 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
891 intel_set_memory_cxsr(dev_priv
, true);
894 static void cherryview_update_wm(struct drm_crtc
*crtc
)
896 struct drm_device
*dev
= crtc
->dev
;
897 static const int sr_latency_ns
= 12000;
898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
899 int planea_wm
, planeb_wm
, planec_wm
;
900 int cursora_wm
, cursorb_wm
, cursorc_wm
;
901 int plane_sr
, cursor_sr
;
902 int ignore_plane_sr
, ignore_cursor_sr
;
903 unsigned int enabled
= 0;
906 vlv_update_drain_latency(crtc
);
908 if (g4x_compute_wm0(dev
, PIPE_A
,
909 &valleyview_wm_info
, pessimal_latency_ns
,
910 &valleyview_cursor_wm_info
, pessimal_latency_ns
,
911 &planea_wm
, &cursora_wm
))
912 enabled
|= 1 << PIPE_A
;
914 if (g4x_compute_wm0(dev
, PIPE_B
,
915 &valleyview_wm_info
, pessimal_latency_ns
,
916 &valleyview_cursor_wm_info
, pessimal_latency_ns
,
917 &planeb_wm
, &cursorb_wm
))
918 enabled
|= 1 << PIPE_B
;
920 if (g4x_compute_wm0(dev
, PIPE_C
,
921 &valleyview_wm_info
, pessimal_latency_ns
,
922 &valleyview_cursor_wm_info
, pessimal_latency_ns
,
923 &planec_wm
, &cursorc_wm
))
924 enabled
|= 1 << PIPE_C
;
926 if (single_plane_enabled(enabled
) &&
927 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
930 &valleyview_cursor_wm_info
,
931 &plane_sr
, &ignore_cursor_sr
) &&
932 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
935 &valleyview_cursor_wm_info
,
936 &ignore_plane_sr
, &cursor_sr
)) {
939 cxsr_enabled
= false;
940 intel_set_memory_cxsr(dev_priv
, false);
941 plane_sr
= cursor_sr
= 0;
944 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
945 "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
946 "SR: plane=%d, cursor=%d\n",
947 planea_wm
, cursora_wm
,
948 planeb_wm
, cursorb_wm
,
949 planec_wm
, cursorc_wm
,
950 plane_sr
, cursor_sr
);
953 (plane_sr
<< DSPFW_SR_SHIFT
) |
954 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
955 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
956 (planea_wm
<< DSPFW_PLANEA_SHIFT
));
958 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
959 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
961 (I915_READ(DSPFW3
) & ~DSPFW_CURSOR_SR_MASK
) |
962 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
963 I915_WRITE(DSPFW9_CHV
,
964 (I915_READ(DSPFW9_CHV
) & ~(DSPFW_PLANEC_MASK
|
965 DSPFW_CURSORC_MASK
)) |
966 (planec_wm
<< DSPFW_PLANEC_SHIFT
) |
967 (cursorc_wm
<< DSPFW_CURSORC_SHIFT
));
970 intel_set_memory_cxsr(dev_priv
, true);
973 static void valleyview_update_sprite_wm(struct drm_plane
*plane
,
974 struct drm_crtc
*crtc
,
975 uint32_t sprite_width
,
976 uint32_t sprite_height
,
978 bool enabled
, bool scaled
)
980 struct drm_device
*dev
= crtc
->dev
;
981 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
982 int pipe
= to_intel_plane(plane
)->pipe
;
983 int sprite
= to_intel_plane(plane
)->plane
;
988 const int high_precision
= IS_CHERRYVIEW(dev
) ?
989 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_64
;
991 sprite_dl
= I915_READ(VLV_DDL(pipe
)) & ~(DDL_SPRITE_PRECISION_HIGH(sprite
) |
992 (DRAIN_LATENCY_MASK
<< DDL_SPRITE_SHIFT(sprite
)));
994 if (enabled
&& vlv_compute_drain_latency(crtc
, pixel_size
, &prec_mult
,
996 plane_prec
= (prec_mult
== high_precision
) ?
997 DDL_SPRITE_PRECISION_HIGH(sprite
) :
998 DDL_SPRITE_PRECISION_LOW(sprite
);
999 sprite_dl
|= plane_prec
|
1000 (drain_latency
<< DDL_SPRITE_SHIFT(sprite
));
1003 I915_WRITE(VLV_DDL(pipe
), sprite_dl
);
1006 static void g4x_update_wm(struct drm_crtc
*crtc
)
1008 struct drm_device
*dev
= crtc
->dev
;
1009 static const int sr_latency_ns
= 12000;
1010 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1011 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1012 int plane_sr
, cursor_sr
;
1013 unsigned int enabled
= 0;
1016 if (g4x_compute_wm0(dev
, PIPE_A
,
1017 &g4x_wm_info
, pessimal_latency_ns
,
1018 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1019 &planea_wm
, &cursora_wm
))
1020 enabled
|= 1 << PIPE_A
;
1022 if (g4x_compute_wm0(dev
, PIPE_B
,
1023 &g4x_wm_info
, pessimal_latency_ns
,
1024 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1025 &planeb_wm
, &cursorb_wm
))
1026 enabled
|= 1 << PIPE_B
;
1028 if (single_plane_enabled(enabled
) &&
1029 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1032 &g4x_cursor_wm_info
,
1033 &plane_sr
, &cursor_sr
)) {
1034 cxsr_enabled
= true;
1036 cxsr_enabled
= false;
1037 intel_set_memory_cxsr(dev_priv
, false);
1038 plane_sr
= cursor_sr
= 0;
1041 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1042 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1043 planea_wm
, cursora_wm
,
1044 planeb_wm
, cursorb_wm
,
1045 plane_sr
, cursor_sr
);
1048 (plane_sr
<< DSPFW_SR_SHIFT
) |
1049 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1050 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1051 (planea_wm
<< DSPFW_PLANEA_SHIFT
));
1053 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1054 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1055 /* HPLL off in SR has some issues on G4x... disable it */
1057 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1058 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1061 intel_set_memory_cxsr(dev_priv
, true);
1064 static void i965_update_wm(struct drm_crtc
*unused_crtc
)
1066 struct drm_device
*dev
= unused_crtc
->dev
;
1067 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1068 struct drm_crtc
*crtc
;
1073 /* Calc sr entries for one plane configs */
1074 crtc
= single_enabled_crtc(dev
);
1076 /* self-refresh has much higher latency */
1077 static const int sr_latency_ns
= 12000;
1078 const struct drm_display_mode
*adjusted_mode
=
1079 &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1080 int clock
= adjusted_mode
->crtc_clock
;
1081 int htotal
= adjusted_mode
->crtc_htotal
;
1082 int hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
1083 int pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1084 unsigned long line_time_us
;
1087 line_time_us
= max(htotal
* 1000 / clock
, 1);
1089 /* Use ns/us then divide to preserve precision */
1090 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1091 pixel_size
* hdisplay
;
1092 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1093 srwm
= I965_FIFO_SIZE
- entries
;
1097 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1100 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1101 pixel_size
* to_intel_crtc(crtc
)->cursor_width
;
1102 entries
= DIV_ROUND_UP(entries
,
1103 i965_cursor_wm_info
.cacheline_size
);
1104 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1105 (entries
+ i965_cursor_wm_info
.guard_size
);
1107 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1108 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1110 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1111 "cursor %d\n", srwm
, cursor_sr
);
1113 cxsr_enabled
= true;
1115 cxsr_enabled
= false;
1116 /* Turn off self refresh if both pipes are enabled */
1117 intel_set_memory_cxsr(dev_priv
, false);
1120 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1123 /* 965 has limitations... */
1124 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) |
1125 (8 << DSPFW_CURSORB_SHIFT
) |
1126 (8 << DSPFW_PLANEB_SHIFT
) |
1127 (8 << DSPFW_PLANEA_SHIFT
));
1128 I915_WRITE(DSPFW2
, (8 << DSPFW_CURSORA_SHIFT
) |
1129 (8 << DSPFW_PLANEC_SHIFT_OLD
));
1130 /* update cursor SR watermark */
1131 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1134 intel_set_memory_cxsr(dev_priv
, true);
1137 static void i9xx_update_wm(struct drm_crtc
*unused_crtc
)
1139 struct drm_device
*dev
= unused_crtc
->dev
;
1140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1141 const struct intel_watermark_params
*wm_info
;
1146 int planea_wm
, planeb_wm
;
1147 struct drm_crtc
*crtc
, *enabled
= NULL
;
1150 wm_info
= &i945_wm_info
;
1151 else if (!IS_GEN2(dev
))
1152 wm_info
= &i915_wm_info
;
1154 wm_info
= &i830_a_wm_info
;
1156 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
1157 crtc
= intel_get_crtc_for_plane(dev
, 0);
1158 if (intel_crtc_active(crtc
)) {
1159 const struct drm_display_mode
*adjusted_mode
;
1160 int cpp
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1164 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1165 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1166 wm_info
, fifo_size
, cpp
,
1167 pessimal_latency_ns
);
1170 planea_wm
= fifo_size
- wm_info
->guard_size
;
1171 if (planea_wm
> (long)wm_info
->max_wm
)
1172 planea_wm
= wm_info
->max_wm
;
1176 wm_info
= &i830_bc_wm_info
;
1178 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
1179 crtc
= intel_get_crtc_for_plane(dev
, 1);
1180 if (intel_crtc_active(crtc
)) {
1181 const struct drm_display_mode
*adjusted_mode
;
1182 int cpp
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1186 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1187 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1188 wm_info
, fifo_size
, cpp
,
1189 pessimal_latency_ns
);
1190 if (enabled
== NULL
)
1195 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1196 if (planeb_wm
> (long)wm_info
->max_wm
)
1197 planeb_wm
= wm_info
->max_wm
;
1200 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1202 if (IS_I915GM(dev
) && enabled
) {
1203 struct drm_i915_gem_object
*obj
;
1205 obj
= intel_fb_obj(enabled
->primary
->fb
);
1207 /* self-refresh seems busted with untiled */
1208 if (obj
->tiling_mode
== I915_TILING_NONE
)
1213 * Overlay gets an aggressive default since video jitter is bad.
1217 /* Play safe and disable self-refresh before adjusting watermarks. */
1218 intel_set_memory_cxsr(dev_priv
, false);
1220 /* Calc sr entries for one plane configs */
1221 if (HAS_FW_BLC(dev
) && enabled
) {
1222 /* self-refresh has much higher latency */
1223 static const int sr_latency_ns
= 6000;
1224 const struct drm_display_mode
*adjusted_mode
=
1225 &to_intel_crtc(enabled
)->config
->base
.adjusted_mode
;
1226 int clock
= adjusted_mode
->crtc_clock
;
1227 int htotal
= adjusted_mode
->crtc_htotal
;
1228 int hdisplay
= to_intel_crtc(enabled
)->config
->pipe_src_w
;
1229 int pixel_size
= enabled
->primary
->fb
->bits_per_pixel
/ 8;
1230 unsigned long line_time_us
;
1233 line_time_us
= max(htotal
* 1000 / clock
, 1);
1235 /* Use ns/us then divide to preserve precision */
1236 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1237 pixel_size
* hdisplay
;
1238 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1239 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1240 srwm
= wm_info
->fifo_size
- entries
;
1244 if (IS_I945G(dev
) || IS_I945GM(dev
))
1245 I915_WRITE(FW_BLC_SELF
,
1246 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1247 else if (IS_I915GM(dev
))
1248 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1251 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1252 planea_wm
, planeb_wm
, cwm
, srwm
);
1254 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1255 fwater_hi
= (cwm
& 0x1f);
1257 /* Set request length to 8 cachelines per fetch */
1258 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1259 fwater_hi
= fwater_hi
| (1 << 8);
1261 I915_WRITE(FW_BLC
, fwater_lo
);
1262 I915_WRITE(FW_BLC2
, fwater_hi
);
1265 intel_set_memory_cxsr(dev_priv
, true);
1268 static void i845_update_wm(struct drm_crtc
*unused_crtc
)
1270 struct drm_device
*dev
= unused_crtc
->dev
;
1271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1272 struct drm_crtc
*crtc
;
1273 const struct drm_display_mode
*adjusted_mode
;
1277 crtc
= single_enabled_crtc(dev
);
1281 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1282 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1284 dev_priv
->display
.get_fifo_size(dev
, 0),
1285 4, pessimal_latency_ns
);
1286 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1287 fwater_lo
|= (3<<8) | planea_wm
;
1289 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1291 I915_WRITE(FW_BLC
, fwater_lo
);
1294 static uint32_t ilk_pipe_pixel_rate(struct drm_device
*dev
,
1295 struct drm_crtc
*crtc
)
1297 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1298 uint32_t pixel_rate
;
1300 pixel_rate
= intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1302 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1303 * adjust the pixel_rate here. */
1305 if (intel_crtc
->config
->pch_pfit
.enabled
) {
1306 uint64_t pipe_w
, pipe_h
, pfit_w
, pfit_h
;
1307 uint32_t pfit_size
= intel_crtc
->config
->pch_pfit
.size
;
1309 pipe_w
= intel_crtc
->config
->pipe_src_w
;
1310 pipe_h
= intel_crtc
->config
->pipe_src_h
;
1311 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
1312 pfit_h
= pfit_size
& 0xFFFF;
1313 if (pipe_w
< pfit_w
)
1315 if (pipe_h
< pfit_h
)
1318 pixel_rate
= div_u64((uint64_t) pixel_rate
* pipe_w
* pipe_h
,
1325 /* latency must be in 0.1us units. */
1326 static uint32_t ilk_wm_method1(uint32_t pixel_rate
, uint8_t bytes_per_pixel
,
1331 if (WARN(latency
== 0, "Latency value missing\n"))
1334 ret
= (uint64_t) pixel_rate
* bytes_per_pixel
* latency
;
1335 ret
= DIV_ROUND_UP_ULL(ret
, 64 * 10000) + 2;
1340 /* latency must be in 0.1us units. */
1341 static uint32_t ilk_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
1342 uint32_t horiz_pixels
, uint8_t bytes_per_pixel
,
1347 if (WARN(latency
== 0, "Latency value missing\n"))
1350 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
1351 ret
= (ret
+ 1) * horiz_pixels
* bytes_per_pixel
;
1352 ret
= DIV_ROUND_UP(ret
, 64) + 2;
1356 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
1357 uint8_t bytes_per_pixel
)
1359 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* bytes_per_pixel
) + 2;
1362 struct skl_pipe_wm_parameters
{
1364 uint32_t pipe_htotal
;
1365 uint32_t pixel_rate
; /* in KHz */
1366 struct intel_plane_wm_parameters plane
[I915_MAX_PLANES
];
1367 struct intel_plane_wm_parameters cursor
;
1370 struct ilk_pipe_wm_parameters
{
1372 uint32_t pipe_htotal
;
1373 uint32_t pixel_rate
;
1374 struct intel_plane_wm_parameters pri
;
1375 struct intel_plane_wm_parameters spr
;
1376 struct intel_plane_wm_parameters cur
;
1379 struct ilk_wm_maximums
{
1386 /* used in computing the new watermarks state */
1387 struct intel_wm_config
{
1388 unsigned int num_pipes_active
;
1389 bool sprites_enabled
;
1390 bool sprites_scaled
;
1394 * For both WM_PIPE and WM_LP.
1395 * mem_value must be in 0.1us units.
1397 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters
*params
,
1401 uint32_t method1
, method2
;
1403 if (!params
->active
|| !params
->pri
.enabled
)
1406 method1
= ilk_wm_method1(params
->pixel_rate
,
1407 params
->pri
.bytes_per_pixel
,
1413 method2
= ilk_wm_method2(params
->pixel_rate
,
1414 params
->pipe_htotal
,
1415 params
->pri
.horiz_pixels
,
1416 params
->pri
.bytes_per_pixel
,
1419 return min(method1
, method2
);
1423 * For both WM_PIPE and WM_LP.
1424 * mem_value must be in 0.1us units.
1426 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters
*params
,
1429 uint32_t method1
, method2
;
1431 if (!params
->active
|| !params
->spr
.enabled
)
1434 method1
= ilk_wm_method1(params
->pixel_rate
,
1435 params
->spr
.bytes_per_pixel
,
1437 method2
= ilk_wm_method2(params
->pixel_rate
,
1438 params
->pipe_htotal
,
1439 params
->spr
.horiz_pixels
,
1440 params
->spr
.bytes_per_pixel
,
1442 return min(method1
, method2
);
1446 * For both WM_PIPE and WM_LP.
1447 * mem_value must be in 0.1us units.
1449 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters
*params
,
1452 if (!params
->active
|| !params
->cur
.enabled
)
1455 return ilk_wm_method2(params
->pixel_rate
,
1456 params
->pipe_htotal
,
1457 params
->cur
.horiz_pixels
,
1458 params
->cur
.bytes_per_pixel
,
1462 /* Only for WM_LP. */
1463 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters
*params
,
1466 if (!params
->active
|| !params
->pri
.enabled
)
1469 return ilk_wm_fbc(pri_val
,
1470 params
->pri
.horiz_pixels
,
1471 params
->pri
.bytes_per_pixel
);
1474 static unsigned int ilk_display_fifo_size(const struct drm_device
*dev
)
1476 if (INTEL_INFO(dev
)->gen
>= 8)
1478 else if (INTEL_INFO(dev
)->gen
>= 7)
1484 static unsigned int ilk_plane_wm_reg_max(const struct drm_device
*dev
,
1485 int level
, bool is_sprite
)
1487 if (INTEL_INFO(dev
)->gen
>= 8)
1488 /* BDW primary/sprite plane watermarks */
1489 return level
== 0 ? 255 : 2047;
1490 else if (INTEL_INFO(dev
)->gen
>= 7)
1491 /* IVB/HSW primary/sprite plane watermarks */
1492 return level
== 0 ? 127 : 1023;
1493 else if (!is_sprite
)
1494 /* ILK/SNB primary plane watermarks */
1495 return level
== 0 ? 127 : 511;
1497 /* ILK/SNB sprite plane watermarks */
1498 return level
== 0 ? 63 : 255;
1501 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device
*dev
,
1504 if (INTEL_INFO(dev
)->gen
>= 7)
1505 return level
== 0 ? 63 : 255;
1507 return level
== 0 ? 31 : 63;
1510 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device
*dev
)
1512 if (INTEL_INFO(dev
)->gen
>= 8)
1518 /* Calculate the maximum primary/sprite plane watermark */
1519 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
1521 const struct intel_wm_config
*config
,
1522 enum intel_ddb_partitioning ddb_partitioning
,
1525 unsigned int fifo_size
= ilk_display_fifo_size(dev
);
1527 /* if sprites aren't enabled, sprites get nothing */
1528 if (is_sprite
&& !config
->sprites_enabled
)
1531 /* HSW allows LP1+ watermarks even with multiple pipes */
1532 if (level
== 0 || config
->num_pipes_active
> 1) {
1533 fifo_size
/= INTEL_INFO(dev
)->num_pipes
;
1536 * For some reason the non self refresh
1537 * FIFO size is only half of the self
1538 * refresh FIFO size on ILK/SNB.
1540 if (INTEL_INFO(dev
)->gen
<= 6)
1544 if (config
->sprites_enabled
) {
1545 /* level 0 is always calculated with 1:1 split */
1546 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
1555 /* clamp to max that the registers can hold */
1556 return min(fifo_size
, ilk_plane_wm_reg_max(dev
, level
, is_sprite
));
1559 /* Calculate the maximum cursor plane watermark */
1560 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
1562 const struct intel_wm_config
*config
)
1564 /* HSW LP1+ watermarks w/ multiple pipes */
1565 if (level
> 0 && config
->num_pipes_active
> 1)
1568 /* otherwise just report max that registers can hold */
1569 return ilk_cursor_wm_reg_max(dev
, level
);
1572 static void ilk_compute_wm_maximums(const struct drm_device
*dev
,
1574 const struct intel_wm_config
*config
,
1575 enum intel_ddb_partitioning ddb_partitioning
,
1576 struct ilk_wm_maximums
*max
)
1578 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
1579 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
1580 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
1581 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
1584 static void ilk_compute_wm_reg_maximums(struct drm_device
*dev
,
1586 struct ilk_wm_maximums
*max
)
1588 max
->pri
= ilk_plane_wm_reg_max(dev
, level
, false);
1589 max
->spr
= ilk_plane_wm_reg_max(dev
, level
, true);
1590 max
->cur
= ilk_cursor_wm_reg_max(dev
, level
);
1591 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
1594 static bool ilk_validate_wm_level(int level
,
1595 const struct ilk_wm_maximums
*max
,
1596 struct intel_wm_level
*result
)
1600 /* already determined to be invalid? */
1601 if (!result
->enable
)
1604 result
->enable
= result
->pri_val
<= max
->pri
&&
1605 result
->spr_val
<= max
->spr
&&
1606 result
->cur_val
<= max
->cur
;
1608 ret
= result
->enable
;
1611 * HACK until we can pre-compute everything,
1612 * and thus fail gracefully if LP0 watermarks
1615 if (level
== 0 && !result
->enable
) {
1616 if (result
->pri_val
> max
->pri
)
1617 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1618 level
, result
->pri_val
, max
->pri
);
1619 if (result
->spr_val
> max
->spr
)
1620 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1621 level
, result
->spr_val
, max
->spr
);
1622 if (result
->cur_val
> max
->cur
)
1623 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1624 level
, result
->cur_val
, max
->cur
);
1626 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
1627 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
1628 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
1629 result
->enable
= true;
1635 static void ilk_compute_wm_level(const struct drm_i915_private
*dev_priv
,
1637 const struct ilk_pipe_wm_parameters
*p
,
1638 struct intel_wm_level
*result
)
1640 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
1641 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
1642 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
1644 /* WM1+ latency values stored in 0.5us units */
1651 result
->pri_val
= ilk_compute_pri_wm(p
, pri_latency
, level
);
1652 result
->spr_val
= ilk_compute_spr_wm(p
, spr_latency
);
1653 result
->cur_val
= ilk_compute_cur_wm(p
, cur_latency
);
1654 result
->fbc_val
= ilk_compute_fbc_wm(p
, result
->pri_val
);
1655 result
->enable
= true;
1659 hsw_compute_linetime_wm(struct drm_device
*dev
, struct drm_crtc
*crtc
)
1661 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1662 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1663 struct drm_display_mode
*mode
= &intel_crtc
->config
->base
.adjusted_mode
;
1664 u32 linetime
, ips_linetime
;
1666 if (!intel_crtc_active(crtc
))
1669 /* The WM are computed with base on how long it takes to fill a single
1670 * row at the given clock rate, multiplied by 8.
1672 linetime
= DIV_ROUND_CLOSEST(mode
->crtc_htotal
* 1000 * 8,
1674 ips_linetime
= DIV_ROUND_CLOSEST(mode
->crtc_htotal
* 1000 * 8,
1675 intel_ddi_get_cdclk_freq(dev_priv
));
1677 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
1678 PIPE_WM_LINETIME_TIME(linetime
);
1681 static void intel_read_wm_latency(struct drm_device
*dev
, uint16_t wm
[8])
1683 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1688 int level
, max_level
= ilk_wm_max_level(dev
);
1690 /* read the first set of memory latencies[0:3] */
1691 val
= 0; /* data0 to be programmed to 0 for first set */
1692 mutex_lock(&dev_priv
->rps
.hw_lock
);
1693 ret
= sandybridge_pcode_read(dev_priv
,
1694 GEN9_PCODE_READ_MEM_LATENCY
,
1696 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1699 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
1703 wm
[0] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
1704 wm
[1] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
1705 GEN9_MEM_LATENCY_LEVEL_MASK
;
1706 wm
[2] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
1707 GEN9_MEM_LATENCY_LEVEL_MASK
;
1708 wm
[3] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
1709 GEN9_MEM_LATENCY_LEVEL_MASK
;
1711 /* read the second set of memory latencies[4:7] */
1712 val
= 1; /* data0 to be programmed to 1 for second set */
1713 mutex_lock(&dev_priv
->rps
.hw_lock
);
1714 ret
= sandybridge_pcode_read(dev_priv
,
1715 GEN9_PCODE_READ_MEM_LATENCY
,
1717 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1719 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
1723 wm
[4] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
1724 wm
[5] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
1725 GEN9_MEM_LATENCY_LEVEL_MASK
;
1726 wm
[6] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
1727 GEN9_MEM_LATENCY_LEVEL_MASK
;
1728 wm
[7] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
1729 GEN9_MEM_LATENCY_LEVEL_MASK
;
1732 * WaWmMemoryReadLatency:skl
1734 * punit doesn't take into account the read latency so we need
1735 * to add 2us to the various latency levels we retrieve from
1737 * - W0 is a bit special in that it's the only level that
1738 * can't be disabled if we want to have display working, so
1739 * we always add 2us there.
1740 * - For levels >=1, punit returns 0us latency when they are
1741 * disabled, so we respect that and don't add 2us then
1743 * Additionally, if a level n (n > 1) has a 0us latency, all
1744 * levels m (m >= n) need to be disabled. We make sure to
1745 * sanitize the values out of the punit to satisfy this
1749 for (level
= 1; level
<= max_level
; level
++)
1753 for (i
= level
+ 1; i
<= max_level
; i
++)
1758 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
1759 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
1761 wm
[0] = (sskpd
>> 56) & 0xFF;
1763 wm
[0] = sskpd
& 0xF;
1764 wm
[1] = (sskpd
>> 4) & 0xFF;
1765 wm
[2] = (sskpd
>> 12) & 0xFF;
1766 wm
[3] = (sskpd
>> 20) & 0x1FF;
1767 wm
[4] = (sskpd
>> 32) & 0x1FF;
1768 } else if (INTEL_INFO(dev
)->gen
>= 6) {
1769 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
1771 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
1772 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
1773 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
1774 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
1775 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1776 uint32_t mltr
= I915_READ(MLTR_ILK
);
1778 /* ILK primary LP0 latency is 700 ns */
1780 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
1781 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
1785 static void intel_fixup_spr_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
1787 /* ILK sprite LP0 latency is 1300 ns */
1788 if (INTEL_INFO(dev
)->gen
== 5)
1792 static void intel_fixup_cur_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
1794 /* ILK cursor LP0 latency is 1300 ns */
1795 if (INTEL_INFO(dev
)->gen
== 5)
1798 /* WaDoubleCursorLP3Latency:ivb */
1799 if (IS_IVYBRIDGE(dev
))
1803 int ilk_wm_max_level(const struct drm_device
*dev
)
1805 /* how many WM levels are we expecting */
1808 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1810 else if (INTEL_INFO(dev
)->gen
>= 6)
1816 static void intel_print_wm_latency(struct drm_device
*dev
,
1818 const uint16_t wm
[8])
1820 int level
, max_level
= ilk_wm_max_level(dev
);
1822 for (level
= 0; level
<= max_level
; level
++) {
1823 unsigned int latency
= wm
[level
];
1826 DRM_ERROR("%s WM%d latency not provided\n",
1832 * - latencies are in us on gen9.
1833 * - before then, WM1+ latency values are in 0.5us units
1840 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
1841 name
, level
, wm
[level
],
1842 latency
/ 10, latency
% 10);
1846 static bool ilk_increase_wm_latency(struct drm_i915_private
*dev_priv
,
1847 uint16_t wm
[5], uint16_t min
)
1849 int level
, max_level
= ilk_wm_max_level(dev_priv
->dev
);
1854 wm
[0] = max(wm
[0], min
);
1855 for (level
= 1; level
<= max_level
; level
++)
1856 wm
[level
] = max_t(uint16_t, wm
[level
], DIV_ROUND_UP(min
, 5));
1861 static void snb_wm_latency_quirk(struct drm_device
*dev
)
1863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1867 * The BIOS provided WM memory latency values are often
1868 * inadequate for high resolution displays. Adjust them.
1870 changed
= ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
, 12) |
1871 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
, 12) |
1872 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
, 12);
1877 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
1878 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
1879 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
1880 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
1883 static void ilk_setup_wm_latency(struct drm_device
*dev
)
1885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1887 intel_read_wm_latency(dev
, dev_priv
->wm
.pri_latency
);
1889 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
1890 sizeof(dev_priv
->wm
.pri_latency
));
1891 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
1892 sizeof(dev_priv
->wm
.pri_latency
));
1894 intel_fixup_spr_wm_latency(dev
, dev_priv
->wm
.spr_latency
);
1895 intel_fixup_cur_wm_latency(dev
, dev_priv
->wm
.cur_latency
);
1897 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
1898 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
1899 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
1902 snb_wm_latency_quirk(dev
);
1905 static void skl_setup_wm_latency(struct drm_device
*dev
)
1907 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1909 intel_read_wm_latency(dev
, dev_priv
->wm
.skl_latency
);
1910 intel_print_wm_latency(dev
, "Gen9 Plane", dev_priv
->wm
.skl_latency
);
1913 static void ilk_compute_wm_parameters(struct drm_crtc
*crtc
,
1914 struct ilk_pipe_wm_parameters
*p
)
1916 struct drm_device
*dev
= crtc
->dev
;
1917 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1918 enum pipe pipe
= intel_crtc
->pipe
;
1919 struct drm_plane
*plane
;
1921 if (!intel_crtc_active(crtc
))
1925 p
->pipe_htotal
= intel_crtc
->config
->base
.adjusted_mode
.crtc_htotal
;
1926 p
->pixel_rate
= ilk_pipe_pixel_rate(dev
, crtc
);
1927 p
->pri
.bytes_per_pixel
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1928 p
->cur
.bytes_per_pixel
= 4;
1929 p
->pri
.horiz_pixels
= intel_crtc
->config
->pipe_src_w
;
1930 p
->cur
.horiz_pixels
= intel_crtc
->cursor_width
;
1931 /* TODO: for now, assume primary and cursor planes are always enabled. */
1932 p
->pri
.enabled
= true;
1933 p
->cur
.enabled
= true;
1935 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
1936 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
1938 if (intel_plane
->pipe
== pipe
) {
1939 p
->spr
= intel_plane
->wm
;
1945 static void ilk_compute_wm_config(struct drm_device
*dev
,
1946 struct intel_wm_config
*config
)
1948 struct intel_crtc
*intel_crtc
;
1950 /* Compute the currently _active_ config */
1951 for_each_intel_crtc(dev
, intel_crtc
) {
1952 const struct intel_pipe_wm
*wm
= &intel_crtc
->wm
.active
;
1954 if (!wm
->pipe_enabled
)
1957 config
->sprites_enabled
|= wm
->sprites_enabled
;
1958 config
->sprites_scaled
|= wm
->sprites_scaled
;
1959 config
->num_pipes_active
++;
1963 /* Compute new watermarks for the pipe */
1964 static bool intel_compute_pipe_wm(struct drm_crtc
*crtc
,
1965 const struct ilk_pipe_wm_parameters
*params
,
1966 struct intel_pipe_wm
*pipe_wm
)
1968 struct drm_device
*dev
= crtc
->dev
;
1969 const struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1970 int level
, max_level
= ilk_wm_max_level(dev
);
1971 /* LP0 watermark maximums depend on this pipe alone */
1972 struct intel_wm_config config
= {
1973 .num_pipes_active
= 1,
1974 .sprites_enabled
= params
->spr
.enabled
,
1975 .sprites_scaled
= params
->spr
.scaled
,
1977 struct ilk_wm_maximums max
;
1979 pipe_wm
->pipe_enabled
= params
->active
;
1980 pipe_wm
->sprites_enabled
= params
->spr
.enabled
;
1981 pipe_wm
->sprites_scaled
= params
->spr
.scaled
;
1983 /* ILK/SNB: LP2+ watermarks only w/o sprites */
1984 if (INTEL_INFO(dev
)->gen
<= 6 && params
->spr
.enabled
)
1987 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
1988 if (params
->spr
.scaled
)
1991 ilk_compute_wm_level(dev_priv
, 0, params
, &pipe_wm
->wm
[0]);
1993 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1994 pipe_wm
->linetime
= hsw_compute_linetime_wm(dev
, crtc
);
1996 /* LP0 watermarks always use 1/2 DDB partitioning */
1997 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
1999 /* At least LP0 must be valid */
2000 if (!ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0]))
2003 ilk_compute_wm_reg_maximums(dev
, 1, &max
);
2005 for (level
= 1; level
<= max_level
; level
++) {
2006 struct intel_wm_level wm
= {};
2008 ilk_compute_wm_level(dev_priv
, level
, params
, &wm
);
2011 * Disable any watermark level that exceeds the
2012 * register maximums since such watermarks are
2015 if (!ilk_validate_wm_level(level
, &max
, &wm
))
2018 pipe_wm
->wm
[level
] = wm
;
2025 * Merge the watermarks from all active pipes for a specific level.
2027 static void ilk_merge_wm_level(struct drm_device
*dev
,
2029 struct intel_wm_level
*ret_wm
)
2031 const struct intel_crtc
*intel_crtc
;
2033 ret_wm
->enable
= true;
2035 for_each_intel_crtc(dev
, intel_crtc
) {
2036 const struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
;
2037 const struct intel_wm_level
*wm
= &active
->wm
[level
];
2039 if (!active
->pipe_enabled
)
2043 * The watermark values may have been used in the past,
2044 * so we must maintain them in the registers for some
2045 * time even if the level is now disabled.
2048 ret_wm
->enable
= false;
2050 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
2051 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
2052 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
2053 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
2058 * Merge all low power watermarks for all active pipes.
2060 static void ilk_wm_merge(struct drm_device
*dev
,
2061 const struct intel_wm_config
*config
,
2062 const struct ilk_wm_maximums
*max
,
2063 struct intel_pipe_wm
*merged
)
2065 int level
, max_level
= ilk_wm_max_level(dev
);
2066 int last_enabled_level
= max_level
;
2068 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2069 if ((INTEL_INFO(dev
)->gen
<= 6 || IS_IVYBRIDGE(dev
)) &&
2070 config
->num_pipes_active
> 1)
2073 /* ILK: FBC WM must be disabled always */
2074 merged
->fbc_wm_enabled
= INTEL_INFO(dev
)->gen
>= 6;
2076 /* merge each WM1+ level */
2077 for (level
= 1; level
<= max_level
; level
++) {
2078 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2080 ilk_merge_wm_level(dev
, level
, wm
);
2082 if (level
> last_enabled_level
)
2084 else if (!ilk_validate_wm_level(level
, max
, wm
))
2085 /* make sure all following levels get disabled */
2086 last_enabled_level
= level
- 1;
2089 * The spec says it is preferred to disable
2090 * FBC WMs instead of disabling a WM level.
2092 if (wm
->fbc_val
> max
->fbc
) {
2094 merged
->fbc_wm_enabled
= false;
2099 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2101 * FIXME this is racy. FBC might get enabled later.
2102 * What we should check here is whether FBC can be
2103 * enabled sometime later.
2105 if (IS_GEN5(dev
) && !merged
->fbc_wm_enabled
&& intel_fbc_enabled(dev
)) {
2106 for (level
= 2; level
<= max_level
; level
++) {
2107 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2114 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
2116 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2117 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
2120 /* The value we need to program into the WM_LPx latency field */
2121 static unsigned int ilk_wm_lp_latency(struct drm_device
*dev
, int level
)
2123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2125 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2128 return dev_priv
->wm
.pri_latency
[level
];
2131 static void ilk_compute_wm_results(struct drm_device
*dev
,
2132 const struct intel_pipe_wm
*merged
,
2133 enum intel_ddb_partitioning partitioning
,
2134 struct ilk_wm_values
*results
)
2136 struct intel_crtc
*intel_crtc
;
2139 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
2140 results
->partitioning
= partitioning
;
2142 /* LP1+ register values */
2143 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2144 const struct intel_wm_level
*r
;
2146 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
2148 r
= &merged
->wm
[level
];
2151 * Maintain the watermark values even if the level is
2152 * disabled. Doing otherwise could cause underruns.
2154 results
->wm_lp
[wm_lp
- 1] =
2155 (ilk_wm_lp_latency(dev
, level
) << WM1_LP_LATENCY_SHIFT
) |
2156 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
2160 results
->wm_lp
[wm_lp
- 1] |= WM1_LP_SR_EN
;
2162 if (INTEL_INFO(dev
)->gen
>= 8)
2163 results
->wm_lp
[wm_lp
- 1] |=
2164 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
2166 results
->wm_lp
[wm_lp
- 1] |=
2167 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
2170 * Always set WM1S_LP_EN when spr_val != 0, even if the
2171 * level is disabled. Doing otherwise could cause underruns.
2173 if (INTEL_INFO(dev
)->gen
<= 6 && r
->spr_val
) {
2174 WARN_ON(wm_lp
!= 1);
2175 results
->wm_lp_spr
[wm_lp
- 1] = WM1S_LP_EN
| r
->spr_val
;
2177 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
2180 /* LP0 register values */
2181 for_each_intel_crtc(dev
, intel_crtc
) {
2182 enum pipe pipe
= intel_crtc
->pipe
;
2183 const struct intel_wm_level
*r
=
2184 &intel_crtc
->wm
.active
.wm
[0];
2186 if (WARN_ON(!r
->enable
))
2189 results
->wm_linetime
[pipe
] = intel_crtc
->wm
.active
.linetime
;
2191 results
->wm_pipe
[pipe
] =
2192 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
2193 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
2198 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2199 * case both are at the same level. Prefer r1 in case they're the same. */
2200 static struct intel_pipe_wm
*ilk_find_best_result(struct drm_device
*dev
,
2201 struct intel_pipe_wm
*r1
,
2202 struct intel_pipe_wm
*r2
)
2204 int level
, max_level
= ilk_wm_max_level(dev
);
2205 int level1
= 0, level2
= 0;
2207 for (level
= 1; level
<= max_level
; level
++) {
2208 if (r1
->wm
[level
].enable
)
2210 if (r2
->wm
[level
].enable
)
2214 if (level1
== level2
) {
2215 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
2219 } else if (level1
> level2
) {
2226 /* dirty bits used to track which watermarks need changes */
2227 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2228 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2229 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2230 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2231 #define WM_DIRTY_FBC (1 << 24)
2232 #define WM_DIRTY_DDB (1 << 25)
2234 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private
*dev_priv
,
2235 const struct ilk_wm_values
*old
,
2236 const struct ilk_wm_values
*new)
2238 unsigned int dirty
= 0;
2242 for_each_pipe(dev_priv
, pipe
) {
2243 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
2244 dirty
|= WM_DIRTY_LINETIME(pipe
);
2245 /* Must disable LP1+ watermarks too */
2246 dirty
|= WM_DIRTY_LP_ALL
;
2249 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
2250 dirty
|= WM_DIRTY_PIPE(pipe
);
2251 /* Must disable LP1+ watermarks too */
2252 dirty
|= WM_DIRTY_LP_ALL
;
2256 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
2257 dirty
|= WM_DIRTY_FBC
;
2258 /* Must disable LP1+ watermarks too */
2259 dirty
|= WM_DIRTY_LP_ALL
;
2262 if (old
->partitioning
!= new->partitioning
) {
2263 dirty
|= WM_DIRTY_DDB
;
2264 /* Must disable LP1+ watermarks too */
2265 dirty
|= WM_DIRTY_LP_ALL
;
2268 /* LP1+ watermarks already deemed dirty, no need to continue */
2269 if (dirty
& WM_DIRTY_LP_ALL
)
2272 /* Find the lowest numbered LP1+ watermark in need of an update... */
2273 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2274 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
2275 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
2279 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2280 for (; wm_lp
<= 3; wm_lp
++)
2281 dirty
|= WM_DIRTY_LP(wm_lp
);
2286 static bool _ilk_disable_lp_wm(struct drm_i915_private
*dev_priv
,
2289 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2290 bool changed
= false;
2292 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] & WM1_LP_SR_EN
) {
2293 previous
->wm_lp
[2] &= ~WM1_LP_SR_EN
;
2294 I915_WRITE(WM3_LP_ILK
, previous
->wm_lp
[2]);
2297 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] & WM1_LP_SR_EN
) {
2298 previous
->wm_lp
[1] &= ~WM1_LP_SR_EN
;
2299 I915_WRITE(WM2_LP_ILK
, previous
->wm_lp
[1]);
2302 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] & WM1_LP_SR_EN
) {
2303 previous
->wm_lp
[0] &= ~WM1_LP_SR_EN
;
2304 I915_WRITE(WM1_LP_ILK
, previous
->wm_lp
[0]);
2309 * Don't touch WM1S_LP_EN here.
2310 * Doing so could cause underruns.
2317 * The spec says we shouldn't write when we don't need, because every write
2318 * causes WMs to be re-evaluated, expending some power.
2320 static void ilk_write_wm_values(struct drm_i915_private
*dev_priv
,
2321 struct ilk_wm_values
*results
)
2323 struct drm_device
*dev
= dev_priv
->dev
;
2324 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2328 dirty
= ilk_compute_wm_dirty(dev_priv
, previous
, results
);
2332 _ilk_disable_lp_wm(dev_priv
, dirty
);
2334 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
2335 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
2336 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
2337 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
2338 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
2339 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
2341 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
2342 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
2343 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
2344 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
2345 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
2346 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
2348 if (dirty
& WM_DIRTY_DDB
) {
2349 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2350 val
= I915_READ(WM_MISC
);
2351 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2352 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
2354 val
|= WM_MISC_DATA_PARTITION_5_6
;
2355 I915_WRITE(WM_MISC
, val
);
2357 val
= I915_READ(DISP_ARB_CTL2
);
2358 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2359 val
&= ~DISP_DATA_PARTITION_5_6
;
2361 val
|= DISP_DATA_PARTITION_5_6
;
2362 I915_WRITE(DISP_ARB_CTL2
, val
);
2366 if (dirty
& WM_DIRTY_FBC
) {
2367 val
= I915_READ(DISP_ARB_CTL
);
2368 if (results
->enable_fbc_wm
)
2369 val
&= ~DISP_FBC_WM_DIS
;
2371 val
|= DISP_FBC_WM_DIS
;
2372 I915_WRITE(DISP_ARB_CTL
, val
);
2375 if (dirty
& WM_DIRTY_LP(1) &&
2376 previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
2377 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
2379 if (INTEL_INFO(dev
)->gen
>= 7) {
2380 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
2381 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
2382 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
2383 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
2386 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != results
->wm_lp
[0])
2387 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
2388 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != results
->wm_lp
[1])
2389 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
2390 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != results
->wm_lp
[2])
2391 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
2393 dev_priv
->wm
.hw
= *results
;
2396 static bool ilk_disable_lp_wm(struct drm_device
*dev
)
2398 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2400 return _ilk_disable_lp_wm(dev_priv
, WM_DIRTY_LP_ALL
);
2404 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2405 * different active planes.
2408 #define SKL_DDB_SIZE 896 /* in blocks */
2411 skl_ddb_get_pipe_allocation_limits(struct drm_device
*dev
,
2412 struct drm_crtc
*for_crtc
,
2413 const struct intel_wm_config
*config
,
2414 const struct skl_pipe_wm_parameters
*params
,
2415 struct skl_ddb_entry
*alloc
/* out */)
2417 struct drm_crtc
*crtc
;
2418 unsigned int pipe_size
, ddb_size
;
2419 int nth_active_pipe
;
2421 if (!params
->active
) {
2427 ddb_size
= SKL_DDB_SIZE
;
2429 ddb_size
-= 4; /* 4 blocks for bypass path allocation */
2431 nth_active_pipe
= 0;
2432 for_each_crtc(dev
, crtc
) {
2433 if (!intel_crtc_active(crtc
))
2436 if (crtc
== for_crtc
)
2442 pipe_size
= ddb_size
/ config
->num_pipes_active
;
2443 alloc
->start
= nth_active_pipe
* ddb_size
/ config
->num_pipes_active
;
2444 alloc
->end
= alloc
->start
+ pipe_size
;
2447 static unsigned int skl_cursor_allocation(const struct intel_wm_config
*config
)
2449 if (config
->num_pipes_active
== 1)
2455 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry
*entry
, u32 reg
)
2457 entry
->start
= reg
& 0x3ff;
2458 entry
->end
= (reg
>> 16) & 0x3ff;
2463 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
2464 struct skl_ddb_allocation
*ddb
/* out */)
2466 struct drm_device
*dev
= dev_priv
->dev
;
2471 for_each_pipe(dev_priv
, pipe
) {
2472 for_each_plane(pipe
, plane
) {
2473 val
= I915_READ(PLANE_BUF_CFG(pipe
, plane
));
2474 skl_ddb_entry_init_from_hw(&ddb
->plane
[pipe
][plane
],
2478 val
= I915_READ(CUR_BUF_CFG(pipe
));
2479 skl_ddb_entry_init_from_hw(&ddb
->cursor
[pipe
], val
);
2484 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters
*p
)
2486 return p
->horiz_pixels
* p
->vert_pixels
* p
->bytes_per_pixel
;
2490 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2491 * a 8192x4096@32bpp framebuffer:
2492 * 3 * 4096 * 8192 * 4 < 2^32
2495 skl_get_total_relative_data_rate(struct intel_crtc
*intel_crtc
,
2496 const struct skl_pipe_wm_parameters
*params
)
2498 unsigned int total_data_rate
= 0;
2501 for (plane
= 0; plane
< intel_num_planes(intel_crtc
); plane
++) {
2502 const struct intel_plane_wm_parameters
*p
;
2504 p
= ¶ms
->plane
[plane
];
2508 total_data_rate
+= skl_plane_relative_data_rate(p
);
2511 return total_data_rate
;
2515 skl_allocate_pipe_ddb(struct drm_crtc
*crtc
,
2516 const struct intel_wm_config
*config
,
2517 const struct skl_pipe_wm_parameters
*params
,
2518 struct skl_ddb_allocation
*ddb
/* out */)
2520 struct drm_device
*dev
= crtc
->dev
;
2521 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2522 enum pipe pipe
= intel_crtc
->pipe
;
2523 struct skl_ddb_entry
*alloc
= &ddb
->pipe
[pipe
];
2524 uint16_t alloc_size
, start
, cursor_blocks
;
2525 uint16_t minimum
[I915_MAX_PLANES
];
2526 unsigned int total_data_rate
;
2529 skl_ddb_get_pipe_allocation_limits(dev
, crtc
, config
, params
, alloc
);
2530 alloc_size
= skl_ddb_entry_size(alloc
);
2531 if (alloc_size
== 0) {
2532 memset(ddb
->plane
[pipe
], 0, sizeof(ddb
->plane
[pipe
]));
2533 memset(&ddb
->cursor
[pipe
], 0, sizeof(ddb
->cursor
[pipe
]));
2537 cursor_blocks
= skl_cursor_allocation(config
);
2538 ddb
->cursor
[pipe
].start
= alloc
->end
- cursor_blocks
;
2539 ddb
->cursor
[pipe
].end
= alloc
->end
;
2541 alloc_size
-= cursor_blocks
;
2542 alloc
->end
-= cursor_blocks
;
2544 /* 1. Allocate the mininum required blocks for each active plane */
2545 for_each_plane(pipe
, plane
) {
2546 const struct intel_plane_wm_parameters
*p
;
2548 p
= ¶ms
->plane
[plane
];
2553 alloc_size
-= minimum
[plane
];
2557 * 2. Distribute the remaining space in proportion to the amount of
2558 * data each plane needs to fetch from memory.
2560 * FIXME: we may not allocate every single block here.
2562 total_data_rate
= skl_get_total_relative_data_rate(intel_crtc
, params
);
2564 start
= alloc
->start
;
2565 for (plane
= 0; plane
< intel_num_planes(intel_crtc
); plane
++) {
2566 const struct intel_plane_wm_parameters
*p
;
2567 unsigned int data_rate
;
2568 uint16_t plane_blocks
;
2570 p
= ¶ms
->plane
[plane
];
2574 data_rate
= skl_plane_relative_data_rate(p
);
2577 * promote the expression to 64 bits to avoid overflowing, the
2578 * result is < available as data_rate / total_data_rate < 1
2580 plane_blocks
= minimum
[plane
];
2581 plane_blocks
+= div_u64((uint64_t)alloc_size
* data_rate
,
2584 ddb
->plane
[pipe
][plane
].start
= start
;
2585 ddb
->plane
[pipe
][plane
].end
= start
+ plane_blocks
;
2587 start
+= plane_blocks
;
2592 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state
*config
)
2594 /* TODO: Take into account the scalers once we support them */
2595 return config
->base
.adjusted_mode
.crtc_clock
;
2599 * The max latency should be 257 (max the punit can code is 255 and we add 2us
2600 * for the read latency) and bytes_per_pixel should always be <= 8, so that
2601 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
2602 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
2604 static uint32_t skl_wm_method1(uint32_t pixel_rate
, uint8_t bytes_per_pixel
,
2607 uint32_t wm_intermediate_val
, ret
;
2612 wm_intermediate_val
= latency
* pixel_rate
* bytes_per_pixel
/ 512;
2613 ret
= DIV_ROUND_UP(wm_intermediate_val
, 1000);
2618 static uint32_t skl_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
2619 uint32_t horiz_pixels
, uint8_t bytes_per_pixel
,
2620 uint64_t tiling
, uint32_t latency
)
2623 uint32_t plane_bytes_per_line
, plane_blocks_per_line
;
2624 uint32_t wm_intermediate_val
;
2629 plane_bytes_per_line
= horiz_pixels
* bytes_per_pixel
;
2631 if (tiling
== I915_FORMAT_MOD_Y_TILED
||
2632 tiling
== I915_FORMAT_MOD_Yf_TILED
) {
2633 plane_bytes_per_line
*= 4;
2634 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
2635 plane_blocks_per_line
/= 4;
2637 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
2640 wm_intermediate_val
= latency
* pixel_rate
;
2641 ret
= DIV_ROUND_UP(wm_intermediate_val
, pipe_htotal
* 1000) *
2642 plane_blocks_per_line
;
2647 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation
*new_ddb
,
2648 const struct intel_crtc
*intel_crtc
)
2650 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2652 const struct skl_ddb_allocation
*cur_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
2653 enum pipe pipe
= intel_crtc
->pipe
;
2655 if (memcmp(new_ddb
->plane
[pipe
], cur_ddb
->plane
[pipe
],
2656 sizeof(new_ddb
->plane
[pipe
])))
2659 if (memcmp(&new_ddb
->cursor
[pipe
], &cur_ddb
->cursor
[pipe
],
2660 sizeof(new_ddb
->cursor
[pipe
])))
2666 static void skl_compute_wm_global_parameters(struct drm_device
*dev
,
2667 struct intel_wm_config
*config
)
2669 struct drm_crtc
*crtc
;
2670 struct drm_plane
*plane
;
2672 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
2673 config
->num_pipes_active
+= intel_crtc_active(crtc
);
2675 /* FIXME: I don't think we need those two global parameters on SKL */
2676 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
2677 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2679 config
->sprites_enabled
|= intel_plane
->wm
.enabled
;
2680 config
->sprites_scaled
|= intel_plane
->wm
.scaled
;
2684 static void skl_compute_wm_pipe_parameters(struct drm_crtc
*crtc
,
2685 struct skl_pipe_wm_parameters
*p
)
2687 struct drm_device
*dev
= crtc
->dev
;
2688 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2689 enum pipe pipe
= intel_crtc
->pipe
;
2690 struct drm_plane
*plane
;
2691 struct drm_framebuffer
*fb
;
2692 int i
= 1; /* Index for sprite planes start */
2694 p
->active
= intel_crtc_active(crtc
);
2696 p
->pipe_htotal
= intel_crtc
->config
->base
.adjusted_mode
.crtc_htotal
;
2697 p
->pixel_rate
= skl_pipe_pixel_rate(intel_crtc
->config
);
2700 * For now, assume primary and cursor planes are always enabled.
2702 p
->plane
[0].enabled
= true;
2703 p
->plane
[0].bytes_per_pixel
=
2704 crtc
->primary
->fb
->bits_per_pixel
/ 8;
2705 p
->plane
[0].horiz_pixels
= intel_crtc
->config
->pipe_src_w
;
2706 p
->plane
[0].vert_pixels
= intel_crtc
->config
->pipe_src_h
;
2707 p
->plane
[0].tiling
= DRM_FORMAT_MOD_NONE
;
2708 fb
= crtc
->primary
->state
->fb
;
2710 * Framebuffer can be NULL on plane disable, but it does not
2711 * matter for watermarks if we assume no tiling in that case.
2714 p
->plane
[0].tiling
= fb
->modifier
[0];
2716 p
->cursor
.enabled
= true;
2717 p
->cursor
.bytes_per_pixel
= 4;
2718 p
->cursor
.horiz_pixels
= intel_crtc
->cursor_width
?
2719 intel_crtc
->cursor_width
: 64;
2722 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
2723 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2725 if (intel_plane
->pipe
== pipe
&&
2726 plane
->type
== DRM_PLANE_TYPE_OVERLAY
)
2727 p
->plane
[i
++] = intel_plane
->wm
;
2731 static bool skl_compute_plane_wm(const struct drm_i915_private
*dev_priv
,
2732 struct skl_pipe_wm_parameters
*p
,
2733 struct intel_plane_wm_parameters
*p_params
,
2734 uint16_t ddb_allocation
,
2736 uint16_t *out_blocks
, /* out */
2737 uint8_t *out_lines
/* out */)
2739 uint32_t latency
= dev_priv
->wm
.skl_latency
[level
];
2740 uint32_t method1
, method2
;
2741 uint32_t plane_bytes_per_line
, plane_blocks_per_line
;
2742 uint32_t res_blocks
, res_lines
;
2743 uint32_t selected_result
;
2745 if (latency
== 0 || !p
->active
|| !p_params
->enabled
)
2748 method1
= skl_wm_method1(p
->pixel_rate
,
2749 p_params
->bytes_per_pixel
,
2751 method2
= skl_wm_method2(p
->pixel_rate
,
2753 p_params
->horiz_pixels
,
2754 p_params
->bytes_per_pixel
,
2758 plane_bytes_per_line
= p_params
->horiz_pixels
*
2759 p_params
->bytes_per_pixel
;
2760 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
2762 if (p_params
->tiling
== I915_FORMAT_MOD_Y_TILED
||
2763 p_params
->tiling
== I915_FORMAT_MOD_Yf_TILED
) {
2764 uint32_t y_tile_minimum
= plane_blocks_per_line
* 4;
2765 selected_result
= max(method2
, y_tile_minimum
);
2767 if ((ddb_allocation
/ plane_blocks_per_line
) >= 1)
2768 selected_result
= min(method1
, method2
);
2770 selected_result
= method1
;
2773 res_blocks
= selected_result
+ 1;
2774 res_lines
= DIV_ROUND_UP(selected_result
, plane_blocks_per_line
);
2776 if (level
>= 1 && level
<= 7) {
2777 if (p_params
->tiling
== I915_FORMAT_MOD_Y_TILED
||
2778 p_params
->tiling
== I915_FORMAT_MOD_Yf_TILED
)
2784 if (res_blocks
>= ddb_allocation
|| res_lines
> 31)
2787 *out_blocks
= res_blocks
;
2788 *out_lines
= res_lines
;
2793 static void skl_compute_wm_level(const struct drm_i915_private
*dev_priv
,
2794 struct skl_ddb_allocation
*ddb
,
2795 struct skl_pipe_wm_parameters
*p
,
2799 struct skl_wm_level
*result
)
2801 uint16_t ddb_blocks
;
2804 for (i
= 0; i
< num_planes
; i
++) {
2805 ddb_blocks
= skl_ddb_entry_size(&ddb
->plane
[pipe
][i
]);
2807 result
->plane_en
[i
] = skl_compute_plane_wm(dev_priv
,
2811 &result
->plane_res_b
[i
],
2812 &result
->plane_res_l
[i
]);
2815 ddb_blocks
= skl_ddb_entry_size(&ddb
->cursor
[pipe
]);
2816 result
->cursor_en
= skl_compute_plane_wm(dev_priv
, p
, &p
->cursor
,
2818 &result
->cursor_res_b
,
2819 &result
->cursor_res_l
);
2823 skl_compute_linetime_wm(struct drm_crtc
*crtc
, struct skl_pipe_wm_parameters
*p
)
2825 if (!intel_crtc_active(crtc
))
2828 return DIV_ROUND_UP(8 * p
->pipe_htotal
* 1000, p
->pixel_rate
);
2832 static void skl_compute_transition_wm(struct drm_crtc
*crtc
,
2833 struct skl_pipe_wm_parameters
*params
,
2834 struct skl_wm_level
*trans_wm
/* out */)
2836 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2839 if (!params
->active
)
2842 /* Until we know more, just disable transition WMs */
2843 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++)
2844 trans_wm
->plane_en
[i
] = false;
2845 trans_wm
->cursor_en
= false;
2848 static void skl_compute_pipe_wm(struct drm_crtc
*crtc
,
2849 struct skl_ddb_allocation
*ddb
,
2850 struct skl_pipe_wm_parameters
*params
,
2851 struct skl_pipe_wm
*pipe_wm
)
2853 struct drm_device
*dev
= crtc
->dev
;
2854 const struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2855 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2856 int level
, max_level
= ilk_wm_max_level(dev
);
2858 for (level
= 0; level
<= max_level
; level
++) {
2859 skl_compute_wm_level(dev_priv
, ddb
, params
, intel_crtc
->pipe
,
2860 level
, intel_num_planes(intel_crtc
),
2861 &pipe_wm
->wm
[level
]);
2863 pipe_wm
->linetime
= skl_compute_linetime_wm(crtc
, params
);
2865 skl_compute_transition_wm(crtc
, params
, &pipe_wm
->trans_wm
);
2868 static void skl_compute_wm_results(struct drm_device
*dev
,
2869 struct skl_pipe_wm_parameters
*p
,
2870 struct skl_pipe_wm
*p_wm
,
2871 struct skl_wm_values
*r
,
2872 struct intel_crtc
*intel_crtc
)
2874 int level
, max_level
= ilk_wm_max_level(dev
);
2875 enum pipe pipe
= intel_crtc
->pipe
;
2879 for (level
= 0; level
<= max_level
; level
++) {
2880 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
2883 temp
|= p_wm
->wm
[level
].plane_res_l
[i
] <<
2884 PLANE_WM_LINES_SHIFT
;
2885 temp
|= p_wm
->wm
[level
].plane_res_b
[i
];
2886 if (p_wm
->wm
[level
].plane_en
[i
])
2887 temp
|= PLANE_WM_EN
;
2889 r
->plane
[pipe
][i
][level
] = temp
;
2894 temp
|= p_wm
->wm
[level
].cursor_res_l
<< PLANE_WM_LINES_SHIFT
;
2895 temp
|= p_wm
->wm
[level
].cursor_res_b
;
2897 if (p_wm
->wm
[level
].cursor_en
)
2898 temp
|= PLANE_WM_EN
;
2900 r
->cursor
[pipe
][level
] = temp
;
2904 /* transition WMs */
2905 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
2907 temp
|= p_wm
->trans_wm
.plane_res_l
[i
] << PLANE_WM_LINES_SHIFT
;
2908 temp
|= p_wm
->trans_wm
.plane_res_b
[i
];
2909 if (p_wm
->trans_wm
.plane_en
[i
])
2910 temp
|= PLANE_WM_EN
;
2912 r
->plane_trans
[pipe
][i
] = temp
;
2916 temp
|= p_wm
->trans_wm
.cursor_res_l
<< PLANE_WM_LINES_SHIFT
;
2917 temp
|= p_wm
->trans_wm
.cursor_res_b
;
2918 if (p_wm
->trans_wm
.cursor_en
)
2919 temp
|= PLANE_WM_EN
;
2921 r
->cursor_trans
[pipe
] = temp
;
2923 r
->wm_linetime
[pipe
] = p_wm
->linetime
;
2926 static void skl_ddb_entry_write(struct drm_i915_private
*dev_priv
, uint32_t reg
,
2927 const struct skl_ddb_entry
*entry
)
2930 I915_WRITE(reg
, (entry
->end
- 1) << 16 | entry
->start
);
2935 static void skl_write_wm_values(struct drm_i915_private
*dev_priv
,
2936 const struct skl_wm_values
*new)
2938 struct drm_device
*dev
= dev_priv
->dev
;
2939 struct intel_crtc
*crtc
;
2941 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
2942 int i
, level
, max_level
= ilk_wm_max_level(dev
);
2943 enum pipe pipe
= crtc
->pipe
;
2945 if (!new->dirty
[pipe
])
2948 I915_WRITE(PIPE_WM_LINETIME(pipe
), new->wm_linetime
[pipe
]);
2950 for (level
= 0; level
<= max_level
; level
++) {
2951 for (i
= 0; i
< intel_num_planes(crtc
); i
++)
2952 I915_WRITE(PLANE_WM(pipe
, i
, level
),
2953 new->plane
[pipe
][i
][level
]);
2954 I915_WRITE(CUR_WM(pipe
, level
),
2955 new->cursor
[pipe
][level
]);
2957 for (i
= 0; i
< intel_num_planes(crtc
); i
++)
2958 I915_WRITE(PLANE_WM_TRANS(pipe
, i
),
2959 new->plane_trans
[pipe
][i
]);
2960 I915_WRITE(CUR_WM_TRANS(pipe
), new->cursor_trans
[pipe
]);
2962 for (i
= 0; i
< intel_num_planes(crtc
); i
++)
2963 skl_ddb_entry_write(dev_priv
,
2964 PLANE_BUF_CFG(pipe
, i
),
2965 &new->ddb
.plane
[pipe
][i
]);
2967 skl_ddb_entry_write(dev_priv
, CUR_BUF_CFG(pipe
),
2968 &new->ddb
.cursor
[pipe
]);
2973 * When setting up a new DDB allocation arrangement, we need to correctly
2974 * sequence the times at which the new allocations for the pipes are taken into
2975 * account or we'll have pipes fetching from space previously allocated to
2978 * Roughly the sequence looks like:
2979 * 1. re-allocate the pipe(s) with the allocation being reduced and not
2980 * overlapping with a previous light-up pipe (another way to put it is:
2981 * pipes with their new allocation strickly included into their old ones).
2982 * 2. re-allocate the other pipes that get their allocation reduced
2983 * 3. allocate the pipes having their allocation increased
2985 * Steps 1. and 2. are here to take care of the following case:
2986 * - Initially DDB looks like this:
2989 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
2993 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
2997 skl_wm_flush_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int pass
)
2999 struct drm_device
*dev
= dev_priv
->dev
;
3002 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe
), pass
);
3004 for_each_plane(pipe
, plane
) {
3005 I915_WRITE(PLANE_SURF(pipe
, plane
),
3006 I915_READ(PLANE_SURF(pipe
, plane
)));
3008 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3012 skl_ddb_allocation_included(const struct skl_ddb_allocation
*old
,
3013 const struct skl_ddb_allocation
*new,
3016 uint16_t old_size
, new_size
;
3018 old_size
= skl_ddb_entry_size(&old
->pipe
[pipe
]);
3019 new_size
= skl_ddb_entry_size(&new->pipe
[pipe
]);
3021 return old_size
!= new_size
&&
3022 new->pipe
[pipe
].start
>= old
->pipe
[pipe
].start
&&
3023 new->pipe
[pipe
].end
<= old
->pipe
[pipe
].end
;
3026 static void skl_flush_wm_values(struct drm_i915_private
*dev_priv
,
3027 struct skl_wm_values
*new_values
)
3029 struct drm_device
*dev
= dev_priv
->dev
;
3030 struct skl_ddb_allocation
*cur_ddb
, *new_ddb
;
3031 bool reallocated
[I915_MAX_PIPES
] = {false, false, false};
3032 struct intel_crtc
*crtc
;
3035 new_ddb
= &new_values
->ddb
;
3036 cur_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3039 * First pass: flush the pipes with the new allocation contained into
3042 * We'll wait for the vblank on those pipes to ensure we can safely
3043 * re-allocate the freed space without this pipe fetching from it.
3045 for_each_intel_crtc(dev
, crtc
) {
3051 if (!skl_ddb_allocation_included(cur_ddb
, new_ddb
, pipe
))
3054 skl_wm_flush_pipe(dev_priv
, pipe
, 1);
3055 intel_wait_for_vblank(dev
, pipe
);
3057 reallocated
[pipe
] = true;
3062 * Second pass: flush the pipes that are having their allocation
3063 * reduced, but overlapping with a previous allocation.
3065 * Here as well we need to wait for the vblank to make sure the freed
3066 * space is not used anymore.
3068 for_each_intel_crtc(dev
, crtc
) {
3074 if (reallocated
[pipe
])
3077 if (skl_ddb_entry_size(&new_ddb
->pipe
[pipe
]) <
3078 skl_ddb_entry_size(&cur_ddb
->pipe
[pipe
])) {
3079 skl_wm_flush_pipe(dev_priv
, pipe
, 2);
3080 intel_wait_for_vblank(dev
, pipe
);
3081 reallocated
[pipe
] = true;
3086 * Third pass: flush the pipes that got more space allocated.
3088 * We don't need to actively wait for the update here, next vblank
3089 * will just get more DDB space with the correct WM values.
3091 for_each_intel_crtc(dev
, crtc
) {
3098 * At this point, only the pipes more space than before are
3099 * left to re-allocate.
3101 if (reallocated
[pipe
])
3104 skl_wm_flush_pipe(dev_priv
, pipe
, 3);
3108 static bool skl_update_pipe_wm(struct drm_crtc
*crtc
,
3109 struct skl_pipe_wm_parameters
*params
,
3110 struct intel_wm_config
*config
,
3111 struct skl_ddb_allocation
*ddb
, /* out */
3112 struct skl_pipe_wm
*pipe_wm
/* out */)
3114 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3116 skl_compute_wm_pipe_parameters(crtc
, params
);
3117 skl_allocate_pipe_ddb(crtc
, config
, params
, ddb
);
3118 skl_compute_pipe_wm(crtc
, ddb
, params
, pipe_wm
);
3120 if (!memcmp(&intel_crtc
->wm
.skl_active
, pipe_wm
, sizeof(*pipe_wm
)))
3123 intel_crtc
->wm
.skl_active
= *pipe_wm
;
3127 static void skl_update_other_pipe_wm(struct drm_device
*dev
,
3128 struct drm_crtc
*crtc
,
3129 struct intel_wm_config
*config
,
3130 struct skl_wm_values
*r
)
3132 struct intel_crtc
*intel_crtc
;
3133 struct intel_crtc
*this_crtc
= to_intel_crtc(crtc
);
3136 * If the WM update hasn't changed the allocation for this_crtc (the
3137 * crtc we are currently computing the new WM values for), other
3138 * enabled crtcs will keep the same allocation and we don't need to
3139 * recompute anything for them.
3141 if (!skl_ddb_allocation_changed(&r
->ddb
, this_crtc
))
3145 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3146 * other active pipes need new DDB allocation and WM values.
3148 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
3150 struct skl_pipe_wm_parameters params
= {};
3151 struct skl_pipe_wm pipe_wm
= {};
3154 if (this_crtc
->pipe
== intel_crtc
->pipe
)
3157 if (!intel_crtc
->active
)
3160 wm_changed
= skl_update_pipe_wm(&intel_crtc
->base
,
3165 * If we end up re-computing the other pipe WM values, it's
3166 * because it was really needed, so we expect the WM values to
3169 WARN_ON(!wm_changed
);
3171 skl_compute_wm_results(dev
, ¶ms
, &pipe_wm
, r
, intel_crtc
);
3172 r
->dirty
[intel_crtc
->pipe
] = true;
3176 static void skl_update_wm(struct drm_crtc
*crtc
)
3178 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3179 struct drm_device
*dev
= crtc
->dev
;
3180 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3181 struct skl_pipe_wm_parameters params
= {};
3182 struct skl_wm_values
*results
= &dev_priv
->wm
.skl_results
;
3183 struct skl_pipe_wm pipe_wm
= {};
3184 struct intel_wm_config config
= {};
3186 memset(results
, 0, sizeof(*results
));
3188 skl_compute_wm_global_parameters(dev
, &config
);
3190 if (!skl_update_pipe_wm(crtc
, ¶ms
, &config
,
3191 &results
->ddb
, &pipe_wm
))
3194 skl_compute_wm_results(dev
, ¶ms
, &pipe_wm
, results
, intel_crtc
);
3195 results
->dirty
[intel_crtc
->pipe
] = true;
3197 skl_update_other_pipe_wm(dev
, crtc
, &config
, results
);
3198 skl_write_wm_values(dev_priv
, results
);
3199 skl_flush_wm_values(dev_priv
, results
);
3201 /* store the new configuration */
3202 dev_priv
->wm
.skl_hw
= *results
;
3206 skl_update_sprite_wm(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
3207 uint32_t sprite_width
, uint32_t sprite_height
,
3208 int pixel_size
, bool enabled
, bool scaled
)
3210 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
3211 struct drm_framebuffer
*fb
= plane
->state
->fb
;
3213 intel_plane
->wm
.enabled
= enabled
;
3214 intel_plane
->wm
.scaled
= scaled
;
3215 intel_plane
->wm
.horiz_pixels
= sprite_width
;
3216 intel_plane
->wm
.vert_pixels
= sprite_height
;
3217 intel_plane
->wm
.bytes_per_pixel
= pixel_size
;
3218 intel_plane
->wm
.tiling
= DRM_FORMAT_MOD_NONE
;
3220 * Framebuffer can be NULL on plane disable, but it does not
3221 * matter for watermarks if we assume no tiling in that case.
3224 intel_plane
->wm
.tiling
= fb
->modifier
[0];
3226 skl_update_wm(crtc
);
3229 static void ilk_update_wm(struct drm_crtc
*crtc
)
3231 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3232 struct drm_device
*dev
= crtc
->dev
;
3233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3234 struct ilk_wm_maximums max
;
3235 struct ilk_pipe_wm_parameters params
= {};
3236 struct ilk_wm_values results
= {};
3237 enum intel_ddb_partitioning partitioning
;
3238 struct intel_pipe_wm pipe_wm
= {};
3239 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
3240 struct intel_wm_config config
= {};
3242 ilk_compute_wm_parameters(crtc
, ¶ms
);
3244 intel_compute_pipe_wm(crtc
, ¶ms
, &pipe_wm
);
3246 if (!memcmp(&intel_crtc
->wm
.active
, &pipe_wm
, sizeof(pipe_wm
)))
3249 intel_crtc
->wm
.active
= pipe_wm
;
3251 ilk_compute_wm_config(dev
, &config
);
3253 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_1_2
, &max
);
3254 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_1_2
);
3256 /* 5/6 split only in single pipe config on IVB+ */
3257 if (INTEL_INFO(dev
)->gen
>= 7 &&
3258 config
.num_pipes_active
== 1 && config
.sprites_enabled
) {
3259 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_5_6
, &max
);
3260 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_5_6
);
3262 best_lp_wm
= ilk_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
3264 best_lp_wm
= &lp_wm_1_2
;
3267 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
3268 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
3270 ilk_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
3272 ilk_write_wm_values(dev_priv
, &results
);
3276 ilk_update_sprite_wm(struct drm_plane
*plane
,
3277 struct drm_crtc
*crtc
,
3278 uint32_t sprite_width
, uint32_t sprite_height
,
3279 int pixel_size
, bool enabled
, bool scaled
)
3281 struct drm_device
*dev
= plane
->dev
;
3282 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
3284 intel_plane
->wm
.enabled
= enabled
;
3285 intel_plane
->wm
.scaled
= scaled
;
3286 intel_plane
->wm
.horiz_pixels
= sprite_width
;
3287 intel_plane
->wm
.vert_pixels
= sprite_width
;
3288 intel_plane
->wm
.bytes_per_pixel
= pixel_size
;
3291 * IVB workaround: must disable low power watermarks for at least
3292 * one frame before enabling scaling. LP watermarks can be re-enabled
3293 * when scaling is disabled.
3295 * WaCxSRDisabledForSpriteScaling:ivb
3297 if (IS_IVYBRIDGE(dev
) && scaled
&& ilk_disable_lp_wm(dev
))
3298 intel_wait_for_vblank(dev
, intel_plane
->pipe
);
3300 ilk_update_wm(crtc
);
3303 static void skl_pipe_wm_active_state(uint32_t val
,
3304 struct skl_pipe_wm
*active
,
3310 bool is_enabled
= (val
& PLANE_WM_EN
) != 0;
3314 active
->wm
[level
].plane_en
[i
] = is_enabled
;
3315 active
->wm
[level
].plane_res_b
[i
] =
3316 val
& PLANE_WM_BLOCKS_MASK
;
3317 active
->wm
[level
].plane_res_l
[i
] =
3318 (val
>> PLANE_WM_LINES_SHIFT
) &
3319 PLANE_WM_LINES_MASK
;
3321 active
->wm
[level
].cursor_en
= is_enabled
;
3322 active
->wm
[level
].cursor_res_b
=
3323 val
& PLANE_WM_BLOCKS_MASK
;
3324 active
->wm
[level
].cursor_res_l
=
3325 (val
>> PLANE_WM_LINES_SHIFT
) &
3326 PLANE_WM_LINES_MASK
;
3330 active
->trans_wm
.plane_en
[i
] = is_enabled
;
3331 active
->trans_wm
.plane_res_b
[i
] =
3332 val
& PLANE_WM_BLOCKS_MASK
;
3333 active
->trans_wm
.plane_res_l
[i
] =
3334 (val
>> PLANE_WM_LINES_SHIFT
) &
3335 PLANE_WM_LINES_MASK
;
3337 active
->trans_wm
.cursor_en
= is_enabled
;
3338 active
->trans_wm
.cursor_res_b
=
3339 val
& PLANE_WM_BLOCKS_MASK
;
3340 active
->trans_wm
.cursor_res_l
=
3341 (val
>> PLANE_WM_LINES_SHIFT
) &
3342 PLANE_WM_LINES_MASK
;
3347 static void skl_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
3349 struct drm_device
*dev
= crtc
->dev
;
3350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3351 struct skl_wm_values
*hw
= &dev_priv
->wm
.skl_hw
;
3352 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3353 struct skl_pipe_wm
*active
= &intel_crtc
->wm
.skl_active
;
3354 enum pipe pipe
= intel_crtc
->pipe
;
3355 int level
, i
, max_level
;
3358 max_level
= ilk_wm_max_level(dev
);
3360 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
3362 for (level
= 0; level
<= max_level
; level
++) {
3363 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++)
3364 hw
->plane
[pipe
][i
][level
] =
3365 I915_READ(PLANE_WM(pipe
, i
, level
));
3366 hw
->cursor
[pipe
][level
] = I915_READ(CUR_WM(pipe
, level
));
3369 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++)
3370 hw
->plane_trans
[pipe
][i
] = I915_READ(PLANE_WM_TRANS(pipe
, i
));
3371 hw
->cursor_trans
[pipe
] = I915_READ(CUR_WM_TRANS(pipe
));
3373 if (!intel_crtc_active(crtc
))
3376 hw
->dirty
[pipe
] = true;
3378 active
->linetime
= hw
->wm_linetime
[pipe
];
3380 for (level
= 0; level
<= max_level
; level
++) {
3381 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3382 temp
= hw
->plane
[pipe
][i
][level
];
3383 skl_pipe_wm_active_state(temp
, active
, false,
3386 temp
= hw
->cursor
[pipe
][level
];
3387 skl_pipe_wm_active_state(temp
, active
, false, true, i
, level
);
3390 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3391 temp
= hw
->plane_trans
[pipe
][i
];
3392 skl_pipe_wm_active_state(temp
, active
, true, false, i
, 0);
3395 temp
= hw
->cursor_trans
[pipe
];
3396 skl_pipe_wm_active_state(temp
, active
, true, true, i
, 0);
3399 void skl_wm_get_hw_state(struct drm_device
*dev
)
3401 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3402 struct skl_ddb_allocation
*ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3403 struct drm_crtc
*crtc
;
3405 skl_ddb_get_hw_state(dev_priv
, ddb
);
3406 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
3407 skl_pipe_wm_get_hw_state(crtc
);
3410 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
3412 struct drm_device
*dev
= crtc
->dev
;
3413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3414 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
3415 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3416 struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
;
3417 enum pipe pipe
= intel_crtc
->pipe
;
3418 static const unsigned int wm0_pipe_reg
[] = {
3419 [PIPE_A
] = WM0_PIPEA_ILK
,
3420 [PIPE_B
] = WM0_PIPEB_ILK
,
3421 [PIPE_C
] = WM0_PIPEC_IVB
,
3424 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
3425 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
3426 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
3428 active
->pipe_enabled
= intel_crtc_active(crtc
);
3430 if (active
->pipe_enabled
) {
3431 u32 tmp
= hw
->wm_pipe
[pipe
];
3434 * For active pipes LP0 watermark is marked as
3435 * enabled, and LP1+ watermaks as disabled since
3436 * we can't really reverse compute them in case
3437 * multiple pipes are active.
3439 active
->wm
[0].enable
= true;
3440 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
3441 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
3442 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
3443 active
->linetime
= hw
->wm_linetime
[pipe
];
3445 int level
, max_level
= ilk_wm_max_level(dev
);
3448 * For inactive pipes, all watermark levels
3449 * should be marked as enabled but zeroed,
3450 * which is what we'd compute them to.
3452 for (level
= 0; level
<= max_level
; level
++)
3453 active
->wm
[level
].enable
= true;
3457 void ilk_wm_get_hw_state(struct drm_device
*dev
)
3459 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3460 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
3461 struct drm_crtc
*crtc
;
3463 for_each_crtc(dev
, crtc
)
3464 ilk_pipe_wm_get_hw_state(crtc
);
3466 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
3467 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
3468 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
3470 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
3471 if (INTEL_INFO(dev
)->gen
>= 7) {
3472 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
3473 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
3476 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
3477 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
3478 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
3479 else if (IS_IVYBRIDGE(dev
))
3480 hw
->partitioning
= (I915_READ(DISP_ARB_CTL2
) & DISP_DATA_PARTITION_5_6
) ?
3481 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
3484 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
3488 * intel_update_watermarks - update FIFO watermark values based on current modes
3490 * Calculate watermark values for the various WM regs based on current mode
3491 * and plane configuration.
3493 * There are several cases to deal with here:
3494 * - normal (i.e. non-self-refresh)
3495 * - self-refresh (SR) mode
3496 * - lines are large relative to FIFO size (buffer can hold up to 2)
3497 * - lines are small relative to FIFO size (buffer can hold more than 2
3498 * lines), so need to account for TLB latency
3500 * The normal calculation is:
3501 * watermark = dotclock * bytes per pixel * latency
3502 * where latency is platform & configuration dependent (we assume pessimal
3505 * The SR calculation is:
3506 * watermark = (trunc(latency/line time)+1) * surface width *
3509 * line time = htotal / dotclock
3510 * surface width = hdisplay for normal plane and 64 for cursor
3511 * and latency is assumed to be high, as above.
3513 * The final value programmed to the register should always be rounded up,
3514 * and include an extra 2 entries to account for clock crossings.
3516 * We don't use the sprite, so we can ignore that. And on Crestline we have
3517 * to set the non-SR watermarks to 8.
3519 void intel_update_watermarks(struct drm_crtc
*crtc
)
3521 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
3523 if (dev_priv
->display
.update_wm
)
3524 dev_priv
->display
.update_wm(crtc
);
3527 void intel_update_sprite_watermarks(struct drm_plane
*plane
,
3528 struct drm_crtc
*crtc
,
3529 uint32_t sprite_width
,
3530 uint32_t sprite_height
,
3532 bool enabled
, bool scaled
)
3534 struct drm_i915_private
*dev_priv
= plane
->dev
->dev_private
;
3536 if (dev_priv
->display
.update_sprite_wm
)
3537 dev_priv
->display
.update_sprite_wm(plane
, crtc
,
3538 sprite_width
, sprite_height
,
3539 pixel_size
, enabled
, scaled
);
3542 static struct drm_i915_gem_object
*
3543 intel_alloc_context_page(struct drm_device
*dev
)
3545 struct drm_i915_gem_object
*ctx
;
3548 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
3550 ctx
= i915_gem_alloc_object(dev
, 4096);
3552 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3556 ret
= i915_gem_obj_ggtt_pin(ctx
, 4096, 0);
3558 DRM_ERROR("failed to pin power context: %d\n", ret
);
3562 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
3564 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
3571 i915_gem_object_ggtt_unpin(ctx
);
3573 drm_gem_object_unreference(&ctx
->base
);
3578 * Lock protecting IPS related data structures
3580 DEFINE_SPINLOCK(mchdev_lock
);
3582 /* Global for IPS driver to get at the current i915 device. Protected by
3584 static struct drm_i915_private
*i915_mch_dev
;
3586 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
3588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3591 assert_spin_locked(&mchdev_lock
);
3593 rgvswctl
= I915_READ16(MEMSWCTL
);
3594 if (rgvswctl
& MEMCTL_CMD_STS
) {
3595 DRM_DEBUG("gpu busy, RCS change rejected\n");
3596 return false; /* still busy with another command */
3599 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
3600 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
3601 I915_WRITE16(MEMSWCTL
, rgvswctl
);
3602 POSTING_READ16(MEMSWCTL
);
3604 rgvswctl
|= MEMCTL_CMD_STS
;
3605 I915_WRITE16(MEMSWCTL
, rgvswctl
);
3610 static void ironlake_enable_drps(struct drm_device
*dev
)
3612 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3613 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
3614 u8 fmax
, fmin
, fstart
, vstart
;
3616 spin_lock_irq(&mchdev_lock
);
3618 /* Enable temp reporting */
3619 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
3620 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
3622 /* 100ms RC evaluation intervals */
3623 I915_WRITE(RCUPEI
, 100000);
3624 I915_WRITE(RCDNEI
, 100000);
3626 /* Set max/min thresholds to 90ms and 80ms respectively */
3627 I915_WRITE(RCBMAXAVG
, 90000);
3628 I915_WRITE(RCBMINAVG
, 80000);
3630 I915_WRITE(MEMIHYST
, 1);
3632 /* Set up min, max, and cur for interrupt handling */
3633 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
3634 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
3635 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
3636 MEMMODE_FSTART_SHIFT
;
3638 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
3641 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
3642 dev_priv
->ips
.fstart
= fstart
;
3644 dev_priv
->ips
.max_delay
= fstart
;
3645 dev_priv
->ips
.min_delay
= fmin
;
3646 dev_priv
->ips
.cur_delay
= fstart
;
3648 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3649 fmax
, fmin
, fstart
);
3651 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
3654 * Interrupts will be enabled in ironlake_irq_postinstall
3657 I915_WRITE(VIDSTART
, vstart
);
3658 POSTING_READ(VIDSTART
);
3660 rgvmodectl
|= MEMMODE_SWMODE_EN
;
3661 I915_WRITE(MEMMODECTL
, rgvmodectl
);
3663 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
3664 DRM_ERROR("stuck trying to change perf mode\n");
3667 ironlake_set_drps(dev
, fstart
);
3669 dev_priv
->ips
.last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
3671 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
3672 dev_priv
->ips
.last_count2
= I915_READ(0x112f4);
3673 dev_priv
->ips
.last_time2
= ktime_get_raw_ns();
3675 spin_unlock_irq(&mchdev_lock
);
3678 static void ironlake_disable_drps(struct drm_device
*dev
)
3680 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3683 spin_lock_irq(&mchdev_lock
);
3685 rgvswctl
= I915_READ16(MEMSWCTL
);
3687 /* Ack interrupts, disable EFC interrupt */
3688 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
3689 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
3690 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
3691 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
3692 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
3694 /* Go back to the starting frequency */
3695 ironlake_set_drps(dev
, dev_priv
->ips
.fstart
);
3697 rgvswctl
|= MEMCTL_CMD_STS
;
3698 I915_WRITE(MEMSWCTL
, rgvswctl
);
3701 spin_unlock_irq(&mchdev_lock
);
3704 /* There's a funny hw issue where the hw returns all 0 when reading from
3705 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3706 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3707 * all limits and the gpu stuck at whatever frequency it is at atm).
3709 static u32
gen6_rps_limits(struct drm_i915_private
*dev_priv
, u8 val
)
3713 /* Only set the down limit when we've reached the lowest level to avoid
3714 * getting more interrupts, otherwise leave this clear. This prevents a
3715 * race in the hw when coming out of rc6: There's a tiny window where
3716 * the hw runs at the minimal clock before selecting the desired
3717 * frequency, if the down threshold expires in that window we will not
3718 * receive a down interrupt. */
3719 limits
= dev_priv
->rps
.max_freq_softlimit
<< 24;
3720 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
3721 limits
|= dev_priv
->rps
.min_freq_softlimit
<< 16;
3726 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
3730 new_power
= dev_priv
->rps
.power
;
3731 switch (dev_priv
->rps
.power
) {
3733 if (val
> dev_priv
->rps
.efficient_freq
+ 1 && val
> dev_priv
->rps
.cur_freq
)
3734 new_power
= BETWEEN
;
3738 if (val
<= dev_priv
->rps
.efficient_freq
&& val
< dev_priv
->rps
.cur_freq
)
3739 new_power
= LOW_POWER
;
3740 else if (val
>= dev_priv
->rps
.rp0_freq
&& val
> dev_priv
->rps
.cur_freq
)
3741 new_power
= HIGH_POWER
;
3745 if (val
< (dev_priv
->rps
.rp1_freq
+ dev_priv
->rps
.rp0_freq
) >> 1 && val
< dev_priv
->rps
.cur_freq
)
3746 new_power
= BETWEEN
;
3749 /* Max/min bins are special */
3750 if (val
== dev_priv
->rps
.min_freq_softlimit
)
3751 new_power
= LOW_POWER
;
3752 if (val
== dev_priv
->rps
.max_freq_softlimit
)
3753 new_power
= HIGH_POWER
;
3754 if (new_power
== dev_priv
->rps
.power
)
3757 /* Note the units here are not exactly 1us, but 1280ns. */
3758 switch (new_power
) {
3760 /* Upclock if more than 95% busy over 16ms */
3761 I915_WRITE(GEN6_RP_UP_EI
, 12500);
3762 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 11800);
3764 /* Downclock if less than 85% busy over 32ms */
3765 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3766 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 21250);
3768 I915_WRITE(GEN6_RP_CONTROL
,
3769 GEN6_RP_MEDIA_TURBO
|
3770 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3771 GEN6_RP_MEDIA_IS_GFX
|
3773 GEN6_RP_UP_BUSY_AVG
|
3774 GEN6_RP_DOWN_IDLE_AVG
);
3778 /* Upclock if more than 90% busy over 13ms */
3779 I915_WRITE(GEN6_RP_UP_EI
, 10250);
3780 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 9225);
3782 /* Downclock if less than 75% busy over 32ms */
3783 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3784 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 18750);
3786 I915_WRITE(GEN6_RP_CONTROL
,
3787 GEN6_RP_MEDIA_TURBO
|
3788 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3789 GEN6_RP_MEDIA_IS_GFX
|
3791 GEN6_RP_UP_BUSY_AVG
|
3792 GEN6_RP_DOWN_IDLE_AVG
);
3796 /* Upclock if more than 85% busy over 10ms */
3797 I915_WRITE(GEN6_RP_UP_EI
, 8000);
3798 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 6800);
3800 /* Downclock if less than 60% busy over 32ms */
3801 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3802 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 15000);
3804 I915_WRITE(GEN6_RP_CONTROL
,
3805 GEN6_RP_MEDIA_TURBO
|
3806 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3807 GEN6_RP_MEDIA_IS_GFX
|
3809 GEN6_RP_UP_BUSY_AVG
|
3810 GEN6_RP_DOWN_IDLE_AVG
);
3814 dev_priv
->rps
.power
= new_power
;
3815 dev_priv
->rps
.last_adj
= 0;
3818 static u32
gen6_rps_pm_mask(struct drm_i915_private
*dev_priv
, u8 val
)
3822 if (val
> dev_priv
->rps
.min_freq_softlimit
)
3823 mask
|= GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT
;
3824 if (val
< dev_priv
->rps
.max_freq_softlimit
)
3825 mask
|= GEN6_PM_RP_UP_THRESHOLD
;
3827 mask
|= dev_priv
->pm_rps_events
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
);
3828 mask
&= dev_priv
->pm_rps_events
;
3830 return gen6_sanitize_rps_pm_mask(dev_priv
, ~mask
);
3833 /* gen6_set_rps is called to update the frequency request, but should also be
3834 * called when the range (min_delay and max_delay) is modified so that we can
3835 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3836 static void gen6_set_rps(struct drm_device
*dev
, u8 val
)
3838 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3840 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3841 WARN_ON(val
> dev_priv
->rps
.max_freq_softlimit
);
3842 WARN_ON(val
< dev_priv
->rps
.min_freq_softlimit
);
3844 /* min/max delay may still have been modified so be sure to
3845 * write the limits value.
3847 if (val
!= dev_priv
->rps
.cur_freq
) {
3848 gen6_set_rps_thresholds(dev_priv
, val
);
3850 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
3851 I915_WRITE(GEN6_RPNSWREQ
,
3852 HSW_FREQUENCY(val
));
3854 I915_WRITE(GEN6_RPNSWREQ
,
3855 GEN6_FREQUENCY(val
) |
3857 GEN6_AGGRESSIVE_TURBO
);
3860 /* Make sure we continue to get interrupts
3861 * until we hit the minimum or maximum frequencies.
3863 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, gen6_rps_limits(dev_priv
, val
));
3864 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
3866 POSTING_READ(GEN6_RPNSWREQ
);
3868 dev_priv
->rps
.cur_freq
= val
;
3869 trace_intel_gpu_freq_change(val
* 50);
3872 static void valleyview_set_rps(struct drm_device
*dev
, u8 val
)
3874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3876 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3877 WARN_ON(val
> dev_priv
->rps
.max_freq_softlimit
);
3878 WARN_ON(val
< dev_priv
->rps
.min_freq_softlimit
);
3880 if (WARN_ONCE(IS_CHERRYVIEW(dev
) && (val
& 1),
3881 "Odd GPU freq value\n"))
3884 if (val
!= dev_priv
->rps
.cur_freq
)
3885 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
3887 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
3889 dev_priv
->rps
.cur_freq
= val
;
3890 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
3893 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3895 * * If Gfx is Idle, then
3896 * 1. Mask Turbo interrupts
3897 * 2. Bring up Gfx clock
3898 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3899 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3900 * 5. Unmask Turbo interrupts
3902 static void vlv_set_rps_idle(struct drm_i915_private
*dev_priv
)
3904 struct drm_device
*dev
= dev_priv
->dev
;
3906 /* CHV and latest VLV don't need to force the gfx clock */
3907 if (IS_CHERRYVIEW(dev
) || dev
->pdev
->revision
>= 0xd) {
3908 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
3913 * When we are idle. Drop to min voltage state.
3916 if (dev_priv
->rps
.cur_freq
<= dev_priv
->rps
.min_freq_softlimit
)
3919 /* Mask turbo interrupt so that they will not come in between */
3920 I915_WRITE(GEN6_PMINTRMSK
,
3921 gen6_sanitize_rps_pm_mask(dev_priv
, ~0));
3923 vlv_force_gfx_clock(dev_priv
, true);
3925 dev_priv
->rps
.cur_freq
= dev_priv
->rps
.min_freq_softlimit
;
3927 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
,
3928 dev_priv
->rps
.min_freq_softlimit
);
3930 if (wait_for(((vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
))
3931 & GENFREQSTATUS
) == 0, 100))
3932 DRM_ERROR("timed out waiting for Punit\n");
3934 vlv_force_gfx_clock(dev_priv
, false);
3936 I915_WRITE(GEN6_PMINTRMSK
,
3937 gen6_rps_pm_mask(dev_priv
, dev_priv
->rps
.cur_freq
));
3940 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
3942 struct drm_device
*dev
= dev_priv
->dev
;
3944 mutex_lock(&dev_priv
->rps
.hw_lock
);
3945 if (dev_priv
->rps
.enabled
) {
3946 if (IS_VALLEYVIEW(dev
))
3947 vlv_set_rps_idle(dev_priv
);
3949 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
3950 dev_priv
->rps
.last_adj
= 0;
3952 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3955 void gen6_rps_boost(struct drm_i915_private
*dev_priv
)
3957 mutex_lock(&dev_priv
->rps
.hw_lock
);
3958 if (dev_priv
->rps
.enabled
) {
3959 intel_set_rps(dev_priv
->dev
, dev_priv
->rps
.max_freq_softlimit
);
3960 dev_priv
->rps
.last_adj
= 0;
3962 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3965 void intel_set_rps(struct drm_device
*dev
, u8 val
)
3967 if (IS_VALLEYVIEW(dev
))
3968 valleyview_set_rps(dev
, val
);
3970 gen6_set_rps(dev
, val
);
3973 static void gen9_disable_rps(struct drm_device
*dev
)
3975 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3977 I915_WRITE(GEN6_RC_CONTROL
, 0);
3978 I915_WRITE(GEN9_PG_ENABLE
, 0);
3981 static void gen6_disable_rps(struct drm_device
*dev
)
3983 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3985 I915_WRITE(GEN6_RC_CONTROL
, 0);
3986 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
3989 static void cherryview_disable_rps(struct drm_device
*dev
)
3991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3993 I915_WRITE(GEN6_RC_CONTROL
, 0);
3996 static void valleyview_disable_rps(struct drm_device
*dev
)
3998 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4000 /* we're doing forcewake before Disabling RC6,
4001 * This what the BIOS expects when going into suspend */
4002 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4004 I915_WRITE(GEN6_RC_CONTROL
, 0);
4006 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4009 static void intel_print_rc6_info(struct drm_device
*dev
, u32 mode
)
4011 if (IS_VALLEYVIEW(dev
)) {
4012 if (mode
& (GEN7_RC_CTL_TO_MODE
| GEN6_RC_CTL_EI_MODE(1)))
4013 mode
= GEN6_RC_CTL_RC6_ENABLE
;
4018 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4019 (mode
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off",
4020 (mode
& GEN6_RC_CTL_RC6p_ENABLE
) ? "on" : "off",
4021 (mode
& GEN6_RC_CTL_RC6pp_ENABLE
) ? "on" : "off");
4024 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4025 (mode
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off");
4028 static int sanitize_rc6_option(const struct drm_device
*dev
, int enable_rc6
)
4030 /* No RC6 before Ironlake */
4031 if (INTEL_INFO(dev
)->gen
< 5)
4034 /* RC6 is only on Ironlake mobile not on desktop */
4035 if (INTEL_INFO(dev
)->gen
== 5 && !IS_IRONLAKE_M(dev
))
4038 /* Respect the kernel parameter if it is set */
4039 if (enable_rc6
>= 0) {
4043 mask
= INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
|
4046 mask
= INTEL_RC6_ENABLE
;
4048 if ((enable_rc6
& mask
) != enable_rc6
)
4049 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4050 enable_rc6
& mask
, enable_rc6
, mask
);
4052 return enable_rc6
& mask
;
4055 /* Disable RC6 on Ironlake */
4056 if (INTEL_INFO(dev
)->gen
== 5)
4059 if (IS_IVYBRIDGE(dev
))
4060 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
4062 return INTEL_RC6_ENABLE
;
4065 int intel_enable_rc6(const struct drm_device
*dev
)
4067 return i915
.enable_rc6
;
4070 static void gen6_init_rps_frequencies(struct drm_device
*dev
)
4072 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4073 uint32_t rp_state_cap
;
4074 u32 ddcc_status
= 0;
4077 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
4078 /* All of these values are in units of 50MHz */
4079 dev_priv
->rps
.cur_freq
= 0;
4080 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4081 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 0) & 0xff;
4082 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
4083 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 16) & 0xff;
4084 /* hw_max = RP0 until we check for overclocking */
4085 dev_priv
->rps
.max_freq
= dev_priv
->rps
.rp0_freq
;
4087 dev_priv
->rps
.efficient_freq
= dev_priv
->rps
.rp1_freq
;
4088 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
4089 ret
= sandybridge_pcode_read(dev_priv
,
4090 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL
,
4093 dev_priv
->rps
.efficient_freq
=
4095 ((ddcc_status
>> 8) & 0xff),
4096 dev_priv
->rps
.min_freq
,
4097 dev_priv
->rps
.max_freq
);
4100 /* Preserve min/max settings in case of re-init */
4101 if (dev_priv
->rps
.max_freq_softlimit
== 0)
4102 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
4104 if (dev_priv
->rps
.min_freq_softlimit
== 0) {
4105 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4106 dev_priv
->rps
.min_freq_softlimit
=
4107 /* max(RPe, 450 MHz) */
4108 max(dev_priv
->rps
.efficient_freq
, (u8
) 9);
4110 dev_priv
->rps
.min_freq_softlimit
=
4111 dev_priv
->rps
.min_freq
;
4115 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4116 static void gen9_enable_rps(struct drm_device
*dev
)
4118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4120 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4122 gen6_init_rps_frequencies(dev
);
4124 I915_WRITE(GEN6_RPNSWREQ
, 0xc800000);
4125 I915_WRITE(GEN6_RC_VIDEO_FREQ
, 0xc800000);
4127 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 0xf4240);
4128 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, 0x12060000);
4129 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 0xe808);
4130 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 0x3bd08);
4131 I915_WRITE(GEN6_RP_UP_EI
, 0x101d0);
4132 I915_WRITE(GEN6_RP_DOWN_EI
, 0x55730);
4133 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 0xa);
4134 I915_WRITE(GEN6_PMINTRMSK
, 0x6);
4135 I915_WRITE(GEN6_RP_CONTROL
, GEN6_RP_MEDIA_TURBO
|
4136 GEN6_RP_MEDIA_HW_MODE
| GEN6_RP_MEDIA_IS_GFX
|
4137 GEN6_RP_ENABLE
| GEN6_RP_UP_BUSY_AVG
|
4138 GEN6_RP_DOWN_IDLE_AVG
);
4140 gen6_enable_rps_interrupts(dev
);
4142 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4145 static void gen9_enable_rc6(struct drm_device
*dev
)
4147 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4148 struct intel_engine_cs
*ring
;
4149 uint32_t rc6_mask
= 0;
4152 /* 1a: Software RC state - RC0 */
4153 I915_WRITE(GEN6_RC_STATE
, 0);
4155 /* 1b: Get forcewake during program sequence. Although the driver
4156 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4157 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4159 /* 2a: Disable RC states. */
4160 I915_WRITE(GEN6_RC_CONTROL
, 0);
4162 /* 2b: Program RC6 thresholds.*/
4163 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 54 << 16);
4164 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
4165 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
4166 for_each_ring(ring
, dev_priv
, unused
)
4167 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4168 I915_WRITE(GEN6_RC_SLEEP
, 0);
4169 I915_WRITE(GEN6_RC6_THRESHOLD
, 37500); /* 37.5/125ms per EI */
4171 /* 2c: Program Coarse Power Gating Policies. */
4172 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS
, 25);
4173 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS
, 25);
4175 /* 3a: Enable RC6 */
4176 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
4177 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
4178 DRM_INFO("RC6 %s\n", (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ?
4180 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
4181 GEN6_RC_CTL_EI_MODE(1) |
4184 /* 3b: Enable Coarse Power Gating only when RC6 is enabled */
4185 I915_WRITE(GEN9_PG_ENABLE
, (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ? 3 : 0);
4187 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4191 static void gen8_enable_rps(struct drm_device
*dev
)
4193 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4194 struct intel_engine_cs
*ring
;
4195 uint32_t rc6_mask
= 0;
4198 /* 1a: Software RC state - RC0 */
4199 I915_WRITE(GEN6_RC_STATE
, 0);
4201 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4202 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4203 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4205 /* 2a: Disable RC states. */
4206 I915_WRITE(GEN6_RC_CONTROL
, 0);
4208 /* Initialize rps frequencies */
4209 gen6_init_rps_frequencies(dev
);
4211 /* 2b: Program RC6 thresholds.*/
4212 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
4213 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
4214 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
4215 for_each_ring(ring
, dev_priv
, unused
)
4216 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4217 I915_WRITE(GEN6_RC_SLEEP
, 0);
4218 if (IS_BROADWELL(dev
))
4219 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us/1.28 for TO */
4221 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
4224 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
4225 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
4226 intel_print_rc6_info(dev
, rc6_mask
);
4227 if (IS_BROADWELL(dev
))
4228 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
4229 GEN7_RC_CTL_TO_MODE
|
4232 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
4233 GEN6_RC_CTL_EI_MODE(1) |
4236 /* 4 Program defaults and thresholds for RPS*/
4237 I915_WRITE(GEN6_RPNSWREQ
,
4238 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
4239 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
4240 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
4241 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4242 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 100000000 / 128); /* 1 second timeout */
4244 /* Docs recommend 900MHz, and 300 MHz respectively */
4245 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
4246 dev_priv
->rps
.max_freq_softlimit
<< 24 |
4247 dev_priv
->rps
.min_freq_softlimit
<< 16);
4249 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 7600000 / 128); /* 76ms busyness per EI, 90% */
4250 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4251 I915_WRITE(GEN6_RP_UP_EI
, 66000); /* 84.48ms, XXX: random? */
4252 I915_WRITE(GEN6_RP_DOWN_EI
, 350000); /* 448ms, XXX: random? */
4254 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4257 I915_WRITE(GEN6_RP_CONTROL
,
4258 GEN6_RP_MEDIA_TURBO
|
4259 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4260 GEN6_RP_MEDIA_IS_GFX
|
4262 GEN6_RP_UP_BUSY_AVG
|
4263 GEN6_RP_DOWN_IDLE_AVG
);
4265 /* 6: Ring frequency + overclocking (our driver does this later */
4267 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
4268 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
4270 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4273 static void gen6_enable_rps(struct drm_device
*dev
)
4275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4276 struct intel_engine_cs
*ring
;
4277 u32 rc6vids
, pcu_mbox
= 0, rc6_mask
= 0;
4282 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4284 /* Here begins a magic sequence of register writes to enable
4285 * auto-downclocking.
4287 * Perhaps there might be some value in exposing these to
4290 I915_WRITE(GEN6_RC_STATE
, 0);
4292 /* Clear the DBG now so we don't confuse earlier errors */
4293 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
4294 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
4295 I915_WRITE(GTFIFODBG
, gtfifodbg
);
4298 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4300 /* Initialize rps frequencies */
4301 gen6_init_rps_frequencies(dev
);
4303 /* disable the counters and set deterministic thresholds */
4304 I915_WRITE(GEN6_RC_CONTROL
, 0);
4306 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
4307 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
4308 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
4309 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
4310 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
4312 for_each_ring(ring
, dev_priv
, i
)
4313 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4315 I915_WRITE(GEN6_RC_SLEEP
, 0);
4316 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
4317 if (IS_IVYBRIDGE(dev
))
4318 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
4320 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
4321 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
4322 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
4324 /* Check if we are enabling RC6 */
4325 rc6_mode
= intel_enable_rc6(dev_priv
->dev
);
4326 if (rc6_mode
& INTEL_RC6_ENABLE
)
4327 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
4329 /* We don't use those on Haswell */
4330 if (!IS_HASWELL(dev
)) {
4331 if (rc6_mode
& INTEL_RC6p_ENABLE
)
4332 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
4334 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
4335 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
4338 intel_print_rc6_info(dev
, rc6_mask
);
4340 I915_WRITE(GEN6_RC_CONTROL
,
4342 GEN6_RC_CTL_EI_MODE(1) |
4343 GEN6_RC_CTL_HW_ENABLE
);
4345 /* Power down if completely idle for over 50ms */
4346 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
4347 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4349 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_MIN_FREQ_TABLE
, 0);
4351 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4353 ret
= sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, &pcu_mbox
);
4354 if (!ret
&& (pcu_mbox
& (1<<31))) { /* OC supported */
4355 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4356 (dev_priv
->rps
.max_freq_softlimit
& 0xff) * 50,
4357 (pcu_mbox
& 0xff) * 50);
4358 dev_priv
->rps
.max_freq
= pcu_mbox
& 0xff;
4361 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
4362 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
4365 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
4366 if (IS_GEN6(dev
) && ret
) {
4367 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4368 } else if (IS_GEN6(dev
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
4369 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4370 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
4371 rc6vids
&= 0xffff00;
4372 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
4373 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
4375 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4378 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4381 static void __gen6_update_ring_freq(struct drm_device
*dev
)
4383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4385 unsigned int gpu_freq
;
4386 unsigned int max_ia_freq
, min_ring_freq
;
4387 int scaling_factor
= 180;
4388 struct cpufreq_policy
*policy
;
4390 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4392 policy
= cpufreq_cpu_get(0);
4394 max_ia_freq
= policy
->cpuinfo
.max_freq
;
4395 cpufreq_cpu_put(policy
);
4398 * Default to measured freq if none found, PCU will ensure we
4401 max_ia_freq
= tsc_khz
;
4404 /* Convert from kHz to MHz */
4405 max_ia_freq
/= 1000;
4407 min_ring_freq
= I915_READ(DCLK
) & 0xf;
4408 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4409 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
4412 * For each potential GPU frequency, load a ring frequency we'd like
4413 * to use for memory access. We do this by specifying the IA frequency
4414 * the PCU should use as a reference to determine the ring frequency.
4416 for (gpu_freq
= dev_priv
->rps
.max_freq
; gpu_freq
>= dev_priv
->rps
.min_freq
;
4418 int diff
= dev_priv
->rps
.max_freq
- gpu_freq
;
4419 unsigned int ia_freq
= 0, ring_freq
= 0;
4421 if (INTEL_INFO(dev
)->gen
>= 8) {
4422 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4423 ring_freq
= max(min_ring_freq
, gpu_freq
);
4424 } else if (IS_HASWELL(dev
)) {
4425 ring_freq
= mult_frac(gpu_freq
, 5, 4);
4426 ring_freq
= max(min_ring_freq
, ring_freq
);
4427 /* leave ia_freq as the default, chosen by cpufreq */
4429 /* On older processors, there is no separate ring
4430 * clock domain, so in order to boost the bandwidth
4431 * of the ring, we need to upclock the CPU (ia_freq).
4433 * For GPU frequencies less than 750MHz,
4434 * just use the lowest ring freq.
4436 if (gpu_freq
< min_freq
)
4439 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
4440 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
4443 sandybridge_pcode_write(dev_priv
,
4444 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
4445 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
4446 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
4451 void gen6_update_ring_freq(struct drm_device
*dev
)
4453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4455 if (INTEL_INFO(dev
)->gen
< 6 || IS_VALLEYVIEW(dev
))
4458 mutex_lock(&dev_priv
->rps
.hw_lock
);
4459 __gen6_update_ring_freq(dev
);
4460 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4463 static int cherryview_rps_max_freq(struct drm_i915_private
*dev_priv
)
4465 struct drm_device
*dev
= dev_priv
->dev
;
4468 if (dev
->pdev
->revision
>= 0x20) {
4469 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
4471 switch (INTEL_INFO(dev
)->eu_total
) {
4473 /* (2 * 4) config */
4474 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT
);
4477 /* (2 * 6) config */
4478 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT
);
4481 /* (2 * 8) config */
4483 /* Setting (2 * 8) Min RP0 for any other combination */
4484 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT
);
4487 rp0
= (rp0
& FB_GFX_FREQ_FUSE_MASK
);
4489 /* For pre-production hardware */
4490 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_STATUS_REG
);
4491 rp0
= (val
>> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT
) &
4492 PUNIT_GPU_STATUS_MAX_FREQ_MASK
;
4497 static int cherryview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
4501 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_DUTYCYCLE_REG
);
4502 rpe
= (val
>> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT
) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK
;
4507 static int cherryview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
4509 struct drm_device
*dev
= dev_priv
->dev
;
4512 if (dev
->pdev
->revision
>= 0x20) {
4513 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
4514 rp1
= (val
& FB_GFX_FREQ_FUSE_MASK
);
4516 /* For pre-production hardware */
4517 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4518 rp1
= ((val
>> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT
) &
4519 PUNIT_GPU_STATUS_MAX_FREQ_MASK
);
4524 static int cherryview_rps_min_freq(struct drm_i915_private
*dev_priv
)
4526 struct drm_device
*dev
= dev_priv
->dev
;
4529 if (dev
->pdev
->revision
>= 0x20) {
4530 val
= vlv_punit_read(dev_priv
, FB_GFX_FMIN_AT_VMIN_FUSE
);
4531 rpn
= ((val
>> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT
) &
4532 FB_GFX_FREQ_FUSE_MASK
);
4533 } else { /* For pre-production hardware */
4534 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_STATUS_REG
);
4535 rpn
= ((val
>> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT
) &
4536 PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK
);
4542 static int valleyview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
4546 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
4548 rp1
= (val
& FB_GFX_FGUARANTEED_FREQ_FUSE_MASK
) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT
;
4553 static int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
4557 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
4559 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
4561 rp0
= min_t(u32
, rp0
, 0xea);
4566 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
4570 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
4571 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
4572 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
4573 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
4578 static int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
4580 return vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
4583 /* Check that the pctx buffer wasn't move under us. */
4584 static void valleyview_check_pctx(struct drm_i915_private
*dev_priv
)
4586 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
4588 WARN_ON(pctx_addr
!= dev_priv
->mm
.stolen_base
+
4589 dev_priv
->vlv_pctx
->stolen
->start
);
4593 /* Check that the pcbr address is not empty. */
4594 static void cherryview_check_pctx(struct drm_i915_private
*dev_priv
)
4596 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
4598 WARN_ON((pctx_addr
>> VLV_PCBR_ADDR_SHIFT
) == 0);
4601 static void cherryview_setup_pctx(struct drm_device
*dev
)
4603 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4604 unsigned long pctx_paddr
, paddr
;
4605 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
4607 int pctx_size
= 32*1024;
4609 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
4611 pcbr
= I915_READ(VLV_PCBR
);
4612 if ((pcbr
>> VLV_PCBR_ADDR_SHIFT
) == 0) {
4613 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4614 paddr
= (dev_priv
->mm
.stolen_base
+
4615 (gtt
->stolen_size
- pctx_size
));
4617 pctx_paddr
= (paddr
& (~4095));
4618 I915_WRITE(VLV_PCBR
, pctx_paddr
);
4621 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
4624 static void valleyview_setup_pctx(struct drm_device
*dev
)
4626 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4627 struct drm_i915_gem_object
*pctx
;
4628 unsigned long pctx_paddr
;
4630 int pctx_size
= 24*1024;
4632 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
4634 pcbr
= I915_READ(VLV_PCBR
);
4636 /* BIOS set it up already, grab the pre-alloc'd space */
4639 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
4640 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
->dev
,
4642 I915_GTT_OFFSET_NONE
,
4647 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4650 * From the Gunit register HAS:
4651 * The Gfx driver is expected to program this register and ensure
4652 * proper allocation within Gfx stolen memory. For example, this
4653 * register should be programmed such than the PCBR range does not
4654 * overlap with other ranges, such as the frame buffer, protected
4655 * memory, or any other relevant ranges.
4657 pctx
= i915_gem_object_create_stolen(dev
, pctx_size
);
4659 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4663 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
4664 I915_WRITE(VLV_PCBR
, pctx_paddr
);
4667 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
4668 dev_priv
->vlv_pctx
= pctx
;
4671 static void valleyview_cleanup_pctx(struct drm_device
*dev
)
4673 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4675 if (WARN_ON(!dev_priv
->vlv_pctx
))
4678 drm_gem_object_unreference(&dev_priv
->vlv_pctx
->base
);
4679 dev_priv
->vlv_pctx
= NULL
;
4682 static void valleyview_init_gt_powersave(struct drm_device
*dev
)
4684 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4687 valleyview_setup_pctx(dev
);
4689 mutex_lock(&dev_priv
->rps
.hw_lock
);
4691 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4692 switch ((val
>> 6) & 3) {
4695 dev_priv
->mem_freq
= 800;
4698 dev_priv
->mem_freq
= 1066;
4701 dev_priv
->mem_freq
= 1333;
4704 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
4706 dev_priv
->rps
.max_freq
= valleyview_rps_max_freq(dev_priv
);
4707 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
4708 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4709 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
4710 dev_priv
->rps
.max_freq
);
4712 dev_priv
->rps
.efficient_freq
= valleyview_rps_rpe_freq(dev_priv
);
4713 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4714 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4715 dev_priv
->rps
.efficient_freq
);
4717 dev_priv
->rps
.rp1_freq
= valleyview_rps_guar_freq(dev_priv
);
4718 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4719 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
4720 dev_priv
->rps
.rp1_freq
);
4722 dev_priv
->rps
.min_freq
= valleyview_rps_min_freq(dev_priv
);
4723 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4724 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
4725 dev_priv
->rps
.min_freq
);
4727 /* Preserve min/max settings in case of re-init */
4728 if (dev_priv
->rps
.max_freq_softlimit
== 0)
4729 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
4731 if (dev_priv
->rps
.min_freq_softlimit
== 0)
4732 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
4734 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4737 static void cherryview_init_gt_powersave(struct drm_device
*dev
)
4739 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4742 cherryview_setup_pctx(dev
);
4744 mutex_lock(&dev_priv
->rps
.hw_lock
);
4746 mutex_lock(&dev_priv
->dpio_lock
);
4747 val
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
);
4748 mutex_unlock(&dev_priv
->dpio_lock
);
4750 switch ((val
>> 2) & 0x7) {
4753 dev_priv
->rps
.cz_freq
= 200;
4754 dev_priv
->mem_freq
= 1600;
4757 dev_priv
->rps
.cz_freq
= 267;
4758 dev_priv
->mem_freq
= 1600;
4761 dev_priv
->rps
.cz_freq
= 333;
4762 dev_priv
->mem_freq
= 2000;
4765 dev_priv
->rps
.cz_freq
= 320;
4766 dev_priv
->mem_freq
= 1600;
4769 dev_priv
->rps
.cz_freq
= 400;
4770 dev_priv
->mem_freq
= 1600;
4773 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
4775 dev_priv
->rps
.max_freq
= cherryview_rps_max_freq(dev_priv
);
4776 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
4777 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4778 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
4779 dev_priv
->rps
.max_freq
);
4781 dev_priv
->rps
.efficient_freq
= cherryview_rps_rpe_freq(dev_priv
);
4782 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4783 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4784 dev_priv
->rps
.efficient_freq
);
4786 dev_priv
->rps
.rp1_freq
= cherryview_rps_guar_freq(dev_priv
);
4787 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4788 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
4789 dev_priv
->rps
.rp1_freq
);
4791 dev_priv
->rps
.min_freq
= cherryview_rps_min_freq(dev_priv
);
4792 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4793 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
4794 dev_priv
->rps
.min_freq
);
4796 WARN_ONCE((dev_priv
->rps
.max_freq
|
4797 dev_priv
->rps
.efficient_freq
|
4798 dev_priv
->rps
.rp1_freq
|
4799 dev_priv
->rps
.min_freq
) & 1,
4800 "Odd GPU freq values\n");
4802 /* Preserve min/max settings in case of re-init */
4803 if (dev_priv
->rps
.max_freq_softlimit
== 0)
4804 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
4806 if (dev_priv
->rps
.min_freq_softlimit
== 0)
4807 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
4809 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4812 static void valleyview_cleanup_gt_powersave(struct drm_device
*dev
)
4814 valleyview_cleanup_pctx(dev
);
4817 static void cherryview_enable_rps(struct drm_device
*dev
)
4819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4820 struct intel_engine_cs
*ring
;
4821 u32 gtfifodbg
, val
, rc6_mode
= 0, pcbr
;
4824 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4826 gtfifodbg
= I915_READ(GTFIFODBG
);
4828 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4830 I915_WRITE(GTFIFODBG
, gtfifodbg
);
4833 cherryview_check_pctx(dev_priv
);
4835 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4836 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4837 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4839 /* Disable RC states. */
4840 I915_WRITE(GEN6_RC_CONTROL
, 0);
4842 /* 2a: Program RC6 thresholds.*/
4843 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
4844 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
4845 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
4847 for_each_ring(ring
, dev_priv
, i
)
4848 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4849 I915_WRITE(GEN6_RC_SLEEP
, 0);
4851 /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */
4852 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
4854 /* allows RC6 residency counter to work */
4855 I915_WRITE(VLV_COUNTER_CONTROL
,
4856 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
4857 VLV_MEDIA_RC6_COUNT_EN
|
4858 VLV_RENDER_RC6_COUNT_EN
));
4860 /* For now we assume BIOS is allocating and populating the PCBR */
4861 pcbr
= I915_READ(VLV_PCBR
);
4864 if ((intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
) &&
4865 (pcbr
>> VLV_PCBR_ADDR_SHIFT
))
4866 rc6_mode
= GEN7_RC_CTL_TO_MODE
;
4868 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
4870 /* 4 Program defaults and thresholds for RPS*/
4871 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
4872 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
4873 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
4874 I915_WRITE(GEN6_RP_UP_EI
, 66000);
4875 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
4877 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4880 I915_WRITE(GEN6_RP_CONTROL
,
4881 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4882 GEN6_RP_MEDIA_IS_GFX
|
4884 GEN6_RP_UP_BUSY_AVG
|
4885 GEN6_RP_DOWN_IDLE_AVG
);
4887 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4889 /* RPS code assumes GPLL is used */
4890 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
4892 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val
& GPLLENABLE
? "yes" : "no");
4893 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
4895 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
4896 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4897 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
4898 dev_priv
->rps
.cur_freq
);
4900 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4901 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4902 dev_priv
->rps
.efficient_freq
);
4904 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.efficient_freq
);
4906 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4909 static void valleyview_enable_rps(struct drm_device
*dev
)
4911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4912 struct intel_engine_cs
*ring
;
4913 u32 gtfifodbg
, val
, rc6_mode
= 0;
4916 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4918 valleyview_check_pctx(dev_priv
);
4920 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
4921 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4923 I915_WRITE(GTFIFODBG
, gtfifodbg
);
4926 /* If VLV, Forcewake all wells, else re-direct to regular path */
4927 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4929 /* Disable RC states. */
4930 I915_WRITE(GEN6_RC_CONTROL
, 0);
4932 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
4933 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
4934 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
4935 I915_WRITE(GEN6_RP_UP_EI
, 66000);
4936 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
4938 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4940 I915_WRITE(GEN6_RP_CONTROL
,
4941 GEN6_RP_MEDIA_TURBO
|
4942 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4943 GEN6_RP_MEDIA_IS_GFX
|
4945 GEN6_RP_UP_BUSY_AVG
|
4946 GEN6_RP_DOWN_IDLE_CONT
);
4948 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
4949 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
4950 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
4952 for_each_ring(ring
, dev_priv
, i
)
4953 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4955 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
4957 /* allows RC6 residency counter to work */
4958 I915_WRITE(VLV_COUNTER_CONTROL
,
4959 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN
|
4960 VLV_RENDER_RC0_COUNT_EN
|
4961 VLV_MEDIA_RC6_COUNT_EN
|
4962 VLV_RENDER_RC6_COUNT_EN
));
4964 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
4965 rc6_mode
= GEN7_RC_CTL_TO_MODE
| VLV_RC_CTL_CTX_RST_PARALLEL
;
4967 intel_print_rc6_info(dev
, rc6_mode
);
4969 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
4971 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4973 /* RPS code assumes GPLL is used */
4974 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
4976 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val
& GPLLENABLE
? "yes" : "no");
4977 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
4979 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
4980 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4981 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
4982 dev_priv
->rps
.cur_freq
);
4984 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4985 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4986 dev_priv
->rps
.efficient_freq
);
4988 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.efficient_freq
);
4990 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4993 void ironlake_teardown_rc6(struct drm_device
*dev
)
4995 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4997 if (dev_priv
->ips
.renderctx
) {
4998 i915_gem_object_ggtt_unpin(dev_priv
->ips
.renderctx
);
4999 drm_gem_object_unreference(&dev_priv
->ips
.renderctx
->base
);
5000 dev_priv
->ips
.renderctx
= NULL
;
5003 if (dev_priv
->ips
.pwrctx
) {
5004 i915_gem_object_ggtt_unpin(dev_priv
->ips
.pwrctx
);
5005 drm_gem_object_unreference(&dev_priv
->ips
.pwrctx
->base
);
5006 dev_priv
->ips
.pwrctx
= NULL
;
5010 static void ironlake_disable_rc6(struct drm_device
*dev
)
5012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5014 if (I915_READ(PWRCTXA
)) {
5015 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
5016 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) | RCX_SW_EXIT
);
5017 wait_for(((I915_READ(RSTDBYCTL
) & RSX_STATUS_MASK
) == RSX_STATUS_ON
),
5020 I915_WRITE(PWRCTXA
, 0);
5021 POSTING_READ(PWRCTXA
);
5023 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
5024 POSTING_READ(RSTDBYCTL
);
5028 static int ironlake_setup_rc6(struct drm_device
*dev
)
5030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5032 if (dev_priv
->ips
.renderctx
== NULL
)
5033 dev_priv
->ips
.renderctx
= intel_alloc_context_page(dev
);
5034 if (!dev_priv
->ips
.renderctx
)
5037 if (dev_priv
->ips
.pwrctx
== NULL
)
5038 dev_priv
->ips
.pwrctx
= intel_alloc_context_page(dev
);
5039 if (!dev_priv
->ips
.pwrctx
) {
5040 ironlake_teardown_rc6(dev
);
5047 static void ironlake_enable_rc6(struct drm_device
*dev
)
5049 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5050 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
5051 bool was_interruptible
;
5054 /* rc6 disabled by default due to repeated reports of hanging during
5057 if (!intel_enable_rc6(dev
))
5060 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
5062 ret
= ironlake_setup_rc6(dev
);
5066 was_interruptible
= dev_priv
->mm
.interruptible
;
5067 dev_priv
->mm
.interruptible
= false;
5070 * GPU can automatically power down the render unit if given a page
5073 ret
= intel_ring_begin(ring
, 6);
5075 ironlake_teardown_rc6(dev
);
5076 dev_priv
->mm
.interruptible
= was_interruptible
;
5080 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
| MI_SUSPEND_FLUSH_EN
);
5081 intel_ring_emit(ring
, MI_SET_CONTEXT
);
5082 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(dev_priv
->ips
.renderctx
) |
5084 MI_SAVE_EXT_STATE_EN
|
5085 MI_RESTORE_EXT_STATE_EN
|
5086 MI_RESTORE_INHIBIT
);
5087 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
);
5088 intel_ring_emit(ring
, MI_NOOP
);
5089 intel_ring_emit(ring
, MI_FLUSH
);
5090 intel_ring_advance(ring
);
5093 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
5094 * does an implicit flush, combined with MI_FLUSH above, it should be
5095 * safe to assume that renderctx is valid
5097 ret
= intel_ring_idle(ring
);
5098 dev_priv
->mm
.interruptible
= was_interruptible
;
5100 DRM_ERROR("failed to enable ironlake power savings\n");
5101 ironlake_teardown_rc6(dev
);
5105 I915_WRITE(PWRCTXA
, i915_gem_obj_ggtt_offset(dev_priv
->ips
.pwrctx
) | PWRCTX_EN
);
5106 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
5108 intel_print_rc6_info(dev
, GEN6_RC_CTL_RC6_ENABLE
);
5111 static unsigned long intel_pxfreq(u32 vidfreq
)
5114 int div
= (vidfreq
& 0x3f0000) >> 16;
5115 int post
= (vidfreq
& 0x3000) >> 12;
5116 int pre
= (vidfreq
& 0x7);
5121 freq
= ((div
* 133333) / ((1<<post
) * pre
));
5126 static const struct cparams
{
5132 { 1, 1333, 301, 28664 },
5133 { 1, 1066, 294, 24460 },
5134 { 1, 800, 294, 25192 },
5135 { 0, 1333, 276, 27605 },
5136 { 0, 1066, 276, 27605 },
5137 { 0, 800, 231, 23784 },
5140 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
5142 u64 total_count
, diff
, ret
;
5143 u32 count1
, count2
, count3
, m
= 0, c
= 0;
5144 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
5147 assert_spin_locked(&mchdev_lock
);
5149 diff1
= now
- dev_priv
->ips
.last_time1
;
5151 /* Prevent division-by-zero if we are asking too fast.
5152 * Also, we don't get interesting results if we are polling
5153 * faster than once in 10ms, so just return the saved value
5157 return dev_priv
->ips
.chipset_power
;
5159 count1
= I915_READ(DMIEC
);
5160 count2
= I915_READ(DDREC
);
5161 count3
= I915_READ(CSIEC
);
5163 total_count
= count1
+ count2
+ count3
;
5165 /* FIXME: handle per-counter overflow */
5166 if (total_count
< dev_priv
->ips
.last_count1
) {
5167 diff
= ~0UL - dev_priv
->ips
.last_count1
;
5168 diff
+= total_count
;
5170 diff
= total_count
- dev_priv
->ips
.last_count1
;
5173 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
5174 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
5175 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
5182 diff
= div_u64(diff
, diff1
);
5183 ret
= ((m
* diff
) + c
);
5184 ret
= div_u64(ret
, 10);
5186 dev_priv
->ips
.last_count1
= total_count
;
5187 dev_priv
->ips
.last_time1
= now
;
5189 dev_priv
->ips
.chipset_power
= ret
;
5194 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
5196 struct drm_device
*dev
= dev_priv
->dev
;
5199 if (INTEL_INFO(dev
)->gen
!= 5)
5202 spin_lock_irq(&mchdev_lock
);
5204 val
= __i915_chipset_val(dev_priv
);
5206 spin_unlock_irq(&mchdev_lock
);
5211 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
5213 unsigned long m
, x
, b
;
5216 tsfs
= I915_READ(TSFS
);
5218 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
5219 x
= I915_READ8(TR1
);
5221 b
= tsfs
& TSFS_INTR_MASK
;
5223 return ((m
* x
) / 127) - b
;
5226 static int _pxvid_to_vd(u8 pxvid
)
5231 if (pxvid
>= 8 && pxvid
< 31)
5234 return (pxvid
+ 2) * 125;
5237 static u32
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
5239 struct drm_device
*dev
= dev_priv
->dev
;
5240 const int vd
= _pxvid_to_vd(pxvid
);
5241 const int vm
= vd
- 1125;
5243 if (INTEL_INFO(dev
)->is_mobile
)
5244 return vm
> 0 ? vm
: 0;
5249 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
5251 u64 now
, diff
, diffms
;
5254 assert_spin_locked(&mchdev_lock
);
5256 now
= ktime_get_raw_ns();
5257 diffms
= now
- dev_priv
->ips
.last_time2
;
5258 do_div(diffms
, NSEC_PER_MSEC
);
5260 /* Don't divide by 0 */
5264 count
= I915_READ(GFXEC
);
5266 if (count
< dev_priv
->ips
.last_count2
) {
5267 diff
= ~0UL - dev_priv
->ips
.last_count2
;
5270 diff
= count
- dev_priv
->ips
.last_count2
;
5273 dev_priv
->ips
.last_count2
= count
;
5274 dev_priv
->ips
.last_time2
= now
;
5276 /* More magic constants... */
5278 diff
= div_u64(diff
, diffms
* 10);
5279 dev_priv
->ips
.gfx_power
= diff
;
5282 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
5284 struct drm_device
*dev
= dev_priv
->dev
;
5286 if (INTEL_INFO(dev
)->gen
!= 5)
5289 spin_lock_irq(&mchdev_lock
);
5291 __i915_update_gfx_val(dev_priv
);
5293 spin_unlock_irq(&mchdev_lock
);
5296 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
5298 unsigned long t
, corr
, state1
, corr2
, state2
;
5301 assert_spin_locked(&mchdev_lock
);
5303 pxvid
= I915_READ(PXVFREQ_BASE
+ (dev_priv
->rps
.cur_freq
* 4));
5304 pxvid
= (pxvid
>> 24) & 0x7f;
5305 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
5309 t
= i915_mch_val(dev_priv
);
5311 /* Revel in the empirically derived constants */
5313 /* Correction factor in 1/100000 units */
5315 corr
= ((t
* 2349) + 135940);
5317 corr
= ((t
* 964) + 29317);
5319 corr
= ((t
* 301) + 1004);
5321 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
5323 corr2
= (corr
* dev_priv
->ips
.corr
);
5325 state2
= (corr2
* state1
) / 10000;
5326 state2
/= 100; /* convert to mW */
5328 __i915_update_gfx_val(dev_priv
);
5330 return dev_priv
->ips
.gfx_power
+ state2
;
5333 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
5335 struct drm_device
*dev
= dev_priv
->dev
;
5338 if (INTEL_INFO(dev
)->gen
!= 5)
5341 spin_lock_irq(&mchdev_lock
);
5343 val
= __i915_gfx_val(dev_priv
);
5345 spin_unlock_irq(&mchdev_lock
);
5351 * i915_read_mch_val - return value for IPS use
5353 * Calculate and return a value for the IPS driver to use when deciding whether
5354 * we have thermal and power headroom to increase CPU or GPU power budget.
5356 unsigned long i915_read_mch_val(void)
5358 struct drm_i915_private
*dev_priv
;
5359 unsigned long chipset_val
, graphics_val
, ret
= 0;
5361 spin_lock_irq(&mchdev_lock
);
5364 dev_priv
= i915_mch_dev
;
5366 chipset_val
= __i915_chipset_val(dev_priv
);
5367 graphics_val
= __i915_gfx_val(dev_priv
);
5369 ret
= chipset_val
+ graphics_val
;
5372 spin_unlock_irq(&mchdev_lock
);
5376 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
5379 * i915_gpu_raise - raise GPU frequency limit
5381 * Raise the limit; IPS indicates we have thermal headroom.
5383 bool i915_gpu_raise(void)
5385 struct drm_i915_private
*dev_priv
;
5388 spin_lock_irq(&mchdev_lock
);
5389 if (!i915_mch_dev
) {
5393 dev_priv
= i915_mch_dev
;
5395 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
5396 dev_priv
->ips
.max_delay
--;
5399 spin_unlock_irq(&mchdev_lock
);
5403 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
5406 * i915_gpu_lower - lower GPU frequency limit
5408 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5409 * frequency maximum.
5411 bool i915_gpu_lower(void)
5413 struct drm_i915_private
*dev_priv
;
5416 spin_lock_irq(&mchdev_lock
);
5417 if (!i915_mch_dev
) {
5421 dev_priv
= i915_mch_dev
;
5423 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
5424 dev_priv
->ips
.max_delay
++;
5427 spin_unlock_irq(&mchdev_lock
);
5431 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
5434 * i915_gpu_busy - indicate GPU business to IPS
5436 * Tell the IPS driver whether or not the GPU is busy.
5438 bool i915_gpu_busy(void)
5440 struct drm_i915_private
*dev_priv
;
5441 struct intel_engine_cs
*ring
;
5445 spin_lock_irq(&mchdev_lock
);
5448 dev_priv
= i915_mch_dev
;
5450 for_each_ring(ring
, dev_priv
, i
)
5451 ret
|= !list_empty(&ring
->request_list
);
5454 spin_unlock_irq(&mchdev_lock
);
5458 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
5461 * i915_gpu_turbo_disable - disable graphics turbo
5463 * Disable graphics turbo by resetting the max frequency and setting the
5464 * current frequency to the default.
5466 bool i915_gpu_turbo_disable(void)
5468 struct drm_i915_private
*dev_priv
;
5471 spin_lock_irq(&mchdev_lock
);
5472 if (!i915_mch_dev
) {
5476 dev_priv
= i915_mch_dev
;
5478 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
5480 if (!ironlake_set_drps(dev_priv
->dev
, dev_priv
->ips
.fstart
))
5484 spin_unlock_irq(&mchdev_lock
);
5488 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
5491 * Tells the intel_ips driver that the i915 driver is now loaded, if
5492 * IPS got loaded first.
5494 * This awkward dance is so that neither module has to depend on the
5495 * other in order for IPS to do the appropriate communication of
5496 * GPU turbo limits to i915.
5499 ips_ping_for_i915_load(void)
5503 link
= symbol_get(ips_link_to_i915_driver
);
5506 symbol_put(ips_link_to_i915_driver
);
5510 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
5512 /* We only register the i915 ips part with intel-ips once everything is
5513 * set up, to avoid intel-ips sneaking in and reading bogus values. */
5514 spin_lock_irq(&mchdev_lock
);
5515 i915_mch_dev
= dev_priv
;
5516 spin_unlock_irq(&mchdev_lock
);
5518 ips_ping_for_i915_load();
5521 void intel_gpu_ips_teardown(void)
5523 spin_lock_irq(&mchdev_lock
);
5524 i915_mch_dev
= NULL
;
5525 spin_unlock_irq(&mchdev_lock
);
5528 static void intel_init_emon(struct drm_device
*dev
)
5530 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5535 /* Disable to program */
5539 /* Program energy weights for various events */
5540 I915_WRITE(SDEW
, 0x15040d00);
5541 I915_WRITE(CSIEW0
, 0x007f0000);
5542 I915_WRITE(CSIEW1
, 0x1e220004);
5543 I915_WRITE(CSIEW2
, 0x04000004);
5545 for (i
= 0; i
< 5; i
++)
5546 I915_WRITE(PEW
+ (i
* 4), 0);
5547 for (i
= 0; i
< 3; i
++)
5548 I915_WRITE(DEW
+ (i
* 4), 0);
5550 /* Program P-state weights to account for frequency power adjustment */
5551 for (i
= 0; i
< 16; i
++) {
5552 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
5553 unsigned long freq
= intel_pxfreq(pxvidfreq
);
5554 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
5559 val
*= (freq
/ 1000);
5561 val
/= (127*127*900);
5563 DRM_ERROR("bad pxval: %ld\n", val
);
5566 /* Render standby states get 0 weight */
5570 for (i
= 0; i
< 4; i
++) {
5571 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
5572 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
5573 I915_WRITE(PXW
+ (i
* 4), val
);
5576 /* Adjust magic regs to magic values (more experimental results) */
5577 I915_WRITE(OGW0
, 0);
5578 I915_WRITE(OGW1
, 0);
5579 I915_WRITE(EG0
, 0x00007f00);
5580 I915_WRITE(EG1
, 0x0000000e);
5581 I915_WRITE(EG2
, 0x000e0000);
5582 I915_WRITE(EG3
, 0x68000300);
5583 I915_WRITE(EG4
, 0x42000000);
5584 I915_WRITE(EG5
, 0x00140031);
5588 for (i
= 0; i
< 8; i
++)
5589 I915_WRITE(PXWL
+ (i
* 4), 0);
5591 /* Enable PMON + select events */
5592 I915_WRITE(ECR
, 0x80000019);
5594 lcfuse
= I915_READ(LCFUSE02
);
5596 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
5599 void intel_init_gt_powersave(struct drm_device
*dev
)
5601 i915
.enable_rc6
= sanitize_rc6_option(dev
, i915
.enable_rc6
);
5603 if (IS_CHERRYVIEW(dev
))
5604 cherryview_init_gt_powersave(dev
);
5605 else if (IS_VALLEYVIEW(dev
))
5606 valleyview_init_gt_powersave(dev
);
5609 void intel_cleanup_gt_powersave(struct drm_device
*dev
)
5611 if (IS_CHERRYVIEW(dev
))
5613 else if (IS_VALLEYVIEW(dev
))
5614 valleyview_cleanup_gt_powersave(dev
);
5617 static void gen6_suspend_rps(struct drm_device
*dev
)
5619 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5621 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
5624 * TODO: disable RPS interrupts on GEN9+ too once RPS support
5627 if (INTEL_INFO(dev
)->gen
< 9)
5628 gen6_disable_rps_interrupts(dev
);
5632 * intel_suspend_gt_powersave - suspend PM work and helper threads
5635 * We don't want to disable RC6 or other features here, we just want
5636 * to make sure any work we've queued has finished and won't bother
5637 * us while we're suspended.
5639 void intel_suspend_gt_powersave(struct drm_device
*dev
)
5641 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5643 if (INTEL_INFO(dev
)->gen
< 6)
5646 gen6_suspend_rps(dev
);
5648 /* Force GPU to min freq during suspend */
5649 gen6_rps_idle(dev_priv
);
5652 void intel_disable_gt_powersave(struct drm_device
*dev
)
5654 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5656 if (IS_IRONLAKE_M(dev
)) {
5657 ironlake_disable_drps(dev
);
5658 ironlake_disable_rc6(dev
);
5659 } else if (INTEL_INFO(dev
)->gen
>= 6) {
5660 intel_suspend_gt_powersave(dev
);
5662 mutex_lock(&dev_priv
->rps
.hw_lock
);
5663 if (INTEL_INFO(dev
)->gen
>= 9)
5664 gen9_disable_rps(dev
);
5665 else if (IS_CHERRYVIEW(dev
))
5666 cherryview_disable_rps(dev
);
5667 else if (IS_VALLEYVIEW(dev
))
5668 valleyview_disable_rps(dev
);
5670 gen6_disable_rps(dev
);
5672 dev_priv
->rps
.enabled
= false;
5673 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5677 static void intel_gen6_powersave_work(struct work_struct
*work
)
5679 struct drm_i915_private
*dev_priv
=
5680 container_of(work
, struct drm_i915_private
,
5681 rps
.delayed_resume_work
.work
);
5682 struct drm_device
*dev
= dev_priv
->dev
;
5684 mutex_lock(&dev_priv
->rps
.hw_lock
);
5687 * TODO: reset/enable RPS interrupts on GEN9+ too, once RPS support is
5690 if (INTEL_INFO(dev
)->gen
< 9)
5691 gen6_reset_rps_interrupts(dev
);
5693 if (IS_CHERRYVIEW(dev
)) {
5694 cherryview_enable_rps(dev
);
5695 } else if (IS_VALLEYVIEW(dev
)) {
5696 valleyview_enable_rps(dev
);
5697 } else if (INTEL_INFO(dev
)->gen
>= 9) {
5698 gen9_enable_rc6(dev
);
5699 gen9_enable_rps(dev
);
5700 __gen6_update_ring_freq(dev
);
5701 } else if (IS_BROADWELL(dev
)) {
5702 gen8_enable_rps(dev
);
5703 __gen6_update_ring_freq(dev
);
5705 gen6_enable_rps(dev
);
5706 __gen6_update_ring_freq(dev
);
5708 dev_priv
->rps
.enabled
= true;
5710 if (INTEL_INFO(dev
)->gen
< 9)
5711 gen6_enable_rps_interrupts(dev
);
5713 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5715 intel_runtime_pm_put(dev_priv
);
5718 void intel_enable_gt_powersave(struct drm_device
*dev
)
5720 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5722 /* Powersaving is controlled by the host when inside a VM */
5723 if (intel_vgpu_active(dev
))
5726 if (IS_IRONLAKE_M(dev
)) {
5727 mutex_lock(&dev
->struct_mutex
);
5728 ironlake_enable_drps(dev
);
5729 ironlake_enable_rc6(dev
);
5730 intel_init_emon(dev
);
5731 mutex_unlock(&dev
->struct_mutex
);
5732 } else if (INTEL_INFO(dev
)->gen
>= 6) {
5734 * PCU communication is slow and this doesn't need to be
5735 * done at any specific time, so do this out of our fast path
5736 * to make resume and init faster.
5738 * We depend on the HW RC6 power context save/restore
5739 * mechanism when entering D3 through runtime PM suspend. So
5740 * disable RPM until RPS/RC6 is properly setup. We can only
5741 * get here via the driver load/system resume/runtime resume
5742 * paths, so the _noresume version is enough (and in case of
5743 * runtime resume it's necessary).
5745 if (schedule_delayed_work(&dev_priv
->rps
.delayed_resume_work
,
5746 round_jiffies_up_relative(HZ
)))
5747 intel_runtime_pm_get_noresume(dev_priv
);
5751 void intel_reset_gt_powersave(struct drm_device
*dev
)
5753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5755 if (INTEL_INFO(dev
)->gen
< 6)
5758 gen6_suspend_rps(dev
);
5759 dev_priv
->rps
.enabled
= false;
5762 static void ibx_init_clock_gating(struct drm_device
*dev
)
5764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5767 * On Ibex Peak and Cougar Point, we need to disable clock
5768 * gating for the panel power sequencer or it will fail to
5769 * start up when no ports are active.
5771 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
5774 static void g4x_disable_trickle_feed(struct drm_device
*dev
)
5776 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5779 for_each_pipe(dev_priv
, pipe
) {
5780 I915_WRITE(DSPCNTR(pipe
),
5781 I915_READ(DSPCNTR(pipe
)) |
5782 DISPPLANE_TRICKLE_FEED_DISABLE
);
5783 intel_flush_primary_plane(dev_priv
, pipe
);
5787 static void ilk_init_lp_watermarks(struct drm_device
*dev
)
5789 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5791 I915_WRITE(WM3_LP_ILK
, I915_READ(WM3_LP_ILK
) & ~WM1_LP_SR_EN
);
5792 I915_WRITE(WM2_LP_ILK
, I915_READ(WM2_LP_ILK
) & ~WM1_LP_SR_EN
);
5793 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
5796 * Don't touch WM1S_LP_EN here.
5797 * Doing so could cause underruns.
5801 static void ironlake_init_clock_gating(struct drm_device
*dev
)
5803 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5804 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
5808 * WaFbcDisableDpfcClockGating:ilk
5810 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
5811 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
5812 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
5814 I915_WRITE(PCH_3DCGDIS0
,
5815 MARIUNIT_CLOCK_GATE_DISABLE
|
5816 SVSMUNIT_CLOCK_GATE_DISABLE
);
5817 I915_WRITE(PCH_3DCGDIS1
,
5818 VFMUNIT_CLOCK_GATE_DISABLE
);
5821 * According to the spec the following bits should be set in
5822 * order to enable memory self-refresh
5823 * The bit 22/21 of 0x42004
5824 * The bit 5 of 0x42020
5825 * The bit 15 of 0x45000
5827 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5828 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
5829 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
5830 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
5831 I915_WRITE(DISP_ARB_CTL
,
5832 (I915_READ(DISP_ARB_CTL
) |
5835 ilk_init_lp_watermarks(dev
);
5838 * Based on the document from hardware guys the following bits
5839 * should be set unconditionally in order to enable FBC.
5840 * The bit 22 of 0x42000
5841 * The bit 22 of 0x42004
5842 * The bit 7,8,9 of 0x42020.
5844 if (IS_IRONLAKE_M(dev
)) {
5845 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5846 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5847 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5849 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5850 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5854 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
5856 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5857 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5858 ILK_ELPIN_409_SELECT
);
5859 I915_WRITE(_3D_CHICKEN2
,
5860 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
5861 _3D_CHICKEN2_WM_READ_PIPELINED
);
5863 /* WaDisableRenderCachePipelinedFlush:ilk */
5864 I915_WRITE(CACHE_MODE_0
,
5865 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
5867 /* WaDisable_RenderCache_OperationalFlush:ilk */
5868 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5870 g4x_disable_trickle_feed(dev
);
5872 ibx_init_clock_gating(dev
);
5875 static void cpt_init_clock_gating(struct drm_device
*dev
)
5877 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5882 * On Ibex Peak and Cougar Point, we need to disable clock
5883 * gating for the panel power sequencer or it will fail to
5884 * start up when no ports are active.
5886 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
5887 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
5888 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
5889 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
5890 DPLS_EDP_PPS_FIX_DIS
);
5891 /* The below fixes the weird display corruption, a few pixels shifted
5892 * downward, on (only) LVDS of some HP laptops with IVY.
5894 for_each_pipe(dev_priv
, pipe
) {
5895 val
= I915_READ(TRANS_CHICKEN2(pipe
));
5896 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
5897 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
5898 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
5899 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
5900 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
5901 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
5902 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
5903 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
5905 /* WADP0ClockGatingDisable */
5906 for_each_pipe(dev_priv
, pipe
) {
5907 I915_WRITE(TRANS_CHICKEN1(pipe
),
5908 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
5912 static void gen6_check_mch_setup(struct drm_device
*dev
)
5914 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5917 tmp
= I915_READ(MCH_SSKPD
);
5918 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
)
5919 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5923 static void gen6_init_clock_gating(struct drm_device
*dev
)
5925 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5926 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
5928 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
5930 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5931 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5932 ILK_ELPIN_409_SELECT
);
5934 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5935 I915_WRITE(_3D_CHICKEN
,
5936 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
5938 /* WaDisable_RenderCache_OperationalFlush:snb */
5939 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5942 * BSpec recoomends 8x4 when MSAA is used,
5943 * however in practice 16x4 seems fastest.
5945 * Note that PS/WM thread counts depend on the WIZ hashing
5946 * disable bit, which we don't touch here, but it's good
5947 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5949 I915_WRITE(GEN6_GT_MODE
,
5950 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
5952 ilk_init_lp_watermarks(dev
);
5954 I915_WRITE(CACHE_MODE_0
,
5955 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
5957 I915_WRITE(GEN6_UCGCTL1
,
5958 I915_READ(GEN6_UCGCTL1
) |
5959 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
5960 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
5962 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5963 * gating disable must be set. Failure to set it results in
5964 * flickering pixels due to Z write ordering failures after
5965 * some amount of runtime in the Mesa "fire" demo, and Unigine
5966 * Sanctuary and Tropics, and apparently anything else with
5967 * alpha test or pixel discard.
5969 * According to the spec, bit 11 (RCCUNIT) must also be set,
5970 * but we didn't debug actual testcases to find it out.
5972 * WaDisableRCCUnitClockGating:snb
5973 * WaDisableRCPBUnitClockGating:snb
5975 I915_WRITE(GEN6_UCGCTL2
,
5976 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
5977 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
5979 /* WaStripsFansDisableFastClipPerformanceFix:snb */
5980 I915_WRITE(_3D_CHICKEN3
,
5981 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
));
5985 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5986 * 3DSTATE_SF number of SF output attributes is more than 16."
5988 I915_WRITE(_3D_CHICKEN3
,
5989 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH
));
5992 * According to the spec the following bits should be
5993 * set in order to enable memory self-refresh and fbc:
5994 * The bit21 and bit22 of 0x42000
5995 * The bit21 and bit22 of 0x42004
5996 * The bit5 and bit7 of 0x42020
5997 * The bit14 of 0x70180
5998 * The bit14 of 0x71180
6000 * WaFbcAsynchFlipDisableFbcQueue:snb
6002 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
6003 I915_READ(ILK_DISPLAY_CHICKEN1
) |
6004 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
6005 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6006 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6007 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
6008 I915_WRITE(ILK_DSPCLK_GATE_D
,
6009 I915_READ(ILK_DSPCLK_GATE_D
) |
6010 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
6011 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
6013 g4x_disable_trickle_feed(dev
);
6015 cpt_init_clock_gating(dev
);
6017 gen6_check_mch_setup(dev
);
6020 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
6022 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
6025 * WaVSThreadDispatchOverride:ivb,vlv
6027 * This actually overrides the dispatch
6028 * mode for all thread types.
6030 reg
&= ~GEN7_FF_SCHED_MASK
;
6031 reg
|= GEN7_FF_TS_SCHED_HW
;
6032 reg
|= GEN7_FF_VS_SCHED_HW
;
6033 reg
|= GEN7_FF_DS_SCHED_HW
;
6035 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
6038 static void lpt_init_clock_gating(struct drm_device
*dev
)
6040 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6043 * TODO: this bit should only be enabled when really needed, then
6044 * disabled when not needed anymore in order to save power.
6046 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
)
6047 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
6048 I915_READ(SOUTH_DSPCLK_GATE_D
) |
6049 PCH_LP_PARTITION_LEVEL_DISABLE
);
6051 /* WADPOClockGatingDisable:hsw */
6052 I915_WRITE(_TRANSA_CHICKEN1
,
6053 I915_READ(_TRANSA_CHICKEN1
) |
6054 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
6057 static void lpt_suspend_hw(struct drm_device
*dev
)
6059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6061 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6062 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6064 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
6065 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6069 static void broadwell_init_clock_gating(struct drm_device
*dev
)
6071 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6074 I915_WRITE(WM3_LP_ILK
, 0);
6075 I915_WRITE(WM2_LP_ILK
, 0);
6076 I915_WRITE(WM1_LP_ILK
, 0);
6078 /* WaSwitchSolVfFArbitrationPriority:bdw */
6079 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
6081 /* WaPsrDPAMaskVBlankInSRD:bdw */
6082 I915_WRITE(CHICKEN_PAR1_1
,
6083 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
6085 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6086 for_each_pipe(dev_priv
, pipe
) {
6087 I915_WRITE(CHICKEN_PIPESL_1(pipe
),
6088 I915_READ(CHICKEN_PIPESL_1(pipe
)) |
6089 BDW_DPRS_MASK_VBLANK_SRD
);
6092 /* WaVSRefCountFullforceMissDisable:bdw */
6093 /* WaDSRefCountFullforceMissDisable:bdw */
6094 I915_WRITE(GEN7_FF_THREAD_MODE
,
6095 I915_READ(GEN7_FF_THREAD_MODE
) &
6096 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
6098 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
6099 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
6101 /* WaDisableSDEUnitClockGating:bdw */
6102 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
6103 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
6105 lpt_init_clock_gating(dev
);
6108 static void haswell_init_clock_gating(struct drm_device
*dev
)
6110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6112 ilk_init_lp_watermarks(dev
);
6114 /* L3 caching of data atomics doesn't work -- disable it. */
6115 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
6116 I915_WRITE(HSW_ROW_CHICKEN3
,
6117 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
6119 /* This is required by WaCatErrorRejectionIssue:hsw */
6120 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
6121 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
6122 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
6124 /* WaVSRefCountFullforceMissDisable:hsw */
6125 I915_WRITE(GEN7_FF_THREAD_MODE
,
6126 I915_READ(GEN7_FF_THREAD_MODE
) & ~GEN7_FF_VS_REF_CNT_FFME
);
6128 /* WaDisable_RenderCache_OperationalFlush:hsw */
6129 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6131 /* enable HiZ Raw Stall Optimization */
6132 I915_WRITE(CACHE_MODE_0_GEN7
,
6133 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
6135 /* WaDisable4x2SubspanOptimization:hsw */
6136 I915_WRITE(CACHE_MODE_1
,
6137 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
6140 * BSpec recommends 8x4 when MSAA is used,
6141 * however in practice 16x4 seems fastest.
6143 * Note that PS/WM thread counts depend on the WIZ hashing
6144 * disable bit, which we don't touch here, but it's good
6145 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6147 I915_WRITE(GEN7_GT_MODE
,
6148 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6150 /* WaSampleCChickenBitEnable:hsw */
6151 I915_WRITE(HALF_SLICE_CHICKEN3
,
6152 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE
));
6154 /* WaSwitchSolVfFArbitrationPriority:hsw */
6155 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
6157 /* WaRsPkgCStateDisplayPMReq:hsw */
6158 I915_WRITE(CHICKEN_PAR1_1
,
6159 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
6161 lpt_init_clock_gating(dev
);
6164 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
6166 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6169 ilk_init_lp_watermarks(dev
);
6171 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
6173 /* WaDisableEarlyCull:ivb */
6174 I915_WRITE(_3D_CHICKEN3
,
6175 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
6177 /* WaDisableBackToBackFlipFix:ivb */
6178 I915_WRITE(IVB_CHICKEN3
,
6179 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
6180 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
6182 /* WaDisablePSDDualDispatchEnable:ivb */
6183 if (IS_IVB_GT1(dev
))
6184 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
6185 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
6187 /* WaDisable_RenderCache_OperationalFlush:ivb */
6188 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6190 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6191 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
6192 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
6194 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6195 I915_WRITE(GEN7_L3CNTLREG1
,
6196 GEN7_WA_FOR_GEN7_L3_CONTROL
);
6197 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
6198 GEN7_WA_L3_CHICKEN_MODE
);
6199 if (IS_IVB_GT1(dev
))
6200 I915_WRITE(GEN7_ROW_CHICKEN2
,
6201 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6203 /* must write both registers */
6204 I915_WRITE(GEN7_ROW_CHICKEN2
,
6205 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6206 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
6207 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6210 /* WaForceL3Serialization:ivb */
6211 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
6212 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
6215 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6216 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6218 I915_WRITE(GEN6_UCGCTL2
,
6219 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
6221 /* This is required by WaCatErrorRejectionIssue:ivb */
6222 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
6223 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
6224 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
6226 g4x_disable_trickle_feed(dev
);
6228 gen7_setup_fixed_func_scheduler(dev_priv
);
6230 if (0) { /* causes HiZ corruption on ivb:gt1 */
6231 /* enable HiZ Raw Stall Optimization */
6232 I915_WRITE(CACHE_MODE_0_GEN7
,
6233 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
6236 /* WaDisable4x2SubspanOptimization:ivb */
6237 I915_WRITE(CACHE_MODE_1
,
6238 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
6241 * BSpec recommends 8x4 when MSAA is used,
6242 * however in practice 16x4 seems fastest.
6244 * Note that PS/WM thread counts depend on the WIZ hashing
6245 * disable bit, which we don't touch here, but it's good
6246 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6248 I915_WRITE(GEN7_GT_MODE
,
6249 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6251 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
6252 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
6253 snpcr
|= GEN6_MBC_SNPCR_MED
;
6254 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
6256 if (!HAS_PCH_NOP(dev
))
6257 cpt_init_clock_gating(dev
);
6259 gen6_check_mch_setup(dev
);
6262 static void valleyview_init_clock_gating(struct drm_device
*dev
)
6264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6266 I915_WRITE(DSPCLK_GATE_D
, VRHUNIT_CLOCK_GATE_DISABLE
);
6268 /* WaDisableEarlyCull:vlv */
6269 I915_WRITE(_3D_CHICKEN3
,
6270 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
6272 /* WaDisableBackToBackFlipFix:vlv */
6273 I915_WRITE(IVB_CHICKEN3
,
6274 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
6275 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
6277 /* WaPsdDispatchEnable:vlv */
6278 /* WaDisablePSDDualDispatchEnable:vlv */
6279 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
6280 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
6281 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
6283 /* WaDisable_RenderCache_OperationalFlush:vlv */
6284 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6286 /* WaForceL3Serialization:vlv */
6287 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
6288 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
6290 /* WaDisableDopClockGating:vlv */
6291 I915_WRITE(GEN7_ROW_CHICKEN2
,
6292 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6294 /* This is required by WaCatErrorRejectionIssue:vlv */
6295 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
6296 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
6297 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
6299 gen7_setup_fixed_func_scheduler(dev_priv
);
6302 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6303 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6305 I915_WRITE(GEN6_UCGCTL2
,
6306 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
6308 /* WaDisableL3Bank2xClockGate:vlv
6309 * Disabling L3 clock gating- MMIO 940c[25] = 1
6310 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6311 I915_WRITE(GEN7_UCGCTL4
,
6312 I915_READ(GEN7_UCGCTL4
) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
6314 I915_WRITE(MI_ARB_VLV
, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
);
6317 * BSpec says this must be set, even though
6318 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6320 I915_WRITE(CACHE_MODE_1
,
6321 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
6324 * BSpec recommends 8x4 when MSAA is used,
6325 * however in practice 16x4 seems fastest.
6327 * Note that PS/WM thread counts depend on the WIZ hashing
6328 * disable bit, which we don't touch here, but it's good
6329 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6331 I915_WRITE(GEN7_GT_MODE
,
6332 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6335 * WaIncreaseL3CreditsForVLVB0:vlv
6336 * This is the hardware default actually.
6338 I915_WRITE(GEN7_L3SQCREG1
, VLV_B0_WA_L3SQCREG1_VALUE
);
6341 * WaDisableVLVClockGating_VBIIssue:vlv
6342 * Disable clock gating on th GCFG unit to prevent a delay
6343 * in the reporting of vblank events.
6345 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, GCFG_DIS
);
6348 static void cherryview_init_clock_gating(struct drm_device
*dev
)
6350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6352 I915_WRITE(DSPCLK_GATE_D
, VRHUNIT_CLOCK_GATE_DISABLE
);
6354 I915_WRITE(MI_ARB_VLV
, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
);
6356 /* WaVSRefCountFullforceMissDisable:chv */
6357 /* WaDSRefCountFullforceMissDisable:chv */
6358 I915_WRITE(GEN7_FF_THREAD_MODE
,
6359 I915_READ(GEN7_FF_THREAD_MODE
) &
6360 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
6362 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6363 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
6364 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
6366 /* WaDisableCSUnitClockGating:chv */
6367 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
6368 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
6370 /* WaDisableSDEUnitClockGating:chv */
6371 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
6372 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
6375 static void g4x_init_clock_gating(struct drm_device
*dev
)
6377 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6378 uint32_t dspclk_gate
;
6380 I915_WRITE(RENCLK_GATE_D1
, 0);
6381 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
6382 GS_UNIT_CLOCK_GATE_DISABLE
|
6383 CL_UNIT_CLOCK_GATE_DISABLE
);
6384 I915_WRITE(RAMCLK_GATE_D
, 0);
6385 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
6386 OVRUNIT_CLOCK_GATE_DISABLE
|
6387 OVCUNIT_CLOCK_GATE_DISABLE
;
6389 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
6390 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
6392 /* WaDisableRenderCachePipelinedFlush */
6393 I915_WRITE(CACHE_MODE_0
,
6394 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
6396 /* WaDisable_RenderCache_OperationalFlush:g4x */
6397 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6399 g4x_disable_trickle_feed(dev
);
6402 static void crestline_init_clock_gating(struct drm_device
*dev
)
6404 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6406 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
6407 I915_WRITE(RENCLK_GATE_D2
, 0);
6408 I915_WRITE(DSPCLK_GATE_D
, 0);
6409 I915_WRITE(RAMCLK_GATE_D
, 0);
6410 I915_WRITE16(DEUC
, 0);
6411 I915_WRITE(MI_ARB_STATE
,
6412 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
6414 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6415 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6418 static void broadwater_init_clock_gating(struct drm_device
*dev
)
6420 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6422 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
6423 I965_RCC_CLOCK_GATE_DISABLE
|
6424 I965_RCPB_CLOCK_GATE_DISABLE
|
6425 I965_ISC_CLOCK_GATE_DISABLE
|
6426 I965_FBC_CLOCK_GATE_DISABLE
);
6427 I915_WRITE(RENCLK_GATE_D2
, 0);
6428 I915_WRITE(MI_ARB_STATE
,
6429 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
6431 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6432 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6435 static void gen3_init_clock_gating(struct drm_device
*dev
)
6437 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6438 u32 dstate
= I915_READ(D_STATE
);
6440 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
6441 DSTATE_DOT_CLOCK_GATING
;
6442 I915_WRITE(D_STATE
, dstate
);
6444 if (IS_PINEVIEW(dev
))
6445 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
6447 /* IIR "flip pending" means done if this bit is set */
6448 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
6450 /* interrupts should cause a wake up from C3 */
6451 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN
));
6453 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6454 I915_WRITE(MI_ARB_STATE
, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
6456 I915_WRITE(MI_ARB_STATE
,
6457 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
6460 static void i85x_init_clock_gating(struct drm_device
*dev
)
6462 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6464 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
6466 /* interrupts should cause a wake up from C3 */
6467 I915_WRITE(MI_STATE
, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN
) |
6468 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE
));
6470 I915_WRITE(MEM_MODE
,
6471 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE
));
6474 static void i830_init_clock_gating(struct drm_device
*dev
)
6476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6478 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
6480 I915_WRITE(MEM_MODE
,
6481 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE
) |
6482 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE
));
6485 void intel_init_clock_gating(struct drm_device
*dev
)
6487 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6489 if (dev_priv
->display
.init_clock_gating
)
6490 dev_priv
->display
.init_clock_gating(dev
);
6493 void intel_suspend_hw(struct drm_device
*dev
)
6495 if (HAS_PCH_LPT(dev
))
6496 lpt_suspend_hw(dev
);
6499 /* Set up chip specific power management-related functions */
6500 void intel_init_pm(struct drm_device
*dev
)
6502 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6504 intel_fbc_init(dev_priv
);
6507 if (IS_PINEVIEW(dev
))
6508 i915_pineview_get_mem_freq(dev
);
6509 else if (IS_GEN5(dev
))
6510 i915_ironlake_get_mem_freq(dev
);
6512 /* For FIFO watermark updates */
6513 if (INTEL_INFO(dev
)->gen
>= 9) {
6514 skl_setup_wm_latency(dev
);
6516 dev_priv
->display
.init_clock_gating
= skl_init_clock_gating
;
6517 dev_priv
->display
.update_wm
= skl_update_wm
;
6518 dev_priv
->display
.update_sprite_wm
= skl_update_sprite_wm
;
6519 } else if (HAS_PCH_SPLIT(dev
)) {
6520 ilk_setup_wm_latency(dev
);
6522 if ((IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[1] &&
6523 dev_priv
->wm
.spr_latency
[1] && dev_priv
->wm
.cur_latency
[1]) ||
6524 (!IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[0] &&
6525 dev_priv
->wm
.spr_latency
[0] && dev_priv
->wm
.cur_latency
[0])) {
6526 dev_priv
->display
.update_wm
= ilk_update_wm
;
6527 dev_priv
->display
.update_sprite_wm
= ilk_update_sprite_wm
;
6529 DRM_DEBUG_KMS("Failed to read display plane latency. "
6534 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
6535 else if (IS_GEN6(dev
))
6536 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
6537 else if (IS_IVYBRIDGE(dev
))
6538 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
6539 else if (IS_HASWELL(dev
))
6540 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
6541 else if (INTEL_INFO(dev
)->gen
== 8)
6542 dev_priv
->display
.init_clock_gating
= broadwell_init_clock_gating
;
6543 } else if (IS_CHERRYVIEW(dev
)) {
6544 dev_priv
->display
.update_wm
= cherryview_update_wm
;
6545 dev_priv
->display
.update_sprite_wm
= valleyview_update_sprite_wm
;
6546 dev_priv
->display
.init_clock_gating
=
6547 cherryview_init_clock_gating
;
6548 } else if (IS_VALLEYVIEW(dev
)) {
6549 dev_priv
->display
.update_wm
= valleyview_update_wm
;
6550 dev_priv
->display
.update_sprite_wm
= valleyview_update_sprite_wm
;
6551 dev_priv
->display
.init_clock_gating
=
6552 valleyview_init_clock_gating
;
6553 } else if (IS_PINEVIEW(dev
)) {
6554 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
6557 dev_priv
->mem_freq
)) {
6558 DRM_INFO("failed to find known CxSR latency "
6559 "(found ddr%s fsb freq %d, mem freq %d), "
6561 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
6562 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
6563 /* Disable CxSR and never update its watermark again */
6564 intel_set_memory_cxsr(dev_priv
, false);
6565 dev_priv
->display
.update_wm
= NULL
;
6567 dev_priv
->display
.update_wm
= pineview_update_wm
;
6568 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
6569 } else if (IS_G4X(dev
)) {
6570 dev_priv
->display
.update_wm
= g4x_update_wm
;
6571 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
6572 } else if (IS_GEN4(dev
)) {
6573 dev_priv
->display
.update_wm
= i965_update_wm
;
6574 if (IS_CRESTLINE(dev
))
6575 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
6576 else if (IS_BROADWATER(dev
))
6577 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
6578 } else if (IS_GEN3(dev
)) {
6579 dev_priv
->display
.update_wm
= i9xx_update_wm
;
6580 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
6581 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
6582 } else if (IS_GEN2(dev
)) {
6583 if (INTEL_INFO(dev
)->num_pipes
== 1) {
6584 dev_priv
->display
.update_wm
= i845_update_wm
;
6585 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
6587 dev_priv
->display
.update_wm
= i9xx_update_wm
;
6588 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
6591 if (IS_I85X(dev
) || IS_I865G(dev
))
6592 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
6594 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
6596 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
6600 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
)
6602 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6604 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
6605 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6609 I915_WRITE(GEN6_PCODE_DATA
, *val
);
6610 I915_WRITE(GEN6_PCODE_DATA1
, 0);
6611 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
6613 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6615 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
6619 *val
= I915_READ(GEN6_PCODE_DATA
);
6620 I915_WRITE(GEN6_PCODE_DATA
, 0);
6625 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
)
6627 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6629 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
6630 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6634 I915_WRITE(GEN6_PCODE_DATA
, val
);
6635 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
6637 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6639 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
6643 I915_WRITE(GEN6_PCODE_DATA
, 0);
6648 static int vlv_gpu_freq_div(unsigned int czclk_freq
)
6650 switch (czclk_freq
) {
6665 static int byt_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
6667 int div
, czclk_freq
= DIV_ROUND_CLOSEST(dev_priv
->mem_freq
, 4);
6669 div
= vlv_gpu_freq_div(czclk_freq
);
6673 return DIV_ROUND_CLOSEST(czclk_freq
* (val
+ 6 - 0xbd), div
);
6676 static int byt_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
6678 int mul
, czclk_freq
= DIV_ROUND_CLOSEST(dev_priv
->mem_freq
, 4);
6680 mul
= vlv_gpu_freq_div(czclk_freq
);
6684 return DIV_ROUND_CLOSEST(mul
* val
, czclk_freq
) + 0xbd - 6;
6687 static int chv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
6689 int div
, czclk_freq
= dev_priv
->rps
.cz_freq
;
6691 div
= vlv_gpu_freq_div(czclk_freq
) / 2;
6695 return DIV_ROUND_CLOSEST(czclk_freq
* val
, 2 * div
) / 2;
6698 static int chv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
6700 int mul
, czclk_freq
= dev_priv
->rps
.cz_freq
;
6702 mul
= vlv_gpu_freq_div(czclk_freq
) / 2;
6706 /* CHV needs even values */
6707 return DIV_ROUND_CLOSEST(val
* 2 * mul
, czclk_freq
) * 2;
6710 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
6712 if (IS_CHERRYVIEW(dev_priv
->dev
))
6713 return chv_gpu_freq(dev_priv
, val
);
6714 else if (IS_VALLEYVIEW(dev_priv
->dev
))
6715 return byt_gpu_freq(dev_priv
, val
);
6717 return val
* GT_FREQUENCY_MULTIPLIER
;
6720 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
6722 if (IS_CHERRYVIEW(dev_priv
->dev
))
6723 return chv_freq_opcode(dev_priv
, val
);
6724 else if (IS_VALLEYVIEW(dev_priv
->dev
))
6725 return byt_freq_opcode(dev_priv
, val
);
6727 return val
/ GT_FREQUENCY_MULTIPLIER
;
6730 void intel_pm_setup(struct drm_device
*dev
)
6732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6734 mutex_init(&dev_priv
->rps
.hw_lock
);
6736 INIT_DELAYED_WORK(&dev_priv
->rps
.delayed_resume_work
,
6737 intel_gen6_powersave_work
);
6739 dev_priv
->pm
.suspended
= false;