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drm/i915: Store the requested frequency whilst RPS is disabled
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include <drm/drm_plane_helper.h>
30 #include "i915_drv.h"
31 #include "intel_drv.h"
32 #include "../../../platform/x86/intel_ips.h"
33 #include <linux/module.h>
34 #include <drm/drm_atomic_helper.h>
35
36 /**
37 * DOC: RC6
38 *
39 * RC6 is a special power stage which allows the GPU to enter an very
40 * low-voltage mode when idle, using down to 0V while at this stage. This
41 * stage is entered automatically when the GPU is idle when RC6 support is
42 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 *
44 * There are different RC6 modes available in Intel GPU, which differentiate
45 * among each other with the latency required to enter and leave RC6 and
46 * voltage consumed by the GPU in different states.
47 *
48 * The combination of the following flags define which states GPU is allowed
49 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
50 * RC6pp is deepest RC6. Their support by hardware varies according to the
51 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
52 * which brings the most power savings; deeper states save more power, but
53 * require higher latency to switch to and wake up.
54 */
55 #define INTEL_RC6_ENABLE (1<<0)
56 #define INTEL_RC6p_ENABLE (1<<1)
57 #define INTEL_RC6pp_ENABLE (1<<2)
58
59 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
60 {
61 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
62 I915_WRITE(CHICKEN_PAR1_1,
63 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
64
65 I915_WRITE(GEN8_CONFIG0,
66 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
67
68 /* WaEnableChickenDCPR:skl,bxt,kbl,glk */
69 I915_WRITE(GEN8_CHICKEN_DCPR_1,
70 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
71
72 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
73 /* WaFbcWakeMemOn:skl,bxt,kbl,glk */
74 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
75 DISP_FBC_WM_DIS |
76 DISP_FBC_MEMORY_WAKE);
77
78 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
79 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
80 ILK_DPFC_DISABLE_DUMMY0);
81 }
82
83 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
84 {
85 gen9_init_clock_gating(dev_priv);
86
87 /* WaDisableSDEUnitClockGating:bxt */
88 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
89 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
90
91 /*
92 * FIXME:
93 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
94 */
95 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
96 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
97
98 /*
99 * Wa: Backlight PWM may stop in the asserted state, causing backlight
100 * to stay fully on.
101 */
102 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
103 PWM1_GATING_DIS | PWM2_GATING_DIS);
104 }
105
106 static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
107 {
108 gen9_init_clock_gating(dev_priv);
109
110 /*
111 * WaDisablePWMClockGating:glk
112 * Backlight PWM may stop in the asserted state, causing backlight
113 * to stay fully on.
114 */
115 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
116 PWM1_GATING_DIS | PWM2_GATING_DIS);
117 }
118
119 static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
120 {
121 u32 tmp;
122
123 tmp = I915_READ(CLKCFG);
124
125 switch (tmp & CLKCFG_FSB_MASK) {
126 case CLKCFG_FSB_533:
127 dev_priv->fsb_freq = 533; /* 133*4 */
128 break;
129 case CLKCFG_FSB_800:
130 dev_priv->fsb_freq = 800; /* 200*4 */
131 break;
132 case CLKCFG_FSB_667:
133 dev_priv->fsb_freq = 667; /* 167*4 */
134 break;
135 case CLKCFG_FSB_400:
136 dev_priv->fsb_freq = 400; /* 100*4 */
137 break;
138 }
139
140 switch (tmp & CLKCFG_MEM_MASK) {
141 case CLKCFG_MEM_533:
142 dev_priv->mem_freq = 533;
143 break;
144 case CLKCFG_MEM_667:
145 dev_priv->mem_freq = 667;
146 break;
147 case CLKCFG_MEM_800:
148 dev_priv->mem_freq = 800;
149 break;
150 }
151
152 /* detect pineview DDR3 setting */
153 tmp = I915_READ(CSHRDDR3CTL);
154 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
155 }
156
157 static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
158 {
159 u16 ddrpll, csipll;
160
161 ddrpll = I915_READ16(DDRMPLL1);
162 csipll = I915_READ16(CSIPLL0);
163
164 switch (ddrpll & 0xff) {
165 case 0xc:
166 dev_priv->mem_freq = 800;
167 break;
168 case 0x10:
169 dev_priv->mem_freq = 1066;
170 break;
171 case 0x14:
172 dev_priv->mem_freq = 1333;
173 break;
174 case 0x18:
175 dev_priv->mem_freq = 1600;
176 break;
177 default:
178 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
179 ddrpll & 0xff);
180 dev_priv->mem_freq = 0;
181 break;
182 }
183
184 dev_priv->ips.r_t = dev_priv->mem_freq;
185
186 switch (csipll & 0x3ff) {
187 case 0x00c:
188 dev_priv->fsb_freq = 3200;
189 break;
190 case 0x00e:
191 dev_priv->fsb_freq = 3733;
192 break;
193 case 0x010:
194 dev_priv->fsb_freq = 4266;
195 break;
196 case 0x012:
197 dev_priv->fsb_freq = 4800;
198 break;
199 case 0x014:
200 dev_priv->fsb_freq = 5333;
201 break;
202 case 0x016:
203 dev_priv->fsb_freq = 5866;
204 break;
205 case 0x018:
206 dev_priv->fsb_freq = 6400;
207 break;
208 default:
209 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
210 csipll & 0x3ff);
211 dev_priv->fsb_freq = 0;
212 break;
213 }
214
215 if (dev_priv->fsb_freq == 3200) {
216 dev_priv->ips.c_m = 0;
217 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
218 dev_priv->ips.c_m = 1;
219 } else {
220 dev_priv->ips.c_m = 2;
221 }
222 }
223
224 static const struct cxsr_latency cxsr_latency_table[] = {
225 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
226 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
227 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
228 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
229 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
230
231 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
232 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
233 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
234 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
235 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
236
237 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
238 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
239 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
240 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
241 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
242
243 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
244 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
245 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
246 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
247 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
248
249 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
250 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
251 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
252 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
253 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
254
255 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
256 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
257 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
258 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
259 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
260 };
261
262 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
263 bool is_ddr3,
264 int fsb,
265 int mem)
266 {
267 const struct cxsr_latency *latency;
268 int i;
269
270 if (fsb == 0 || mem == 0)
271 return NULL;
272
273 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
274 latency = &cxsr_latency_table[i];
275 if (is_desktop == latency->is_desktop &&
276 is_ddr3 == latency->is_ddr3 &&
277 fsb == latency->fsb_freq && mem == latency->mem_freq)
278 return latency;
279 }
280
281 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
282
283 return NULL;
284 }
285
286 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
287 {
288 u32 val;
289
290 mutex_lock(&dev_priv->rps.hw_lock);
291
292 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
293 if (enable)
294 val &= ~FORCE_DDR_HIGH_FREQ;
295 else
296 val |= FORCE_DDR_HIGH_FREQ;
297 val &= ~FORCE_DDR_LOW_FREQ;
298 val |= FORCE_DDR_FREQ_REQ_ACK;
299 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
300
301 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
302 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
303 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
304
305 mutex_unlock(&dev_priv->rps.hw_lock);
306 }
307
308 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
309 {
310 u32 val;
311
312 mutex_lock(&dev_priv->rps.hw_lock);
313
314 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
315 if (enable)
316 val |= DSP_MAXFIFO_PM5_ENABLE;
317 else
318 val &= ~DSP_MAXFIFO_PM5_ENABLE;
319 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
320
321 mutex_unlock(&dev_priv->rps.hw_lock);
322 }
323
324 #define FW_WM(value, plane) \
325 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
326
327 static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
328 {
329 bool was_enabled;
330 u32 val;
331
332 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
333 was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
334 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
335 POSTING_READ(FW_BLC_SELF_VLV);
336 } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
337 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
338 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
339 POSTING_READ(FW_BLC_SELF);
340 } else if (IS_PINEVIEW(dev_priv)) {
341 val = I915_READ(DSPFW3);
342 was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
343 if (enable)
344 val |= PINEVIEW_SELF_REFRESH_EN;
345 else
346 val &= ~PINEVIEW_SELF_REFRESH_EN;
347 I915_WRITE(DSPFW3, val);
348 POSTING_READ(DSPFW3);
349 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
350 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
351 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
352 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
353 I915_WRITE(FW_BLC_SELF, val);
354 POSTING_READ(FW_BLC_SELF);
355 } else if (IS_I915GM(dev_priv)) {
356 /*
357 * FIXME can't find a bit like this for 915G, and
358 * and yet it does have the related watermark in
359 * FW_BLC_SELF. What's going on?
360 */
361 was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
362 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
363 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
364 I915_WRITE(INSTPM, val);
365 POSTING_READ(INSTPM);
366 } else {
367 return false;
368 }
369
370 DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
371 enableddisabled(enable),
372 enableddisabled(was_enabled));
373
374 return was_enabled;
375 }
376
377 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
378 {
379 bool ret;
380
381 mutex_lock(&dev_priv->wm.wm_mutex);
382 ret = _intel_set_memory_cxsr(dev_priv, enable);
383 dev_priv->wm.vlv.cxsr = enable;
384 mutex_unlock(&dev_priv->wm.wm_mutex);
385
386 return ret;
387 }
388
389 /*
390 * Latency for FIFO fetches is dependent on several factors:
391 * - memory configuration (speed, channels)
392 * - chipset
393 * - current MCH state
394 * It can be fairly high in some situations, so here we assume a fairly
395 * pessimal value. It's a tradeoff between extra memory fetches (if we
396 * set this value too high, the FIFO will fetch frequently to stay full)
397 * and power consumption (set it too low to save power and we might see
398 * FIFO underruns and display "flicker").
399 *
400 * A value of 5us seems to be a good balance; safe for very low end
401 * platforms but not overly aggressive on lower latency configs.
402 */
403 static const int pessimal_latency_ns = 5000;
404
405 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
406 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
407
408 static int vlv_get_fifo_size(struct intel_plane *plane)
409 {
410 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
411 int sprite0_start, sprite1_start, size;
412
413 if (plane->id == PLANE_CURSOR)
414 return 63;
415
416 switch (plane->pipe) {
417 uint32_t dsparb, dsparb2, dsparb3;
418 case PIPE_A:
419 dsparb = I915_READ(DSPARB);
420 dsparb2 = I915_READ(DSPARB2);
421 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
422 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
423 break;
424 case PIPE_B:
425 dsparb = I915_READ(DSPARB);
426 dsparb2 = I915_READ(DSPARB2);
427 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
428 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
429 break;
430 case PIPE_C:
431 dsparb2 = I915_READ(DSPARB2);
432 dsparb3 = I915_READ(DSPARB3);
433 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
434 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
435 break;
436 default:
437 return 0;
438 }
439
440 switch (plane->id) {
441 case PLANE_PRIMARY:
442 size = sprite0_start;
443 break;
444 case PLANE_SPRITE0:
445 size = sprite1_start - sprite0_start;
446 break;
447 case PLANE_SPRITE1:
448 size = 512 - 1 - sprite1_start;
449 break;
450 default:
451 return 0;
452 }
453
454 DRM_DEBUG_KMS("%s FIFO size: %d\n", plane->base.name, size);
455
456 return size;
457 }
458
459 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
460 {
461 uint32_t dsparb = I915_READ(DSPARB);
462 int size;
463
464 size = dsparb & 0x7f;
465 if (plane)
466 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
467
468 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
469 plane ? "B" : "A", size);
470
471 return size;
472 }
473
474 static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
475 {
476 uint32_t dsparb = I915_READ(DSPARB);
477 int size;
478
479 size = dsparb & 0x1ff;
480 if (plane)
481 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
482 size >>= 1; /* Convert to cachelines */
483
484 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
485 plane ? "B" : "A", size);
486
487 return size;
488 }
489
490 static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
491 {
492 uint32_t dsparb = I915_READ(DSPARB);
493 int size;
494
495 size = dsparb & 0x7f;
496 size >>= 2; /* Convert to cachelines */
497
498 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
499 plane ? "B" : "A",
500 size);
501
502 return size;
503 }
504
505 /* Pineview has different values for various configs */
506 static const struct intel_watermark_params pineview_display_wm = {
507 .fifo_size = PINEVIEW_DISPLAY_FIFO,
508 .max_wm = PINEVIEW_MAX_WM,
509 .default_wm = PINEVIEW_DFT_WM,
510 .guard_size = PINEVIEW_GUARD_WM,
511 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
512 };
513 static const struct intel_watermark_params pineview_display_hplloff_wm = {
514 .fifo_size = PINEVIEW_DISPLAY_FIFO,
515 .max_wm = PINEVIEW_MAX_WM,
516 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
517 .guard_size = PINEVIEW_GUARD_WM,
518 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
519 };
520 static const struct intel_watermark_params pineview_cursor_wm = {
521 .fifo_size = PINEVIEW_CURSOR_FIFO,
522 .max_wm = PINEVIEW_CURSOR_MAX_WM,
523 .default_wm = PINEVIEW_CURSOR_DFT_WM,
524 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
525 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
526 };
527 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
528 .fifo_size = PINEVIEW_CURSOR_FIFO,
529 .max_wm = PINEVIEW_CURSOR_MAX_WM,
530 .default_wm = PINEVIEW_CURSOR_DFT_WM,
531 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
532 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
533 };
534 static const struct intel_watermark_params g4x_wm_info = {
535 .fifo_size = G4X_FIFO_SIZE,
536 .max_wm = G4X_MAX_WM,
537 .default_wm = G4X_MAX_WM,
538 .guard_size = 2,
539 .cacheline_size = G4X_FIFO_LINE_SIZE,
540 };
541 static const struct intel_watermark_params g4x_cursor_wm_info = {
542 .fifo_size = I965_CURSOR_FIFO,
543 .max_wm = I965_CURSOR_MAX_WM,
544 .default_wm = I965_CURSOR_DFT_WM,
545 .guard_size = 2,
546 .cacheline_size = G4X_FIFO_LINE_SIZE,
547 };
548 static const struct intel_watermark_params i965_cursor_wm_info = {
549 .fifo_size = I965_CURSOR_FIFO,
550 .max_wm = I965_CURSOR_MAX_WM,
551 .default_wm = I965_CURSOR_DFT_WM,
552 .guard_size = 2,
553 .cacheline_size = I915_FIFO_LINE_SIZE,
554 };
555 static const struct intel_watermark_params i945_wm_info = {
556 .fifo_size = I945_FIFO_SIZE,
557 .max_wm = I915_MAX_WM,
558 .default_wm = 1,
559 .guard_size = 2,
560 .cacheline_size = I915_FIFO_LINE_SIZE,
561 };
562 static const struct intel_watermark_params i915_wm_info = {
563 .fifo_size = I915_FIFO_SIZE,
564 .max_wm = I915_MAX_WM,
565 .default_wm = 1,
566 .guard_size = 2,
567 .cacheline_size = I915_FIFO_LINE_SIZE,
568 };
569 static const struct intel_watermark_params i830_a_wm_info = {
570 .fifo_size = I855GM_FIFO_SIZE,
571 .max_wm = I915_MAX_WM,
572 .default_wm = 1,
573 .guard_size = 2,
574 .cacheline_size = I830_FIFO_LINE_SIZE,
575 };
576 static const struct intel_watermark_params i830_bc_wm_info = {
577 .fifo_size = I855GM_FIFO_SIZE,
578 .max_wm = I915_MAX_WM/2,
579 .default_wm = 1,
580 .guard_size = 2,
581 .cacheline_size = I830_FIFO_LINE_SIZE,
582 };
583 static const struct intel_watermark_params i845_wm_info = {
584 .fifo_size = I830_FIFO_SIZE,
585 .max_wm = I915_MAX_WM,
586 .default_wm = 1,
587 .guard_size = 2,
588 .cacheline_size = I830_FIFO_LINE_SIZE,
589 };
590
591 /**
592 * intel_calculate_wm - calculate watermark level
593 * @clock_in_khz: pixel clock
594 * @wm: chip FIFO params
595 * @cpp: bytes per pixel
596 * @latency_ns: memory latency for the platform
597 *
598 * Calculate the watermark level (the level at which the display plane will
599 * start fetching from memory again). Each chip has a different display
600 * FIFO size and allocation, so the caller needs to figure that out and pass
601 * in the correct intel_watermark_params structure.
602 *
603 * As the pixel clock runs, the FIFO will be drained at a rate that depends
604 * on the pixel size. When it reaches the watermark level, it'll start
605 * fetching FIFO line sized based chunks from memory until the FIFO fills
606 * past the watermark point. If the FIFO drains completely, a FIFO underrun
607 * will occur, and a display engine hang could result.
608 */
609 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
610 const struct intel_watermark_params *wm,
611 int fifo_size, int cpp,
612 unsigned long latency_ns)
613 {
614 long entries_required, wm_size;
615
616 /*
617 * Note: we need to make sure we don't overflow for various clock &
618 * latency values.
619 * clocks go from a few thousand to several hundred thousand.
620 * latency is usually a few thousand
621 */
622 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
623 1000;
624 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
625
626 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
627
628 wm_size = fifo_size - (entries_required + wm->guard_size);
629
630 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
631
632 /* Don't promote wm_size to unsigned... */
633 if (wm_size > (long)wm->max_wm)
634 wm_size = wm->max_wm;
635 if (wm_size <= 0)
636 wm_size = wm->default_wm;
637
638 /*
639 * Bspec seems to indicate that the value shouldn't be lower than
640 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
641 * Lets go for 8 which is the burst size since certain platforms
642 * already use a hardcoded 8 (which is what the spec says should be
643 * done).
644 */
645 if (wm_size <= 8)
646 wm_size = 8;
647
648 return wm_size;
649 }
650
651 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
652 {
653 struct intel_crtc *crtc, *enabled = NULL;
654
655 for_each_intel_crtc(&dev_priv->drm, crtc) {
656 if (intel_crtc_active(crtc)) {
657 if (enabled)
658 return NULL;
659 enabled = crtc;
660 }
661 }
662
663 return enabled;
664 }
665
666 static void pineview_update_wm(struct intel_crtc *unused_crtc)
667 {
668 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
669 struct intel_crtc *crtc;
670 const struct cxsr_latency *latency;
671 u32 reg;
672 unsigned long wm;
673
674 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
675 dev_priv->is_ddr3,
676 dev_priv->fsb_freq,
677 dev_priv->mem_freq);
678 if (!latency) {
679 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
680 intel_set_memory_cxsr(dev_priv, false);
681 return;
682 }
683
684 crtc = single_enabled_crtc(dev_priv);
685 if (crtc) {
686 const struct drm_display_mode *adjusted_mode =
687 &crtc->config->base.adjusted_mode;
688 const struct drm_framebuffer *fb =
689 crtc->base.primary->state->fb;
690 int cpp = fb->format->cpp[0];
691 int clock = adjusted_mode->crtc_clock;
692
693 /* Display SR */
694 wm = intel_calculate_wm(clock, &pineview_display_wm,
695 pineview_display_wm.fifo_size,
696 cpp, latency->display_sr);
697 reg = I915_READ(DSPFW1);
698 reg &= ~DSPFW_SR_MASK;
699 reg |= FW_WM(wm, SR);
700 I915_WRITE(DSPFW1, reg);
701 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
702
703 /* cursor SR */
704 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
705 pineview_display_wm.fifo_size,
706 cpp, latency->cursor_sr);
707 reg = I915_READ(DSPFW3);
708 reg &= ~DSPFW_CURSOR_SR_MASK;
709 reg |= FW_WM(wm, CURSOR_SR);
710 I915_WRITE(DSPFW3, reg);
711
712 /* Display HPLL off SR */
713 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
714 pineview_display_hplloff_wm.fifo_size,
715 cpp, latency->display_hpll_disable);
716 reg = I915_READ(DSPFW3);
717 reg &= ~DSPFW_HPLL_SR_MASK;
718 reg |= FW_WM(wm, HPLL_SR);
719 I915_WRITE(DSPFW3, reg);
720
721 /* cursor HPLL off SR */
722 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
723 pineview_display_hplloff_wm.fifo_size,
724 cpp, latency->cursor_hpll_disable);
725 reg = I915_READ(DSPFW3);
726 reg &= ~DSPFW_HPLL_CURSOR_MASK;
727 reg |= FW_WM(wm, HPLL_CURSOR);
728 I915_WRITE(DSPFW3, reg);
729 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
730
731 intel_set_memory_cxsr(dev_priv, true);
732 } else {
733 intel_set_memory_cxsr(dev_priv, false);
734 }
735 }
736
737 static bool g4x_compute_wm0(struct drm_i915_private *dev_priv,
738 int plane,
739 const struct intel_watermark_params *display,
740 int display_latency_ns,
741 const struct intel_watermark_params *cursor,
742 int cursor_latency_ns,
743 int *plane_wm,
744 int *cursor_wm)
745 {
746 struct intel_crtc *crtc;
747 const struct drm_display_mode *adjusted_mode;
748 const struct drm_framebuffer *fb;
749 int htotal, hdisplay, clock, cpp;
750 int line_time_us, line_count;
751 int entries, tlb_miss;
752
753 crtc = intel_get_crtc_for_plane(dev_priv, plane);
754 if (!intel_crtc_active(crtc)) {
755 *cursor_wm = cursor->guard_size;
756 *plane_wm = display->guard_size;
757 return false;
758 }
759
760 adjusted_mode = &crtc->config->base.adjusted_mode;
761 fb = crtc->base.primary->state->fb;
762 clock = adjusted_mode->crtc_clock;
763 htotal = adjusted_mode->crtc_htotal;
764 hdisplay = crtc->config->pipe_src_w;
765 cpp = fb->format->cpp[0];
766
767 /* Use the small buffer method to calculate plane watermark */
768 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
769 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
770 if (tlb_miss > 0)
771 entries += tlb_miss;
772 entries = DIV_ROUND_UP(entries, display->cacheline_size);
773 *plane_wm = entries + display->guard_size;
774 if (*plane_wm > (int)display->max_wm)
775 *plane_wm = display->max_wm;
776
777 /* Use the large buffer method to calculate cursor watermark */
778 line_time_us = max(htotal * 1000 / clock, 1);
779 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
780 entries = line_count * crtc->base.cursor->state->crtc_w * cpp;
781 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
782 if (tlb_miss > 0)
783 entries += tlb_miss;
784 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
785 *cursor_wm = entries + cursor->guard_size;
786 if (*cursor_wm > (int)cursor->max_wm)
787 *cursor_wm = (int)cursor->max_wm;
788
789 return true;
790 }
791
792 /*
793 * Check the wm result.
794 *
795 * If any calculated watermark values is larger than the maximum value that
796 * can be programmed into the associated watermark register, that watermark
797 * must be disabled.
798 */
799 static bool g4x_check_srwm(struct drm_i915_private *dev_priv,
800 int display_wm, int cursor_wm,
801 const struct intel_watermark_params *display,
802 const struct intel_watermark_params *cursor)
803 {
804 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
805 display_wm, cursor_wm);
806
807 if (display_wm > display->max_wm) {
808 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
809 display_wm, display->max_wm);
810 return false;
811 }
812
813 if (cursor_wm > cursor->max_wm) {
814 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
815 cursor_wm, cursor->max_wm);
816 return false;
817 }
818
819 if (!(display_wm || cursor_wm)) {
820 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
821 return false;
822 }
823
824 return true;
825 }
826
827 static bool g4x_compute_srwm(struct drm_i915_private *dev_priv,
828 int plane,
829 int latency_ns,
830 const struct intel_watermark_params *display,
831 const struct intel_watermark_params *cursor,
832 int *display_wm, int *cursor_wm)
833 {
834 struct intel_crtc *crtc;
835 const struct drm_display_mode *adjusted_mode;
836 const struct drm_framebuffer *fb;
837 int hdisplay, htotal, cpp, clock;
838 unsigned long line_time_us;
839 int line_count, line_size;
840 int small, large;
841 int entries;
842
843 if (!latency_ns) {
844 *display_wm = *cursor_wm = 0;
845 return false;
846 }
847
848 crtc = intel_get_crtc_for_plane(dev_priv, plane);
849 adjusted_mode = &crtc->config->base.adjusted_mode;
850 fb = crtc->base.primary->state->fb;
851 clock = adjusted_mode->crtc_clock;
852 htotal = adjusted_mode->crtc_htotal;
853 hdisplay = crtc->config->pipe_src_w;
854 cpp = fb->format->cpp[0];
855
856 line_time_us = max(htotal * 1000 / clock, 1);
857 line_count = (latency_ns / line_time_us + 1000) / 1000;
858 line_size = hdisplay * cpp;
859
860 /* Use the minimum of the small and large buffer method for primary */
861 small = ((clock * cpp / 1000) * latency_ns) / 1000;
862 large = line_count * line_size;
863
864 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
865 *display_wm = entries + display->guard_size;
866
867 /* calculate the self-refresh watermark for display cursor */
868 entries = line_count * cpp * crtc->base.cursor->state->crtc_w;
869 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
870 *cursor_wm = entries + cursor->guard_size;
871
872 return g4x_check_srwm(dev_priv,
873 *display_wm, *cursor_wm,
874 display, cursor);
875 }
876
877 #define FW_WM_VLV(value, plane) \
878 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
879
880 static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
881 const struct vlv_wm_values *wm)
882 {
883 enum pipe pipe;
884
885 for_each_pipe(dev_priv, pipe) {
886 I915_WRITE(VLV_DDL(pipe),
887 (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
888 (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
889 (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
890 (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
891 }
892
893 /*
894 * Zero the (unused) WM1 watermarks, and also clear all the
895 * high order bits so that there are no out of bounds values
896 * present in the registers during the reprogramming.
897 */
898 I915_WRITE(DSPHOWM, 0);
899 I915_WRITE(DSPHOWM1, 0);
900 I915_WRITE(DSPFW4, 0);
901 I915_WRITE(DSPFW5, 0);
902 I915_WRITE(DSPFW6, 0);
903
904 I915_WRITE(DSPFW1,
905 FW_WM(wm->sr.plane, SR) |
906 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
907 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
908 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
909 I915_WRITE(DSPFW2,
910 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
911 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
912 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
913 I915_WRITE(DSPFW3,
914 FW_WM(wm->sr.cursor, CURSOR_SR));
915
916 if (IS_CHERRYVIEW(dev_priv)) {
917 I915_WRITE(DSPFW7_CHV,
918 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
919 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
920 I915_WRITE(DSPFW8_CHV,
921 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
922 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
923 I915_WRITE(DSPFW9_CHV,
924 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
925 FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
926 I915_WRITE(DSPHOWM,
927 FW_WM(wm->sr.plane >> 9, SR_HI) |
928 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
929 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
930 FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
931 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
932 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
933 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
934 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
935 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
936 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
937 } else {
938 I915_WRITE(DSPFW7,
939 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
940 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
941 I915_WRITE(DSPHOWM,
942 FW_WM(wm->sr.plane >> 9, SR_HI) |
943 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
944 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
945 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
946 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
947 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
948 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
949 }
950
951 POSTING_READ(DSPFW1);
952 }
953
954 #undef FW_WM_VLV
955
956 enum vlv_wm_level {
957 VLV_WM_LEVEL_PM2,
958 VLV_WM_LEVEL_PM5,
959 VLV_WM_LEVEL_DDR_DVFS,
960 };
961
962 /* latency must be in 0.1us units. */
963 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
964 unsigned int pipe_htotal,
965 unsigned int horiz_pixels,
966 unsigned int cpp,
967 unsigned int latency)
968 {
969 unsigned int ret;
970
971 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
972 ret = (ret + 1) * horiz_pixels * cpp;
973 ret = DIV_ROUND_UP(ret, 64);
974
975 return ret;
976 }
977
978 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
979 {
980 /* all latencies in usec */
981 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
982
983 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
984
985 if (IS_CHERRYVIEW(dev_priv)) {
986 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
987 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
988
989 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
990 }
991 }
992
993 static uint16_t vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
994 const struct intel_plane_state *plane_state,
995 int level)
996 {
997 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
998 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
999 const struct drm_display_mode *adjusted_mode =
1000 &crtc_state->base.adjusted_mode;
1001 int clock, htotal, cpp, width, wm;
1002
1003 if (dev_priv->wm.pri_latency[level] == 0)
1004 return USHRT_MAX;
1005
1006 if (!plane_state->base.visible)
1007 return 0;
1008
1009 cpp = plane_state->base.fb->format->cpp[0];
1010 clock = adjusted_mode->crtc_clock;
1011 htotal = adjusted_mode->crtc_htotal;
1012 width = crtc_state->pipe_src_w;
1013 if (WARN_ON(htotal == 0))
1014 htotal = 1;
1015
1016 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1017 /*
1018 * FIXME the formula gives values that are
1019 * too big for the cursor FIFO, and hence we
1020 * would never be able to use cursors. For
1021 * now just hardcode the watermark.
1022 */
1023 wm = 63;
1024 } else {
1025 wm = vlv_wm_method2(clock, htotal, width, cpp,
1026 dev_priv->wm.pri_latency[level] * 10);
1027 }
1028
1029 return min_t(int, wm, USHRT_MAX);
1030 }
1031
1032 static void vlv_compute_fifo(struct intel_crtc *crtc)
1033 {
1034 struct drm_device *dev = crtc->base.dev;
1035 struct vlv_wm_state *wm_state = &crtc->wm_state;
1036 struct intel_plane *plane;
1037 unsigned int total_rate = 0;
1038 const int fifo_size = 512 - 1;
1039 int fifo_extra, fifo_left = fifo_size;
1040
1041 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1042 struct intel_plane_state *state =
1043 to_intel_plane_state(plane->base.state);
1044
1045 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1046 continue;
1047
1048 if (state->base.visible) {
1049 wm_state->num_active_planes++;
1050 total_rate += state->base.fb->format->cpp[0];
1051 }
1052 }
1053
1054 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1055 struct intel_plane_state *state =
1056 to_intel_plane_state(plane->base.state);
1057 unsigned int rate;
1058
1059 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1060 plane->wm.fifo_size = 63;
1061 continue;
1062 }
1063
1064 if (!state->base.visible) {
1065 plane->wm.fifo_size = 0;
1066 continue;
1067 }
1068
1069 rate = state->base.fb->format->cpp[0];
1070 plane->wm.fifo_size = fifo_size * rate / total_rate;
1071 fifo_left -= plane->wm.fifo_size;
1072 }
1073
1074 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1075
1076 /* spread the remainder evenly */
1077 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1078 int plane_extra;
1079
1080 if (fifo_left == 0)
1081 break;
1082
1083 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1084 continue;
1085
1086 /* give it all to the first plane if none are active */
1087 if (plane->wm.fifo_size == 0 &&
1088 wm_state->num_active_planes)
1089 continue;
1090
1091 plane_extra = min(fifo_extra, fifo_left);
1092 plane->wm.fifo_size += plane_extra;
1093 fifo_left -= plane_extra;
1094 }
1095
1096 WARN_ON(fifo_left != 0);
1097 }
1098
1099 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1100 {
1101 if (wm > fifo_size)
1102 return USHRT_MAX;
1103 else
1104 return fifo_size - wm;
1105 }
1106
1107 static void vlv_invert_wms(struct intel_crtc *crtc)
1108 {
1109 struct vlv_wm_state *wm_state = &crtc->wm_state;
1110 int level;
1111
1112 for (level = 0; level < wm_state->num_levels; level++) {
1113 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1114 const int sr_fifo_size =
1115 INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1116 struct intel_plane *plane;
1117
1118 wm_state->sr[level].plane =
1119 vlv_invert_wm_value(wm_state->sr[level].plane,
1120 sr_fifo_size);
1121 wm_state->sr[level].cursor =
1122 vlv_invert_wm_value(wm_state->sr[level].cursor,
1123 63);
1124
1125 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
1126 wm_state->wm[level].plane[plane->id] =
1127 vlv_invert_wm_value(wm_state->wm[level].plane[plane->id],
1128 plane->wm.fifo_size);
1129 }
1130 }
1131 }
1132
1133 static void vlv_compute_wm(struct intel_crtc *crtc)
1134 {
1135 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1136 struct vlv_wm_state *wm_state = &crtc->wm_state;
1137 struct intel_plane *plane;
1138 int level;
1139
1140 memset(wm_state, 0, sizeof(*wm_state));
1141
1142 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1143 wm_state->num_levels = dev_priv->wm.max_level + 1;
1144
1145 wm_state->num_active_planes = 0;
1146
1147 vlv_compute_fifo(crtc);
1148
1149 if (wm_state->num_active_planes != 1)
1150 wm_state->cxsr = false;
1151
1152 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
1153 struct intel_plane_state *state =
1154 to_intel_plane_state(plane->base.state);
1155 int level;
1156
1157 if (!state->base.visible)
1158 continue;
1159
1160 /* normal watermarks */
1161 for (level = 0; level < wm_state->num_levels; level++) {
1162 int wm = vlv_compute_wm_level(crtc->config, state, level);
1163 int max_wm = plane->wm.fifo_size;
1164
1165 /* hack */
1166 if (WARN_ON(level == 0 && wm > max_wm))
1167 wm = max_wm;
1168
1169 if (wm > max_wm)
1170 break;
1171
1172 wm_state->wm[level].plane[plane->id] = wm;
1173 }
1174
1175 wm_state->num_levels = level;
1176
1177 if (!wm_state->cxsr)
1178 continue;
1179
1180 /* maxfifo watermarks */
1181 if (plane->id == PLANE_CURSOR) {
1182 for (level = 0; level < wm_state->num_levels; level++)
1183 wm_state->sr[level].cursor =
1184 wm_state->wm[level].plane[PLANE_CURSOR];
1185 } else {
1186 for (level = 0; level < wm_state->num_levels; level++)
1187 wm_state->sr[level].plane =
1188 max(wm_state->sr[level].plane,
1189 wm_state->wm[level].plane[plane->id]);
1190 }
1191 }
1192
1193 /* clear any (partially) filled invalid levels */
1194 for (level = wm_state->num_levels; level < dev_priv->wm.max_level + 1; level++) {
1195 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1196 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1197 }
1198
1199 vlv_invert_wms(crtc);
1200 }
1201
1202 #define VLV_FIFO(plane, value) \
1203 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1204
1205 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1206 {
1207 struct drm_device *dev = crtc->base.dev;
1208 struct drm_i915_private *dev_priv = to_i915(dev);
1209 struct intel_plane *plane;
1210 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1211
1212 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1213 switch (plane->id) {
1214 case PLANE_PRIMARY:
1215 sprite0_start = plane->wm.fifo_size;
1216 break;
1217 case PLANE_SPRITE0:
1218 sprite1_start = sprite0_start + plane->wm.fifo_size;
1219 break;
1220 case PLANE_SPRITE1:
1221 fifo_size = sprite1_start + plane->wm.fifo_size;
1222 break;
1223 case PLANE_CURSOR:
1224 WARN_ON(plane->wm.fifo_size != 63);
1225 break;
1226 default:
1227 MISSING_CASE(plane->id);
1228 break;
1229 }
1230 }
1231
1232 WARN_ON(fifo_size != 512 - 1);
1233
1234 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1235 pipe_name(crtc->pipe), sprite0_start,
1236 sprite1_start, fifo_size);
1237
1238 spin_lock(&dev_priv->wm.dsparb_lock);
1239
1240 switch (crtc->pipe) {
1241 uint32_t dsparb, dsparb2, dsparb3;
1242 case PIPE_A:
1243 dsparb = I915_READ(DSPARB);
1244 dsparb2 = I915_READ(DSPARB2);
1245
1246 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1247 VLV_FIFO(SPRITEB, 0xff));
1248 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1249 VLV_FIFO(SPRITEB, sprite1_start));
1250
1251 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1252 VLV_FIFO(SPRITEB_HI, 0x1));
1253 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1254 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1255
1256 I915_WRITE(DSPARB, dsparb);
1257 I915_WRITE(DSPARB2, dsparb2);
1258 break;
1259 case PIPE_B:
1260 dsparb = I915_READ(DSPARB);
1261 dsparb2 = I915_READ(DSPARB2);
1262
1263 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1264 VLV_FIFO(SPRITED, 0xff));
1265 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1266 VLV_FIFO(SPRITED, sprite1_start));
1267
1268 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1269 VLV_FIFO(SPRITED_HI, 0xff));
1270 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1271 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1272
1273 I915_WRITE(DSPARB, dsparb);
1274 I915_WRITE(DSPARB2, dsparb2);
1275 break;
1276 case PIPE_C:
1277 dsparb3 = I915_READ(DSPARB3);
1278 dsparb2 = I915_READ(DSPARB2);
1279
1280 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1281 VLV_FIFO(SPRITEF, 0xff));
1282 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1283 VLV_FIFO(SPRITEF, sprite1_start));
1284
1285 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1286 VLV_FIFO(SPRITEF_HI, 0xff));
1287 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1288 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1289
1290 I915_WRITE(DSPARB3, dsparb3);
1291 I915_WRITE(DSPARB2, dsparb2);
1292 break;
1293 default:
1294 break;
1295 }
1296
1297 POSTING_READ(DSPARB);
1298
1299 spin_unlock(&dev_priv->wm.dsparb_lock);
1300 }
1301
1302 #undef VLV_FIFO
1303
1304 static void vlv_merge_wm(struct drm_i915_private *dev_priv,
1305 struct vlv_wm_values *wm)
1306 {
1307 struct intel_crtc *crtc;
1308 int num_active_crtcs = 0;
1309
1310 wm->level = dev_priv->wm.max_level;
1311 wm->cxsr = true;
1312
1313 for_each_intel_crtc(&dev_priv->drm, crtc) {
1314 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1315
1316 if (!crtc->active)
1317 continue;
1318
1319 if (!wm_state->cxsr)
1320 wm->cxsr = false;
1321
1322 num_active_crtcs++;
1323 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1324 }
1325
1326 if (num_active_crtcs != 1)
1327 wm->cxsr = false;
1328
1329 if (num_active_crtcs > 1)
1330 wm->level = VLV_WM_LEVEL_PM2;
1331
1332 for_each_intel_crtc(&dev_priv->drm, crtc) {
1333 struct vlv_wm_state *wm_state = &crtc->wm_state;
1334 enum pipe pipe = crtc->pipe;
1335
1336 if (!crtc->active)
1337 continue;
1338
1339 wm->pipe[pipe] = wm_state->wm[wm->level];
1340 if (wm->cxsr)
1341 wm->sr = wm_state->sr[wm->level];
1342
1343 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
1344 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
1345 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
1346 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
1347 }
1348 }
1349
1350 static bool is_disabling(int old, int new, int threshold)
1351 {
1352 return old >= threshold && new < threshold;
1353 }
1354
1355 static bool is_enabling(int old, int new, int threshold)
1356 {
1357 return old < threshold && new >= threshold;
1358 }
1359
1360 static void vlv_update_wm(struct intel_crtc *crtc)
1361 {
1362 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1363 enum pipe pipe = crtc->pipe;
1364 struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
1365 struct vlv_wm_values new_wm = {};
1366
1367 vlv_compute_wm(crtc);
1368 vlv_merge_wm(dev_priv, &new_wm);
1369
1370 if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0) {
1371 /* FIXME should be part of crtc atomic commit */
1372 vlv_pipe_set_fifo_size(crtc);
1373
1374 return;
1375 }
1376
1377 if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
1378 chv_set_memory_dvfs(dev_priv, false);
1379
1380 if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
1381 chv_set_memory_pm5(dev_priv, false);
1382
1383 if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
1384 _intel_set_memory_cxsr(dev_priv, false);
1385
1386 /* FIXME should be part of crtc atomic commit */
1387 vlv_pipe_set_fifo_size(crtc);
1388
1389 vlv_write_wm_values(dev_priv, &new_wm);
1390
1391 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1392 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1393 pipe_name(pipe), new_wm.pipe[pipe].plane[PLANE_PRIMARY], new_wm.pipe[pipe].plane[PLANE_CURSOR],
1394 new_wm.pipe[pipe].plane[PLANE_SPRITE0], new_wm.pipe[pipe].plane[PLANE_SPRITE1],
1395 new_wm.sr.plane, new_wm.sr.cursor, new_wm.level, new_wm.cxsr);
1396
1397 if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
1398 _intel_set_memory_cxsr(dev_priv, true);
1399
1400 if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
1401 chv_set_memory_pm5(dev_priv, true);
1402
1403 if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
1404 chv_set_memory_dvfs(dev_priv, true);
1405
1406 *old_wm = new_wm;
1407 }
1408
1409 #define single_plane_enabled(mask) is_power_of_2(mask)
1410
1411 static void g4x_update_wm(struct intel_crtc *crtc)
1412 {
1413 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1414 static const int sr_latency_ns = 12000;
1415 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1416 int plane_sr, cursor_sr;
1417 unsigned int enabled = 0;
1418 bool cxsr_enabled;
1419
1420 if (g4x_compute_wm0(dev_priv, PIPE_A,
1421 &g4x_wm_info, pessimal_latency_ns,
1422 &g4x_cursor_wm_info, pessimal_latency_ns,
1423 &planea_wm, &cursora_wm))
1424 enabled |= 1 << PIPE_A;
1425
1426 if (g4x_compute_wm0(dev_priv, PIPE_B,
1427 &g4x_wm_info, pessimal_latency_ns,
1428 &g4x_cursor_wm_info, pessimal_latency_ns,
1429 &planeb_wm, &cursorb_wm))
1430 enabled |= 1 << PIPE_B;
1431
1432 if (single_plane_enabled(enabled) &&
1433 g4x_compute_srwm(dev_priv, ffs(enabled) - 1,
1434 sr_latency_ns,
1435 &g4x_wm_info,
1436 &g4x_cursor_wm_info,
1437 &plane_sr, &cursor_sr)) {
1438 cxsr_enabled = true;
1439 } else {
1440 cxsr_enabled = false;
1441 intel_set_memory_cxsr(dev_priv, false);
1442 plane_sr = cursor_sr = 0;
1443 }
1444
1445 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1446 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1447 planea_wm, cursora_wm,
1448 planeb_wm, cursorb_wm,
1449 plane_sr, cursor_sr);
1450
1451 I915_WRITE(DSPFW1,
1452 FW_WM(plane_sr, SR) |
1453 FW_WM(cursorb_wm, CURSORB) |
1454 FW_WM(planeb_wm, PLANEB) |
1455 FW_WM(planea_wm, PLANEA));
1456 I915_WRITE(DSPFW2,
1457 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1458 FW_WM(cursora_wm, CURSORA));
1459 /* HPLL off in SR has some issues on G4x... disable it */
1460 I915_WRITE(DSPFW3,
1461 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1462 FW_WM(cursor_sr, CURSOR_SR));
1463
1464 if (cxsr_enabled)
1465 intel_set_memory_cxsr(dev_priv, true);
1466 }
1467
1468 static void i965_update_wm(struct intel_crtc *unused_crtc)
1469 {
1470 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1471 struct intel_crtc *crtc;
1472 int srwm = 1;
1473 int cursor_sr = 16;
1474 bool cxsr_enabled;
1475
1476 /* Calc sr entries for one plane configs */
1477 crtc = single_enabled_crtc(dev_priv);
1478 if (crtc) {
1479 /* self-refresh has much higher latency */
1480 static const int sr_latency_ns = 12000;
1481 const struct drm_display_mode *adjusted_mode =
1482 &crtc->config->base.adjusted_mode;
1483 const struct drm_framebuffer *fb =
1484 crtc->base.primary->state->fb;
1485 int clock = adjusted_mode->crtc_clock;
1486 int htotal = adjusted_mode->crtc_htotal;
1487 int hdisplay = crtc->config->pipe_src_w;
1488 int cpp = fb->format->cpp[0];
1489 unsigned long line_time_us;
1490 int entries;
1491
1492 line_time_us = max(htotal * 1000 / clock, 1);
1493
1494 /* Use ns/us then divide to preserve precision */
1495 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1496 cpp * hdisplay;
1497 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1498 srwm = I965_FIFO_SIZE - entries;
1499 if (srwm < 0)
1500 srwm = 1;
1501 srwm &= 0x1ff;
1502 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1503 entries, srwm);
1504
1505 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1506 cpp * crtc->base.cursor->state->crtc_w;
1507 entries = DIV_ROUND_UP(entries,
1508 i965_cursor_wm_info.cacheline_size);
1509 cursor_sr = i965_cursor_wm_info.fifo_size -
1510 (entries + i965_cursor_wm_info.guard_size);
1511
1512 if (cursor_sr > i965_cursor_wm_info.max_wm)
1513 cursor_sr = i965_cursor_wm_info.max_wm;
1514
1515 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1516 "cursor %d\n", srwm, cursor_sr);
1517
1518 cxsr_enabled = true;
1519 } else {
1520 cxsr_enabled = false;
1521 /* Turn off self refresh if both pipes are enabled */
1522 intel_set_memory_cxsr(dev_priv, false);
1523 }
1524
1525 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1526 srwm);
1527
1528 /* 965 has limitations... */
1529 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1530 FW_WM(8, CURSORB) |
1531 FW_WM(8, PLANEB) |
1532 FW_WM(8, PLANEA));
1533 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1534 FW_WM(8, PLANEC_OLD));
1535 /* update cursor SR watermark */
1536 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1537
1538 if (cxsr_enabled)
1539 intel_set_memory_cxsr(dev_priv, true);
1540 }
1541
1542 #undef FW_WM
1543
1544 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
1545 {
1546 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1547 const struct intel_watermark_params *wm_info;
1548 uint32_t fwater_lo;
1549 uint32_t fwater_hi;
1550 int cwm, srwm = 1;
1551 int fifo_size;
1552 int planea_wm, planeb_wm;
1553 struct intel_crtc *crtc, *enabled = NULL;
1554
1555 if (IS_I945GM(dev_priv))
1556 wm_info = &i945_wm_info;
1557 else if (!IS_GEN2(dev_priv))
1558 wm_info = &i915_wm_info;
1559 else
1560 wm_info = &i830_a_wm_info;
1561
1562 fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
1563 crtc = intel_get_crtc_for_plane(dev_priv, 0);
1564 if (intel_crtc_active(crtc)) {
1565 const struct drm_display_mode *adjusted_mode =
1566 &crtc->config->base.adjusted_mode;
1567 const struct drm_framebuffer *fb =
1568 crtc->base.primary->state->fb;
1569 int cpp;
1570
1571 if (IS_GEN2(dev_priv))
1572 cpp = 4;
1573 else
1574 cpp = fb->format->cpp[0];
1575
1576 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1577 wm_info, fifo_size, cpp,
1578 pessimal_latency_ns);
1579 enabled = crtc;
1580 } else {
1581 planea_wm = fifo_size - wm_info->guard_size;
1582 if (planea_wm > (long)wm_info->max_wm)
1583 planea_wm = wm_info->max_wm;
1584 }
1585
1586 if (IS_GEN2(dev_priv))
1587 wm_info = &i830_bc_wm_info;
1588
1589 fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
1590 crtc = intel_get_crtc_for_plane(dev_priv, 1);
1591 if (intel_crtc_active(crtc)) {
1592 const struct drm_display_mode *adjusted_mode =
1593 &crtc->config->base.adjusted_mode;
1594 const struct drm_framebuffer *fb =
1595 crtc->base.primary->state->fb;
1596 int cpp;
1597
1598 if (IS_GEN2(dev_priv))
1599 cpp = 4;
1600 else
1601 cpp = fb->format->cpp[0];
1602
1603 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1604 wm_info, fifo_size, cpp,
1605 pessimal_latency_ns);
1606 if (enabled == NULL)
1607 enabled = crtc;
1608 else
1609 enabled = NULL;
1610 } else {
1611 planeb_wm = fifo_size - wm_info->guard_size;
1612 if (planeb_wm > (long)wm_info->max_wm)
1613 planeb_wm = wm_info->max_wm;
1614 }
1615
1616 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1617
1618 if (IS_I915GM(dev_priv) && enabled) {
1619 struct drm_i915_gem_object *obj;
1620
1621 obj = intel_fb_obj(enabled->base.primary->state->fb);
1622
1623 /* self-refresh seems busted with untiled */
1624 if (!i915_gem_object_is_tiled(obj))
1625 enabled = NULL;
1626 }
1627
1628 /*
1629 * Overlay gets an aggressive default since video jitter is bad.
1630 */
1631 cwm = 2;
1632
1633 /* Play safe and disable self-refresh before adjusting watermarks. */
1634 intel_set_memory_cxsr(dev_priv, false);
1635
1636 /* Calc sr entries for one plane configs */
1637 if (HAS_FW_BLC(dev_priv) && enabled) {
1638 /* self-refresh has much higher latency */
1639 static const int sr_latency_ns = 6000;
1640 const struct drm_display_mode *adjusted_mode =
1641 &enabled->config->base.adjusted_mode;
1642 const struct drm_framebuffer *fb =
1643 enabled->base.primary->state->fb;
1644 int clock = adjusted_mode->crtc_clock;
1645 int htotal = adjusted_mode->crtc_htotal;
1646 int hdisplay = enabled->config->pipe_src_w;
1647 int cpp;
1648 unsigned long line_time_us;
1649 int entries;
1650
1651 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
1652 cpp = 4;
1653 else
1654 cpp = fb->format->cpp[0];
1655
1656 line_time_us = max(htotal * 1000 / clock, 1);
1657
1658 /* Use ns/us then divide to preserve precision */
1659 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1660 cpp * hdisplay;
1661 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1662 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1663 srwm = wm_info->fifo_size - entries;
1664 if (srwm < 0)
1665 srwm = 1;
1666
1667 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1668 I915_WRITE(FW_BLC_SELF,
1669 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1670 else
1671 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1672 }
1673
1674 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1675 planea_wm, planeb_wm, cwm, srwm);
1676
1677 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1678 fwater_hi = (cwm & 0x1f);
1679
1680 /* Set request length to 8 cachelines per fetch */
1681 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1682 fwater_hi = fwater_hi | (1 << 8);
1683
1684 I915_WRITE(FW_BLC, fwater_lo);
1685 I915_WRITE(FW_BLC2, fwater_hi);
1686
1687 if (enabled)
1688 intel_set_memory_cxsr(dev_priv, true);
1689 }
1690
1691 static void i845_update_wm(struct intel_crtc *unused_crtc)
1692 {
1693 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1694 struct intel_crtc *crtc;
1695 const struct drm_display_mode *adjusted_mode;
1696 uint32_t fwater_lo;
1697 int planea_wm;
1698
1699 crtc = single_enabled_crtc(dev_priv);
1700 if (crtc == NULL)
1701 return;
1702
1703 adjusted_mode = &crtc->config->base.adjusted_mode;
1704 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1705 &i845_wm_info,
1706 dev_priv->display.get_fifo_size(dev_priv, 0),
1707 4, pessimal_latency_ns);
1708 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1709 fwater_lo |= (3<<8) | planea_wm;
1710
1711 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1712
1713 I915_WRITE(FW_BLC, fwater_lo);
1714 }
1715
1716 /* latency must be in 0.1us units. */
1717 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1718 {
1719 uint64_t ret;
1720
1721 if (WARN(latency == 0, "Latency value missing\n"))
1722 return UINT_MAX;
1723
1724 ret = (uint64_t) pixel_rate * cpp * latency;
1725 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1726
1727 return ret;
1728 }
1729
1730 /* latency must be in 0.1us units. */
1731 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1732 uint32_t horiz_pixels, uint8_t cpp,
1733 uint32_t latency)
1734 {
1735 uint32_t ret;
1736
1737 if (WARN(latency == 0, "Latency value missing\n"))
1738 return UINT_MAX;
1739 if (WARN_ON(!pipe_htotal))
1740 return UINT_MAX;
1741
1742 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1743 ret = (ret + 1) * horiz_pixels * cpp;
1744 ret = DIV_ROUND_UP(ret, 64) + 2;
1745 return ret;
1746 }
1747
1748 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1749 uint8_t cpp)
1750 {
1751 /*
1752 * Neither of these should be possible since this function shouldn't be
1753 * called if the CRTC is off or the plane is invisible. But let's be
1754 * extra paranoid to avoid a potential divide-by-zero if we screw up
1755 * elsewhere in the driver.
1756 */
1757 if (WARN_ON(!cpp))
1758 return 0;
1759 if (WARN_ON(!horiz_pixels))
1760 return 0;
1761
1762 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1763 }
1764
1765 struct ilk_wm_maximums {
1766 uint16_t pri;
1767 uint16_t spr;
1768 uint16_t cur;
1769 uint16_t fbc;
1770 };
1771
1772 /*
1773 * For both WM_PIPE and WM_LP.
1774 * mem_value must be in 0.1us units.
1775 */
1776 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1777 const struct intel_plane_state *pstate,
1778 uint32_t mem_value,
1779 bool is_lp)
1780 {
1781 uint32_t method1, method2;
1782 int cpp;
1783
1784 if (!cstate->base.active || !pstate->base.visible)
1785 return 0;
1786
1787 cpp = pstate->base.fb->format->cpp[0];
1788
1789 method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
1790
1791 if (!is_lp)
1792 return method1;
1793
1794 method2 = ilk_wm_method2(cstate->pixel_rate,
1795 cstate->base.adjusted_mode.crtc_htotal,
1796 drm_rect_width(&pstate->base.dst),
1797 cpp, mem_value);
1798
1799 return min(method1, method2);
1800 }
1801
1802 /*
1803 * For both WM_PIPE and WM_LP.
1804 * mem_value must be in 0.1us units.
1805 */
1806 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1807 const struct intel_plane_state *pstate,
1808 uint32_t mem_value)
1809 {
1810 uint32_t method1, method2;
1811 int cpp;
1812
1813 if (!cstate->base.active || !pstate->base.visible)
1814 return 0;
1815
1816 cpp = pstate->base.fb->format->cpp[0];
1817
1818 method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
1819 method2 = ilk_wm_method2(cstate->pixel_rate,
1820 cstate->base.adjusted_mode.crtc_htotal,
1821 drm_rect_width(&pstate->base.dst),
1822 cpp, mem_value);
1823 return min(method1, method2);
1824 }
1825
1826 /*
1827 * For both WM_PIPE and WM_LP.
1828 * mem_value must be in 0.1us units.
1829 */
1830 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1831 const struct intel_plane_state *pstate,
1832 uint32_t mem_value)
1833 {
1834 /*
1835 * We treat the cursor plane as always-on for the purposes of watermark
1836 * calculation. Until we have two-stage watermark programming merged,
1837 * this is necessary to avoid flickering.
1838 */
1839 int cpp = 4;
1840 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
1841
1842 if (!cstate->base.active)
1843 return 0;
1844
1845 return ilk_wm_method2(cstate->pixel_rate,
1846 cstate->base.adjusted_mode.crtc_htotal,
1847 width, cpp, mem_value);
1848 }
1849
1850 /* Only for WM_LP. */
1851 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1852 const struct intel_plane_state *pstate,
1853 uint32_t pri_val)
1854 {
1855 int cpp;
1856
1857 if (!cstate->base.active || !pstate->base.visible)
1858 return 0;
1859
1860 cpp = pstate->base.fb->format->cpp[0];
1861
1862 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
1863 }
1864
1865 static unsigned int
1866 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
1867 {
1868 if (INTEL_GEN(dev_priv) >= 8)
1869 return 3072;
1870 else if (INTEL_GEN(dev_priv) >= 7)
1871 return 768;
1872 else
1873 return 512;
1874 }
1875
1876 static unsigned int
1877 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
1878 int level, bool is_sprite)
1879 {
1880 if (INTEL_GEN(dev_priv) >= 8)
1881 /* BDW primary/sprite plane watermarks */
1882 return level == 0 ? 255 : 2047;
1883 else if (INTEL_GEN(dev_priv) >= 7)
1884 /* IVB/HSW primary/sprite plane watermarks */
1885 return level == 0 ? 127 : 1023;
1886 else if (!is_sprite)
1887 /* ILK/SNB primary plane watermarks */
1888 return level == 0 ? 127 : 511;
1889 else
1890 /* ILK/SNB sprite plane watermarks */
1891 return level == 0 ? 63 : 255;
1892 }
1893
1894 static unsigned int
1895 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
1896 {
1897 if (INTEL_GEN(dev_priv) >= 7)
1898 return level == 0 ? 63 : 255;
1899 else
1900 return level == 0 ? 31 : 63;
1901 }
1902
1903 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
1904 {
1905 if (INTEL_GEN(dev_priv) >= 8)
1906 return 31;
1907 else
1908 return 15;
1909 }
1910
1911 /* Calculate the maximum primary/sprite plane watermark */
1912 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1913 int level,
1914 const struct intel_wm_config *config,
1915 enum intel_ddb_partitioning ddb_partitioning,
1916 bool is_sprite)
1917 {
1918 struct drm_i915_private *dev_priv = to_i915(dev);
1919 unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
1920
1921 /* if sprites aren't enabled, sprites get nothing */
1922 if (is_sprite && !config->sprites_enabled)
1923 return 0;
1924
1925 /* HSW allows LP1+ watermarks even with multiple pipes */
1926 if (level == 0 || config->num_pipes_active > 1) {
1927 fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
1928
1929 /*
1930 * For some reason the non self refresh
1931 * FIFO size is only half of the self
1932 * refresh FIFO size on ILK/SNB.
1933 */
1934 if (INTEL_GEN(dev_priv) <= 6)
1935 fifo_size /= 2;
1936 }
1937
1938 if (config->sprites_enabled) {
1939 /* level 0 is always calculated with 1:1 split */
1940 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1941 if (is_sprite)
1942 fifo_size *= 5;
1943 fifo_size /= 6;
1944 } else {
1945 fifo_size /= 2;
1946 }
1947 }
1948
1949 /* clamp to max that the registers can hold */
1950 return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
1951 }
1952
1953 /* Calculate the maximum cursor plane watermark */
1954 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1955 int level,
1956 const struct intel_wm_config *config)
1957 {
1958 /* HSW LP1+ watermarks w/ multiple pipes */
1959 if (level > 0 && config->num_pipes_active > 1)
1960 return 64;
1961
1962 /* otherwise just report max that registers can hold */
1963 return ilk_cursor_wm_reg_max(to_i915(dev), level);
1964 }
1965
1966 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1967 int level,
1968 const struct intel_wm_config *config,
1969 enum intel_ddb_partitioning ddb_partitioning,
1970 struct ilk_wm_maximums *max)
1971 {
1972 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1973 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1974 max->cur = ilk_cursor_wm_max(dev, level, config);
1975 max->fbc = ilk_fbc_wm_reg_max(to_i915(dev));
1976 }
1977
1978 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
1979 int level,
1980 struct ilk_wm_maximums *max)
1981 {
1982 max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
1983 max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
1984 max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
1985 max->fbc = ilk_fbc_wm_reg_max(dev_priv);
1986 }
1987
1988 static bool ilk_validate_wm_level(int level,
1989 const struct ilk_wm_maximums *max,
1990 struct intel_wm_level *result)
1991 {
1992 bool ret;
1993
1994 /* already determined to be invalid? */
1995 if (!result->enable)
1996 return false;
1997
1998 result->enable = result->pri_val <= max->pri &&
1999 result->spr_val <= max->spr &&
2000 result->cur_val <= max->cur;
2001
2002 ret = result->enable;
2003
2004 /*
2005 * HACK until we can pre-compute everything,
2006 * and thus fail gracefully if LP0 watermarks
2007 * are exceeded...
2008 */
2009 if (level == 0 && !result->enable) {
2010 if (result->pri_val > max->pri)
2011 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2012 level, result->pri_val, max->pri);
2013 if (result->spr_val > max->spr)
2014 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2015 level, result->spr_val, max->spr);
2016 if (result->cur_val > max->cur)
2017 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2018 level, result->cur_val, max->cur);
2019
2020 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2021 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2022 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2023 result->enable = true;
2024 }
2025
2026 return ret;
2027 }
2028
2029 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2030 const struct intel_crtc *intel_crtc,
2031 int level,
2032 struct intel_crtc_state *cstate,
2033 struct intel_plane_state *pristate,
2034 struct intel_plane_state *sprstate,
2035 struct intel_plane_state *curstate,
2036 struct intel_wm_level *result)
2037 {
2038 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2039 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2040 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2041
2042 /* WM1+ latency values stored in 0.5us units */
2043 if (level > 0) {
2044 pri_latency *= 5;
2045 spr_latency *= 5;
2046 cur_latency *= 5;
2047 }
2048
2049 if (pristate) {
2050 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2051 pri_latency, level);
2052 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2053 }
2054
2055 if (sprstate)
2056 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2057
2058 if (curstate)
2059 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2060
2061 result->enable = true;
2062 }
2063
2064 static uint32_t
2065 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2066 {
2067 const struct intel_atomic_state *intel_state =
2068 to_intel_atomic_state(cstate->base.state);
2069 const struct drm_display_mode *adjusted_mode =
2070 &cstate->base.adjusted_mode;
2071 u32 linetime, ips_linetime;
2072
2073 if (!cstate->base.active)
2074 return 0;
2075 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2076 return 0;
2077 if (WARN_ON(intel_state->cdclk.logical.cdclk == 0))
2078 return 0;
2079
2080 /* The WM are computed with base on how long it takes to fill a single
2081 * row at the given clock rate, multiplied by 8.
2082 * */
2083 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2084 adjusted_mode->crtc_clock);
2085 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2086 intel_state->cdclk.logical.cdclk);
2087
2088 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2089 PIPE_WM_LINETIME_TIME(linetime);
2090 }
2091
2092 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2093 uint16_t wm[8])
2094 {
2095 if (IS_GEN9(dev_priv)) {
2096 uint32_t val;
2097 int ret, i;
2098 int level, max_level = ilk_wm_max_level(dev_priv);
2099
2100 /* read the first set of memory latencies[0:3] */
2101 val = 0; /* data0 to be programmed to 0 for first set */
2102 mutex_lock(&dev_priv->rps.hw_lock);
2103 ret = sandybridge_pcode_read(dev_priv,
2104 GEN9_PCODE_READ_MEM_LATENCY,
2105 &val);
2106 mutex_unlock(&dev_priv->rps.hw_lock);
2107
2108 if (ret) {
2109 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2110 return;
2111 }
2112
2113 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2114 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2115 GEN9_MEM_LATENCY_LEVEL_MASK;
2116 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2117 GEN9_MEM_LATENCY_LEVEL_MASK;
2118 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2119 GEN9_MEM_LATENCY_LEVEL_MASK;
2120
2121 /* read the second set of memory latencies[4:7] */
2122 val = 1; /* data0 to be programmed to 1 for second set */
2123 mutex_lock(&dev_priv->rps.hw_lock);
2124 ret = sandybridge_pcode_read(dev_priv,
2125 GEN9_PCODE_READ_MEM_LATENCY,
2126 &val);
2127 mutex_unlock(&dev_priv->rps.hw_lock);
2128 if (ret) {
2129 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2130 return;
2131 }
2132
2133 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2134 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2135 GEN9_MEM_LATENCY_LEVEL_MASK;
2136 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2137 GEN9_MEM_LATENCY_LEVEL_MASK;
2138 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2139 GEN9_MEM_LATENCY_LEVEL_MASK;
2140
2141 /*
2142 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2143 * need to be disabled. We make sure to sanitize the values out
2144 * of the punit to satisfy this requirement.
2145 */
2146 for (level = 1; level <= max_level; level++) {
2147 if (wm[level] == 0) {
2148 for (i = level + 1; i <= max_level; i++)
2149 wm[i] = 0;
2150 break;
2151 }
2152 }
2153
2154 /*
2155 * WaWmMemoryReadLatency:skl,glk
2156 *
2157 * punit doesn't take into account the read latency so we need
2158 * to add 2us to the various latency levels we retrieve from the
2159 * punit when level 0 response data us 0us.
2160 */
2161 if (wm[0] == 0) {
2162 wm[0] += 2;
2163 for (level = 1; level <= max_level; level++) {
2164 if (wm[level] == 0)
2165 break;
2166 wm[level] += 2;
2167 }
2168 }
2169
2170 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2171 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2172
2173 wm[0] = (sskpd >> 56) & 0xFF;
2174 if (wm[0] == 0)
2175 wm[0] = sskpd & 0xF;
2176 wm[1] = (sskpd >> 4) & 0xFF;
2177 wm[2] = (sskpd >> 12) & 0xFF;
2178 wm[3] = (sskpd >> 20) & 0x1FF;
2179 wm[4] = (sskpd >> 32) & 0x1FF;
2180 } else if (INTEL_GEN(dev_priv) >= 6) {
2181 uint32_t sskpd = I915_READ(MCH_SSKPD);
2182
2183 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2184 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2185 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2186 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2187 } else if (INTEL_GEN(dev_priv) >= 5) {
2188 uint32_t mltr = I915_READ(MLTR_ILK);
2189
2190 /* ILK primary LP0 latency is 700 ns */
2191 wm[0] = 7;
2192 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2193 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2194 }
2195 }
2196
2197 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2198 uint16_t wm[5])
2199 {
2200 /* ILK sprite LP0 latency is 1300 ns */
2201 if (IS_GEN5(dev_priv))
2202 wm[0] = 13;
2203 }
2204
2205 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2206 uint16_t wm[5])
2207 {
2208 /* ILK cursor LP0 latency is 1300 ns */
2209 if (IS_GEN5(dev_priv))
2210 wm[0] = 13;
2211
2212 /* WaDoubleCursorLP3Latency:ivb */
2213 if (IS_IVYBRIDGE(dev_priv))
2214 wm[3] *= 2;
2215 }
2216
2217 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2218 {
2219 /* how many WM levels are we expecting */
2220 if (INTEL_GEN(dev_priv) >= 9)
2221 return 7;
2222 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2223 return 4;
2224 else if (INTEL_GEN(dev_priv) >= 6)
2225 return 3;
2226 else
2227 return 2;
2228 }
2229
2230 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2231 const char *name,
2232 const uint16_t wm[8])
2233 {
2234 int level, max_level = ilk_wm_max_level(dev_priv);
2235
2236 for (level = 0; level <= max_level; level++) {
2237 unsigned int latency = wm[level];
2238
2239 if (latency == 0) {
2240 DRM_ERROR("%s WM%d latency not provided\n",
2241 name, level);
2242 continue;
2243 }
2244
2245 /*
2246 * - latencies are in us on gen9.
2247 * - before then, WM1+ latency values are in 0.5us units
2248 */
2249 if (IS_GEN9(dev_priv))
2250 latency *= 10;
2251 else if (level > 0)
2252 latency *= 5;
2253
2254 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2255 name, level, wm[level],
2256 latency / 10, latency % 10);
2257 }
2258 }
2259
2260 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2261 uint16_t wm[5], uint16_t min)
2262 {
2263 int level, max_level = ilk_wm_max_level(dev_priv);
2264
2265 if (wm[0] >= min)
2266 return false;
2267
2268 wm[0] = max(wm[0], min);
2269 for (level = 1; level <= max_level; level++)
2270 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2271
2272 return true;
2273 }
2274
2275 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
2276 {
2277 bool changed;
2278
2279 /*
2280 * The BIOS provided WM memory latency values are often
2281 * inadequate for high resolution displays. Adjust them.
2282 */
2283 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2284 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2285 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2286
2287 if (!changed)
2288 return;
2289
2290 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2291 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2292 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2293 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2294 }
2295
2296 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
2297 {
2298 intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
2299
2300 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2301 sizeof(dev_priv->wm.pri_latency));
2302 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2303 sizeof(dev_priv->wm.pri_latency));
2304
2305 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
2306 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
2307
2308 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2309 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2310 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2311
2312 if (IS_GEN6(dev_priv))
2313 snb_wm_latency_quirk(dev_priv);
2314 }
2315
2316 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
2317 {
2318 intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
2319 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2320 }
2321
2322 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2323 struct intel_pipe_wm *pipe_wm)
2324 {
2325 /* LP0 watermark maximums depend on this pipe alone */
2326 const struct intel_wm_config config = {
2327 .num_pipes_active = 1,
2328 .sprites_enabled = pipe_wm->sprites_enabled,
2329 .sprites_scaled = pipe_wm->sprites_scaled,
2330 };
2331 struct ilk_wm_maximums max;
2332
2333 /* LP0 watermarks always use 1/2 DDB partitioning */
2334 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2335
2336 /* At least LP0 must be valid */
2337 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2338 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2339 return false;
2340 }
2341
2342 return true;
2343 }
2344
2345 /* Compute new watermarks for the pipe */
2346 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2347 {
2348 struct drm_atomic_state *state = cstate->base.state;
2349 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2350 struct intel_pipe_wm *pipe_wm;
2351 struct drm_device *dev = state->dev;
2352 const struct drm_i915_private *dev_priv = to_i915(dev);
2353 struct intel_plane *intel_plane;
2354 struct intel_plane_state *pristate = NULL;
2355 struct intel_plane_state *sprstate = NULL;
2356 struct intel_plane_state *curstate = NULL;
2357 int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
2358 struct ilk_wm_maximums max;
2359
2360 pipe_wm = &cstate->wm.ilk.optimal;
2361
2362 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2363 struct intel_plane_state *ps;
2364
2365 ps = intel_atomic_get_existing_plane_state(state,
2366 intel_plane);
2367 if (!ps)
2368 continue;
2369
2370 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2371 pristate = ps;
2372 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2373 sprstate = ps;
2374 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2375 curstate = ps;
2376 }
2377
2378 pipe_wm->pipe_enabled = cstate->base.active;
2379 if (sprstate) {
2380 pipe_wm->sprites_enabled = sprstate->base.visible;
2381 pipe_wm->sprites_scaled = sprstate->base.visible &&
2382 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2383 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
2384 }
2385
2386 usable_level = max_level;
2387
2388 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2389 if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
2390 usable_level = 1;
2391
2392 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2393 if (pipe_wm->sprites_scaled)
2394 usable_level = 0;
2395
2396 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2397 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2398
2399 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2400 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2401
2402 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2403 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2404
2405 if (!ilk_validate_pipe_wm(dev, pipe_wm))
2406 return -EINVAL;
2407
2408 ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
2409
2410 for (level = 1; level <= max_level; level++) {
2411 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2412
2413 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2414 pristate, sprstate, curstate, wm);
2415
2416 /*
2417 * Disable any watermark level that exceeds the
2418 * register maximums since such watermarks are
2419 * always invalid.
2420 */
2421 if (level > usable_level)
2422 continue;
2423
2424 if (ilk_validate_wm_level(level, &max, wm))
2425 pipe_wm->wm[level] = *wm;
2426 else
2427 usable_level = level;
2428 }
2429
2430 return 0;
2431 }
2432
2433 /*
2434 * Build a set of 'intermediate' watermark values that satisfy both the old
2435 * state and the new state. These can be programmed to the hardware
2436 * immediately.
2437 */
2438 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2439 struct intel_crtc *intel_crtc,
2440 struct intel_crtc_state *newstate)
2441 {
2442 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2443 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2444 int level, max_level = ilk_wm_max_level(to_i915(dev));
2445
2446 /*
2447 * Start with the final, target watermarks, then combine with the
2448 * currently active watermarks to get values that are safe both before
2449 * and after the vblank.
2450 */
2451 *a = newstate->wm.ilk.optimal;
2452 a->pipe_enabled |= b->pipe_enabled;
2453 a->sprites_enabled |= b->sprites_enabled;
2454 a->sprites_scaled |= b->sprites_scaled;
2455
2456 for (level = 0; level <= max_level; level++) {
2457 struct intel_wm_level *a_wm = &a->wm[level];
2458 const struct intel_wm_level *b_wm = &b->wm[level];
2459
2460 a_wm->enable &= b_wm->enable;
2461 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2462 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2463 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2464 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2465 }
2466
2467 /*
2468 * We need to make sure that these merged watermark values are
2469 * actually a valid configuration themselves. If they're not,
2470 * there's no safe way to transition from the old state to
2471 * the new state, so we need to fail the atomic transaction.
2472 */
2473 if (!ilk_validate_pipe_wm(dev, a))
2474 return -EINVAL;
2475
2476 /*
2477 * If our intermediate WM are identical to the final WM, then we can
2478 * omit the post-vblank programming; only update if it's different.
2479 */
2480 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2481 newstate->wm.need_postvbl_update = false;
2482
2483 return 0;
2484 }
2485
2486 /*
2487 * Merge the watermarks from all active pipes for a specific level.
2488 */
2489 static void ilk_merge_wm_level(struct drm_device *dev,
2490 int level,
2491 struct intel_wm_level *ret_wm)
2492 {
2493 const struct intel_crtc *intel_crtc;
2494
2495 ret_wm->enable = true;
2496
2497 for_each_intel_crtc(dev, intel_crtc) {
2498 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2499 const struct intel_wm_level *wm = &active->wm[level];
2500
2501 if (!active->pipe_enabled)
2502 continue;
2503
2504 /*
2505 * The watermark values may have been used in the past,
2506 * so we must maintain them in the registers for some
2507 * time even if the level is now disabled.
2508 */
2509 if (!wm->enable)
2510 ret_wm->enable = false;
2511
2512 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2513 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2514 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2515 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2516 }
2517 }
2518
2519 /*
2520 * Merge all low power watermarks for all active pipes.
2521 */
2522 static void ilk_wm_merge(struct drm_device *dev,
2523 const struct intel_wm_config *config,
2524 const struct ilk_wm_maximums *max,
2525 struct intel_pipe_wm *merged)
2526 {
2527 struct drm_i915_private *dev_priv = to_i915(dev);
2528 int level, max_level = ilk_wm_max_level(dev_priv);
2529 int last_enabled_level = max_level;
2530
2531 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2532 if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
2533 config->num_pipes_active > 1)
2534 last_enabled_level = 0;
2535
2536 /* ILK: FBC WM must be disabled always */
2537 merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
2538
2539 /* merge each WM1+ level */
2540 for (level = 1; level <= max_level; level++) {
2541 struct intel_wm_level *wm = &merged->wm[level];
2542
2543 ilk_merge_wm_level(dev, level, wm);
2544
2545 if (level > last_enabled_level)
2546 wm->enable = false;
2547 else if (!ilk_validate_wm_level(level, max, wm))
2548 /* make sure all following levels get disabled */
2549 last_enabled_level = level - 1;
2550
2551 /*
2552 * The spec says it is preferred to disable
2553 * FBC WMs instead of disabling a WM level.
2554 */
2555 if (wm->fbc_val > max->fbc) {
2556 if (wm->enable)
2557 merged->fbc_wm_enabled = false;
2558 wm->fbc_val = 0;
2559 }
2560 }
2561
2562 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2563 /*
2564 * FIXME this is racy. FBC might get enabled later.
2565 * What we should check here is whether FBC can be
2566 * enabled sometime later.
2567 */
2568 if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
2569 intel_fbc_is_active(dev_priv)) {
2570 for (level = 2; level <= max_level; level++) {
2571 struct intel_wm_level *wm = &merged->wm[level];
2572
2573 wm->enable = false;
2574 }
2575 }
2576 }
2577
2578 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2579 {
2580 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2581 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2582 }
2583
2584 /* The value we need to program into the WM_LPx latency field */
2585 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2586 {
2587 struct drm_i915_private *dev_priv = to_i915(dev);
2588
2589 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2590 return 2 * level;
2591 else
2592 return dev_priv->wm.pri_latency[level];
2593 }
2594
2595 static void ilk_compute_wm_results(struct drm_device *dev,
2596 const struct intel_pipe_wm *merged,
2597 enum intel_ddb_partitioning partitioning,
2598 struct ilk_wm_values *results)
2599 {
2600 struct drm_i915_private *dev_priv = to_i915(dev);
2601 struct intel_crtc *intel_crtc;
2602 int level, wm_lp;
2603
2604 results->enable_fbc_wm = merged->fbc_wm_enabled;
2605 results->partitioning = partitioning;
2606
2607 /* LP1+ register values */
2608 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2609 const struct intel_wm_level *r;
2610
2611 level = ilk_wm_lp_to_level(wm_lp, merged);
2612
2613 r = &merged->wm[level];
2614
2615 /*
2616 * Maintain the watermark values even if the level is
2617 * disabled. Doing otherwise could cause underruns.
2618 */
2619 results->wm_lp[wm_lp - 1] =
2620 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2621 (r->pri_val << WM1_LP_SR_SHIFT) |
2622 r->cur_val;
2623
2624 if (r->enable)
2625 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2626
2627 if (INTEL_GEN(dev_priv) >= 8)
2628 results->wm_lp[wm_lp - 1] |=
2629 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2630 else
2631 results->wm_lp[wm_lp - 1] |=
2632 r->fbc_val << WM1_LP_FBC_SHIFT;
2633
2634 /*
2635 * Always set WM1S_LP_EN when spr_val != 0, even if the
2636 * level is disabled. Doing otherwise could cause underruns.
2637 */
2638 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
2639 WARN_ON(wm_lp != 1);
2640 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2641 } else
2642 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2643 }
2644
2645 /* LP0 register values */
2646 for_each_intel_crtc(dev, intel_crtc) {
2647 enum pipe pipe = intel_crtc->pipe;
2648 const struct intel_wm_level *r =
2649 &intel_crtc->wm.active.ilk.wm[0];
2650
2651 if (WARN_ON(!r->enable))
2652 continue;
2653
2654 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2655
2656 results->wm_pipe[pipe] =
2657 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2658 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2659 r->cur_val;
2660 }
2661 }
2662
2663 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2664 * case both are at the same level. Prefer r1 in case they're the same. */
2665 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2666 struct intel_pipe_wm *r1,
2667 struct intel_pipe_wm *r2)
2668 {
2669 int level, max_level = ilk_wm_max_level(to_i915(dev));
2670 int level1 = 0, level2 = 0;
2671
2672 for (level = 1; level <= max_level; level++) {
2673 if (r1->wm[level].enable)
2674 level1 = level;
2675 if (r2->wm[level].enable)
2676 level2 = level;
2677 }
2678
2679 if (level1 == level2) {
2680 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2681 return r2;
2682 else
2683 return r1;
2684 } else if (level1 > level2) {
2685 return r1;
2686 } else {
2687 return r2;
2688 }
2689 }
2690
2691 /* dirty bits used to track which watermarks need changes */
2692 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2693 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2694 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2695 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2696 #define WM_DIRTY_FBC (1 << 24)
2697 #define WM_DIRTY_DDB (1 << 25)
2698
2699 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2700 const struct ilk_wm_values *old,
2701 const struct ilk_wm_values *new)
2702 {
2703 unsigned int dirty = 0;
2704 enum pipe pipe;
2705 int wm_lp;
2706
2707 for_each_pipe(dev_priv, pipe) {
2708 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2709 dirty |= WM_DIRTY_LINETIME(pipe);
2710 /* Must disable LP1+ watermarks too */
2711 dirty |= WM_DIRTY_LP_ALL;
2712 }
2713
2714 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2715 dirty |= WM_DIRTY_PIPE(pipe);
2716 /* Must disable LP1+ watermarks too */
2717 dirty |= WM_DIRTY_LP_ALL;
2718 }
2719 }
2720
2721 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2722 dirty |= WM_DIRTY_FBC;
2723 /* Must disable LP1+ watermarks too */
2724 dirty |= WM_DIRTY_LP_ALL;
2725 }
2726
2727 if (old->partitioning != new->partitioning) {
2728 dirty |= WM_DIRTY_DDB;
2729 /* Must disable LP1+ watermarks too */
2730 dirty |= WM_DIRTY_LP_ALL;
2731 }
2732
2733 /* LP1+ watermarks already deemed dirty, no need to continue */
2734 if (dirty & WM_DIRTY_LP_ALL)
2735 return dirty;
2736
2737 /* Find the lowest numbered LP1+ watermark in need of an update... */
2738 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2739 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2740 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2741 break;
2742 }
2743
2744 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2745 for (; wm_lp <= 3; wm_lp++)
2746 dirty |= WM_DIRTY_LP(wm_lp);
2747
2748 return dirty;
2749 }
2750
2751 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2752 unsigned int dirty)
2753 {
2754 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2755 bool changed = false;
2756
2757 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2758 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2759 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2760 changed = true;
2761 }
2762 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2763 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2764 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2765 changed = true;
2766 }
2767 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2768 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2769 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2770 changed = true;
2771 }
2772
2773 /*
2774 * Don't touch WM1S_LP_EN here.
2775 * Doing so could cause underruns.
2776 */
2777
2778 return changed;
2779 }
2780
2781 /*
2782 * The spec says we shouldn't write when we don't need, because every write
2783 * causes WMs to be re-evaluated, expending some power.
2784 */
2785 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2786 struct ilk_wm_values *results)
2787 {
2788 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2789 unsigned int dirty;
2790 uint32_t val;
2791
2792 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2793 if (!dirty)
2794 return;
2795
2796 _ilk_disable_lp_wm(dev_priv, dirty);
2797
2798 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2799 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2800 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2801 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2802 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2803 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2804
2805 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2806 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2807 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2808 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2809 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2810 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2811
2812 if (dirty & WM_DIRTY_DDB) {
2813 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2814 val = I915_READ(WM_MISC);
2815 if (results->partitioning == INTEL_DDB_PART_1_2)
2816 val &= ~WM_MISC_DATA_PARTITION_5_6;
2817 else
2818 val |= WM_MISC_DATA_PARTITION_5_6;
2819 I915_WRITE(WM_MISC, val);
2820 } else {
2821 val = I915_READ(DISP_ARB_CTL2);
2822 if (results->partitioning == INTEL_DDB_PART_1_2)
2823 val &= ~DISP_DATA_PARTITION_5_6;
2824 else
2825 val |= DISP_DATA_PARTITION_5_6;
2826 I915_WRITE(DISP_ARB_CTL2, val);
2827 }
2828 }
2829
2830 if (dirty & WM_DIRTY_FBC) {
2831 val = I915_READ(DISP_ARB_CTL);
2832 if (results->enable_fbc_wm)
2833 val &= ~DISP_FBC_WM_DIS;
2834 else
2835 val |= DISP_FBC_WM_DIS;
2836 I915_WRITE(DISP_ARB_CTL, val);
2837 }
2838
2839 if (dirty & WM_DIRTY_LP(1) &&
2840 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2841 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2842
2843 if (INTEL_GEN(dev_priv) >= 7) {
2844 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2845 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2846 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2847 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2848 }
2849
2850 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2851 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2852 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2853 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2854 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2855 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2856
2857 dev_priv->wm.hw = *results;
2858 }
2859
2860 bool ilk_disable_lp_wm(struct drm_device *dev)
2861 {
2862 struct drm_i915_private *dev_priv = to_i915(dev);
2863
2864 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2865 }
2866
2867 #define SKL_SAGV_BLOCK_TIME 30 /* µs */
2868
2869 /*
2870 * FIXME: We still don't have the proper code detect if we need to apply the WA,
2871 * so assume we'll always need it in order to avoid underruns.
2872 */
2873 static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2874 {
2875 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2876
2877 if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
2878 return true;
2879
2880 return false;
2881 }
2882
2883 static bool
2884 intel_has_sagv(struct drm_i915_private *dev_priv)
2885 {
2886 if (IS_KABYLAKE(dev_priv))
2887 return true;
2888
2889 if (IS_SKYLAKE(dev_priv) &&
2890 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2891 return true;
2892
2893 return false;
2894 }
2895
2896 /*
2897 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2898 * depending on power and performance requirements. The display engine access
2899 * to system memory is blocked during the adjustment time. Because of the
2900 * blocking time, having this enabled can cause full system hangs and/or pipe
2901 * underruns if we don't meet all of the following requirements:
2902 *
2903 * - <= 1 pipe enabled
2904 * - All planes can enable watermarks for latencies >= SAGV engine block time
2905 * - We're not using an interlaced display configuration
2906 */
2907 int
2908 intel_enable_sagv(struct drm_i915_private *dev_priv)
2909 {
2910 int ret;
2911
2912 if (!intel_has_sagv(dev_priv))
2913 return 0;
2914
2915 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
2916 return 0;
2917
2918 DRM_DEBUG_KMS("Enabling the SAGV\n");
2919 mutex_lock(&dev_priv->rps.hw_lock);
2920
2921 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2922 GEN9_SAGV_ENABLE);
2923
2924 /* We don't need to wait for the SAGV when enabling */
2925 mutex_unlock(&dev_priv->rps.hw_lock);
2926
2927 /*
2928 * Some skl systems, pre-release machines in particular,
2929 * don't actually have an SAGV.
2930 */
2931 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2932 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2933 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2934 return 0;
2935 } else if (ret < 0) {
2936 DRM_ERROR("Failed to enable the SAGV\n");
2937 return ret;
2938 }
2939
2940 dev_priv->sagv_status = I915_SAGV_ENABLED;
2941 return 0;
2942 }
2943
2944 int
2945 intel_disable_sagv(struct drm_i915_private *dev_priv)
2946 {
2947 int ret;
2948
2949 if (!intel_has_sagv(dev_priv))
2950 return 0;
2951
2952 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
2953 return 0;
2954
2955 DRM_DEBUG_KMS("Disabling the SAGV\n");
2956 mutex_lock(&dev_priv->rps.hw_lock);
2957
2958 /* bspec says to keep retrying for at least 1 ms */
2959 ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2960 GEN9_SAGV_DISABLE,
2961 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
2962 1);
2963 mutex_unlock(&dev_priv->rps.hw_lock);
2964
2965 /*
2966 * Some skl systems, pre-release machines in particular,
2967 * don't actually have an SAGV.
2968 */
2969 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2970 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2971 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2972 return 0;
2973 } else if (ret < 0) {
2974 DRM_ERROR("Failed to disable the SAGV (%d)\n", ret);
2975 return ret;
2976 }
2977
2978 dev_priv->sagv_status = I915_SAGV_DISABLED;
2979 return 0;
2980 }
2981
2982 bool intel_can_enable_sagv(struct drm_atomic_state *state)
2983 {
2984 struct drm_device *dev = state->dev;
2985 struct drm_i915_private *dev_priv = to_i915(dev);
2986 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2987 struct intel_crtc *crtc;
2988 struct intel_plane *plane;
2989 struct intel_crtc_state *cstate;
2990 enum pipe pipe;
2991 int level, latency;
2992
2993 if (!intel_has_sagv(dev_priv))
2994 return false;
2995
2996 /*
2997 * SKL workaround: bspec recommends we disable the SAGV when we have
2998 * more then one pipe enabled
2999 *
3000 * If there are no active CRTCs, no additional checks need be performed
3001 */
3002 if (hweight32(intel_state->active_crtcs) == 0)
3003 return true;
3004 else if (hweight32(intel_state->active_crtcs) > 1)
3005 return false;
3006
3007 /* Since we're now guaranteed to only have one active CRTC... */
3008 pipe = ffs(intel_state->active_crtcs) - 1;
3009 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
3010 cstate = to_intel_crtc_state(crtc->base.state);
3011
3012 if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3013 return false;
3014
3015 for_each_intel_plane_on_crtc(dev, crtc, plane) {
3016 struct skl_plane_wm *wm =
3017 &cstate->wm.skl.optimal.planes[plane->id];
3018
3019 /* Skip this plane if it's not enabled */
3020 if (!wm->wm[0].plane_en)
3021 continue;
3022
3023 /* Find the highest enabled wm level for this plane */
3024 for (level = ilk_wm_max_level(dev_priv);
3025 !wm->wm[level].plane_en; --level)
3026 { }
3027
3028 latency = dev_priv->wm.skl_latency[level];
3029
3030 if (skl_needs_memory_bw_wa(intel_state) &&
3031 plane->base.state->fb->modifier ==
3032 I915_FORMAT_MOD_X_TILED)
3033 latency += 15;
3034
3035 /*
3036 * If any of the planes on this pipe don't enable wm levels
3037 * that incur memory latencies higher then 30µs we can't enable
3038 * the SAGV
3039 */
3040 if (latency < SKL_SAGV_BLOCK_TIME)
3041 return false;
3042 }
3043
3044 return true;
3045 }
3046
3047 static void
3048 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3049 const struct intel_crtc_state *cstate,
3050 struct skl_ddb_entry *alloc, /* out */
3051 int *num_active /* out */)
3052 {
3053 struct drm_atomic_state *state = cstate->base.state;
3054 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3055 struct drm_i915_private *dev_priv = to_i915(dev);
3056 struct drm_crtc *for_crtc = cstate->base.crtc;
3057 unsigned int pipe_size, ddb_size;
3058 int nth_active_pipe;
3059
3060 if (WARN_ON(!state) || !cstate->base.active) {
3061 alloc->start = 0;
3062 alloc->end = 0;
3063 *num_active = hweight32(dev_priv->active_crtcs);
3064 return;
3065 }
3066
3067 if (intel_state->active_pipe_changes)
3068 *num_active = hweight32(intel_state->active_crtcs);
3069 else
3070 *num_active = hweight32(dev_priv->active_crtcs);
3071
3072 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3073 WARN_ON(ddb_size == 0);
3074
3075 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3076
3077 /*
3078 * If the state doesn't change the active CRTC's, then there's
3079 * no need to recalculate; the existing pipe allocation limits
3080 * should remain unchanged. Note that we're safe from racing
3081 * commits since any racing commit that changes the active CRTC
3082 * list would need to grab _all_ crtc locks, including the one
3083 * we currently hold.
3084 */
3085 if (!intel_state->active_pipe_changes) {
3086 /*
3087 * alloc may be cleared by clear_intel_crtc_state,
3088 * copy from old state to be sure
3089 */
3090 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
3091 return;
3092 }
3093
3094 nth_active_pipe = hweight32(intel_state->active_crtcs &
3095 (drm_crtc_mask(for_crtc) - 1));
3096 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3097 alloc->start = nth_active_pipe * ddb_size / *num_active;
3098 alloc->end = alloc->start + pipe_size;
3099 }
3100
3101 static unsigned int skl_cursor_allocation(int num_active)
3102 {
3103 if (num_active == 1)
3104 return 32;
3105
3106 return 8;
3107 }
3108
3109 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3110 {
3111 entry->start = reg & 0x3ff;
3112 entry->end = (reg >> 16) & 0x3ff;
3113 if (entry->end)
3114 entry->end += 1;
3115 }
3116
3117 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3118 struct skl_ddb_allocation *ddb /* out */)
3119 {
3120 struct intel_crtc *crtc;
3121
3122 memset(ddb, 0, sizeof(*ddb));
3123
3124 for_each_intel_crtc(&dev_priv->drm, crtc) {
3125 enum intel_display_power_domain power_domain;
3126 enum plane_id plane_id;
3127 enum pipe pipe = crtc->pipe;
3128
3129 power_domain = POWER_DOMAIN_PIPE(pipe);
3130 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3131 continue;
3132
3133 for_each_plane_id_on_crtc(crtc, plane_id) {
3134 u32 val;
3135
3136 if (plane_id != PLANE_CURSOR)
3137 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
3138 else
3139 val = I915_READ(CUR_BUF_CFG(pipe));
3140
3141 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
3142 }
3143
3144 intel_display_power_put(dev_priv, power_domain);
3145 }
3146 }
3147
3148 /*
3149 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3150 * The bspec defines downscale amount as:
3151 *
3152 * """
3153 * Horizontal down scale amount = maximum[1, Horizontal source size /
3154 * Horizontal destination size]
3155 * Vertical down scale amount = maximum[1, Vertical source size /
3156 * Vertical destination size]
3157 * Total down scale amount = Horizontal down scale amount *
3158 * Vertical down scale amount
3159 * """
3160 *
3161 * Return value is provided in 16.16 fixed point form to retain fractional part.
3162 * Caller should take care of dividing & rounding off the value.
3163 */
3164 static uint32_t
3165 skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3166 {
3167 uint32_t downscale_h, downscale_w;
3168 uint32_t src_w, src_h, dst_w, dst_h;
3169
3170 if (WARN_ON(!pstate->base.visible))
3171 return DRM_PLANE_HELPER_NO_SCALING;
3172
3173 /* n.b., src is 16.16 fixed point, dst is whole integer */
3174 src_w = drm_rect_width(&pstate->base.src);
3175 src_h = drm_rect_height(&pstate->base.src);
3176 dst_w = drm_rect_width(&pstate->base.dst);
3177 dst_h = drm_rect_height(&pstate->base.dst);
3178 if (drm_rotation_90_or_270(pstate->base.rotation))
3179 swap(dst_w, dst_h);
3180
3181 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3182 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3183
3184 /* Provide result in 16.16 fixed point */
3185 return (uint64_t)downscale_w * downscale_h >> 16;
3186 }
3187
3188 static unsigned int
3189 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3190 const struct drm_plane_state *pstate,
3191 int y)
3192 {
3193 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3194 uint32_t down_scale_amount, data_rate;
3195 uint32_t width = 0, height = 0;
3196 struct drm_framebuffer *fb;
3197 u32 format;
3198
3199 if (!intel_pstate->base.visible)
3200 return 0;
3201
3202 fb = pstate->fb;
3203 format = fb->format->format;
3204
3205 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3206 return 0;
3207 if (y && format != DRM_FORMAT_NV12)
3208 return 0;
3209
3210 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3211 height = drm_rect_height(&intel_pstate->base.src) >> 16;
3212
3213 if (drm_rotation_90_or_270(pstate->rotation))
3214 swap(width, height);
3215
3216 /* for planar format */
3217 if (format == DRM_FORMAT_NV12) {
3218 if (y) /* y-plane data rate */
3219 data_rate = width * height *
3220 fb->format->cpp[0];
3221 else /* uv-plane data rate */
3222 data_rate = (width / 2) * (height / 2) *
3223 fb->format->cpp[1];
3224 } else {
3225 /* for packed formats */
3226 data_rate = width * height * fb->format->cpp[0];
3227 }
3228
3229 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3230
3231 return (uint64_t)data_rate * down_scale_amount >> 16;
3232 }
3233
3234 /*
3235 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3236 * a 8192x4096@32bpp framebuffer:
3237 * 3 * 4096 * 8192 * 4 < 2^32
3238 */
3239 static unsigned int
3240 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
3241 unsigned *plane_data_rate,
3242 unsigned *plane_y_data_rate)
3243 {
3244 struct drm_crtc_state *cstate = &intel_cstate->base;
3245 struct drm_atomic_state *state = cstate->state;
3246 struct drm_plane *plane;
3247 const struct drm_plane_state *pstate;
3248 unsigned int total_data_rate = 0;
3249
3250 if (WARN_ON(!state))
3251 return 0;
3252
3253 /* Calculate and cache data rate for each plane */
3254 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
3255 enum plane_id plane_id = to_intel_plane(plane)->id;
3256 unsigned int rate;
3257
3258 /* packed/uv */
3259 rate = skl_plane_relative_data_rate(intel_cstate,
3260 pstate, 0);
3261 plane_data_rate[plane_id] = rate;
3262
3263 total_data_rate += rate;
3264
3265 /* y-plane */
3266 rate = skl_plane_relative_data_rate(intel_cstate,
3267 pstate, 1);
3268 plane_y_data_rate[plane_id] = rate;
3269
3270 total_data_rate += rate;
3271 }
3272
3273 return total_data_rate;
3274 }
3275
3276 static uint16_t
3277 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3278 const int y)
3279 {
3280 struct drm_framebuffer *fb = pstate->fb;
3281 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3282 uint32_t src_w, src_h;
3283 uint32_t min_scanlines = 8;
3284 uint8_t plane_bpp;
3285
3286 if (WARN_ON(!fb))
3287 return 0;
3288
3289 /* For packed formats, no y-plane, return 0 */
3290 if (y && fb->format->format != DRM_FORMAT_NV12)
3291 return 0;
3292
3293 /* For Non Y-tile return 8-blocks */
3294 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
3295 fb->modifier != I915_FORMAT_MOD_Yf_TILED)
3296 return 8;
3297
3298 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3299 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
3300
3301 if (drm_rotation_90_or_270(pstate->rotation))
3302 swap(src_w, src_h);
3303
3304 /* Halve UV plane width and height for NV12 */
3305 if (fb->format->format == DRM_FORMAT_NV12 && !y) {
3306 src_w /= 2;
3307 src_h /= 2;
3308 }
3309
3310 if (fb->format->format == DRM_FORMAT_NV12 && !y)
3311 plane_bpp = fb->format->cpp[1];
3312 else
3313 plane_bpp = fb->format->cpp[0];
3314
3315 if (drm_rotation_90_or_270(pstate->rotation)) {
3316 switch (plane_bpp) {
3317 case 1:
3318 min_scanlines = 32;
3319 break;
3320 case 2:
3321 min_scanlines = 16;
3322 break;
3323 case 4:
3324 min_scanlines = 8;
3325 break;
3326 case 8:
3327 min_scanlines = 4;
3328 break;
3329 default:
3330 WARN(1, "Unsupported pixel depth %u for rotation",
3331 plane_bpp);
3332 min_scanlines = 32;
3333 }
3334 }
3335
3336 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3337 }
3338
3339 static void
3340 skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
3341 uint16_t *minimum, uint16_t *y_minimum)
3342 {
3343 const struct drm_plane_state *pstate;
3344 struct drm_plane *plane;
3345
3346 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
3347 enum plane_id plane_id = to_intel_plane(plane)->id;
3348
3349 if (plane_id == PLANE_CURSOR)
3350 continue;
3351
3352 if (!pstate->visible)
3353 continue;
3354
3355 minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
3356 y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
3357 }
3358
3359 minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
3360 }
3361
3362 static int
3363 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3364 struct skl_ddb_allocation *ddb /* out */)
3365 {
3366 struct drm_atomic_state *state = cstate->base.state;
3367 struct drm_crtc *crtc = cstate->base.crtc;
3368 struct drm_device *dev = crtc->dev;
3369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3370 enum pipe pipe = intel_crtc->pipe;
3371 struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
3372 uint16_t alloc_size, start;
3373 uint16_t minimum[I915_MAX_PLANES] = {};
3374 uint16_t y_minimum[I915_MAX_PLANES] = {};
3375 unsigned int total_data_rate;
3376 enum plane_id plane_id;
3377 int num_active;
3378 unsigned plane_data_rate[I915_MAX_PLANES] = {};
3379 unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
3380
3381 /* Clear the partitioning for disabled planes. */
3382 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3383 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3384
3385 if (WARN_ON(!state))
3386 return 0;
3387
3388 if (!cstate->base.active) {
3389 alloc->start = alloc->end = 0;
3390 return 0;
3391 }
3392
3393 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3394 alloc_size = skl_ddb_entry_size(alloc);
3395 if (alloc_size == 0) {
3396 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3397 return 0;
3398 }
3399
3400 skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
3401
3402 /*
3403 * 1. Allocate the mininum required blocks for each active plane
3404 * and allocate the cursor, it doesn't require extra allocation
3405 * proportional to the data rate.
3406 */
3407
3408 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
3409 alloc_size -= minimum[plane_id];
3410 alloc_size -= y_minimum[plane_id];
3411 }
3412
3413 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
3414 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3415
3416 /*
3417 * 2. Distribute the remaining space in proportion to the amount of
3418 * data each plane needs to fetch from memory.
3419 *
3420 * FIXME: we may not allocate every single block here.
3421 */
3422 total_data_rate = skl_get_total_relative_data_rate(cstate,
3423 plane_data_rate,
3424 plane_y_data_rate);
3425 if (total_data_rate == 0)
3426 return 0;
3427
3428 start = alloc->start;
3429 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
3430 unsigned int data_rate, y_data_rate;
3431 uint16_t plane_blocks, y_plane_blocks = 0;
3432
3433 if (plane_id == PLANE_CURSOR)
3434 continue;
3435
3436 data_rate = plane_data_rate[plane_id];
3437
3438 /*
3439 * allocation for (packed formats) or (uv-plane part of planar format):
3440 * promote the expression to 64 bits to avoid overflowing, the
3441 * result is < available as data_rate / total_data_rate < 1
3442 */
3443 plane_blocks = minimum[plane_id];
3444 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3445 total_data_rate);
3446
3447 /* Leave disabled planes at (0,0) */
3448 if (data_rate) {
3449 ddb->plane[pipe][plane_id].start = start;
3450 ddb->plane[pipe][plane_id].end = start + plane_blocks;
3451 }
3452
3453 start += plane_blocks;
3454
3455 /*
3456 * allocation for y_plane part of planar format:
3457 */
3458 y_data_rate = plane_y_data_rate[plane_id];
3459
3460 y_plane_blocks = y_minimum[plane_id];
3461 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3462 total_data_rate);
3463
3464 if (y_data_rate) {
3465 ddb->y_plane[pipe][plane_id].start = start;
3466 ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
3467 }
3468
3469 start += y_plane_blocks;
3470 }
3471
3472 return 0;
3473 }
3474
3475 /*
3476 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3477 * for the read latency) and cpp should always be <= 8, so that
3478 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3479 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3480 */
3481 static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp,
3482 uint32_t latency)
3483 {
3484 uint32_t wm_intermediate_val;
3485 uint_fixed_16_16_t ret;
3486
3487 if (latency == 0)
3488 return FP_16_16_MAX;
3489
3490 wm_intermediate_val = latency * pixel_rate * cpp;
3491 ret = fixed_16_16_div_round_up_u64(wm_intermediate_val, 1000 * 512);
3492 return ret;
3493 }
3494
3495 static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
3496 uint32_t pipe_htotal,
3497 uint32_t latency,
3498 uint_fixed_16_16_t plane_blocks_per_line)
3499 {
3500 uint32_t wm_intermediate_val;
3501 uint_fixed_16_16_t ret;
3502
3503 if (latency == 0)
3504 return FP_16_16_MAX;
3505
3506 wm_intermediate_val = latency * pixel_rate;
3507 wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,
3508 pipe_htotal * 1000);
3509 ret = mul_u32_fixed_16_16(wm_intermediate_val, plane_blocks_per_line);
3510 return ret;
3511 }
3512
3513 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3514 struct intel_plane_state *pstate)
3515 {
3516 uint64_t adjusted_pixel_rate;
3517 uint64_t downscale_amount;
3518 uint64_t pixel_rate;
3519
3520 /* Shouldn't reach here on disabled planes... */
3521 if (WARN_ON(!pstate->base.visible))
3522 return 0;
3523
3524 /*
3525 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3526 * with additional adjustments for plane-specific scaling.
3527 */
3528 adjusted_pixel_rate = cstate->pixel_rate;
3529 downscale_amount = skl_plane_downscale_amount(pstate);
3530
3531 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3532 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3533
3534 return pixel_rate;
3535 }
3536
3537 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3538 struct intel_crtc_state *cstate,
3539 struct intel_plane_state *intel_pstate,
3540 uint16_t ddb_allocation,
3541 int level,
3542 uint16_t *out_blocks, /* out */
3543 uint8_t *out_lines, /* out */
3544 bool *enabled /* out */)
3545 {
3546 struct drm_plane_state *pstate = &intel_pstate->base;
3547 struct drm_framebuffer *fb = pstate->fb;
3548 uint32_t latency = dev_priv->wm.skl_latency[level];
3549 uint_fixed_16_16_t method1, method2;
3550 uint_fixed_16_16_t plane_blocks_per_line;
3551 uint_fixed_16_16_t selected_result;
3552 uint32_t interm_pbpl;
3553 uint32_t plane_bytes_per_line;
3554 uint32_t res_blocks, res_lines;
3555 uint8_t cpp;
3556 uint32_t width = 0, height = 0;
3557 uint32_t plane_pixel_rate;
3558 uint_fixed_16_16_t y_tile_minimum;
3559 uint32_t y_min_scanlines;
3560 struct intel_atomic_state *state =
3561 to_intel_atomic_state(cstate->base.state);
3562 bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
3563 bool y_tiled, x_tiled;
3564
3565 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
3566 *enabled = false;
3567 return 0;
3568 }
3569
3570 y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
3571 fb->modifier == I915_FORMAT_MOD_Yf_TILED;
3572 x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
3573
3574 /* Display WA #1141: kbl. */
3575 if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled)
3576 latency += 4;
3577
3578 if (apply_memory_bw_wa && x_tiled)
3579 latency += 15;
3580
3581 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3582 height = drm_rect_height(&intel_pstate->base.src) >> 16;
3583
3584 if (drm_rotation_90_or_270(pstate->rotation))
3585 swap(width, height);
3586
3587 cpp = fb->format->cpp[0];
3588 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3589
3590 if (drm_rotation_90_or_270(pstate->rotation)) {
3591 int cpp = (fb->format->format == DRM_FORMAT_NV12) ?
3592 fb->format->cpp[1] :
3593 fb->format->cpp[0];
3594
3595 switch (cpp) {
3596 case 1:
3597 y_min_scanlines = 16;
3598 break;
3599 case 2:
3600 y_min_scanlines = 8;
3601 break;
3602 case 4:
3603 y_min_scanlines = 4;
3604 break;
3605 default:
3606 MISSING_CASE(cpp);
3607 return -EINVAL;
3608 }
3609 } else {
3610 y_min_scanlines = 4;
3611 }
3612
3613 if (apply_memory_bw_wa)
3614 y_min_scanlines *= 2;
3615
3616 plane_bytes_per_line = width * cpp;
3617 if (y_tiled) {
3618 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line *
3619 y_min_scanlines, 512);
3620 plane_blocks_per_line =
3621 fixed_16_16_div_round_up(interm_pbpl, y_min_scanlines);
3622 } else if (x_tiled) {
3623 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512);
3624 plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl);
3625 } else {
3626 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
3627 plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl);
3628 }
3629
3630 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3631 method2 = skl_wm_method2(plane_pixel_rate,
3632 cstate->base.adjusted_mode.crtc_htotal,
3633 latency,
3634 plane_blocks_per_line);
3635
3636 y_tile_minimum = mul_u32_fixed_16_16(y_min_scanlines,
3637 plane_blocks_per_line);
3638
3639 if (y_tiled) {
3640 selected_result = max_fixed_16_16(method2, y_tile_minimum);
3641 } else {
3642 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3643 (plane_bytes_per_line / 512 < 1))
3644 selected_result = method2;
3645 else if ((ddb_allocation /
3646 fixed_16_16_to_u32_round_up(plane_blocks_per_line)) >= 1)
3647 selected_result = min_fixed_16_16(method1, method2);
3648 else
3649 selected_result = method1;
3650 }
3651
3652 res_blocks = fixed_16_16_to_u32_round_up(selected_result) + 1;
3653 res_lines = DIV_ROUND_UP(selected_result.val,
3654 plane_blocks_per_line.val);
3655
3656 if (level >= 1 && level <= 7) {
3657 if (y_tiled) {
3658 res_blocks += fixed_16_16_to_u32_round_up(y_tile_minimum);
3659 res_lines += y_min_scanlines;
3660 } else {
3661 res_blocks++;
3662 }
3663 }
3664
3665 if (res_blocks >= ddb_allocation || res_lines > 31) {
3666 *enabled = false;
3667
3668 /*
3669 * If there are no valid level 0 watermarks, then we can't
3670 * support this display configuration.
3671 */
3672 if (level) {
3673 return 0;
3674 } else {
3675 struct drm_plane *plane = pstate->plane;
3676
3677 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3678 DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n",
3679 plane->base.id, plane->name,
3680 res_blocks, ddb_allocation, res_lines);
3681 return -EINVAL;
3682 }
3683 }
3684
3685 *out_blocks = res_blocks;
3686 *out_lines = res_lines;
3687 *enabled = true;
3688
3689 return 0;
3690 }
3691
3692 static int
3693 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3694 struct skl_ddb_allocation *ddb,
3695 struct intel_crtc_state *cstate,
3696 struct intel_plane *intel_plane,
3697 int level,
3698 struct skl_wm_level *result)
3699 {
3700 struct drm_atomic_state *state = cstate->base.state;
3701 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3702 struct drm_plane *plane = &intel_plane->base;
3703 struct intel_plane_state *intel_pstate = NULL;
3704 uint16_t ddb_blocks;
3705 enum pipe pipe = intel_crtc->pipe;
3706 int ret;
3707
3708 if (state)
3709 intel_pstate =
3710 intel_atomic_get_existing_plane_state(state,
3711 intel_plane);
3712
3713 /*
3714 * Note: If we start supporting multiple pending atomic commits against
3715 * the same planes/CRTC's in the future, plane->state will no longer be
3716 * the correct pre-state to use for the calculations here and we'll
3717 * need to change where we get the 'unchanged' plane data from.
3718 *
3719 * For now this is fine because we only allow one queued commit against
3720 * a CRTC. Even if the plane isn't modified by this transaction and we
3721 * don't have a plane lock, we still have the CRTC's lock, so we know
3722 * that no other transactions are racing with us to update it.
3723 */
3724 if (!intel_pstate)
3725 intel_pstate = to_intel_plane_state(plane->state);
3726
3727 WARN_ON(!intel_pstate->base.fb);
3728
3729 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
3730
3731 ret = skl_compute_plane_wm(dev_priv,
3732 cstate,
3733 intel_pstate,
3734 ddb_blocks,
3735 level,
3736 &result->plane_res_b,
3737 &result->plane_res_l,
3738 &result->plane_en);
3739 if (ret)
3740 return ret;
3741
3742 return 0;
3743 }
3744
3745 static uint32_t
3746 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3747 {
3748 struct drm_atomic_state *state = cstate->base.state;
3749 struct drm_i915_private *dev_priv = to_i915(state->dev);
3750 uint32_t pixel_rate;
3751 uint32_t linetime_wm;
3752
3753 if (!cstate->base.active)
3754 return 0;
3755
3756 pixel_rate = cstate->pixel_rate;
3757
3758 if (WARN_ON(pixel_rate == 0))
3759 return 0;
3760
3761 linetime_wm = DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal *
3762 1000, pixel_rate);
3763
3764 /* Display WA #1135: bxt. */
3765 if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled)
3766 linetime_wm = DIV_ROUND_UP(linetime_wm, 2);
3767
3768 return linetime_wm;
3769 }
3770
3771 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3772 struct skl_wm_level *trans_wm /* out */)
3773 {
3774 if (!cstate->base.active)
3775 return;
3776
3777 /* Until we know more, just disable transition WMs */
3778 trans_wm->plane_en = false;
3779 }
3780
3781 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3782 struct skl_ddb_allocation *ddb,
3783 struct skl_pipe_wm *pipe_wm)
3784 {
3785 struct drm_device *dev = cstate->base.crtc->dev;
3786 const struct drm_i915_private *dev_priv = to_i915(dev);
3787 struct intel_plane *intel_plane;
3788 struct skl_plane_wm *wm;
3789 int level, max_level = ilk_wm_max_level(dev_priv);
3790 int ret;
3791
3792 /*
3793 * We'll only calculate watermarks for planes that are actually
3794 * enabled, so make sure all other planes are set as disabled.
3795 */
3796 memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3797
3798 for_each_intel_plane_mask(&dev_priv->drm,
3799 intel_plane,
3800 cstate->base.plane_mask) {
3801 wm = &pipe_wm->planes[intel_plane->id];
3802
3803 for (level = 0; level <= max_level; level++) {
3804 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3805 intel_plane, level,
3806 &wm->wm[level]);
3807 if (ret)
3808 return ret;
3809 }
3810 skl_compute_transition_wm(cstate, &wm->trans_wm);
3811 }
3812 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3813
3814 return 0;
3815 }
3816
3817 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3818 i915_reg_t reg,
3819 const struct skl_ddb_entry *entry)
3820 {
3821 if (entry->end)
3822 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3823 else
3824 I915_WRITE(reg, 0);
3825 }
3826
3827 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
3828 i915_reg_t reg,
3829 const struct skl_wm_level *level)
3830 {
3831 uint32_t val = 0;
3832
3833 if (level->plane_en) {
3834 val |= PLANE_WM_EN;
3835 val |= level->plane_res_b;
3836 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
3837 }
3838
3839 I915_WRITE(reg, val);
3840 }
3841
3842 static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3843 const struct skl_plane_wm *wm,
3844 const struct skl_ddb_allocation *ddb,
3845 enum plane_id plane_id)
3846 {
3847 struct drm_crtc *crtc = &intel_crtc->base;
3848 struct drm_device *dev = crtc->dev;
3849 struct drm_i915_private *dev_priv = to_i915(dev);
3850 int level, max_level = ilk_wm_max_level(dev_priv);
3851 enum pipe pipe = intel_crtc->pipe;
3852
3853 for (level = 0; level <= max_level; level++) {
3854 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
3855 &wm->wm[level]);
3856 }
3857 skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
3858 &wm->trans_wm);
3859
3860 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
3861 &ddb->plane[pipe][plane_id]);
3862 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
3863 &ddb->y_plane[pipe][plane_id]);
3864 }
3865
3866 static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3867 const struct skl_plane_wm *wm,
3868 const struct skl_ddb_allocation *ddb)
3869 {
3870 struct drm_crtc *crtc = &intel_crtc->base;
3871 struct drm_device *dev = crtc->dev;
3872 struct drm_i915_private *dev_priv = to_i915(dev);
3873 int level, max_level = ilk_wm_max_level(dev_priv);
3874 enum pipe pipe = intel_crtc->pipe;
3875
3876 for (level = 0; level <= max_level; level++) {
3877 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
3878 &wm->wm[level]);
3879 }
3880 skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
3881
3882 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3883 &ddb->plane[pipe][PLANE_CURSOR]);
3884 }
3885
3886 bool skl_wm_level_equals(const struct skl_wm_level *l1,
3887 const struct skl_wm_level *l2)
3888 {
3889 if (l1->plane_en != l2->plane_en)
3890 return false;
3891
3892 /* If both planes aren't enabled, the rest shouldn't matter */
3893 if (!l1->plane_en)
3894 return true;
3895
3896 return (l1->plane_res_l == l2->plane_res_l &&
3897 l1->plane_res_b == l2->plane_res_b);
3898 }
3899
3900 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3901 const struct skl_ddb_entry *b)
3902 {
3903 return a->start < b->end && b->start < a->end;
3904 }
3905
3906 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
3907 const struct skl_ddb_entry *ddb,
3908 int ignore)
3909 {
3910 int i;
3911
3912 for (i = 0; i < I915_MAX_PIPES; i++)
3913 if (i != ignore && entries[i] &&
3914 skl_ddb_entries_overlap(ddb, entries[i]))
3915 return true;
3916
3917 return false;
3918 }
3919
3920 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3921 const struct skl_pipe_wm *old_pipe_wm,
3922 struct skl_pipe_wm *pipe_wm, /* out */
3923 struct skl_ddb_allocation *ddb, /* out */
3924 bool *changed /* out */)
3925 {
3926 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3927 int ret;
3928
3929 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3930 if (ret)
3931 return ret;
3932
3933 if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
3934 *changed = false;
3935 else
3936 *changed = true;
3937
3938 return 0;
3939 }
3940
3941 static uint32_t
3942 pipes_modified(struct drm_atomic_state *state)
3943 {
3944 struct drm_crtc *crtc;
3945 struct drm_crtc_state *cstate;
3946 uint32_t i, ret = 0;
3947
3948 for_each_crtc_in_state(state, crtc, cstate, i)
3949 ret |= drm_crtc_mask(crtc);
3950
3951 return ret;
3952 }
3953
3954 static int
3955 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3956 {
3957 struct drm_atomic_state *state = cstate->base.state;
3958 struct drm_device *dev = state->dev;
3959 struct drm_crtc *crtc = cstate->base.crtc;
3960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3961 struct drm_i915_private *dev_priv = to_i915(dev);
3962 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3963 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3964 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3965 struct drm_plane_state *plane_state;
3966 struct drm_plane *plane;
3967 enum pipe pipe = intel_crtc->pipe;
3968
3969 WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3970
3971 drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
3972 enum plane_id plane_id = to_intel_plane(plane)->id;
3973
3974 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
3975 &new_ddb->plane[pipe][plane_id]) &&
3976 skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
3977 &new_ddb->y_plane[pipe][plane_id]))
3978 continue;
3979
3980 plane_state = drm_atomic_get_plane_state(state, plane);
3981 if (IS_ERR(plane_state))
3982 return PTR_ERR(plane_state);
3983 }
3984
3985 return 0;
3986 }
3987
3988 static int
3989 skl_compute_ddb(struct drm_atomic_state *state)
3990 {
3991 struct drm_device *dev = state->dev;
3992 struct drm_i915_private *dev_priv = to_i915(dev);
3993 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3994 struct intel_crtc *intel_crtc;
3995 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
3996 uint32_t realloc_pipes = pipes_modified(state);
3997 int ret;
3998
3999 /*
4000 * If this is our first atomic update following hardware readout,
4001 * we can't trust the DDB that the BIOS programmed for us. Let's
4002 * pretend that all pipes switched active status so that we'll
4003 * ensure a full DDB recompute.
4004 */
4005 if (dev_priv->wm.distrust_bios_wm) {
4006 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4007 state->acquire_ctx);
4008 if (ret)
4009 return ret;
4010
4011 intel_state->active_pipe_changes = ~0;
4012
4013 /*
4014 * We usually only initialize intel_state->active_crtcs if we
4015 * we're doing a modeset; make sure this field is always
4016 * initialized during the sanitization process that happens
4017 * on the first commit too.
4018 */
4019 if (!intel_state->modeset)
4020 intel_state->active_crtcs = dev_priv->active_crtcs;
4021 }
4022
4023 /*
4024 * If the modeset changes which CRTC's are active, we need to
4025 * recompute the DDB allocation for *all* active pipes, even
4026 * those that weren't otherwise being modified in any way by this
4027 * atomic commit. Due to the shrinking of the per-pipe allocations
4028 * when new active CRTC's are added, it's possible for a pipe that
4029 * we were already using and aren't changing at all here to suddenly
4030 * become invalid if its DDB needs exceeds its new allocation.
4031 *
4032 * Note that if we wind up doing a full DDB recompute, we can't let
4033 * any other display updates race with this transaction, so we need
4034 * to grab the lock on *all* CRTC's.
4035 */
4036 if (intel_state->active_pipe_changes) {
4037 realloc_pipes = ~0;
4038 intel_state->wm_results.dirty_pipes = ~0;
4039 }
4040
4041 /*
4042 * We're not recomputing for the pipes not included in the commit, so
4043 * make sure we start with the current state.
4044 */
4045 memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4046
4047 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4048 struct intel_crtc_state *cstate;
4049
4050 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4051 if (IS_ERR(cstate))
4052 return PTR_ERR(cstate);
4053
4054 ret = skl_allocate_pipe_ddb(cstate, ddb);
4055 if (ret)
4056 return ret;
4057
4058 ret = skl_ddb_add_affected_planes(cstate);
4059 if (ret)
4060 return ret;
4061 }
4062
4063 return 0;
4064 }
4065
4066 static void
4067 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4068 struct skl_wm_values *src,
4069 enum pipe pipe)
4070 {
4071 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4072 sizeof(dst->ddb.y_plane[pipe]));
4073 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4074 sizeof(dst->ddb.plane[pipe]));
4075 }
4076
4077 static void
4078 skl_print_wm_changes(const struct drm_atomic_state *state)
4079 {
4080 const struct drm_device *dev = state->dev;
4081 const struct drm_i915_private *dev_priv = to_i915(dev);
4082 const struct intel_atomic_state *intel_state =
4083 to_intel_atomic_state(state);
4084 const struct drm_crtc *crtc;
4085 const struct drm_crtc_state *cstate;
4086 const struct intel_plane *intel_plane;
4087 const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4088 const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4089 int i;
4090
4091 for_each_crtc_in_state(state, crtc, cstate, i) {
4092 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4093 enum pipe pipe = intel_crtc->pipe;
4094
4095 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4096 enum plane_id plane_id = intel_plane->id;
4097 const struct skl_ddb_entry *old, *new;
4098
4099 old = &old_ddb->plane[pipe][plane_id];
4100 new = &new_ddb->plane[pipe][plane_id];
4101
4102 if (skl_ddb_entry_equal(old, new))
4103 continue;
4104
4105 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4106 intel_plane->base.base.id,
4107 intel_plane->base.name,
4108 old->start, old->end,
4109 new->start, new->end);
4110 }
4111 }
4112 }
4113
4114 static int
4115 skl_compute_wm(struct drm_atomic_state *state)
4116 {
4117 struct drm_crtc *crtc;
4118 struct drm_crtc_state *cstate;
4119 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4120 struct skl_wm_values *results = &intel_state->wm_results;
4121 struct skl_pipe_wm *pipe_wm;
4122 bool changed = false;
4123 int ret, i;
4124
4125 /*
4126 * If this transaction isn't actually touching any CRTC's, don't
4127 * bother with watermark calculation. Note that if we pass this
4128 * test, we're guaranteed to hold at least one CRTC state mutex,
4129 * which means we can safely use values like dev_priv->active_crtcs
4130 * since any racing commits that want to update them would need to
4131 * hold _all_ CRTC state mutexes.
4132 */
4133 for_each_crtc_in_state(state, crtc, cstate, i)
4134 changed = true;
4135 if (!changed)
4136 return 0;
4137
4138 /* Clear all dirty flags */
4139 results->dirty_pipes = 0;
4140
4141 ret = skl_compute_ddb(state);
4142 if (ret)
4143 return ret;
4144
4145 /*
4146 * Calculate WM's for all pipes that are part of this transaction.
4147 * Note that the DDB allocation above may have added more CRTC's that
4148 * weren't otherwise being modified (and set bits in dirty_pipes) if
4149 * pipe allocations had to change.
4150 *
4151 * FIXME: Now that we're doing this in the atomic check phase, we
4152 * should allow skl_update_pipe_wm() to return failure in cases where
4153 * no suitable watermark values can be found.
4154 */
4155 for_each_crtc_in_state(state, crtc, cstate, i) {
4156 struct intel_crtc_state *intel_cstate =
4157 to_intel_crtc_state(cstate);
4158 const struct skl_pipe_wm *old_pipe_wm =
4159 &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
4160
4161 pipe_wm = &intel_cstate->wm.skl.optimal;
4162 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
4163 &results->ddb, &changed);
4164 if (ret)
4165 return ret;
4166
4167 if (changed)
4168 results->dirty_pipes |= drm_crtc_mask(crtc);
4169
4170 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4171 /* This pipe's WM's did not change */
4172 continue;
4173
4174 intel_cstate->update_wm_pre = true;
4175 }
4176
4177 skl_print_wm_changes(state);
4178
4179 return 0;
4180 }
4181
4182 static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
4183 struct intel_crtc_state *cstate)
4184 {
4185 struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
4186 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4187 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4188 const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
4189 enum pipe pipe = crtc->pipe;
4190 enum plane_id plane_id;
4191
4192 if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
4193 return;
4194
4195 I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
4196
4197 for_each_plane_id_on_crtc(crtc, plane_id) {
4198 if (plane_id != PLANE_CURSOR)
4199 skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id],
4200 ddb, plane_id);
4201 else
4202 skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id],
4203 ddb);
4204 }
4205 }
4206
4207 static void skl_initial_wm(struct intel_atomic_state *state,
4208 struct intel_crtc_state *cstate)
4209 {
4210 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4211 struct drm_device *dev = intel_crtc->base.dev;
4212 struct drm_i915_private *dev_priv = to_i915(dev);
4213 struct skl_wm_values *results = &state->wm_results;
4214 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4215 enum pipe pipe = intel_crtc->pipe;
4216
4217 if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
4218 return;
4219
4220 mutex_lock(&dev_priv->wm.wm_mutex);
4221
4222 if (cstate->base.active_changed)
4223 skl_atomic_update_crtc_wm(state, cstate);
4224
4225 skl_copy_wm_for_pipe(hw_vals, results, pipe);
4226
4227 mutex_unlock(&dev_priv->wm.wm_mutex);
4228 }
4229
4230 static void ilk_compute_wm_config(struct drm_device *dev,
4231 struct intel_wm_config *config)
4232 {
4233 struct intel_crtc *crtc;
4234
4235 /* Compute the currently _active_ config */
4236 for_each_intel_crtc(dev, crtc) {
4237 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4238
4239 if (!wm->pipe_enabled)
4240 continue;
4241
4242 config->sprites_enabled |= wm->sprites_enabled;
4243 config->sprites_scaled |= wm->sprites_scaled;
4244 config->num_pipes_active++;
4245 }
4246 }
4247
4248 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4249 {
4250 struct drm_device *dev = &dev_priv->drm;
4251 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4252 struct ilk_wm_maximums max;
4253 struct intel_wm_config config = {};
4254 struct ilk_wm_values results = {};
4255 enum intel_ddb_partitioning partitioning;
4256
4257 ilk_compute_wm_config(dev, &config);
4258
4259 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4260 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4261
4262 /* 5/6 split only in single pipe config on IVB+ */
4263 if (INTEL_GEN(dev_priv) >= 7 &&
4264 config.num_pipes_active == 1 && config.sprites_enabled) {
4265 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4266 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4267
4268 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4269 } else {
4270 best_lp_wm = &lp_wm_1_2;
4271 }
4272
4273 partitioning = (best_lp_wm == &lp_wm_1_2) ?
4274 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4275
4276 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4277
4278 ilk_write_wm_values(dev_priv, &results);
4279 }
4280
4281 static void ilk_initial_watermarks(struct intel_atomic_state *state,
4282 struct intel_crtc_state *cstate)
4283 {
4284 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4285 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4286
4287 mutex_lock(&dev_priv->wm.wm_mutex);
4288 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4289 ilk_program_watermarks(dev_priv);
4290 mutex_unlock(&dev_priv->wm.wm_mutex);
4291 }
4292
4293 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
4294 struct intel_crtc_state *cstate)
4295 {
4296 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4297 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4298
4299 mutex_lock(&dev_priv->wm.wm_mutex);
4300 if (cstate->wm.need_postvbl_update) {
4301 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4302 ilk_program_watermarks(dev_priv);
4303 }
4304 mutex_unlock(&dev_priv->wm.wm_mutex);
4305 }
4306
4307 static inline void skl_wm_level_from_reg_val(uint32_t val,
4308 struct skl_wm_level *level)
4309 {
4310 level->plane_en = val & PLANE_WM_EN;
4311 level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4312 level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
4313 PLANE_WM_LINES_MASK;
4314 }
4315
4316 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
4317 struct skl_pipe_wm *out)
4318 {
4319 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4321 enum pipe pipe = intel_crtc->pipe;
4322 int level, max_level;
4323 enum plane_id plane_id;
4324 uint32_t val;
4325
4326 max_level = ilk_wm_max_level(dev_priv);
4327
4328 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4329 struct skl_plane_wm *wm = &out->planes[plane_id];
4330
4331 for (level = 0; level <= max_level; level++) {
4332 if (plane_id != PLANE_CURSOR)
4333 val = I915_READ(PLANE_WM(pipe, plane_id, level));
4334 else
4335 val = I915_READ(CUR_WM(pipe, level));
4336
4337 skl_wm_level_from_reg_val(val, &wm->wm[level]);
4338 }
4339
4340 if (plane_id != PLANE_CURSOR)
4341 val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
4342 else
4343 val = I915_READ(CUR_WM_TRANS(pipe));
4344
4345 skl_wm_level_from_reg_val(val, &wm->trans_wm);
4346 }
4347
4348 if (!intel_crtc->active)
4349 return;
4350
4351 out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
4352 }
4353
4354 void skl_wm_get_hw_state(struct drm_device *dev)
4355 {
4356 struct drm_i915_private *dev_priv = to_i915(dev);
4357 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4358 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4359 struct drm_crtc *crtc;
4360 struct intel_crtc *intel_crtc;
4361 struct intel_crtc_state *cstate;
4362
4363 skl_ddb_get_hw_state(dev_priv, ddb);
4364 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4365 intel_crtc = to_intel_crtc(crtc);
4366 cstate = to_intel_crtc_state(crtc->state);
4367
4368 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
4369
4370 if (intel_crtc->active)
4371 hw->dirty_pipes |= drm_crtc_mask(crtc);
4372 }
4373
4374 if (dev_priv->active_crtcs) {
4375 /* Fully recompute DDB on first atomic commit */
4376 dev_priv->wm.distrust_bios_wm = true;
4377 } else {
4378 /* Easy/common case; just sanitize DDB now if everything off */
4379 memset(ddb, 0, sizeof(*ddb));
4380 }
4381 }
4382
4383 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4384 {
4385 struct drm_device *dev = crtc->dev;
4386 struct drm_i915_private *dev_priv = to_i915(dev);
4387 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4389 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4390 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4391 enum pipe pipe = intel_crtc->pipe;
4392 static const i915_reg_t wm0_pipe_reg[] = {
4393 [PIPE_A] = WM0_PIPEA_ILK,
4394 [PIPE_B] = WM0_PIPEB_ILK,
4395 [PIPE_C] = WM0_PIPEC_IVB,
4396 };
4397
4398 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4399 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4400 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4401
4402 memset(active, 0, sizeof(*active));
4403
4404 active->pipe_enabled = intel_crtc->active;
4405
4406 if (active->pipe_enabled) {
4407 u32 tmp = hw->wm_pipe[pipe];
4408
4409 /*
4410 * For active pipes LP0 watermark is marked as
4411 * enabled, and LP1+ watermaks as disabled since
4412 * we can't really reverse compute them in case
4413 * multiple pipes are active.
4414 */
4415 active->wm[0].enable = true;
4416 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4417 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4418 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4419 active->linetime = hw->wm_linetime[pipe];
4420 } else {
4421 int level, max_level = ilk_wm_max_level(dev_priv);
4422
4423 /*
4424 * For inactive pipes, all watermark levels
4425 * should be marked as enabled but zeroed,
4426 * which is what we'd compute them to.
4427 */
4428 for (level = 0; level <= max_level; level++)
4429 active->wm[level].enable = true;
4430 }
4431
4432 intel_crtc->wm.active.ilk = *active;
4433 }
4434
4435 #define _FW_WM(value, plane) \
4436 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4437 #define _FW_WM_VLV(value, plane) \
4438 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4439
4440 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4441 struct vlv_wm_values *wm)
4442 {
4443 enum pipe pipe;
4444 uint32_t tmp;
4445
4446 for_each_pipe(dev_priv, pipe) {
4447 tmp = I915_READ(VLV_DDL(pipe));
4448
4449 wm->ddl[pipe].plane[PLANE_PRIMARY] =
4450 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4451 wm->ddl[pipe].plane[PLANE_CURSOR] =
4452 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4453 wm->ddl[pipe].plane[PLANE_SPRITE0] =
4454 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4455 wm->ddl[pipe].plane[PLANE_SPRITE1] =
4456 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4457 }
4458
4459 tmp = I915_READ(DSPFW1);
4460 wm->sr.plane = _FW_WM(tmp, SR);
4461 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
4462 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
4463 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
4464
4465 tmp = I915_READ(DSPFW2);
4466 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
4467 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
4468 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
4469
4470 tmp = I915_READ(DSPFW3);
4471 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4472
4473 if (IS_CHERRYVIEW(dev_priv)) {
4474 tmp = I915_READ(DSPFW7_CHV);
4475 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
4476 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
4477
4478 tmp = I915_READ(DSPFW8_CHV);
4479 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
4480 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
4481
4482 tmp = I915_READ(DSPFW9_CHV);
4483 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
4484 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
4485
4486 tmp = I915_READ(DSPHOWM);
4487 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4488 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4489 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4490 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
4491 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4492 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4493 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
4494 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4495 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4496 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
4497 } else {
4498 tmp = I915_READ(DSPFW7);
4499 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
4500 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
4501
4502 tmp = I915_READ(DSPHOWM);
4503 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4504 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4505 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4506 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
4507 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4508 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4509 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
4510 }
4511 }
4512
4513 #undef _FW_WM
4514 #undef _FW_WM_VLV
4515
4516 void vlv_wm_get_hw_state(struct drm_device *dev)
4517 {
4518 struct drm_i915_private *dev_priv = to_i915(dev);
4519 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4520 struct intel_plane *plane;
4521 enum pipe pipe;
4522 u32 val;
4523
4524 vlv_read_wm_values(dev_priv, wm);
4525
4526 for_each_intel_plane(dev, plane)
4527 plane->wm.fifo_size = vlv_get_fifo_size(plane);
4528
4529 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4530 wm->level = VLV_WM_LEVEL_PM2;
4531
4532 if (IS_CHERRYVIEW(dev_priv)) {
4533 mutex_lock(&dev_priv->rps.hw_lock);
4534
4535 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4536 if (val & DSP_MAXFIFO_PM5_ENABLE)
4537 wm->level = VLV_WM_LEVEL_PM5;
4538
4539 /*
4540 * If DDR DVFS is disabled in the BIOS, Punit
4541 * will never ack the request. So if that happens
4542 * assume we don't have to enable/disable DDR DVFS
4543 * dynamically. To test that just set the REQ_ACK
4544 * bit to poke the Punit, but don't change the
4545 * HIGH/LOW bits so that we don't actually change
4546 * the current state.
4547 */
4548 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4549 val |= FORCE_DDR_FREQ_REQ_ACK;
4550 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4551
4552 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4553 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4554 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4555 "assuming DDR DVFS is disabled\n");
4556 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4557 } else {
4558 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4559 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4560 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4561 }
4562
4563 mutex_unlock(&dev_priv->rps.hw_lock);
4564 }
4565
4566 for_each_pipe(dev_priv, pipe)
4567 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4568 pipe_name(pipe),
4569 wm->pipe[pipe].plane[PLANE_PRIMARY],
4570 wm->pipe[pipe].plane[PLANE_CURSOR],
4571 wm->pipe[pipe].plane[PLANE_SPRITE0],
4572 wm->pipe[pipe].plane[PLANE_SPRITE1]);
4573
4574 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4575 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4576 }
4577
4578 void ilk_wm_get_hw_state(struct drm_device *dev)
4579 {
4580 struct drm_i915_private *dev_priv = to_i915(dev);
4581 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4582 struct drm_crtc *crtc;
4583
4584 for_each_crtc(dev, crtc)
4585 ilk_pipe_wm_get_hw_state(crtc);
4586
4587 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4588 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4589 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4590
4591 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4592 if (INTEL_GEN(dev_priv) >= 7) {
4593 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4594 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4595 }
4596
4597 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4598 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4599 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4600 else if (IS_IVYBRIDGE(dev_priv))
4601 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4602 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4603
4604 hw->enable_fbc_wm =
4605 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4606 }
4607
4608 /**
4609 * intel_update_watermarks - update FIFO watermark values based on current modes
4610 *
4611 * Calculate watermark values for the various WM regs based on current mode
4612 * and plane configuration.
4613 *
4614 * There are several cases to deal with here:
4615 * - normal (i.e. non-self-refresh)
4616 * - self-refresh (SR) mode
4617 * - lines are large relative to FIFO size (buffer can hold up to 2)
4618 * - lines are small relative to FIFO size (buffer can hold more than 2
4619 * lines), so need to account for TLB latency
4620 *
4621 * The normal calculation is:
4622 * watermark = dotclock * bytes per pixel * latency
4623 * where latency is platform & configuration dependent (we assume pessimal
4624 * values here).
4625 *
4626 * The SR calculation is:
4627 * watermark = (trunc(latency/line time)+1) * surface width *
4628 * bytes per pixel
4629 * where
4630 * line time = htotal / dotclock
4631 * surface width = hdisplay for normal plane and 64 for cursor
4632 * and latency is assumed to be high, as above.
4633 *
4634 * The final value programmed to the register should always be rounded up,
4635 * and include an extra 2 entries to account for clock crossings.
4636 *
4637 * We don't use the sprite, so we can ignore that. And on Crestline we have
4638 * to set the non-SR watermarks to 8.
4639 */
4640 void intel_update_watermarks(struct intel_crtc *crtc)
4641 {
4642 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4643
4644 if (dev_priv->display.update_wm)
4645 dev_priv->display.update_wm(crtc);
4646 }
4647
4648 /*
4649 * Lock protecting IPS related data structures
4650 */
4651 DEFINE_SPINLOCK(mchdev_lock);
4652
4653 /* Global for IPS driver to get at the current i915 device. Protected by
4654 * mchdev_lock. */
4655 static struct drm_i915_private *i915_mch_dev;
4656
4657 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4658 {
4659 u16 rgvswctl;
4660
4661 assert_spin_locked(&mchdev_lock);
4662
4663 rgvswctl = I915_READ16(MEMSWCTL);
4664 if (rgvswctl & MEMCTL_CMD_STS) {
4665 DRM_DEBUG("gpu busy, RCS change rejected\n");
4666 return false; /* still busy with another command */
4667 }
4668
4669 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4670 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4671 I915_WRITE16(MEMSWCTL, rgvswctl);
4672 POSTING_READ16(MEMSWCTL);
4673
4674 rgvswctl |= MEMCTL_CMD_STS;
4675 I915_WRITE16(MEMSWCTL, rgvswctl);
4676
4677 return true;
4678 }
4679
4680 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4681 {
4682 u32 rgvmodectl;
4683 u8 fmax, fmin, fstart, vstart;
4684
4685 spin_lock_irq(&mchdev_lock);
4686
4687 rgvmodectl = I915_READ(MEMMODECTL);
4688
4689 /* Enable temp reporting */
4690 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4691 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4692
4693 /* 100ms RC evaluation intervals */
4694 I915_WRITE(RCUPEI, 100000);
4695 I915_WRITE(RCDNEI, 100000);
4696
4697 /* Set max/min thresholds to 90ms and 80ms respectively */
4698 I915_WRITE(RCBMAXAVG, 90000);
4699 I915_WRITE(RCBMINAVG, 80000);
4700
4701 I915_WRITE(MEMIHYST, 1);
4702
4703 /* Set up min, max, and cur for interrupt handling */
4704 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4705 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4706 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4707 MEMMODE_FSTART_SHIFT;
4708
4709 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4710 PXVFREQ_PX_SHIFT;
4711
4712 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4713 dev_priv->ips.fstart = fstart;
4714
4715 dev_priv->ips.max_delay = fstart;
4716 dev_priv->ips.min_delay = fmin;
4717 dev_priv->ips.cur_delay = fstart;
4718
4719 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4720 fmax, fmin, fstart);
4721
4722 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4723
4724 /*
4725 * Interrupts will be enabled in ironlake_irq_postinstall
4726 */
4727
4728 I915_WRITE(VIDSTART, vstart);
4729 POSTING_READ(VIDSTART);
4730
4731 rgvmodectl |= MEMMODE_SWMODE_EN;
4732 I915_WRITE(MEMMODECTL, rgvmodectl);
4733
4734 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4735 DRM_ERROR("stuck trying to change perf mode\n");
4736 mdelay(1);
4737
4738 ironlake_set_drps(dev_priv, fstart);
4739
4740 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4741 I915_READ(DDREC) + I915_READ(CSIEC);
4742 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4743 dev_priv->ips.last_count2 = I915_READ(GFXEC);
4744 dev_priv->ips.last_time2 = ktime_get_raw_ns();
4745
4746 spin_unlock_irq(&mchdev_lock);
4747 }
4748
4749 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4750 {
4751 u16 rgvswctl;
4752
4753 spin_lock_irq(&mchdev_lock);
4754
4755 rgvswctl = I915_READ16(MEMSWCTL);
4756
4757 /* Ack interrupts, disable EFC interrupt */
4758 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4759 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4760 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4761 I915_WRITE(DEIIR, DE_PCU_EVENT);
4762 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4763
4764 /* Go back to the starting frequency */
4765 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4766 mdelay(1);
4767 rgvswctl |= MEMCTL_CMD_STS;
4768 I915_WRITE(MEMSWCTL, rgvswctl);
4769 mdelay(1);
4770
4771 spin_unlock_irq(&mchdev_lock);
4772 }
4773
4774 /* There's a funny hw issue where the hw returns all 0 when reading from
4775 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4776 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4777 * all limits and the gpu stuck at whatever frequency it is at atm).
4778 */
4779 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4780 {
4781 u32 limits;
4782
4783 /* Only set the down limit when we've reached the lowest level to avoid
4784 * getting more interrupts, otherwise leave this clear. This prevents a
4785 * race in the hw when coming out of rc6: There's a tiny window where
4786 * the hw runs at the minimal clock before selecting the desired
4787 * frequency, if the down threshold expires in that window we will not
4788 * receive a down interrupt. */
4789 if (IS_GEN9(dev_priv)) {
4790 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4791 if (val <= dev_priv->rps.min_freq_softlimit)
4792 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4793 } else {
4794 limits = dev_priv->rps.max_freq_softlimit << 24;
4795 if (val <= dev_priv->rps.min_freq_softlimit)
4796 limits |= dev_priv->rps.min_freq_softlimit << 16;
4797 }
4798
4799 return limits;
4800 }
4801
4802 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4803 {
4804 int new_power;
4805 u32 threshold_up = 0, threshold_down = 0; /* in % */
4806 u32 ei_up = 0, ei_down = 0;
4807
4808 new_power = dev_priv->rps.power;
4809 switch (dev_priv->rps.power) {
4810 case LOW_POWER:
4811 if (val > dev_priv->rps.efficient_freq + 1 &&
4812 val > dev_priv->rps.cur_freq)
4813 new_power = BETWEEN;
4814 break;
4815
4816 case BETWEEN:
4817 if (val <= dev_priv->rps.efficient_freq &&
4818 val < dev_priv->rps.cur_freq)
4819 new_power = LOW_POWER;
4820 else if (val >= dev_priv->rps.rp0_freq &&
4821 val > dev_priv->rps.cur_freq)
4822 new_power = HIGH_POWER;
4823 break;
4824
4825 case HIGH_POWER:
4826 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4827 val < dev_priv->rps.cur_freq)
4828 new_power = BETWEEN;
4829 break;
4830 }
4831 /* Max/min bins are special */
4832 if (val <= dev_priv->rps.min_freq_softlimit)
4833 new_power = LOW_POWER;
4834 if (val >= dev_priv->rps.max_freq_softlimit)
4835 new_power = HIGH_POWER;
4836 if (new_power == dev_priv->rps.power)
4837 return;
4838
4839 /* Note the units here are not exactly 1us, but 1280ns. */
4840 switch (new_power) {
4841 case LOW_POWER:
4842 /* Upclock if more than 95% busy over 16ms */
4843 ei_up = 16000;
4844 threshold_up = 95;
4845
4846 /* Downclock if less than 85% busy over 32ms */
4847 ei_down = 32000;
4848 threshold_down = 85;
4849 break;
4850
4851 case BETWEEN:
4852 /* Upclock if more than 90% busy over 13ms */
4853 ei_up = 13000;
4854 threshold_up = 90;
4855
4856 /* Downclock if less than 75% busy over 32ms */
4857 ei_down = 32000;
4858 threshold_down = 75;
4859 break;
4860
4861 case HIGH_POWER:
4862 /* Upclock if more than 85% busy over 10ms */
4863 ei_up = 10000;
4864 threshold_up = 85;
4865
4866 /* Downclock if less than 60% busy over 32ms */
4867 ei_down = 32000;
4868 threshold_down = 60;
4869 break;
4870 }
4871
4872 I915_WRITE(GEN6_RP_UP_EI,
4873 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4874 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4875 GT_INTERVAL_FROM_US(dev_priv,
4876 ei_up * threshold_up / 100));
4877
4878 I915_WRITE(GEN6_RP_DOWN_EI,
4879 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4880 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4881 GT_INTERVAL_FROM_US(dev_priv,
4882 ei_down * threshold_down / 100));
4883
4884 I915_WRITE(GEN6_RP_CONTROL,
4885 GEN6_RP_MEDIA_TURBO |
4886 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4887 GEN6_RP_MEDIA_IS_GFX |
4888 GEN6_RP_ENABLE |
4889 GEN6_RP_UP_BUSY_AVG |
4890 GEN6_RP_DOWN_IDLE_AVG);
4891
4892 dev_priv->rps.power = new_power;
4893 dev_priv->rps.up_threshold = threshold_up;
4894 dev_priv->rps.down_threshold = threshold_down;
4895 dev_priv->rps.last_adj = 0;
4896 }
4897
4898 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4899 {
4900 u32 mask = 0;
4901
4902 if (val > dev_priv->rps.min_freq_softlimit)
4903 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4904 if (val < dev_priv->rps.max_freq_softlimit)
4905 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4906
4907 mask &= dev_priv->pm_rps_events;
4908
4909 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4910 }
4911
4912 /* gen6_set_rps is called to update the frequency request, but should also be
4913 * called when the range (min_delay and max_delay) is modified so that we can
4914 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4915 static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4916 {
4917 /* min/max delay may still have been modified so be sure to
4918 * write the limits value.
4919 */
4920 if (val != dev_priv->rps.cur_freq) {
4921 gen6_set_rps_thresholds(dev_priv, val);
4922
4923 if (IS_GEN9(dev_priv))
4924 I915_WRITE(GEN6_RPNSWREQ,
4925 GEN9_FREQUENCY(val));
4926 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4927 I915_WRITE(GEN6_RPNSWREQ,
4928 HSW_FREQUENCY(val));
4929 else
4930 I915_WRITE(GEN6_RPNSWREQ,
4931 GEN6_FREQUENCY(val) |
4932 GEN6_OFFSET(0) |
4933 GEN6_AGGRESSIVE_TURBO);
4934 }
4935
4936 /* Make sure we continue to get interrupts
4937 * until we hit the minimum or maximum frequencies.
4938 */
4939 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4940 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4941
4942 POSTING_READ(GEN6_RPNSWREQ);
4943
4944 dev_priv->rps.cur_freq = val;
4945 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4946
4947 return 0;
4948 }
4949
4950 static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4951 {
4952 int err;
4953
4954 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4955 "Odd GPU freq value\n"))
4956 val &= ~1;
4957
4958 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4959
4960 if (val != dev_priv->rps.cur_freq) {
4961 err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4962 if (err)
4963 return err;
4964
4965 gen6_set_rps_thresholds(dev_priv, val);
4966 }
4967
4968 dev_priv->rps.cur_freq = val;
4969 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4970
4971 return 0;
4972 }
4973
4974 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4975 *
4976 * * If Gfx is Idle, then
4977 * 1. Forcewake Media well.
4978 * 2. Request idle freq.
4979 * 3. Release Forcewake of Media well.
4980 */
4981 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4982 {
4983 u32 val = dev_priv->rps.idle_freq;
4984 int err;
4985
4986 if (dev_priv->rps.cur_freq <= val)
4987 return;
4988
4989 /* The punit delays the write of the frequency and voltage until it
4990 * determines the GPU is awake. During normal usage we don't want to
4991 * waste power changing the frequency if the GPU is sleeping (rc6).
4992 * However, the GPU and driver is now idle and we do not want to delay
4993 * switching to minimum voltage (reducing power whilst idle) as we do
4994 * not expect to be woken in the near future and so must flush the
4995 * change by waking the device.
4996 *
4997 * We choose to take the media powerwell (either would do to trick the
4998 * punit into committing the voltage change) as that takes a lot less
4999 * power than the render powerwell.
5000 */
5001 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
5002 err = valleyview_set_rps(dev_priv, val);
5003 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
5004
5005 if (err)
5006 DRM_ERROR("Failed to set RPS for idle\n");
5007 }
5008
5009 void gen6_rps_busy(struct drm_i915_private *dev_priv)
5010 {
5011 mutex_lock(&dev_priv->rps.hw_lock);
5012 if (dev_priv->rps.enabled) {
5013 u8 freq;
5014
5015 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5016 gen6_rps_reset_ei(dev_priv);
5017 I915_WRITE(GEN6_PMINTRMSK,
5018 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
5019
5020 gen6_enable_rps_interrupts(dev_priv);
5021
5022 /* Use the user's desired frequency as a guide, but for better
5023 * performance, jump directly to RPe as our starting frequency.
5024 */
5025 freq = max(dev_priv->rps.cur_freq,
5026 dev_priv->rps.efficient_freq);
5027
5028 if (intel_set_rps(dev_priv,
5029 clamp(freq,
5030 dev_priv->rps.min_freq_softlimit,
5031 dev_priv->rps.max_freq_softlimit)))
5032 DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
5033 }
5034 mutex_unlock(&dev_priv->rps.hw_lock);
5035 }
5036
5037 void gen6_rps_idle(struct drm_i915_private *dev_priv)
5038 {
5039 /* Flush our bottom-half so that it does not race with us
5040 * setting the idle frequency and so that it is bounded by
5041 * our rpm wakeref. And then disable the interrupts to stop any
5042 * futher RPS reclocking whilst we are asleep.
5043 */
5044 gen6_disable_rps_interrupts(dev_priv);
5045
5046 mutex_lock(&dev_priv->rps.hw_lock);
5047 if (dev_priv->rps.enabled) {
5048 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5049 vlv_set_rps_idle(dev_priv);
5050 else
5051 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5052 dev_priv->rps.last_adj = 0;
5053 I915_WRITE(GEN6_PMINTRMSK,
5054 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
5055 }
5056 mutex_unlock(&dev_priv->rps.hw_lock);
5057
5058 spin_lock(&dev_priv->rps.client_lock);
5059 while (!list_empty(&dev_priv->rps.clients))
5060 list_del_init(dev_priv->rps.clients.next);
5061 spin_unlock(&dev_priv->rps.client_lock);
5062 }
5063
5064 void gen6_rps_boost(struct drm_i915_private *dev_priv,
5065 struct intel_rps_client *rps,
5066 unsigned long submitted)
5067 {
5068 /* This is intentionally racy! We peek at the state here, then
5069 * validate inside the RPS worker.
5070 */
5071 if (!(dev_priv->gt.awake &&
5072 dev_priv->rps.enabled &&
5073 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
5074 return;
5075
5076 /* Force a RPS boost (and don't count it against the client) if
5077 * the GPU is severely congested.
5078 */
5079 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
5080 rps = NULL;
5081
5082 spin_lock(&dev_priv->rps.client_lock);
5083 if (rps == NULL || list_empty(&rps->link)) {
5084 spin_lock_irq(&dev_priv->irq_lock);
5085 if (dev_priv->rps.interrupts_enabled) {
5086 dev_priv->rps.client_boost = true;
5087 schedule_work(&dev_priv->rps.work);
5088 }
5089 spin_unlock_irq(&dev_priv->irq_lock);
5090
5091 if (rps != NULL) {
5092 list_add(&rps->link, &dev_priv->rps.clients);
5093 rps->boosts++;
5094 } else
5095 dev_priv->rps.boosts++;
5096 }
5097 spin_unlock(&dev_priv->rps.client_lock);
5098 }
5099
5100 int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
5101 {
5102 int err;
5103
5104 lockdep_assert_held(&dev_priv->rps.hw_lock);
5105 GEM_BUG_ON(val > dev_priv->rps.max_freq);
5106 GEM_BUG_ON(val < dev_priv->rps.min_freq);
5107
5108 if (!dev_priv->rps.enabled) {
5109 dev_priv->rps.cur_freq = val;
5110 return 0;
5111 }
5112
5113 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5114 err = valleyview_set_rps(dev_priv, val);
5115 else
5116 err = gen6_set_rps(dev_priv, val);
5117
5118 return err;
5119 }
5120
5121 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
5122 {
5123 I915_WRITE(GEN6_RC_CONTROL, 0);
5124 I915_WRITE(GEN9_PG_ENABLE, 0);
5125 }
5126
5127 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
5128 {
5129 I915_WRITE(GEN6_RP_CONTROL, 0);
5130 }
5131
5132 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
5133 {
5134 I915_WRITE(GEN6_RC_CONTROL, 0);
5135 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
5136 I915_WRITE(GEN6_RP_CONTROL, 0);
5137 }
5138
5139 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
5140 {
5141 I915_WRITE(GEN6_RC_CONTROL, 0);
5142 }
5143
5144 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
5145 {
5146 /* we're doing forcewake before Disabling RC6,
5147 * This what the BIOS expects when going into suspend */
5148 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5149
5150 I915_WRITE(GEN6_RC_CONTROL, 0);
5151
5152 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5153 }
5154
5155 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
5156 {
5157 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5158 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5159 mode = GEN6_RC_CTL_RC6_ENABLE;
5160 else
5161 mode = 0;
5162 }
5163 if (HAS_RC6p(dev_priv))
5164 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5165 "RC6 %s RC6p %s RC6pp %s\n",
5166 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5167 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5168 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
5169
5170 else
5171 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5172 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
5173 }
5174
5175 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
5176 {
5177 struct i915_ggtt *ggtt = &dev_priv->ggtt;
5178 bool enable_rc6 = true;
5179 unsigned long rc6_ctx_base;
5180 u32 rc_ctl;
5181 int rc_sw_target;
5182
5183 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5184 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5185 RC_SW_TARGET_STATE_SHIFT;
5186 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5187 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5188 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5189 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5190 rc_sw_target);
5191
5192 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
5193 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5194 enable_rc6 = false;
5195 }
5196
5197 /*
5198 * The exact context size is not known for BXT, so assume a page size
5199 * for this check.
5200 */
5201 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
5202 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5203 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5204 ggtt->stolen_reserved_size))) {
5205 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5206 enable_rc6 = false;
5207 }
5208
5209 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5210 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5211 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5212 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
5213 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5214 enable_rc6 = false;
5215 }
5216
5217 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5218 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5219 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5220 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5221 enable_rc6 = false;
5222 }
5223
5224 if (!I915_READ(GEN6_GFXPAUSE)) {
5225 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5226 enable_rc6 = false;
5227 }
5228
5229 if (!I915_READ(GEN8_MISC_CTRL0)) {
5230 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5231 enable_rc6 = false;
5232 }
5233
5234 return enable_rc6;
5235 }
5236
5237 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
5238 {
5239 /* No RC6 before Ironlake and code is gone for ilk. */
5240 if (INTEL_INFO(dev_priv)->gen < 6)
5241 return 0;
5242
5243 if (!enable_rc6)
5244 return 0;
5245
5246 if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5247 DRM_INFO("RC6 disabled by BIOS\n");
5248 return 0;
5249 }
5250
5251 /* Respect the kernel parameter if it is set */
5252 if (enable_rc6 >= 0) {
5253 int mask;
5254
5255 if (HAS_RC6p(dev_priv))
5256 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5257 INTEL_RC6pp_ENABLE;
5258 else
5259 mask = INTEL_RC6_ENABLE;
5260
5261 if ((enable_rc6 & mask) != enable_rc6)
5262 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5263 "(requested %d, valid %d)\n",
5264 enable_rc6 & mask, enable_rc6, mask);
5265
5266 return enable_rc6 & mask;
5267 }
5268
5269 if (IS_IVYBRIDGE(dev_priv))
5270 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5271
5272 return INTEL_RC6_ENABLE;
5273 }
5274
5275 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5276 {
5277 /* All of these values are in units of 50MHz */
5278
5279 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5280 if (IS_GEN9_LP(dev_priv)) {
5281 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5282 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5283 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5284 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5285 } else {
5286 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5287 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5288 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5289 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5290 }
5291 /* hw_max = RP0 until we check for overclocking */
5292 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5293
5294 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5295 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5296 IS_GEN9_BC(dev_priv)) {
5297 u32 ddcc_status = 0;
5298
5299 if (sandybridge_pcode_read(dev_priv,
5300 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5301 &ddcc_status) == 0)
5302 dev_priv->rps.efficient_freq =
5303 clamp_t(u8,
5304 ((ddcc_status >> 8) & 0xff),
5305 dev_priv->rps.min_freq,
5306 dev_priv->rps.max_freq);
5307 }
5308
5309 if (IS_GEN9_BC(dev_priv)) {
5310 /* Store the frequency values in 16.66 MHZ units, which is
5311 * the natural hardware unit for SKL
5312 */
5313 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5314 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5315 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5316 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5317 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5318 }
5319 }
5320
5321 static void reset_rps(struct drm_i915_private *dev_priv,
5322 int (*set)(struct drm_i915_private *, u8))
5323 {
5324 u8 freq = dev_priv->rps.cur_freq;
5325
5326 /* force a reset */
5327 dev_priv->rps.power = -1;
5328 dev_priv->rps.cur_freq = -1;
5329
5330 if (set(dev_priv, freq))
5331 DRM_ERROR("Failed to reset RPS to initial values\n");
5332 }
5333
5334 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5335 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5336 {
5337 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5338
5339 /* Program defaults and thresholds for RPS*/
5340 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5341 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5342
5343 /* 1 second timeout*/
5344 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5345 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5346
5347 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5348
5349 /* Leaning on the below call to gen6_set_rps to program/setup the
5350 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5351 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5352 reset_rps(dev_priv, gen6_set_rps);
5353
5354 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5355 }
5356
5357 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5358 {
5359 struct intel_engine_cs *engine;
5360 enum intel_engine_id id;
5361 uint32_t rc6_mask = 0;
5362
5363 /* 1a: Software RC state - RC0 */
5364 I915_WRITE(GEN6_RC_STATE, 0);
5365
5366 /* 1b: Get forcewake during program sequence. Although the driver
5367 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5368 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5369
5370 /* 2a: Disable RC states. */
5371 I915_WRITE(GEN6_RC_CONTROL, 0);
5372
5373 /* 2b: Program RC6 thresholds.*/
5374
5375 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5376 if (IS_SKYLAKE(dev_priv))
5377 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5378 else
5379 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5380 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5381 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5382 for_each_engine(engine, dev_priv, id)
5383 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5384
5385 if (HAS_GUC(dev_priv))
5386 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5387
5388 I915_WRITE(GEN6_RC_SLEEP, 0);
5389
5390 /* 2c: Program Coarse Power Gating Policies. */
5391 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5392 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5393
5394 /* 3a: Enable RC6 */
5395 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5396 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5397 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5398 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5399 I915_WRITE(GEN6_RC_CONTROL,
5400 GEN6_RC_CTL_HW_ENABLE | GEN6_RC_CTL_EI_MODE(1) | rc6_mask);
5401
5402 /*
5403 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5404 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5405 */
5406 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5407 I915_WRITE(GEN9_PG_ENABLE, 0);
5408 else
5409 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5410 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5411
5412 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5413 }
5414
5415 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5416 {
5417 struct intel_engine_cs *engine;
5418 enum intel_engine_id id;
5419 uint32_t rc6_mask = 0;
5420
5421 /* 1a: Software RC state - RC0 */
5422 I915_WRITE(GEN6_RC_STATE, 0);
5423
5424 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5425 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5426 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5427
5428 /* 2a: Disable RC states. */
5429 I915_WRITE(GEN6_RC_CONTROL, 0);
5430
5431 /* 2b: Program RC6 thresholds.*/
5432 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5433 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5434 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5435 for_each_engine(engine, dev_priv, id)
5436 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5437 I915_WRITE(GEN6_RC_SLEEP, 0);
5438 if (IS_BROADWELL(dev_priv))
5439 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5440 else
5441 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5442
5443 /* 3: Enable RC6 */
5444 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5445 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5446 intel_print_rc6_info(dev_priv, rc6_mask);
5447 if (IS_BROADWELL(dev_priv))
5448 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5449 GEN7_RC_CTL_TO_MODE |
5450 rc6_mask);
5451 else
5452 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5453 GEN6_RC_CTL_EI_MODE(1) |
5454 rc6_mask);
5455
5456 /* 4 Program defaults and thresholds for RPS*/
5457 I915_WRITE(GEN6_RPNSWREQ,
5458 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5459 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5460 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5461 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5462 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5463
5464 /* Docs recommend 900MHz, and 300 MHz respectively */
5465 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5466 dev_priv->rps.max_freq_softlimit << 24 |
5467 dev_priv->rps.min_freq_softlimit << 16);
5468
5469 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5470 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5471 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5472 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5473
5474 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5475
5476 /* 5: Enable RPS */
5477 I915_WRITE(GEN6_RP_CONTROL,
5478 GEN6_RP_MEDIA_TURBO |
5479 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5480 GEN6_RP_MEDIA_IS_GFX |
5481 GEN6_RP_ENABLE |
5482 GEN6_RP_UP_BUSY_AVG |
5483 GEN6_RP_DOWN_IDLE_AVG);
5484
5485 /* 6: Ring frequency + overclocking (our driver does this later */
5486
5487 reset_rps(dev_priv, gen6_set_rps);
5488
5489 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5490 }
5491
5492 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5493 {
5494 struct intel_engine_cs *engine;
5495 enum intel_engine_id id;
5496 u32 rc6vids, rc6_mask = 0;
5497 u32 gtfifodbg;
5498 int rc6_mode;
5499 int ret;
5500
5501 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5502
5503 /* Here begins a magic sequence of register writes to enable
5504 * auto-downclocking.
5505 *
5506 * Perhaps there might be some value in exposing these to
5507 * userspace...
5508 */
5509 I915_WRITE(GEN6_RC_STATE, 0);
5510
5511 /* Clear the DBG now so we don't confuse earlier errors */
5512 gtfifodbg = I915_READ(GTFIFODBG);
5513 if (gtfifodbg) {
5514 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5515 I915_WRITE(GTFIFODBG, gtfifodbg);
5516 }
5517
5518 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5519
5520 /* disable the counters and set deterministic thresholds */
5521 I915_WRITE(GEN6_RC_CONTROL, 0);
5522
5523 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5524 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5525 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5526 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5527 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5528
5529 for_each_engine(engine, dev_priv, id)
5530 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5531
5532 I915_WRITE(GEN6_RC_SLEEP, 0);
5533 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5534 if (IS_IVYBRIDGE(dev_priv))
5535 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5536 else
5537 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5538 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5539 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5540
5541 /* Check if we are enabling RC6 */
5542 rc6_mode = intel_enable_rc6();
5543 if (rc6_mode & INTEL_RC6_ENABLE)
5544 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5545
5546 /* We don't use those on Haswell */
5547 if (!IS_HASWELL(dev_priv)) {
5548 if (rc6_mode & INTEL_RC6p_ENABLE)
5549 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5550
5551 if (rc6_mode & INTEL_RC6pp_ENABLE)
5552 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5553 }
5554
5555 intel_print_rc6_info(dev_priv, rc6_mask);
5556
5557 I915_WRITE(GEN6_RC_CONTROL,
5558 rc6_mask |
5559 GEN6_RC_CTL_EI_MODE(1) |
5560 GEN6_RC_CTL_HW_ENABLE);
5561
5562 /* Power down if completely idle for over 50ms */
5563 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5564 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5565
5566 reset_rps(dev_priv, gen6_set_rps);
5567
5568 rc6vids = 0;
5569 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5570 if (IS_GEN6(dev_priv) && ret) {
5571 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5572 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5573 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5574 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5575 rc6vids &= 0xffff00;
5576 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5577 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5578 if (ret)
5579 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5580 }
5581
5582 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5583 }
5584
5585 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5586 {
5587 int min_freq = 15;
5588 unsigned int gpu_freq;
5589 unsigned int max_ia_freq, min_ring_freq;
5590 unsigned int max_gpu_freq, min_gpu_freq;
5591 int scaling_factor = 180;
5592 struct cpufreq_policy *policy;
5593
5594 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5595
5596 policy = cpufreq_cpu_get(0);
5597 if (policy) {
5598 max_ia_freq = policy->cpuinfo.max_freq;
5599 cpufreq_cpu_put(policy);
5600 } else {
5601 /*
5602 * Default to measured freq if none found, PCU will ensure we
5603 * don't go over
5604 */
5605 max_ia_freq = tsc_khz;
5606 }
5607
5608 /* Convert from kHz to MHz */
5609 max_ia_freq /= 1000;
5610
5611 min_ring_freq = I915_READ(DCLK) & 0xf;
5612 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5613 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5614
5615 if (IS_GEN9_BC(dev_priv)) {
5616 /* Convert GT frequency to 50 HZ units */
5617 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5618 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5619 } else {
5620 min_gpu_freq = dev_priv->rps.min_freq;
5621 max_gpu_freq = dev_priv->rps.max_freq;
5622 }
5623
5624 /*
5625 * For each potential GPU frequency, load a ring frequency we'd like
5626 * to use for memory access. We do this by specifying the IA frequency
5627 * the PCU should use as a reference to determine the ring frequency.
5628 */
5629 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5630 int diff = max_gpu_freq - gpu_freq;
5631 unsigned int ia_freq = 0, ring_freq = 0;
5632
5633 if (IS_GEN9_BC(dev_priv)) {
5634 /*
5635 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5636 * No floor required for ring frequency on SKL.
5637 */
5638 ring_freq = gpu_freq;
5639 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5640 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5641 ring_freq = max(min_ring_freq, gpu_freq);
5642 } else if (IS_HASWELL(dev_priv)) {
5643 ring_freq = mult_frac(gpu_freq, 5, 4);
5644 ring_freq = max(min_ring_freq, ring_freq);
5645 /* leave ia_freq as the default, chosen by cpufreq */
5646 } else {
5647 /* On older processors, there is no separate ring
5648 * clock domain, so in order to boost the bandwidth
5649 * of the ring, we need to upclock the CPU (ia_freq).
5650 *
5651 * For GPU frequencies less than 750MHz,
5652 * just use the lowest ring freq.
5653 */
5654 if (gpu_freq < min_freq)
5655 ia_freq = 800;
5656 else
5657 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5658 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5659 }
5660
5661 sandybridge_pcode_write(dev_priv,
5662 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5663 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5664 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5665 gpu_freq);
5666 }
5667 }
5668
5669 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5670 {
5671 u32 val, rp0;
5672
5673 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5674
5675 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5676 case 8:
5677 /* (2 * 4) config */
5678 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5679 break;
5680 case 12:
5681 /* (2 * 6) config */
5682 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5683 break;
5684 case 16:
5685 /* (2 * 8) config */
5686 default:
5687 /* Setting (2 * 8) Min RP0 for any other combination */
5688 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5689 break;
5690 }
5691
5692 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5693
5694 return rp0;
5695 }
5696
5697 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5698 {
5699 u32 val, rpe;
5700
5701 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5702 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5703
5704 return rpe;
5705 }
5706
5707 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5708 {
5709 u32 val, rp1;
5710
5711 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5712 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5713
5714 return rp1;
5715 }
5716
5717 static u32 cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
5718 {
5719 u32 val, rpn;
5720
5721 val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
5722 rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
5723 FB_GFX_FREQ_FUSE_MASK);
5724
5725 return rpn;
5726 }
5727
5728 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5729 {
5730 u32 val, rp1;
5731
5732 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5733
5734 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5735
5736 return rp1;
5737 }
5738
5739 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5740 {
5741 u32 val, rp0;
5742
5743 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5744
5745 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5746 /* Clamp to max */
5747 rp0 = min_t(u32, rp0, 0xea);
5748
5749 return rp0;
5750 }
5751
5752 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5753 {
5754 u32 val, rpe;
5755
5756 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5757 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5758 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5759 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5760
5761 return rpe;
5762 }
5763
5764 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5765 {
5766 u32 val;
5767
5768 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5769 /*
5770 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5771 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5772 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5773 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5774 * to make sure it matches what Punit accepts.
5775 */
5776 return max_t(u32, val, 0xc0);
5777 }
5778
5779 /* Check that the pctx buffer wasn't move under us. */
5780 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5781 {
5782 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5783
5784 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5785 dev_priv->vlv_pctx->stolen->start);
5786 }
5787
5788
5789 /* Check that the pcbr address is not empty. */
5790 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5791 {
5792 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5793
5794 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5795 }
5796
5797 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5798 {
5799 struct i915_ggtt *ggtt = &dev_priv->ggtt;
5800 unsigned long pctx_paddr, paddr;
5801 u32 pcbr;
5802 int pctx_size = 32*1024;
5803
5804 pcbr = I915_READ(VLV_PCBR);
5805 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5806 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5807 paddr = (dev_priv->mm.stolen_base +
5808 (ggtt->stolen_size - pctx_size));
5809
5810 pctx_paddr = (paddr & (~4095));
5811 I915_WRITE(VLV_PCBR, pctx_paddr);
5812 }
5813
5814 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5815 }
5816
5817 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5818 {
5819 struct drm_i915_gem_object *pctx;
5820 unsigned long pctx_paddr;
5821 u32 pcbr;
5822 int pctx_size = 24*1024;
5823
5824 pcbr = I915_READ(VLV_PCBR);
5825 if (pcbr) {
5826 /* BIOS set it up already, grab the pre-alloc'd space */
5827 int pcbr_offset;
5828
5829 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5830 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv,
5831 pcbr_offset,
5832 I915_GTT_OFFSET_NONE,
5833 pctx_size);
5834 goto out;
5835 }
5836
5837 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5838
5839 /*
5840 * From the Gunit register HAS:
5841 * The Gfx driver is expected to program this register and ensure
5842 * proper allocation within Gfx stolen memory. For example, this
5843 * register should be programmed such than the PCBR range does not
5844 * overlap with other ranges, such as the frame buffer, protected
5845 * memory, or any other relevant ranges.
5846 */
5847 pctx = i915_gem_object_create_stolen(dev_priv, pctx_size);
5848 if (!pctx) {
5849 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5850 goto out;
5851 }
5852
5853 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5854 I915_WRITE(VLV_PCBR, pctx_paddr);
5855
5856 out:
5857 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5858 dev_priv->vlv_pctx = pctx;
5859 }
5860
5861 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5862 {
5863 if (WARN_ON(!dev_priv->vlv_pctx))
5864 return;
5865
5866 i915_gem_object_put(dev_priv->vlv_pctx);
5867 dev_priv->vlv_pctx = NULL;
5868 }
5869
5870 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5871 {
5872 dev_priv->rps.gpll_ref_freq =
5873 vlv_get_cck_clock(dev_priv, "GPLL ref",
5874 CCK_GPLL_CLOCK_CONTROL,
5875 dev_priv->czclk_freq);
5876
5877 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5878 dev_priv->rps.gpll_ref_freq);
5879 }
5880
5881 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5882 {
5883 u32 val;
5884
5885 valleyview_setup_pctx(dev_priv);
5886
5887 vlv_init_gpll_ref_freq(dev_priv);
5888
5889 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5890 switch ((val >> 6) & 3) {
5891 case 0:
5892 case 1:
5893 dev_priv->mem_freq = 800;
5894 break;
5895 case 2:
5896 dev_priv->mem_freq = 1066;
5897 break;
5898 case 3:
5899 dev_priv->mem_freq = 1333;
5900 break;
5901 }
5902 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5903
5904 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5905 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5906 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5907 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5908 dev_priv->rps.max_freq);
5909
5910 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5911 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5912 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5913 dev_priv->rps.efficient_freq);
5914
5915 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5916 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5917 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5918 dev_priv->rps.rp1_freq);
5919
5920 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5921 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5922 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5923 dev_priv->rps.min_freq);
5924 }
5925
5926 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5927 {
5928 u32 val;
5929
5930 cherryview_setup_pctx(dev_priv);
5931
5932 vlv_init_gpll_ref_freq(dev_priv);
5933
5934 mutex_lock(&dev_priv->sb_lock);
5935 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5936 mutex_unlock(&dev_priv->sb_lock);
5937
5938 switch ((val >> 2) & 0x7) {
5939 case 3:
5940 dev_priv->mem_freq = 2000;
5941 break;
5942 default:
5943 dev_priv->mem_freq = 1600;
5944 break;
5945 }
5946 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5947
5948 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5949 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5950 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5951 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5952 dev_priv->rps.max_freq);
5953
5954 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5955 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5956 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5957 dev_priv->rps.efficient_freq);
5958
5959 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5960 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5961 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5962 dev_priv->rps.rp1_freq);
5963
5964 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
5965 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5966 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5967 dev_priv->rps.min_freq);
5968
5969 WARN_ONCE((dev_priv->rps.max_freq |
5970 dev_priv->rps.efficient_freq |
5971 dev_priv->rps.rp1_freq |
5972 dev_priv->rps.min_freq) & 1,
5973 "Odd GPU freq values\n");
5974 }
5975
5976 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5977 {
5978 valleyview_cleanup_pctx(dev_priv);
5979 }
5980
5981 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5982 {
5983 struct intel_engine_cs *engine;
5984 enum intel_engine_id id;
5985 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5986
5987 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5988
5989 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5990 GT_FIFO_FREE_ENTRIES_CHV);
5991 if (gtfifodbg) {
5992 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5993 gtfifodbg);
5994 I915_WRITE(GTFIFODBG, gtfifodbg);
5995 }
5996
5997 cherryview_check_pctx(dev_priv);
5998
5999 /* 1a & 1b: Get forcewake during program sequence. Although the driver
6000 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6001 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6002
6003 /* Disable RC states. */
6004 I915_WRITE(GEN6_RC_CONTROL, 0);
6005
6006 /* 2a: Program RC6 thresholds.*/
6007 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6008 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6009 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6010
6011 for_each_engine(engine, dev_priv, id)
6012 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6013 I915_WRITE(GEN6_RC_SLEEP, 0);
6014
6015 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6016 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
6017
6018 /* allows RC6 residency counter to work */
6019 I915_WRITE(VLV_COUNTER_CONTROL,
6020 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6021 VLV_MEDIA_RC6_COUNT_EN |
6022 VLV_RENDER_RC6_COUNT_EN));
6023
6024 /* For now we assume BIOS is allocating and populating the PCBR */
6025 pcbr = I915_READ(VLV_PCBR);
6026
6027 /* 3: Enable RC6 */
6028 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6029 (pcbr >> VLV_PCBR_ADDR_SHIFT))
6030 rc6_mode = GEN7_RC_CTL_TO_MODE;
6031
6032 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6033
6034 /* 4 Program defaults and thresholds for RPS*/
6035 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6036 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6037 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6038 I915_WRITE(GEN6_RP_UP_EI, 66000);
6039 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6040
6041 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6042
6043 /* 5: Enable RPS */
6044 I915_WRITE(GEN6_RP_CONTROL,
6045 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6046 GEN6_RP_MEDIA_IS_GFX |
6047 GEN6_RP_ENABLE |
6048 GEN6_RP_UP_BUSY_AVG |
6049 GEN6_RP_DOWN_IDLE_AVG);
6050
6051 /* Setting Fixed Bias */
6052 val = VLV_OVERRIDE_EN |
6053 VLV_SOC_TDP_EN |
6054 CHV_BIAS_CPU_50_SOC_50;
6055 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6056
6057 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6058
6059 /* RPS code assumes GPLL is used */
6060 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6061
6062 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6063 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6064
6065 reset_rps(dev_priv, valleyview_set_rps);
6066
6067 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6068 }
6069
6070 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
6071 {
6072 struct intel_engine_cs *engine;
6073 enum intel_engine_id id;
6074 u32 gtfifodbg, val, rc6_mode = 0;
6075
6076 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6077
6078 valleyview_check_pctx(dev_priv);
6079
6080 gtfifodbg = I915_READ(GTFIFODBG);
6081 if (gtfifodbg) {
6082 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6083 gtfifodbg);
6084 I915_WRITE(GTFIFODBG, gtfifodbg);
6085 }
6086
6087 /* If VLV, Forcewake all wells, else re-direct to regular path */
6088 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6089
6090 /* Disable RC states. */
6091 I915_WRITE(GEN6_RC_CONTROL, 0);
6092
6093 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6094 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6095 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6096 I915_WRITE(GEN6_RP_UP_EI, 66000);
6097 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6098
6099 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6100
6101 I915_WRITE(GEN6_RP_CONTROL,
6102 GEN6_RP_MEDIA_TURBO |
6103 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6104 GEN6_RP_MEDIA_IS_GFX |
6105 GEN6_RP_ENABLE |
6106 GEN6_RP_UP_BUSY_AVG |
6107 GEN6_RP_DOWN_IDLE_CONT);
6108
6109 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6110 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6111 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6112
6113 for_each_engine(engine, dev_priv, id)
6114 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6115
6116 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
6117
6118 /* allows RC6 residency counter to work */
6119 I915_WRITE(VLV_COUNTER_CONTROL,
6120 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6121 VLV_RENDER_RC0_COUNT_EN |
6122 VLV_MEDIA_RC6_COUNT_EN |
6123 VLV_RENDER_RC6_COUNT_EN));
6124
6125 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6126 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
6127
6128 intel_print_rc6_info(dev_priv, rc6_mode);
6129
6130 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6131
6132 /* Setting Fixed Bias */
6133 val = VLV_OVERRIDE_EN |
6134 VLV_SOC_TDP_EN |
6135 VLV_BIAS_CPU_125_SOC_875;
6136 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6137
6138 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6139
6140 /* RPS code assumes GPLL is used */
6141 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6142
6143 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6144 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6145
6146 reset_rps(dev_priv, valleyview_set_rps);
6147
6148 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6149 }
6150
6151 static unsigned long intel_pxfreq(u32 vidfreq)
6152 {
6153 unsigned long freq;
6154 int div = (vidfreq & 0x3f0000) >> 16;
6155 int post = (vidfreq & 0x3000) >> 12;
6156 int pre = (vidfreq & 0x7);
6157
6158 if (!pre)
6159 return 0;
6160
6161 freq = ((div * 133333) / ((1<<post) * pre));
6162
6163 return freq;
6164 }
6165
6166 static const struct cparams {
6167 u16 i;
6168 u16 t;
6169 u16 m;
6170 u16 c;
6171 } cparams[] = {
6172 { 1, 1333, 301, 28664 },
6173 { 1, 1066, 294, 24460 },
6174 { 1, 800, 294, 25192 },
6175 { 0, 1333, 276, 27605 },
6176 { 0, 1066, 276, 27605 },
6177 { 0, 800, 231, 23784 },
6178 };
6179
6180 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6181 {
6182 u64 total_count, diff, ret;
6183 u32 count1, count2, count3, m = 0, c = 0;
6184 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6185 int i;
6186
6187 assert_spin_locked(&mchdev_lock);
6188
6189 diff1 = now - dev_priv->ips.last_time1;
6190
6191 /* Prevent division-by-zero if we are asking too fast.
6192 * Also, we don't get interesting results if we are polling
6193 * faster than once in 10ms, so just return the saved value
6194 * in such cases.
6195 */
6196 if (diff1 <= 10)
6197 return dev_priv->ips.chipset_power;
6198
6199 count1 = I915_READ(DMIEC);
6200 count2 = I915_READ(DDREC);
6201 count3 = I915_READ(CSIEC);
6202
6203 total_count = count1 + count2 + count3;
6204
6205 /* FIXME: handle per-counter overflow */
6206 if (total_count < dev_priv->ips.last_count1) {
6207 diff = ~0UL - dev_priv->ips.last_count1;
6208 diff += total_count;
6209 } else {
6210 diff = total_count - dev_priv->ips.last_count1;
6211 }
6212
6213 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6214 if (cparams[i].i == dev_priv->ips.c_m &&
6215 cparams[i].t == dev_priv->ips.r_t) {
6216 m = cparams[i].m;
6217 c = cparams[i].c;
6218 break;
6219 }
6220 }
6221
6222 diff = div_u64(diff, diff1);
6223 ret = ((m * diff) + c);
6224 ret = div_u64(ret, 10);
6225
6226 dev_priv->ips.last_count1 = total_count;
6227 dev_priv->ips.last_time1 = now;
6228
6229 dev_priv->ips.chipset_power = ret;
6230
6231 return ret;
6232 }
6233
6234 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6235 {
6236 unsigned long val;
6237
6238 if (INTEL_INFO(dev_priv)->gen != 5)
6239 return 0;
6240
6241 spin_lock_irq(&mchdev_lock);
6242
6243 val = __i915_chipset_val(dev_priv);
6244
6245 spin_unlock_irq(&mchdev_lock);
6246
6247 return val;
6248 }
6249
6250 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6251 {
6252 unsigned long m, x, b;
6253 u32 tsfs;
6254
6255 tsfs = I915_READ(TSFS);
6256
6257 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6258 x = I915_READ8(TR1);
6259
6260 b = tsfs & TSFS_INTR_MASK;
6261
6262 return ((m * x) / 127) - b;
6263 }
6264
6265 static int _pxvid_to_vd(u8 pxvid)
6266 {
6267 if (pxvid == 0)
6268 return 0;
6269
6270 if (pxvid >= 8 && pxvid < 31)
6271 pxvid = 31;
6272
6273 return (pxvid + 2) * 125;
6274 }
6275
6276 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6277 {
6278 const int vd = _pxvid_to_vd(pxvid);
6279 const int vm = vd - 1125;
6280
6281 if (INTEL_INFO(dev_priv)->is_mobile)
6282 return vm > 0 ? vm : 0;
6283
6284 return vd;
6285 }
6286
6287 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6288 {
6289 u64 now, diff, diffms;
6290 u32 count;
6291
6292 assert_spin_locked(&mchdev_lock);
6293
6294 now = ktime_get_raw_ns();
6295 diffms = now - dev_priv->ips.last_time2;
6296 do_div(diffms, NSEC_PER_MSEC);
6297
6298 /* Don't divide by 0 */
6299 if (!diffms)
6300 return;
6301
6302 count = I915_READ(GFXEC);
6303
6304 if (count < dev_priv->ips.last_count2) {
6305 diff = ~0UL - dev_priv->ips.last_count2;
6306 diff += count;
6307 } else {
6308 diff = count - dev_priv->ips.last_count2;
6309 }
6310
6311 dev_priv->ips.last_count2 = count;
6312 dev_priv->ips.last_time2 = now;
6313
6314 /* More magic constants... */
6315 diff = diff * 1181;
6316 diff = div_u64(diff, diffms * 10);
6317 dev_priv->ips.gfx_power = diff;
6318 }
6319
6320 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6321 {
6322 if (INTEL_INFO(dev_priv)->gen != 5)
6323 return;
6324
6325 spin_lock_irq(&mchdev_lock);
6326
6327 __i915_update_gfx_val(dev_priv);
6328
6329 spin_unlock_irq(&mchdev_lock);
6330 }
6331
6332 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6333 {
6334 unsigned long t, corr, state1, corr2, state2;
6335 u32 pxvid, ext_v;
6336
6337 assert_spin_locked(&mchdev_lock);
6338
6339 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6340 pxvid = (pxvid >> 24) & 0x7f;
6341 ext_v = pvid_to_extvid(dev_priv, pxvid);
6342
6343 state1 = ext_v;
6344
6345 t = i915_mch_val(dev_priv);
6346
6347 /* Revel in the empirically derived constants */
6348
6349 /* Correction factor in 1/100000 units */
6350 if (t > 80)
6351 corr = ((t * 2349) + 135940);
6352 else if (t >= 50)
6353 corr = ((t * 964) + 29317);
6354 else /* < 50 */
6355 corr = ((t * 301) + 1004);
6356
6357 corr = corr * ((150142 * state1) / 10000 - 78642);
6358 corr /= 100000;
6359 corr2 = (corr * dev_priv->ips.corr);
6360
6361 state2 = (corr2 * state1) / 10000;
6362 state2 /= 100; /* convert to mW */
6363
6364 __i915_update_gfx_val(dev_priv);
6365
6366 return dev_priv->ips.gfx_power + state2;
6367 }
6368
6369 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6370 {
6371 unsigned long val;
6372
6373 if (INTEL_INFO(dev_priv)->gen != 5)
6374 return 0;
6375
6376 spin_lock_irq(&mchdev_lock);
6377
6378 val = __i915_gfx_val(dev_priv);
6379
6380 spin_unlock_irq(&mchdev_lock);
6381
6382 return val;
6383 }
6384
6385 /**
6386 * i915_read_mch_val - return value for IPS use
6387 *
6388 * Calculate and return a value for the IPS driver to use when deciding whether
6389 * we have thermal and power headroom to increase CPU or GPU power budget.
6390 */
6391 unsigned long i915_read_mch_val(void)
6392 {
6393 struct drm_i915_private *dev_priv;
6394 unsigned long chipset_val, graphics_val, ret = 0;
6395
6396 spin_lock_irq(&mchdev_lock);
6397 if (!i915_mch_dev)
6398 goto out_unlock;
6399 dev_priv = i915_mch_dev;
6400
6401 chipset_val = __i915_chipset_val(dev_priv);
6402 graphics_val = __i915_gfx_val(dev_priv);
6403
6404 ret = chipset_val + graphics_val;
6405
6406 out_unlock:
6407 spin_unlock_irq(&mchdev_lock);
6408
6409 return ret;
6410 }
6411 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6412
6413 /**
6414 * i915_gpu_raise - raise GPU frequency limit
6415 *
6416 * Raise the limit; IPS indicates we have thermal headroom.
6417 */
6418 bool i915_gpu_raise(void)
6419 {
6420 struct drm_i915_private *dev_priv;
6421 bool ret = true;
6422
6423 spin_lock_irq(&mchdev_lock);
6424 if (!i915_mch_dev) {
6425 ret = false;
6426 goto out_unlock;
6427 }
6428 dev_priv = i915_mch_dev;
6429
6430 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6431 dev_priv->ips.max_delay--;
6432
6433 out_unlock:
6434 spin_unlock_irq(&mchdev_lock);
6435
6436 return ret;
6437 }
6438 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6439
6440 /**
6441 * i915_gpu_lower - lower GPU frequency limit
6442 *
6443 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6444 * frequency maximum.
6445 */
6446 bool i915_gpu_lower(void)
6447 {
6448 struct drm_i915_private *dev_priv;
6449 bool ret = true;
6450
6451 spin_lock_irq(&mchdev_lock);
6452 if (!i915_mch_dev) {
6453 ret = false;
6454 goto out_unlock;
6455 }
6456 dev_priv = i915_mch_dev;
6457
6458 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6459 dev_priv->ips.max_delay++;
6460
6461 out_unlock:
6462 spin_unlock_irq(&mchdev_lock);
6463
6464 return ret;
6465 }
6466 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6467
6468 /**
6469 * i915_gpu_busy - indicate GPU business to IPS
6470 *
6471 * Tell the IPS driver whether or not the GPU is busy.
6472 */
6473 bool i915_gpu_busy(void)
6474 {
6475 bool ret = false;
6476
6477 spin_lock_irq(&mchdev_lock);
6478 if (i915_mch_dev)
6479 ret = i915_mch_dev->gt.awake;
6480 spin_unlock_irq(&mchdev_lock);
6481
6482 return ret;
6483 }
6484 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6485
6486 /**
6487 * i915_gpu_turbo_disable - disable graphics turbo
6488 *
6489 * Disable graphics turbo by resetting the max frequency and setting the
6490 * current frequency to the default.
6491 */
6492 bool i915_gpu_turbo_disable(void)
6493 {
6494 struct drm_i915_private *dev_priv;
6495 bool ret = true;
6496
6497 spin_lock_irq(&mchdev_lock);
6498 if (!i915_mch_dev) {
6499 ret = false;
6500 goto out_unlock;
6501 }
6502 dev_priv = i915_mch_dev;
6503
6504 dev_priv->ips.max_delay = dev_priv->ips.fstart;
6505
6506 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6507 ret = false;
6508
6509 out_unlock:
6510 spin_unlock_irq(&mchdev_lock);
6511
6512 return ret;
6513 }
6514 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6515
6516 /**
6517 * Tells the intel_ips driver that the i915 driver is now loaded, if
6518 * IPS got loaded first.
6519 *
6520 * This awkward dance is so that neither module has to depend on the
6521 * other in order for IPS to do the appropriate communication of
6522 * GPU turbo limits to i915.
6523 */
6524 static void
6525 ips_ping_for_i915_load(void)
6526 {
6527 void (*link)(void);
6528
6529 link = symbol_get(ips_link_to_i915_driver);
6530 if (link) {
6531 link();
6532 symbol_put(ips_link_to_i915_driver);
6533 }
6534 }
6535
6536 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6537 {
6538 /* We only register the i915 ips part with intel-ips once everything is
6539 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6540 spin_lock_irq(&mchdev_lock);
6541 i915_mch_dev = dev_priv;
6542 spin_unlock_irq(&mchdev_lock);
6543
6544 ips_ping_for_i915_load();
6545 }
6546
6547 void intel_gpu_ips_teardown(void)
6548 {
6549 spin_lock_irq(&mchdev_lock);
6550 i915_mch_dev = NULL;
6551 spin_unlock_irq(&mchdev_lock);
6552 }
6553
6554 static void intel_init_emon(struct drm_i915_private *dev_priv)
6555 {
6556 u32 lcfuse;
6557 u8 pxw[16];
6558 int i;
6559
6560 /* Disable to program */
6561 I915_WRITE(ECR, 0);
6562 POSTING_READ(ECR);
6563
6564 /* Program energy weights for various events */
6565 I915_WRITE(SDEW, 0x15040d00);
6566 I915_WRITE(CSIEW0, 0x007f0000);
6567 I915_WRITE(CSIEW1, 0x1e220004);
6568 I915_WRITE(CSIEW2, 0x04000004);
6569
6570 for (i = 0; i < 5; i++)
6571 I915_WRITE(PEW(i), 0);
6572 for (i = 0; i < 3; i++)
6573 I915_WRITE(DEW(i), 0);
6574
6575 /* Program P-state weights to account for frequency power adjustment */
6576 for (i = 0; i < 16; i++) {
6577 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6578 unsigned long freq = intel_pxfreq(pxvidfreq);
6579 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6580 PXVFREQ_PX_SHIFT;
6581 unsigned long val;
6582
6583 val = vid * vid;
6584 val *= (freq / 1000);
6585 val *= 255;
6586 val /= (127*127*900);
6587 if (val > 0xff)
6588 DRM_ERROR("bad pxval: %ld\n", val);
6589 pxw[i] = val;
6590 }
6591 /* Render standby states get 0 weight */
6592 pxw[14] = 0;
6593 pxw[15] = 0;
6594
6595 for (i = 0; i < 4; i++) {
6596 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6597 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6598 I915_WRITE(PXW(i), val);
6599 }
6600
6601 /* Adjust magic regs to magic values (more experimental results) */
6602 I915_WRITE(OGW0, 0);
6603 I915_WRITE(OGW1, 0);
6604 I915_WRITE(EG0, 0x00007f00);
6605 I915_WRITE(EG1, 0x0000000e);
6606 I915_WRITE(EG2, 0x000e0000);
6607 I915_WRITE(EG3, 0x68000300);
6608 I915_WRITE(EG4, 0x42000000);
6609 I915_WRITE(EG5, 0x00140031);
6610 I915_WRITE(EG6, 0);
6611 I915_WRITE(EG7, 0);
6612
6613 for (i = 0; i < 8; i++)
6614 I915_WRITE(PXWL(i), 0);
6615
6616 /* Enable PMON + select events */
6617 I915_WRITE(ECR, 0x80000019);
6618
6619 lcfuse = I915_READ(LCFUSE02);
6620
6621 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6622 }
6623
6624 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6625 {
6626 /*
6627 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6628 * requirement.
6629 */
6630 if (!i915.enable_rc6) {
6631 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6632 intel_runtime_pm_get(dev_priv);
6633 }
6634
6635 mutex_lock(&dev_priv->drm.struct_mutex);
6636 mutex_lock(&dev_priv->rps.hw_lock);
6637
6638 /* Initialize RPS limits (for userspace) */
6639 if (IS_CHERRYVIEW(dev_priv))
6640 cherryview_init_gt_powersave(dev_priv);
6641 else if (IS_VALLEYVIEW(dev_priv))
6642 valleyview_init_gt_powersave(dev_priv);
6643 else if (INTEL_GEN(dev_priv) >= 6)
6644 gen6_init_rps_frequencies(dev_priv);
6645
6646 /* Derive initial user preferences/limits from the hardware limits */
6647 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6648 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6649
6650 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6651 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6652
6653 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6654 dev_priv->rps.min_freq_softlimit =
6655 max_t(int,
6656 dev_priv->rps.efficient_freq,
6657 intel_freq_opcode(dev_priv, 450));
6658
6659 /* After setting max-softlimit, find the overclock max freq */
6660 if (IS_GEN6(dev_priv) ||
6661 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6662 u32 params = 0;
6663
6664 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6665 if (params & BIT(31)) { /* OC supported */
6666 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6667 (dev_priv->rps.max_freq & 0xff) * 50,
6668 (params & 0xff) * 50);
6669 dev_priv->rps.max_freq = params & 0xff;
6670 }
6671 }
6672
6673 /* Finally allow us to boost to max by default */
6674 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6675
6676 mutex_unlock(&dev_priv->rps.hw_lock);
6677 mutex_unlock(&dev_priv->drm.struct_mutex);
6678
6679 intel_autoenable_gt_powersave(dev_priv);
6680 }
6681
6682 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6683 {
6684 if (IS_VALLEYVIEW(dev_priv))
6685 valleyview_cleanup_gt_powersave(dev_priv);
6686
6687 if (!i915.enable_rc6)
6688 intel_runtime_pm_put(dev_priv);
6689 }
6690
6691 /**
6692 * intel_suspend_gt_powersave - suspend PM work and helper threads
6693 * @dev_priv: i915 device
6694 *
6695 * We don't want to disable RC6 or other features here, we just want
6696 * to make sure any work we've queued has finished and won't bother
6697 * us while we're suspended.
6698 */
6699 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6700 {
6701 if (INTEL_GEN(dev_priv) < 6)
6702 return;
6703
6704 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6705 intel_runtime_pm_put(dev_priv);
6706
6707 /* gen6_rps_idle() will be called later to disable interrupts */
6708 }
6709
6710 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6711 {
6712 dev_priv->rps.enabled = true; /* force disabling */
6713 intel_disable_gt_powersave(dev_priv);
6714
6715 gen6_reset_rps_interrupts(dev_priv);
6716 }
6717
6718 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6719 {
6720 if (!READ_ONCE(dev_priv->rps.enabled))
6721 return;
6722
6723 mutex_lock(&dev_priv->rps.hw_lock);
6724
6725 if (INTEL_GEN(dev_priv) >= 9) {
6726 gen9_disable_rc6(dev_priv);
6727 gen9_disable_rps(dev_priv);
6728 } else if (IS_CHERRYVIEW(dev_priv)) {
6729 cherryview_disable_rps(dev_priv);
6730 } else if (IS_VALLEYVIEW(dev_priv)) {
6731 valleyview_disable_rps(dev_priv);
6732 } else if (INTEL_GEN(dev_priv) >= 6) {
6733 gen6_disable_rps(dev_priv);
6734 } else if (IS_IRONLAKE_M(dev_priv)) {
6735 ironlake_disable_drps(dev_priv);
6736 }
6737
6738 dev_priv->rps.enabled = false;
6739 mutex_unlock(&dev_priv->rps.hw_lock);
6740 }
6741
6742 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6743 {
6744 /* We shouldn't be disabling as we submit, so this should be less
6745 * racy than it appears!
6746 */
6747 if (READ_ONCE(dev_priv->rps.enabled))
6748 return;
6749
6750 /* Powersaving is controlled by the host when inside a VM */
6751 if (intel_vgpu_active(dev_priv))
6752 return;
6753
6754 mutex_lock(&dev_priv->rps.hw_lock);
6755
6756 if (IS_CHERRYVIEW(dev_priv)) {
6757 cherryview_enable_rps(dev_priv);
6758 } else if (IS_VALLEYVIEW(dev_priv)) {
6759 valleyview_enable_rps(dev_priv);
6760 } else if (INTEL_GEN(dev_priv) >= 9) {
6761 gen9_enable_rc6(dev_priv);
6762 gen9_enable_rps(dev_priv);
6763 if (IS_GEN9_BC(dev_priv))
6764 gen6_update_ring_freq(dev_priv);
6765 } else if (IS_BROADWELL(dev_priv)) {
6766 gen8_enable_rps(dev_priv);
6767 gen6_update_ring_freq(dev_priv);
6768 } else if (INTEL_GEN(dev_priv) >= 6) {
6769 gen6_enable_rps(dev_priv);
6770 gen6_update_ring_freq(dev_priv);
6771 } else if (IS_IRONLAKE_M(dev_priv)) {
6772 ironlake_enable_drps(dev_priv);
6773 intel_init_emon(dev_priv);
6774 }
6775
6776 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6777 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6778
6779 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6780 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6781
6782 dev_priv->rps.enabled = true;
6783 mutex_unlock(&dev_priv->rps.hw_lock);
6784 }
6785
6786 static void __intel_autoenable_gt_powersave(struct work_struct *work)
6787 {
6788 struct drm_i915_private *dev_priv =
6789 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6790 struct intel_engine_cs *rcs;
6791 struct drm_i915_gem_request *req;
6792
6793 if (READ_ONCE(dev_priv->rps.enabled))
6794 goto out;
6795
6796 rcs = dev_priv->engine[RCS];
6797 if (rcs->last_retired_context)
6798 goto out;
6799
6800 if (!rcs->init_context)
6801 goto out;
6802
6803 mutex_lock(&dev_priv->drm.struct_mutex);
6804
6805 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6806 if (IS_ERR(req))
6807 goto unlock;
6808
6809 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6810 rcs->init_context(req);
6811
6812 /* Mark the device busy, calling intel_enable_gt_powersave() */
6813 i915_add_request_no_flush(req);
6814
6815 unlock:
6816 mutex_unlock(&dev_priv->drm.struct_mutex);
6817 out:
6818 intel_runtime_pm_put(dev_priv);
6819 }
6820
6821 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6822 {
6823 if (READ_ONCE(dev_priv->rps.enabled))
6824 return;
6825
6826 if (IS_IRONLAKE_M(dev_priv)) {
6827 ironlake_enable_drps(dev_priv);
6828 intel_init_emon(dev_priv);
6829 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6830 /*
6831 * PCU communication is slow and this doesn't need to be
6832 * done at any specific time, so do this out of our fast path
6833 * to make resume and init faster.
6834 *
6835 * We depend on the HW RC6 power context save/restore
6836 * mechanism when entering D3 through runtime PM suspend. So
6837 * disable RPM until RPS/RC6 is properly setup. We can only
6838 * get here via the driver load/system resume/runtime resume
6839 * paths, so the _noresume version is enough (and in case of
6840 * runtime resume it's necessary).
6841 */
6842 if (queue_delayed_work(dev_priv->wq,
6843 &dev_priv->rps.autoenable_work,
6844 round_jiffies_up_relative(HZ)))
6845 intel_runtime_pm_get_noresume(dev_priv);
6846 }
6847 }
6848
6849 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
6850 {
6851 /*
6852 * On Ibex Peak and Cougar Point, we need to disable clock
6853 * gating for the panel power sequencer or it will fail to
6854 * start up when no ports are active.
6855 */
6856 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6857 }
6858
6859 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
6860 {
6861 enum pipe pipe;
6862
6863 for_each_pipe(dev_priv, pipe) {
6864 I915_WRITE(DSPCNTR(pipe),
6865 I915_READ(DSPCNTR(pipe)) |
6866 DISPPLANE_TRICKLE_FEED_DISABLE);
6867
6868 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6869 POSTING_READ(DSPSURF(pipe));
6870 }
6871 }
6872
6873 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
6874 {
6875 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6876 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6877 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6878
6879 /*
6880 * Don't touch WM1S_LP_EN here.
6881 * Doing so could cause underruns.
6882 */
6883 }
6884
6885 static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
6886 {
6887 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6888
6889 /*
6890 * Required for FBC
6891 * WaFbcDisableDpfcClockGating:ilk
6892 */
6893 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6894 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6895 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6896
6897 I915_WRITE(PCH_3DCGDIS0,
6898 MARIUNIT_CLOCK_GATE_DISABLE |
6899 SVSMUNIT_CLOCK_GATE_DISABLE);
6900 I915_WRITE(PCH_3DCGDIS1,
6901 VFMUNIT_CLOCK_GATE_DISABLE);
6902
6903 /*
6904 * According to the spec the following bits should be set in
6905 * order to enable memory self-refresh
6906 * The bit 22/21 of 0x42004
6907 * The bit 5 of 0x42020
6908 * The bit 15 of 0x45000
6909 */
6910 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6911 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6912 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6913 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6914 I915_WRITE(DISP_ARB_CTL,
6915 (I915_READ(DISP_ARB_CTL) |
6916 DISP_FBC_WM_DIS));
6917
6918 ilk_init_lp_watermarks(dev_priv);
6919
6920 /*
6921 * Based on the document from hardware guys the following bits
6922 * should be set unconditionally in order to enable FBC.
6923 * The bit 22 of 0x42000
6924 * The bit 22 of 0x42004
6925 * The bit 7,8,9 of 0x42020.
6926 */
6927 if (IS_IRONLAKE_M(dev_priv)) {
6928 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6929 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6930 I915_READ(ILK_DISPLAY_CHICKEN1) |
6931 ILK_FBCQ_DIS);
6932 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6933 I915_READ(ILK_DISPLAY_CHICKEN2) |
6934 ILK_DPARB_GATE);
6935 }
6936
6937 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6938
6939 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6940 I915_READ(ILK_DISPLAY_CHICKEN2) |
6941 ILK_ELPIN_409_SELECT);
6942 I915_WRITE(_3D_CHICKEN2,
6943 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6944 _3D_CHICKEN2_WM_READ_PIPELINED);
6945
6946 /* WaDisableRenderCachePipelinedFlush:ilk */
6947 I915_WRITE(CACHE_MODE_0,
6948 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6949
6950 /* WaDisable_RenderCache_OperationalFlush:ilk */
6951 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6952
6953 g4x_disable_trickle_feed(dev_priv);
6954
6955 ibx_init_clock_gating(dev_priv);
6956 }
6957
6958 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
6959 {
6960 int pipe;
6961 uint32_t val;
6962
6963 /*
6964 * On Ibex Peak and Cougar Point, we need to disable clock
6965 * gating for the panel power sequencer or it will fail to
6966 * start up when no ports are active.
6967 */
6968 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6969 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6970 PCH_CPUNIT_CLOCK_GATE_DISABLE);
6971 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6972 DPLS_EDP_PPS_FIX_DIS);
6973 /* The below fixes the weird display corruption, a few pixels shifted
6974 * downward, on (only) LVDS of some HP laptops with IVY.
6975 */
6976 for_each_pipe(dev_priv, pipe) {
6977 val = I915_READ(TRANS_CHICKEN2(pipe));
6978 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6979 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6980 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6981 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6982 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6983 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6984 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6985 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6986 }
6987 /* WADP0ClockGatingDisable */
6988 for_each_pipe(dev_priv, pipe) {
6989 I915_WRITE(TRANS_CHICKEN1(pipe),
6990 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6991 }
6992 }
6993
6994 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
6995 {
6996 uint32_t tmp;
6997
6998 tmp = I915_READ(MCH_SSKPD);
6999 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7000 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7001 tmp);
7002 }
7003
7004 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
7005 {
7006 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7007
7008 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
7009
7010 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7011 I915_READ(ILK_DISPLAY_CHICKEN2) |
7012 ILK_ELPIN_409_SELECT);
7013
7014 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
7015 I915_WRITE(_3D_CHICKEN,
7016 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7017
7018 /* WaDisable_RenderCache_OperationalFlush:snb */
7019 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7020
7021 /*
7022 * BSpec recoomends 8x4 when MSAA is used,
7023 * however in practice 16x4 seems fastest.
7024 *
7025 * Note that PS/WM thread counts depend on the WIZ hashing
7026 * disable bit, which we don't touch here, but it's good
7027 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7028 */
7029 I915_WRITE(GEN6_GT_MODE,
7030 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7031
7032 ilk_init_lp_watermarks(dev_priv);
7033
7034 I915_WRITE(CACHE_MODE_0,
7035 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
7036
7037 I915_WRITE(GEN6_UCGCTL1,
7038 I915_READ(GEN6_UCGCTL1) |
7039 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7040 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7041
7042 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7043 * gating disable must be set. Failure to set it results in
7044 * flickering pixels due to Z write ordering failures after
7045 * some amount of runtime in the Mesa "fire" demo, and Unigine
7046 * Sanctuary and Tropics, and apparently anything else with
7047 * alpha test or pixel discard.
7048 *
7049 * According to the spec, bit 11 (RCCUNIT) must also be set,
7050 * but we didn't debug actual testcases to find it out.
7051 *
7052 * WaDisableRCCUnitClockGating:snb
7053 * WaDisableRCPBUnitClockGating:snb
7054 */
7055 I915_WRITE(GEN6_UCGCTL2,
7056 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7057 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7058
7059 /* WaStripsFansDisableFastClipPerformanceFix:snb */
7060 I915_WRITE(_3D_CHICKEN3,
7061 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
7062
7063 /*
7064 * Bspec says:
7065 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7066 * 3DSTATE_SF number of SF output attributes is more than 16."
7067 */
7068 I915_WRITE(_3D_CHICKEN3,
7069 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7070
7071 /*
7072 * According to the spec the following bits should be
7073 * set in order to enable memory self-refresh and fbc:
7074 * The bit21 and bit22 of 0x42000
7075 * The bit21 and bit22 of 0x42004
7076 * The bit5 and bit7 of 0x42020
7077 * The bit14 of 0x70180
7078 * The bit14 of 0x71180
7079 *
7080 * WaFbcAsynchFlipDisableFbcQueue:snb
7081 */
7082 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7083 I915_READ(ILK_DISPLAY_CHICKEN1) |
7084 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7085 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7086 I915_READ(ILK_DISPLAY_CHICKEN2) |
7087 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7088 I915_WRITE(ILK_DSPCLK_GATE_D,
7089 I915_READ(ILK_DSPCLK_GATE_D) |
7090 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7091 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7092
7093 g4x_disable_trickle_feed(dev_priv);
7094
7095 cpt_init_clock_gating(dev_priv);
7096
7097 gen6_check_mch_setup(dev_priv);
7098 }
7099
7100 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7101 {
7102 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7103
7104 /*
7105 * WaVSThreadDispatchOverride:ivb,vlv
7106 *
7107 * This actually overrides the dispatch
7108 * mode for all thread types.
7109 */
7110 reg &= ~GEN7_FF_SCHED_MASK;
7111 reg |= GEN7_FF_TS_SCHED_HW;
7112 reg |= GEN7_FF_VS_SCHED_HW;
7113 reg |= GEN7_FF_DS_SCHED_HW;
7114
7115 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7116 }
7117
7118 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
7119 {
7120 /*
7121 * TODO: this bit should only be enabled when really needed, then
7122 * disabled when not needed anymore in order to save power.
7123 */
7124 if (HAS_PCH_LPT_LP(dev_priv))
7125 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7126 I915_READ(SOUTH_DSPCLK_GATE_D) |
7127 PCH_LP_PARTITION_LEVEL_DISABLE);
7128
7129 /* WADPOClockGatingDisable:hsw */
7130 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7131 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7132 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7133 }
7134
7135 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
7136 {
7137 if (HAS_PCH_LPT_LP(dev_priv)) {
7138 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7139
7140 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7141 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7142 }
7143 }
7144
7145 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7146 int general_prio_credits,
7147 int high_prio_credits)
7148 {
7149 u32 misccpctl;
7150
7151 /* WaTempDisableDOPClkGating:bdw */
7152 misccpctl = I915_READ(GEN7_MISCCPCTL);
7153 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7154
7155 I915_WRITE(GEN8_L3SQCREG1,
7156 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7157 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7158
7159 /*
7160 * Wait at least 100 clocks before re-enabling clock gating.
7161 * See the definition of L3SQCREG1 in BSpec.
7162 */
7163 POSTING_READ(GEN8_L3SQCREG1);
7164 udelay(1);
7165 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7166 }
7167
7168 static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
7169 {
7170 gen9_init_clock_gating(dev_priv);
7171
7172 /* WaDisableSDEUnitClockGating:kbl */
7173 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7174 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7175 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7176
7177 /* WaDisableGamClockGating:kbl */
7178 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7179 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7180 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7181
7182 /* WaFbcNukeOnHostModify:kbl */
7183 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7184 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7185 }
7186
7187 static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
7188 {
7189 gen9_init_clock_gating(dev_priv);
7190
7191 /* WAC6entrylatency:skl */
7192 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7193 FBC_LLC_FULLY_OPEN);
7194
7195 /* WaFbcNukeOnHostModify:skl */
7196 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7197 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7198 }
7199
7200 static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
7201 {
7202 enum pipe pipe;
7203
7204 ilk_init_lp_watermarks(dev_priv);
7205
7206 /* WaSwitchSolVfFArbitrationPriority:bdw */
7207 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7208
7209 /* WaPsrDPAMaskVBlankInSRD:bdw */
7210 I915_WRITE(CHICKEN_PAR1_1,
7211 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7212
7213 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7214 for_each_pipe(dev_priv, pipe) {
7215 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7216 I915_READ(CHICKEN_PIPESL_1(pipe)) |
7217 BDW_DPRS_MASK_VBLANK_SRD);
7218 }
7219
7220 /* WaVSRefCountFullforceMissDisable:bdw */
7221 /* WaDSRefCountFullforceMissDisable:bdw */
7222 I915_WRITE(GEN7_FF_THREAD_MODE,
7223 I915_READ(GEN7_FF_THREAD_MODE) &
7224 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7225
7226 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7227 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7228
7229 /* WaDisableSDEUnitClockGating:bdw */
7230 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7231 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7232
7233 /* WaProgramL3SqcReg1Default:bdw */
7234 gen8_set_l3sqc_credits(dev_priv, 30, 2);
7235
7236 /*
7237 * WaGttCachingOffByDefault:bdw
7238 * GTT cache may not work with big pages, so if those
7239 * are ever enabled GTT cache may need to be disabled.
7240 */
7241 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7242
7243 /* WaKVMNotificationOnConfigChange:bdw */
7244 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7245 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7246
7247 lpt_init_clock_gating(dev_priv);
7248
7249 /* WaDisableDopClockGating:bdw
7250 *
7251 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
7252 * clock gating.
7253 */
7254 I915_WRITE(GEN6_UCGCTL1,
7255 I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
7256 }
7257
7258 static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
7259 {
7260 ilk_init_lp_watermarks(dev_priv);
7261
7262 /* L3 caching of data atomics doesn't work -- disable it. */
7263 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7264 I915_WRITE(HSW_ROW_CHICKEN3,
7265 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7266
7267 /* This is required by WaCatErrorRejectionIssue:hsw */
7268 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7269 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7270 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7271
7272 /* WaVSRefCountFullforceMissDisable:hsw */
7273 I915_WRITE(GEN7_FF_THREAD_MODE,
7274 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7275
7276 /* WaDisable_RenderCache_OperationalFlush:hsw */
7277 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7278
7279 /* enable HiZ Raw Stall Optimization */
7280 I915_WRITE(CACHE_MODE_0_GEN7,
7281 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7282
7283 /* WaDisable4x2SubspanOptimization:hsw */
7284 I915_WRITE(CACHE_MODE_1,
7285 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7286
7287 /*
7288 * BSpec recommends 8x4 when MSAA is used,
7289 * however in practice 16x4 seems fastest.
7290 *
7291 * Note that PS/WM thread counts depend on the WIZ hashing
7292 * disable bit, which we don't touch here, but it's good
7293 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7294 */
7295 I915_WRITE(GEN7_GT_MODE,
7296 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7297
7298 /* WaSampleCChickenBitEnable:hsw */
7299 I915_WRITE(HALF_SLICE_CHICKEN3,
7300 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7301
7302 /* WaSwitchSolVfFArbitrationPriority:hsw */
7303 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7304
7305 /* WaRsPkgCStateDisplayPMReq:hsw */
7306 I915_WRITE(CHICKEN_PAR1_1,
7307 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7308
7309 lpt_init_clock_gating(dev_priv);
7310 }
7311
7312 static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
7313 {
7314 uint32_t snpcr;
7315
7316 ilk_init_lp_watermarks(dev_priv);
7317
7318 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7319
7320 /* WaDisableEarlyCull:ivb */
7321 I915_WRITE(_3D_CHICKEN3,
7322 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7323
7324 /* WaDisableBackToBackFlipFix:ivb */
7325 I915_WRITE(IVB_CHICKEN3,
7326 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7327 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7328
7329 /* WaDisablePSDDualDispatchEnable:ivb */
7330 if (IS_IVB_GT1(dev_priv))
7331 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7332 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7333
7334 /* WaDisable_RenderCache_OperationalFlush:ivb */
7335 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7336
7337 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7338 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7339 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7340
7341 /* WaApplyL3ControlAndL3ChickenMode:ivb */
7342 I915_WRITE(GEN7_L3CNTLREG1,
7343 GEN7_WA_FOR_GEN7_L3_CONTROL);
7344 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7345 GEN7_WA_L3_CHICKEN_MODE);
7346 if (IS_IVB_GT1(dev_priv))
7347 I915_WRITE(GEN7_ROW_CHICKEN2,
7348 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7349 else {
7350 /* must write both registers */
7351 I915_WRITE(GEN7_ROW_CHICKEN2,
7352 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7353 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7354 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7355 }
7356
7357 /* WaForceL3Serialization:ivb */
7358 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7359 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7360
7361 /*
7362 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7363 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7364 */
7365 I915_WRITE(GEN6_UCGCTL2,
7366 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7367
7368 /* This is required by WaCatErrorRejectionIssue:ivb */
7369 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7370 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7371 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7372
7373 g4x_disable_trickle_feed(dev_priv);
7374
7375 gen7_setup_fixed_func_scheduler(dev_priv);
7376
7377 if (0) { /* causes HiZ corruption on ivb:gt1 */
7378 /* enable HiZ Raw Stall Optimization */
7379 I915_WRITE(CACHE_MODE_0_GEN7,
7380 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7381 }
7382
7383 /* WaDisable4x2SubspanOptimization:ivb */
7384 I915_WRITE(CACHE_MODE_1,
7385 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7386
7387 /*
7388 * BSpec recommends 8x4 when MSAA is used,
7389 * however in practice 16x4 seems fastest.
7390 *
7391 * Note that PS/WM thread counts depend on the WIZ hashing
7392 * disable bit, which we don't touch here, but it's good
7393 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7394 */
7395 I915_WRITE(GEN7_GT_MODE,
7396 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7397
7398 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7399 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7400 snpcr |= GEN6_MBC_SNPCR_MED;
7401 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7402
7403 if (!HAS_PCH_NOP(dev_priv))
7404 cpt_init_clock_gating(dev_priv);
7405
7406 gen6_check_mch_setup(dev_priv);
7407 }
7408
7409 static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
7410 {
7411 /* WaDisableEarlyCull:vlv */
7412 I915_WRITE(_3D_CHICKEN3,
7413 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7414
7415 /* WaDisableBackToBackFlipFix:vlv */
7416 I915_WRITE(IVB_CHICKEN3,
7417 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7418 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7419
7420 /* WaPsdDispatchEnable:vlv */
7421 /* WaDisablePSDDualDispatchEnable:vlv */
7422 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7423 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7424 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7425
7426 /* WaDisable_RenderCache_OperationalFlush:vlv */
7427 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7428
7429 /* WaForceL3Serialization:vlv */
7430 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7431 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7432
7433 /* WaDisableDopClockGating:vlv */
7434 I915_WRITE(GEN7_ROW_CHICKEN2,
7435 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7436
7437 /* This is required by WaCatErrorRejectionIssue:vlv */
7438 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7439 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7440 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7441
7442 gen7_setup_fixed_func_scheduler(dev_priv);
7443
7444 /*
7445 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7446 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7447 */
7448 I915_WRITE(GEN6_UCGCTL2,
7449 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7450
7451 /* WaDisableL3Bank2xClockGate:vlv
7452 * Disabling L3 clock gating- MMIO 940c[25] = 1
7453 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7454 I915_WRITE(GEN7_UCGCTL4,
7455 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7456
7457 /*
7458 * BSpec says this must be set, even though
7459 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7460 */
7461 I915_WRITE(CACHE_MODE_1,
7462 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7463
7464 /*
7465 * BSpec recommends 8x4 when MSAA is used,
7466 * however in practice 16x4 seems fastest.
7467 *
7468 * Note that PS/WM thread counts depend on the WIZ hashing
7469 * disable bit, which we don't touch here, but it's good
7470 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7471 */
7472 I915_WRITE(GEN7_GT_MODE,
7473 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7474
7475 /*
7476 * WaIncreaseL3CreditsForVLVB0:vlv
7477 * This is the hardware default actually.
7478 */
7479 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7480
7481 /*
7482 * WaDisableVLVClockGating_VBIIssue:vlv
7483 * Disable clock gating on th GCFG unit to prevent a delay
7484 * in the reporting of vblank events.
7485 */
7486 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7487 }
7488
7489 static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
7490 {
7491 /* WaVSRefCountFullforceMissDisable:chv */
7492 /* WaDSRefCountFullforceMissDisable:chv */
7493 I915_WRITE(GEN7_FF_THREAD_MODE,
7494 I915_READ(GEN7_FF_THREAD_MODE) &
7495 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7496
7497 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7498 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7499 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7500
7501 /* WaDisableCSUnitClockGating:chv */
7502 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7503 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7504
7505 /* WaDisableSDEUnitClockGating:chv */
7506 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7507 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7508
7509 /*
7510 * WaProgramL3SqcReg1Default:chv
7511 * See gfxspecs/Related Documents/Performance Guide/
7512 * LSQC Setting Recommendations.
7513 */
7514 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7515
7516 /*
7517 * GTT cache may not work with big pages, so if those
7518 * are ever enabled GTT cache may need to be disabled.
7519 */
7520 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7521 }
7522
7523 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
7524 {
7525 uint32_t dspclk_gate;
7526
7527 I915_WRITE(RENCLK_GATE_D1, 0);
7528 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7529 GS_UNIT_CLOCK_GATE_DISABLE |
7530 CL_UNIT_CLOCK_GATE_DISABLE);
7531 I915_WRITE(RAMCLK_GATE_D, 0);
7532 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7533 OVRUNIT_CLOCK_GATE_DISABLE |
7534 OVCUNIT_CLOCK_GATE_DISABLE;
7535 if (IS_GM45(dev_priv))
7536 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7537 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7538
7539 /* WaDisableRenderCachePipelinedFlush */
7540 I915_WRITE(CACHE_MODE_0,
7541 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7542
7543 /* WaDisable_RenderCache_OperationalFlush:g4x */
7544 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7545
7546 g4x_disable_trickle_feed(dev_priv);
7547 }
7548
7549 static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
7550 {
7551 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7552 I915_WRITE(RENCLK_GATE_D2, 0);
7553 I915_WRITE(DSPCLK_GATE_D, 0);
7554 I915_WRITE(RAMCLK_GATE_D, 0);
7555 I915_WRITE16(DEUC, 0);
7556 I915_WRITE(MI_ARB_STATE,
7557 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7558
7559 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7560 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7561 }
7562
7563 static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
7564 {
7565 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7566 I965_RCC_CLOCK_GATE_DISABLE |
7567 I965_RCPB_CLOCK_GATE_DISABLE |
7568 I965_ISC_CLOCK_GATE_DISABLE |
7569 I965_FBC_CLOCK_GATE_DISABLE);
7570 I915_WRITE(RENCLK_GATE_D2, 0);
7571 I915_WRITE(MI_ARB_STATE,
7572 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7573
7574 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7575 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7576 }
7577
7578 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
7579 {
7580 u32 dstate = I915_READ(D_STATE);
7581
7582 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7583 DSTATE_DOT_CLOCK_GATING;
7584 I915_WRITE(D_STATE, dstate);
7585
7586 if (IS_PINEVIEW(dev_priv))
7587 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7588
7589 /* IIR "flip pending" means done if this bit is set */
7590 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7591
7592 /* interrupts should cause a wake up from C3 */
7593 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7594
7595 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7596 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7597
7598 I915_WRITE(MI_ARB_STATE,
7599 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7600 }
7601
7602 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
7603 {
7604 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7605
7606 /* interrupts should cause a wake up from C3 */
7607 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7608 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7609
7610 I915_WRITE(MEM_MODE,
7611 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7612 }
7613
7614 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
7615 {
7616 I915_WRITE(MEM_MODE,
7617 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7618 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7619 }
7620
7621 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
7622 {
7623 dev_priv->display.init_clock_gating(dev_priv);
7624 }
7625
7626 void intel_suspend_hw(struct drm_i915_private *dev_priv)
7627 {
7628 if (HAS_PCH_LPT(dev_priv))
7629 lpt_suspend_hw(dev_priv);
7630 }
7631
7632 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
7633 {
7634 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7635 }
7636
7637 /**
7638 * intel_init_clock_gating_hooks - setup the clock gating hooks
7639 * @dev_priv: device private
7640 *
7641 * Setup the hooks that configure which clocks of a given platform can be
7642 * gated and also apply various GT and display specific workarounds for these
7643 * platforms. Note that some GT specific workarounds are applied separately
7644 * when GPU contexts or batchbuffers start their execution.
7645 */
7646 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7647 {
7648 if (IS_SKYLAKE(dev_priv))
7649 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7650 else if (IS_KABYLAKE(dev_priv))
7651 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7652 else if (IS_BROXTON(dev_priv))
7653 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7654 else if (IS_GEMINILAKE(dev_priv))
7655 dev_priv->display.init_clock_gating = glk_init_clock_gating;
7656 else if (IS_BROADWELL(dev_priv))
7657 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7658 else if (IS_CHERRYVIEW(dev_priv))
7659 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7660 else if (IS_HASWELL(dev_priv))
7661 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7662 else if (IS_IVYBRIDGE(dev_priv))
7663 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7664 else if (IS_VALLEYVIEW(dev_priv))
7665 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7666 else if (IS_GEN6(dev_priv))
7667 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7668 else if (IS_GEN5(dev_priv))
7669 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7670 else if (IS_G4X(dev_priv))
7671 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7672 else if (IS_I965GM(dev_priv))
7673 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7674 else if (IS_I965G(dev_priv))
7675 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7676 else if (IS_GEN3(dev_priv))
7677 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7678 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7679 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7680 else if (IS_GEN2(dev_priv))
7681 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7682 else {
7683 MISSING_CASE(INTEL_DEVID(dev_priv));
7684 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7685 }
7686 }
7687
7688 /* Set up chip specific power management-related functions */
7689 void intel_init_pm(struct drm_i915_private *dev_priv)
7690 {
7691 intel_fbc_init(dev_priv);
7692
7693 /* For cxsr */
7694 if (IS_PINEVIEW(dev_priv))
7695 i915_pineview_get_mem_freq(dev_priv);
7696 else if (IS_GEN5(dev_priv))
7697 i915_ironlake_get_mem_freq(dev_priv);
7698
7699 /* For FIFO watermark updates */
7700 if (INTEL_GEN(dev_priv) >= 9) {
7701 skl_setup_wm_latency(dev_priv);
7702 dev_priv->display.initial_watermarks = skl_initial_wm;
7703 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
7704 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7705 } else if (HAS_PCH_SPLIT(dev_priv)) {
7706 ilk_setup_wm_latency(dev_priv);
7707
7708 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
7709 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7710 (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
7711 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7712 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7713 dev_priv->display.compute_intermediate_wm =
7714 ilk_compute_intermediate_wm;
7715 dev_priv->display.initial_watermarks =
7716 ilk_initial_watermarks;
7717 dev_priv->display.optimize_watermarks =
7718 ilk_optimize_watermarks;
7719 } else {
7720 DRM_DEBUG_KMS("Failed to read display plane latency. "
7721 "Disable CxSR\n");
7722 }
7723 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7724 vlv_setup_wm_latency(dev_priv);
7725 dev_priv->display.update_wm = vlv_update_wm;
7726 } else if (IS_PINEVIEW(dev_priv)) {
7727 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
7728 dev_priv->is_ddr3,
7729 dev_priv->fsb_freq,
7730 dev_priv->mem_freq)) {
7731 DRM_INFO("failed to find known CxSR latency "
7732 "(found ddr%s fsb freq %d, mem freq %d), "
7733 "disabling CxSR\n",
7734 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7735 dev_priv->fsb_freq, dev_priv->mem_freq);
7736 /* Disable CxSR and never update its watermark again */
7737 intel_set_memory_cxsr(dev_priv, false);
7738 dev_priv->display.update_wm = NULL;
7739 } else
7740 dev_priv->display.update_wm = pineview_update_wm;
7741 } else if (IS_G4X(dev_priv)) {
7742 dev_priv->display.update_wm = g4x_update_wm;
7743 } else if (IS_GEN4(dev_priv)) {
7744 dev_priv->display.update_wm = i965_update_wm;
7745 } else if (IS_GEN3(dev_priv)) {
7746 dev_priv->display.update_wm = i9xx_update_wm;
7747 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7748 } else if (IS_GEN2(dev_priv)) {
7749 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
7750 dev_priv->display.update_wm = i845_update_wm;
7751 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7752 } else {
7753 dev_priv->display.update_wm = i9xx_update_wm;
7754 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7755 }
7756 } else {
7757 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7758 }
7759 }
7760
7761 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7762 {
7763 uint32_t flags =
7764 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7765
7766 switch (flags) {
7767 case GEN6_PCODE_SUCCESS:
7768 return 0;
7769 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7770 case GEN6_PCODE_ILLEGAL_CMD:
7771 return -ENXIO;
7772 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7773 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7774 return -EOVERFLOW;
7775 case GEN6_PCODE_TIMEOUT:
7776 return -ETIMEDOUT;
7777 default:
7778 MISSING_CASE(flags)
7779 return 0;
7780 }
7781 }
7782
7783 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7784 {
7785 uint32_t flags =
7786 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7787
7788 switch (flags) {
7789 case GEN6_PCODE_SUCCESS:
7790 return 0;
7791 case GEN6_PCODE_ILLEGAL_CMD:
7792 return -ENXIO;
7793 case GEN7_PCODE_TIMEOUT:
7794 return -ETIMEDOUT;
7795 case GEN7_PCODE_ILLEGAL_DATA:
7796 return -EINVAL;
7797 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7798 return -EOVERFLOW;
7799 default:
7800 MISSING_CASE(flags);
7801 return 0;
7802 }
7803 }
7804
7805 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7806 {
7807 int status;
7808
7809 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7810
7811 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7812 * use te fw I915_READ variants to reduce the amount of work
7813 * required when reading/writing.
7814 */
7815
7816 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7817 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7818 return -EAGAIN;
7819 }
7820
7821 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7822 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7823 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7824
7825 if (intel_wait_for_register_fw(dev_priv,
7826 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7827 500)) {
7828 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7829 return -ETIMEDOUT;
7830 }
7831
7832 *val = I915_READ_FW(GEN6_PCODE_DATA);
7833 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7834
7835 if (INTEL_GEN(dev_priv) > 6)
7836 status = gen7_check_mailbox_status(dev_priv);
7837 else
7838 status = gen6_check_mailbox_status(dev_priv);
7839
7840 if (status) {
7841 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7842 status);
7843 return status;
7844 }
7845
7846 return 0;
7847 }
7848
7849 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7850 u32 mbox, u32 val)
7851 {
7852 int status;
7853
7854 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7855
7856 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7857 * use te fw I915_READ variants to reduce the amount of work
7858 * required when reading/writing.
7859 */
7860
7861 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7862 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7863 return -EAGAIN;
7864 }
7865
7866 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7867 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7868 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7869
7870 if (intel_wait_for_register_fw(dev_priv,
7871 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7872 500)) {
7873 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7874 return -ETIMEDOUT;
7875 }
7876
7877 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7878
7879 if (INTEL_GEN(dev_priv) > 6)
7880 status = gen7_check_mailbox_status(dev_priv);
7881 else
7882 status = gen6_check_mailbox_status(dev_priv);
7883
7884 if (status) {
7885 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7886 status);
7887 return status;
7888 }
7889
7890 return 0;
7891 }
7892
7893 static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
7894 u32 request, u32 reply_mask, u32 reply,
7895 u32 *status)
7896 {
7897 u32 val = request;
7898
7899 *status = sandybridge_pcode_read(dev_priv, mbox, &val);
7900
7901 return *status || ((val & reply_mask) == reply);
7902 }
7903
7904 /**
7905 * skl_pcode_request - send PCODE request until acknowledgment
7906 * @dev_priv: device private
7907 * @mbox: PCODE mailbox ID the request is targeted for
7908 * @request: request ID
7909 * @reply_mask: mask used to check for request acknowledgment
7910 * @reply: value used to check for request acknowledgment
7911 * @timeout_base_ms: timeout for polling with preemption enabled
7912 *
7913 * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
7914 * reports an error or an overall timeout of @timeout_base_ms+10 ms expires.
7915 * The request is acknowledged once the PCODE reply dword equals @reply after
7916 * applying @reply_mask. Polling is first attempted with preemption enabled
7917 * for @timeout_base_ms and if this times out for another 10 ms with
7918 * preemption disabled.
7919 *
7920 * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
7921 * other error as reported by PCODE.
7922 */
7923 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
7924 u32 reply_mask, u32 reply, int timeout_base_ms)
7925 {
7926 u32 status;
7927 int ret;
7928
7929 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7930
7931 #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
7932 &status)
7933
7934 /*
7935 * Prime the PCODE by doing a request first. Normally it guarantees
7936 * that a subsequent request, at most @timeout_base_ms later, succeeds.
7937 * _wait_for() doesn't guarantee when its passed condition is evaluated
7938 * first, so send the first request explicitly.
7939 */
7940 if (COND) {
7941 ret = 0;
7942 goto out;
7943 }
7944 ret = _wait_for(COND, timeout_base_ms * 1000, 10);
7945 if (!ret)
7946 goto out;
7947
7948 /*
7949 * The above can time out if the number of requests was low (2 in the
7950 * worst case) _and_ PCODE was busy for some reason even after a
7951 * (queued) request and @timeout_base_ms delay. As a workaround retry
7952 * the poll with preemption disabled to maximize the number of
7953 * requests. Increase the timeout from @timeout_base_ms to 10ms to
7954 * account for interrupts that could reduce the number of these
7955 * requests.
7956 */
7957 DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
7958 WARN_ON_ONCE(timeout_base_ms > 3);
7959 preempt_disable();
7960 ret = wait_for_atomic(COND, 10);
7961 preempt_enable();
7962
7963 out:
7964 return ret ? ret : status;
7965 #undef COND
7966 }
7967
7968 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7969 {
7970 /*
7971 * N = val - 0xb7
7972 * Slow = Fast = GPLL ref * N
7973 */
7974 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7975 }
7976
7977 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7978 {
7979 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7980 }
7981
7982 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7983 {
7984 /*
7985 * N = val / 2
7986 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7987 */
7988 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7989 }
7990
7991 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7992 {
7993 /* CHV needs even values */
7994 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7995 }
7996
7997 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7998 {
7999 if (IS_GEN9(dev_priv))
8000 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
8001 GEN9_FREQ_SCALER);
8002 else if (IS_CHERRYVIEW(dev_priv))
8003 return chv_gpu_freq(dev_priv, val);
8004 else if (IS_VALLEYVIEW(dev_priv))
8005 return byt_gpu_freq(dev_priv, val);
8006 else
8007 return val * GT_FREQUENCY_MULTIPLIER;
8008 }
8009
8010 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
8011 {
8012 if (IS_GEN9(dev_priv))
8013 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
8014 GT_FREQUENCY_MULTIPLIER);
8015 else if (IS_CHERRYVIEW(dev_priv))
8016 return chv_freq_opcode(dev_priv, val);
8017 else if (IS_VALLEYVIEW(dev_priv))
8018 return byt_freq_opcode(dev_priv, val);
8019 else
8020 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
8021 }
8022
8023 struct request_boost {
8024 struct work_struct work;
8025 struct drm_i915_gem_request *req;
8026 };
8027
8028 static void __intel_rps_boost_work(struct work_struct *work)
8029 {
8030 struct request_boost *boost = container_of(work, struct request_boost, work);
8031 struct drm_i915_gem_request *req = boost->req;
8032
8033 if (!i915_gem_request_completed(req))
8034 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
8035
8036 i915_gem_request_put(req);
8037 kfree(boost);
8038 }
8039
8040 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
8041 {
8042 struct request_boost *boost;
8043
8044 if (req == NULL || INTEL_GEN(req->i915) < 6)
8045 return;
8046
8047 if (i915_gem_request_completed(req))
8048 return;
8049
8050 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8051 if (boost == NULL)
8052 return;
8053
8054 boost->req = i915_gem_request_get(req);
8055
8056 INIT_WORK(&boost->work, __intel_rps_boost_work);
8057 queue_work(req->i915->wq, &boost->work);
8058 }
8059
8060 void intel_pm_setup(struct drm_i915_private *dev_priv)
8061 {
8062 mutex_init(&dev_priv->rps.hw_lock);
8063 spin_lock_init(&dev_priv->rps.client_lock);
8064
8065 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8066 __intel_autoenable_gt_powersave);
8067 INIT_LIST_HEAD(&dev_priv->rps.clients);
8068
8069 dev_priv->pm.suspended = false;
8070 atomic_set(&dev_priv->pm.wakeref_count, 0);
8071 }
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