2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
34 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
35 * framebuffer contents in-memory, aiming at reducing the required bandwidth
36 * during in-memory transfers and, therefore, reduce the power packet.
38 * The benefits of FBC are mostly visible with solid backgrounds and
39 * variation-less patterns.
41 * FBC-related functionality can be enabled by the means of the
42 * i915.i915_enable_fbc parameter
45 static void i8xx_disable_fbc(struct drm_device
*dev
)
47 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
50 /* Disable compression */
51 fbc_ctl
= I915_READ(FBC_CONTROL
);
52 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
55 fbc_ctl
&= ~FBC_CTL_EN
;
56 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
58 /* Wait for compressing bit to clear */
59 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
60 DRM_DEBUG_KMS("FBC idle timed out\n");
64 DRM_DEBUG_KMS("disabled FBC\n");
67 static void i8xx_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
69 struct drm_device
*dev
= crtc
->dev
;
70 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
71 struct drm_framebuffer
*fb
= crtc
->fb
;
72 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
73 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
74 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
77 u32 fbc_ctl
, fbc_ctl2
;
79 cfb_pitch
= dev_priv
->cfb_size
/ FBC_LL_SIZE
;
80 if (fb
->pitches
[0] < cfb_pitch
)
81 cfb_pitch
= fb
->pitches
[0];
83 /* FBC_CTL wants 64B units */
84 cfb_pitch
= (cfb_pitch
/ 64) - 1;
85 plane
= intel_crtc
->plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
88 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
89 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
92 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| FBC_CTL_CPU_FENCE
;
94 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
95 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
98 fbc_ctl
= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
100 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
101 fbc_ctl
|= (cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
102 fbc_ctl
|= (interval
& 0x2fff) << FBC_CTL_INTERVAL_SHIFT
;
103 fbc_ctl
|= obj
->fence_reg
;
104 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
106 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
107 cfb_pitch
, crtc
->y
, intel_crtc
->plane
);
110 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
112 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
114 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
117 static void g4x_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
119 struct drm_device
*dev
= crtc
->dev
;
120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
121 struct drm_framebuffer
*fb
= crtc
->fb
;
122 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
123 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
124 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
125 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
126 unsigned long stall_watermark
= 200;
129 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
130 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| obj
->fence_reg
;
131 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
133 I915_WRITE(DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
134 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
135 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
136 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
139 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
141 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
144 static void g4x_disable_fbc(struct drm_device
*dev
)
146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
149 /* Disable compression */
150 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
151 if (dpfc_ctl
& DPFC_CTL_EN
) {
152 dpfc_ctl
&= ~DPFC_CTL_EN
;
153 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
155 DRM_DEBUG_KMS("disabled FBC\n");
159 static bool g4x_fbc_enabled(struct drm_device
*dev
)
161 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
163 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
166 static void sandybridge_blit_fbc_update(struct drm_device
*dev
)
168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
171 /* Make sure blitter notifies FBC of writes */
172 gen6_gt_force_wake_get(dev_priv
);
173 blt_ecoskpd
= I915_READ(GEN6_BLITTER_ECOSKPD
);
174 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
<<
175 GEN6_BLITTER_LOCK_SHIFT
;
176 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
177 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
;
178 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
179 blt_ecoskpd
&= ~(GEN6_BLITTER_FBC_NOTIFY
<<
180 GEN6_BLITTER_LOCK_SHIFT
);
181 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
182 POSTING_READ(GEN6_BLITTER_ECOSKPD
);
183 gen6_gt_force_wake_put(dev_priv
);
186 static void ironlake_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
188 struct drm_device
*dev
= crtc
->dev
;
189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
190 struct drm_framebuffer
*fb
= crtc
->fb
;
191 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
192 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
193 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
194 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
195 unsigned long stall_watermark
= 200;
198 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
199 dpfc_ctl
&= DPFC_RESERVED
;
200 dpfc_ctl
|= (plane
| DPFC_CTL_LIMIT_1X
);
201 /* Set persistent mode for front-buffer rendering, ala X. */
202 dpfc_ctl
|= DPFC_CTL_PERSISTENT_MODE
;
203 dpfc_ctl
|= (DPFC_CTL_FENCE_EN
| obj
->fence_reg
);
204 I915_WRITE(ILK_DPFC_CHICKEN
, DPFC_HT_MODIFY
);
206 I915_WRITE(ILK_DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
207 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
208 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
209 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
210 I915_WRITE(ILK_FBC_RT_BASE
, obj
->gtt_offset
| ILK_FBC_RT_VALID
);
212 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
215 I915_WRITE(SNB_DPFC_CTL_SA
,
216 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
217 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
218 sandybridge_blit_fbc_update(dev
);
221 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
224 static void ironlake_disable_fbc(struct drm_device
*dev
)
226 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
229 /* Disable compression */
230 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
231 if (dpfc_ctl
& DPFC_CTL_EN
) {
232 dpfc_ctl
&= ~DPFC_CTL_EN
;
233 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
235 DRM_DEBUG_KMS("disabled FBC\n");
239 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
243 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
246 bool intel_fbc_enabled(struct drm_device
*dev
)
248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
250 if (!dev_priv
->display
.fbc_enabled
)
253 return dev_priv
->display
.fbc_enabled(dev
);
256 static void intel_fbc_work_fn(struct work_struct
*__work
)
258 struct intel_fbc_work
*work
=
259 container_of(to_delayed_work(__work
),
260 struct intel_fbc_work
, work
);
261 struct drm_device
*dev
= work
->crtc
->dev
;
262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
264 mutex_lock(&dev
->struct_mutex
);
265 if (work
== dev_priv
->fbc_work
) {
266 /* Double check that we haven't switched fb without cancelling
269 if (work
->crtc
->fb
== work
->fb
) {
270 dev_priv
->display
.enable_fbc(work
->crtc
,
273 dev_priv
->cfb_plane
= to_intel_crtc(work
->crtc
)->plane
;
274 dev_priv
->cfb_fb
= work
->crtc
->fb
->base
.id
;
275 dev_priv
->cfb_y
= work
->crtc
->y
;
278 dev_priv
->fbc_work
= NULL
;
280 mutex_unlock(&dev
->struct_mutex
);
285 static void intel_cancel_fbc_work(struct drm_i915_private
*dev_priv
)
287 if (dev_priv
->fbc_work
== NULL
)
290 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
292 /* Synchronisation is provided by struct_mutex and checking of
293 * dev_priv->fbc_work, so we can perform the cancellation
294 * entirely asynchronously.
296 if (cancel_delayed_work(&dev_priv
->fbc_work
->work
))
297 /* tasklet was killed before being run, clean up */
298 kfree(dev_priv
->fbc_work
);
300 /* Mark the work as no longer wanted so that if it does
301 * wake-up (because the work was already running and waiting
302 * for our mutex), it will discover that is no longer
305 dev_priv
->fbc_work
= NULL
;
308 void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
310 struct intel_fbc_work
*work
;
311 struct drm_device
*dev
= crtc
->dev
;
312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
314 if (!dev_priv
->display
.enable_fbc
)
317 intel_cancel_fbc_work(dev_priv
);
319 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
321 dev_priv
->display
.enable_fbc(crtc
, interval
);
327 work
->interval
= interval
;
328 INIT_DELAYED_WORK(&work
->work
, intel_fbc_work_fn
);
330 dev_priv
->fbc_work
= work
;
332 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
334 /* Delay the actual enabling to let pageflipping cease and the
335 * display to settle before starting the compression. Note that
336 * this delay also serves a second purpose: it allows for a
337 * vblank to pass after disabling the FBC before we attempt
338 * to modify the control registers.
340 * A more complicated solution would involve tracking vblanks
341 * following the termination of the page-flipping sequence
342 * and indeed performing the enable as a co-routine and not
343 * waiting synchronously upon the vblank.
345 schedule_delayed_work(&work
->work
, msecs_to_jiffies(50));
348 void intel_disable_fbc(struct drm_device
*dev
)
350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
352 intel_cancel_fbc_work(dev_priv
);
354 if (!dev_priv
->display
.disable_fbc
)
357 dev_priv
->display
.disable_fbc(dev
);
358 dev_priv
->cfb_plane
= -1;
362 * intel_update_fbc - enable/disable FBC as needed
363 * @dev: the drm_device
365 * Set up the framebuffer compression hardware at mode set time. We
366 * enable it if possible:
367 * - plane A only (on pre-965)
368 * - no pixel mulitply/line duplication
369 * - no alpha buffer discard
371 * - framebuffer <= 2048 in width, 1536 in height
373 * We can't assume that any compression will take place (worst case),
374 * so the compressed buffer has to be the same size as the uncompressed
375 * one. It also must reside (along with the line length buffer) in
378 * We need to enable/disable FBC on a global basis.
380 void intel_update_fbc(struct drm_device
*dev
)
382 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
383 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
384 struct intel_crtc
*intel_crtc
;
385 struct drm_framebuffer
*fb
;
386 struct intel_framebuffer
*intel_fb
;
387 struct drm_i915_gem_object
*obj
;
393 if (!I915_HAS_FBC(dev
))
397 * If FBC is already on, we just have to verify that we can
398 * keep it that way...
399 * Need to disable if:
400 * - more than one pipe is active
401 * - changing FBC params (stride, fence, mode)
402 * - new fb is too large to fit in compressed buffer
403 * - going to an unsupported config (interlace, pixel multiply, etc.)
405 list_for_each_entry(tmp_crtc
, &dev
->mode_config
.crtc_list
, head
) {
406 if (tmp_crtc
->enabled
&&
407 !to_intel_crtc(tmp_crtc
)->primary_disabled
&&
410 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
411 dev_priv
->no_fbc_reason
= FBC_MULTIPLE_PIPES
;
418 if (!crtc
|| crtc
->fb
== NULL
) {
419 DRM_DEBUG_KMS("no output, disabling\n");
420 dev_priv
->no_fbc_reason
= FBC_NO_OUTPUT
;
424 intel_crtc
= to_intel_crtc(crtc
);
426 intel_fb
= to_intel_framebuffer(fb
);
429 enable_fbc
= i915_enable_fbc
;
430 if (enable_fbc
< 0) {
431 DRM_DEBUG_KMS("fbc set to per-chip default\n");
433 if (INTEL_INFO(dev
)->gen
<= 6)
437 DRM_DEBUG_KMS("fbc disabled per module param\n");
438 dev_priv
->no_fbc_reason
= FBC_MODULE_PARAM
;
441 if (intel_fb
->obj
->base
.size
> dev_priv
->cfb_size
) {
442 DRM_DEBUG_KMS("framebuffer too large, disabling "
444 dev_priv
->no_fbc_reason
= FBC_STOLEN_TOO_SMALL
;
447 if ((crtc
->mode
.flags
& DRM_MODE_FLAG_INTERLACE
) ||
448 (crtc
->mode
.flags
& DRM_MODE_FLAG_DBLSCAN
)) {
449 DRM_DEBUG_KMS("mode incompatible with compression, "
451 dev_priv
->no_fbc_reason
= FBC_UNSUPPORTED_MODE
;
454 if ((crtc
->mode
.hdisplay
> 2048) ||
455 (crtc
->mode
.vdisplay
> 1536)) {
456 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
457 dev_priv
->no_fbc_reason
= FBC_MODE_TOO_LARGE
;
460 if ((IS_I915GM(dev
) || IS_I945GM(dev
)) && intel_crtc
->plane
!= 0) {
461 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
462 dev_priv
->no_fbc_reason
= FBC_BAD_PLANE
;
466 /* The use of a CPU fence is mandatory in order to detect writes
467 * by the CPU to the scanout and trigger updates to the FBC.
469 if (obj
->tiling_mode
!= I915_TILING_X
||
470 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
471 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
472 dev_priv
->no_fbc_reason
= FBC_NOT_TILED
;
476 /* If the kernel debugger is active, always disable compression */
480 /* If the scanout has not changed, don't modify the FBC settings.
481 * Note that we make the fundamental assumption that the fb->obj
482 * cannot be unpinned (and have its GTT offset and fence revoked)
483 * without first being decoupled from the scanout and FBC disabled.
485 if (dev_priv
->cfb_plane
== intel_crtc
->plane
&&
486 dev_priv
->cfb_fb
== fb
->base
.id
&&
487 dev_priv
->cfb_y
== crtc
->y
)
490 if (intel_fbc_enabled(dev
)) {
491 /* We update FBC along two paths, after changing fb/crtc
492 * configuration (modeswitching) and after page-flipping
493 * finishes. For the latter, we know that not only did
494 * we disable the FBC at the start of the page-flip
495 * sequence, but also more than one vblank has passed.
497 * For the former case of modeswitching, it is possible
498 * to switch between two FBC valid configurations
499 * instantaneously so we do need to disable the FBC
500 * before we can modify its control registers. We also
501 * have to wait for the next vblank for that to take
502 * effect. However, since we delay enabling FBC we can
503 * assume that a vblank has passed since disabling and
504 * that we can safely alter the registers in the deferred
507 * In the scenario that we go from a valid to invalid
508 * and then back to valid FBC configuration we have
509 * no strict enforcement that a vblank occurred since
510 * disabling the FBC. However, along all current pipe
511 * disabling paths we do need to wait for a vblank at
512 * some point. And we wait before enabling FBC anyway.
514 DRM_DEBUG_KMS("disabling active FBC for update\n");
515 intel_disable_fbc(dev
);
518 intel_enable_fbc(crtc
, 500);
522 /* Multiple disables should be harmless */
523 if (intel_fbc_enabled(dev
)) {
524 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
525 intel_disable_fbc(dev
);
529 static void i915_pineview_get_mem_freq(struct drm_device
*dev
)
531 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
534 tmp
= I915_READ(CLKCFG
);
536 switch (tmp
& CLKCFG_FSB_MASK
) {
538 dev_priv
->fsb_freq
= 533; /* 133*4 */
541 dev_priv
->fsb_freq
= 800; /* 200*4 */
544 dev_priv
->fsb_freq
= 667; /* 167*4 */
547 dev_priv
->fsb_freq
= 400; /* 100*4 */
551 switch (tmp
& CLKCFG_MEM_MASK
) {
553 dev_priv
->mem_freq
= 533;
556 dev_priv
->mem_freq
= 667;
559 dev_priv
->mem_freq
= 800;
563 /* detect pineview DDR3 setting */
564 tmp
= I915_READ(CSHRDDR3CTL
);
565 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
568 static void i915_ironlake_get_mem_freq(struct drm_device
*dev
)
570 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
573 ddrpll
= I915_READ16(DDRMPLL1
);
574 csipll
= I915_READ16(CSIPLL0
);
576 switch (ddrpll
& 0xff) {
578 dev_priv
->mem_freq
= 800;
581 dev_priv
->mem_freq
= 1066;
584 dev_priv
->mem_freq
= 1333;
587 dev_priv
->mem_freq
= 1600;
590 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
592 dev_priv
->mem_freq
= 0;
596 dev_priv
->r_t
= dev_priv
->mem_freq
;
598 switch (csipll
& 0x3ff) {
600 dev_priv
->fsb_freq
= 3200;
603 dev_priv
->fsb_freq
= 3733;
606 dev_priv
->fsb_freq
= 4266;
609 dev_priv
->fsb_freq
= 4800;
612 dev_priv
->fsb_freq
= 5333;
615 dev_priv
->fsb_freq
= 5866;
618 dev_priv
->fsb_freq
= 6400;
621 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
623 dev_priv
->fsb_freq
= 0;
627 if (dev_priv
->fsb_freq
== 3200) {
629 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
636 static const struct cxsr_latency cxsr_latency_table
[] = {
637 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
638 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
639 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
640 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
641 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
643 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
644 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
645 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
646 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
647 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
649 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
650 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
651 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
652 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
653 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
655 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
656 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
657 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
658 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
659 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
661 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
662 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
663 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
664 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
665 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
667 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
668 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
669 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
670 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
671 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
674 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
679 const struct cxsr_latency
*latency
;
682 if (fsb
== 0 || mem
== 0)
685 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
686 latency
= &cxsr_latency_table
[i
];
687 if (is_desktop
== latency
->is_desktop
&&
688 is_ddr3
== latency
->is_ddr3
&&
689 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
693 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
698 static void pineview_disable_cxsr(struct drm_device
*dev
)
700 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
702 /* deactivate cxsr */
703 I915_WRITE(DSPFW3
, I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
);
707 * Latency for FIFO fetches is dependent on several factors:
708 * - memory configuration (speed, channels)
710 * - current MCH state
711 * It can be fairly high in some situations, so here we assume a fairly
712 * pessimal value. It's a tradeoff between extra memory fetches (if we
713 * set this value too high, the FIFO will fetch frequently to stay full)
714 * and power consumption (set it too low to save power and we might see
715 * FIFO underruns and display "flicker").
717 * A value of 5us seems to be a good balance; safe for very low end
718 * platforms but not overly aggressive on lower latency configs.
720 static const int latency_ns
= 5000;
722 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
725 uint32_t dsparb
= I915_READ(DSPARB
);
728 size
= dsparb
& 0x7f;
730 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
732 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
733 plane
? "B" : "A", size
);
738 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
741 uint32_t dsparb
= I915_READ(DSPARB
);
744 size
= dsparb
& 0x1ff;
746 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
747 size
>>= 1; /* Convert to cachelines */
749 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
750 plane
? "B" : "A", size
);
755 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
757 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
758 uint32_t dsparb
= I915_READ(DSPARB
);
761 size
= dsparb
& 0x7f;
762 size
>>= 2; /* Convert to cachelines */
764 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
771 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
773 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
774 uint32_t dsparb
= I915_READ(DSPARB
);
777 size
= dsparb
& 0x7f;
778 size
>>= 1; /* Convert to cachelines */
780 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
781 plane
? "B" : "A", size
);
786 /* Pineview has different values for various configs */
787 static const struct intel_watermark_params pineview_display_wm
= {
788 PINEVIEW_DISPLAY_FIFO
,
792 PINEVIEW_FIFO_LINE_SIZE
794 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
795 PINEVIEW_DISPLAY_FIFO
,
797 PINEVIEW_DFT_HPLLOFF_WM
,
799 PINEVIEW_FIFO_LINE_SIZE
801 static const struct intel_watermark_params pineview_cursor_wm
= {
802 PINEVIEW_CURSOR_FIFO
,
803 PINEVIEW_CURSOR_MAX_WM
,
804 PINEVIEW_CURSOR_DFT_WM
,
805 PINEVIEW_CURSOR_GUARD_WM
,
806 PINEVIEW_FIFO_LINE_SIZE
,
808 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
809 PINEVIEW_CURSOR_FIFO
,
810 PINEVIEW_CURSOR_MAX_WM
,
811 PINEVIEW_CURSOR_DFT_WM
,
812 PINEVIEW_CURSOR_GUARD_WM
,
813 PINEVIEW_FIFO_LINE_SIZE
815 static const struct intel_watermark_params g4x_wm_info
= {
822 static const struct intel_watermark_params g4x_cursor_wm_info
= {
829 static const struct intel_watermark_params valleyview_wm_info
= {
830 VALLEYVIEW_FIFO_SIZE
,
836 static const struct intel_watermark_params valleyview_cursor_wm_info
= {
838 VALLEYVIEW_CURSOR_MAX_WM
,
843 static const struct intel_watermark_params i965_cursor_wm_info
= {
850 static const struct intel_watermark_params i945_wm_info
= {
857 static const struct intel_watermark_params i915_wm_info
= {
864 static const struct intel_watermark_params i855_wm_info
= {
871 static const struct intel_watermark_params i830_wm_info
= {
879 static const struct intel_watermark_params ironlake_display_wm_info
= {
886 static const struct intel_watermark_params ironlake_cursor_wm_info
= {
893 static const struct intel_watermark_params ironlake_display_srwm_info
= {
895 ILK_DISPLAY_MAX_SRWM
,
896 ILK_DISPLAY_DFT_SRWM
,
900 static const struct intel_watermark_params ironlake_cursor_srwm_info
= {
908 static const struct intel_watermark_params sandybridge_display_wm_info
= {
915 static const struct intel_watermark_params sandybridge_cursor_wm_info
= {
922 static const struct intel_watermark_params sandybridge_display_srwm_info
= {
924 SNB_DISPLAY_MAX_SRWM
,
925 SNB_DISPLAY_DFT_SRWM
,
929 static const struct intel_watermark_params sandybridge_cursor_srwm_info
= {
939 * intel_calculate_wm - calculate watermark level
940 * @clock_in_khz: pixel clock
941 * @wm: chip FIFO params
942 * @pixel_size: display pixel size
943 * @latency_ns: memory latency for the platform
945 * Calculate the watermark level (the level at which the display plane will
946 * start fetching from memory again). Each chip has a different display
947 * FIFO size and allocation, so the caller needs to figure that out and pass
948 * in the correct intel_watermark_params structure.
950 * As the pixel clock runs, the FIFO will be drained at a rate that depends
951 * on the pixel size. When it reaches the watermark level, it'll start
952 * fetching FIFO line sized based chunks from memory until the FIFO fills
953 * past the watermark point. If the FIFO drains completely, a FIFO underrun
954 * will occur, and a display engine hang could result.
956 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
957 const struct intel_watermark_params
*wm
,
960 unsigned long latency_ns
)
962 long entries_required
, wm_size
;
965 * Note: we need to make sure we don't overflow for various clock &
967 * clocks go from a few thousand to several hundred thousand.
968 * latency is usually a few thousand
970 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
972 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
974 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
976 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
978 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
980 /* Don't promote wm_size to unsigned... */
981 if (wm_size
> (long)wm
->max_wm
)
982 wm_size
= wm
->max_wm
;
984 wm_size
= wm
->default_wm
;
988 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
990 struct drm_crtc
*crtc
, *enabled
= NULL
;
992 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
993 if (crtc
->enabled
&& crtc
->fb
) {
1003 static void pineview_update_wm(struct drm_device
*dev
)
1005 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1006 struct drm_crtc
*crtc
;
1007 const struct cxsr_latency
*latency
;
1011 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
1012 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
1014 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1015 pineview_disable_cxsr(dev
);
1019 crtc
= single_enabled_crtc(dev
);
1021 int clock
= crtc
->mode
.clock
;
1022 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1025 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
1026 pineview_display_wm
.fifo_size
,
1027 pixel_size
, latency
->display_sr
);
1028 reg
= I915_READ(DSPFW1
);
1029 reg
&= ~DSPFW_SR_MASK
;
1030 reg
|= wm
<< DSPFW_SR_SHIFT
;
1031 I915_WRITE(DSPFW1
, reg
);
1032 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
1035 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
1036 pineview_display_wm
.fifo_size
,
1037 pixel_size
, latency
->cursor_sr
);
1038 reg
= I915_READ(DSPFW3
);
1039 reg
&= ~DSPFW_CURSOR_SR_MASK
;
1040 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
1041 I915_WRITE(DSPFW3
, reg
);
1043 /* Display HPLL off SR */
1044 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
1045 pineview_display_hplloff_wm
.fifo_size
,
1046 pixel_size
, latency
->display_hpll_disable
);
1047 reg
= I915_READ(DSPFW3
);
1048 reg
&= ~DSPFW_HPLL_SR_MASK
;
1049 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
1050 I915_WRITE(DSPFW3
, reg
);
1052 /* cursor HPLL off SR */
1053 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
1054 pineview_display_hplloff_wm
.fifo_size
,
1055 pixel_size
, latency
->cursor_hpll_disable
);
1056 reg
= I915_READ(DSPFW3
);
1057 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
1058 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
1059 I915_WRITE(DSPFW3
, reg
);
1060 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
1064 I915_READ(DSPFW3
) | PINEVIEW_SELF_REFRESH_EN
);
1065 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1067 pineview_disable_cxsr(dev
);
1068 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1072 static bool g4x_compute_wm0(struct drm_device
*dev
,
1074 const struct intel_watermark_params
*display
,
1075 int display_latency_ns
,
1076 const struct intel_watermark_params
*cursor
,
1077 int cursor_latency_ns
,
1081 struct drm_crtc
*crtc
;
1082 int htotal
, hdisplay
, clock
, pixel_size
;
1083 int line_time_us
, line_count
;
1084 int entries
, tlb_miss
;
1086 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1087 if (crtc
->fb
== NULL
|| !crtc
->enabled
) {
1088 *cursor_wm
= cursor
->guard_size
;
1089 *plane_wm
= display
->guard_size
;
1093 htotal
= crtc
->mode
.htotal
;
1094 hdisplay
= crtc
->mode
.hdisplay
;
1095 clock
= crtc
->mode
.clock
;
1096 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1098 /* Use the small buffer method to calculate plane watermark */
1099 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
1100 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
1102 entries
+= tlb_miss
;
1103 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
1104 *plane_wm
= entries
+ display
->guard_size
;
1105 if (*plane_wm
> (int)display
->max_wm
)
1106 *plane_wm
= display
->max_wm
;
1108 /* Use the large buffer method to calculate cursor watermark */
1109 line_time_us
= ((htotal
* 1000) / clock
);
1110 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
1111 entries
= line_count
* 64 * pixel_size
;
1112 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
1114 entries
+= tlb_miss
;
1115 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1116 *cursor_wm
= entries
+ cursor
->guard_size
;
1117 if (*cursor_wm
> (int)cursor
->max_wm
)
1118 *cursor_wm
= (int)cursor
->max_wm
;
1124 * Check the wm result.
1126 * If any calculated watermark values is larger than the maximum value that
1127 * can be programmed into the associated watermark register, that watermark
1130 static bool g4x_check_srwm(struct drm_device
*dev
,
1131 int display_wm
, int cursor_wm
,
1132 const struct intel_watermark_params
*display
,
1133 const struct intel_watermark_params
*cursor
)
1135 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1136 display_wm
, cursor_wm
);
1138 if (display_wm
> display
->max_wm
) {
1139 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1140 display_wm
, display
->max_wm
);
1144 if (cursor_wm
> cursor
->max_wm
) {
1145 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1146 cursor_wm
, cursor
->max_wm
);
1150 if (!(display_wm
|| cursor_wm
)) {
1151 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1158 static bool g4x_compute_srwm(struct drm_device
*dev
,
1161 const struct intel_watermark_params
*display
,
1162 const struct intel_watermark_params
*cursor
,
1163 int *display_wm
, int *cursor_wm
)
1165 struct drm_crtc
*crtc
;
1166 int hdisplay
, htotal
, pixel_size
, clock
;
1167 unsigned long line_time_us
;
1168 int line_count
, line_size
;
1173 *display_wm
= *cursor_wm
= 0;
1177 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1178 hdisplay
= crtc
->mode
.hdisplay
;
1179 htotal
= crtc
->mode
.htotal
;
1180 clock
= crtc
->mode
.clock
;
1181 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1183 line_time_us
= (htotal
* 1000) / clock
;
1184 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
1185 line_size
= hdisplay
* pixel_size
;
1187 /* Use the minimum of the small and large buffer method for primary */
1188 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
1189 large
= line_count
* line_size
;
1191 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
1192 *display_wm
= entries
+ display
->guard_size
;
1194 /* calculate the self-refresh watermark for display cursor */
1195 entries
= line_count
* pixel_size
* 64;
1196 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1197 *cursor_wm
= entries
+ cursor
->guard_size
;
1199 return g4x_check_srwm(dev
,
1200 *display_wm
, *cursor_wm
,
1204 static bool vlv_compute_drain_latency(struct drm_device
*dev
,
1206 int *plane_prec_mult
,
1208 int *cursor_prec_mult
,
1211 struct drm_crtc
*crtc
;
1212 int clock
, pixel_size
;
1215 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1216 if (crtc
->fb
== NULL
|| !crtc
->enabled
)
1219 clock
= crtc
->mode
.clock
; /* VESA DOT Clock */
1220 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8; /* BPP */
1222 entries
= (clock
/ 1000) * pixel_size
;
1223 *plane_prec_mult
= (entries
> 256) ?
1224 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_16
;
1225 *plane_dl
= (64 * (*plane_prec_mult
) * 4) / ((clock
/ 1000) *
1228 entries
= (clock
/ 1000) * 4; /* BPP is always 4 for cursor */
1229 *cursor_prec_mult
= (entries
> 256) ?
1230 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_16
;
1231 *cursor_dl
= (64 * (*cursor_prec_mult
) * 4) / ((clock
/ 1000) * 4);
1237 * Update drain latency registers of memory arbiter
1239 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1240 * to be programmed. Each plane has a drain latency multiplier and a drain
1244 static void vlv_update_drain_latency(struct drm_device
*dev
)
1246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1247 int planea_prec
, planea_dl
, planeb_prec
, planeb_dl
;
1248 int cursora_prec
, cursora_dl
, cursorb_prec
, cursorb_dl
;
1249 int plane_prec_mult
, cursor_prec_mult
; /* Precision multiplier is
1252 /* For plane A, Cursor A */
1253 if (vlv_compute_drain_latency(dev
, 0, &plane_prec_mult
, &planea_dl
,
1254 &cursor_prec_mult
, &cursora_dl
)) {
1255 cursora_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1256 DDL_CURSORA_PRECISION_32
: DDL_CURSORA_PRECISION_16
;
1257 planea_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1258 DDL_PLANEA_PRECISION_32
: DDL_PLANEA_PRECISION_16
;
1260 I915_WRITE(VLV_DDL1
, cursora_prec
|
1261 (cursora_dl
<< DDL_CURSORA_SHIFT
) |
1262 planea_prec
| planea_dl
);
1265 /* For plane B, Cursor B */
1266 if (vlv_compute_drain_latency(dev
, 1, &plane_prec_mult
, &planeb_dl
,
1267 &cursor_prec_mult
, &cursorb_dl
)) {
1268 cursorb_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1269 DDL_CURSORB_PRECISION_32
: DDL_CURSORB_PRECISION_16
;
1270 planeb_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1271 DDL_PLANEB_PRECISION_32
: DDL_PLANEB_PRECISION_16
;
1273 I915_WRITE(VLV_DDL2
, cursorb_prec
|
1274 (cursorb_dl
<< DDL_CURSORB_SHIFT
) |
1275 planeb_prec
| planeb_dl
);
1279 #define single_plane_enabled(mask) is_power_of_2(mask)
1281 static void valleyview_update_wm(struct drm_device
*dev
)
1283 static const int sr_latency_ns
= 12000;
1284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1285 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1286 int plane_sr
, cursor_sr
;
1287 unsigned int enabled
= 0;
1289 vlv_update_drain_latency(dev
);
1291 if (g4x_compute_wm0(dev
, 0,
1292 &valleyview_wm_info
, latency_ns
,
1293 &valleyview_cursor_wm_info
, latency_ns
,
1294 &planea_wm
, &cursora_wm
))
1297 if (g4x_compute_wm0(dev
, 1,
1298 &valleyview_wm_info
, latency_ns
,
1299 &valleyview_cursor_wm_info
, latency_ns
,
1300 &planeb_wm
, &cursorb_wm
))
1303 plane_sr
= cursor_sr
= 0;
1304 if (single_plane_enabled(enabled
) &&
1305 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1307 &valleyview_wm_info
,
1308 &valleyview_cursor_wm_info
,
1309 &plane_sr
, &cursor_sr
))
1310 I915_WRITE(FW_BLC_SELF_VLV
, FW_CSPWRDWNEN
);
1312 I915_WRITE(FW_BLC_SELF_VLV
,
1313 I915_READ(FW_BLC_SELF_VLV
) & ~FW_CSPWRDWNEN
);
1315 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1316 planea_wm
, cursora_wm
,
1317 planeb_wm
, cursorb_wm
,
1318 plane_sr
, cursor_sr
);
1321 (plane_sr
<< DSPFW_SR_SHIFT
) |
1322 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1323 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1326 (I915_READ(DSPFW2
) & DSPFW_CURSORA_MASK
) |
1327 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1329 (I915_READ(DSPFW3
) | (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
)));
1332 static void g4x_update_wm(struct drm_device
*dev
)
1334 static const int sr_latency_ns
= 12000;
1335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1336 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1337 int plane_sr
, cursor_sr
;
1338 unsigned int enabled
= 0;
1340 if (g4x_compute_wm0(dev
, 0,
1341 &g4x_wm_info
, latency_ns
,
1342 &g4x_cursor_wm_info
, latency_ns
,
1343 &planea_wm
, &cursora_wm
))
1346 if (g4x_compute_wm0(dev
, 1,
1347 &g4x_wm_info
, latency_ns
,
1348 &g4x_cursor_wm_info
, latency_ns
,
1349 &planeb_wm
, &cursorb_wm
))
1352 plane_sr
= cursor_sr
= 0;
1353 if (single_plane_enabled(enabled
) &&
1354 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1357 &g4x_cursor_wm_info
,
1358 &plane_sr
, &cursor_sr
))
1359 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
1361 I915_WRITE(FW_BLC_SELF
,
1362 I915_READ(FW_BLC_SELF
) & ~FW_BLC_SELF_EN
);
1364 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1365 planea_wm
, cursora_wm
,
1366 planeb_wm
, cursorb_wm
,
1367 plane_sr
, cursor_sr
);
1370 (plane_sr
<< DSPFW_SR_SHIFT
) |
1371 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1372 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1375 (I915_READ(DSPFW2
) & DSPFW_CURSORA_MASK
) |
1376 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1377 /* HPLL off in SR has some issues on G4x... disable it */
1379 (I915_READ(DSPFW3
) & ~DSPFW_HPLL_SR_EN
) |
1380 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1383 static void i965_update_wm(struct drm_device
*dev
)
1385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1386 struct drm_crtc
*crtc
;
1390 /* Calc sr entries for one plane configs */
1391 crtc
= single_enabled_crtc(dev
);
1393 /* self-refresh has much higher latency */
1394 static const int sr_latency_ns
= 12000;
1395 int clock
= crtc
->mode
.clock
;
1396 int htotal
= crtc
->mode
.htotal
;
1397 int hdisplay
= crtc
->mode
.hdisplay
;
1398 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1399 unsigned long line_time_us
;
1402 line_time_us
= ((htotal
* 1000) / clock
);
1404 /* Use ns/us then divide to preserve precision */
1405 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1406 pixel_size
* hdisplay
;
1407 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1408 srwm
= I965_FIFO_SIZE
- entries
;
1412 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1415 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1417 entries
= DIV_ROUND_UP(entries
,
1418 i965_cursor_wm_info
.cacheline_size
);
1419 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1420 (entries
+ i965_cursor_wm_info
.guard_size
);
1422 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1423 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1425 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1426 "cursor %d\n", srwm
, cursor_sr
);
1428 if (IS_CRESTLINE(dev
))
1429 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
1431 /* Turn off self refresh if both pipes are enabled */
1432 if (IS_CRESTLINE(dev
))
1433 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
1437 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1440 /* 965 has limitations... */
1441 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) |
1442 (8 << 16) | (8 << 8) | (8 << 0));
1443 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
1444 /* update cursor SR watermark */
1445 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1448 static void i9xx_update_wm(struct drm_device
*dev
)
1450 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1451 const struct intel_watermark_params
*wm_info
;
1456 int planea_wm
, planeb_wm
;
1457 struct drm_crtc
*crtc
, *enabled
= NULL
;
1460 wm_info
= &i945_wm_info
;
1461 else if (!IS_GEN2(dev
))
1462 wm_info
= &i915_wm_info
;
1464 wm_info
= &i855_wm_info
;
1466 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
1467 crtc
= intel_get_crtc_for_plane(dev
, 0);
1468 if (crtc
->enabled
&& crtc
->fb
) {
1469 planea_wm
= intel_calculate_wm(crtc
->mode
.clock
,
1471 crtc
->fb
->bits_per_pixel
/ 8,
1475 planea_wm
= fifo_size
- wm_info
->guard_size
;
1477 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
1478 crtc
= intel_get_crtc_for_plane(dev
, 1);
1479 if (crtc
->enabled
&& crtc
->fb
) {
1480 planeb_wm
= intel_calculate_wm(crtc
->mode
.clock
,
1482 crtc
->fb
->bits_per_pixel
/ 8,
1484 if (enabled
== NULL
)
1489 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1491 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1494 * Overlay gets an aggressive default since video jitter is bad.
1498 /* Play safe and disable self-refresh before adjusting watermarks. */
1499 if (IS_I945G(dev
) || IS_I945GM(dev
))
1500 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
| 0);
1501 else if (IS_I915GM(dev
))
1502 I915_WRITE(INSTPM
, I915_READ(INSTPM
) & ~INSTPM_SELF_EN
);
1504 /* Calc sr entries for one plane configs */
1505 if (HAS_FW_BLC(dev
) && enabled
) {
1506 /* self-refresh has much higher latency */
1507 static const int sr_latency_ns
= 6000;
1508 int clock
= enabled
->mode
.clock
;
1509 int htotal
= enabled
->mode
.htotal
;
1510 int hdisplay
= enabled
->mode
.hdisplay
;
1511 int pixel_size
= enabled
->fb
->bits_per_pixel
/ 8;
1512 unsigned long line_time_us
;
1515 line_time_us
= (htotal
* 1000) / clock
;
1517 /* Use ns/us then divide to preserve precision */
1518 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1519 pixel_size
* hdisplay
;
1520 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1521 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1522 srwm
= wm_info
->fifo_size
- entries
;
1526 if (IS_I945G(dev
) || IS_I945GM(dev
))
1527 I915_WRITE(FW_BLC_SELF
,
1528 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1529 else if (IS_I915GM(dev
))
1530 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1533 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1534 planea_wm
, planeb_wm
, cwm
, srwm
);
1536 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1537 fwater_hi
= (cwm
& 0x1f);
1539 /* Set request length to 8 cachelines per fetch */
1540 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1541 fwater_hi
= fwater_hi
| (1 << 8);
1543 I915_WRITE(FW_BLC
, fwater_lo
);
1544 I915_WRITE(FW_BLC2
, fwater_hi
);
1546 if (HAS_FW_BLC(dev
)) {
1548 if (IS_I945G(dev
) || IS_I945GM(dev
))
1549 I915_WRITE(FW_BLC_SELF
,
1550 FW_BLC_SELF_EN_MASK
| FW_BLC_SELF_EN
);
1551 else if (IS_I915GM(dev
))
1552 I915_WRITE(INSTPM
, I915_READ(INSTPM
) | INSTPM_SELF_EN
);
1553 DRM_DEBUG_KMS("memory self refresh enabled\n");
1555 DRM_DEBUG_KMS("memory self refresh disabled\n");
1559 static void i830_update_wm(struct drm_device
*dev
)
1561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1562 struct drm_crtc
*crtc
;
1566 crtc
= single_enabled_crtc(dev
);
1570 planea_wm
= intel_calculate_wm(crtc
->mode
.clock
, &i830_wm_info
,
1571 dev_priv
->display
.get_fifo_size(dev
, 0),
1572 crtc
->fb
->bits_per_pixel
/ 8,
1574 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1575 fwater_lo
|= (3<<8) | planea_wm
;
1577 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1579 I915_WRITE(FW_BLC
, fwater_lo
);
1582 #define ILK_LP0_PLANE_LATENCY 700
1583 #define ILK_LP0_CURSOR_LATENCY 1300
1586 * Check the wm result.
1588 * If any calculated watermark values is larger than the maximum value that
1589 * can be programmed into the associated watermark register, that watermark
1592 static bool ironlake_check_srwm(struct drm_device
*dev
, int level
,
1593 int fbc_wm
, int display_wm
, int cursor_wm
,
1594 const struct intel_watermark_params
*display
,
1595 const struct intel_watermark_params
*cursor
)
1597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1599 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1600 " cursor %d\n", level
, display_wm
, fbc_wm
, cursor_wm
);
1602 if (fbc_wm
> SNB_FBC_MAX_SRWM
) {
1603 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1604 fbc_wm
, SNB_FBC_MAX_SRWM
, level
);
1606 /* fbc has it's own way to disable FBC WM */
1607 I915_WRITE(DISP_ARB_CTL
,
1608 I915_READ(DISP_ARB_CTL
) | DISP_FBC_WM_DIS
);
1612 if (display_wm
> display
->max_wm
) {
1613 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1614 display_wm
, SNB_DISPLAY_MAX_SRWM
, level
);
1618 if (cursor_wm
> cursor
->max_wm
) {
1619 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1620 cursor_wm
, SNB_CURSOR_MAX_SRWM
, level
);
1624 if (!(fbc_wm
|| display_wm
|| cursor_wm
)) {
1625 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level
, level
);
1633 * Compute watermark values of WM[1-3],
1635 static bool ironlake_compute_srwm(struct drm_device
*dev
, int level
, int plane
,
1637 const struct intel_watermark_params
*display
,
1638 const struct intel_watermark_params
*cursor
,
1639 int *fbc_wm
, int *display_wm
, int *cursor_wm
)
1641 struct drm_crtc
*crtc
;
1642 unsigned long line_time_us
;
1643 int hdisplay
, htotal
, pixel_size
, clock
;
1644 int line_count
, line_size
;
1649 *fbc_wm
= *display_wm
= *cursor_wm
= 0;
1653 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1654 hdisplay
= crtc
->mode
.hdisplay
;
1655 htotal
= crtc
->mode
.htotal
;
1656 clock
= crtc
->mode
.clock
;
1657 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
1659 line_time_us
= (htotal
* 1000) / clock
;
1660 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
1661 line_size
= hdisplay
* pixel_size
;
1663 /* Use the minimum of the small and large buffer method for primary */
1664 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
1665 large
= line_count
* line_size
;
1667 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
1668 *display_wm
= entries
+ display
->guard_size
;
1672 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1674 *fbc_wm
= DIV_ROUND_UP(*display_wm
* 64, line_size
) + 2;
1676 /* calculate the self-refresh watermark for display cursor */
1677 entries
= line_count
* pixel_size
* 64;
1678 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1679 *cursor_wm
= entries
+ cursor
->guard_size
;
1681 return ironlake_check_srwm(dev
, level
,
1682 *fbc_wm
, *display_wm
, *cursor_wm
,
1686 static void ironlake_update_wm(struct drm_device
*dev
)
1688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1689 int fbc_wm
, plane_wm
, cursor_wm
;
1690 unsigned int enabled
;
1693 if (g4x_compute_wm0(dev
, 0,
1694 &ironlake_display_wm_info
,
1695 ILK_LP0_PLANE_LATENCY
,
1696 &ironlake_cursor_wm_info
,
1697 ILK_LP0_CURSOR_LATENCY
,
1698 &plane_wm
, &cursor_wm
)) {
1699 I915_WRITE(WM0_PIPEA_ILK
,
1700 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
1701 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1702 " plane %d, " "cursor: %d\n",
1703 plane_wm
, cursor_wm
);
1707 if (g4x_compute_wm0(dev
, 1,
1708 &ironlake_display_wm_info
,
1709 ILK_LP0_PLANE_LATENCY
,
1710 &ironlake_cursor_wm_info
,
1711 ILK_LP0_CURSOR_LATENCY
,
1712 &plane_wm
, &cursor_wm
)) {
1713 I915_WRITE(WM0_PIPEB_ILK
,
1714 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
1715 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1716 " plane %d, cursor: %d\n",
1717 plane_wm
, cursor_wm
);
1722 * Calculate and update the self-refresh watermark only when one
1723 * display plane is used.
1725 I915_WRITE(WM3_LP_ILK
, 0);
1726 I915_WRITE(WM2_LP_ILK
, 0);
1727 I915_WRITE(WM1_LP_ILK
, 0);
1729 if (!single_plane_enabled(enabled
))
1731 enabled
= ffs(enabled
) - 1;
1734 if (!ironlake_compute_srwm(dev
, 1, enabled
,
1735 ILK_READ_WM1_LATENCY() * 500,
1736 &ironlake_display_srwm_info
,
1737 &ironlake_cursor_srwm_info
,
1738 &fbc_wm
, &plane_wm
, &cursor_wm
))
1741 I915_WRITE(WM1_LP_ILK
,
1743 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1744 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1745 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1749 if (!ironlake_compute_srwm(dev
, 2, enabled
,
1750 ILK_READ_WM2_LATENCY() * 500,
1751 &ironlake_display_srwm_info
,
1752 &ironlake_cursor_srwm_info
,
1753 &fbc_wm
, &plane_wm
, &cursor_wm
))
1756 I915_WRITE(WM2_LP_ILK
,
1758 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1759 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1760 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1764 * WM3 is unsupported on ILK, probably because we don't have latency
1765 * data for that power state
1769 static void sandybridge_update_wm(struct drm_device
*dev
)
1771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1772 int latency
= SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1774 int fbc_wm
, plane_wm
, cursor_wm
;
1775 unsigned int enabled
;
1778 if (g4x_compute_wm0(dev
, 0,
1779 &sandybridge_display_wm_info
, latency
,
1780 &sandybridge_cursor_wm_info
, latency
,
1781 &plane_wm
, &cursor_wm
)) {
1782 val
= I915_READ(WM0_PIPEA_ILK
);
1783 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1784 I915_WRITE(WM0_PIPEA_ILK
, val
|
1785 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1786 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1787 " plane %d, " "cursor: %d\n",
1788 plane_wm
, cursor_wm
);
1792 if (g4x_compute_wm0(dev
, 1,
1793 &sandybridge_display_wm_info
, latency
,
1794 &sandybridge_cursor_wm_info
, latency
,
1795 &plane_wm
, &cursor_wm
)) {
1796 val
= I915_READ(WM0_PIPEB_ILK
);
1797 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1798 I915_WRITE(WM0_PIPEB_ILK
, val
|
1799 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1800 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1801 " plane %d, cursor: %d\n",
1802 plane_wm
, cursor_wm
);
1806 if ((dev_priv
->num_pipe
== 3) &&
1807 g4x_compute_wm0(dev
, 2,
1808 &sandybridge_display_wm_info
, latency
,
1809 &sandybridge_cursor_wm_info
, latency
,
1810 &plane_wm
, &cursor_wm
)) {
1811 val
= I915_READ(WM0_PIPEC_IVB
);
1812 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
1813 I915_WRITE(WM0_PIPEC_IVB
, val
|
1814 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
1815 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1816 " plane %d, cursor: %d\n",
1817 plane_wm
, cursor_wm
);
1822 * Calculate and update the self-refresh watermark only when one
1823 * display plane is used.
1825 * SNB support 3 levels of watermark.
1827 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1828 * and disabled in the descending order
1831 I915_WRITE(WM3_LP_ILK
, 0);
1832 I915_WRITE(WM2_LP_ILK
, 0);
1833 I915_WRITE(WM1_LP_ILK
, 0);
1835 if (!single_plane_enabled(enabled
) ||
1836 dev_priv
->sprite_scaling_enabled
)
1838 enabled
= ffs(enabled
) - 1;
1841 if (!ironlake_compute_srwm(dev
, 1, enabled
,
1842 SNB_READ_WM1_LATENCY() * 500,
1843 &sandybridge_display_srwm_info
,
1844 &sandybridge_cursor_srwm_info
,
1845 &fbc_wm
, &plane_wm
, &cursor_wm
))
1848 I915_WRITE(WM1_LP_ILK
,
1850 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1851 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1852 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1856 if (!ironlake_compute_srwm(dev
, 2, enabled
,
1857 SNB_READ_WM2_LATENCY() * 500,
1858 &sandybridge_display_srwm_info
,
1859 &sandybridge_cursor_srwm_info
,
1860 &fbc_wm
, &plane_wm
, &cursor_wm
))
1863 I915_WRITE(WM2_LP_ILK
,
1865 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1866 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1867 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1871 if (!ironlake_compute_srwm(dev
, 3, enabled
,
1872 SNB_READ_WM3_LATENCY() * 500,
1873 &sandybridge_display_srwm_info
,
1874 &sandybridge_cursor_srwm_info
,
1875 &fbc_wm
, &plane_wm
, &cursor_wm
))
1878 I915_WRITE(WM3_LP_ILK
,
1880 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
1881 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
1882 (plane_wm
<< WM1_LP_SR_SHIFT
) |
1887 haswell_update_linetime_wm(struct drm_device
*dev
, int pipe
,
1888 struct drm_display_mode
*mode
)
1890 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1893 temp
= I915_READ(PIPE_WM_LINETIME(pipe
));
1894 temp
&= ~PIPE_WM_LINETIME_MASK
;
1896 /* The WM are computed with base on how long it takes to fill a single
1897 * row at the given clock rate, multiplied by 8.
1899 temp
|= PIPE_WM_LINETIME_TIME(
1900 ((mode
->crtc_hdisplay
* 1000) / mode
->clock
) * 8);
1902 /* IPS watermarks are only used by pipe A, and are ignored by
1903 * pipes B and C. They are calculated similarly to the common
1904 * linetime values, except that we are using CD clock frequency
1905 * in MHz instead of pixel rate for the division.
1907 * This is a placeholder for the IPS watermark calculation code.
1910 I915_WRITE(PIPE_WM_LINETIME(pipe
), temp
);
1914 sandybridge_compute_sprite_wm(struct drm_device
*dev
, int plane
,
1915 uint32_t sprite_width
, int pixel_size
,
1916 const struct intel_watermark_params
*display
,
1917 int display_latency_ns
, int *sprite_wm
)
1919 struct drm_crtc
*crtc
;
1921 int entries
, tlb_miss
;
1923 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1924 if (crtc
->fb
== NULL
|| !crtc
->enabled
) {
1925 *sprite_wm
= display
->guard_size
;
1929 clock
= crtc
->mode
.clock
;
1931 /* Use the small buffer method to calculate the sprite watermark */
1932 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
1933 tlb_miss
= display
->fifo_size
*display
->cacheline_size
-
1936 entries
+= tlb_miss
;
1937 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
1938 *sprite_wm
= entries
+ display
->guard_size
;
1939 if (*sprite_wm
> (int)display
->max_wm
)
1940 *sprite_wm
= display
->max_wm
;
1946 sandybridge_compute_sprite_srwm(struct drm_device
*dev
, int plane
,
1947 uint32_t sprite_width
, int pixel_size
,
1948 const struct intel_watermark_params
*display
,
1949 int latency_ns
, int *sprite_wm
)
1951 struct drm_crtc
*crtc
;
1952 unsigned long line_time_us
;
1954 int line_count
, line_size
;
1963 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1964 clock
= crtc
->mode
.clock
;
1970 line_time_us
= (sprite_width
* 1000) / clock
;
1971 if (!line_time_us
) {
1976 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
1977 line_size
= sprite_width
* pixel_size
;
1979 /* Use the minimum of the small and large buffer method for primary */
1980 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
1981 large
= line_count
* line_size
;
1983 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
1984 *sprite_wm
= entries
+ display
->guard_size
;
1986 return *sprite_wm
> 0x3ff ? false : true;
1989 static void sandybridge_update_sprite_wm(struct drm_device
*dev
, int pipe
,
1990 uint32_t sprite_width
, int pixel_size
)
1992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1993 int latency
= SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2000 reg
= WM0_PIPEA_ILK
;
2003 reg
= WM0_PIPEB_ILK
;
2006 reg
= WM0_PIPEC_IVB
;
2009 return; /* bad pipe */
2012 ret
= sandybridge_compute_sprite_wm(dev
, pipe
, sprite_width
, pixel_size
,
2013 &sandybridge_display_wm_info
,
2014 latency
, &sprite_wm
);
2016 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
2021 val
= I915_READ(reg
);
2022 val
&= ~WM0_PIPE_SPRITE_MASK
;
2023 I915_WRITE(reg
, val
| (sprite_wm
<< WM0_PIPE_SPRITE_SHIFT
));
2024 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe
, sprite_wm
);
2027 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
2029 &sandybridge_display_srwm_info
,
2030 SNB_READ_WM1_LATENCY() * 500,
2033 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
2037 I915_WRITE(WM1S_LP_ILK
, sprite_wm
);
2039 /* Only IVB has two more LP watermarks for sprite */
2040 if (!IS_IVYBRIDGE(dev
))
2043 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
2045 &sandybridge_display_srwm_info
,
2046 SNB_READ_WM2_LATENCY() * 500,
2049 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
2053 I915_WRITE(WM2S_LP_IVB
, sprite_wm
);
2055 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
2057 &sandybridge_display_srwm_info
,
2058 SNB_READ_WM3_LATENCY() * 500,
2061 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
2065 I915_WRITE(WM3S_LP_IVB
, sprite_wm
);
2069 * intel_update_watermarks - update FIFO watermark values based on current modes
2071 * Calculate watermark values for the various WM regs based on current mode
2072 * and plane configuration.
2074 * There are several cases to deal with here:
2075 * - normal (i.e. non-self-refresh)
2076 * - self-refresh (SR) mode
2077 * - lines are large relative to FIFO size (buffer can hold up to 2)
2078 * - lines are small relative to FIFO size (buffer can hold more than 2
2079 * lines), so need to account for TLB latency
2081 * The normal calculation is:
2082 * watermark = dotclock * bytes per pixel * latency
2083 * where latency is platform & configuration dependent (we assume pessimal
2086 * The SR calculation is:
2087 * watermark = (trunc(latency/line time)+1) * surface width *
2090 * line time = htotal / dotclock
2091 * surface width = hdisplay for normal plane and 64 for cursor
2092 * and latency is assumed to be high, as above.
2094 * The final value programmed to the register should always be rounded up,
2095 * and include an extra 2 entries to account for clock crossings.
2097 * We don't use the sprite, so we can ignore that. And on Crestline we have
2098 * to set the non-SR watermarks to 8.
2100 void intel_update_watermarks(struct drm_device
*dev
)
2102 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2104 if (dev_priv
->display
.update_wm
)
2105 dev_priv
->display
.update_wm(dev
);
2108 void intel_update_linetime_watermarks(struct drm_device
*dev
,
2109 int pipe
, struct drm_display_mode
*mode
)
2111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2113 if (dev_priv
->display
.update_linetime_wm
)
2114 dev_priv
->display
.update_linetime_wm(dev
, pipe
, mode
);
2117 void intel_update_sprite_watermarks(struct drm_device
*dev
, int pipe
,
2118 uint32_t sprite_width
, int pixel_size
)
2120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2122 if (dev_priv
->display
.update_sprite_wm
)
2123 dev_priv
->display
.update_sprite_wm(dev
, pipe
, sprite_width
,
2127 static struct drm_i915_gem_object
*
2128 intel_alloc_context_page(struct drm_device
*dev
)
2130 struct drm_i915_gem_object
*ctx
;
2133 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2135 ctx
= i915_gem_alloc_object(dev
, 4096);
2137 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2141 ret
= i915_gem_object_pin(ctx
, 4096, true);
2143 DRM_ERROR("failed to pin power context: %d\n", ret
);
2147 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
2149 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
2156 i915_gem_object_unpin(ctx
);
2158 drm_gem_object_unreference(&ctx
->base
);
2159 mutex_unlock(&dev
->struct_mutex
);
2164 * Lock protecting IPS related data structures
2166 * - dev_priv->max_delay
2167 * - dev_priv->min_delay
2169 * - dev_priv->gpu_busy
2170 * - dev_priv->gfx_power
2172 DEFINE_SPINLOCK(mchdev_lock
);
2174 /* Global for IPS driver to get at the current i915 device. Protected by
2176 static struct drm_i915_private
*i915_mch_dev
;
2178 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
2180 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2183 assert_spin_locked(&mchdev_lock
);
2185 rgvswctl
= I915_READ16(MEMSWCTL
);
2186 if (rgvswctl
& MEMCTL_CMD_STS
) {
2187 DRM_DEBUG("gpu busy, RCS change rejected\n");
2188 return false; /* still busy with another command */
2191 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
2192 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
2193 I915_WRITE16(MEMSWCTL
, rgvswctl
);
2194 POSTING_READ16(MEMSWCTL
);
2196 rgvswctl
|= MEMCTL_CMD_STS
;
2197 I915_WRITE16(MEMSWCTL
, rgvswctl
);
2202 static void ironlake_enable_drps(struct drm_device
*dev
)
2204 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2205 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
2206 u8 fmax
, fmin
, fstart
, vstart
;
2208 spin_lock_irq(&mchdev_lock
);
2210 /* Enable temp reporting */
2211 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
2212 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
2214 /* 100ms RC evaluation intervals */
2215 I915_WRITE(RCUPEI
, 100000);
2216 I915_WRITE(RCDNEI
, 100000);
2218 /* Set max/min thresholds to 90ms and 80ms respectively */
2219 I915_WRITE(RCBMAXAVG
, 90000);
2220 I915_WRITE(RCBMINAVG
, 80000);
2222 I915_WRITE(MEMIHYST
, 1);
2224 /* Set up min, max, and cur for interrupt handling */
2225 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
2226 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
2227 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
2228 MEMMODE_FSTART_SHIFT
;
2230 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
2233 dev_priv
->fmax
= fmax
; /* IPS callback will increase this */
2234 dev_priv
->fstart
= fstart
;
2236 dev_priv
->max_delay
= fstart
;
2237 dev_priv
->min_delay
= fmin
;
2238 dev_priv
->cur_delay
= fstart
;
2240 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2241 fmax
, fmin
, fstart
);
2243 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
2246 * Interrupts will be enabled in ironlake_irq_postinstall
2249 I915_WRITE(VIDSTART
, vstart
);
2250 POSTING_READ(VIDSTART
);
2252 rgvmodectl
|= MEMMODE_SWMODE_EN
;
2253 I915_WRITE(MEMMODECTL
, rgvmodectl
);
2255 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
2256 DRM_ERROR("stuck trying to change perf mode\n");
2259 ironlake_set_drps(dev
, fstart
);
2261 dev_priv
->last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
2263 dev_priv
->last_time1
= jiffies_to_msecs(jiffies
);
2264 dev_priv
->last_count2
= I915_READ(0x112f4);
2265 getrawmonotonic(&dev_priv
->last_time2
);
2267 spin_unlock_irq(&mchdev_lock
);
2270 static void ironlake_disable_drps(struct drm_device
*dev
)
2272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2275 spin_lock_irq(&mchdev_lock
);
2277 rgvswctl
= I915_READ16(MEMSWCTL
);
2279 /* Ack interrupts, disable EFC interrupt */
2280 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
2281 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
2282 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
2283 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
2284 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
2286 /* Go back to the starting frequency */
2287 ironlake_set_drps(dev
, dev_priv
->fstart
);
2289 rgvswctl
|= MEMCTL_CMD_STS
;
2290 I915_WRITE(MEMSWCTL
, rgvswctl
);
2293 spin_unlock_irq(&mchdev_lock
);
2296 /* There's a funny hw issue where the hw returns all 0 when reading from
2297 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2298 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2299 * all limits and the gpu stuck at whatever frequency it is at atm).
2301 static u32
gen6_rps_limits(struct drm_i915_private
*dev_priv
, u8
*val
)
2307 if (*val
>= dev_priv
->rps
.max_delay
)
2308 *val
= dev_priv
->rps
.max_delay
;
2309 limits
|= dev_priv
->rps
.max_delay
<< 24;
2311 /* Only set the down limit when we've reached the lowest level to avoid
2312 * getting more interrupts, otherwise leave this clear. This prevents a
2313 * race in the hw when coming out of rc6: There's a tiny window where
2314 * the hw runs at the minimal clock before selecting the desired
2315 * frequency, if the down threshold expires in that window we will not
2316 * receive a down interrupt. */
2317 if (*val
<= dev_priv
->rps
.min_delay
) {
2318 *val
= dev_priv
->rps
.min_delay
;
2319 limits
|= dev_priv
->rps
.min_delay
<< 16;
2325 void gen6_set_rps(struct drm_device
*dev
, u8 val
)
2327 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2328 u32 limits
= gen6_rps_limits(dev_priv
, &val
);
2330 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2332 if (val
== dev_priv
->rps
.cur_delay
)
2335 I915_WRITE(GEN6_RPNSWREQ
,
2336 GEN6_FREQUENCY(val
) |
2338 GEN6_AGGRESSIVE_TURBO
);
2340 /* Make sure we continue to get interrupts
2341 * until we hit the minimum or maximum frequencies.
2343 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, limits
);
2345 dev_priv
->rps
.cur_delay
= val
;
2348 static void gen6_disable_rps(struct drm_device
*dev
)
2350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2352 I915_WRITE(GEN6_RC_CONTROL
, 0);
2353 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
2354 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
2355 I915_WRITE(GEN6_PMIER
, 0);
2356 /* Complete PM interrupt masking here doesn't race with the rps work
2357 * item again unmasking PM interrupts because that is using a different
2358 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2359 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2361 spin_lock_irq(&dev_priv
->rps
.lock
);
2362 dev_priv
->rps
.pm_iir
= 0;
2363 spin_unlock_irq(&dev_priv
->rps
.lock
);
2365 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
2368 int intel_enable_rc6(const struct drm_device
*dev
)
2370 /* Respect the kernel parameter if it is set */
2371 if (i915_enable_rc6
>= 0)
2372 return i915_enable_rc6
;
2374 if (INTEL_INFO(dev
)->gen
== 5) {
2375 DRM_DEBUG_DRIVER("Ironlake: only RC6 available\n");
2376 return INTEL_RC6_ENABLE
;
2379 if (IS_HASWELL(dev
)) {
2380 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
2381 return INTEL_RC6_ENABLE
;
2384 /* snb/ivb have more than one rc6 state. */
2385 if (INTEL_INFO(dev
)->gen
== 6) {
2386 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2387 return INTEL_RC6_ENABLE
;
2390 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2391 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
2394 static void gen6_enable_rps(struct drm_device
*dev
)
2396 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2397 struct intel_ring_buffer
*ring
;
2400 u32 pcu_mbox
, rc6_mask
= 0;
2405 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2407 /* Here begins a magic sequence of register writes to enable
2408 * auto-downclocking.
2410 * Perhaps there might be some value in exposing these to
2413 I915_WRITE(GEN6_RC_STATE
, 0);
2415 /* Clear the DBG now so we don't confuse earlier errors */
2416 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
2417 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
2418 I915_WRITE(GTFIFODBG
, gtfifodbg
);
2421 gen6_gt_force_wake_get(dev_priv
);
2423 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
2424 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
2426 /* In units of 100MHz */
2427 dev_priv
->rps
.max_delay
= rp_state_cap
& 0xff;
2428 dev_priv
->rps
.min_delay
= (rp_state_cap
& 0xff0000) >> 16;
2429 dev_priv
->rps
.cur_delay
= 0;
2431 /* disable the counters and set deterministic thresholds */
2432 I915_WRITE(GEN6_RC_CONTROL
, 0);
2434 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
2435 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
2436 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
2437 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
2438 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
2440 for_each_ring(ring
, dev_priv
, i
)
2441 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
2443 I915_WRITE(GEN6_RC_SLEEP
, 0);
2444 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
2445 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
2446 I915_WRITE(GEN6_RC6p_THRESHOLD
, 100000);
2447 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
2449 /* Check if we are enabling RC6 */
2450 rc6_mode
= intel_enable_rc6(dev_priv
->dev
);
2451 if (rc6_mode
& INTEL_RC6_ENABLE
)
2452 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
2454 /* We don't use those on Haswell */
2455 if (!IS_HASWELL(dev
)) {
2456 if (rc6_mode
& INTEL_RC6p_ENABLE
)
2457 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
2459 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
2460 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
2463 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
2464 (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off",
2465 (rc6_mask
& GEN6_RC_CTL_RC6p_ENABLE
) ? "on" : "off",
2466 (rc6_mask
& GEN6_RC_CTL_RC6pp_ENABLE
) ? "on" : "off");
2468 I915_WRITE(GEN6_RC_CONTROL
,
2470 GEN6_RC_CTL_EI_MODE(1) |
2471 GEN6_RC_CTL_HW_ENABLE
);
2473 I915_WRITE(GEN6_RPNSWREQ
,
2474 GEN6_FREQUENCY(10) |
2476 GEN6_AGGRESSIVE_TURBO
);
2477 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
2478 GEN6_FREQUENCY(12));
2480 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
2481 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
2482 dev_priv
->rps
.max_delay
<< 24 |
2483 dev_priv
->rps
.min_delay
<< 16);
2485 if (IS_HASWELL(dev
)) {
2486 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
2487 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
2488 I915_WRITE(GEN6_RP_UP_EI
, 66000);
2489 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
2491 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 10000);
2492 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 1000000);
2493 I915_WRITE(GEN6_RP_UP_EI
, 100000);
2494 I915_WRITE(GEN6_RP_DOWN_EI
, 5000000);
2497 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
2498 I915_WRITE(GEN6_RP_CONTROL
,
2499 GEN6_RP_MEDIA_TURBO
|
2500 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
2501 GEN6_RP_MEDIA_IS_GFX
|
2503 GEN6_RP_UP_BUSY_AVG
|
2504 (IS_HASWELL(dev
) ? GEN7_RP_DOWN_IDLE_AVG
: GEN6_RP_DOWN_IDLE_CONT
));
2506 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
2508 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
2510 I915_WRITE(GEN6_PCODE_DATA
, 0);
2511 I915_WRITE(GEN6_PCODE_MAILBOX
,
2513 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
);
2514 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
2516 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
2518 /* Check for overclock support */
2519 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
2521 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
2522 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_READ_OC_PARAMS
);
2523 pcu_mbox
= I915_READ(GEN6_PCODE_DATA
);
2524 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
2526 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
2527 if (pcu_mbox
& (1<<31)) { /* OC supported */
2528 dev_priv
->rps
.max_delay
= pcu_mbox
& 0xff;
2529 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox
* 50);
2532 gen6_set_rps(dev_priv
->dev
, (gt_perf_status
& 0xff00) >> 8);
2534 /* requires MSI enabled */
2535 I915_WRITE(GEN6_PMIER
, GEN6_PM_DEFERRED_EVENTS
);
2536 spin_lock_irq(&dev_priv
->rps
.lock
);
2537 WARN_ON(dev_priv
->rps
.pm_iir
!= 0);
2538 I915_WRITE(GEN6_PMIMR
, 0);
2539 spin_unlock_irq(&dev_priv
->rps
.lock
);
2540 /* enable all PM interrupts */
2541 I915_WRITE(GEN6_PMINTRMSK
, 0);
2543 gen6_gt_force_wake_put(dev_priv
);
2546 static void gen6_update_ring_freq(struct drm_device
*dev
)
2548 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2550 int gpu_freq
, ia_freq
, max_ia_freq
;
2551 int scaling_factor
= 180;
2553 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2555 max_ia_freq
= cpufreq_quick_get_max(0);
2557 * Default to measured freq if none found, PCU will ensure we don't go
2561 max_ia_freq
= tsc_khz
;
2563 /* Convert from kHz to MHz */
2564 max_ia_freq
/= 1000;
2567 * For each potential GPU frequency, load a ring frequency we'd like
2568 * to use for memory access. We do this by specifying the IA frequency
2569 * the PCU should use as a reference to determine the ring frequency.
2571 for (gpu_freq
= dev_priv
->rps
.max_delay
; gpu_freq
>= dev_priv
->rps
.min_delay
;
2573 int diff
= dev_priv
->rps
.max_delay
- gpu_freq
;
2576 * For GPU frequencies less than 750MHz, just use the lowest
2579 if (gpu_freq
< min_freq
)
2582 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
2583 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
2585 I915_WRITE(GEN6_PCODE_DATA
,
2586 (ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
) |
2588 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
|
2589 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
);
2590 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) &
2591 GEN6_PCODE_READY
) == 0, 10)) {
2592 DRM_ERROR("pcode write of freq table timed out\n");
2598 void ironlake_teardown_rc6(struct drm_device
*dev
)
2600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2602 if (dev_priv
->renderctx
) {
2603 i915_gem_object_unpin(dev_priv
->renderctx
);
2604 drm_gem_object_unreference(&dev_priv
->renderctx
->base
);
2605 dev_priv
->renderctx
= NULL
;
2608 if (dev_priv
->pwrctx
) {
2609 i915_gem_object_unpin(dev_priv
->pwrctx
);
2610 drm_gem_object_unreference(&dev_priv
->pwrctx
->base
);
2611 dev_priv
->pwrctx
= NULL
;
2615 static void ironlake_disable_rc6(struct drm_device
*dev
)
2617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2619 if (I915_READ(PWRCTXA
)) {
2620 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
2621 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) | RCX_SW_EXIT
);
2622 wait_for(((I915_READ(RSTDBYCTL
) & RSX_STATUS_MASK
) == RSX_STATUS_ON
),
2625 I915_WRITE(PWRCTXA
, 0);
2626 POSTING_READ(PWRCTXA
);
2628 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
2629 POSTING_READ(RSTDBYCTL
);
2633 static int ironlake_setup_rc6(struct drm_device
*dev
)
2635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2637 if (dev_priv
->renderctx
== NULL
)
2638 dev_priv
->renderctx
= intel_alloc_context_page(dev
);
2639 if (!dev_priv
->renderctx
)
2642 if (dev_priv
->pwrctx
== NULL
)
2643 dev_priv
->pwrctx
= intel_alloc_context_page(dev
);
2644 if (!dev_priv
->pwrctx
) {
2645 ironlake_teardown_rc6(dev
);
2652 static void ironlake_enable_rc6(struct drm_device
*dev
)
2654 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2655 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
2658 /* rc6 disabled by default due to repeated reports of hanging during
2661 if (!intel_enable_rc6(dev
))
2664 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2666 ret
= ironlake_setup_rc6(dev
);
2671 * GPU can automatically power down the render unit if given a page
2674 ret
= intel_ring_begin(ring
, 6);
2676 ironlake_teardown_rc6(dev
);
2680 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
| MI_SUSPEND_FLUSH_EN
);
2681 intel_ring_emit(ring
, MI_SET_CONTEXT
);
2682 intel_ring_emit(ring
, dev_priv
->renderctx
->gtt_offset
|
2684 MI_SAVE_EXT_STATE_EN
|
2685 MI_RESTORE_EXT_STATE_EN
|
2686 MI_RESTORE_INHIBIT
);
2687 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
);
2688 intel_ring_emit(ring
, MI_NOOP
);
2689 intel_ring_emit(ring
, MI_FLUSH
);
2690 intel_ring_advance(ring
);
2693 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
2694 * does an implicit flush, combined with MI_FLUSH above, it should be
2695 * safe to assume that renderctx is valid
2697 ret
= intel_wait_ring_idle(ring
);
2699 DRM_ERROR("failed to enable ironlake power power savings\n");
2700 ironlake_teardown_rc6(dev
);
2704 I915_WRITE(PWRCTXA
, dev_priv
->pwrctx
->gtt_offset
| PWRCTX_EN
);
2705 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
2708 static unsigned long intel_pxfreq(u32 vidfreq
)
2711 int div
= (vidfreq
& 0x3f0000) >> 16;
2712 int post
= (vidfreq
& 0x3000) >> 12;
2713 int pre
= (vidfreq
& 0x7);
2718 freq
= ((div
* 133333) / ((1<<post
) * pre
));
2723 static const struct cparams
{
2729 { 1, 1333, 301, 28664 },
2730 { 1, 1066, 294, 24460 },
2731 { 1, 800, 294, 25192 },
2732 { 0, 1333, 276, 27605 },
2733 { 0, 1066, 276, 27605 },
2734 { 0, 800, 231, 23784 },
2737 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
2739 u64 total_count
, diff
, ret
;
2740 u32 count1
, count2
, count3
, m
= 0, c
= 0;
2741 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
2744 assert_spin_locked(&mchdev_lock
);
2746 diff1
= now
- dev_priv
->last_time1
;
2748 /* Prevent division-by-zero if we are asking too fast.
2749 * Also, we don't get interesting results if we are polling
2750 * faster than once in 10ms, so just return the saved value
2754 return dev_priv
->chipset_power
;
2756 count1
= I915_READ(DMIEC
);
2757 count2
= I915_READ(DDREC
);
2758 count3
= I915_READ(CSIEC
);
2760 total_count
= count1
+ count2
+ count3
;
2762 /* FIXME: handle per-counter overflow */
2763 if (total_count
< dev_priv
->last_count1
) {
2764 diff
= ~0UL - dev_priv
->last_count1
;
2765 diff
+= total_count
;
2767 diff
= total_count
- dev_priv
->last_count1
;
2770 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
2771 if (cparams
[i
].i
== dev_priv
->c_m
&&
2772 cparams
[i
].t
== dev_priv
->r_t
) {
2779 diff
= div_u64(diff
, diff1
);
2780 ret
= ((m
* diff
) + c
);
2781 ret
= div_u64(ret
, 10);
2783 dev_priv
->last_count1
= total_count
;
2784 dev_priv
->last_time1
= now
;
2786 dev_priv
->chipset_power
= ret
;
2791 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
2793 unsigned long m
, x
, b
;
2796 tsfs
= I915_READ(TSFS
);
2798 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
2799 x
= I915_READ8(TR1
);
2801 b
= tsfs
& TSFS_INTR_MASK
;
2803 return ((m
* x
) / 127) - b
;
2806 static u16
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
2808 static const struct v_table
{
2809 u16 vd
; /* in .1 mil */
2810 u16 vm
; /* in .1 mil */
2941 if (dev_priv
->info
->is_mobile
)
2942 return v_table
[pxvid
].vm
;
2944 return v_table
[pxvid
].vd
;
2947 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
2949 struct timespec now
, diff1
;
2951 unsigned long diffms
;
2954 assert_spin_locked(&mchdev_lock
);
2956 getrawmonotonic(&now
);
2957 diff1
= timespec_sub(now
, dev_priv
->last_time2
);
2959 /* Don't divide by 0 */
2960 diffms
= diff1
.tv_sec
* 1000 + diff1
.tv_nsec
/ 1000000;
2964 count
= I915_READ(GFXEC
);
2966 if (count
< dev_priv
->last_count2
) {
2967 diff
= ~0UL - dev_priv
->last_count2
;
2970 diff
= count
- dev_priv
->last_count2
;
2973 dev_priv
->last_count2
= count
;
2974 dev_priv
->last_time2
= now
;
2976 /* More magic constants... */
2978 diff
= div_u64(diff
, diffms
* 10);
2979 dev_priv
->gfx_power
= diff
;
2982 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
2984 if (dev_priv
->info
->gen
!= 5)
2987 spin_lock_irq(&mchdev_lock
);
2989 __i915_update_gfx_val(dev_priv
);
2991 spin_unlock_irq(&mchdev_lock
);
2994 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
2996 unsigned long t
, corr
, state1
, corr2
, state2
;
2999 assert_spin_locked(&mchdev_lock
);
3001 pxvid
= I915_READ(PXVFREQ_BASE
+ (dev_priv
->rps
.cur_delay
* 4));
3002 pxvid
= (pxvid
>> 24) & 0x7f;
3003 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
3007 t
= i915_mch_val(dev_priv
);
3009 /* Revel in the empirically derived constants */
3011 /* Correction factor in 1/100000 units */
3013 corr
= ((t
* 2349) + 135940);
3015 corr
= ((t
* 964) + 29317);
3017 corr
= ((t
* 301) + 1004);
3019 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
3021 corr2
= (corr
* dev_priv
->corr
);
3023 state2
= (corr2
* state1
) / 10000;
3024 state2
/= 100; /* convert to mW */
3026 __i915_update_gfx_val(dev_priv
);
3028 return dev_priv
->gfx_power
+ state2
;
3032 * i915_read_mch_val - return value for IPS use
3034 * Calculate and return a value for the IPS driver to use when deciding whether
3035 * we have thermal and power headroom to increase CPU or GPU power budget.
3037 unsigned long i915_read_mch_val(void)
3039 struct drm_i915_private
*dev_priv
;
3040 unsigned long chipset_val
, graphics_val
, ret
= 0;
3042 spin_lock_irq(&mchdev_lock
);
3045 dev_priv
= i915_mch_dev
;
3047 chipset_val
= i915_chipset_val(dev_priv
);
3048 graphics_val
= i915_gfx_val(dev_priv
);
3050 ret
= chipset_val
+ graphics_val
;
3053 spin_unlock_irq(&mchdev_lock
);
3057 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
3060 * i915_gpu_raise - raise GPU frequency limit
3062 * Raise the limit; IPS indicates we have thermal headroom.
3064 bool i915_gpu_raise(void)
3066 struct drm_i915_private
*dev_priv
;
3069 spin_lock_irq(&mchdev_lock
);
3070 if (!i915_mch_dev
) {
3074 dev_priv
= i915_mch_dev
;
3076 if (dev_priv
->max_delay
> dev_priv
->fmax
)
3077 dev_priv
->max_delay
--;
3080 spin_unlock_irq(&mchdev_lock
);
3084 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
3087 * i915_gpu_lower - lower GPU frequency limit
3089 * IPS indicates we're close to a thermal limit, so throttle back the GPU
3090 * frequency maximum.
3092 bool i915_gpu_lower(void)
3094 struct drm_i915_private
*dev_priv
;
3097 spin_lock_irq(&mchdev_lock
);
3098 if (!i915_mch_dev
) {
3102 dev_priv
= i915_mch_dev
;
3104 if (dev_priv
->max_delay
< dev_priv
->min_delay
)
3105 dev_priv
->max_delay
++;
3108 spin_unlock_irq(&mchdev_lock
);
3112 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
3115 * i915_gpu_busy - indicate GPU business to IPS
3117 * Tell the IPS driver whether or not the GPU is busy.
3119 bool i915_gpu_busy(void)
3121 struct drm_i915_private
*dev_priv
;
3122 struct intel_ring_buffer
*ring
;
3126 spin_lock_irq(&mchdev_lock
);
3129 dev_priv
= i915_mch_dev
;
3131 for_each_ring(ring
, dev_priv
, i
)
3132 ret
|= !list_empty(&ring
->request_list
);
3135 spin_unlock_irq(&mchdev_lock
);
3139 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
3142 * i915_gpu_turbo_disable - disable graphics turbo
3144 * Disable graphics turbo by resetting the max frequency and setting the
3145 * current frequency to the default.
3147 bool i915_gpu_turbo_disable(void)
3149 struct drm_i915_private
*dev_priv
;
3152 spin_lock_irq(&mchdev_lock
);
3153 if (!i915_mch_dev
) {
3157 dev_priv
= i915_mch_dev
;
3159 dev_priv
->max_delay
= dev_priv
->fstart
;
3161 if (!ironlake_set_drps(dev_priv
->dev
, dev_priv
->fstart
))
3165 spin_unlock_irq(&mchdev_lock
);
3169 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
3172 * Tells the intel_ips driver that the i915 driver is now loaded, if
3173 * IPS got loaded first.
3175 * This awkward dance is so that neither module has to depend on the
3176 * other in order for IPS to do the appropriate communication of
3177 * GPU turbo limits to i915.
3180 ips_ping_for_i915_load(void)
3184 link
= symbol_get(ips_link_to_i915_driver
);
3187 symbol_put(ips_link_to_i915_driver
);
3191 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
3193 /* We only register the i915 ips part with intel-ips once everything is
3194 * set up, to avoid intel-ips sneaking in and reading bogus values. */
3195 spin_lock_irq(&mchdev_lock
);
3196 i915_mch_dev
= dev_priv
;
3197 spin_unlock_irq(&mchdev_lock
);
3199 ips_ping_for_i915_load();
3202 void intel_gpu_ips_teardown(void)
3204 spin_lock_irq(&mchdev_lock
);
3205 i915_mch_dev
= NULL
;
3206 spin_unlock_irq(&mchdev_lock
);
3208 static void intel_init_emon(struct drm_device
*dev
)
3210 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3215 /* Disable to program */
3219 /* Program energy weights for various events */
3220 I915_WRITE(SDEW
, 0x15040d00);
3221 I915_WRITE(CSIEW0
, 0x007f0000);
3222 I915_WRITE(CSIEW1
, 0x1e220004);
3223 I915_WRITE(CSIEW2
, 0x04000004);
3225 for (i
= 0; i
< 5; i
++)
3226 I915_WRITE(PEW
+ (i
* 4), 0);
3227 for (i
= 0; i
< 3; i
++)
3228 I915_WRITE(DEW
+ (i
* 4), 0);
3230 /* Program P-state weights to account for frequency power adjustment */
3231 for (i
= 0; i
< 16; i
++) {
3232 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
3233 unsigned long freq
= intel_pxfreq(pxvidfreq
);
3234 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
3239 val
*= (freq
/ 1000);
3241 val
/= (127*127*900);
3243 DRM_ERROR("bad pxval: %ld\n", val
);
3246 /* Render standby states get 0 weight */
3250 for (i
= 0; i
< 4; i
++) {
3251 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
3252 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
3253 I915_WRITE(PXW
+ (i
* 4), val
);
3256 /* Adjust magic regs to magic values (more experimental results) */
3257 I915_WRITE(OGW0
, 0);
3258 I915_WRITE(OGW1
, 0);
3259 I915_WRITE(EG0
, 0x00007f00);
3260 I915_WRITE(EG1
, 0x0000000e);
3261 I915_WRITE(EG2
, 0x000e0000);
3262 I915_WRITE(EG3
, 0x68000300);
3263 I915_WRITE(EG4
, 0x42000000);
3264 I915_WRITE(EG5
, 0x00140031);
3268 for (i
= 0; i
< 8; i
++)
3269 I915_WRITE(PXWL
+ (i
* 4), 0);
3271 /* Enable PMON + select events */
3272 I915_WRITE(ECR
, 0x80000019);
3274 lcfuse
= I915_READ(LCFUSE02
);
3276 dev_priv
->corr
= (lcfuse
& LCFUSE_HIV_MASK
);
3279 void intel_disable_gt_powersave(struct drm_device
*dev
)
3281 if (IS_IRONLAKE_M(dev
)) {
3282 ironlake_disable_drps(dev
);
3283 ironlake_disable_rc6(dev
);
3284 } else if (INTEL_INFO(dev
)->gen
>= 6 && !IS_VALLEYVIEW(dev
)) {
3285 gen6_disable_rps(dev
);
3289 void intel_enable_gt_powersave(struct drm_device
*dev
)
3291 if (IS_IRONLAKE_M(dev
)) {
3292 ironlake_enable_drps(dev
);
3293 ironlake_enable_rc6(dev
);
3294 intel_init_emon(dev
);
3295 } else if ((IS_GEN6(dev
) || IS_GEN7(dev
)) && !IS_VALLEYVIEW(dev
)) {
3296 gen6_enable_rps(dev
);
3297 gen6_update_ring_freq(dev
);
3301 static void ironlake_init_clock_gating(struct drm_device
*dev
)
3303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3304 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
3306 /* Required for FBC */
3307 dspclk_gate
|= DPFCUNIT_CLOCK_GATE_DISABLE
|
3308 DPFCRUNIT_CLOCK_GATE_DISABLE
|
3309 DPFDUNIT_CLOCK_GATE_DISABLE
;
3310 /* Required for CxSR */
3311 dspclk_gate
|= DPARBUNIT_CLOCK_GATE_DISABLE
;
3313 I915_WRITE(PCH_3DCGDIS0
,
3314 MARIUNIT_CLOCK_GATE_DISABLE
|
3315 SVSMUNIT_CLOCK_GATE_DISABLE
);
3316 I915_WRITE(PCH_3DCGDIS1
,
3317 VFMUNIT_CLOCK_GATE_DISABLE
);
3319 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
3322 * According to the spec the following bits should be set in
3323 * order to enable memory self-refresh
3324 * The bit 22/21 of 0x42004
3325 * The bit 5 of 0x42020
3326 * The bit 15 of 0x45000
3328 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
3329 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
3330 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
3331 I915_WRITE(ILK_DSPCLK_GATE
,
3332 (I915_READ(ILK_DSPCLK_GATE
) |
3333 ILK_DPARB_CLK_GATE
));
3334 I915_WRITE(DISP_ARB_CTL
,
3335 (I915_READ(DISP_ARB_CTL
) |
3337 I915_WRITE(WM3_LP_ILK
, 0);
3338 I915_WRITE(WM2_LP_ILK
, 0);
3339 I915_WRITE(WM1_LP_ILK
, 0);
3342 * Based on the document from hardware guys the following bits
3343 * should be set unconditionally in order to enable FBC.
3344 * The bit 22 of 0x42000
3345 * The bit 22 of 0x42004
3346 * The bit 7,8,9 of 0x42020.
3348 if (IS_IRONLAKE_M(dev
)) {
3349 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
3350 I915_READ(ILK_DISPLAY_CHICKEN1
) |
3352 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
3353 I915_READ(ILK_DISPLAY_CHICKEN2
) |
3355 I915_WRITE(ILK_DSPCLK_GATE
,
3356 I915_READ(ILK_DSPCLK_GATE
) |
3362 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
3363 I915_READ(ILK_DISPLAY_CHICKEN2
) |
3364 ILK_ELPIN_409_SELECT
);
3365 I915_WRITE(_3D_CHICKEN2
,
3366 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
3367 _3D_CHICKEN2_WM_READ_PIPELINED
);
3370 static void gen6_init_clock_gating(struct drm_device
*dev
)
3372 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3374 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
3376 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
3378 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
3379 I915_READ(ILK_DISPLAY_CHICKEN2
) |
3380 ILK_ELPIN_409_SELECT
);
3382 I915_WRITE(WM3_LP_ILK
, 0);
3383 I915_WRITE(WM2_LP_ILK
, 0);
3384 I915_WRITE(WM1_LP_ILK
, 0);
3386 I915_WRITE(CACHE_MODE_0
,
3387 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
3389 I915_WRITE(GEN6_UCGCTL1
,
3390 I915_READ(GEN6_UCGCTL1
) |
3391 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
3392 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
3394 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3395 * gating disable must be set. Failure to set it results in
3396 * flickering pixels due to Z write ordering failures after
3397 * some amount of runtime in the Mesa "fire" demo, and Unigine
3398 * Sanctuary and Tropics, and apparently anything else with
3399 * alpha test or pixel discard.
3401 * According to the spec, bit 11 (RCCUNIT) must also be set,
3402 * but we didn't debug actual testcases to find it out.
3404 * Also apply WaDisableVDSUnitClockGating and
3405 * WaDisableRCPBUnitClockGating.
3407 I915_WRITE(GEN6_UCGCTL2
,
3408 GEN7_VDSUNIT_CLOCK_GATE_DISABLE
|
3409 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
3410 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
3412 /* Bspec says we need to always set all mask bits. */
3413 I915_WRITE(_3D_CHICKEN
, (0xFFFF << 16) |
3414 _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL
);
3417 * According to the spec the following bits should be
3418 * set in order to enable memory self-refresh and fbc:
3419 * The bit21 and bit22 of 0x42000
3420 * The bit21 and bit22 of 0x42004
3421 * The bit5 and bit7 of 0x42020
3422 * The bit14 of 0x70180
3423 * The bit14 of 0x71180
3425 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
3426 I915_READ(ILK_DISPLAY_CHICKEN1
) |
3427 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
3428 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
3429 I915_READ(ILK_DISPLAY_CHICKEN2
) |
3430 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
3431 I915_WRITE(ILK_DSPCLK_GATE
,
3432 I915_READ(ILK_DSPCLK_GATE
) |
3433 ILK_DPARB_CLK_GATE
|
3436 I915_WRITE(GEN6_MBCTL
, I915_READ(GEN6_MBCTL
) |
3437 GEN6_MBCTL_ENABLE_BOOT_FETCH
);
3439 for_each_pipe(pipe
) {
3440 I915_WRITE(DSPCNTR(pipe
),
3441 I915_READ(DSPCNTR(pipe
)) |
3442 DISPPLANE_TRICKLE_FEED_DISABLE
);
3443 intel_flush_display_plane(dev_priv
, pipe
);
3447 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
3449 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
3451 reg
&= ~GEN7_FF_SCHED_MASK
;
3452 reg
|= GEN7_FF_TS_SCHED_HW
;
3453 reg
|= GEN7_FF_VS_SCHED_HW
;
3454 reg
|= GEN7_FF_DS_SCHED_HW
;
3456 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
3459 static void haswell_init_clock_gating(struct drm_device
*dev
)
3461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3463 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
3465 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
3467 I915_WRITE(WM3_LP_ILK
, 0);
3468 I915_WRITE(WM2_LP_ILK
, 0);
3469 I915_WRITE(WM1_LP_ILK
, 0);
3471 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3472 * This implements the WaDisableRCZUnitClockGating workaround.
3474 I915_WRITE(GEN6_UCGCTL2
, GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
3476 I915_WRITE(ILK_DSPCLK_GATE
, IVB_VRHUNIT_CLK_GATE
);
3478 I915_WRITE(IVB_CHICKEN3
,
3479 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
3480 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
3482 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3483 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
3484 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
3486 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3487 I915_WRITE(GEN7_L3CNTLREG1
,
3488 GEN7_WA_FOR_GEN7_L3_CONTROL
);
3489 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
3490 GEN7_WA_L3_CHICKEN_MODE
);
3492 /* This is required by WaCatErrorRejectionIssue */
3493 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
3494 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
3495 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
3497 for_each_pipe(pipe
) {
3498 I915_WRITE(DSPCNTR(pipe
),
3499 I915_READ(DSPCNTR(pipe
)) |
3500 DISPPLANE_TRICKLE_FEED_DISABLE
);
3501 intel_flush_display_plane(dev_priv
, pipe
);
3504 gen7_setup_fixed_func_scheduler(dev_priv
);
3506 /* WaDisable4x2SubspanOptimization */
3507 I915_WRITE(CACHE_MODE_1
,
3508 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
3510 /* XXX: This is a workaround for early silicon revisions and should be
3515 WM_DBG_DISALLOW_MULTIPLE_LP
|
3516 WM_DBG_DISALLOW_SPRITE
|
3517 WM_DBG_DISALLOW_MAXFIFO
);
3521 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
3523 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3525 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
3528 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
3530 I915_WRITE(WM3_LP_ILK
, 0);
3531 I915_WRITE(WM2_LP_ILK
, 0);
3532 I915_WRITE(WM1_LP_ILK
, 0);
3534 I915_WRITE(ILK_DSPCLK_GATE
, IVB_VRHUNIT_CLK_GATE
);
3536 I915_WRITE(IVB_CHICKEN3
,
3537 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
3538 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
3540 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3541 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
3542 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
3544 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3545 I915_WRITE(GEN7_L3CNTLREG1
,
3546 GEN7_WA_FOR_GEN7_L3_CONTROL
);
3547 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
3548 GEN7_WA_L3_CHICKEN_MODE
);
3550 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3551 * gating disable must be set. Failure to set it results in
3552 * flickering pixels due to Z write ordering failures after
3553 * some amount of runtime in the Mesa "fire" demo, and Unigine
3554 * Sanctuary and Tropics, and apparently anything else with
3555 * alpha test or pixel discard.
3557 * According to the spec, bit 11 (RCCUNIT) must also be set,
3558 * but we didn't debug actual testcases to find it out.
3560 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3561 * This implements the WaDisableRCZUnitClockGating workaround.
3563 I915_WRITE(GEN6_UCGCTL2
,
3564 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
|
3565 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
3567 /* This is required by WaCatErrorRejectionIssue */
3568 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
3569 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
3570 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
3572 for_each_pipe(pipe
) {
3573 I915_WRITE(DSPCNTR(pipe
),
3574 I915_READ(DSPCNTR(pipe
)) |
3575 DISPPLANE_TRICKLE_FEED_DISABLE
);
3576 intel_flush_display_plane(dev_priv
, pipe
);
3579 I915_WRITE(GEN6_MBCTL
, I915_READ(GEN6_MBCTL
) |
3580 GEN6_MBCTL_ENABLE_BOOT_FETCH
);
3582 gen7_setup_fixed_func_scheduler(dev_priv
);
3584 /* WaDisable4x2SubspanOptimization */
3585 I915_WRITE(CACHE_MODE_1
,
3586 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
3588 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
3589 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
3590 snpcr
|= GEN6_MBC_SNPCR_MED
;
3591 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
3594 static void valleyview_init_clock_gating(struct drm_device
*dev
)
3596 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3598 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
3600 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
3602 I915_WRITE(WM3_LP_ILK
, 0);
3603 I915_WRITE(WM2_LP_ILK
, 0);
3604 I915_WRITE(WM1_LP_ILK
, 0);
3606 I915_WRITE(ILK_DSPCLK_GATE
, IVB_VRHUNIT_CLK_GATE
);
3608 I915_WRITE(IVB_CHICKEN3
,
3609 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
3610 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
3612 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3613 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
3614 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
3616 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3617 I915_WRITE(GEN7_L3CNTLREG1
, GEN7_WA_FOR_GEN7_L3_CONTROL
);
3618 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
, GEN7_WA_L3_CHICKEN_MODE
);
3620 /* This is required by WaCatErrorRejectionIssue */
3621 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
3622 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
3623 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
3625 I915_WRITE(GEN6_MBCTL
, I915_READ(GEN6_MBCTL
) |
3626 GEN6_MBCTL_ENABLE_BOOT_FETCH
);
3629 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3630 * gating disable must be set. Failure to set it results in
3631 * flickering pixels due to Z write ordering failures after
3632 * some amount of runtime in the Mesa "fire" demo, and Unigine
3633 * Sanctuary and Tropics, and apparently anything else with
3634 * alpha test or pixel discard.
3636 * According to the spec, bit 11 (RCCUNIT) must also be set,
3637 * but we didn't debug actual testcases to find it out.
3639 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3640 * This implements the WaDisableRCZUnitClockGating workaround.
3642 * Also apply WaDisableVDSUnitClockGating and
3643 * WaDisableRCPBUnitClockGating.
3645 I915_WRITE(GEN6_UCGCTL2
,
3646 GEN7_VDSUNIT_CLOCK_GATE_DISABLE
|
3647 GEN7_TDLUNIT_CLOCK_GATE_DISABLE
|
3648 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
|
3649 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
3650 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
3652 I915_WRITE(GEN7_UCGCTL4
, GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
3654 for_each_pipe(pipe
) {
3655 I915_WRITE(DSPCNTR(pipe
),
3656 I915_READ(DSPCNTR(pipe
)) |
3657 DISPPLANE_TRICKLE_FEED_DISABLE
);
3658 intel_flush_display_plane(dev_priv
, pipe
);
3661 I915_WRITE(CACHE_MODE_1
,
3662 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
3665 * On ValleyView, the GUnit needs to signal the GT
3666 * when flip and other events complete. So enable
3667 * all the GUnit->GT interrupts here
3669 I915_WRITE(VLV_DPFLIPSTAT
, PIPEB_LINE_COMPARE_INT_EN
|
3670 PIPEB_HLINE_INT_EN
| PIPEB_VBLANK_INT_EN
|
3671 SPRITED_FLIPDONE_INT_EN
| SPRITEC_FLIPDONE_INT_EN
|
3672 PLANEB_FLIPDONE_INT_EN
| PIPEA_LINE_COMPARE_INT_EN
|
3673 PIPEA_HLINE_INT_EN
| PIPEA_VBLANK_INT_EN
|
3674 SPRITEB_FLIPDONE_INT_EN
| SPRITEA_FLIPDONE_INT_EN
|
3675 PLANEA_FLIPDONE_INT_EN
);
3678 static void g4x_init_clock_gating(struct drm_device
*dev
)
3680 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3681 uint32_t dspclk_gate
;
3683 I915_WRITE(RENCLK_GATE_D1
, 0);
3684 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
3685 GS_UNIT_CLOCK_GATE_DISABLE
|
3686 CL_UNIT_CLOCK_GATE_DISABLE
);
3687 I915_WRITE(RAMCLK_GATE_D
, 0);
3688 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
3689 OVRUNIT_CLOCK_GATE_DISABLE
|
3690 OVCUNIT_CLOCK_GATE_DISABLE
;
3692 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
3693 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
3696 static void crestline_init_clock_gating(struct drm_device
*dev
)
3698 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3700 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
3701 I915_WRITE(RENCLK_GATE_D2
, 0);
3702 I915_WRITE(DSPCLK_GATE_D
, 0);
3703 I915_WRITE(RAMCLK_GATE_D
, 0);
3704 I915_WRITE16(DEUC
, 0);
3707 static void broadwater_init_clock_gating(struct drm_device
*dev
)
3709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3711 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
3712 I965_RCC_CLOCK_GATE_DISABLE
|
3713 I965_RCPB_CLOCK_GATE_DISABLE
|
3714 I965_ISC_CLOCK_GATE_DISABLE
|
3715 I965_FBC_CLOCK_GATE_DISABLE
);
3716 I915_WRITE(RENCLK_GATE_D2
, 0);
3719 static void gen3_init_clock_gating(struct drm_device
*dev
)
3721 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3722 u32 dstate
= I915_READ(D_STATE
);
3724 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
3725 DSTATE_DOT_CLOCK_GATING
;
3726 I915_WRITE(D_STATE
, dstate
);
3728 if (IS_PINEVIEW(dev
))
3729 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
3732 static void i85x_init_clock_gating(struct drm_device
*dev
)
3734 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3736 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
3739 static void i830_init_clock_gating(struct drm_device
*dev
)
3741 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3743 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
3746 static void ibx_init_clock_gating(struct drm_device
*dev
)
3748 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3751 * On Ibex Peak and Cougar Point, we need to disable clock
3752 * gating for the panel power sequencer or it will fail to
3753 * start up when no ports are active.
3755 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
3758 static void cpt_init_clock_gating(struct drm_device
*dev
)
3760 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3764 * On Ibex Peak and Cougar Point, we need to disable clock
3765 * gating for the panel power sequencer or it will fail to
3766 * start up when no ports are active.
3768 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
3769 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
3770 DPLS_EDP_PPS_FIX_DIS
);
3771 /* Without this, mode sets may fail silently on FDI */
3773 I915_WRITE(TRANS_CHICKEN2(pipe
), TRANS_AUTOTRAIN_GEN_STALL_DIS
);
3776 void intel_init_clock_gating(struct drm_device
*dev
)
3778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3780 dev_priv
->display
.init_clock_gating(dev
);
3782 if (dev_priv
->display
.init_pch_clock_gating
)
3783 dev_priv
->display
.init_pch_clock_gating(dev
);
3786 /* Starting with Haswell, we have different power wells for
3787 * different parts of the GPU. This attempts to enable them all.
3789 void intel_init_power_wells(struct drm_device
*dev
)
3791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3792 unsigned long power_wells
[] = {
3799 if (!IS_HASWELL(dev
))
3802 mutex_lock(&dev
->struct_mutex
);
3804 for (i
= 0; i
< ARRAY_SIZE(power_wells
); i
++) {
3805 int well
= I915_READ(power_wells
[i
]);
3807 if ((well
& HSW_PWR_WELL_STATE
) == 0) {
3808 I915_WRITE(power_wells
[i
], well
& HSW_PWR_WELL_ENABLE
);
3809 if (wait_for(I915_READ(power_wells
[i
] & HSW_PWR_WELL_STATE
), 20))
3810 DRM_ERROR("Error enabling power well %lx\n", power_wells
[i
]);
3814 mutex_unlock(&dev
->struct_mutex
);
3817 /* Set up chip specific power management-related functions */
3818 void intel_init_pm(struct drm_device
*dev
)
3820 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3822 if (I915_HAS_FBC(dev
)) {
3823 if (HAS_PCH_SPLIT(dev
)) {
3824 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
3825 dev_priv
->display
.enable_fbc
= ironlake_enable_fbc
;
3826 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
3827 } else if (IS_GM45(dev
)) {
3828 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
3829 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
3830 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
3831 } else if (IS_CRESTLINE(dev
)) {
3832 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
3833 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
3834 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
3836 /* 855GM needs testing */
3840 if (IS_PINEVIEW(dev
))
3841 i915_pineview_get_mem_freq(dev
);
3842 else if (IS_GEN5(dev
))
3843 i915_ironlake_get_mem_freq(dev
);
3845 /* For FIFO watermark updates */
3846 if (HAS_PCH_SPLIT(dev
)) {
3847 if (HAS_PCH_IBX(dev
))
3848 dev_priv
->display
.init_pch_clock_gating
= ibx_init_clock_gating
;
3849 else if (HAS_PCH_CPT(dev
))
3850 dev_priv
->display
.init_pch_clock_gating
= cpt_init_clock_gating
;
3853 if (I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
)
3854 dev_priv
->display
.update_wm
= ironlake_update_wm
;
3856 DRM_DEBUG_KMS("Failed to get proper latency. "
3858 dev_priv
->display
.update_wm
= NULL
;
3860 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
3861 } else if (IS_GEN6(dev
)) {
3862 if (SNB_READ_WM0_LATENCY()) {
3863 dev_priv
->display
.update_wm
= sandybridge_update_wm
;
3864 dev_priv
->display
.update_sprite_wm
= sandybridge_update_sprite_wm
;
3866 DRM_DEBUG_KMS("Failed to read display plane latency. "
3868 dev_priv
->display
.update_wm
= NULL
;
3870 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
3871 } else if (IS_IVYBRIDGE(dev
)) {
3872 /* FIXME: detect B0+ stepping and use auto training */
3873 if (SNB_READ_WM0_LATENCY()) {
3874 dev_priv
->display
.update_wm
= sandybridge_update_wm
;
3875 dev_priv
->display
.update_sprite_wm
= sandybridge_update_sprite_wm
;
3877 DRM_DEBUG_KMS("Failed to read display plane latency. "
3879 dev_priv
->display
.update_wm
= NULL
;
3881 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
3882 } else if (IS_HASWELL(dev
)) {
3883 if (SNB_READ_WM0_LATENCY()) {
3884 dev_priv
->display
.update_wm
= sandybridge_update_wm
;
3885 dev_priv
->display
.update_sprite_wm
= sandybridge_update_sprite_wm
;
3886 dev_priv
->display
.update_linetime_wm
= haswell_update_linetime_wm
;
3888 DRM_DEBUG_KMS("Failed to read display plane latency. "
3890 dev_priv
->display
.update_wm
= NULL
;
3892 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
3894 dev_priv
->display
.update_wm
= NULL
;
3895 } else if (IS_VALLEYVIEW(dev
)) {
3896 dev_priv
->display
.update_wm
= valleyview_update_wm
;
3897 dev_priv
->display
.init_clock_gating
=
3898 valleyview_init_clock_gating
;
3899 } else if (IS_PINEVIEW(dev
)) {
3900 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
3903 dev_priv
->mem_freq
)) {
3904 DRM_INFO("failed to find known CxSR latency "
3905 "(found ddr%s fsb freq %d, mem freq %d), "
3907 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
3908 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
3909 /* Disable CxSR and never update its watermark again */
3910 pineview_disable_cxsr(dev
);
3911 dev_priv
->display
.update_wm
= NULL
;
3913 dev_priv
->display
.update_wm
= pineview_update_wm
;
3914 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
3915 } else if (IS_G4X(dev
)) {
3916 dev_priv
->display
.update_wm
= g4x_update_wm
;
3917 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
3918 } else if (IS_GEN4(dev
)) {
3919 dev_priv
->display
.update_wm
= i965_update_wm
;
3920 if (IS_CRESTLINE(dev
))
3921 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
3922 else if (IS_BROADWATER(dev
))
3923 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
3924 } else if (IS_GEN3(dev
)) {
3925 dev_priv
->display
.update_wm
= i9xx_update_wm
;
3926 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
3927 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
3928 } else if (IS_I865G(dev
)) {
3929 dev_priv
->display
.update_wm
= i830_update_wm
;
3930 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
3931 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
3932 } else if (IS_I85X(dev
)) {
3933 dev_priv
->display
.update_wm
= i9xx_update_wm
;
3934 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
3935 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
3937 dev_priv
->display
.update_wm
= i830_update_wm
;
3938 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
3940 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
3942 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
3946 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private
*dev_priv
)
3948 u32 gt_thread_status_mask
;
3950 if (IS_HASWELL(dev_priv
->dev
))
3951 gt_thread_status_mask
= GEN6_GT_THREAD_STATUS_CORE_MASK_HSW
;
3953 gt_thread_status_mask
= GEN6_GT_THREAD_STATUS_CORE_MASK
;
3955 /* w/a for a sporadic read returning 0 by waiting for the GT
3956 * thread to wake up.
3958 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG
) & gt_thread_status_mask
) == 0, 500))
3959 DRM_ERROR("GT thread status wait timed out\n");
3962 static void __gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
)
3966 if (IS_HASWELL(dev_priv
->dev
))
3967 forcewake_ack
= FORCEWAKE_ACK_HSW
;
3969 forcewake_ack
= FORCEWAKE_ACK
;
3971 if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack
) & 1) == 0, 500))
3972 DRM_ERROR("Force wake wait timed out\n");
3974 I915_WRITE_NOTRACE(FORCEWAKE
, 1);
3975 POSTING_READ(FORCEWAKE
);
3977 if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack
) & 1), 500))
3978 DRM_ERROR("Force wake wait timed out\n");
3980 __gen6_gt_wait_for_thread_c0(dev_priv
);
3983 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private
*dev_priv
)
3987 if (IS_HASWELL(dev_priv
->dev
))
3988 forcewake_ack
= FORCEWAKE_ACK_HSW
;
3990 forcewake_ack
= FORCEWAKE_MT_ACK
;
3992 if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack
) & 1) == 0, 500))
3993 DRM_ERROR("Force wake wait timed out\n");
3995 I915_WRITE_NOTRACE(FORCEWAKE_MT
, _MASKED_BIT_ENABLE(1));
3996 POSTING_READ(FORCEWAKE_MT
);
3998 if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack
) & 1), 500))
3999 DRM_ERROR("Force wake wait timed out\n");
4001 __gen6_gt_wait_for_thread_c0(dev_priv
);
4005 * Generally this is called implicitly by the register read function. However,
4006 * if some sequence requires the GT to not power down then this function should
4007 * be called at the beginning of the sequence followed by a call to
4008 * gen6_gt_force_wake_put() at the end of the sequence.
4010 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
)
4012 unsigned long irqflags
;
4014 spin_lock_irqsave(&dev_priv
->gt_lock
, irqflags
);
4015 if (dev_priv
->forcewake_count
++ == 0)
4016 dev_priv
->gt
.force_wake_get(dev_priv
);
4017 spin_unlock_irqrestore(&dev_priv
->gt_lock
, irqflags
);
4020 void gen6_gt_check_fifodbg(struct drm_i915_private
*dev_priv
)
4023 gtfifodbg
= I915_READ_NOTRACE(GTFIFODBG
);
4024 if (WARN(gtfifodbg
& GT_FIFO_CPU_ERROR_MASK
,
4025 "MMIO read or write has been dropped %x\n", gtfifodbg
))
4026 I915_WRITE_NOTRACE(GTFIFODBG
, GT_FIFO_CPU_ERROR_MASK
);
4029 static void __gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
)
4031 I915_WRITE_NOTRACE(FORCEWAKE
, 0);
4032 POSTING_READ(FORCEWAKE
);
4033 gen6_gt_check_fifodbg(dev_priv
);
4036 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private
*dev_priv
)
4038 I915_WRITE_NOTRACE(FORCEWAKE_MT
, _MASKED_BIT_DISABLE(1));
4039 POSTING_READ(FORCEWAKE_MT
);
4040 gen6_gt_check_fifodbg(dev_priv
);
4044 * see gen6_gt_force_wake_get()
4046 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
)
4048 unsigned long irqflags
;
4050 spin_lock_irqsave(&dev_priv
->gt_lock
, irqflags
);
4051 if (--dev_priv
->forcewake_count
== 0)
4052 dev_priv
->gt
.force_wake_put(dev_priv
);
4053 spin_unlock_irqrestore(&dev_priv
->gt_lock
, irqflags
);
4056 int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
)
4060 if (dev_priv
->gt_fifo_count
< GT_FIFO_NUM_RESERVED_ENTRIES
) {
4062 u32 fifo
= I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES
);
4063 while (fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
&& loop
--) {
4065 fifo
= I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES
);
4067 if (WARN_ON(loop
< 0 && fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
))
4069 dev_priv
->gt_fifo_count
= fifo
;
4071 dev_priv
->gt_fifo_count
--;
4076 static void vlv_force_wake_get(struct drm_i915_private
*dev_priv
)
4078 /* Already awake? */
4079 if ((I915_READ(0x130094) & 0xa1) == 0xa1)
4082 I915_WRITE_NOTRACE(FORCEWAKE_VLV
, 0xffffffff);
4083 POSTING_READ(FORCEWAKE_VLV
);
4085 if (wait_for_atomic_us((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV
) & 1), 500))
4086 DRM_ERROR("Force wake wait timed out\n");
4088 __gen6_gt_wait_for_thread_c0(dev_priv
);
4091 static void vlv_force_wake_put(struct drm_i915_private
*dev_priv
)
4093 I915_WRITE_NOTRACE(FORCEWAKE_VLV
, 0xffff0000);
4094 /* FIXME: confirm VLV behavior with Punit folks */
4095 POSTING_READ(FORCEWAKE_VLV
);
4098 void intel_gt_init(struct drm_device
*dev
)
4100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4102 spin_lock_init(&dev_priv
->gt_lock
);
4104 if (IS_VALLEYVIEW(dev
)) {
4105 dev_priv
->gt
.force_wake_get
= vlv_force_wake_get
;
4106 dev_priv
->gt
.force_wake_put
= vlv_force_wake_put
;
4107 } else if (INTEL_INFO(dev
)->gen
>= 6) {
4108 dev_priv
->gt
.force_wake_get
= __gen6_gt_force_wake_get
;
4109 dev_priv
->gt
.force_wake_put
= __gen6_gt_force_wake_put
;
4111 /* IVB configs may use multi-threaded forcewake */
4112 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
4115 /* A small trick here - if the bios hasn't configured
4116 * MT forcewake, and if the device is in RC6, then
4117 * force_wake_mt_get will not wake the device and the
4118 * ECOBUS read will return zero. Which will be
4119 * (correctly) interpreted by the test below as MT
4120 * forcewake being disabled.
4122 mutex_lock(&dev
->struct_mutex
);
4123 __gen6_gt_force_wake_mt_get(dev_priv
);
4124 ecobus
= I915_READ_NOTRACE(ECOBUS
);
4125 __gen6_gt_force_wake_mt_put(dev_priv
);
4126 mutex_unlock(&dev
->struct_mutex
);
4128 if (ecobus
& FORCEWAKE_MT_ENABLE
) {
4129 DRM_DEBUG_KMS("Using MT version of forcewake\n");
4130 dev_priv
->gt
.force_wake_get
=
4131 __gen6_gt_force_wake_mt_get
;
4132 dev_priv
->gt
.force_wake_put
=
4133 __gen6_gt_force_wake_mt_put
;