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1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include <drm/drm_plane_helper.h>
30 #include "i915_drv.h"
31 #include "intel_drv.h"
32 #include "../../../platform/x86/intel_ips.h"
33 #include <linux/module.h>
34 #include <drm/drm_atomic_helper.h>
35
36 /**
37 * DOC: RC6
38 *
39 * RC6 is a special power stage which allows the GPU to enter an very
40 * low-voltage mode when idle, using down to 0V while at this stage. This
41 * stage is entered automatically when the GPU is idle when RC6 support is
42 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 *
44 * There are different RC6 modes available in Intel GPU, which differentiate
45 * among each other with the latency required to enter and leave RC6 and
46 * voltage consumed by the GPU in different states.
47 *
48 * The combination of the following flags define which states GPU is allowed
49 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
50 * RC6pp is deepest RC6. Their support by hardware varies according to the
51 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
52 * which brings the most power savings; deeper states save more power, but
53 * require higher latency to switch to and wake up.
54 */
55 #define INTEL_RC6_ENABLE (1<<0)
56 #define INTEL_RC6p_ENABLE (1<<1)
57 #define INTEL_RC6pp_ENABLE (1<<2)
58
59 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
60 {
61 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
62 I915_WRITE(CHICKEN_PAR1_1,
63 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
64
65 I915_WRITE(GEN8_CONFIG0,
66 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
67
68 /* WaEnableChickenDCPR:skl,bxt,kbl */
69 I915_WRITE(GEN8_CHICKEN_DCPR_1,
70 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
71
72 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
73 /* WaFbcWakeMemOn:skl,bxt,kbl */
74 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
75 DISP_FBC_WM_DIS |
76 DISP_FBC_MEMORY_WAKE);
77
78 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
79 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
80 ILK_DPFC_DISABLE_DUMMY0);
81 }
82
83 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
84 {
85 gen9_init_clock_gating(dev_priv);
86
87 /* WaDisableSDEUnitClockGating:bxt */
88 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
89 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
90
91 /*
92 * FIXME:
93 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
94 */
95 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
96 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
97
98 /*
99 * Wa: Backlight PWM may stop in the asserted state, causing backlight
100 * to stay fully on.
101 */
102 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
103 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
104 PWM1_GATING_DIS | PWM2_GATING_DIS);
105 }
106
107 static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
108 {
109 u32 tmp;
110
111 tmp = I915_READ(CLKCFG);
112
113 switch (tmp & CLKCFG_FSB_MASK) {
114 case CLKCFG_FSB_533:
115 dev_priv->fsb_freq = 533; /* 133*4 */
116 break;
117 case CLKCFG_FSB_800:
118 dev_priv->fsb_freq = 800; /* 200*4 */
119 break;
120 case CLKCFG_FSB_667:
121 dev_priv->fsb_freq = 667; /* 167*4 */
122 break;
123 case CLKCFG_FSB_400:
124 dev_priv->fsb_freq = 400; /* 100*4 */
125 break;
126 }
127
128 switch (tmp & CLKCFG_MEM_MASK) {
129 case CLKCFG_MEM_533:
130 dev_priv->mem_freq = 533;
131 break;
132 case CLKCFG_MEM_667:
133 dev_priv->mem_freq = 667;
134 break;
135 case CLKCFG_MEM_800:
136 dev_priv->mem_freq = 800;
137 break;
138 }
139
140 /* detect pineview DDR3 setting */
141 tmp = I915_READ(CSHRDDR3CTL);
142 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
143 }
144
145 static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
146 {
147 u16 ddrpll, csipll;
148
149 ddrpll = I915_READ16(DDRMPLL1);
150 csipll = I915_READ16(CSIPLL0);
151
152 switch (ddrpll & 0xff) {
153 case 0xc:
154 dev_priv->mem_freq = 800;
155 break;
156 case 0x10:
157 dev_priv->mem_freq = 1066;
158 break;
159 case 0x14:
160 dev_priv->mem_freq = 1333;
161 break;
162 case 0x18:
163 dev_priv->mem_freq = 1600;
164 break;
165 default:
166 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
167 ddrpll & 0xff);
168 dev_priv->mem_freq = 0;
169 break;
170 }
171
172 dev_priv->ips.r_t = dev_priv->mem_freq;
173
174 switch (csipll & 0x3ff) {
175 case 0x00c:
176 dev_priv->fsb_freq = 3200;
177 break;
178 case 0x00e:
179 dev_priv->fsb_freq = 3733;
180 break;
181 case 0x010:
182 dev_priv->fsb_freq = 4266;
183 break;
184 case 0x012:
185 dev_priv->fsb_freq = 4800;
186 break;
187 case 0x014:
188 dev_priv->fsb_freq = 5333;
189 break;
190 case 0x016:
191 dev_priv->fsb_freq = 5866;
192 break;
193 case 0x018:
194 dev_priv->fsb_freq = 6400;
195 break;
196 default:
197 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
198 csipll & 0x3ff);
199 dev_priv->fsb_freq = 0;
200 break;
201 }
202
203 if (dev_priv->fsb_freq == 3200) {
204 dev_priv->ips.c_m = 0;
205 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
206 dev_priv->ips.c_m = 1;
207 } else {
208 dev_priv->ips.c_m = 2;
209 }
210 }
211
212 static const struct cxsr_latency cxsr_latency_table[] = {
213 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
214 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
215 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
216 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
217 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
218
219 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
220 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
221 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
222 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
223 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
224
225 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
226 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
227 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
228 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
229 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
230
231 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
232 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
233 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
234 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
235 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
236
237 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
238 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
239 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
240 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
241 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
242
243 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
244 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
245 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
246 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
247 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
248 };
249
250 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
251 bool is_ddr3,
252 int fsb,
253 int mem)
254 {
255 const struct cxsr_latency *latency;
256 int i;
257
258 if (fsb == 0 || mem == 0)
259 return NULL;
260
261 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
262 latency = &cxsr_latency_table[i];
263 if (is_desktop == latency->is_desktop &&
264 is_ddr3 == latency->is_ddr3 &&
265 fsb == latency->fsb_freq && mem == latency->mem_freq)
266 return latency;
267 }
268
269 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
270
271 return NULL;
272 }
273
274 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
275 {
276 u32 val;
277
278 mutex_lock(&dev_priv->rps.hw_lock);
279
280 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
281 if (enable)
282 val &= ~FORCE_DDR_HIGH_FREQ;
283 else
284 val |= FORCE_DDR_HIGH_FREQ;
285 val &= ~FORCE_DDR_LOW_FREQ;
286 val |= FORCE_DDR_FREQ_REQ_ACK;
287 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
288
289 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
290 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
291 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
292
293 mutex_unlock(&dev_priv->rps.hw_lock);
294 }
295
296 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
297 {
298 u32 val;
299
300 mutex_lock(&dev_priv->rps.hw_lock);
301
302 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
303 if (enable)
304 val |= DSP_MAXFIFO_PM5_ENABLE;
305 else
306 val &= ~DSP_MAXFIFO_PM5_ENABLE;
307 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
308
309 mutex_unlock(&dev_priv->rps.hw_lock);
310 }
311
312 #define FW_WM(value, plane) \
313 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
314
315 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
316 {
317 u32 val;
318
319 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
320 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
321 POSTING_READ(FW_BLC_SELF_VLV);
322 dev_priv->wm.vlv.cxsr = enable;
323 } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
324 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
325 POSTING_READ(FW_BLC_SELF);
326 } else if (IS_PINEVIEW(dev_priv)) {
327 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
328 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
329 I915_WRITE(DSPFW3, val);
330 POSTING_READ(DSPFW3);
331 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
332 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
333 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
334 I915_WRITE(FW_BLC_SELF, val);
335 POSTING_READ(FW_BLC_SELF);
336 } else if (IS_I915GM(dev_priv)) {
337 /*
338 * FIXME can't find a bit like this for 915G, and
339 * and yet it does have the related watermark in
340 * FW_BLC_SELF. What's going on?
341 */
342 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
343 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
344 I915_WRITE(INSTPM, val);
345 POSTING_READ(INSTPM);
346 } else {
347 return;
348 }
349
350 DRM_DEBUG_KMS("memory self-refresh is %s\n", enableddisabled(enable));
351 }
352
353
354 /*
355 * Latency for FIFO fetches is dependent on several factors:
356 * - memory configuration (speed, channels)
357 * - chipset
358 * - current MCH state
359 * It can be fairly high in some situations, so here we assume a fairly
360 * pessimal value. It's a tradeoff between extra memory fetches (if we
361 * set this value too high, the FIFO will fetch frequently to stay full)
362 * and power consumption (set it too low to save power and we might see
363 * FIFO underruns and display "flicker").
364 *
365 * A value of 5us seems to be a good balance; safe for very low end
366 * platforms but not overly aggressive on lower latency configs.
367 */
368 static const int pessimal_latency_ns = 5000;
369
370 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
371 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
372
373 static int vlv_get_fifo_size(struct drm_i915_private *dev_priv,
374 enum pipe pipe, int plane)
375 {
376 int sprite0_start, sprite1_start, size;
377
378 switch (pipe) {
379 uint32_t dsparb, dsparb2, dsparb3;
380 case PIPE_A:
381 dsparb = I915_READ(DSPARB);
382 dsparb2 = I915_READ(DSPARB2);
383 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
384 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
385 break;
386 case PIPE_B:
387 dsparb = I915_READ(DSPARB);
388 dsparb2 = I915_READ(DSPARB2);
389 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
390 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
391 break;
392 case PIPE_C:
393 dsparb2 = I915_READ(DSPARB2);
394 dsparb3 = I915_READ(DSPARB3);
395 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
396 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
397 break;
398 default:
399 return 0;
400 }
401
402 switch (plane) {
403 case 0:
404 size = sprite0_start;
405 break;
406 case 1:
407 size = sprite1_start - sprite0_start;
408 break;
409 case 2:
410 size = 512 - 1 - sprite1_start;
411 break;
412 default:
413 return 0;
414 }
415
416 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
417 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
418 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
419 size);
420
421 return size;
422 }
423
424 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
425 {
426 uint32_t dsparb = I915_READ(DSPARB);
427 int size;
428
429 size = dsparb & 0x7f;
430 if (plane)
431 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
432
433 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
434 plane ? "B" : "A", size);
435
436 return size;
437 }
438
439 static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
440 {
441 uint32_t dsparb = I915_READ(DSPARB);
442 int size;
443
444 size = dsparb & 0x1ff;
445 if (plane)
446 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
447 size >>= 1; /* Convert to cachelines */
448
449 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
450 plane ? "B" : "A", size);
451
452 return size;
453 }
454
455 static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
456 {
457 uint32_t dsparb = I915_READ(DSPARB);
458 int size;
459
460 size = dsparb & 0x7f;
461 size >>= 2; /* Convert to cachelines */
462
463 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
464 plane ? "B" : "A",
465 size);
466
467 return size;
468 }
469
470 /* Pineview has different values for various configs */
471 static const struct intel_watermark_params pineview_display_wm = {
472 .fifo_size = PINEVIEW_DISPLAY_FIFO,
473 .max_wm = PINEVIEW_MAX_WM,
474 .default_wm = PINEVIEW_DFT_WM,
475 .guard_size = PINEVIEW_GUARD_WM,
476 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
477 };
478 static const struct intel_watermark_params pineview_display_hplloff_wm = {
479 .fifo_size = PINEVIEW_DISPLAY_FIFO,
480 .max_wm = PINEVIEW_MAX_WM,
481 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
482 .guard_size = PINEVIEW_GUARD_WM,
483 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
484 };
485 static const struct intel_watermark_params pineview_cursor_wm = {
486 .fifo_size = PINEVIEW_CURSOR_FIFO,
487 .max_wm = PINEVIEW_CURSOR_MAX_WM,
488 .default_wm = PINEVIEW_CURSOR_DFT_WM,
489 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
490 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
491 };
492 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
493 .fifo_size = PINEVIEW_CURSOR_FIFO,
494 .max_wm = PINEVIEW_CURSOR_MAX_WM,
495 .default_wm = PINEVIEW_CURSOR_DFT_WM,
496 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
497 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
498 };
499 static const struct intel_watermark_params g4x_wm_info = {
500 .fifo_size = G4X_FIFO_SIZE,
501 .max_wm = G4X_MAX_WM,
502 .default_wm = G4X_MAX_WM,
503 .guard_size = 2,
504 .cacheline_size = G4X_FIFO_LINE_SIZE,
505 };
506 static const struct intel_watermark_params g4x_cursor_wm_info = {
507 .fifo_size = I965_CURSOR_FIFO,
508 .max_wm = I965_CURSOR_MAX_WM,
509 .default_wm = I965_CURSOR_DFT_WM,
510 .guard_size = 2,
511 .cacheline_size = G4X_FIFO_LINE_SIZE,
512 };
513 static const struct intel_watermark_params i965_cursor_wm_info = {
514 .fifo_size = I965_CURSOR_FIFO,
515 .max_wm = I965_CURSOR_MAX_WM,
516 .default_wm = I965_CURSOR_DFT_WM,
517 .guard_size = 2,
518 .cacheline_size = I915_FIFO_LINE_SIZE,
519 };
520 static const struct intel_watermark_params i945_wm_info = {
521 .fifo_size = I945_FIFO_SIZE,
522 .max_wm = I915_MAX_WM,
523 .default_wm = 1,
524 .guard_size = 2,
525 .cacheline_size = I915_FIFO_LINE_SIZE,
526 };
527 static const struct intel_watermark_params i915_wm_info = {
528 .fifo_size = I915_FIFO_SIZE,
529 .max_wm = I915_MAX_WM,
530 .default_wm = 1,
531 .guard_size = 2,
532 .cacheline_size = I915_FIFO_LINE_SIZE,
533 };
534 static const struct intel_watermark_params i830_a_wm_info = {
535 .fifo_size = I855GM_FIFO_SIZE,
536 .max_wm = I915_MAX_WM,
537 .default_wm = 1,
538 .guard_size = 2,
539 .cacheline_size = I830_FIFO_LINE_SIZE,
540 };
541 static const struct intel_watermark_params i830_bc_wm_info = {
542 .fifo_size = I855GM_FIFO_SIZE,
543 .max_wm = I915_MAX_WM/2,
544 .default_wm = 1,
545 .guard_size = 2,
546 .cacheline_size = I830_FIFO_LINE_SIZE,
547 };
548 static const struct intel_watermark_params i845_wm_info = {
549 .fifo_size = I830_FIFO_SIZE,
550 .max_wm = I915_MAX_WM,
551 .default_wm = 1,
552 .guard_size = 2,
553 .cacheline_size = I830_FIFO_LINE_SIZE,
554 };
555
556 /**
557 * intel_calculate_wm - calculate watermark level
558 * @clock_in_khz: pixel clock
559 * @wm: chip FIFO params
560 * @cpp: bytes per pixel
561 * @latency_ns: memory latency for the platform
562 *
563 * Calculate the watermark level (the level at which the display plane will
564 * start fetching from memory again). Each chip has a different display
565 * FIFO size and allocation, so the caller needs to figure that out and pass
566 * in the correct intel_watermark_params structure.
567 *
568 * As the pixel clock runs, the FIFO will be drained at a rate that depends
569 * on the pixel size. When it reaches the watermark level, it'll start
570 * fetching FIFO line sized based chunks from memory until the FIFO fills
571 * past the watermark point. If the FIFO drains completely, a FIFO underrun
572 * will occur, and a display engine hang could result.
573 */
574 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
575 const struct intel_watermark_params *wm,
576 int fifo_size, int cpp,
577 unsigned long latency_ns)
578 {
579 long entries_required, wm_size;
580
581 /*
582 * Note: we need to make sure we don't overflow for various clock &
583 * latency values.
584 * clocks go from a few thousand to several hundred thousand.
585 * latency is usually a few thousand
586 */
587 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
588 1000;
589 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
590
591 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
592
593 wm_size = fifo_size - (entries_required + wm->guard_size);
594
595 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
596
597 /* Don't promote wm_size to unsigned... */
598 if (wm_size > (long)wm->max_wm)
599 wm_size = wm->max_wm;
600 if (wm_size <= 0)
601 wm_size = wm->default_wm;
602
603 /*
604 * Bspec seems to indicate that the value shouldn't be lower than
605 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
606 * Lets go for 8 which is the burst size since certain platforms
607 * already use a hardcoded 8 (which is what the spec says should be
608 * done).
609 */
610 if (wm_size <= 8)
611 wm_size = 8;
612
613 return wm_size;
614 }
615
616 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
617 {
618 struct intel_crtc *crtc, *enabled = NULL;
619
620 for_each_intel_crtc(&dev_priv->drm, crtc) {
621 if (intel_crtc_active(crtc)) {
622 if (enabled)
623 return NULL;
624 enabled = crtc;
625 }
626 }
627
628 return enabled;
629 }
630
631 static void pineview_update_wm(struct intel_crtc *unused_crtc)
632 {
633 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
634 struct intel_crtc *crtc;
635 const struct cxsr_latency *latency;
636 u32 reg;
637 unsigned long wm;
638
639 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
640 dev_priv->is_ddr3,
641 dev_priv->fsb_freq,
642 dev_priv->mem_freq);
643 if (!latency) {
644 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
645 intel_set_memory_cxsr(dev_priv, false);
646 return;
647 }
648
649 crtc = single_enabled_crtc(dev_priv);
650 if (crtc) {
651 const struct drm_display_mode *adjusted_mode =
652 &crtc->config->base.adjusted_mode;
653 const struct drm_framebuffer *fb =
654 crtc->base.primary->state->fb;
655 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
656 int clock = adjusted_mode->crtc_clock;
657
658 /* Display SR */
659 wm = intel_calculate_wm(clock, &pineview_display_wm,
660 pineview_display_wm.fifo_size,
661 cpp, latency->display_sr);
662 reg = I915_READ(DSPFW1);
663 reg &= ~DSPFW_SR_MASK;
664 reg |= FW_WM(wm, SR);
665 I915_WRITE(DSPFW1, reg);
666 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
667
668 /* cursor SR */
669 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
670 pineview_display_wm.fifo_size,
671 cpp, latency->cursor_sr);
672 reg = I915_READ(DSPFW3);
673 reg &= ~DSPFW_CURSOR_SR_MASK;
674 reg |= FW_WM(wm, CURSOR_SR);
675 I915_WRITE(DSPFW3, reg);
676
677 /* Display HPLL off SR */
678 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
679 pineview_display_hplloff_wm.fifo_size,
680 cpp, latency->display_hpll_disable);
681 reg = I915_READ(DSPFW3);
682 reg &= ~DSPFW_HPLL_SR_MASK;
683 reg |= FW_WM(wm, HPLL_SR);
684 I915_WRITE(DSPFW3, reg);
685
686 /* cursor HPLL off SR */
687 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
688 pineview_display_hplloff_wm.fifo_size,
689 cpp, latency->cursor_hpll_disable);
690 reg = I915_READ(DSPFW3);
691 reg &= ~DSPFW_HPLL_CURSOR_MASK;
692 reg |= FW_WM(wm, HPLL_CURSOR);
693 I915_WRITE(DSPFW3, reg);
694 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
695
696 intel_set_memory_cxsr(dev_priv, true);
697 } else {
698 intel_set_memory_cxsr(dev_priv, false);
699 }
700 }
701
702 static bool g4x_compute_wm0(struct drm_i915_private *dev_priv,
703 int plane,
704 const struct intel_watermark_params *display,
705 int display_latency_ns,
706 const struct intel_watermark_params *cursor,
707 int cursor_latency_ns,
708 int *plane_wm,
709 int *cursor_wm)
710 {
711 struct intel_crtc *crtc;
712 const struct drm_display_mode *adjusted_mode;
713 const struct drm_framebuffer *fb;
714 int htotal, hdisplay, clock, cpp;
715 int line_time_us, line_count;
716 int entries, tlb_miss;
717
718 crtc = intel_get_crtc_for_plane(dev_priv, plane);
719 if (!intel_crtc_active(crtc)) {
720 *cursor_wm = cursor->guard_size;
721 *plane_wm = display->guard_size;
722 return false;
723 }
724
725 adjusted_mode = &crtc->config->base.adjusted_mode;
726 fb = crtc->base.primary->state->fb;
727 clock = adjusted_mode->crtc_clock;
728 htotal = adjusted_mode->crtc_htotal;
729 hdisplay = crtc->config->pipe_src_w;
730 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
731
732 /* Use the small buffer method to calculate plane watermark */
733 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
734 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
735 if (tlb_miss > 0)
736 entries += tlb_miss;
737 entries = DIV_ROUND_UP(entries, display->cacheline_size);
738 *plane_wm = entries + display->guard_size;
739 if (*plane_wm > (int)display->max_wm)
740 *plane_wm = display->max_wm;
741
742 /* Use the large buffer method to calculate cursor watermark */
743 line_time_us = max(htotal * 1000 / clock, 1);
744 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
745 entries = line_count * crtc->base.cursor->state->crtc_w * cpp;
746 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
747 if (tlb_miss > 0)
748 entries += tlb_miss;
749 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
750 *cursor_wm = entries + cursor->guard_size;
751 if (*cursor_wm > (int)cursor->max_wm)
752 *cursor_wm = (int)cursor->max_wm;
753
754 return true;
755 }
756
757 /*
758 * Check the wm result.
759 *
760 * If any calculated watermark values is larger than the maximum value that
761 * can be programmed into the associated watermark register, that watermark
762 * must be disabled.
763 */
764 static bool g4x_check_srwm(struct drm_i915_private *dev_priv,
765 int display_wm, int cursor_wm,
766 const struct intel_watermark_params *display,
767 const struct intel_watermark_params *cursor)
768 {
769 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
770 display_wm, cursor_wm);
771
772 if (display_wm > display->max_wm) {
773 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
774 display_wm, display->max_wm);
775 return false;
776 }
777
778 if (cursor_wm > cursor->max_wm) {
779 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
780 cursor_wm, cursor->max_wm);
781 return false;
782 }
783
784 if (!(display_wm || cursor_wm)) {
785 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
786 return false;
787 }
788
789 return true;
790 }
791
792 static bool g4x_compute_srwm(struct drm_i915_private *dev_priv,
793 int plane,
794 int latency_ns,
795 const struct intel_watermark_params *display,
796 const struct intel_watermark_params *cursor,
797 int *display_wm, int *cursor_wm)
798 {
799 struct intel_crtc *crtc;
800 const struct drm_display_mode *adjusted_mode;
801 const struct drm_framebuffer *fb;
802 int hdisplay, htotal, cpp, clock;
803 unsigned long line_time_us;
804 int line_count, line_size;
805 int small, large;
806 int entries;
807
808 if (!latency_ns) {
809 *display_wm = *cursor_wm = 0;
810 return false;
811 }
812
813 crtc = intel_get_crtc_for_plane(dev_priv, plane);
814 adjusted_mode = &crtc->config->base.adjusted_mode;
815 fb = crtc->base.primary->state->fb;
816 clock = adjusted_mode->crtc_clock;
817 htotal = adjusted_mode->crtc_htotal;
818 hdisplay = crtc->config->pipe_src_w;
819 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
820
821 line_time_us = max(htotal * 1000 / clock, 1);
822 line_count = (latency_ns / line_time_us + 1000) / 1000;
823 line_size = hdisplay * cpp;
824
825 /* Use the minimum of the small and large buffer method for primary */
826 small = ((clock * cpp / 1000) * latency_ns) / 1000;
827 large = line_count * line_size;
828
829 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
830 *display_wm = entries + display->guard_size;
831
832 /* calculate the self-refresh watermark for display cursor */
833 entries = line_count * cpp * crtc->base.cursor->state->crtc_w;
834 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
835 *cursor_wm = entries + cursor->guard_size;
836
837 return g4x_check_srwm(dev_priv,
838 *display_wm, *cursor_wm,
839 display, cursor);
840 }
841
842 #define FW_WM_VLV(value, plane) \
843 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
844
845 static void vlv_write_wm_values(struct intel_crtc *crtc,
846 const struct vlv_wm_values *wm)
847 {
848 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
849 enum pipe pipe = crtc->pipe;
850
851 I915_WRITE(VLV_DDL(pipe),
852 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
853 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
854 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
855 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
856
857 I915_WRITE(DSPFW1,
858 FW_WM(wm->sr.plane, SR) |
859 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
860 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
861 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
862 I915_WRITE(DSPFW2,
863 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
864 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
865 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
866 I915_WRITE(DSPFW3,
867 FW_WM(wm->sr.cursor, CURSOR_SR));
868
869 if (IS_CHERRYVIEW(dev_priv)) {
870 I915_WRITE(DSPFW7_CHV,
871 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
872 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
873 I915_WRITE(DSPFW8_CHV,
874 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
875 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
876 I915_WRITE(DSPFW9_CHV,
877 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
878 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
879 I915_WRITE(DSPHOWM,
880 FW_WM(wm->sr.plane >> 9, SR_HI) |
881 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
882 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
883 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
884 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
885 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
886 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
887 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
888 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
889 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
890 } else {
891 I915_WRITE(DSPFW7,
892 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
893 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
894 I915_WRITE(DSPHOWM,
895 FW_WM(wm->sr.plane >> 9, SR_HI) |
896 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
897 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
898 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
899 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
900 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
901 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
902 }
903
904 /* zero (unused) WM1 watermarks */
905 I915_WRITE(DSPFW4, 0);
906 I915_WRITE(DSPFW5, 0);
907 I915_WRITE(DSPFW6, 0);
908 I915_WRITE(DSPHOWM1, 0);
909
910 POSTING_READ(DSPFW1);
911 }
912
913 #undef FW_WM_VLV
914
915 enum vlv_wm_level {
916 VLV_WM_LEVEL_PM2,
917 VLV_WM_LEVEL_PM5,
918 VLV_WM_LEVEL_DDR_DVFS,
919 };
920
921 /* latency must be in 0.1us units. */
922 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
923 unsigned int pipe_htotal,
924 unsigned int horiz_pixels,
925 unsigned int cpp,
926 unsigned int latency)
927 {
928 unsigned int ret;
929
930 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
931 ret = (ret + 1) * horiz_pixels * cpp;
932 ret = DIV_ROUND_UP(ret, 64);
933
934 return ret;
935 }
936
937 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
938 {
939 /* all latencies in usec */
940 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
941
942 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
943
944 if (IS_CHERRYVIEW(dev_priv)) {
945 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
946 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
947
948 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
949 }
950 }
951
952 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
953 struct intel_crtc *crtc,
954 const struct intel_plane_state *state,
955 int level)
956 {
957 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
958 int clock, htotal, cpp, width, wm;
959
960 if (dev_priv->wm.pri_latency[level] == 0)
961 return USHRT_MAX;
962
963 if (!state->base.visible)
964 return 0;
965
966 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
967 clock = crtc->config->base.adjusted_mode.crtc_clock;
968 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
969 width = crtc->config->pipe_src_w;
970 if (WARN_ON(htotal == 0))
971 htotal = 1;
972
973 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
974 /*
975 * FIXME the formula gives values that are
976 * too big for the cursor FIFO, and hence we
977 * would never be able to use cursors. For
978 * now just hardcode the watermark.
979 */
980 wm = 63;
981 } else {
982 wm = vlv_wm_method2(clock, htotal, width, cpp,
983 dev_priv->wm.pri_latency[level] * 10);
984 }
985
986 return min_t(int, wm, USHRT_MAX);
987 }
988
989 static void vlv_compute_fifo(struct intel_crtc *crtc)
990 {
991 struct drm_device *dev = crtc->base.dev;
992 struct vlv_wm_state *wm_state = &crtc->wm_state;
993 struct intel_plane *plane;
994 unsigned int total_rate = 0;
995 const int fifo_size = 512 - 1;
996 int fifo_extra, fifo_left = fifo_size;
997
998 for_each_intel_plane_on_crtc(dev, crtc, plane) {
999 struct intel_plane_state *state =
1000 to_intel_plane_state(plane->base.state);
1001
1002 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1003 continue;
1004
1005 if (state->base.visible) {
1006 wm_state->num_active_planes++;
1007 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1008 }
1009 }
1010
1011 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1012 struct intel_plane_state *state =
1013 to_intel_plane_state(plane->base.state);
1014 unsigned int rate;
1015
1016 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1017 plane->wm.fifo_size = 63;
1018 continue;
1019 }
1020
1021 if (!state->base.visible) {
1022 plane->wm.fifo_size = 0;
1023 continue;
1024 }
1025
1026 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1027 plane->wm.fifo_size = fifo_size * rate / total_rate;
1028 fifo_left -= plane->wm.fifo_size;
1029 }
1030
1031 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1032
1033 /* spread the remainder evenly */
1034 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1035 int plane_extra;
1036
1037 if (fifo_left == 0)
1038 break;
1039
1040 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1041 continue;
1042
1043 /* give it all to the first plane if none are active */
1044 if (plane->wm.fifo_size == 0 &&
1045 wm_state->num_active_planes)
1046 continue;
1047
1048 plane_extra = min(fifo_extra, fifo_left);
1049 plane->wm.fifo_size += plane_extra;
1050 fifo_left -= plane_extra;
1051 }
1052
1053 WARN_ON(fifo_left != 0);
1054 }
1055
1056 static void vlv_invert_wms(struct intel_crtc *crtc)
1057 {
1058 struct vlv_wm_state *wm_state = &crtc->wm_state;
1059 int level;
1060
1061 for (level = 0; level < wm_state->num_levels; level++) {
1062 struct drm_device *dev = crtc->base.dev;
1063 const int sr_fifo_size =
1064 INTEL_INFO(to_i915(dev))->num_pipes * 512 - 1;
1065 struct intel_plane *plane;
1066
1067 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1068 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1069
1070 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1071 switch (plane->base.type) {
1072 int sprite;
1073 case DRM_PLANE_TYPE_CURSOR:
1074 wm_state->wm[level].cursor = plane->wm.fifo_size -
1075 wm_state->wm[level].cursor;
1076 break;
1077 case DRM_PLANE_TYPE_PRIMARY:
1078 wm_state->wm[level].primary = plane->wm.fifo_size -
1079 wm_state->wm[level].primary;
1080 break;
1081 case DRM_PLANE_TYPE_OVERLAY:
1082 sprite = plane->plane;
1083 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1084 wm_state->wm[level].sprite[sprite];
1085 break;
1086 }
1087 }
1088 }
1089 }
1090
1091 static void vlv_compute_wm(struct intel_crtc *crtc)
1092 {
1093 struct drm_device *dev = crtc->base.dev;
1094 struct drm_i915_private *dev_priv = to_i915(dev);
1095 struct vlv_wm_state *wm_state = &crtc->wm_state;
1096 struct intel_plane *plane;
1097 int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1098 int level;
1099
1100 memset(wm_state, 0, sizeof(*wm_state));
1101
1102 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1103 wm_state->num_levels = dev_priv->wm.max_level + 1;
1104
1105 wm_state->num_active_planes = 0;
1106
1107 vlv_compute_fifo(crtc);
1108
1109 if (wm_state->num_active_planes != 1)
1110 wm_state->cxsr = false;
1111
1112 if (wm_state->cxsr) {
1113 for (level = 0; level < wm_state->num_levels; level++) {
1114 wm_state->sr[level].plane = sr_fifo_size;
1115 wm_state->sr[level].cursor = 63;
1116 }
1117 }
1118
1119 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1120 struct intel_plane_state *state =
1121 to_intel_plane_state(plane->base.state);
1122
1123 if (!state->base.visible)
1124 continue;
1125
1126 /* normal watermarks */
1127 for (level = 0; level < wm_state->num_levels; level++) {
1128 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1129 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1130
1131 /* hack */
1132 if (WARN_ON(level == 0 && wm > max_wm))
1133 wm = max_wm;
1134
1135 if (wm > plane->wm.fifo_size)
1136 break;
1137
1138 switch (plane->base.type) {
1139 int sprite;
1140 case DRM_PLANE_TYPE_CURSOR:
1141 wm_state->wm[level].cursor = wm;
1142 break;
1143 case DRM_PLANE_TYPE_PRIMARY:
1144 wm_state->wm[level].primary = wm;
1145 break;
1146 case DRM_PLANE_TYPE_OVERLAY:
1147 sprite = plane->plane;
1148 wm_state->wm[level].sprite[sprite] = wm;
1149 break;
1150 }
1151 }
1152
1153 wm_state->num_levels = level;
1154
1155 if (!wm_state->cxsr)
1156 continue;
1157
1158 /* maxfifo watermarks */
1159 switch (plane->base.type) {
1160 int sprite, level;
1161 case DRM_PLANE_TYPE_CURSOR:
1162 for (level = 0; level < wm_state->num_levels; level++)
1163 wm_state->sr[level].cursor =
1164 wm_state->wm[level].cursor;
1165 break;
1166 case DRM_PLANE_TYPE_PRIMARY:
1167 for (level = 0; level < wm_state->num_levels; level++)
1168 wm_state->sr[level].plane =
1169 min(wm_state->sr[level].plane,
1170 wm_state->wm[level].primary);
1171 break;
1172 case DRM_PLANE_TYPE_OVERLAY:
1173 sprite = plane->plane;
1174 for (level = 0; level < wm_state->num_levels; level++)
1175 wm_state->sr[level].plane =
1176 min(wm_state->sr[level].plane,
1177 wm_state->wm[level].sprite[sprite]);
1178 break;
1179 }
1180 }
1181
1182 /* clear any (partially) filled invalid levels */
1183 for (level = wm_state->num_levels; level < dev_priv->wm.max_level + 1; level++) {
1184 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1185 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1186 }
1187
1188 vlv_invert_wms(crtc);
1189 }
1190
1191 #define VLV_FIFO(plane, value) \
1192 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1193
1194 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1195 {
1196 struct drm_device *dev = crtc->base.dev;
1197 struct drm_i915_private *dev_priv = to_i915(dev);
1198 struct intel_plane *plane;
1199 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1200
1201 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1202 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1203 WARN_ON(plane->wm.fifo_size != 63);
1204 continue;
1205 }
1206
1207 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1208 sprite0_start = plane->wm.fifo_size;
1209 else if (plane->plane == 0)
1210 sprite1_start = sprite0_start + plane->wm.fifo_size;
1211 else
1212 fifo_size = sprite1_start + plane->wm.fifo_size;
1213 }
1214
1215 WARN_ON(fifo_size != 512 - 1);
1216
1217 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1218 pipe_name(crtc->pipe), sprite0_start,
1219 sprite1_start, fifo_size);
1220
1221 switch (crtc->pipe) {
1222 uint32_t dsparb, dsparb2, dsparb3;
1223 case PIPE_A:
1224 dsparb = I915_READ(DSPARB);
1225 dsparb2 = I915_READ(DSPARB2);
1226
1227 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1228 VLV_FIFO(SPRITEB, 0xff));
1229 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1230 VLV_FIFO(SPRITEB, sprite1_start));
1231
1232 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1233 VLV_FIFO(SPRITEB_HI, 0x1));
1234 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1235 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1236
1237 I915_WRITE(DSPARB, dsparb);
1238 I915_WRITE(DSPARB2, dsparb2);
1239 break;
1240 case PIPE_B:
1241 dsparb = I915_READ(DSPARB);
1242 dsparb2 = I915_READ(DSPARB2);
1243
1244 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1245 VLV_FIFO(SPRITED, 0xff));
1246 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1247 VLV_FIFO(SPRITED, sprite1_start));
1248
1249 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1250 VLV_FIFO(SPRITED_HI, 0xff));
1251 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1252 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1253
1254 I915_WRITE(DSPARB, dsparb);
1255 I915_WRITE(DSPARB2, dsparb2);
1256 break;
1257 case PIPE_C:
1258 dsparb3 = I915_READ(DSPARB3);
1259 dsparb2 = I915_READ(DSPARB2);
1260
1261 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1262 VLV_FIFO(SPRITEF, 0xff));
1263 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1264 VLV_FIFO(SPRITEF, sprite1_start));
1265
1266 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1267 VLV_FIFO(SPRITEF_HI, 0xff));
1268 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1269 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1270
1271 I915_WRITE(DSPARB3, dsparb3);
1272 I915_WRITE(DSPARB2, dsparb2);
1273 break;
1274 default:
1275 break;
1276 }
1277 }
1278
1279 #undef VLV_FIFO
1280
1281 static void vlv_merge_wm(struct drm_device *dev,
1282 struct vlv_wm_values *wm)
1283 {
1284 struct intel_crtc *crtc;
1285 int num_active_crtcs = 0;
1286
1287 wm->level = to_i915(dev)->wm.max_level;
1288 wm->cxsr = true;
1289
1290 for_each_intel_crtc(dev, crtc) {
1291 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1292
1293 if (!crtc->active)
1294 continue;
1295
1296 if (!wm_state->cxsr)
1297 wm->cxsr = false;
1298
1299 num_active_crtcs++;
1300 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1301 }
1302
1303 if (num_active_crtcs != 1)
1304 wm->cxsr = false;
1305
1306 if (num_active_crtcs > 1)
1307 wm->level = VLV_WM_LEVEL_PM2;
1308
1309 for_each_intel_crtc(dev, crtc) {
1310 struct vlv_wm_state *wm_state = &crtc->wm_state;
1311 enum pipe pipe = crtc->pipe;
1312
1313 if (!crtc->active)
1314 continue;
1315
1316 wm->pipe[pipe] = wm_state->wm[wm->level];
1317 if (wm->cxsr)
1318 wm->sr = wm_state->sr[wm->level];
1319
1320 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1321 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1322 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1323 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1324 }
1325 }
1326
1327 static void vlv_update_wm(struct intel_crtc *crtc)
1328 {
1329 struct drm_device *dev = crtc->base.dev;
1330 struct drm_i915_private *dev_priv = to_i915(dev);
1331 enum pipe pipe = crtc->pipe;
1332 struct vlv_wm_values wm = {};
1333
1334 vlv_compute_wm(crtc);
1335 vlv_merge_wm(dev, &wm);
1336
1337 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1338 /* FIXME should be part of crtc atomic commit */
1339 vlv_pipe_set_fifo_size(crtc);
1340 return;
1341 }
1342
1343 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1344 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1345 chv_set_memory_dvfs(dev_priv, false);
1346
1347 if (wm.level < VLV_WM_LEVEL_PM5 &&
1348 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1349 chv_set_memory_pm5(dev_priv, false);
1350
1351 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1352 intel_set_memory_cxsr(dev_priv, false);
1353
1354 /* FIXME should be part of crtc atomic commit */
1355 vlv_pipe_set_fifo_size(crtc);
1356
1357 vlv_write_wm_values(crtc, &wm);
1358
1359 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1360 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1361 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1362 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1363 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1364
1365 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1366 intel_set_memory_cxsr(dev_priv, true);
1367
1368 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1369 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1370 chv_set_memory_pm5(dev_priv, true);
1371
1372 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1373 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1374 chv_set_memory_dvfs(dev_priv, true);
1375
1376 dev_priv->wm.vlv = wm;
1377 }
1378
1379 #define single_plane_enabled(mask) is_power_of_2(mask)
1380
1381 static void g4x_update_wm(struct intel_crtc *crtc)
1382 {
1383 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1384 static const int sr_latency_ns = 12000;
1385 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1386 int plane_sr, cursor_sr;
1387 unsigned int enabled = 0;
1388 bool cxsr_enabled;
1389
1390 if (g4x_compute_wm0(dev_priv, PIPE_A,
1391 &g4x_wm_info, pessimal_latency_ns,
1392 &g4x_cursor_wm_info, pessimal_latency_ns,
1393 &planea_wm, &cursora_wm))
1394 enabled |= 1 << PIPE_A;
1395
1396 if (g4x_compute_wm0(dev_priv, PIPE_B,
1397 &g4x_wm_info, pessimal_latency_ns,
1398 &g4x_cursor_wm_info, pessimal_latency_ns,
1399 &planeb_wm, &cursorb_wm))
1400 enabled |= 1 << PIPE_B;
1401
1402 if (single_plane_enabled(enabled) &&
1403 g4x_compute_srwm(dev_priv, ffs(enabled) - 1,
1404 sr_latency_ns,
1405 &g4x_wm_info,
1406 &g4x_cursor_wm_info,
1407 &plane_sr, &cursor_sr)) {
1408 cxsr_enabled = true;
1409 } else {
1410 cxsr_enabled = false;
1411 intel_set_memory_cxsr(dev_priv, false);
1412 plane_sr = cursor_sr = 0;
1413 }
1414
1415 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1416 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1417 planea_wm, cursora_wm,
1418 planeb_wm, cursorb_wm,
1419 plane_sr, cursor_sr);
1420
1421 I915_WRITE(DSPFW1,
1422 FW_WM(plane_sr, SR) |
1423 FW_WM(cursorb_wm, CURSORB) |
1424 FW_WM(planeb_wm, PLANEB) |
1425 FW_WM(planea_wm, PLANEA));
1426 I915_WRITE(DSPFW2,
1427 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1428 FW_WM(cursora_wm, CURSORA));
1429 /* HPLL off in SR has some issues on G4x... disable it */
1430 I915_WRITE(DSPFW3,
1431 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1432 FW_WM(cursor_sr, CURSOR_SR));
1433
1434 if (cxsr_enabled)
1435 intel_set_memory_cxsr(dev_priv, true);
1436 }
1437
1438 static void i965_update_wm(struct intel_crtc *unused_crtc)
1439 {
1440 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1441 struct intel_crtc *crtc;
1442 int srwm = 1;
1443 int cursor_sr = 16;
1444 bool cxsr_enabled;
1445
1446 /* Calc sr entries for one plane configs */
1447 crtc = single_enabled_crtc(dev_priv);
1448 if (crtc) {
1449 /* self-refresh has much higher latency */
1450 static const int sr_latency_ns = 12000;
1451 const struct drm_display_mode *adjusted_mode =
1452 &crtc->config->base.adjusted_mode;
1453 const struct drm_framebuffer *fb =
1454 crtc->base.primary->state->fb;
1455 int clock = adjusted_mode->crtc_clock;
1456 int htotal = adjusted_mode->crtc_htotal;
1457 int hdisplay = crtc->config->pipe_src_w;
1458 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1459 unsigned long line_time_us;
1460 int entries;
1461
1462 line_time_us = max(htotal * 1000 / clock, 1);
1463
1464 /* Use ns/us then divide to preserve precision */
1465 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1466 cpp * hdisplay;
1467 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1468 srwm = I965_FIFO_SIZE - entries;
1469 if (srwm < 0)
1470 srwm = 1;
1471 srwm &= 0x1ff;
1472 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1473 entries, srwm);
1474
1475 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1476 cpp * crtc->base.cursor->state->crtc_w;
1477 entries = DIV_ROUND_UP(entries,
1478 i965_cursor_wm_info.cacheline_size);
1479 cursor_sr = i965_cursor_wm_info.fifo_size -
1480 (entries + i965_cursor_wm_info.guard_size);
1481
1482 if (cursor_sr > i965_cursor_wm_info.max_wm)
1483 cursor_sr = i965_cursor_wm_info.max_wm;
1484
1485 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1486 "cursor %d\n", srwm, cursor_sr);
1487
1488 cxsr_enabled = true;
1489 } else {
1490 cxsr_enabled = false;
1491 /* Turn off self refresh if both pipes are enabled */
1492 intel_set_memory_cxsr(dev_priv, false);
1493 }
1494
1495 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1496 srwm);
1497
1498 /* 965 has limitations... */
1499 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1500 FW_WM(8, CURSORB) |
1501 FW_WM(8, PLANEB) |
1502 FW_WM(8, PLANEA));
1503 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1504 FW_WM(8, PLANEC_OLD));
1505 /* update cursor SR watermark */
1506 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1507
1508 if (cxsr_enabled)
1509 intel_set_memory_cxsr(dev_priv, true);
1510 }
1511
1512 #undef FW_WM
1513
1514 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
1515 {
1516 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1517 const struct intel_watermark_params *wm_info;
1518 uint32_t fwater_lo;
1519 uint32_t fwater_hi;
1520 int cwm, srwm = 1;
1521 int fifo_size;
1522 int planea_wm, planeb_wm;
1523 struct intel_crtc *crtc, *enabled = NULL;
1524
1525 if (IS_I945GM(dev_priv))
1526 wm_info = &i945_wm_info;
1527 else if (!IS_GEN2(dev_priv))
1528 wm_info = &i915_wm_info;
1529 else
1530 wm_info = &i830_a_wm_info;
1531
1532 fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
1533 crtc = intel_get_crtc_for_plane(dev_priv, 0);
1534 if (intel_crtc_active(crtc)) {
1535 const struct drm_display_mode *adjusted_mode =
1536 &crtc->config->base.adjusted_mode;
1537 const struct drm_framebuffer *fb =
1538 crtc->base.primary->state->fb;
1539 int cpp;
1540
1541 if (IS_GEN2(dev_priv))
1542 cpp = 4;
1543 else
1544 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1545
1546 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1547 wm_info, fifo_size, cpp,
1548 pessimal_latency_ns);
1549 enabled = crtc;
1550 } else {
1551 planea_wm = fifo_size - wm_info->guard_size;
1552 if (planea_wm > (long)wm_info->max_wm)
1553 planea_wm = wm_info->max_wm;
1554 }
1555
1556 if (IS_GEN2(dev_priv))
1557 wm_info = &i830_bc_wm_info;
1558
1559 fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
1560 crtc = intel_get_crtc_for_plane(dev_priv, 1);
1561 if (intel_crtc_active(crtc)) {
1562 const struct drm_display_mode *adjusted_mode =
1563 &crtc->config->base.adjusted_mode;
1564 const struct drm_framebuffer *fb =
1565 crtc->base.primary->state->fb;
1566 int cpp;
1567
1568 if (IS_GEN2(dev_priv))
1569 cpp = 4;
1570 else
1571 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1572
1573 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1574 wm_info, fifo_size, cpp,
1575 pessimal_latency_ns);
1576 if (enabled == NULL)
1577 enabled = crtc;
1578 else
1579 enabled = NULL;
1580 } else {
1581 planeb_wm = fifo_size - wm_info->guard_size;
1582 if (planeb_wm > (long)wm_info->max_wm)
1583 planeb_wm = wm_info->max_wm;
1584 }
1585
1586 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1587
1588 if (IS_I915GM(dev_priv) && enabled) {
1589 struct drm_i915_gem_object *obj;
1590
1591 obj = intel_fb_obj(enabled->base.primary->state->fb);
1592
1593 /* self-refresh seems busted with untiled */
1594 if (!i915_gem_object_is_tiled(obj))
1595 enabled = NULL;
1596 }
1597
1598 /*
1599 * Overlay gets an aggressive default since video jitter is bad.
1600 */
1601 cwm = 2;
1602
1603 /* Play safe and disable self-refresh before adjusting watermarks. */
1604 intel_set_memory_cxsr(dev_priv, false);
1605
1606 /* Calc sr entries for one plane configs */
1607 if (HAS_FW_BLC(dev_priv) && enabled) {
1608 /* self-refresh has much higher latency */
1609 static const int sr_latency_ns = 6000;
1610 const struct drm_display_mode *adjusted_mode =
1611 &enabled->config->base.adjusted_mode;
1612 const struct drm_framebuffer *fb =
1613 enabled->base.primary->state->fb;
1614 int clock = adjusted_mode->crtc_clock;
1615 int htotal = adjusted_mode->crtc_htotal;
1616 int hdisplay = enabled->config->pipe_src_w;
1617 int cpp;
1618 unsigned long line_time_us;
1619 int entries;
1620
1621 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
1622 cpp = 4;
1623 else
1624 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1625
1626 line_time_us = max(htotal * 1000 / clock, 1);
1627
1628 /* Use ns/us then divide to preserve precision */
1629 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1630 cpp * hdisplay;
1631 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1632 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1633 srwm = wm_info->fifo_size - entries;
1634 if (srwm < 0)
1635 srwm = 1;
1636
1637 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1638 I915_WRITE(FW_BLC_SELF,
1639 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1640 else
1641 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1642 }
1643
1644 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1645 planea_wm, planeb_wm, cwm, srwm);
1646
1647 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1648 fwater_hi = (cwm & 0x1f);
1649
1650 /* Set request length to 8 cachelines per fetch */
1651 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1652 fwater_hi = fwater_hi | (1 << 8);
1653
1654 I915_WRITE(FW_BLC, fwater_lo);
1655 I915_WRITE(FW_BLC2, fwater_hi);
1656
1657 if (enabled)
1658 intel_set_memory_cxsr(dev_priv, true);
1659 }
1660
1661 static void i845_update_wm(struct intel_crtc *unused_crtc)
1662 {
1663 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1664 struct intel_crtc *crtc;
1665 const struct drm_display_mode *adjusted_mode;
1666 uint32_t fwater_lo;
1667 int planea_wm;
1668
1669 crtc = single_enabled_crtc(dev_priv);
1670 if (crtc == NULL)
1671 return;
1672
1673 adjusted_mode = &crtc->config->base.adjusted_mode;
1674 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1675 &i845_wm_info,
1676 dev_priv->display.get_fifo_size(dev_priv, 0),
1677 4, pessimal_latency_ns);
1678 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1679 fwater_lo |= (3<<8) | planea_wm;
1680
1681 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1682
1683 I915_WRITE(FW_BLC, fwater_lo);
1684 }
1685
1686 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1687 {
1688 uint32_t pixel_rate;
1689
1690 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1691
1692 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1693 * adjust the pixel_rate here. */
1694
1695 if (pipe_config->pch_pfit.enabled) {
1696 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1697 uint32_t pfit_size = pipe_config->pch_pfit.size;
1698
1699 pipe_w = pipe_config->pipe_src_w;
1700 pipe_h = pipe_config->pipe_src_h;
1701
1702 pfit_w = (pfit_size >> 16) & 0xFFFF;
1703 pfit_h = pfit_size & 0xFFFF;
1704 if (pipe_w < pfit_w)
1705 pipe_w = pfit_w;
1706 if (pipe_h < pfit_h)
1707 pipe_h = pfit_h;
1708
1709 if (WARN_ON(!pfit_w || !pfit_h))
1710 return pixel_rate;
1711
1712 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1713 pfit_w * pfit_h);
1714 }
1715
1716 return pixel_rate;
1717 }
1718
1719 /* latency must be in 0.1us units. */
1720 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1721 {
1722 uint64_t ret;
1723
1724 if (WARN(latency == 0, "Latency value missing\n"))
1725 return UINT_MAX;
1726
1727 ret = (uint64_t) pixel_rate * cpp * latency;
1728 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1729
1730 return ret;
1731 }
1732
1733 /* latency must be in 0.1us units. */
1734 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1735 uint32_t horiz_pixels, uint8_t cpp,
1736 uint32_t latency)
1737 {
1738 uint32_t ret;
1739
1740 if (WARN(latency == 0, "Latency value missing\n"))
1741 return UINT_MAX;
1742 if (WARN_ON(!pipe_htotal))
1743 return UINT_MAX;
1744
1745 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1746 ret = (ret + 1) * horiz_pixels * cpp;
1747 ret = DIV_ROUND_UP(ret, 64) + 2;
1748 return ret;
1749 }
1750
1751 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1752 uint8_t cpp)
1753 {
1754 /*
1755 * Neither of these should be possible since this function shouldn't be
1756 * called if the CRTC is off or the plane is invisible. But let's be
1757 * extra paranoid to avoid a potential divide-by-zero if we screw up
1758 * elsewhere in the driver.
1759 */
1760 if (WARN_ON(!cpp))
1761 return 0;
1762 if (WARN_ON(!horiz_pixels))
1763 return 0;
1764
1765 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1766 }
1767
1768 struct ilk_wm_maximums {
1769 uint16_t pri;
1770 uint16_t spr;
1771 uint16_t cur;
1772 uint16_t fbc;
1773 };
1774
1775 /*
1776 * For both WM_PIPE and WM_LP.
1777 * mem_value must be in 0.1us units.
1778 */
1779 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1780 const struct intel_plane_state *pstate,
1781 uint32_t mem_value,
1782 bool is_lp)
1783 {
1784 int cpp = pstate->base.fb ?
1785 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1786 uint32_t method1, method2;
1787
1788 if (!cstate->base.active || !pstate->base.visible)
1789 return 0;
1790
1791 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1792
1793 if (!is_lp)
1794 return method1;
1795
1796 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1797 cstate->base.adjusted_mode.crtc_htotal,
1798 drm_rect_width(&pstate->base.dst),
1799 cpp, mem_value);
1800
1801 return min(method1, method2);
1802 }
1803
1804 /*
1805 * For both WM_PIPE and WM_LP.
1806 * mem_value must be in 0.1us units.
1807 */
1808 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1809 const struct intel_plane_state *pstate,
1810 uint32_t mem_value)
1811 {
1812 int cpp = pstate->base.fb ?
1813 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1814 uint32_t method1, method2;
1815
1816 if (!cstate->base.active || !pstate->base.visible)
1817 return 0;
1818
1819 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1820 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1821 cstate->base.adjusted_mode.crtc_htotal,
1822 drm_rect_width(&pstate->base.dst),
1823 cpp, mem_value);
1824 return min(method1, method2);
1825 }
1826
1827 /*
1828 * For both WM_PIPE and WM_LP.
1829 * mem_value must be in 0.1us units.
1830 */
1831 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1832 const struct intel_plane_state *pstate,
1833 uint32_t mem_value)
1834 {
1835 /*
1836 * We treat the cursor plane as always-on for the purposes of watermark
1837 * calculation. Until we have two-stage watermark programming merged,
1838 * this is necessary to avoid flickering.
1839 */
1840 int cpp = 4;
1841 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
1842
1843 if (!cstate->base.active)
1844 return 0;
1845
1846 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1847 cstate->base.adjusted_mode.crtc_htotal,
1848 width, cpp, mem_value);
1849 }
1850
1851 /* Only for WM_LP. */
1852 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1853 const struct intel_plane_state *pstate,
1854 uint32_t pri_val)
1855 {
1856 int cpp = pstate->base.fb ?
1857 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1858
1859 if (!cstate->base.active || !pstate->base.visible)
1860 return 0;
1861
1862 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
1863 }
1864
1865 static unsigned int
1866 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
1867 {
1868 if (INTEL_GEN(dev_priv) >= 8)
1869 return 3072;
1870 else if (INTEL_GEN(dev_priv) >= 7)
1871 return 768;
1872 else
1873 return 512;
1874 }
1875
1876 static unsigned int
1877 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
1878 int level, bool is_sprite)
1879 {
1880 if (INTEL_GEN(dev_priv) >= 8)
1881 /* BDW primary/sprite plane watermarks */
1882 return level == 0 ? 255 : 2047;
1883 else if (INTEL_GEN(dev_priv) >= 7)
1884 /* IVB/HSW primary/sprite plane watermarks */
1885 return level == 0 ? 127 : 1023;
1886 else if (!is_sprite)
1887 /* ILK/SNB primary plane watermarks */
1888 return level == 0 ? 127 : 511;
1889 else
1890 /* ILK/SNB sprite plane watermarks */
1891 return level == 0 ? 63 : 255;
1892 }
1893
1894 static unsigned int
1895 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
1896 {
1897 if (INTEL_GEN(dev_priv) >= 7)
1898 return level == 0 ? 63 : 255;
1899 else
1900 return level == 0 ? 31 : 63;
1901 }
1902
1903 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
1904 {
1905 if (INTEL_GEN(dev_priv) >= 8)
1906 return 31;
1907 else
1908 return 15;
1909 }
1910
1911 /* Calculate the maximum primary/sprite plane watermark */
1912 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1913 int level,
1914 const struct intel_wm_config *config,
1915 enum intel_ddb_partitioning ddb_partitioning,
1916 bool is_sprite)
1917 {
1918 struct drm_i915_private *dev_priv = to_i915(dev);
1919 unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
1920
1921 /* if sprites aren't enabled, sprites get nothing */
1922 if (is_sprite && !config->sprites_enabled)
1923 return 0;
1924
1925 /* HSW allows LP1+ watermarks even with multiple pipes */
1926 if (level == 0 || config->num_pipes_active > 1) {
1927 fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
1928
1929 /*
1930 * For some reason the non self refresh
1931 * FIFO size is only half of the self
1932 * refresh FIFO size on ILK/SNB.
1933 */
1934 if (INTEL_GEN(dev_priv) <= 6)
1935 fifo_size /= 2;
1936 }
1937
1938 if (config->sprites_enabled) {
1939 /* level 0 is always calculated with 1:1 split */
1940 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1941 if (is_sprite)
1942 fifo_size *= 5;
1943 fifo_size /= 6;
1944 } else {
1945 fifo_size /= 2;
1946 }
1947 }
1948
1949 /* clamp to max that the registers can hold */
1950 return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
1951 }
1952
1953 /* Calculate the maximum cursor plane watermark */
1954 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1955 int level,
1956 const struct intel_wm_config *config)
1957 {
1958 /* HSW LP1+ watermarks w/ multiple pipes */
1959 if (level > 0 && config->num_pipes_active > 1)
1960 return 64;
1961
1962 /* otherwise just report max that registers can hold */
1963 return ilk_cursor_wm_reg_max(to_i915(dev), level);
1964 }
1965
1966 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1967 int level,
1968 const struct intel_wm_config *config,
1969 enum intel_ddb_partitioning ddb_partitioning,
1970 struct ilk_wm_maximums *max)
1971 {
1972 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1973 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1974 max->cur = ilk_cursor_wm_max(dev, level, config);
1975 max->fbc = ilk_fbc_wm_reg_max(to_i915(dev));
1976 }
1977
1978 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
1979 int level,
1980 struct ilk_wm_maximums *max)
1981 {
1982 max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
1983 max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
1984 max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
1985 max->fbc = ilk_fbc_wm_reg_max(dev_priv);
1986 }
1987
1988 static bool ilk_validate_wm_level(int level,
1989 const struct ilk_wm_maximums *max,
1990 struct intel_wm_level *result)
1991 {
1992 bool ret;
1993
1994 /* already determined to be invalid? */
1995 if (!result->enable)
1996 return false;
1997
1998 result->enable = result->pri_val <= max->pri &&
1999 result->spr_val <= max->spr &&
2000 result->cur_val <= max->cur;
2001
2002 ret = result->enable;
2003
2004 /*
2005 * HACK until we can pre-compute everything,
2006 * and thus fail gracefully if LP0 watermarks
2007 * are exceeded...
2008 */
2009 if (level == 0 && !result->enable) {
2010 if (result->pri_val > max->pri)
2011 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2012 level, result->pri_val, max->pri);
2013 if (result->spr_val > max->spr)
2014 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2015 level, result->spr_val, max->spr);
2016 if (result->cur_val > max->cur)
2017 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2018 level, result->cur_val, max->cur);
2019
2020 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2021 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2022 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2023 result->enable = true;
2024 }
2025
2026 return ret;
2027 }
2028
2029 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2030 const struct intel_crtc *intel_crtc,
2031 int level,
2032 struct intel_crtc_state *cstate,
2033 struct intel_plane_state *pristate,
2034 struct intel_plane_state *sprstate,
2035 struct intel_plane_state *curstate,
2036 struct intel_wm_level *result)
2037 {
2038 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2039 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2040 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2041
2042 /* WM1+ latency values stored in 0.5us units */
2043 if (level > 0) {
2044 pri_latency *= 5;
2045 spr_latency *= 5;
2046 cur_latency *= 5;
2047 }
2048
2049 if (pristate) {
2050 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2051 pri_latency, level);
2052 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2053 }
2054
2055 if (sprstate)
2056 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2057
2058 if (curstate)
2059 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2060
2061 result->enable = true;
2062 }
2063
2064 static uint32_t
2065 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2066 {
2067 const struct intel_atomic_state *intel_state =
2068 to_intel_atomic_state(cstate->base.state);
2069 const struct drm_display_mode *adjusted_mode =
2070 &cstate->base.adjusted_mode;
2071 u32 linetime, ips_linetime;
2072
2073 if (!cstate->base.active)
2074 return 0;
2075 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2076 return 0;
2077 if (WARN_ON(intel_state->cdclk == 0))
2078 return 0;
2079
2080 /* The WM are computed with base on how long it takes to fill a single
2081 * row at the given clock rate, multiplied by 8.
2082 * */
2083 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2084 adjusted_mode->crtc_clock);
2085 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2086 intel_state->cdclk);
2087
2088 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2089 PIPE_WM_LINETIME_TIME(linetime);
2090 }
2091
2092 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2093 uint16_t wm[8])
2094 {
2095 if (IS_GEN9(dev_priv)) {
2096 uint32_t val;
2097 int ret, i;
2098 int level, max_level = ilk_wm_max_level(dev_priv);
2099
2100 /* read the first set of memory latencies[0:3] */
2101 val = 0; /* data0 to be programmed to 0 for first set */
2102 mutex_lock(&dev_priv->rps.hw_lock);
2103 ret = sandybridge_pcode_read(dev_priv,
2104 GEN9_PCODE_READ_MEM_LATENCY,
2105 &val);
2106 mutex_unlock(&dev_priv->rps.hw_lock);
2107
2108 if (ret) {
2109 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2110 return;
2111 }
2112
2113 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2114 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2115 GEN9_MEM_LATENCY_LEVEL_MASK;
2116 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2117 GEN9_MEM_LATENCY_LEVEL_MASK;
2118 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2119 GEN9_MEM_LATENCY_LEVEL_MASK;
2120
2121 /* read the second set of memory latencies[4:7] */
2122 val = 1; /* data0 to be programmed to 1 for second set */
2123 mutex_lock(&dev_priv->rps.hw_lock);
2124 ret = sandybridge_pcode_read(dev_priv,
2125 GEN9_PCODE_READ_MEM_LATENCY,
2126 &val);
2127 mutex_unlock(&dev_priv->rps.hw_lock);
2128 if (ret) {
2129 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2130 return;
2131 }
2132
2133 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2134 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2135 GEN9_MEM_LATENCY_LEVEL_MASK;
2136 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2137 GEN9_MEM_LATENCY_LEVEL_MASK;
2138 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2139 GEN9_MEM_LATENCY_LEVEL_MASK;
2140
2141 /*
2142 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2143 * need to be disabled. We make sure to sanitize the values out
2144 * of the punit to satisfy this requirement.
2145 */
2146 for (level = 1; level <= max_level; level++) {
2147 if (wm[level] == 0) {
2148 for (i = level + 1; i <= max_level; i++)
2149 wm[i] = 0;
2150 break;
2151 }
2152 }
2153
2154 /*
2155 * WaWmMemoryReadLatency:skl
2156 *
2157 * punit doesn't take into account the read latency so we need
2158 * to add 2us to the various latency levels we retrieve from the
2159 * punit when level 0 response data us 0us.
2160 */
2161 if (wm[0] == 0) {
2162 wm[0] += 2;
2163 for (level = 1; level <= max_level; level++) {
2164 if (wm[level] == 0)
2165 break;
2166 wm[level] += 2;
2167 }
2168 }
2169
2170 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2171 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2172
2173 wm[0] = (sskpd >> 56) & 0xFF;
2174 if (wm[0] == 0)
2175 wm[0] = sskpd & 0xF;
2176 wm[1] = (sskpd >> 4) & 0xFF;
2177 wm[2] = (sskpd >> 12) & 0xFF;
2178 wm[3] = (sskpd >> 20) & 0x1FF;
2179 wm[4] = (sskpd >> 32) & 0x1FF;
2180 } else if (INTEL_GEN(dev_priv) >= 6) {
2181 uint32_t sskpd = I915_READ(MCH_SSKPD);
2182
2183 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2184 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2185 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2186 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2187 } else if (INTEL_GEN(dev_priv) >= 5) {
2188 uint32_t mltr = I915_READ(MLTR_ILK);
2189
2190 /* ILK primary LP0 latency is 700 ns */
2191 wm[0] = 7;
2192 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2193 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2194 }
2195 }
2196
2197 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2198 uint16_t wm[5])
2199 {
2200 /* ILK sprite LP0 latency is 1300 ns */
2201 if (IS_GEN5(dev_priv))
2202 wm[0] = 13;
2203 }
2204
2205 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2206 uint16_t wm[5])
2207 {
2208 /* ILK cursor LP0 latency is 1300 ns */
2209 if (IS_GEN5(dev_priv))
2210 wm[0] = 13;
2211
2212 /* WaDoubleCursorLP3Latency:ivb */
2213 if (IS_IVYBRIDGE(dev_priv))
2214 wm[3] *= 2;
2215 }
2216
2217 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2218 {
2219 /* how many WM levels are we expecting */
2220 if (INTEL_GEN(dev_priv) >= 9)
2221 return 7;
2222 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2223 return 4;
2224 else if (INTEL_GEN(dev_priv) >= 6)
2225 return 3;
2226 else
2227 return 2;
2228 }
2229
2230 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2231 const char *name,
2232 const uint16_t wm[8])
2233 {
2234 int level, max_level = ilk_wm_max_level(dev_priv);
2235
2236 for (level = 0; level <= max_level; level++) {
2237 unsigned int latency = wm[level];
2238
2239 if (latency == 0) {
2240 DRM_ERROR("%s WM%d latency not provided\n",
2241 name, level);
2242 continue;
2243 }
2244
2245 /*
2246 * - latencies are in us on gen9.
2247 * - before then, WM1+ latency values are in 0.5us units
2248 */
2249 if (IS_GEN9(dev_priv))
2250 latency *= 10;
2251 else if (level > 0)
2252 latency *= 5;
2253
2254 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2255 name, level, wm[level],
2256 latency / 10, latency % 10);
2257 }
2258 }
2259
2260 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2261 uint16_t wm[5], uint16_t min)
2262 {
2263 int level, max_level = ilk_wm_max_level(dev_priv);
2264
2265 if (wm[0] >= min)
2266 return false;
2267
2268 wm[0] = max(wm[0], min);
2269 for (level = 1; level <= max_level; level++)
2270 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2271
2272 return true;
2273 }
2274
2275 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
2276 {
2277 bool changed;
2278
2279 /*
2280 * The BIOS provided WM memory latency values are often
2281 * inadequate for high resolution displays. Adjust them.
2282 */
2283 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2284 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2285 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2286
2287 if (!changed)
2288 return;
2289
2290 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2291 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2292 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2293 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2294 }
2295
2296 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
2297 {
2298 intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
2299
2300 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2301 sizeof(dev_priv->wm.pri_latency));
2302 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2303 sizeof(dev_priv->wm.pri_latency));
2304
2305 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
2306 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
2307
2308 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2309 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2310 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2311
2312 if (IS_GEN6(dev_priv))
2313 snb_wm_latency_quirk(dev_priv);
2314 }
2315
2316 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
2317 {
2318 intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
2319 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2320 }
2321
2322 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2323 struct intel_pipe_wm *pipe_wm)
2324 {
2325 /* LP0 watermark maximums depend on this pipe alone */
2326 const struct intel_wm_config config = {
2327 .num_pipes_active = 1,
2328 .sprites_enabled = pipe_wm->sprites_enabled,
2329 .sprites_scaled = pipe_wm->sprites_scaled,
2330 };
2331 struct ilk_wm_maximums max;
2332
2333 /* LP0 watermarks always use 1/2 DDB partitioning */
2334 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2335
2336 /* At least LP0 must be valid */
2337 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2338 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2339 return false;
2340 }
2341
2342 return true;
2343 }
2344
2345 /* Compute new watermarks for the pipe */
2346 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2347 {
2348 struct drm_atomic_state *state = cstate->base.state;
2349 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2350 struct intel_pipe_wm *pipe_wm;
2351 struct drm_device *dev = state->dev;
2352 const struct drm_i915_private *dev_priv = to_i915(dev);
2353 struct intel_plane *intel_plane;
2354 struct intel_plane_state *pristate = NULL;
2355 struct intel_plane_state *sprstate = NULL;
2356 struct intel_plane_state *curstate = NULL;
2357 int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
2358 struct ilk_wm_maximums max;
2359
2360 pipe_wm = &cstate->wm.ilk.optimal;
2361
2362 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2363 struct intel_plane_state *ps;
2364
2365 ps = intel_atomic_get_existing_plane_state(state,
2366 intel_plane);
2367 if (!ps)
2368 continue;
2369
2370 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2371 pristate = ps;
2372 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2373 sprstate = ps;
2374 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2375 curstate = ps;
2376 }
2377
2378 pipe_wm->pipe_enabled = cstate->base.active;
2379 if (sprstate) {
2380 pipe_wm->sprites_enabled = sprstate->base.visible;
2381 pipe_wm->sprites_scaled = sprstate->base.visible &&
2382 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2383 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
2384 }
2385
2386 usable_level = max_level;
2387
2388 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2389 if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
2390 usable_level = 1;
2391
2392 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2393 if (pipe_wm->sprites_scaled)
2394 usable_level = 0;
2395
2396 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2397 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2398
2399 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2400 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2401
2402 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2403 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2404
2405 if (!ilk_validate_pipe_wm(dev, pipe_wm))
2406 return -EINVAL;
2407
2408 ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
2409
2410 for (level = 1; level <= max_level; level++) {
2411 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2412
2413 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2414 pristate, sprstate, curstate, wm);
2415
2416 /*
2417 * Disable any watermark level that exceeds the
2418 * register maximums since such watermarks are
2419 * always invalid.
2420 */
2421 if (level > usable_level)
2422 continue;
2423
2424 if (ilk_validate_wm_level(level, &max, wm))
2425 pipe_wm->wm[level] = *wm;
2426 else
2427 usable_level = level;
2428 }
2429
2430 return 0;
2431 }
2432
2433 /*
2434 * Build a set of 'intermediate' watermark values that satisfy both the old
2435 * state and the new state. These can be programmed to the hardware
2436 * immediately.
2437 */
2438 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2439 struct intel_crtc *intel_crtc,
2440 struct intel_crtc_state *newstate)
2441 {
2442 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2443 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2444 int level, max_level = ilk_wm_max_level(to_i915(dev));
2445
2446 /*
2447 * Start with the final, target watermarks, then combine with the
2448 * currently active watermarks to get values that are safe both before
2449 * and after the vblank.
2450 */
2451 *a = newstate->wm.ilk.optimal;
2452 a->pipe_enabled |= b->pipe_enabled;
2453 a->sprites_enabled |= b->sprites_enabled;
2454 a->sprites_scaled |= b->sprites_scaled;
2455
2456 for (level = 0; level <= max_level; level++) {
2457 struct intel_wm_level *a_wm = &a->wm[level];
2458 const struct intel_wm_level *b_wm = &b->wm[level];
2459
2460 a_wm->enable &= b_wm->enable;
2461 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2462 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2463 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2464 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2465 }
2466
2467 /*
2468 * We need to make sure that these merged watermark values are
2469 * actually a valid configuration themselves. If they're not,
2470 * there's no safe way to transition from the old state to
2471 * the new state, so we need to fail the atomic transaction.
2472 */
2473 if (!ilk_validate_pipe_wm(dev, a))
2474 return -EINVAL;
2475
2476 /*
2477 * If our intermediate WM are identical to the final WM, then we can
2478 * omit the post-vblank programming; only update if it's different.
2479 */
2480 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2481 newstate->wm.need_postvbl_update = false;
2482
2483 return 0;
2484 }
2485
2486 /*
2487 * Merge the watermarks from all active pipes for a specific level.
2488 */
2489 static void ilk_merge_wm_level(struct drm_device *dev,
2490 int level,
2491 struct intel_wm_level *ret_wm)
2492 {
2493 const struct intel_crtc *intel_crtc;
2494
2495 ret_wm->enable = true;
2496
2497 for_each_intel_crtc(dev, intel_crtc) {
2498 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2499 const struct intel_wm_level *wm = &active->wm[level];
2500
2501 if (!active->pipe_enabled)
2502 continue;
2503
2504 /*
2505 * The watermark values may have been used in the past,
2506 * so we must maintain them in the registers for some
2507 * time even if the level is now disabled.
2508 */
2509 if (!wm->enable)
2510 ret_wm->enable = false;
2511
2512 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2513 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2514 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2515 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2516 }
2517 }
2518
2519 /*
2520 * Merge all low power watermarks for all active pipes.
2521 */
2522 static void ilk_wm_merge(struct drm_device *dev,
2523 const struct intel_wm_config *config,
2524 const struct ilk_wm_maximums *max,
2525 struct intel_pipe_wm *merged)
2526 {
2527 struct drm_i915_private *dev_priv = to_i915(dev);
2528 int level, max_level = ilk_wm_max_level(dev_priv);
2529 int last_enabled_level = max_level;
2530
2531 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2532 if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
2533 config->num_pipes_active > 1)
2534 last_enabled_level = 0;
2535
2536 /* ILK: FBC WM must be disabled always */
2537 merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
2538
2539 /* merge each WM1+ level */
2540 for (level = 1; level <= max_level; level++) {
2541 struct intel_wm_level *wm = &merged->wm[level];
2542
2543 ilk_merge_wm_level(dev, level, wm);
2544
2545 if (level > last_enabled_level)
2546 wm->enable = false;
2547 else if (!ilk_validate_wm_level(level, max, wm))
2548 /* make sure all following levels get disabled */
2549 last_enabled_level = level - 1;
2550
2551 /*
2552 * The spec says it is preferred to disable
2553 * FBC WMs instead of disabling a WM level.
2554 */
2555 if (wm->fbc_val > max->fbc) {
2556 if (wm->enable)
2557 merged->fbc_wm_enabled = false;
2558 wm->fbc_val = 0;
2559 }
2560 }
2561
2562 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2563 /*
2564 * FIXME this is racy. FBC might get enabled later.
2565 * What we should check here is whether FBC can be
2566 * enabled sometime later.
2567 */
2568 if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
2569 intel_fbc_is_active(dev_priv)) {
2570 for (level = 2; level <= max_level; level++) {
2571 struct intel_wm_level *wm = &merged->wm[level];
2572
2573 wm->enable = false;
2574 }
2575 }
2576 }
2577
2578 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2579 {
2580 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2581 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2582 }
2583
2584 /* The value we need to program into the WM_LPx latency field */
2585 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2586 {
2587 struct drm_i915_private *dev_priv = to_i915(dev);
2588
2589 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2590 return 2 * level;
2591 else
2592 return dev_priv->wm.pri_latency[level];
2593 }
2594
2595 static void ilk_compute_wm_results(struct drm_device *dev,
2596 const struct intel_pipe_wm *merged,
2597 enum intel_ddb_partitioning partitioning,
2598 struct ilk_wm_values *results)
2599 {
2600 struct drm_i915_private *dev_priv = to_i915(dev);
2601 struct intel_crtc *intel_crtc;
2602 int level, wm_lp;
2603
2604 results->enable_fbc_wm = merged->fbc_wm_enabled;
2605 results->partitioning = partitioning;
2606
2607 /* LP1+ register values */
2608 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2609 const struct intel_wm_level *r;
2610
2611 level = ilk_wm_lp_to_level(wm_lp, merged);
2612
2613 r = &merged->wm[level];
2614
2615 /*
2616 * Maintain the watermark values even if the level is
2617 * disabled. Doing otherwise could cause underruns.
2618 */
2619 results->wm_lp[wm_lp - 1] =
2620 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2621 (r->pri_val << WM1_LP_SR_SHIFT) |
2622 r->cur_val;
2623
2624 if (r->enable)
2625 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2626
2627 if (INTEL_GEN(dev_priv) >= 8)
2628 results->wm_lp[wm_lp - 1] |=
2629 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2630 else
2631 results->wm_lp[wm_lp - 1] |=
2632 r->fbc_val << WM1_LP_FBC_SHIFT;
2633
2634 /*
2635 * Always set WM1S_LP_EN when spr_val != 0, even if the
2636 * level is disabled. Doing otherwise could cause underruns.
2637 */
2638 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
2639 WARN_ON(wm_lp != 1);
2640 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2641 } else
2642 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2643 }
2644
2645 /* LP0 register values */
2646 for_each_intel_crtc(dev, intel_crtc) {
2647 enum pipe pipe = intel_crtc->pipe;
2648 const struct intel_wm_level *r =
2649 &intel_crtc->wm.active.ilk.wm[0];
2650
2651 if (WARN_ON(!r->enable))
2652 continue;
2653
2654 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2655
2656 results->wm_pipe[pipe] =
2657 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2658 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2659 r->cur_val;
2660 }
2661 }
2662
2663 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2664 * case both are at the same level. Prefer r1 in case they're the same. */
2665 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2666 struct intel_pipe_wm *r1,
2667 struct intel_pipe_wm *r2)
2668 {
2669 int level, max_level = ilk_wm_max_level(to_i915(dev));
2670 int level1 = 0, level2 = 0;
2671
2672 for (level = 1; level <= max_level; level++) {
2673 if (r1->wm[level].enable)
2674 level1 = level;
2675 if (r2->wm[level].enable)
2676 level2 = level;
2677 }
2678
2679 if (level1 == level2) {
2680 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2681 return r2;
2682 else
2683 return r1;
2684 } else if (level1 > level2) {
2685 return r1;
2686 } else {
2687 return r2;
2688 }
2689 }
2690
2691 /* dirty bits used to track which watermarks need changes */
2692 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2693 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2694 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2695 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2696 #define WM_DIRTY_FBC (1 << 24)
2697 #define WM_DIRTY_DDB (1 << 25)
2698
2699 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2700 const struct ilk_wm_values *old,
2701 const struct ilk_wm_values *new)
2702 {
2703 unsigned int dirty = 0;
2704 enum pipe pipe;
2705 int wm_lp;
2706
2707 for_each_pipe(dev_priv, pipe) {
2708 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2709 dirty |= WM_DIRTY_LINETIME(pipe);
2710 /* Must disable LP1+ watermarks too */
2711 dirty |= WM_DIRTY_LP_ALL;
2712 }
2713
2714 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2715 dirty |= WM_DIRTY_PIPE(pipe);
2716 /* Must disable LP1+ watermarks too */
2717 dirty |= WM_DIRTY_LP_ALL;
2718 }
2719 }
2720
2721 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2722 dirty |= WM_DIRTY_FBC;
2723 /* Must disable LP1+ watermarks too */
2724 dirty |= WM_DIRTY_LP_ALL;
2725 }
2726
2727 if (old->partitioning != new->partitioning) {
2728 dirty |= WM_DIRTY_DDB;
2729 /* Must disable LP1+ watermarks too */
2730 dirty |= WM_DIRTY_LP_ALL;
2731 }
2732
2733 /* LP1+ watermarks already deemed dirty, no need to continue */
2734 if (dirty & WM_DIRTY_LP_ALL)
2735 return dirty;
2736
2737 /* Find the lowest numbered LP1+ watermark in need of an update... */
2738 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2739 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2740 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2741 break;
2742 }
2743
2744 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2745 for (; wm_lp <= 3; wm_lp++)
2746 dirty |= WM_DIRTY_LP(wm_lp);
2747
2748 return dirty;
2749 }
2750
2751 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2752 unsigned int dirty)
2753 {
2754 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2755 bool changed = false;
2756
2757 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2758 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2759 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2760 changed = true;
2761 }
2762 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2763 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2764 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2765 changed = true;
2766 }
2767 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2768 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2769 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2770 changed = true;
2771 }
2772
2773 /*
2774 * Don't touch WM1S_LP_EN here.
2775 * Doing so could cause underruns.
2776 */
2777
2778 return changed;
2779 }
2780
2781 /*
2782 * The spec says we shouldn't write when we don't need, because every write
2783 * causes WMs to be re-evaluated, expending some power.
2784 */
2785 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2786 struct ilk_wm_values *results)
2787 {
2788 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2789 unsigned int dirty;
2790 uint32_t val;
2791
2792 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2793 if (!dirty)
2794 return;
2795
2796 _ilk_disable_lp_wm(dev_priv, dirty);
2797
2798 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2799 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2800 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2801 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2802 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2803 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2804
2805 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2806 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2807 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2808 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2809 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2810 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2811
2812 if (dirty & WM_DIRTY_DDB) {
2813 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2814 val = I915_READ(WM_MISC);
2815 if (results->partitioning == INTEL_DDB_PART_1_2)
2816 val &= ~WM_MISC_DATA_PARTITION_5_6;
2817 else
2818 val |= WM_MISC_DATA_PARTITION_5_6;
2819 I915_WRITE(WM_MISC, val);
2820 } else {
2821 val = I915_READ(DISP_ARB_CTL2);
2822 if (results->partitioning == INTEL_DDB_PART_1_2)
2823 val &= ~DISP_DATA_PARTITION_5_6;
2824 else
2825 val |= DISP_DATA_PARTITION_5_6;
2826 I915_WRITE(DISP_ARB_CTL2, val);
2827 }
2828 }
2829
2830 if (dirty & WM_DIRTY_FBC) {
2831 val = I915_READ(DISP_ARB_CTL);
2832 if (results->enable_fbc_wm)
2833 val &= ~DISP_FBC_WM_DIS;
2834 else
2835 val |= DISP_FBC_WM_DIS;
2836 I915_WRITE(DISP_ARB_CTL, val);
2837 }
2838
2839 if (dirty & WM_DIRTY_LP(1) &&
2840 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2841 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2842
2843 if (INTEL_GEN(dev_priv) >= 7) {
2844 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2845 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2846 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2847 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2848 }
2849
2850 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2851 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2852 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2853 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2854 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2855 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2856
2857 dev_priv->wm.hw = *results;
2858 }
2859
2860 bool ilk_disable_lp_wm(struct drm_device *dev)
2861 {
2862 struct drm_i915_private *dev_priv = to_i915(dev);
2863
2864 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2865 }
2866
2867 #define SKL_SAGV_BLOCK_TIME 30 /* µs */
2868
2869 /*
2870 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2871 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2872 * other universal planes are in indices 1..n. Note that this may leave unused
2873 * indices between the top "sprite" plane and the cursor.
2874 */
2875 static int
2876 skl_wm_plane_id(const struct intel_plane *plane)
2877 {
2878 switch (plane->base.type) {
2879 case DRM_PLANE_TYPE_PRIMARY:
2880 return 0;
2881 case DRM_PLANE_TYPE_CURSOR:
2882 return PLANE_CURSOR;
2883 case DRM_PLANE_TYPE_OVERLAY:
2884 return plane->plane + 1;
2885 default:
2886 MISSING_CASE(plane->base.type);
2887 return plane->plane;
2888 }
2889 }
2890
2891 /*
2892 * FIXME: We still don't have the proper code detect if we need to apply the WA,
2893 * so assume we'll always need it in order to avoid underruns.
2894 */
2895 static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2896 {
2897 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2898
2899 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
2900 IS_KABYLAKE(dev_priv))
2901 return true;
2902
2903 return false;
2904 }
2905
2906 static bool
2907 intel_has_sagv(struct drm_i915_private *dev_priv)
2908 {
2909 if (IS_KABYLAKE(dev_priv))
2910 return true;
2911
2912 if (IS_SKYLAKE(dev_priv) &&
2913 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2914 return true;
2915
2916 return false;
2917 }
2918
2919 /*
2920 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2921 * depending on power and performance requirements. The display engine access
2922 * to system memory is blocked during the adjustment time. Because of the
2923 * blocking time, having this enabled can cause full system hangs and/or pipe
2924 * underruns if we don't meet all of the following requirements:
2925 *
2926 * - <= 1 pipe enabled
2927 * - All planes can enable watermarks for latencies >= SAGV engine block time
2928 * - We're not using an interlaced display configuration
2929 */
2930 int
2931 intel_enable_sagv(struct drm_i915_private *dev_priv)
2932 {
2933 int ret;
2934
2935 if (!intel_has_sagv(dev_priv))
2936 return 0;
2937
2938 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
2939 return 0;
2940
2941 DRM_DEBUG_KMS("Enabling the SAGV\n");
2942 mutex_lock(&dev_priv->rps.hw_lock);
2943
2944 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2945 GEN9_SAGV_ENABLE);
2946
2947 /* We don't need to wait for the SAGV when enabling */
2948 mutex_unlock(&dev_priv->rps.hw_lock);
2949
2950 /*
2951 * Some skl systems, pre-release machines in particular,
2952 * don't actually have an SAGV.
2953 */
2954 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2955 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2956 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2957 return 0;
2958 } else if (ret < 0) {
2959 DRM_ERROR("Failed to enable the SAGV\n");
2960 return ret;
2961 }
2962
2963 dev_priv->sagv_status = I915_SAGV_ENABLED;
2964 return 0;
2965 }
2966
2967 int
2968 intel_disable_sagv(struct drm_i915_private *dev_priv)
2969 {
2970 int ret;
2971
2972 if (!intel_has_sagv(dev_priv))
2973 return 0;
2974
2975 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
2976 return 0;
2977
2978 DRM_DEBUG_KMS("Disabling the SAGV\n");
2979 mutex_lock(&dev_priv->rps.hw_lock);
2980
2981 /* bspec says to keep retrying for at least 1 ms */
2982 ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2983 GEN9_SAGV_DISABLE,
2984 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
2985 1);
2986 mutex_unlock(&dev_priv->rps.hw_lock);
2987
2988 /*
2989 * Some skl systems, pre-release machines in particular,
2990 * don't actually have an SAGV.
2991 */
2992 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2993 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2994 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2995 return 0;
2996 } else if (ret < 0) {
2997 DRM_ERROR("Failed to disable the SAGV (%d)\n", ret);
2998 return ret;
2999 }
3000
3001 dev_priv->sagv_status = I915_SAGV_DISABLED;
3002 return 0;
3003 }
3004
3005 bool intel_can_enable_sagv(struct drm_atomic_state *state)
3006 {
3007 struct drm_device *dev = state->dev;
3008 struct drm_i915_private *dev_priv = to_i915(dev);
3009 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3010 struct intel_crtc *crtc;
3011 struct intel_plane *plane;
3012 struct intel_crtc_state *cstate;
3013 struct skl_plane_wm *wm;
3014 enum pipe pipe;
3015 int level, latency;
3016
3017 if (!intel_has_sagv(dev_priv))
3018 return false;
3019
3020 /*
3021 * SKL workaround: bspec recommends we disable the SAGV when we have
3022 * more then one pipe enabled
3023 *
3024 * If there are no active CRTCs, no additional checks need be performed
3025 */
3026 if (hweight32(intel_state->active_crtcs) == 0)
3027 return true;
3028 else if (hweight32(intel_state->active_crtcs) > 1)
3029 return false;
3030
3031 /* Since we're now guaranteed to only have one active CRTC... */
3032 pipe = ffs(intel_state->active_crtcs) - 1;
3033 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
3034 cstate = to_intel_crtc_state(crtc->base.state);
3035
3036 if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3037 return false;
3038
3039 for_each_intel_plane_on_crtc(dev, crtc, plane) {
3040 wm = &cstate->wm.skl.optimal.planes[skl_wm_plane_id(plane)];
3041
3042 /* Skip this plane if it's not enabled */
3043 if (!wm->wm[0].plane_en)
3044 continue;
3045
3046 /* Find the highest enabled wm level for this plane */
3047 for (level = ilk_wm_max_level(dev_priv);
3048 !wm->wm[level].plane_en; --level)
3049 { }
3050
3051 latency = dev_priv->wm.skl_latency[level];
3052
3053 if (skl_needs_memory_bw_wa(intel_state) &&
3054 plane->base.state->fb->modifier ==
3055 I915_FORMAT_MOD_X_TILED)
3056 latency += 15;
3057
3058 /*
3059 * If any of the planes on this pipe don't enable wm levels
3060 * that incur memory latencies higher then 30µs we can't enable
3061 * the SAGV
3062 */
3063 if (latency < SKL_SAGV_BLOCK_TIME)
3064 return false;
3065 }
3066
3067 return true;
3068 }
3069
3070 static void
3071 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3072 const struct intel_crtc_state *cstate,
3073 struct skl_ddb_entry *alloc, /* out */
3074 int *num_active /* out */)
3075 {
3076 struct drm_atomic_state *state = cstate->base.state;
3077 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3078 struct drm_i915_private *dev_priv = to_i915(dev);
3079 struct drm_crtc *for_crtc = cstate->base.crtc;
3080 unsigned int pipe_size, ddb_size;
3081 int nth_active_pipe;
3082
3083 if (WARN_ON(!state) || !cstate->base.active) {
3084 alloc->start = 0;
3085 alloc->end = 0;
3086 *num_active = hweight32(dev_priv->active_crtcs);
3087 return;
3088 }
3089
3090 if (intel_state->active_pipe_changes)
3091 *num_active = hweight32(intel_state->active_crtcs);
3092 else
3093 *num_active = hweight32(dev_priv->active_crtcs);
3094
3095 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3096 WARN_ON(ddb_size == 0);
3097
3098 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3099
3100 /*
3101 * If the state doesn't change the active CRTC's, then there's
3102 * no need to recalculate; the existing pipe allocation limits
3103 * should remain unchanged. Note that we're safe from racing
3104 * commits since any racing commit that changes the active CRTC
3105 * list would need to grab _all_ crtc locks, including the one
3106 * we currently hold.
3107 */
3108 if (!intel_state->active_pipe_changes) {
3109 /*
3110 * alloc may be cleared by clear_intel_crtc_state,
3111 * copy from old state to be sure
3112 */
3113 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
3114 return;
3115 }
3116
3117 nth_active_pipe = hweight32(intel_state->active_crtcs &
3118 (drm_crtc_mask(for_crtc) - 1));
3119 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3120 alloc->start = nth_active_pipe * ddb_size / *num_active;
3121 alloc->end = alloc->start + pipe_size;
3122 }
3123
3124 static unsigned int skl_cursor_allocation(int num_active)
3125 {
3126 if (num_active == 1)
3127 return 32;
3128
3129 return 8;
3130 }
3131
3132 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3133 {
3134 entry->start = reg & 0x3ff;
3135 entry->end = (reg >> 16) & 0x3ff;
3136 if (entry->end)
3137 entry->end += 1;
3138 }
3139
3140 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3141 struct skl_ddb_allocation *ddb /* out */)
3142 {
3143 enum pipe pipe;
3144 int plane;
3145 u32 val;
3146
3147 memset(ddb, 0, sizeof(*ddb));
3148
3149 for_each_pipe(dev_priv, pipe) {
3150 enum intel_display_power_domain power_domain;
3151
3152 power_domain = POWER_DOMAIN_PIPE(pipe);
3153 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3154 continue;
3155
3156 for_each_universal_plane(dev_priv, pipe, plane) {
3157 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3158 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3159 val);
3160 }
3161
3162 val = I915_READ(CUR_BUF_CFG(pipe));
3163 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3164 val);
3165
3166 intel_display_power_put(dev_priv, power_domain);
3167 }
3168 }
3169
3170 /*
3171 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3172 * The bspec defines downscale amount as:
3173 *
3174 * """
3175 * Horizontal down scale amount = maximum[1, Horizontal source size /
3176 * Horizontal destination size]
3177 * Vertical down scale amount = maximum[1, Vertical source size /
3178 * Vertical destination size]
3179 * Total down scale amount = Horizontal down scale amount *
3180 * Vertical down scale amount
3181 * """
3182 *
3183 * Return value is provided in 16.16 fixed point form to retain fractional part.
3184 * Caller should take care of dividing & rounding off the value.
3185 */
3186 static uint32_t
3187 skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3188 {
3189 uint32_t downscale_h, downscale_w;
3190 uint32_t src_w, src_h, dst_w, dst_h;
3191
3192 if (WARN_ON(!pstate->base.visible))
3193 return DRM_PLANE_HELPER_NO_SCALING;
3194
3195 /* n.b., src is 16.16 fixed point, dst is whole integer */
3196 src_w = drm_rect_width(&pstate->base.src);
3197 src_h = drm_rect_height(&pstate->base.src);
3198 dst_w = drm_rect_width(&pstate->base.dst);
3199 dst_h = drm_rect_height(&pstate->base.dst);
3200 if (drm_rotation_90_or_270(pstate->base.rotation))
3201 swap(dst_w, dst_h);
3202
3203 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3204 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3205
3206 /* Provide result in 16.16 fixed point */
3207 return (uint64_t)downscale_w * downscale_h >> 16;
3208 }
3209
3210 static unsigned int
3211 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3212 const struct drm_plane_state *pstate,
3213 int y)
3214 {
3215 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3216 struct drm_framebuffer *fb = pstate->fb;
3217 uint32_t down_scale_amount, data_rate;
3218 uint32_t width = 0, height = 0;
3219 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3220
3221 if (!intel_pstate->base.visible)
3222 return 0;
3223 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3224 return 0;
3225 if (y && format != DRM_FORMAT_NV12)
3226 return 0;
3227
3228 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3229 height = drm_rect_height(&intel_pstate->base.src) >> 16;
3230
3231 if (drm_rotation_90_or_270(pstate->rotation))
3232 swap(width, height);
3233
3234 /* for planar format */
3235 if (format == DRM_FORMAT_NV12) {
3236 if (y) /* y-plane data rate */
3237 data_rate = width * height *
3238 drm_format_plane_cpp(format, 0);
3239 else /* uv-plane data rate */
3240 data_rate = (width / 2) * (height / 2) *
3241 drm_format_plane_cpp(format, 1);
3242 } else {
3243 /* for packed formats */
3244 data_rate = width * height * drm_format_plane_cpp(format, 0);
3245 }
3246
3247 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3248
3249 return (uint64_t)data_rate * down_scale_amount >> 16;
3250 }
3251
3252 /*
3253 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3254 * a 8192x4096@32bpp framebuffer:
3255 * 3 * 4096 * 8192 * 4 < 2^32
3256 */
3257 static unsigned int
3258 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
3259 unsigned *plane_data_rate,
3260 unsigned *plane_y_data_rate)
3261 {
3262 struct drm_crtc_state *cstate = &intel_cstate->base;
3263 struct drm_atomic_state *state = cstate->state;
3264 struct drm_plane *plane;
3265 const struct intel_plane *intel_plane;
3266 const struct drm_plane_state *pstate;
3267 unsigned int rate, total_data_rate = 0;
3268 int id;
3269
3270 if (WARN_ON(!state))
3271 return 0;
3272
3273 /* Calculate and cache data rate for each plane */
3274 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
3275 id = skl_wm_plane_id(to_intel_plane(plane));
3276 intel_plane = to_intel_plane(plane);
3277
3278 /* packed/uv */
3279 rate = skl_plane_relative_data_rate(intel_cstate,
3280 pstate, 0);
3281 plane_data_rate[id] = rate;
3282
3283 total_data_rate += rate;
3284
3285 /* y-plane */
3286 rate = skl_plane_relative_data_rate(intel_cstate,
3287 pstate, 1);
3288 plane_y_data_rate[id] = rate;
3289
3290 total_data_rate += rate;
3291 }
3292
3293 return total_data_rate;
3294 }
3295
3296 static uint16_t
3297 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3298 const int y)
3299 {
3300 struct drm_framebuffer *fb = pstate->fb;
3301 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3302 uint32_t src_w, src_h;
3303 uint32_t min_scanlines = 8;
3304 uint8_t plane_bpp;
3305
3306 if (WARN_ON(!fb))
3307 return 0;
3308
3309 /* For packed formats, no y-plane, return 0 */
3310 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3311 return 0;
3312
3313 /* For Non Y-tile return 8-blocks */
3314 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
3315 fb->modifier != I915_FORMAT_MOD_Yf_TILED)
3316 return 8;
3317
3318 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3319 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
3320
3321 if (drm_rotation_90_or_270(pstate->rotation))
3322 swap(src_w, src_h);
3323
3324 /* Halve UV plane width and height for NV12 */
3325 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3326 src_w /= 2;
3327 src_h /= 2;
3328 }
3329
3330 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3331 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3332 else
3333 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3334
3335 if (drm_rotation_90_or_270(pstate->rotation)) {
3336 switch (plane_bpp) {
3337 case 1:
3338 min_scanlines = 32;
3339 break;
3340 case 2:
3341 min_scanlines = 16;
3342 break;
3343 case 4:
3344 min_scanlines = 8;
3345 break;
3346 case 8:
3347 min_scanlines = 4;
3348 break;
3349 default:
3350 WARN(1, "Unsupported pixel depth %u for rotation",
3351 plane_bpp);
3352 min_scanlines = 32;
3353 }
3354 }
3355
3356 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3357 }
3358
3359 static void
3360 skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
3361 uint16_t *minimum, uint16_t *y_minimum)
3362 {
3363 const struct drm_plane_state *pstate;
3364 struct drm_plane *plane;
3365
3366 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
3367 struct intel_plane *intel_plane = to_intel_plane(plane);
3368 int id = skl_wm_plane_id(intel_plane);
3369
3370 if (id == PLANE_CURSOR)
3371 continue;
3372
3373 if (!pstate->visible)
3374 continue;
3375
3376 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3377 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3378 }
3379
3380 minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
3381 }
3382
3383 static int
3384 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3385 struct skl_ddb_allocation *ddb /* out */)
3386 {
3387 struct drm_atomic_state *state = cstate->base.state;
3388 struct drm_crtc *crtc = cstate->base.crtc;
3389 struct drm_device *dev = crtc->dev;
3390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3391 enum pipe pipe = intel_crtc->pipe;
3392 struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
3393 uint16_t alloc_size, start;
3394 uint16_t minimum[I915_MAX_PLANES] = {};
3395 uint16_t y_minimum[I915_MAX_PLANES] = {};
3396 unsigned int total_data_rate;
3397 int num_active;
3398 int id, i;
3399 unsigned plane_data_rate[I915_MAX_PLANES] = {};
3400 unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
3401
3402 /* Clear the partitioning for disabled planes. */
3403 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3404 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3405
3406 if (WARN_ON(!state))
3407 return 0;
3408
3409 if (!cstate->base.active) {
3410 alloc->start = alloc->end = 0;
3411 return 0;
3412 }
3413
3414 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3415 alloc_size = skl_ddb_entry_size(alloc);
3416 if (alloc_size == 0) {
3417 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3418 return 0;
3419 }
3420
3421 skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
3422
3423 /*
3424 * 1. Allocate the mininum required blocks for each active plane
3425 * and allocate the cursor, it doesn't require extra allocation
3426 * proportional to the data rate.
3427 */
3428
3429 for (i = 0; i < I915_MAX_PLANES; i++) {
3430 alloc_size -= minimum[i];
3431 alloc_size -= y_minimum[i];
3432 }
3433
3434 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
3435 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3436
3437 /*
3438 * 2. Distribute the remaining space in proportion to the amount of
3439 * data each plane needs to fetch from memory.
3440 *
3441 * FIXME: we may not allocate every single block here.
3442 */
3443 total_data_rate = skl_get_total_relative_data_rate(cstate,
3444 plane_data_rate,
3445 plane_y_data_rate);
3446 if (total_data_rate == 0)
3447 return 0;
3448
3449 start = alloc->start;
3450 for (id = 0; id < I915_MAX_PLANES; id++) {
3451 unsigned int data_rate, y_data_rate;
3452 uint16_t plane_blocks, y_plane_blocks = 0;
3453
3454 if (id == PLANE_CURSOR)
3455 continue;
3456
3457 data_rate = plane_data_rate[id];
3458
3459 /*
3460 * allocation for (packed formats) or (uv-plane part of planar format):
3461 * promote the expression to 64 bits to avoid overflowing, the
3462 * result is < available as data_rate / total_data_rate < 1
3463 */
3464 plane_blocks = minimum[id];
3465 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3466 total_data_rate);
3467
3468 /* Leave disabled planes at (0,0) */
3469 if (data_rate) {
3470 ddb->plane[pipe][id].start = start;
3471 ddb->plane[pipe][id].end = start + plane_blocks;
3472 }
3473
3474 start += plane_blocks;
3475
3476 /*
3477 * allocation for y_plane part of planar format:
3478 */
3479 y_data_rate = plane_y_data_rate[id];
3480
3481 y_plane_blocks = y_minimum[id];
3482 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3483 total_data_rate);
3484
3485 if (y_data_rate) {
3486 ddb->y_plane[pipe][id].start = start;
3487 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3488 }
3489
3490 start += y_plane_blocks;
3491 }
3492
3493 return 0;
3494 }
3495
3496 /*
3497 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3498 * for the read latency) and cpp should always be <= 8, so that
3499 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3500 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3501 */
3502 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3503 {
3504 uint32_t wm_intermediate_val, ret;
3505
3506 if (latency == 0)
3507 return UINT_MAX;
3508
3509 wm_intermediate_val = latency * pixel_rate * cpp / 512;
3510 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3511
3512 return ret;
3513 }
3514
3515 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3516 uint32_t latency, uint32_t plane_blocks_per_line)
3517 {
3518 uint32_t ret;
3519 uint32_t wm_intermediate_val;
3520
3521 if (latency == 0)
3522 return UINT_MAX;
3523
3524 wm_intermediate_val = latency * pixel_rate;
3525 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3526 plane_blocks_per_line;
3527
3528 return ret;
3529 }
3530
3531 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3532 struct intel_plane_state *pstate)
3533 {
3534 uint64_t adjusted_pixel_rate;
3535 uint64_t downscale_amount;
3536 uint64_t pixel_rate;
3537
3538 /* Shouldn't reach here on disabled planes... */
3539 if (WARN_ON(!pstate->base.visible))
3540 return 0;
3541
3542 /*
3543 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3544 * with additional adjustments for plane-specific scaling.
3545 */
3546 adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
3547 downscale_amount = skl_plane_downscale_amount(pstate);
3548
3549 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3550 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3551
3552 return pixel_rate;
3553 }
3554
3555 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3556 struct intel_crtc_state *cstate,
3557 struct intel_plane_state *intel_pstate,
3558 uint16_t ddb_allocation,
3559 int level,
3560 uint16_t *out_blocks, /* out */
3561 uint8_t *out_lines, /* out */
3562 bool *enabled /* out */)
3563 {
3564 struct drm_plane_state *pstate = &intel_pstate->base;
3565 struct drm_framebuffer *fb = pstate->fb;
3566 uint32_t latency = dev_priv->wm.skl_latency[level];
3567 uint32_t method1, method2;
3568 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3569 uint32_t res_blocks, res_lines;
3570 uint32_t selected_result;
3571 uint8_t cpp;
3572 uint32_t width = 0, height = 0;
3573 uint32_t plane_pixel_rate;
3574 uint32_t y_tile_minimum, y_min_scanlines;
3575 struct intel_atomic_state *state =
3576 to_intel_atomic_state(cstate->base.state);
3577 bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
3578
3579 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
3580 *enabled = false;
3581 return 0;
3582 }
3583
3584 if (apply_memory_bw_wa && fb->modifier == I915_FORMAT_MOD_X_TILED)
3585 latency += 15;
3586
3587 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3588 height = drm_rect_height(&intel_pstate->base.src) >> 16;
3589
3590 if (drm_rotation_90_or_270(pstate->rotation))
3591 swap(width, height);
3592
3593 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3594 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3595
3596 if (drm_rotation_90_or_270(pstate->rotation)) {
3597 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3598 drm_format_plane_cpp(fb->pixel_format, 1) :
3599 drm_format_plane_cpp(fb->pixel_format, 0);
3600
3601 switch (cpp) {
3602 case 1:
3603 y_min_scanlines = 16;
3604 break;
3605 case 2:
3606 y_min_scanlines = 8;
3607 break;
3608 case 4:
3609 y_min_scanlines = 4;
3610 break;
3611 default:
3612 MISSING_CASE(cpp);
3613 return -EINVAL;
3614 }
3615 } else {
3616 y_min_scanlines = 4;
3617 }
3618
3619 if (apply_memory_bw_wa)
3620 y_min_scanlines *= 2;
3621
3622 plane_bytes_per_line = width * cpp;
3623 if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
3624 fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
3625 plane_blocks_per_line =
3626 DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3627 plane_blocks_per_line /= y_min_scanlines;
3628 } else if (fb->modifier == DRM_FORMAT_MOD_NONE) {
3629 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3630 + 1;
3631 } else {
3632 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3633 }
3634
3635 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3636 method2 = skl_wm_method2(plane_pixel_rate,
3637 cstate->base.adjusted_mode.crtc_htotal,
3638 latency,
3639 plane_blocks_per_line);
3640
3641 y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
3642
3643 if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
3644 fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
3645 selected_result = max(method2, y_tile_minimum);
3646 } else {
3647 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3648 (plane_bytes_per_line / 512 < 1))
3649 selected_result = method2;
3650 else if ((ddb_allocation / plane_blocks_per_line) >= 1)
3651 selected_result = min(method1, method2);
3652 else
3653 selected_result = method1;
3654 }
3655
3656 res_blocks = selected_result + 1;
3657 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3658
3659 if (level >= 1 && level <= 7) {
3660 if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
3661 fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
3662 res_blocks += y_tile_minimum;
3663 res_lines += y_min_scanlines;
3664 } else {
3665 res_blocks++;
3666 }
3667 }
3668
3669 if (res_blocks >= ddb_allocation || res_lines > 31) {
3670 *enabled = false;
3671
3672 /*
3673 * If there are no valid level 0 watermarks, then we can't
3674 * support this display configuration.
3675 */
3676 if (level) {
3677 return 0;
3678 } else {
3679 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3680 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3681 to_intel_crtc(cstate->base.crtc)->pipe,
3682 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3683 res_blocks, ddb_allocation, res_lines);
3684
3685 return -EINVAL;
3686 }
3687 }
3688
3689 *out_blocks = res_blocks;
3690 *out_lines = res_lines;
3691 *enabled = true;
3692
3693 return 0;
3694 }
3695
3696 static int
3697 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3698 struct skl_ddb_allocation *ddb,
3699 struct intel_crtc_state *cstate,
3700 struct intel_plane *intel_plane,
3701 int level,
3702 struct skl_wm_level *result)
3703 {
3704 struct drm_atomic_state *state = cstate->base.state;
3705 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3706 struct drm_plane *plane = &intel_plane->base;
3707 struct intel_plane_state *intel_pstate = NULL;
3708 uint16_t ddb_blocks;
3709 enum pipe pipe = intel_crtc->pipe;
3710 int ret;
3711 int i = skl_wm_plane_id(intel_plane);
3712
3713 if (state)
3714 intel_pstate =
3715 intel_atomic_get_existing_plane_state(state,
3716 intel_plane);
3717
3718 /*
3719 * Note: If we start supporting multiple pending atomic commits against
3720 * the same planes/CRTC's in the future, plane->state will no longer be
3721 * the correct pre-state to use for the calculations here and we'll
3722 * need to change where we get the 'unchanged' plane data from.
3723 *
3724 * For now this is fine because we only allow one queued commit against
3725 * a CRTC. Even if the plane isn't modified by this transaction and we
3726 * don't have a plane lock, we still have the CRTC's lock, so we know
3727 * that no other transactions are racing with us to update it.
3728 */
3729 if (!intel_pstate)
3730 intel_pstate = to_intel_plane_state(plane->state);
3731
3732 WARN_ON(!intel_pstate->base.fb);
3733
3734 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3735
3736 ret = skl_compute_plane_wm(dev_priv,
3737 cstate,
3738 intel_pstate,
3739 ddb_blocks,
3740 level,
3741 &result->plane_res_b,
3742 &result->plane_res_l,
3743 &result->plane_en);
3744 if (ret)
3745 return ret;
3746
3747 return 0;
3748 }
3749
3750 static uint32_t
3751 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3752 {
3753 uint32_t pixel_rate;
3754
3755 if (!cstate->base.active)
3756 return 0;
3757
3758 pixel_rate = ilk_pipe_pixel_rate(cstate);
3759
3760 if (WARN_ON(pixel_rate == 0))
3761 return 0;
3762
3763 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3764 pixel_rate);
3765 }
3766
3767 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3768 struct skl_wm_level *trans_wm /* out */)
3769 {
3770 if (!cstate->base.active)
3771 return;
3772
3773 /* Until we know more, just disable transition WMs */
3774 trans_wm->plane_en = false;
3775 }
3776
3777 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3778 struct skl_ddb_allocation *ddb,
3779 struct skl_pipe_wm *pipe_wm)
3780 {
3781 struct drm_device *dev = cstate->base.crtc->dev;
3782 const struct drm_i915_private *dev_priv = to_i915(dev);
3783 struct intel_plane *intel_plane;
3784 struct skl_plane_wm *wm;
3785 int level, max_level = ilk_wm_max_level(dev_priv);
3786 int ret;
3787
3788 /*
3789 * We'll only calculate watermarks for planes that are actually
3790 * enabled, so make sure all other planes are set as disabled.
3791 */
3792 memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3793
3794 for_each_intel_plane_mask(&dev_priv->drm,
3795 intel_plane,
3796 cstate->base.plane_mask) {
3797 wm = &pipe_wm->planes[skl_wm_plane_id(intel_plane)];
3798
3799 for (level = 0; level <= max_level; level++) {
3800 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3801 intel_plane, level,
3802 &wm->wm[level]);
3803 if (ret)
3804 return ret;
3805 }
3806 skl_compute_transition_wm(cstate, &wm->trans_wm);
3807 }
3808 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3809
3810 return 0;
3811 }
3812
3813 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3814 i915_reg_t reg,
3815 const struct skl_ddb_entry *entry)
3816 {
3817 if (entry->end)
3818 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3819 else
3820 I915_WRITE(reg, 0);
3821 }
3822
3823 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
3824 i915_reg_t reg,
3825 const struct skl_wm_level *level)
3826 {
3827 uint32_t val = 0;
3828
3829 if (level->plane_en) {
3830 val |= PLANE_WM_EN;
3831 val |= level->plane_res_b;
3832 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
3833 }
3834
3835 I915_WRITE(reg, val);
3836 }
3837
3838 static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3839 const struct skl_plane_wm *wm,
3840 const struct skl_ddb_allocation *ddb,
3841 int plane)
3842 {
3843 struct drm_crtc *crtc = &intel_crtc->base;
3844 struct drm_device *dev = crtc->dev;
3845 struct drm_i915_private *dev_priv = to_i915(dev);
3846 int level, max_level = ilk_wm_max_level(dev_priv);
3847 enum pipe pipe = intel_crtc->pipe;
3848
3849 for (level = 0; level <= max_level; level++) {
3850 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane, level),
3851 &wm->wm[level]);
3852 }
3853 skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane),
3854 &wm->trans_wm);
3855
3856 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3857 &ddb->plane[pipe][plane]);
3858 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3859 &ddb->y_plane[pipe][plane]);
3860 }
3861
3862 static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3863 const struct skl_plane_wm *wm,
3864 const struct skl_ddb_allocation *ddb)
3865 {
3866 struct drm_crtc *crtc = &intel_crtc->base;
3867 struct drm_device *dev = crtc->dev;
3868 struct drm_i915_private *dev_priv = to_i915(dev);
3869 int level, max_level = ilk_wm_max_level(dev_priv);
3870 enum pipe pipe = intel_crtc->pipe;
3871
3872 for (level = 0; level <= max_level; level++) {
3873 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
3874 &wm->wm[level]);
3875 }
3876 skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
3877
3878 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3879 &ddb->plane[pipe][PLANE_CURSOR]);
3880 }
3881
3882 bool skl_wm_level_equals(const struct skl_wm_level *l1,
3883 const struct skl_wm_level *l2)
3884 {
3885 if (l1->plane_en != l2->plane_en)
3886 return false;
3887
3888 /* If both planes aren't enabled, the rest shouldn't matter */
3889 if (!l1->plane_en)
3890 return true;
3891
3892 return (l1->plane_res_l == l2->plane_res_l &&
3893 l1->plane_res_b == l2->plane_res_b);
3894 }
3895
3896 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3897 const struct skl_ddb_entry *b)
3898 {
3899 return a->start < b->end && b->start < a->end;
3900 }
3901
3902 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
3903 const struct skl_ddb_entry *ddb,
3904 int ignore)
3905 {
3906 int i;
3907
3908 for (i = 0; i < I915_MAX_PIPES; i++)
3909 if (i != ignore && entries[i] &&
3910 skl_ddb_entries_overlap(ddb, entries[i]))
3911 return true;
3912
3913 return false;
3914 }
3915
3916 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3917 const struct skl_pipe_wm *old_pipe_wm,
3918 struct skl_pipe_wm *pipe_wm, /* out */
3919 struct skl_ddb_allocation *ddb, /* out */
3920 bool *changed /* out */)
3921 {
3922 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3923 int ret;
3924
3925 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3926 if (ret)
3927 return ret;
3928
3929 if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
3930 *changed = false;
3931 else
3932 *changed = true;
3933
3934 return 0;
3935 }
3936
3937 static uint32_t
3938 pipes_modified(struct drm_atomic_state *state)
3939 {
3940 struct drm_crtc *crtc;
3941 struct drm_crtc_state *cstate;
3942 uint32_t i, ret = 0;
3943
3944 for_each_crtc_in_state(state, crtc, cstate, i)
3945 ret |= drm_crtc_mask(crtc);
3946
3947 return ret;
3948 }
3949
3950 static int
3951 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3952 {
3953 struct drm_atomic_state *state = cstate->base.state;
3954 struct drm_device *dev = state->dev;
3955 struct drm_crtc *crtc = cstate->base.crtc;
3956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3957 struct drm_i915_private *dev_priv = to_i915(dev);
3958 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3959 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3960 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3961 struct drm_plane_state *plane_state;
3962 struct drm_plane *plane;
3963 enum pipe pipe = intel_crtc->pipe;
3964 int id;
3965
3966 WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3967
3968 drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
3969 id = skl_wm_plane_id(to_intel_plane(plane));
3970
3971 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
3972 &new_ddb->plane[pipe][id]) &&
3973 skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
3974 &new_ddb->y_plane[pipe][id]))
3975 continue;
3976
3977 plane_state = drm_atomic_get_plane_state(state, plane);
3978 if (IS_ERR(plane_state))
3979 return PTR_ERR(plane_state);
3980 }
3981
3982 return 0;
3983 }
3984
3985 static int
3986 skl_compute_ddb(struct drm_atomic_state *state)
3987 {
3988 struct drm_device *dev = state->dev;
3989 struct drm_i915_private *dev_priv = to_i915(dev);
3990 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3991 struct intel_crtc *intel_crtc;
3992 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
3993 uint32_t realloc_pipes = pipes_modified(state);
3994 int ret;
3995
3996 /*
3997 * If this is our first atomic update following hardware readout,
3998 * we can't trust the DDB that the BIOS programmed for us. Let's
3999 * pretend that all pipes switched active status so that we'll
4000 * ensure a full DDB recompute.
4001 */
4002 if (dev_priv->wm.distrust_bios_wm) {
4003 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4004 state->acquire_ctx);
4005 if (ret)
4006 return ret;
4007
4008 intel_state->active_pipe_changes = ~0;
4009
4010 /*
4011 * We usually only initialize intel_state->active_crtcs if we
4012 * we're doing a modeset; make sure this field is always
4013 * initialized during the sanitization process that happens
4014 * on the first commit too.
4015 */
4016 if (!intel_state->modeset)
4017 intel_state->active_crtcs = dev_priv->active_crtcs;
4018 }
4019
4020 /*
4021 * If the modeset changes which CRTC's are active, we need to
4022 * recompute the DDB allocation for *all* active pipes, even
4023 * those that weren't otherwise being modified in any way by this
4024 * atomic commit. Due to the shrinking of the per-pipe allocations
4025 * when new active CRTC's are added, it's possible for a pipe that
4026 * we were already using and aren't changing at all here to suddenly
4027 * become invalid if its DDB needs exceeds its new allocation.
4028 *
4029 * Note that if we wind up doing a full DDB recompute, we can't let
4030 * any other display updates race with this transaction, so we need
4031 * to grab the lock on *all* CRTC's.
4032 */
4033 if (intel_state->active_pipe_changes) {
4034 realloc_pipes = ~0;
4035 intel_state->wm_results.dirty_pipes = ~0;
4036 }
4037
4038 /*
4039 * We're not recomputing for the pipes not included in the commit, so
4040 * make sure we start with the current state.
4041 */
4042 memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4043
4044 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4045 struct intel_crtc_state *cstate;
4046
4047 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4048 if (IS_ERR(cstate))
4049 return PTR_ERR(cstate);
4050
4051 ret = skl_allocate_pipe_ddb(cstate, ddb);
4052 if (ret)
4053 return ret;
4054
4055 ret = skl_ddb_add_affected_planes(cstate);
4056 if (ret)
4057 return ret;
4058 }
4059
4060 return 0;
4061 }
4062
4063 static void
4064 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4065 struct skl_wm_values *src,
4066 enum pipe pipe)
4067 {
4068 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4069 sizeof(dst->ddb.y_plane[pipe]));
4070 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4071 sizeof(dst->ddb.plane[pipe]));
4072 }
4073
4074 static void
4075 skl_print_wm_changes(const struct drm_atomic_state *state)
4076 {
4077 const struct drm_device *dev = state->dev;
4078 const struct drm_i915_private *dev_priv = to_i915(dev);
4079 const struct intel_atomic_state *intel_state =
4080 to_intel_atomic_state(state);
4081 const struct drm_crtc *crtc;
4082 const struct drm_crtc_state *cstate;
4083 const struct intel_plane *intel_plane;
4084 const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4085 const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4086 int id;
4087 int i;
4088
4089 for_each_crtc_in_state(state, crtc, cstate, i) {
4090 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4091 enum pipe pipe = intel_crtc->pipe;
4092
4093 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4094 const struct skl_ddb_entry *old, *new;
4095
4096 id = skl_wm_plane_id(intel_plane);
4097 old = &old_ddb->plane[pipe][id];
4098 new = &new_ddb->plane[pipe][id];
4099
4100 if (skl_ddb_entry_equal(old, new))
4101 continue;
4102
4103 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4104 intel_plane->base.base.id,
4105 intel_plane->base.name,
4106 old->start, old->end,
4107 new->start, new->end);
4108 }
4109 }
4110 }
4111
4112 static int
4113 skl_compute_wm(struct drm_atomic_state *state)
4114 {
4115 struct drm_crtc *crtc;
4116 struct drm_crtc_state *cstate;
4117 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4118 struct skl_wm_values *results = &intel_state->wm_results;
4119 struct skl_pipe_wm *pipe_wm;
4120 bool changed = false;
4121 int ret, i;
4122
4123 /*
4124 * If this transaction isn't actually touching any CRTC's, don't
4125 * bother with watermark calculation. Note that if we pass this
4126 * test, we're guaranteed to hold at least one CRTC state mutex,
4127 * which means we can safely use values like dev_priv->active_crtcs
4128 * since any racing commits that want to update them would need to
4129 * hold _all_ CRTC state mutexes.
4130 */
4131 for_each_crtc_in_state(state, crtc, cstate, i)
4132 changed = true;
4133 if (!changed)
4134 return 0;
4135
4136 /* Clear all dirty flags */
4137 results->dirty_pipes = 0;
4138
4139 ret = skl_compute_ddb(state);
4140 if (ret)
4141 return ret;
4142
4143 /*
4144 * Calculate WM's for all pipes that are part of this transaction.
4145 * Note that the DDB allocation above may have added more CRTC's that
4146 * weren't otherwise being modified (and set bits in dirty_pipes) if
4147 * pipe allocations had to change.
4148 *
4149 * FIXME: Now that we're doing this in the atomic check phase, we
4150 * should allow skl_update_pipe_wm() to return failure in cases where
4151 * no suitable watermark values can be found.
4152 */
4153 for_each_crtc_in_state(state, crtc, cstate, i) {
4154 struct intel_crtc_state *intel_cstate =
4155 to_intel_crtc_state(cstate);
4156 const struct skl_pipe_wm *old_pipe_wm =
4157 &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
4158
4159 pipe_wm = &intel_cstate->wm.skl.optimal;
4160 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
4161 &results->ddb, &changed);
4162 if (ret)
4163 return ret;
4164
4165 if (changed)
4166 results->dirty_pipes |= drm_crtc_mask(crtc);
4167
4168 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4169 /* This pipe's WM's did not change */
4170 continue;
4171
4172 intel_cstate->update_wm_pre = true;
4173 }
4174
4175 skl_print_wm_changes(state);
4176
4177 return 0;
4178 }
4179
4180 static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
4181 struct intel_crtc_state *cstate)
4182 {
4183 struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
4184 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4185 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4186 const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
4187 enum pipe pipe = crtc->pipe;
4188 int plane;
4189
4190 if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
4191 return;
4192
4193 I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
4194
4195 for_each_universal_plane(dev_priv, pipe, plane)
4196 skl_write_plane_wm(crtc, &pipe_wm->planes[plane], ddb, plane);
4197
4198 skl_write_cursor_wm(crtc, &pipe_wm->planes[PLANE_CURSOR], ddb);
4199 }
4200
4201 static void skl_initial_wm(struct intel_atomic_state *state,
4202 struct intel_crtc_state *cstate)
4203 {
4204 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4205 struct drm_device *dev = intel_crtc->base.dev;
4206 struct drm_i915_private *dev_priv = to_i915(dev);
4207 struct skl_wm_values *results = &state->wm_results;
4208 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4209 enum pipe pipe = intel_crtc->pipe;
4210
4211 if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
4212 return;
4213
4214 mutex_lock(&dev_priv->wm.wm_mutex);
4215
4216 if (cstate->base.active_changed)
4217 skl_atomic_update_crtc_wm(state, cstate);
4218
4219 skl_copy_wm_for_pipe(hw_vals, results, pipe);
4220
4221 mutex_unlock(&dev_priv->wm.wm_mutex);
4222 }
4223
4224 static void ilk_compute_wm_config(struct drm_device *dev,
4225 struct intel_wm_config *config)
4226 {
4227 struct intel_crtc *crtc;
4228
4229 /* Compute the currently _active_ config */
4230 for_each_intel_crtc(dev, crtc) {
4231 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4232
4233 if (!wm->pipe_enabled)
4234 continue;
4235
4236 config->sprites_enabled |= wm->sprites_enabled;
4237 config->sprites_scaled |= wm->sprites_scaled;
4238 config->num_pipes_active++;
4239 }
4240 }
4241
4242 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4243 {
4244 struct drm_device *dev = &dev_priv->drm;
4245 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4246 struct ilk_wm_maximums max;
4247 struct intel_wm_config config = {};
4248 struct ilk_wm_values results = {};
4249 enum intel_ddb_partitioning partitioning;
4250
4251 ilk_compute_wm_config(dev, &config);
4252
4253 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4254 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4255
4256 /* 5/6 split only in single pipe config on IVB+ */
4257 if (INTEL_GEN(dev_priv) >= 7 &&
4258 config.num_pipes_active == 1 && config.sprites_enabled) {
4259 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4260 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4261
4262 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4263 } else {
4264 best_lp_wm = &lp_wm_1_2;
4265 }
4266
4267 partitioning = (best_lp_wm == &lp_wm_1_2) ?
4268 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4269
4270 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4271
4272 ilk_write_wm_values(dev_priv, &results);
4273 }
4274
4275 static void ilk_initial_watermarks(struct intel_atomic_state *state,
4276 struct intel_crtc_state *cstate)
4277 {
4278 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4279 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4280
4281 mutex_lock(&dev_priv->wm.wm_mutex);
4282 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4283 ilk_program_watermarks(dev_priv);
4284 mutex_unlock(&dev_priv->wm.wm_mutex);
4285 }
4286
4287 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
4288 struct intel_crtc_state *cstate)
4289 {
4290 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4291 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4292
4293 mutex_lock(&dev_priv->wm.wm_mutex);
4294 if (cstate->wm.need_postvbl_update) {
4295 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4296 ilk_program_watermarks(dev_priv);
4297 }
4298 mutex_unlock(&dev_priv->wm.wm_mutex);
4299 }
4300
4301 static inline void skl_wm_level_from_reg_val(uint32_t val,
4302 struct skl_wm_level *level)
4303 {
4304 level->plane_en = val & PLANE_WM_EN;
4305 level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4306 level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
4307 PLANE_WM_LINES_MASK;
4308 }
4309
4310 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
4311 struct skl_pipe_wm *out)
4312 {
4313 struct drm_device *dev = crtc->dev;
4314 struct drm_i915_private *dev_priv = to_i915(dev);
4315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4316 struct intel_plane *intel_plane;
4317 struct skl_plane_wm *wm;
4318 enum pipe pipe = intel_crtc->pipe;
4319 int level, id, max_level;
4320 uint32_t val;
4321
4322 max_level = ilk_wm_max_level(dev_priv);
4323
4324 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4325 id = skl_wm_plane_id(intel_plane);
4326 wm = &out->planes[id];
4327
4328 for (level = 0; level <= max_level; level++) {
4329 if (id != PLANE_CURSOR)
4330 val = I915_READ(PLANE_WM(pipe, id, level));
4331 else
4332 val = I915_READ(CUR_WM(pipe, level));
4333
4334 skl_wm_level_from_reg_val(val, &wm->wm[level]);
4335 }
4336
4337 if (id != PLANE_CURSOR)
4338 val = I915_READ(PLANE_WM_TRANS(pipe, id));
4339 else
4340 val = I915_READ(CUR_WM_TRANS(pipe));
4341
4342 skl_wm_level_from_reg_val(val, &wm->trans_wm);
4343 }
4344
4345 if (!intel_crtc->active)
4346 return;
4347
4348 out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
4349 }
4350
4351 void skl_wm_get_hw_state(struct drm_device *dev)
4352 {
4353 struct drm_i915_private *dev_priv = to_i915(dev);
4354 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4355 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4356 struct drm_crtc *crtc;
4357 struct intel_crtc *intel_crtc;
4358 struct intel_crtc_state *cstate;
4359
4360 skl_ddb_get_hw_state(dev_priv, ddb);
4361 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4362 intel_crtc = to_intel_crtc(crtc);
4363 cstate = to_intel_crtc_state(crtc->state);
4364
4365 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
4366
4367 if (intel_crtc->active)
4368 hw->dirty_pipes |= drm_crtc_mask(crtc);
4369 }
4370
4371 if (dev_priv->active_crtcs) {
4372 /* Fully recompute DDB on first atomic commit */
4373 dev_priv->wm.distrust_bios_wm = true;
4374 } else {
4375 /* Easy/common case; just sanitize DDB now if everything off */
4376 memset(ddb, 0, sizeof(*ddb));
4377 }
4378 }
4379
4380 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4381 {
4382 struct drm_device *dev = crtc->dev;
4383 struct drm_i915_private *dev_priv = to_i915(dev);
4384 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4386 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4387 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4388 enum pipe pipe = intel_crtc->pipe;
4389 static const i915_reg_t wm0_pipe_reg[] = {
4390 [PIPE_A] = WM0_PIPEA_ILK,
4391 [PIPE_B] = WM0_PIPEB_ILK,
4392 [PIPE_C] = WM0_PIPEC_IVB,
4393 };
4394
4395 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4396 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4397 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4398
4399 memset(active, 0, sizeof(*active));
4400
4401 active->pipe_enabled = intel_crtc->active;
4402
4403 if (active->pipe_enabled) {
4404 u32 tmp = hw->wm_pipe[pipe];
4405
4406 /*
4407 * For active pipes LP0 watermark is marked as
4408 * enabled, and LP1+ watermaks as disabled since
4409 * we can't really reverse compute them in case
4410 * multiple pipes are active.
4411 */
4412 active->wm[0].enable = true;
4413 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4414 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4415 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4416 active->linetime = hw->wm_linetime[pipe];
4417 } else {
4418 int level, max_level = ilk_wm_max_level(dev_priv);
4419
4420 /*
4421 * For inactive pipes, all watermark levels
4422 * should be marked as enabled but zeroed,
4423 * which is what we'd compute them to.
4424 */
4425 for (level = 0; level <= max_level; level++)
4426 active->wm[level].enable = true;
4427 }
4428
4429 intel_crtc->wm.active.ilk = *active;
4430 }
4431
4432 #define _FW_WM(value, plane) \
4433 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4434 #define _FW_WM_VLV(value, plane) \
4435 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4436
4437 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4438 struct vlv_wm_values *wm)
4439 {
4440 enum pipe pipe;
4441 uint32_t tmp;
4442
4443 for_each_pipe(dev_priv, pipe) {
4444 tmp = I915_READ(VLV_DDL(pipe));
4445
4446 wm->ddl[pipe].primary =
4447 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4448 wm->ddl[pipe].cursor =
4449 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4450 wm->ddl[pipe].sprite[0] =
4451 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4452 wm->ddl[pipe].sprite[1] =
4453 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4454 }
4455
4456 tmp = I915_READ(DSPFW1);
4457 wm->sr.plane = _FW_WM(tmp, SR);
4458 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4459 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4460 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4461
4462 tmp = I915_READ(DSPFW2);
4463 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4464 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4465 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4466
4467 tmp = I915_READ(DSPFW3);
4468 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4469
4470 if (IS_CHERRYVIEW(dev_priv)) {
4471 tmp = I915_READ(DSPFW7_CHV);
4472 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4473 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4474
4475 tmp = I915_READ(DSPFW8_CHV);
4476 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4477 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4478
4479 tmp = I915_READ(DSPFW9_CHV);
4480 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4481 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4482
4483 tmp = I915_READ(DSPHOWM);
4484 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4485 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4486 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4487 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4488 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4489 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4490 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4491 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4492 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4493 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4494 } else {
4495 tmp = I915_READ(DSPFW7);
4496 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4497 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4498
4499 tmp = I915_READ(DSPHOWM);
4500 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4501 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4502 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4503 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4504 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4505 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4506 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4507 }
4508 }
4509
4510 #undef _FW_WM
4511 #undef _FW_WM_VLV
4512
4513 void vlv_wm_get_hw_state(struct drm_device *dev)
4514 {
4515 struct drm_i915_private *dev_priv = to_i915(dev);
4516 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4517 struct intel_plane *plane;
4518 enum pipe pipe;
4519 u32 val;
4520
4521 vlv_read_wm_values(dev_priv, wm);
4522
4523 for_each_intel_plane(dev, plane) {
4524 switch (plane->base.type) {
4525 int sprite;
4526 case DRM_PLANE_TYPE_CURSOR:
4527 plane->wm.fifo_size = 63;
4528 break;
4529 case DRM_PLANE_TYPE_PRIMARY:
4530 plane->wm.fifo_size = vlv_get_fifo_size(dev_priv, plane->pipe, 0);
4531 break;
4532 case DRM_PLANE_TYPE_OVERLAY:
4533 sprite = plane->plane;
4534 plane->wm.fifo_size = vlv_get_fifo_size(dev_priv, plane->pipe, sprite + 1);
4535 break;
4536 }
4537 }
4538
4539 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4540 wm->level = VLV_WM_LEVEL_PM2;
4541
4542 if (IS_CHERRYVIEW(dev_priv)) {
4543 mutex_lock(&dev_priv->rps.hw_lock);
4544
4545 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4546 if (val & DSP_MAXFIFO_PM5_ENABLE)
4547 wm->level = VLV_WM_LEVEL_PM5;
4548
4549 /*
4550 * If DDR DVFS is disabled in the BIOS, Punit
4551 * will never ack the request. So if that happens
4552 * assume we don't have to enable/disable DDR DVFS
4553 * dynamically. To test that just set the REQ_ACK
4554 * bit to poke the Punit, but don't change the
4555 * HIGH/LOW bits so that we don't actually change
4556 * the current state.
4557 */
4558 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4559 val |= FORCE_DDR_FREQ_REQ_ACK;
4560 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4561
4562 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4563 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4564 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4565 "assuming DDR DVFS is disabled\n");
4566 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4567 } else {
4568 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4569 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4570 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4571 }
4572
4573 mutex_unlock(&dev_priv->rps.hw_lock);
4574 }
4575
4576 for_each_pipe(dev_priv, pipe)
4577 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4578 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4579 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4580
4581 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4582 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4583 }
4584
4585 void ilk_wm_get_hw_state(struct drm_device *dev)
4586 {
4587 struct drm_i915_private *dev_priv = to_i915(dev);
4588 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4589 struct drm_crtc *crtc;
4590
4591 for_each_crtc(dev, crtc)
4592 ilk_pipe_wm_get_hw_state(crtc);
4593
4594 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4595 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4596 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4597
4598 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4599 if (INTEL_GEN(dev_priv) >= 7) {
4600 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4601 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4602 }
4603
4604 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4605 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4606 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4607 else if (IS_IVYBRIDGE(dev_priv))
4608 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4609 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4610
4611 hw->enable_fbc_wm =
4612 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4613 }
4614
4615 /**
4616 * intel_update_watermarks - update FIFO watermark values based on current modes
4617 *
4618 * Calculate watermark values for the various WM regs based on current mode
4619 * and plane configuration.
4620 *
4621 * There are several cases to deal with here:
4622 * - normal (i.e. non-self-refresh)
4623 * - self-refresh (SR) mode
4624 * - lines are large relative to FIFO size (buffer can hold up to 2)
4625 * - lines are small relative to FIFO size (buffer can hold more than 2
4626 * lines), so need to account for TLB latency
4627 *
4628 * The normal calculation is:
4629 * watermark = dotclock * bytes per pixel * latency
4630 * where latency is platform & configuration dependent (we assume pessimal
4631 * values here).
4632 *
4633 * The SR calculation is:
4634 * watermark = (trunc(latency/line time)+1) * surface width *
4635 * bytes per pixel
4636 * where
4637 * line time = htotal / dotclock
4638 * surface width = hdisplay for normal plane and 64 for cursor
4639 * and latency is assumed to be high, as above.
4640 *
4641 * The final value programmed to the register should always be rounded up,
4642 * and include an extra 2 entries to account for clock crossings.
4643 *
4644 * We don't use the sprite, so we can ignore that. And on Crestline we have
4645 * to set the non-SR watermarks to 8.
4646 */
4647 void intel_update_watermarks(struct intel_crtc *crtc)
4648 {
4649 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4650
4651 if (dev_priv->display.update_wm)
4652 dev_priv->display.update_wm(crtc);
4653 }
4654
4655 /*
4656 * Lock protecting IPS related data structures
4657 */
4658 DEFINE_SPINLOCK(mchdev_lock);
4659
4660 /* Global for IPS driver to get at the current i915 device. Protected by
4661 * mchdev_lock. */
4662 static struct drm_i915_private *i915_mch_dev;
4663
4664 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4665 {
4666 u16 rgvswctl;
4667
4668 assert_spin_locked(&mchdev_lock);
4669
4670 rgvswctl = I915_READ16(MEMSWCTL);
4671 if (rgvswctl & MEMCTL_CMD_STS) {
4672 DRM_DEBUG("gpu busy, RCS change rejected\n");
4673 return false; /* still busy with another command */
4674 }
4675
4676 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4677 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4678 I915_WRITE16(MEMSWCTL, rgvswctl);
4679 POSTING_READ16(MEMSWCTL);
4680
4681 rgvswctl |= MEMCTL_CMD_STS;
4682 I915_WRITE16(MEMSWCTL, rgvswctl);
4683
4684 return true;
4685 }
4686
4687 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4688 {
4689 u32 rgvmodectl;
4690 u8 fmax, fmin, fstart, vstart;
4691
4692 spin_lock_irq(&mchdev_lock);
4693
4694 rgvmodectl = I915_READ(MEMMODECTL);
4695
4696 /* Enable temp reporting */
4697 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4698 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4699
4700 /* 100ms RC evaluation intervals */
4701 I915_WRITE(RCUPEI, 100000);
4702 I915_WRITE(RCDNEI, 100000);
4703
4704 /* Set max/min thresholds to 90ms and 80ms respectively */
4705 I915_WRITE(RCBMAXAVG, 90000);
4706 I915_WRITE(RCBMINAVG, 80000);
4707
4708 I915_WRITE(MEMIHYST, 1);
4709
4710 /* Set up min, max, and cur for interrupt handling */
4711 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4712 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4713 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4714 MEMMODE_FSTART_SHIFT;
4715
4716 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4717 PXVFREQ_PX_SHIFT;
4718
4719 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4720 dev_priv->ips.fstart = fstart;
4721
4722 dev_priv->ips.max_delay = fstart;
4723 dev_priv->ips.min_delay = fmin;
4724 dev_priv->ips.cur_delay = fstart;
4725
4726 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4727 fmax, fmin, fstart);
4728
4729 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4730
4731 /*
4732 * Interrupts will be enabled in ironlake_irq_postinstall
4733 */
4734
4735 I915_WRITE(VIDSTART, vstart);
4736 POSTING_READ(VIDSTART);
4737
4738 rgvmodectl |= MEMMODE_SWMODE_EN;
4739 I915_WRITE(MEMMODECTL, rgvmodectl);
4740
4741 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4742 DRM_ERROR("stuck trying to change perf mode\n");
4743 mdelay(1);
4744
4745 ironlake_set_drps(dev_priv, fstart);
4746
4747 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4748 I915_READ(DDREC) + I915_READ(CSIEC);
4749 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4750 dev_priv->ips.last_count2 = I915_READ(GFXEC);
4751 dev_priv->ips.last_time2 = ktime_get_raw_ns();
4752
4753 spin_unlock_irq(&mchdev_lock);
4754 }
4755
4756 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4757 {
4758 u16 rgvswctl;
4759
4760 spin_lock_irq(&mchdev_lock);
4761
4762 rgvswctl = I915_READ16(MEMSWCTL);
4763
4764 /* Ack interrupts, disable EFC interrupt */
4765 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4766 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4767 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4768 I915_WRITE(DEIIR, DE_PCU_EVENT);
4769 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4770
4771 /* Go back to the starting frequency */
4772 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4773 mdelay(1);
4774 rgvswctl |= MEMCTL_CMD_STS;
4775 I915_WRITE(MEMSWCTL, rgvswctl);
4776 mdelay(1);
4777
4778 spin_unlock_irq(&mchdev_lock);
4779 }
4780
4781 /* There's a funny hw issue where the hw returns all 0 when reading from
4782 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4783 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4784 * all limits and the gpu stuck at whatever frequency it is at atm).
4785 */
4786 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4787 {
4788 u32 limits;
4789
4790 /* Only set the down limit when we've reached the lowest level to avoid
4791 * getting more interrupts, otherwise leave this clear. This prevents a
4792 * race in the hw when coming out of rc6: There's a tiny window where
4793 * the hw runs at the minimal clock before selecting the desired
4794 * frequency, if the down threshold expires in that window we will not
4795 * receive a down interrupt. */
4796 if (IS_GEN9(dev_priv)) {
4797 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4798 if (val <= dev_priv->rps.min_freq_softlimit)
4799 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4800 } else {
4801 limits = dev_priv->rps.max_freq_softlimit << 24;
4802 if (val <= dev_priv->rps.min_freq_softlimit)
4803 limits |= dev_priv->rps.min_freq_softlimit << 16;
4804 }
4805
4806 return limits;
4807 }
4808
4809 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4810 {
4811 int new_power;
4812 u32 threshold_up = 0, threshold_down = 0; /* in % */
4813 u32 ei_up = 0, ei_down = 0;
4814
4815 new_power = dev_priv->rps.power;
4816 switch (dev_priv->rps.power) {
4817 case LOW_POWER:
4818 if (val > dev_priv->rps.efficient_freq + 1 &&
4819 val > dev_priv->rps.cur_freq)
4820 new_power = BETWEEN;
4821 break;
4822
4823 case BETWEEN:
4824 if (val <= dev_priv->rps.efficient_freq &&
4825 val < dev_priv->rps.cur_freq)
4826 new_power = LOW_POWER;
4827 else if (val >= dev_priv->rps.rp0_freq &&
4828 val > dev_priv->rps.cur_freq)
4829 new_power = HIGH_POWER;
4830 break;
4831
4832 case HIGH_POWER:
4833 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4834 val < dev_priv->rps.cur_freq)
4835 new_power = BETWEEN;
4836 break;
4837 }
4838 /* Max/min bins are special */
4839 if (val <= dev_priv->rps.min_freq_softlimit)
4840 new_power = LOW_POWER;
4841 if (val >= dev_priv->rps.max_freq_softlimit)
4842 new_power = HIGH_POWER;
4843 if (new_power == dev_priv->rps.power)
4844 return;
4845
4846 /* Note the units here are not exactly 1us, but 1280ns. */
4847 switch (new_power) {
4848 case LOW_POWER:
4849 /* Upclock if more than 95% busy over 16ms */
4850 ei_up = 16000;
4851 threshold_up = 95;
4852
4853 /* Downclock if less than 85% busy over 32ms */
4854 ei_down = 32000;
4855 threshold_down = 85;
4856 break;
4857
4858 case BETWEEN:
4859 /* Upclock if more than 90% busy over 13ms */
4860 ei_up = 13000;
4861 threshold_up = 90;
4862
4863 /* Downclock if less than 75% busy over 32ms */
4864 ei_down = 32000;
4865 threshold_down = 75;
4866 break;
4867
4868 case HIGH_POWER:
4869 /* Upclock if more than 85% busy over 10ms */
4870 ei_up = 10000;
4871 threshold_up = 85;
4872
4873 /* Downclock if less than 60% busy over 32ms */
4874 ei_down = 32000;
4875 threshold_down = 60;
4876 break;
4877 }
4878
4879 I915_WRITE(GEN6_RP_UP_EI,
4880 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4881 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4882 GT_INTERVAL_FROM_US(dev_priv,
4883 ei_up * threshold_up / 100));
4884
4885 I915_WRITE(GEN6_RP_DOWN_EI,
4886 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4887 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4888 GT_INTERVAL_FROM_US(dev_priv,
4889 ei_down * threshold_down / 100));
4890
4891 I915_WRITE(GEN6_RP_CONTROL,
4892 GEN6_RP_MEDIA_TURBO |
4893 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4894 GEN6_RP_MEDIA_IS_GFX |
4895 GEN6_RP_ENABLE |
4896 GEN6_RP_UP_BUSY_AVG |
4897 GEN6_RP_DOWN_IDLE_AVG);
4898
4899 dev_priv->rps.power = new_power;
4900 dev_priv->rps.up_threshold = threshold_up;
4901 dev_priv->rps.down_threshold = threshold_down;
4902 dev_priv->rps.last_adj = 0;
4903 }
4904
4905 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4906 {
4907 u32 mask = 0;
4908
4909 if (val > dev_priv->rps.min_freq_softlimit)
4910 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4911 if (val < dev_priv->rps.max_freq_softlimit)
4912 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4913
4914 mask &= dev_priv->pm_rps_events;
4915
4916 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4917 }
4918
4919 /* gen6_set_rps is called to update the frequency request, but should also be
4920 * called when the range (min_delay and max_delay) is modified so that we can
4921 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4922 static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4923 {
4924 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4925 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4926 return;
4927
4928 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4929 WARN_ON(val > dev_priv->rps.max_freq);
4930 WARN_ON(val < dev_priv->rps.min_freq);
4931
4932 /* min/max delay may still have been modified so be sure to
4933 * write the limits value.
4934 */
4935 if (val != dev_priv->rps.cur_freq) {
4936 gen6_set_rps_thresholds(dev_priv, val);
4937
4938 if (IS_GEN9(dev_priv))
4939 I915_WRITE(GEN6_RPNSWREQ,
4940 GEN9_FREQUENCY(val));
4941 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4942 I915_WRITE(GEN6_RPNSWREQ,
4943 HSW_FREQUENCY(val));
4944 else
4945 I915_WRITE(GEN6_RPNSWREQ,
4946 GEN6_FREQUENCY(val) |
4947 GEN6_OFFSET(0) |
4948 GEN6_AGGRESSIVE_TURBO);
4949 }
4950
4951 /* Make sure we continue to get interrupts
4952 * until we hit the minimum or maximum frequencies.
4953 */
4954 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4955 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4956
4957 POSTING_READ(GEN6_RPNSWREQ);
4958
4959 dev_priv->rps.cur_freq = val;
4960 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4961 }
4962
4963 static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4964 {
4965 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4966 WARN_ON(val > dev_priv->rps.max_freq);
4967 WARN_ON(val < dev_priv->rps.min_freq);
4968
4969 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4970 "Odd GPU freq value\n"))
4971 val &= ~1;
4972
4973 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4974
4975 if (val != dev_priv->rps.cur_freq) {
4976 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4977 if (!IS_CHERRYVIEW(dev_priv))
4978 gen6_set_rps_thresholds(dev_priv, val);
4979 }
4980
4981 dev_priv->rps.cur_freq = val;
4982 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4983 }
4984
4985 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4986 *
4987 * * If Gfx is Idle, then
4988 * 1. Forcewake Media well.
4989 * 2. Request idle freq.
4990 * 3. Release Forcewake of Media well.
4991 */
4992 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4993 {
4994 u32 val = dev_priv->rps.idle_freq;
4995
4996 if (dev_priv->rps.cur_freq <= val)
4997 return;
4998
4999 /* Wake up the media well, as that takes a lot less
5000 * power than the Render well. */
5001 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
5002 valleyview_set_rps(dev_priv, val);
5003 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
5004 }
5005
5006 void gen6_rps_busy(struct drm_i915_private *dev_priv)
5007 {
5008 mutex_lock(&dev_priv->rps.hw_lock);
5009 if (dev_priv->rps.enabled) {
5010 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5011 gen6_rps_reset_ei(dev_priv);
5012 I915_WRITE(GEN6_PMINTRMSK,
5013 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
5014
5015 gen6_enable_rps_interrupts(dev_priv);
5016
5017 /* Ensure we start at the user's desired frequency */
5018 intel_set_rps(dev_priv,
5019 clamp(dev_priv->rps.cur_freq,
5020 dev_priv->rps.min_freq_softlimit,
5021 dev_priv->rps.max_freq_softlimit));
5022 }
5023 mutex_unlock(&dev_priv->rps.hw_lock);
5024 }
5025
5026 void gen6_rps_idle(struct drm_i915_private *dev_priv)
5027 {
5028 /* Flush our bottom-half so that it does not race with us
5029 * setting the idle frequency and so that it is bounded by
5030 * our rpm wakeref. And then disable the interrupts to stop any
5031 * futher RPS reclocking whilst we are asleep.
5032 */
5033 gen6_disable_rps_interrupts(dev_priv);
5034
5035 mutex_lock(&dev_priv->rps.hw_lock);
5036 if (dev_priv->rps.enabled) {
5037 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5038 vlv_set_rps_idle(dev_priv);
5039 else
5040 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5041 dev_priv->rps.last_adj = 0;
5042 I915_WRITE(GEN6_PMINTRMSK,
5043 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
5044 }
5045 mutex_unlock(&dev_priv->rps.hw_lock);
5046
5047 spin_lock(&dev_priv->rps.client_lock);
5048 while (!list_empty(&dev_priv->rps.clients))
5049 list_del_init(dev_priv->rps.clients.next);
5050 spin_unlock(&dev_priv->rps.client_lock);
5051 }
5052
5053 void gen6_rps_boost(struct drm_i915_private *dev_priv,
5054 struct intel_rps_client *rps,
5055 unsigned long submitted)
5056 {
5057 /* This is intentionally racy! We peek at the state here, then
5058 * validate inside the RPS worker.
5059 */
5060 if (!(dev_priv->gt.awake &&
5061 dev_priv->rps.enabled &&
5062 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
5063 return;
5064
5065 /* Force a RPS boost (and don't count it against the client) if
5066 * the GPU is severely congested.
5067 */
5068 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
5069 rps = NULL;
5070
5071 spin_lock(&dev_priv->rps.client_lock);
5072 if (rps == NULL || list_empty(&rps->link)) {
5073 spin_lock_irq(&dev_priv->irq_lock);
5074 if (dev_priv->rps.interrupts_enabled) {
5075 dev_priv->rps.client_boost = true;
5076 schedule_work(&dev_priv->rps.work);
5077 }
5078 spin_unlock_irq(&dev_priv->irq_lock);
5079
5080 if (rps != NULL) {
5081 list_add(&rps->link, &dev_priv->rps.clients);
5082 rps->boosts++;
5083 } else
5084 dev_priv->rps.boosts++;
5085 }
5086 spin_unlock(&dev_priv->rps.client_lock);
5087 }
5088
5089 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
5090 {
5091 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5092 valleyview_set_rps(dev_priv, val);
5093 else
5094 gen6_set_rps(dev_priv, val);
5095 }
5096
5097 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
5098 {
5099 I915_WRITE(GEN6_RC_CONTROL, 0);
5100 I915_WRITE(GEN9_PG_ENABLE, 0);
5101 }
5102
5103 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
5104 {
5105 I915_WRITE(GEN6_RP_CONTROL, 0);
5106 }
5107
5108 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
5109 {
5110 I915_WRITE(GEN6_RC_CONTROL, 0);
5111 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
5112 I915_WRITE(GEN6_RP_CONTROL, 0);
5113 }
5114
5115 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
5116 {
5117 I915_WRITE(GEN6_RC_CONTROL, 0);
5118 }
5119
5120 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
5121 {
5122 /* we're doing forcewake before Disabling RC6,
5123 * This what the BIOS expects when going into suspend */
5124 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5125
5126 I915_WRITE(GEN6_RC_CONTROL, 0);
5127
5128 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5129 }
5130
5131 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
5132 {
5133 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5134 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5135 mode = GEN6_RC_CTL_RC6_ENABLE;
5136 else
5137 mode = 0;
5138 }
5139 if (HAS_RC6p(dev_priv))
5140 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5141 "RC6 %s RC6p %s RC6pp %s\n",
5142 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5143 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5144 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
5145
5146 else
5147 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5148 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
5149 }
5150
5151 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
5152 {
5153 struct i915_ggtt *ggtt = &dev_priv->ggtt;
5154 bool enable_rc6 = true;
5155 unsigned long rc6_ctx_base;
5156 u32 rc_ctl;
5157 int rc_sw_target;
5158
5159 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5160 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5161 RC_SW_TARGET_STATE_SHIFT;
5162 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5163 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5164 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5165 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5166 rc_sw_target);
5167
5168 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
5169 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5170 enable_rc6 = false;
5171 }
5172
5173 /*
5174 * The exact context size is not known for BXT, so assume a page size
5175 * for this check.
5176 */
5177 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
5178 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5179 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5180 ggtt->stolen_reserved_size))) {
5181 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5182 enable_rc6 = false;
5183 }
5184
5185 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5186 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5187 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5188 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
5189 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5190 enable_rc6 = false;
5191 }
5192
5193 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5194 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5195 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5196 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5197 enable_rc6 = false;
5198 }
5199
5200 if (!I915_READ(GEN6_GFXPAUSE)) {
5201 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5202 enable_rc6 = false;
5203 }
5204
5205 if (!I915_READ(GEN8_MISC_CTRL0)) {
5206 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5207 enable_rc6 = false;
5208 }
5209
5210 return enable_rc6;
5211 }
5212
5213 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
5214 {
5215 /* No RC6 before Ironlake and code is gone for ilk. */
5216 if (INTEL_INFO(dev_priv)->gen < 6)
5217 return 0;
5218
5219 if (!enable_rc6)
5220 return 0;
5221
5222 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5223 DRM_INFO("RC6 disabled by BIOS\n");
5224 return 0;
5225 }
5226
5227 /* Respect the kernel parameter if it is set */
5228 if (enable_rc6 >= 0) {
5229 int mask;
5230
5231 if (HAS_RC6p(dev_priv))
5232 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5233 INTEL_RC6pp_ENABLE;
5234 else
5235 mask = INTEL_RC6_ENABLE;
5236
5237 if ((enable_rc6 & mask) != enable_rc6)
5238 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5239 "(requested %d, valid %d)\n",
5240 enable_rc6 & mask, enable_rc6, mask);
5241
5242 return enable_rc6 & mask;
5243 }
5244
5245 if (IS_IVYBRIDGE(dev_priv))
5246 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5247
5248 return INTEL_RC6_ENABLE;
5249 }
5250
5251 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5252 {
5253 /* All of these values are in units of 50MHz */
5254
5255 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5256 if (IS_BROXTON(dev_priv)) {
5257 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5258 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5259 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5260 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5261 } else {
5262 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5263 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5264 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5265 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5266 }
5267 /* hw_max = RP0 until we check for overclocking */
5268 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5269
5270 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5271 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5272 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5273 u32 ddcc_status = 0;
5274
5275 if (sandybridge_pcode_read(dev_priv,
5276 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5277 &ddcc_status) == 0)
5278 dev_priv->rps.efficient_freq =
5279 clamp_t(u8,
5280 ((ddcc_status >> 8) & 0xff),
5281 dev_priv->rps.min_freq,
5282 dev_priv->rps.max_freq);
5283 }
5284
5285 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5286 /* Store the frequency values in 16.66 MHZ units, which is
5287 * the natural hardware unit for SKL
5288 */
5289 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5290 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5291 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5292 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5293 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5294 }
5295 }
5296
5297 static void reset_rps(struct drm_i915_private *dev_priv,
5298 void (*set)(struct drm_i915_private *, u8))
5299 {
5300 u8 freq = dev_priv->rps.cur_freq;
5301
5302 /* force a reset */
5303 dev_priv->rps.power = -1;
5304 dev_priv->rps.cur_freq = -1;
5305
5306 set(dev_priv, freq);
5307 }
5308
5309 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5310 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5311 {
5312 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5313
5314 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5315 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5316 /*
5317 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5318 * clear out the Control register just to avoid inconsitency
5319 * with debugfs interface, which will show Turbo as enabled
5320 * only and that is not expected by the User after adding the
5321 * WaGsvDisableTurbo. Apart from this there is no problem even
5322 * if the Turbo is left enabled in the Control register, as the
5323 * Up/Down interrupts would remain masked.
5324 */
5325 gen9_disable_rps(dev_priv);
5326 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5327 return;
5328 }
5329
5330 /* Program defaults and thresholds for RPS*/
5331 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5332 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5333
5334 /* 1 second timeout*/
5335 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5336 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5337
5338 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5339
5340 /* Leaning on the below call to gen6_set_rps to program/setup the
5341 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5342 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5343 reset_rps(dev_priv, gen6_set_rps);
5344
5345 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5346 }
5347
5348 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5349 {
5350 struct intel_engine_cs *engine;
5351 enum intel_engine_id id;
5352 uint32_t rc6_mask = 0;
5353
5354 /* 1a: Software RC state - RC0 */
5355 I915_WRITE(GEN6_RC_STATE, 0);
5356
5357 /* 1b: Get forcewake during program sequence. Although the driver
5358 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5359 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5360
5361 /* 2a: Disable RC states. */
5362 I915_WRITE(GEN6_RC_CONTROL, 0);
5363
5364 /* 2b: Program RC6 thresholds.*/
5365
5366 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5367 if (IS_SKYLAKE(dev_priv))
5368 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5369 else
5370 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5371 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5372 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5373 for_each_engine(engine, dev_priv, id)
5374 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5375
5376 if (HAS_GUC(dev_priv))
5377 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5378
5379 I915_WRITE(GEN6_RC_SLEEP, 0);
5380
5381 /* 2c: Program Coarse Power Gating Policies. */
5382 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5383 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5384
5385 /* 3a: Enable RC6 */
5386 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5387 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5388 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5389 /* WaRsUseTimeoutMode:bxt */
5390 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5391 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5392 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5393 GEN7_RC_CTL_TO_MODE |
5394 rc6_mask);
5395 } else {
5396 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5397 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5398 GEN6_RC_CTL_EI_MODE(1) |
5399 rc6_mask);
5400 }
5401
5402 /*
5403 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5404 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5405 */
5406 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5407 I915_WRITE(GEN9_PG_ENABLE, 0);
5408 else
5409 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5410 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5411
5412 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5413 }
5414
5415 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5416 {
5417 struct intel_engine_cs *engine;
5418 enum intel_engine_id id;
5419 uint32_t rc6_mask = 0;
5420
5421 /* 1a: Software RC state - RC0 */
5422 I915_WRITE(GEN6_RC_STATE, 0);
5423
5424 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5425 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5426 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5427
5428 /* 2a: Disable RC states. */
5429 I915_WRITE(GEN6_RC_CONTROL, 0);
5430
5431 /* 2b: Program RC6 thresholds.*/
5432 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5433 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5434 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5435 for_each_engine(engine, dev_priv, id)
5436 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5437 I915_WRITE(GEN6_RC_SLEEP, 0);
5438 if (IS_BROADWELL(dev_priv))
5439 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5440 else
5441 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5442
5443 /* 3: Enable RC6 */
5444 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5445 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5446 intel_print_rc6_info(dev_priv, rc6_mask);
5447 if (IS_BROADWELL(dev_priv))
5448 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5449 GEN7_RC_CTL_TO_MODE |
5450 rc6_mask);
5451 else
5452 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5453 GEN6_RC_CTL_EI_MODE(1) |
5454 rc6_mask);
5455
5456 /* 4 Program defaults and thresholds for RPS*/
5457 I915_WRITE(GEN6_RPNSWREQ,
5458 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5459 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5460 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5461 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5462 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5463
5464 /* Docs recommend 900MHz, and 300 MHz respectively */
5465 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5466 dev_priv->rps.max_freq_softlimit << 24 |
5467 dev_priv->rps.min_freq_softlimit << 16);
5468
5469 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5470 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5471 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5472 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5473
5474 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5475
5476 /* 5: Enable RPS */
5477 I915_WRITE(GEN6_RP_CONTROL,
5478 GEN6_RP_MEDIA_TURBO |
5479 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5480 GEN6_RP_MEDIA_IS_GFX |
5481 GEN6_RP_ENABLE |
5482 GEN6_RP_UP_BUSY_AVG |
5483 GEN6_RP_DOWN_IDLE_AVG);
5484
5485 /* 6: Ring frequency + overclocking (our driver does this later */
5486
5487 reset_rps(dev_priv, gen6_set_rps);
5488
5489 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5490 }
5491
5492 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5493 {
5494 struct intel_engine_cs *engine;
5495 enum intel_engine_id id;
5496 u32 rc6vids, rc6_mask = 0;
5497 u32 gtfifodbg;
5498 int rc6_mode;
5499 int ret;
5500
5501 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5502
5503 /* Here begins a magic sequence of register writes to enable
5504 * auto-downclocking.
5505 *
5506 * Perhaps there might be some value in exposing these to
5507 * userspace...
5508 */
5509 I915_WRITE(GEN6_RC_STATE, 0);
5510
5511 /* Clear the DBG now so we don't confuse earlier errors */
5512 gtfifodbg = I915_READ(GTFIFODBG);
5513 if (gtfifodbg) {
5514 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5515 I915_WRITE(GTFIFODBG, gtfifodbg);
5516 }
5517
5518 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5519
5520 /* disable the counters and set deterministic thresholds */
5521 I915_WRITE(GEN6_RC_CONTROL, 0);
5522
5523 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5524 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5525 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5526 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5527 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5528
5529 for_each_engine(engine, dev_priv, id)
5530 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5531
5532 I915_WRITE(GEN6_RC_SLEEP, 0);
5533 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5534 if (IS_IVYBRIDGE(dev_priv))
5535 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5536 else
5537 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5538 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5539 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5540
5541 /* Check if we are enabling RC6 */
5542 rc6_mode = intel_enable_rc6();
5543 if (rc6_mode & INTEL_RC6_ENABLE)
5544 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5545
5546 /* We don't use those on Haswell */
5547 if (!IS_HASWELL(dev_priv)) {
5548 if (rc6_mode & INTEL_RC6p_ENABLE)
5549 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5550
5551 if (rc6_mode & INTEL_RC6pp_ENABLE)
5552 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5553 }
5554
5555 intel_print_rc6_info(dev_priv, rc6_mask);
5556
5557 I915_WRITE(GEN6_RC_CONTROL,
5558 rc6_mask |
5559 GEN6_RC_CTL_EI_MODE(1) |
5560 GEN6_RC_CTL_HW_ENABLE);
5561
5562 /* Power down if completely idle for over 50ms */
5563 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5564 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5565
5566 reset_rps(dev_priv, gen6_set_rps);
5567
5568 rc6vids = 0;
5569 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5570 if (IS_GEN6(dev_priv) && ret) {
5571 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5572 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5573 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5574 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5575 rc6vids &= 0xffff00;
5576 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5577 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5578 if (ret)
5579 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5580 }
5581
5582 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5583 }
5584
5585 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5586 {
5587 int min_freq = 15;
5588 unsigned int gpu_freq;
5589 unsigned int max_ia_freq, min_ring_freq;
5590 unsigned int max_gpu_freq, min_gpu_freq;
5591 int scaling_factor = 180;
5592 struct cpufreq_policy *policy;
5593
5594 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5595
5596 policy = cpufreq_cpu_get(0);
5597 if (policy) {
5598 max_ia_freq = policy->cpuinfo.max_freq;
5599 cpufreq_cpu_put(policy);
5600 } else {
5601 /*
5602 * Default to measured freq if none found, PCU will ensure we
5603 * don't go over
5604 */
5605 max_ia_freq = tsc_khz;
5606 }
5607
5608 /* Convert from kHz to MHz */
5609 max_ia_freq /= 1000;
5610
5611 min_ring_freq = I915_READ(DCLK) & 0xf;
5612 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5613 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5614
5615 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5616 /* Convert GT frequency to 50 HZ units */
5617 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5618 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5619 } else {
5620 min_gpu_freq = dev_priv->rps.min_freq;
5621 max_gpu_freq = dev_priv->rps.max_freq;
5622 }
5623
5624 /*
5625 * For each potential GPU frequency, load a ring frequency we'd like
5626 * to use for memory access. We do this by specifying the IA frequency
5627 * the PCU should use as a reference to determine the ring frequency.
5628 */
5629 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5630 int diff = max_gpu_freq - gpu_freq;
5631 unsigned int ia_freq = 0, ring_freq = 0;
5632
5633 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5634 /*
5635 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5636 * No floor required for ring frequency on SKL.
5637 */
5638 ring_freq = gpu_freq;
5639 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5640 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5641 ring_freq = max(min_ring_freq, gpu_freq);
5642 } else if (IS_HASWELL(dev_priv)) {
5643 ring_freq = mult_frac(gpu_freq, 5, 4);
5644 ring_freq = max(min_ring_freq, ring_freq);
5645 /* leave ia_freq as the default, chosen by cpufreq */
5646 } else {
5647 /* On older processors, there is no separate ring
5648 * clock domain, so in order to boost the bandwidth
5649 * of the ring, we need to upclock the CPU (ia_freq).
5650 *
5651 * For GPU frequencies less than 750MHz,
5652 * just use the lowest ring freq.
5653 */
5654 if (gpu_freq < min_freq)
5655 ia_freq = 800;
5656 else
5657 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5658 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5659 }
5660
5661 sandybridge_pcode_write(dev_priv,
5662 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5663 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5664 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5665 gpu_freq);
5666 }
5667 }
5668
5669 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5670 {
5671 u32 val, rp0;
5672
5673 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5674
5675 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5676 case 8:
5677 /* (2 * 4) config */
5678 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5679 break;
5680 case 12:
5681 /* (2 * 6) config */
5682 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5683 break;
5684 case 16:
5685 /* (2 * 8) config */
5686 default:
5687 /* Setting (2 * 8) Min RP0 for any other combination */
5688 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5689 break;
5690 }
5691
5692 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5693
5694 return rp0;
5695 }
5696
5697 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5698 {
5699 u32 val, rpe;
5700
5701 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5702 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5703
5704 return rpe;
5705 }
5706
5707 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5708 {
5709 u32 val, rp1;
5710
5711 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5712 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5713
5714 return rp1;
5715 }
5716
5717 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5718 {
5719 u32 val, rp1;
5720
5721 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5722
5723 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5724
5725 return rp1;
5726 }
5727
5728 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5729 {
5730 u32 val, rp0;
5731
5732 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5733
5734 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5735 /* Clamp to max */
5736 rp0 = min_t(u32, rp0, 0xea);
5737
5738 return rp0;
5739 }
5740
5741 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5742 {
5743 u32 val, rpe;
5744
5745 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5746 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5747 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5748 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5749
5750 return rpe;
5751 }
5752
5753 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5754 {
5755 u32 val;
5756
5757 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5758 /*
5759 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5760 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5761 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5762 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5763 * to make sure it matches what Punit accepts.
5764 */
5765 return max_t(u32, val, 0xc0);
5766 }
5767
5768 /* Check that the pctx buffer wasn't move under us. */
5769 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5770 {
5771 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5772
5773 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5774 dev_priv->vlv_pctx->stolen->start);
5775 }
5776
5777
5778 /* Check that the pcbr address is not empty. */
5779 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5780 {
5781 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5782
5783 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5784 }
5785
5786 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5787 {
5788 struct i915_ggtt *ggtt = &dev_priv->ggtt;
5789 unsigned long pctx_paddr, paddr;
5790 u32 pcbr;
5791 int pctx_size = 32*1024;
5792
5793 pcbr = I915_READ(VLV_PCBR);
5794 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5795 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5796 paddr = (dev_priv->mm.stolen_base +
5797 (ggtt->stolen_size - pctx_size));
5798
5799 pctx_paddr = (paddr & (~4095));
5800 I915_WRITE(VLV_PCBR, pctx_paddr);
5801 }
5802
5803 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5804 }
5805
5806 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5807 {
5808 struct drm_i915_gem_object *pctx;
5809 unsigned long pctx_paddr;
5810 u32 pcbr;
5811 int pctx_size = 24*1024;
5812
5813 pcbr = I915_READ(VLV_PCBR);
5814 if (pcbr) {
5815 /* BIOS set it up already, grab the pre-alloc'd space */
5816 int pcbr_offset;
5817
5818 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5819 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
5820 pcbr_offset,
5821 I915_GTT_OFFSET_NONE,
5822 pctx_size);
5823 goto out;
5824 }
5825
5826 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5827
5828 /*
5829 * From the Gunit register HAS:
5830 * The Gfx driver is expected to program this register and ensure
5831 * proper allocation within Gfx stolen memory. For example, this
5832 * register should be programmed such than the PCBR range does not
5833 * overlap with other ranges, such as the frame buffer, protected
5834 * memory, or any other relevant ranges.
5835 */
5836 pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
5837 if (!pctx) {
5838 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5839 goto out;
5840 }
5841
5842 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5843 I915_WRITE(VLV_PCBR, pctx_paddr);
5844
5845 out:
5846 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5847 dev_priv->vlv_pctx = pctx;
5848 }
5849
5850 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5851 {
5852 if (WARN_ON(!dev_priv->vlv_pctx))
5853 return;
5854
5855 i915_gem_object_put(dev_priv->vlv_pctx);
5856 dev_priv->vlv_pctx = NULL;
5857 }
5858
5859 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5860 {
5861 dev_priv->rps.gpll_ref_freq =
5862 vlv_get_cck_clock(dev_priv, "GPLL ref",
5863 CCK_GPLL_CLOCK_CONTROL,
5864 dev_priv->czclk_freq);
5865
5866 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5867 dev_priv->rps.gpll_ref_freq);
5868 }
5869
5870 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5871 {
5872 u32 val;
5873
5874 valleyview_setup_pctx(dev_priv);
5875
5876 vlv_init_gpll_ref_freq(dev_priv);
5877
5878 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5879 switch ((val >> 6) & 3) {
5880 case 0:
5881 case 1:
5882 dev_priv->mem_freq = 800;
5883 break;
5884 case 2:
5885 dev_priv->mem_freq = 1066;
5886 break;
5887 case 3:
5888 dev_priv->mem_freq = 1333;
5889 break;
5890 }
5891 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5892
5893 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5894 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5895 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5896 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5897 dev_priv->rps.max_freq);
5898
5899 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5900 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5901 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5902 dev_priv->rps.efficient_freq);
5903
5904 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5905 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5906 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5907 dev_priv->rps.rp1_freq);
5908
5909 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5910 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5911 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5912 dev_priv->rps.min_freq);
5913 }
5914
5915 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5916 {
5917 u32 val;
5918
5919 cherryview_setup_pctx(dev_priv);
5920
5921 vlv_init_gpll_ref_freq(dev_priv);
5922
5923 mutex_lock(&dev_priv->sb_lock);
5924 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5925 mutex_unlock(&dev_priv->sb_lock);
5926
5927 switch ((val >> 2) & 0x7) {
5928 case 3:
5929 dev_priv->mem_freq = 2000;
5930 break;
5931 default:
5932 dev_priv->mem_freq = 1600;
5933 break;
5934 }
5935 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5936
5937 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5938 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5939 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5940 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5941 dev_priv->rps.max_freq);
5942
5943 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5944 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5945 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5946 dev_priv->rps.efficient_freq);
5947
5948 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5949 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5950 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5951 dev_priv->rps.rp1_freq);
5952
5953 /* PUnit validated range is only [RPe, RP0] */
5954 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5955 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5956 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5957 dev_priv->rps.min_freq);
5958
5959 WARN_ONCE((dev_priv->rps.max_freq |
5960 dev_priv->rps.efficient_freq |
5961 dev_priv->rps.rp1_freq |
5962 dev_priv->rps.min_freq) & 1,
5963 "Odd GPU freq values\n");
5964 }
5965
5966 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5967 {
5968 valleyview_cleanup_pctx(dev_priv);
5969 }
5970
5971 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5972 {
5973 struct intel_engine_cs *engine;
5974 enum intel_engine_id id;
5975 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5976
5977 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5978
5979 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5980 GT_FIFO_FREE_ENTRIES_CHV);
5981 if (gtfifodbg) {
5982 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5983 gtfifodbg);
5984 I915_WRITE(GTFIFODBG, gtfifodbg);
5985 }
5986
5987 cherryview_check_pctx(dev_priv);
5988
5989 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5990 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5991 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5992
5993 /* Disable RC states. */
5994 I915_WRITE(GEN6_RC_CONTROL, 0);
5995
5996 /* 2a: Program RC6 thresholds.*/
5997 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5998 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5999 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6000
6001 for_each_engine(engine, dev_priv, id)
6002 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6003 I915_WRITE(GEN6_RC_SLEEP, 0);
6004
6005 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6006 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
6007
6008 /* allows RC6 residency counter to work */
6009 I915_WRITE(VLV_COUNTER_CONTROL,
6010 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6011 VLV_MEDIA_RC6_COUNT_EN |
6012 VLV_RENDER_RC6_COUNT_EN));
6013
6014 /* For now we assume BIOS is allocating and populating the PCBR */
6015 pcbr = I915_READ(VLV_PCBR);
6016
6017 /* 3: Enable RC6 */
6018 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6019 (pcbr >> VLV_PCBR_ADDR_SHIFT))
6020 rc6_mode = GEN7_RC_CTL_TO_MODE;
6021
6022 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6023
6024 /* 4 Program defaults and thresholds for RPS*/
6025 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6026 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6027 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6028 I915_WRITE(GEN6_RP_UP_EI, 66000);
6029 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6030
6031 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6032
6033 /* 5: Enable RPS */
6034 I915_WRITE(GEN6_RP_CONTROL,
6035 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6036 GEN6_RP_MEDIA_IS_GFX |
6037 GEN6_RP_ENABLE |
6038 GEN6_RP_UP_BUSY_AVG |
6039 GEN6_RP_DOWN_IDLE_AVG);
6040
6041 /* Setting Fixed Bias */
6042 val = VLV_OVERRIDE_EN |
6043 VLV_SOC_TDP_EN |
6044 CHV_BIAS_CPU_50_SOC_50;
6045 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6046
6047 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6048
6049 /* RPS code assumes GPLL is used */
6050 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6051
6052 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6053 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6054
6055 reset_rps(dev_priv, valleyview_set_rps);
6056
6057 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6058 }
6059
6060 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
6061 {
6062 struct intel_engine_cs *engine;
6063 enum intel_engine_id id;
6064 u32 gtfifodbg, val, rc6_mode = 0;
6065
6066 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6067
6068 valleyview_check_pctx(dev_priv);
6069
6070 gtfifodbg = I915_READ(GTFIFODBG);
6071 if (gtfifodbg) {
6072 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6073 gtfifodbg);
6074 I915_WRITE(GTFIFODBG, gtfifodbg);
6075 }
6076
6077 /* If VLV, Forcewake all wells, else re-direct to regular path */
6078 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6079
6080 /* Disable RC states. */
6081 I915_WRITE(GEN6_RC_CONTROL, 0);
6082
6083 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6084 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6085 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6086 I915_WRITE(GEN6_RP_UP_EI, 66000);
6087 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6088
6089 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6090
6091 I915_WRITE(GEN6_RP_CONTROL,
6092 GEN6_RP_MEDIA_TURBO |
6093 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6094 GEN6_RP_MEDIA_IS_GFX |
6095 GEN6_RP_ENABLE |
6096 GEN6_RP_UP_BUSY_AVG |
6097 GEN6_RP_DOWN_IDLE_CONT);
6098
6099 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6100 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6101 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6102
6103 for_each_engine(engine, dev_priv, id)
6104 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6105
6106 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
6107
6108 /* allows RC6 residency counter to work */
6109 I915_WRITE(VLV_COUNTER_CONTROL,
6110 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6111 VLV_RENDER_RC0_COUNT_EN |
6112 VLV_MEDIA_RC6_COUNT_EN |
6113 VLV_RENDER_RC6_COUNT_EN));
6114
6115 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6116 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
6117
6118 intel_print_rc6_info(dev_priv, rc6_mode);
6119
6120 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6121
6122 /* Setting Fixed Bias */
6123 val = VLV_OVERRIDE_EN |
6124 VLV_SOC_TDP_EN |
6125 VLV_BIAS_CPU_125_SOC_875;
6126 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6127
6128 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6129
6130 /* RPS code assumes GPLL is used */
6131 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6132
6133 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6134 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6135
6136 reset_rps(dev_priv, valleyview_set_rps);
6137
6138 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6139 }
6140
6141 static unsigned long intel_pxfreq(u32 vidfreq)
6142 {
6143 unsigned long freq;
6144 int div = (vidfreq & 0x3f0000) >> 16;
6145 int post = (vidfreq & 0x3000) >> 12;
6146 int pre = (vidfreq & 0x7);
6147
6148 if (!pre)
6149 return 0;
6150
6151 freq = ((div * 133333) / ((1<<post) * pre));
6152
6153 return freq;
6154 }
6155
6156 static const struct cparams {
6157 u16 i;
6158 u16 t;
6159 u16 m;
6160 u16 c;
6161 } cparams[] = {
6162 { 1, 1333, 301, 28664 },
6163 { 1, 1066, 294, 24460 },
6164 { 1, 800, 294, 25192 },
6165 { 0, 1333, 276, 27605 },
6166 { 0, 1066, 276, 27605 },
6167 { 0, 800, 231, 23784 },
6168 };
6169
6170 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6171 {
6172 u64 total_count, diff, ret;
6173 u32 count1, count2, count3, m = 0, c = 0;
6174 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6175 int i;
6176
6177 assert_spin_locked(&mchdev_lock);
6178
6179 diff1 = now - dev_priv->ips.last_time1;
6180
6181 /* Prevent division-by-zero if we are asking too fast.
6182 * Also, we don't get interesting results if we are polling
6183 * faster than once in 10ms, so just return the saved value
6184 * in such cases.
6185 */
6186 if (diff1 <= 10)
6187 return dev_priv->ips.chipset_power;
6188
6189 count1 = I915_READ(DMIEC);
6190 count2 = I915_READ(DDREC);
6191 count3 = I915_READ(CSIEC);
6192
6193 total_count = count1 + count2 + count3;
6194
6195 /* FIXME: handle per-counter overflow */
6196 if (total_count < dev_priv->ips.last_count1) {
6197 diff = ~0UL - dev_priv->ips.last_count1;
6198 diff += total_count;
6199 } else {
6200 diff = total_count - dev_priv->ips.last_count1;
6201 }
6202
6203 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6204 if (cparams[i].i == dev_priv->ips.c_m &&
6205 cparams[i].t == dev_priv->ips.r_t) {
6206 m = cparams[i].m;
6207 c = cparams[i].c;
6208 break;
6209 }
6210 }
6211
6212 diff = div_u64(diff, diff1);
6213 ret = ((m * diff) + c);
6214 ret = div_u64(ret, 10);
6215
6216 dev_priv->ips.last_count1 = total_count;
6217 dev_priv->ips.last_time1 = now;
6218
6219 dev_priv->ips.chipset_power = ret;
6220
6221 return ret;
6222 }
6223
6224 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6225 {
6226 unsigned long val;
6227
6228 if (INTEL_INFO(dev_priv)->gen != 5)
6229 return 0;
6230
6231 spin_lock_irq(&mchdev_lock);
6232
6233 val = __i915_chipset_val(dev_priv);
6234
6235 spin_unlock_irq(&mchdev_lock);
6236
6237 return val;
6238 }
6239
6240 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6241 {
6242 unsigned long m, x, b;
6243 u32 tsfs;
6244
6245 tsfs = I915_READ(TSFS);
6246
6247 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6248 x = I915_READ8(TR1);
6249
6250 b = tsfs & TSFS_INTR_MASK;
6251
6252 return ((m * x) / 127) - b;
6253 }
6254
6255 static int _pxvid_to_vd(u8 pxvid)
6256 {
6257 if (pxvid == 0)
6258 return 0;
6259
6260 if (pxvid >= 8 && pxvid < 31)
6261 pxvid = 31;
6262
6263 return (pxvid + 2) * 125;
6264 }
6265
6266 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6267 {
6268 const int vd = _pxvid_to_vd(pxvid);
6269 const int vm = vd - 1125;
6270
6271 if (INTEL_INFO(dev_priv)->is_mobile)
6272 return vm > 0 ? vm : 0;
6273
6274 return vd;
6275 }
6276
6277 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6278 {
6279 u64 now, diff, diffms;
6280 u32 count;
6281
6282 assert_spin_locked(&mchdev_lock);
6283
6284 now = ktime_get_raw_ns();
6285 diffms = now - dev_priv->ips.last_time2;
6286 do_div(diffms, NSEC_PER_MSEC);
6287
6288 /* Don't divide by 0 */
6289 if (!diffms)
6290 return;
6291
6292 count = I915_READ(GFXEC);
6293
6294 if (count < dev_priv->ips.last_count2) {
6295 diff = ~0UL - dev_priv->ips.last_count2;
6296 diff += count;
6297 } else {
6298 diff = count - dev_priv->ips.last_count2;
6299 }
6300
6301 dev_priv->ips.last_count2 = count;
6302 dev_priv->ips.last_time2 = now;
6303
6304 /* More magic constants... */
6305 diff = diff * 1181;
6306 diff = div_u64(diff, diffms * 10);
6307 dev_priv->ips.gfx_power = diff;
6308 }
6309
6310 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6311 {
6312 if (INTEL_INFO(dev_priv)->gen != 5)
6313 return;
6314
6315 spin_lock_irq(&mchdev_lock);
6316
6317 __i915_update_gfx_val(dev_priv);
6318
6319 spin_unlock_irq(&mchdev_lock);
6320 }
6321
6322 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6323 {
6324 unsigned long t, corr, state1, corr2, state2;
6325 u32 pxvid, ext_v;
6326
6327 assert_spin_locked(&mchdev_lock);
6328
6329 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6330 pxvid = (pxvid >> 24) & 0x7f;
6331 ext_v = pvid_to_extvid(dev_priv, pxvid);
6332
6333 state1 = ext_v;
6334
6335 t = i915_mch_val(dev_priv);
6336
6337 /* Revel in the empirically derived constants */
6338
6339 /* Correction factor in 1/100000 units */
6340 if (t > 80)
6341 corr = ((t * 2349) + 135940);
6342 else if (t >= 50)
6343 corr = ((t * 964) + 29317);
6344 else /* < 50 */
6345 corr = ((t * 301) + 1004);
6346
6347 corr = corr * ((150142 * state1) / 10000 - 78642);
6348 corr /= 100000;
6349 corr2 = (corr * dev_priv->ips.corr);
6350
6351 state2 = (corr2 * state1) / 10000;
6352 state2 /= 100; /* convert to mW */
6353
6354 __i915_update_gfx_val(dev_priv);
6355
6356 return dev_priv->ips.gfx_power + state2;
6357 }
6358
6359 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6360 {
6361 unsigned long val;
6362
6363 if (INTEL_INFO(dev_priv)->gen != 5)
6364 return 0;
6365
6366 spin_lock_irq(&mchdev_lock);
6367
6368 val = __i915_gfx_val(dev_priv);
6369
6370 spin_unlock_irq(&mchdev_lock);
6371
6372 return val;
6373 }
6374
6375 /**
6376 * i915_read_mch_val - return value for IPS use
6377 *
6378 * Calculate and return a value for the IPS driver to use when deciding whether
6379 * we have thermal and power headroom to increase CPU or GPU power budget.
6380 */
6381 unsigned long i915_read_mch_val(void)
6382 {
6383 struct drm_i915_private *dev_priv;
6384 unsigned long chipset_val, graphics_val, ret = 0;
6385
6386 spin_lock_irq(&mchdev_lock);
6387 if (!i915_mch_dev)
6388 goto out_unlock;
6389 dev_priv = i915_mch_dev;
6390
6391 chipset_val = __i915_chipset_val(dev_priv);
6392 graphics_val = __i915_gfx_val(dev_priv);
6393
6394 ret = chipset_val + graphics_val;
6395
6396 out_unlock:
6397 spin_unlock_irq(&mchdev_lock);
6398
6399 return ret;
6400 }
6401 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6402
6403 /**
6404 * i915_gpu_raise - raise GPU frequency limit
6405 *
6406 * Raise the limit; IPS indicates we have thermal headroom.
6407 */
6408 bool i915_gpu_raise(void)
6409 {
6410 struct drm_i915_private *dev_priv;
6411 bool ret = true;
6412
6413 spin_lock_irq(&mchdev_lock);
6414 if (!i915_mch_dev) {
6415 ret = false;
6416 goto out_unlock;
6417 }
6418 dev_priv = i915_mch_dev;
6419
6420 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6421 dev_priv->ips.max_delay--;
6422
6423 out_unlock:
6424 spin_unlock_irq(&mchdev_lock);
6425
6426 return ret;
6427 }
6428 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6429
6430 /**
6431 * i915_gpu_lower - lower GPU frequency limit
6432 *
6433 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6434 * frequency maximum.
6435 */
6436 bool i915_gpu_lower(void)
6437 {
6438 struct drm_i915_private *dev_priv;
6439 bool ret = true;
6440
6441 spin_lock_irq(&mchdev_lock);
6442 if (!i915_mch_dev) {
6443 ret = false;
6444 goto out_unlock;
6445 }
6446 dev_priv = i915_mch_dev;
6447
6448 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6449 dev_priv->ips.max_delay++;
6450
6451 out_unlock:
6452 spin_unlock_irq(&mchdev_lock);
6453
6454 return ret;
6455 }
6456 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6457
6458 /**
6459 * i915_gpu_busy - indicate GPU business to IPS
6460 *
6461 * Tell the IPS driver whether or not the GPU is busy.
6462 */
6463 bool i915_gpu_busy(void)
6464 {
6465 bool ret = false;
6466
6467 spin_lock_irq(&mchdev_lock);
6468 if (i915_mch_dev)
6469 ret = i915_mch_dev->gt.awake;
6470 spin_unlock_irq(&mchdev_lock);
6471
6472 return ret;
6473 }
6474 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6475
6476 /**
6477 * i915_gpu_turbo_disable - disable graphics turbo
6478 *
6479 * Disable graphics turbo by resetting the max frequency and setting the
6480 * current frequency to the default.
6481 */
6482 bool i915_gpu_turbo_disable(void)
6483 {
6484 struct drm_i915_private *dev_priv;
6485 bool ret = true;
6486
6487 spin_lock_irq(&mchdev_lock);
6488 if (!i915_mch_dev) {
6489 ret = false;
6490 goto out_unlock;
6491 }
6492 dev_priv = i915_mch_dev;
6493
6494 dev_priv->ips.max_delay = dev_priv->ips.fstart;
6495
6496 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6497 ret = false;
6498
6499 out_unlock:
6500 spin_unlock_irq(&mchdev_lock);
6501
6502 return ret;
6503 }
6504 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6505
6506 /**
6507 * Tells the intel_ips driver that the i915 driver is now loaded, if
6508 * IPS got loaded first.
6509 *
6510 * This awkward dance is so that neither module has to depend on the
6511 * other in order for IPS to do the appropriate communication of
6512 * GPU turbo limits to i915.
6513 */
6514 static void
6515 ips_ping_for_i915_load(void)
6516 {
6517 void (*link)(void);
6518
6519 link = symbol_get(ips_link_to_i915_driver);
6520 if (link) {
6521 link();
6522 symbol_put(ips_link_to_i915_driver);
6523 }
6524 }
6525
6526 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6527 {
6528 /* We only register the i915 ips part with intel-ips once everything is
6529 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6530 spin_lock_irq(&mchdev_lock);
6531 i915_mch_dev = dev_priv;
6532 spin_unlock_irq(&mchdev_lock);
6533
6534 ips_ping_for_i915_load();
6535 }
6536
6537 void intel_gpu_ips_teardown(void)
6538 {
6539 spin_lock_irq(&mchdev_lock);
6540 i915_mch_dev = NULL;
6541 spin_unlock_irq(&mchdev_lock);
6542 }
6543
6544 static void intel_init_emon(struct drm_i915_private *dev_priv)
6545 {
6546 u32 lcfuse;
6547 u8 pxw[16];
6548 int i;
6549
6550 /* Disable to program */
6551 I915_WRITE(ECR, 0);
6552 POSTING_READ(ECR);
6553
6554 /* Program energy weights for various events */
6555 I915_WRITE(SDEW, 0x15040d00);
6556 I915_WRITE(CSIEW0, 0x007f0000);
6557 I915_WRITE(CSIEW1, 0x1e220004);
6558 I915_WRITE(CSIEW2, 0x04000004);
6559
6560 for (i = 0; i < 5; i++)
6561 I915_WRITE(PEW(i), 0);
6562 for (i = 0; i < 3; i++)
6563 I915_WRITE(DEW(i), 0);
6564
6565 /* Program P-state weights to account for frequency power adjustment */
6566 for (i = 0; i < 16; i++) {
6567 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6568 unsigned long freq = intel_pxfreq(pxvidfreq);
6569 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6570 PXVFREQ_PX_SHIFT;
6571 unsigned long val;
6572
6573 val = vid * vid;
6574 val *= (freq / 1000);
6575 val *= 255;
6576 val /= (127*127*900);
6577 if (val > 0xff)
6578 DRM_ERROR("bad pxval: %ld\n", val);
6579 pxw[i] = val;
6580 }
6581 /* Render standby states get 0 weight */
6582 pxw[14] = 0;
6583 pxw[15] = 0;
6584
6585 for (i = 0; i < 4; i++) {
6586 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6587 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6588 I915_WRITE(PXW(i), val);
6589 }
6590
6591 /* Adjust magic regs to magic values (more experimental results) */
6592 I915_WRITE(OGW0, 0);
6593 I915_WRITE(OGW1, 0);
6594 I915_WRITE(EG0, 0x00007f00);
6595 I915_WRITE(EG1, 0x0000000e);
6596 I915_WRITE(EG2, 0x000e0000);
6597 I915_WRITE(EG3, 0x68000300);
6598 I915_WRITE(EG4, 0x42000000);
6599 I915_WRITE(EG5, 0x00140031);
6600 I915_WRITE(EG6, 0);
6601 I915_WRITE(EG7, 0);
6602
6603 for (i = 0; i < 8; i++)
6604 I915_WRITE(PXWL(i), 0);
6605
6606 /* Enable PMON + select events */
6607 I915_WRITE(ECR, 0x80000019);
6608
6609 lcfuse = I915_READ(LCFUSE02);
6610
6611 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6612 }
6613
6614 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6615 {
6616 /*
6617 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6618 * requirement.
6619 */
6620 if (!i915.enable_rc6) {
6621 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6622 intel_runtime_pm_get(dev_priv);
6623 }
6624
6625 mutex_lock(&dev_priv->drm.struct_mutex);
6626 mutex_lock(&dev_priv->rps.hw_lock);
6627
6628 /* Initialize RPS limits (for userspace) */
6629 if (IS_CHERRYVIEW(dev_priv))
6630 cherryview_init_gt_powersave(dev_priv);
6631 else if (IS_VALLEYVIEW(dev_priv))
6632 valleyview_init_gt_powersave(dev_priv);
6633 else if (INTEL_GEN(dev_priv) >= 6)
6634 gen6_init_rps_frequencies(dev_priv);
6635
6636 /* Derive initial user preferences/limits from the hardware limits */
6637 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6638 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6639
6640 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6641 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6642
6643 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6644 dev_priv->rps.min_freq_softlimit =
6645 max_t(int,
6646 dev_priv->rps.efficient_freq,
6647 intel_freq_opcode(dev_priv, 450));
6648
6649 /* After setting max-softlimit, find the overclock max freq */
6650 if (IS_GEN6(dev_priv) ||
6651 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6652 u32 params = 0;
6653
6654 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6655 if (params & BIT(31)) { /* OC supported */
6656 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6657 (dev_priv->rps.max_freq & 0xff) * 50,
6658 (params & 0xff) * 50);
6659 dev_priv->rps.max_freq = params & 0xff;
6660 }
6661 }
6662
6663 /* Finally allow us to boost to max by default */
6664 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6665
6666 mutex_unlock(&dev_priv->rps.hw_lock);
6667 mutex_unlock(&dev_priv->drm.struct_mutex);
6668
6669 intel_autoenable_gt_powersave(dev_priv);
6670 }
6671
6672 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6673 {
6674 if (IS_VALLEYVIEW(dev_priv))
6675 valleyview_cleanup_gt_powersave(dev_priv);
6676
6677 if (!i915.enable_rc6)
6678 intel_runtime_pm_put(dev_priv);
6679 }
6680
6681 /**
6682 * intel_suspend_gt_powersave - suspend PM work and helper threads
6683 * @dev_priv: i915 device
6684 *
6685 * We don't want to disable RC6 or other features here, we just want
6686 * to make sure any work we've queued has finished and won't bother
6687 * us while we're suspended.
6688 */
6689 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6690 {
6691 if (INTEL_GEN(dev_priv) < 6)
6692 return;
6693
6694 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6695 intel_runtime_pm_put(dev_priv);
6696
6697 /* gen6_rps_idle() will be called later to disable interrupts */
6698 }
6699
6700 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6701 {
6702 dev_priv->rps.enabled = true; /* force disabling */
6703 intel_disable_gt_powersave(dev_priv);
6704
6705 gen6_reset_rps_interrupts(dev_priv);
6706 }
6707
6708 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6709 {
6710 if (!READ_ONCE(dev_priv->rps.enabled))
6711 return;
6712
6713 mutex_lock(&dev_priv->rps.hw_lock);
6714
6715 if (INTEL_GEN(dev_priv) >= 9) {
6716 gen9_disable_rc6(dev_priv);
6717 gen9_disable_rps(dev_priv);
6718 } else if (IS_CHERRYVIEW(dev_priv)) {
6719 cherryview_disable_rps(dev_priv);
6720 } else if (IS_VALLEYVIEW(dev_priv)) {
6721 valleyview_disable_rps(dev_priv);
6722 } else if (INTEL_GEN(dev_priv) >= 6) {
6723 gen6_disable_rps(dev_priv);
6724 } else if (IS_IRONLAKE_M(dev_priv)) {
6725 ironlake_disable_drps(dev_priv);
6726 }
6727
6728 dev_priv->rps.enabled = false;
6729 mutex_unlock(&dev_priv->rps.hw_lock);
6730 }
6731
6732 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6733 {
6734 /* We shouldn't be disabling as we submit, so this should be less
6735 * racy than it appears!
6736 */
6737 if (READ_ONCE(dev_priv->rps.enabled))
6738 return;
6739
6740 /* Powersaving is controlled by the host when inside a VM */
6741 if (intel_vgpu_active(dev_priv))
6742 return;
6743
6744 mutex_lock(&dev_priv->rps.hw_lock);
6745
6746 if (IS_CHERRYVIEW(dev_priv)) {
6747 cherryview_enable_rps(dev_priv);
6748 } else if (IS_VALLEYVIEW(dev_priv)) {
6749 valleyview_enable_rps(dev_priv);
6750 } else if (INTEL_GEN(dev_priv) >= 9) {
6751 gen9_enable_rc6(dev_priv);
6752 gen9_enable_rps(dev_priv);
6753 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6754 gen6_update_ring_freq(dev_priv);
6755 } else if (IS_BROADWELL(dev_priv)) {
6756 gen8_enable_rps(dev_priv);
6757 gen6_update_ring_freq(dev_priv);
6758 } else if (INTEL_GEN(dev_priv) >= 6) {
6759 gen6_enable_rps(dev_priv);
6760 gen6_update_ring_freq(dev_priv);
6761 } else if (IS_IRONLAKE_M(dev_priv)) {
6762 ironlake_enable_drps(dev_priv);
6763 intel_init_emon(dev_priv);
6764 }
6765
6766 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6767 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6768
6769 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6770 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6771
6772 dev_priv->rps.enabled = true;
6773 mutex_unlock(&dev_priv->rps.hw_lock);
6774 }
6775
6776 static void __intel_autoenable_gt_powersave(struct work_struct *work)
6777 {
6778 struct drm_i915_private *dev_priv =
6779 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6780 struct intel_engine_cs *rcs;
6781 struct drm_i915_gem_request *req;
6782
6783 if (READ_ONCE(dev_priv->rps.enabled))
6784 goto out;
6785
6786 rcs = dev_priv->engine[RCS];
6787 if (rcs->last_context)
6788 goto out;
6789
6790 if (!rcs->init_context)
6791 goto out;
6792
6793 mutex_lock(&dev_priv->drm.struct_mutex);
6794
6795 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6796 if (IS_ERR(req))
6797 goto unlock;
6798
6799 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6800 rcs->init_context(req);
6801
6802 /* Mark the device busy, calling intel_enable_gt_powersave() */
6803 i915_add_request_no_flush(req);
6804
6805 unlock:
6806 mutex_unlock(&dev_priv->drm.struct_mutex);
6807 out:
6808 intel_runtime_pm_put(dev_priv);
6809 }
6810
6811 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6812 {
6813 if (READ_ONCE(dev_priv->rps.enabled))
6814 return;
6815
6816 if (IS_IRONLAKE_M(dev_priv)) {
6817 ironlake_enable_drps(dev_priv);
6818 intel_init_emon(dev_priv);
6819 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6820 /*
6821 * PCU communication is slow and this doesn't need to be
6822 * done at any specific time, so do this out of our fast path
6823 * to make resume and init faster.
6824 *
6825 * We depend on the HW RC6 power context save/restore
6826 * mechanism when entering D3 through runtime PM suspend. So
6827 * disable RPM until RPS/RC6 is properly setup. We can only
6828 * get here via the driver load/system resume/runtime resume
6829 * paths, so the _noresume version is enough (and in case of
6830 * runtime resume it's necessary).
6831 */
6832 if (queue_delayed_work(dev_priv->wq,
6833 &dev_priv->rps.autoenable_work,
6834 round_jiffies_up_relative(HZ)))
6835 intel_runtime_pm_get_noresume(dev_priv);
6836 }
6837 }
6838
6839 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
6840 {
6841 /*
6842 * On Ibex Peak and Cougar Point, we need to disable clock
6843 * gating for the panel power sequencer or it will fail to
6844 * start up when no ports are active.
6845 */
6846 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6847 }
6848
6849 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
6850 {
6851 enum pipe pipe;
6852
6853 for_each_pipe(dev_priv, pipe) {
6854 I915_WRITE(DSPCNTR(pipe),
6855 I915_READ(DSPCNTR(pipe)) |
6856 DISPPLANE_TRICKLE_FEED_DISABLE);
6857
6858 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6859 POSTING_READ(DSPSURF(pipe));
6860 }
6861 }
6862
6863 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
6864 {
6865 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6866 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6867 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6868
6869 /*
6870 * Don't touch WM1S_LP_EN here.
6871 * Doing so could cause underruns.
6872 */
6873 }
6874
6875 static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
6876 {
6877 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6878
6879 /*
6880 * Required for FBC
6881 * WaFbcDisableDpfcClockGating:ilk
6882 */
6883 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6884 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6885 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6886
6887 I915_WRITE(PCH_3DCGDIS0,
6888 MARIUNIT_CLOCK_GATE_DISABLE |
6889 SVSMUNIT_CLOCK_GATE_DISABLE);
6890 I915_WRITE(PCH_3DCGDIS1,
6891 VFMUNIT_CLOCK_GATE_DISABLE);
6892
6893 /*
6894 * According to the spec the following bits should be set in
6895 * order to enable memory self-refresh
6896 * The bit 22/21 of 0x42004
6897 * The bit 5 of 0x42020
6898 * The bit 15 of 0x45000
6899 */
6900 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6901 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6902 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6903 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6904 I915_WRITE(DISP_ARB_CTL,
6905 (I915_READ(DISP_ARB_CTL) |
6906 DISP_FBC_WM_DIS));
6907
6908 ilk_init_lp_watermarks(dev_priv);
6909
6910 /*
6911 * Based on the document from hardware guys the following bits
6912 * should be set unconditionally in order to enable FBC.
6913 * The bit 22 of 0x42000
6914 * The bit 22 of 0x42004
6915 * The bit 7,8,9 of 0x42020.
6916 */
6917 if (IS_IRONLAKE_M(dev_priv)) {
6918 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6919 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6920 I915_READ(ILK_DISPLAY_CHICKEN1) |
6921 ILK_FBCQ_DIS);
6922 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6923 I915_READ(ILK_DISPLAY_CHICKEN2) |
6924 ILK_DPARB_GATE);
6925 }
6926
6927 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6928
6929 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6930 I915_READ(ILK_DISPLAY_CHICKEN2) |
6931 ILK_ELPIN_409_SELECT);
6932 I915_WRITE(_3D_CHICKEN2,
6933 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6934 _3D_CHICKEN2_WM_READ_PIPELINED);
6935
6936 /* WaDisableRenderCachePipelinedFlush:ilk */
6937 I915_WRITE(CACHE_MODE_0,
6938 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6939
6940 /* WaDisable_RenderCache_OperationalFlush:ilk */
6941 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6942
6943 g4x_disable_trickle_feed(dev_priv);
6944
6945 ibx_init_clock_gating(dev_priv);
6946 }
6947
6948 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
6949 {
6950 int pipe;
6951 uint32_t val;
6952
6953 /*
6954 * On Ibex Peak and Cougar Point, we need to disable clock
6955 * gating for the panel power sequencer or it will fail to
6956 * start up when no ports are active.
6957 */
6958 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6959 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6960 PCH_CPUNIT_CLOCK_GATE_DISABLE);
6961 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6962 DPLS_EDP_PPS_FIX_DIS);
6963 /* The below fixes the weird display corruption, a few pixels shifted
6964 * downward, on (only) LVDS of some HP laptops with IVY.
6965 */
6966 for_each_pipe(dev_priv, pipe) {
6967 val = I915_READ(TRANS_CHICKEN2(pipe));
6968 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6969 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6970 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6971 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6972 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6973 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6974 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6975 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6976 }
6977 /* WADP0ClockGatingDisable */
6978 for_each_pipe(dev_priv, pipe) {
6979 I915_WRITE(TRANS_CHICKEN1(pipe),
6980 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6981 }
6982 }
6983
6984 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
6985 {
6986 uint32_t tmp;
6987
6988 tmp = I915_READ(MCH_SSKPD);
6989 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6990 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6991 tmp);
6992 }
6993
6994 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
6995 {
6996 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6997
6998 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6999
7000 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7001 I915_READ(ILK_DISPLAY_CHICKEN2) |
7002 ILK_ELPIN_409_SELECT);
7003
7004 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
7005 I915_WRITE(_3D_CHICKEN,
7006 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7007
7008 /* WaDisable_RenderCache_OperationalFlush:snb */
7009 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7010
7011 /*
7012 * BSpec recoomends 8x4 when MSAA is used,
7013 * however in practice 16x4 seems fastest.
7014 *
7015 * Note that PS/WM thread counts depend on the WIZ hashing
7016 * disable bit, which we don't touch here, but it's good
7017 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7018 */
7019 I915_WRITE(GEN6_GT_MODE,
7020 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7021
7022 ilk_init_lp_watermarks(dev_priv);
7023
7024 I915_WRITE(CACHE_MODE_0,
7025 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
7026
7027 I915_WRITE(GEN6_UCGCTL1,
7028 I915_READ(GEN6_UCGCTL1) |
7029 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7030 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7031
7032 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7033 * gating disable must be set. Failure to set it results in
7034 * flickering pixels due to Z write ordering failures after
7035 * some amount of runtime in the Mesa "fire" demo, and Unigine
7036 * Sanctuary and Tropics, and apparently anything else with
7037 * alpha test or pixel discard.
7038 *
7039 * According to the spec, bit 11 (RCCUNIT) must also be set,
7040 * but we didn't debug actual testcases to find it out.
7041 *
7042 * WaDisableRCCUnitClockGating:snb
7043 * WaDisableRCPBUnitClockGating:snb
7044 */
7045 I915_WRITE(GEN6_UCGCTL2,
7046 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7047 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7048
7049 /* WaStripsFansDisableFastClipPerformanceFix:snb */
7050 I915_WRITE(_3D_CHICKEN3,
7051 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
7052
7053 /*
7054 * Bspec says:
7055 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7056 * 3DSTATE_SF number of SF output attributes is more than 16."
7057 */
7058 I915_WRITE(_3D_CHICKEN3,
7059 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7060
7061 /*
7062 * According to the spec the following bits should be
7063 * set in order to enable memory self-refresh and fbc:
7064 * The bit21 and bit22 of 0x42000
7065 * The bit21 and bit22 of 0x42004
7066 * The bit5 and bit7 of 0x42020
7067 * The bit14 of 0x70180
7068 * The bit14 of 0x71180
7069 *
7070 * WaFbcAsynchFlipDisableFbcQueue:snb
7071 */
7072 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7073 I915_READ(ILK_DISPLAY_CHICKEN1) |
7074 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7075 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7076 I915_READ(ILK_DISPLAY_CHICKEN2) |
7077 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7078 I915_WRITE(ILK_DSPCLK_GATE_D,
7079 I915_READ(ILK_DSPCLK_GATE_D) |
7080 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7081 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7082
7083 g4x_disable_trickle_feed(dev_priv);
7084
7085 cpt_init_clock_gating(dev_priv);
7086
7087 gen6_check_mch_setup(dev_priv);
7088 }
7089
7090 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7091 {
7092 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7093
7094 /*
7095 * WaVSThreadDispatchOverride:ivb,vlv
7096 *
7097 * This actually overrides the dispatch
7098 * mode for all thread types.
7099 */
7100 reg &= ~GEN7_FF_SCHED_MASK;
7101 reg |= GEN7_FF_TS_SCHED_HW;
7102 reg |= GEN7_FF_VS_SCHED_HW;
7103 reg |= GEN7_FF_DS_SCHED_HW;
7104
7105 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7106 }
7107
7108 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
7109 {
7110 /*
7111 * TODO: this bit should only be enabled when really needed, then
7112 * disabled when not needed anymore in order to save power.
7113 */
7114 if (HAS_PCH_LPT_LP(dev_priv))
7115 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7116 I915_READ(SOUTH_DSPCLK_GATE_D) |
7117 PCH_LP_PARTITION_LEVEL_DISABLE);
7118
7119 /* WADPOClockGatingDisable:hsw */
7120 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7121 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7122 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7123 }
7124
7125 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
7126 {
7127 if (HAS_PCH_LPT_LP(dev_priv)) {
7128 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7129
7130 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7131 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7132 }
7133 }
7134
7135 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7136 int general_prio_credits,
7137 int high_prio_credits)
7138 {
7139 u32 misccpctl;
7140
7141 /* WaTempDisableDOPClkGating:bdw */
7142 misccpctl = I915_READ(GEN7_MISCCPCTL);
7143 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7144
7145 I915_WRITE(GEN8_L3SQCREG1,
7146 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7147 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7148
7149 /*
7150 * Wait at least 100 clocks before re-enabling clock gating.
7151 * See the definition of L3SQCREG1 in BSpec.
7152 */
7153 POSTING_READ(GEN8_L3SQCREG1);
7154 udelay(1);
7155 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7156 }
7157
7158 static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
7159 {
7160 gen9_init_clock_gating(dev_priv);
7161
7162 /* WaDisableSDEUnitClockGating:kbl */
7163 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7164 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7165 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7166
7167 /* WaDisableGamClockGating:kbl */
7168 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7169 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7170 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7171
7172 /* WaFbcNukeOnHostModify:kbl */
7173 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7174 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7175 }
7176
7177 static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
7178 {
7179 gen9_init_clock_gating(dev_priv);
7180
7181 /* WAC6entrylatency:skl */
7182 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7183 FBC_LLC_FULLY_OPEN);
7184
7185 /* WaFbcNukeOnHostModify:skl */
7186 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7187 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7188 }
7189
7190 static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
7191 {
7192 enum pipe pipe;
7193
7194 ilk_init_lp_watermarks(dev_priv);
7195
7196 /* WaSwitchSolVfFArbitrationPriority:bdw */
7197 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7198
7199 /* WaPsrDPAMaskVBlankInSRD:bdw */
7200 I915_WRITE(CHICKEN_PAR1_1,
7201 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7202
7203 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7204 for_each_pipe(dev_priv, pipe) {
7205 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7206 I915_READ(CHICKEN_PIPESL_1(pipe)) |
7207 BDW_DPRS_MASK_VBLANK_SRD);
7208 }
7209
7210 /* WaVSRefCountFullforceMissDisable:bdw */
7211 /* WaDSRefCountFullforceMissDisable:bdw */
7212 I915_WRITE(GEN7_FF_THREAD_MODE,
7213 I915_READ(GEN7_FF_THREAD_MODE) &
7214 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7215
7216 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7217 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7218
7219 /* WaDisableSDEUnitClockGating:bdw */
7220 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7221 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7222
7223 /* WaProgramL3SqcReg1Default:bdw */
7224 gen8_set_l3sqc_credits(dev_priv, 30, 2);
7225
7226 /*
7227 * WaGttCachingOffByDefault:bdw
7228 * GTT cache may not work with big pages, so if those
7229 * are ever enabled GTT cache may need to be disabled.
7230 */
7231 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7232
7233 /* WaKVMNotificationOnConfigChange:bdw */
7234 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7235 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7236
7237 lpt_init_clock_gating(dev_priv);
7238 }
7239
7240 static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
7241 {
7242 ilk_init_lp_watermarks(dev_priv);
7243
7244 /* L3 caching of data atomics doesn't work -- disable it. */
7245 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7246 I915_WRITE(HSW_ROW_CHICKEN3,
7247 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7248
7249 /* This is required by WaCatErrorRejectionIssue:hsw */
7250 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7251 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7252 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7253
7254 /* WaVSRefCountFullforceMissDisable:hsw */
7255 I915_WRITE(GEN7_FF_THREAD_MODE,
7256 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7257
7258 /* WaDisable_RenderCache_OperationalFlush:hsw */
7259 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7260
7261 /* enable HiZ Raw Stall Optimization */
7262 I915_WRITE(CACHE_MODE_0_GEN7,
7263 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7264
7265 /* WaDisable4x2SubspanOptimization:hsw */
7266 I915_WRITE(CACHE_MODE_1,
7267 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7268
7269 /*
7270 * BSpec recommends 8x4 when MSAA is used,
7271 * however in practice 16x4 seems fastest.
7272 *
7273 * Note that PS/WM thread counts depend on the WIZ hashing
7274 * disable bit, which we don't touch here, but it's good
7275 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7276 */
7277 I915_WRITE(GEN7_GT_MODE,
7278 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7279
7280 /* WaSampleCChickenBitEnable:hsw */
7281 I915_WRITE(HALF_SLICE_CHICKEN3,
7282 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7283
7284 /* WaSwitchSolVfFArbitrationPriority:hsw */
7285 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7286
7287 /* WaRsPkgCStateDisplayPMReq:hsw */
7288 I915_WRITE(CHICKEN_PAR1_1,
7289 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7290
7291 lpt_init_clock_gating(dev_priv);
7292 }
7293
7294 static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
7295 {
7296 uint32_t snpcr;
7297
7298 ilk_init_lp_watermarks(dev_priv);
7299
7300 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7301
7302 /* WaDisableEarlyCull:ivb */
7303 I915_WRITE(_3D_CHICKEN3,
7304 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7305
7306 /* WaDisableBackToBackFlipFix:ivb */
7307 I915_WRITE(IVB_CHICKEN3,
7308 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7309 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7310
7311 /* WaDisablePSDDualDispatchEnable:ivb */
7312 if (IS_IVB_GT1(dev_priv))
7313 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7314 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7315
7316 /* WaDisable_RenderCache_OperationalFlush:ivb */
7317 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7318
7319 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7320 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7321 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7322
7323 /* WaApplyL3ControlAndL3ChickenMode:ivb */
7324 I915_WRITE(GEN7_L3CNTLREG1,
7325 GEN7_WA_FOR_GEN7_L3_CONTROL);
7326 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7327 GEN7_WA_L3_CHICKEN_MODE);
7328 if (IS_IVB_GT1(dev_priv))
7329 I915_WRITE(GEN7_ROW_CHICKEN2,
7330 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7331 else {
7332 /* must write both registers */
7333 I915_WRITE(GEN7_ROW_CHICKEN2,
7334 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7335 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7336 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7337 }
7338
7339 /* WaForceL3Serialization:ivb */
7340 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7341 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7342
7343 /*
7344 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7345 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7346 */
7347 I915_WRITE(GEN6_UCGCTL2,
7348 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7349
7350 /* This is required by WaCatErrorRejectionIssue:ivb */
7351 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7352 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7353 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7354
7355 g4x_disable_trickle_feed(dev_priv);
7356
7357 gen7_setup_fixed_func_scheduler(dev_priv);
7358
7359 if (0) { /* causes HiZ corruption on ivb:gt1 */
7360 /* enable HiZ Raw Stall Optimization */
7361 I915_WRITE(CACHE_MODE_0_GEN7,
7362 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7363 }
7364
7365 /* WaDisable4x2SubspanOptimization:ivb */
7366 I915_WRITE(CACHE_MODE_1,
7367 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7368
7369 /*
7370 * BSpec recommends 8x4 when MSAA is used,
7371 * however in practice 16x4 seems fastest.
7372 *
7373 * Note that PS/WM thread counts depend on the WIZ hashing
7374 * disable bit, which we don't touch here, but it's good
7375 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7376 */
7377 I915_WRITE(GEN7_GT_MODE,
7378 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7379
7380 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7381 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7382 snpcr |= GEN6_MBC_SNPCR_MED;
7383 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7384
7385 if (!HAS_PCH_NOP(dev_priv))
7386 cpt_init_clock_gating(dev_priv);
7387
7388 gen6_check_mch_setup(dev_priv);
7389 }
7390
7391 static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
7392 {
7393 /* WaDisableEarlyCull:vlv */
7394 I915_WRITE(_3D_CHICKEN3,
7395 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7396
7397 /* WaDisableBackToBackFlipFix:vlv */
7398 I915_WRITE(IVB_CHICKEN3,
7399 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7400 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7401
7402 /* WaPsdDispatchEnable:vlv */
7403 /* WaDisablePSDDualDispatchEnable:vlv */
7404 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7405 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7406 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7407
7408 /* WaDisable_RenderCache_OperationalFlush:vlv */
7409 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7410
7411 /* WaForceL3Serialization:vlv */
7412 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7413 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7414
7415 /* WaDisableDopClockGating:vlv */
7416 I915_WRITE(GEN7_ROW_CHICKEN2,
7417 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7418
7419 /* This is required by WaCatErrorRejectionIssue:vlv */
7420 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7421 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7422 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7423
7424 gen7_setup_fixed_func_scheduler(dev_priv);
7425
7426 /*
7427 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7428 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7429 */
7430 I915_WRITE(GEN6_UCGCTL2,
7431 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7432
7433 /* WaDisableL3Bank2xClockGate:vlv
7434 * Disabling L3 clock gating- MMIO 940c[25] = 1
7435 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7436 I915_WRITE(GEN7_UCGCTL4,
7437 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7438
7439 /*
7440 * BSpec says this must be set, even though
7441 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7442 */
7443 I915_WRITE(CACHE_MODE_1,
7444 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7445
7446 /*
7447 * BSpec recommends 8x4 when MSAA is used,
7448 * however in practice 16x4 seems fastest.
7449 *
7450 * Note that PS/WM thread counts depend on the WIZ hashing
7451 * disable bit, which we don't touch here, but it's good
7452 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7453 */
7454 I915_WRITE(GEN7_GT_MODE,
7455 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7456
7457 /*
7458 * WaIncreaseL3CreditsForVLVB0:vlv
7459 * This is the hardware default actually.
7460 */
7461 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7462
7463 /*
7464 * WaDisableVLVClockGating_VBIIssue:vlv
7465 * Disable clock gating on th GCFG unit to prevent a delay
7466 * in the reporting of vblank events.
7467 */
7468 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7469 }
7470
7471 static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
7472 {
7473 /* WaVSRefCountFullforceMissDisable:chv */
7474 /* WaDSRefCountFullforceMissDisable:chv */
7475 I915_WRITE(GEN7_FF_THREAD_MODE,
7476 I915_READ(GEN7_FF_THREAD_MODE) &
7477 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7478
7479 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7480 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7481 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7482
7483 /* WaDisableCSUnitClockGating:chv */
7484 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7485 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7486
7487 /* WaDisableSDEUnitClockGating:chv */
7488 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7489 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7490
7491 /*
7492 * WaProgramL3SqcReg1Default:chv
7493 * See gfxspecs/Related Documents/Performance Guide/
7494 * LSQC Setting Recommendations.
7495 */
7496 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7497
7498 /*
7499 * GTT cache may not work with big pages, so if those
7500 * are ever enabled GTT cache may need to be disabled.
7501 */
7502 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7503 }
7504
7505 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
7506 {
7507 uint32_t dspclk_gate;
7508
7509 I915_WRITE(RENCLK_GATE_D1, 0);
7510 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7511 GS_UNIT_CLOCK_GATE_DISABLE |
7512 CL_UNIT_CLOCK_GATE_DISABLE);
7513 I915_WRITE(RAMCLK_GATE_D, 0);
7514 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7515 OVRUNIT_CLOCK_GATE_DISABLE |
7516 OVCUNIT_CLOCK_GATE_DISABLE;
7517 if (IS_GM45(dev_priv))
7518 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7519 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7520
7521 /* WaDisableRenderCachePipelinedFlush */
7522 I915_WRITE(CACHE_MODE_0,
7523 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7524
7525 /* WaDisable_RenderCache_OperationalFlush:g4x */
7526 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7527
7528 g4x_disable_trickle_feed(dev_priv);
7529 }
7530
7531 static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
7532 {
7533 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7534 I915_WRITE(RENCLK_GATE_D2, 0);
7535 I915_WRITE(DSPCLK_GATE_D, 0);
7536 I915_WRITE(RAMCLK_GATE_D, 0);
7537 I915_WRITE16(DEUC, 0);
7538 I915_WRITE(MI_ARB_STATE,
7539 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7540
7541 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7542 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7543 }
7544
7545 static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
7546 {
7547 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7548 I965_RCC_CLOCK_GATE_DISABLE |
7549 I965_RCPB_CLOCK_GATE_DISABLE |
7550 I965_ISC_CLOCK_GATE_DISABLE |
7551 I965_FBC_CLOCK_GATE_DISABLE);
7552 I915_WRITE(RENCLK_GATE_D2, 0);
7553 I915_WRITE(MI_ARB_STATE,
7554 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7555
7556 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7557 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7558 }
7559
7560 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
7561 {
7562 u32 dstate = I915_READ(D_STATE);
7563
7564 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7565 DSTATE_DOT_CLOCK_GATING;
7566 I915_WRITE(D_STATE, dstate);
7567
7568 if (IS_PINEVIEW(dev_priv))
7569 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7570
7571 /* IIR "flip pending" means done if this bit is set */
7572 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7573
7574 /* interrupts should cause a wake up from C3 */
7575 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7576
7577 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7578 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7579
7580 I915_WRITE(MI_ARB_STATE,
7581 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7582 }
7583
7584 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
7585 {
7586 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7587
7588 /* interrupts should cause a wake up from C3 */
7589 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7590 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7591
7592 I915_WRITE(MEM_MODE,
7593 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7594 }
7595
7596 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
7597 {
7598 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7599
7600 I915_WRITE(MEM_MODE,
7601 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7602 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7603 }
7604
7605 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
7606 {
7607 dev_priv->display.init_clock_gating(dev_priv);
7608 }
7609
7610 void intel_suspend_hw(struct drm_i915_private *dev_priv)
7611 {
7612 if (HAS_PCH_LPT(dev_priv))
7613 lpt_suspend_hw(dev_priv);
7614 }
7615
7616 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
7617 {
7618 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7619 }
7620
7621 /**
7622 * intel_init_clock_gating_hooks - setup the clock gating hooks
7623 * @dev_priv: device private
7624 *
7625 * Setup the hooks that configure which clocks of a given platform can be
7626 * gated and also apply various GT and display specific workarounds for these
7627 * platforms. Note that some GT specific workarounds are applied separately
7628 * when GPU contexts or batchbuffers start their execution.
7629 */
7630 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7631 {
7632 if (IS_SKYLAKE(dev_priv))
7633 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7634 else if (IS_KABYLAKE(dev_priv))
7635 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7636 else if (IS_BROXTON(dev_priv))
7637 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7638 else if (IS_BROADWELL(dev_priv))
7639 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7640 else if (IS_CHERRYVIEW(dev_priv))
7641 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7642 else if (IS_HASWELL(dev_priv))
7643 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7644 else if (IS_IVYBRIDGE(dev_priv))
7645 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7646 else if (IS_VALLEYVIEW(dev_priv))
7647 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7648 else if (IS_GEN6(dev_priv))
7649 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7650 else if (IS_GEN5(dev_priv))
7651 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7652 else if (IS_G4X(dev_priv))
7653 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7654 else if (IS_CRESTLINE(dev_priv))
7655 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7656 else if (IS_BROADWATER(dev_priv))
7657 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7658 else if (IS_GEN3(dev_priv))
7659 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7660 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7661 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7662 else if (IS_GEN2(dev_priv))
7663 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7664 else {
7665 MISSING_CASE(INTEL_DEVID(dev_priv));
7666 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7667 }
7668 }
7669
7670 /* Set up chip specific power management-related functions */
7671 void intel_init_pm(struct drm_i915_private *dev_priv)
7672 {
7673 intel_fbc_init(dev_priv);
7674
7675 /* For cxsr */
7676 if (IS_PINEVIEW(dev_priv))
7677 i915_pineview_get_mem_freq(dev_priv);
7678 else if (IS_GEN5(dev_priv))
7679 i915_ironlake_get_mem_freq(dev_priv);
7680
7681 /* For FIFO watermark updates */
7682 if (INTEL_GEN(dev_priv) >= 9) {
7683 skl_setup_wm_latency(dev_priv);
7684 dev_priv->display.initial_watermarks = skl_initial_wm;
7685 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
7686 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7687 } else if (HAS_PCH_SPLIT(dev_priv)) {
7688 ilk_setup_wm_latency(dev_priv);
7689
7690 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
7691 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7692 (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
7693 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7694 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7695 dev_priv->display.compute_intermediate_wm =
7696 ilk_compute_intermediate_wm;
7697 dev_priv->display.initial_watermarks =
7698 ilk_initial_watermarks;
7699 dev_priv->display.optimize_watermarks =
7700 ilk_optimize_watermarks;
7701 } else {
7702 DRM_DEBUG_KMS("Failed to read display plane latency. "
7703 "Disable CxSR\n");
7704 }
7705 } else if (IS_CHERRYVIEW(dev_priv)) {
7706 vlv_setup_wm_latency(dev_priv);
7707 dev_priv->display.update_wm = vlv_update_wm;
7708 } else if (IS_VALLEYVIEW(dev_priv)) {
7709 vlv_setup_wm_latency(dev_priv);
7710 dev_priv->display.update_wm = vlv_update_wm;
7711 } else if (IS_PINEVIEW(dev_priv)) {
7712 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
7713 dev_priv->is_ddr3,
7714 dev_priv->fsb_freq,
7715 dev_priv->mem_freq)) {
7716 DRM_INFO("failed to find known CxSR latency "
7717 "(found ddr%s fsb freq %d, mem freq %d), "
7718 "disabling CxSR\n",
7719 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7720 dev_priv->fsb_freq, dev_priv->mem_freq);
7721 /* Disable CxSR and never update its watermark again */
7722 intel_set_memory_cxsr(dev_priv, false);
7723 dev_priv->display.update_wm = NULL;
7724 } else
7725 dev_priv->display.update_wm = pineview_update_wm;
7726 } else if (IS_G4X(dev_priv)) {
7727 dev_priv->display.update_wm = g4x_update_wm;
7728 } else if (IS_GEN4(dev_priv)) {
7729 dev_priv->display.update_wm = i965_update_wm;
7730 } else if (IS_GEN3(dev_priv)) {
7731 dev_priv->display.update_wm = i9xx_update_wm;
7732 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7733 } else if (IS_GEN2(dev_priv)) {
7734 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
7735 dev_priv->display.update_wm = i845_update_wm;
7736 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7737 } else {
7738 dev_priv->display.update_wm = i9xx_update_wm;
7739 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7740 }
7741 } else {
7742 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7743 }
7744 }
7745
7746 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7747 {
7748 uint32_t flags =
7749 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7750
7751 switch (flags) {
7752 case GEN6_PCODE_SUCCESS:
7753 return 0;
7754 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7755 case GEN6_PCODE_ILLEGAL_CMD:
7756 return -ENXIO;
7757 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7758 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7759 return -EOVERFLOW;
7760 case GEN6_PCODE_TIMEOUT:
7761 return -ETIMEDOUT;
7762 default:
7763 MISSING_CASE(flags)
7764 return 0;
7765 }
7766 }
7767
7768 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7769 {
7770 uint32_t flags =
7771 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7772
7773 switch (flags) {
7774 case GEN6_PCODE_SUCCESS:
7775 return 0;
7776 case GEN6_PCODE_ILLEGAL_CMD:
7777 return -ENXIO;
7778 case GEN7_PCODE_TIMEOUT:
7779 return -ETIMEDOUT;
7780 case GEN7_PCODE_ILLEGAL_DATA:
7781 return -EINVAL;
7782 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7783 return -EOVERFLOW;
7784 default:
7785 MISSING_CASE(flags);
7786 return 0;
7787 }
7788 }
7789
7790 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7791 {
7792 int status;
7793
7794 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7795
7796 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7797 * use te fw I915_READ variants to reduce the amount of work
7798 * required when reading/writing.
7799 */
7800
7801 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7802 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7803 return -EAGAIN;
7804 }
7805
7806 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7807 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7808 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7809
7810 if (intel_wait_for_register_fw(dev_priv,
7811 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7812 500)) {
7813 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7814 return -ETIMEDOUT;
7815 }
7816
7817 *val = I915_READ_FW(GEN6_PCODE_DATA);
7818 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7819
7820 if (INTEL_GEN(dev_priv) > 6)
7821 status = gen7_check_mailbox_status(dev_priv);
7822 else
7823 status = gen6_check_mailbox_status(dev_priv);
7824
7825 if (status) {
7826 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7827 status);
7828 return status;
7829 }
7830
7831 return 0;
7832 }
7833
7834 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7835 u32 mbox, u32 val)
7836 {
7837 int status;
7838
7839 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7840
7841 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7842 * use te fw I915_READ variants to reduce the amount of work
7843 * required when reading/writing.
7844 */
7845
7846 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7847 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7848 return -EAGAIN;
7849 }
7850
7851 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7852 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7853
7854 if (intel_wait_for_register_fw(dev_priv,
7855 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7856 500)) {
7857 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7858 return -ETIMEDOUT;
7859 }
7860
7861 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7862
7863 if (INTEL_GEN(dev_priv) > 6)
7864 status = gen7_check_mailbox_status(dev_priv);
7865 else
7866 status = gen6_check_mailbox_status(dev_priv);
7867
7868 if (status) {
7869 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7870 status);
7871 return status;
7872 }
7873
7874 return 0;
7875 }
7876
7877 static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
7878 u32 request, u32 reply_mask, u32 reply,
7879 u32 *status)
7880 {
7881 u32 val = request;
7882
7883 *status = sandybridge_pcode_read(dev_priv, mbox, &val);
7884
7885 return *status || ((val & reply_mask) == reply);
7886 }
7887
7888 /**
7889 * skl_pcode_request - send PCODE request until acknowledgment
7890 * @dev_priv: device private
7891 * @mbox: PCODE mailbox ID the request is targeted for
7892 * @request: request ID
7893 * @reply_mask: mask used to check for request acknowledgment
7894 * @reply: value used to check for request acknowledgment
7895 * @timeout_base_ms: timeout for polling with preemption enabled
7896 *
7897 * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
7898 * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
7899 * The request is acknowledged once the PCODE reply dword equals @reply after
7900 * applying @reply_mask. Polling is first attempted with preemption enabled
7901 * for @timeout_base_ms and if this times out for another 50 ms with
7902 * preemption disabled.
7903 *
7904 * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
7905 * other error as reported by PCODE.
7906 */
7907 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
7908 u32 reply_mask, u32 reply, int timeout_base_ms)
7909 {
7910 u32 status;
7911 int ret;
7912
7913 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7914
7915 #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
7916 &status)
7917
7918 /*
7919 * Prime the PCODE by doing a request first. Normally it guarantees
7920 * that a subsequent request, at most @timeout_base_ms later, succeeds.
7921 * _wait_for() doesn't guarantee when its passed condition is evaluated
7922 * first, so send the first request explicitly.
7923 */
7924 if (COND) {
7925 ret = 0;
7926 goto out;
7927 }
7928 ret = _wait_for(COND, timeout_base_ms * 1000, 10);
7929 if (!ret)
7930 goto out;
7931
7932 /*
7933 * The above can time out if the number of requests was low (2 in the
7934 * worst case) _and_ PCODE was busy for some reason even after a
7935 * (queued) request and @timeout_base_ms delay. As a workaround retry
7936 * the poll with preemption disabled to maximize the number of
7937 * requests. Increase the timeout from @timeout_base_ms to 50ms to
7938 * account for interrupts that could reduce the number of these
7939 * requests, and for any quirks of the PCODE firmware that delays
7940 * the request completion.
7941 */
7942 DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
7943 WARN_ON_ONCE(timeout_base_ms > 3);
7944 preempt_disable();
7945 ret = wait_for_atomic(COND, 50);
7946 preempt_enable();
7947
7948 out:
7949 return ret ? ret : status;
7950 #undef COND
7951 }
7952
7953 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7954 {
7955 /*
7956 * N = val - 0xb7
7957 * Slow = Fast = GPLL ref * N
7958 */
7959 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7960 }
7961
7962 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7963 {
7964 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7965 }
7966
7967 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7968 {
7969 /*
7970 * N = val / 2
7971 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7972 */
7973 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7974 }
7975
7976 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7977 {
7978 /* CHV needs even values */
7979 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7980 }
7981
7982 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7983 {
7984 if (IS_GEN9(dev_priv))
7985 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7986 GEN9_FREQ_SCALER);
7987 else if (IS_CHERRYVIEW(dev_priv))
7988 return chv_gpu_freq(dev_priv, val);
7989 else if (IS_VALLEYVIEW(dev_priv))
7990 return byt_gpu_freq(dev_priv, val);
7991 else
7992 return val * GT_FREQUENCY_MULTIPLIER;
7993 }
7994
7995 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7996 {
7997 if (IS_GEN9(dev_priv))
7998 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7999 GT_FREQUENCY_MULTIPLIER);
8000 else if (IS_CHERRYVIEW(dev_priv))
8001 return chv_freq_opcode(dev_priv, val);
8002 else if (IS_VALLEYVIEW(dev_priv))
8003 return byt_freq_opcode(dev_priv, val);
8004 else
8005 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
8006 }
8007
8008 struct request_boost {
8009 struct work_struct work;
8010 struct drm_i915_gem_request *req;
8011 };
8012
8013 static void __intel_rps_boost_work(struct work_struct *work)
8014 {
8015 struct request_boost *boost = container_of(work, struct request_boost, work);
8016 struct drm_i915_gem_request *req = boost->req;
8017
8018 if (!i915_gem_request_completed(req))
8019 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
8020
8021 i915_gem_request_put(req);
8022 kfree(boost);
8023 }
8024
8025 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
8026 {
8027 struct request_boost *boost;
8028
8029 if (req == NULL || INTEL_GEN(req->i915) < 6)
8030 return;
8031
8032 if (i915_gem_request_completed(req))
8033 return;
8034
8035 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8036 if (boost == NULL)
8037 return;
8038
8039 boost->req = i915_gem_request_get(req);
8040
8041 INIT_WORK(&boost->work, __intel_rps_boost_work);
8042 queue_work(req->i915->wq, &boost->work);
8043 }
8044
8045 void intel_pm_setup(struct drm_device *dev)
8046 {
8047 struct drm_i915_private *dev_priv = to_i915(dev);
8048
8049 mutex_init(&dev_priv->rps.hw_lock);
8050 spin_lock_init(&dev_priv->rps.client_lock);
8051
8052 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8053 __intel_autoenable_gt_powersave);
8054 INIT_LIST_HEAD(&dev_priv->rps.clients);
8055
8056 dev_priv->pm.suspended = false;
8057 atomic_set(&dev_priv->pm.wakeref_count, 0);
8058 }
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