2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
29 #include <drm/drm_plane_helper.h>
31 #include "intel_drv.h"
32 #include "../../../platform/x86/intel_ips.h"
33 #include <linux/module.h>
34 #include <drm/drm_atomic_helper.h>
39 * RC6 is a special power stage which allows the GPU to enter an very
40 * low-voltage mode when idle, using down to 0V while at this stage. This
41 * stage is entered automatically when the GPU is idle when RC6 support is
42 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
44 * There are different RC6 modes available in Intel GPU, which differentiate
45 * among each other with the latency required to enter and leave RC6 and
46 * voltage consumed by the GPU in different states.
48 * The combination of the following flags define which states GPU is allowed
49 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
50 * RC6pp is deepest RC6. Their support by hardware varies according to the
51 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
52 * which brings the most power savings; deeper states save more power, but
53 * require higher latency to switch to and wake up.
55 #define INTEL_RC6_ENABLE (1<<0)
56 #define INTEL_RC6p_ENABLE (1<<1)
57 #define INTEL_RC6pp_ENABLE (1<<2)
59 static void gen9_init_clock_gating(struct drm_i915_private
*dev_priv
)
61 if (HAS_LLC(dev_priv
)) {
63 * WaCompressedResourceDisplayNewHashMode:skl,kbl
64 * Display WA#0390: skl,kbl
66 * Must match Sampler, Pixel Back End, and Media. See
67 * WaCompressedResourceSamplerPbeMediaNewHashMode.
69 I915_WRITE(CHICKEN_PAR1_1
,
70 I915_READ(CHICKEN_PAR1_1
) |
71 SKL_DE_COMPRESSED_HASH_MODE
);
74 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
75 I915_WRITE(CHICKEN_PAR1_1
,
76 I915_READ(CHICKEN_PAR1_1
) | SKL_EDP_PSR_FIX_RDWRAP
);
78 I915_WRITE(GEN8_CONFIG0
,
79 I915_READ(GEN8_CONFIG0
) | GEN9_DEFAULT_FIXES
);
81 /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
82 I915_WRITE(GEN8_CHICKEN_DCPR_1
,
83 I915_READ(GEN8_CHICKEN_DCPR_1
) | MASK_WAKEMEM
);
85 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
86 /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
87 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
89 DISP_FBC_MEMORY_WAKE
);
91 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
92 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
93 ILK_DPFC_DISABLE_DUMMY0
);
95 if (IS_SKYLAKE(dev_priv
)) {
96 /* WaDisableDopClockGating */
97 I915_WRITE(GEN7_MISCCPCTL
, I915_READ(GEN7_MISCCPCTL
)
98 & ~GEN7_DOP_CLOCK_GATE_ENABLE
);
102 static void bxt_init_clock_gating(struct drm_i915_private
*dev_priv
)
104 gen9_init_clock_gating(dev_priv
);
106 /* WaDisableSDEUnitClockGating:bxt */
107 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
108 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
112 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
114 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
115 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ
);
118 * Wa: Backlight PWM may stop in the asserted state, causing backlight
121 I915_WRITE(GEN9_CLKGATE_DIS_0
, I915_READ(GEN9_CLKGATE_DIS_0
) |
122 PWM1_GATING_DIS
| PWM2_GATING_DIS
);
125 static void glk_init_clock_gating(struct drm_i915_private
*dev_priv
)
127 gen9_init_clock_gating(dev_priv
);
130 * WaDisablePWMClockGating:glk
131 * Backlight PWM may stop in the asserted state, causing backlight
134 I915_WRITE(GEN9_CLKGATE_DIS_0
, I915_READ(GEN9_CLKGATE_DIS_0
) |
135 PWM1_GATING_DIS
| PWM2_GATING_DIS
);
137 /* WaDDIIOTimeout:glk */
138 if (IS_GLK_REVID(dev_priv
, 0, GLK_REVID_A1
)) {
139 u32 val
= I915_READ(CHICKEN_MISC_2
);
140 val
&= ~(GLK_CL0_PWR_DOWN
|
143 I915_WRITE(CHICKEN_MISC_2
, val
);
148 static void i915_pineview_get_mem_freq(struct drm_i915_private
*dev_priv
)
152 tmp
= I915_READ(CLKCFG
);
154 switch (tmp
& CLKCFG_FSB_MASK
) {
156 dev_priv
->fsb_freq
= 533; /* 133*4 */
159 dev_priv
->fsb_freq
= 800; /* 200*4 */
162 dev_priv
->fsb_freq
= 667; /* 167*4 */
165 dev_priv
->fsb_freq
= 400; /* 100*4 */
169 switch (tmp
& CLKCFG_MEM_MASK
) {
171 dev_priv
->mem_freq
= 533;
174 dev_priv
->mem_freq
= 667;
177 dev_priv
->mem_freq
= 800;
181 /* detect pineview DDR3 setting */
182 tmp
= I915_READ(CSHRDDR3CTL
);
183 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
186 static void i915_ironlake_get_mem_freq(struct drm_i915_private
*dev_priv
)
190 ddrpll
= I915_READ16(DDRMPLL1
);
191 csipll
= I915_READ16(CSIPLL0
);
193 switch (ddrpll
& 0xff) {
195 dev_priv
->mem_freq
= 800;
198 dev_priv
->mem_freq
= 1066;
201 dev_priv
->mem_freq
= 1333;
204 dev_priv
->mem_freq
= 1600;
207 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
209 dev_priv
->mem_freq
= 0;
213 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
215 switch (csipll
& 0x3ff) {
217 dev_priv
->fsb_freq
= 3200;
220 dev_priv
->fsb_freq
= 3733;
223 dev_priv
->fsb_freq
= 4266;
226 dev_priv
->fsb_freq
= 4800;
229 dev_priv
->fsb_freq
= 5333;
232 dev_priv
->fsb_freq
= 5866;
235 dev_priv
->fsb_freq
= 6400;
238 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
240 dev_priv
->fsb_freq
= 0;
244 if (dev_priv
->fsb_freq
== 3200) {
245 dev_priv
->ips
.c_m
= 0;
246 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
247 dev_priv
->ips
.c_m
= 1;
249 dev_priv
->ips
.c_m
= 2;
253 static const struct cxsr_latency cxsr_latency_table
[] = {
254 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
255 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
256 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
257 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
258 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
260 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
261 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
262 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
263 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
264 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
266 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
267 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
268 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
269 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
270 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
272 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
273 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
274 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
275 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
276 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
278 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
279 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
280 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
281 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
282 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
284 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
285 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
286 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
287 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
288 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
291 static const struct cxsr_latency
*intel_get_cxsr_latency(bool is_desktop
,
296 const struct cxsr_latency
*latency
;
299 if (fsb
== 0 || mem
== 0)
302 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
303 latency
= &cxsr_latency_table
[i
];
304 if (is_desktop
== latency
->is_desktop
&&
305 is_ddr3
== latency
->is_ddr3
&&
306 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
310 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
315 static void chv_set_memory_dvfs(struct drm_i915_private
*dev_priv
, bool enable
)
319 mutex_lock(&dev_priv
->pcu_lock
);
321 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
323 val
&= ~FORCE_DDR_HIGH_FREQ
;
325 val
|= FORCE_DDR_HIGH_FREQ
;
326 val
&= ~FORCE_DDR_LOW_FREQ
;
327 val
|= FORCE_DDR_FREQ_REQ_ACK
;
328 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
330 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
331 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3))
332 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
334 mutex_unlock(&dev_priv
->pcu_lock
);
337 static void chv_set_memory_pm5(struct drm_i915_private
*dev_priv
, bool enable
)
341 mutex_lock(&dev_priv
->pcu_lock
);
343 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
345 val
|= DSP_MAXFIFO_PM5_ENABLE
;
347 val
&= ~DSP_MAXFIFO_PM5_ENABLE
;
348 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
350 mutex_unlock(&dev_priv
->pcu_lock
);
353 #define FW_WM(value, plane) \
354 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
356 static bool _intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
361 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
362 was_enabled
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
363 I915_WRITE(FW_BLC_SELF_VLV
, enable
? FW_CSPWRDWNEN
: 0);
364 POSTING_READ(FW_BLC_SELF_VLV
);
365 } else if (IS_G4X(dev_priv
) || IS_I965GM(dev_priv
)) {
366 was_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
367 I915_WRITE(FW_BLC_SELF
, enable
? FW_BLC_SELF_EN
: 0);
368 POSTING_READ(FW_BLC_SELF
);
369 } else if (IS_PINEVIEW(dev_priv
)) {
370 val
= I915_READ(DSPFW3
);
371 was_enabled
= val
& PINEVIEW_SELF_REFRESH_EN
;
373 val
|= PINEVIEW_SELF_REFRESH_EN
;
375 val
&= ~PINEVIEW_SELF_REFRESH_EN
;
376 I915_WRITE(DSPFW3
, val
);
377 POSTING_READ(DSPFW3
);
378 } else if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
)) {
379 was_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
380 val
= enable
? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN
) :
381 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN
);
382 I915_WRITE(FW_BLC_SELF
, val
);
383 POSTING_READ(FW_BLC_SELF
);
384 } else if (IS_I915GM(dev_priv
)) {
386 * FIXME can't find a bit like this for 915G, and
387 * and yet it does have the related watermark in
388 * FW_BLC_SELF. What's going on?
390 was_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
391 val
= enable
? _MASKED_BIT_ENABLE(INSTPM_SELF_EN
) :
392 _MASKED_BIT_DISABLE(INSTPM_SELF_EN
);
393 I915_WRITE(INSTPM
, val
);
394 POSTING_READ(INSTPM
);
399 trace_intel_memory_cxsr(dev_priv
, was_enabled
, enable
);
401 DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
402 enableddisabled(enable
),
403 enableddisabled(was_enabled
));
409 * intel_set_memory_cxsr - Configure CxSR state
410 * @dev_priv: i915 device
411 * @enable: Allow vs. disallow CxSR
413 * Allow or disallow the system to enter a special CxSR
414 * (C-state self refresh) state. What typically happens in CxSR mode
415 * is that several display FIFOs may get combined into a single larger
416 * FIFO for a particular plane (so called max FIFO mode) to allow the
417 * system to defer memory fetches longer, and the memory will enter
420 * Note that enabling CxSR does not guarantee that the system enter
421 * this special mode, nor does it guarantee that the system stays
422 * in that mode once entered. So this just allows/disallows the system
423 * to autonomously utilize the CxSR mode. Other factors such as core
424 * C-states will affect when/if the system actually enters/exits the
427 * Note that on VLV/CHV this actually only controls the max FIFO mode,
428 * and the system is free to enter/exit memory self refresh at any time
429 * even when the use of CxSR has been disallowed.
431 * While the system is actually in the CxSR/max FIFO mode, some plane
432 * control registers will not get latched on vblank. Thus in order to
433 * guarantee the system will respond to changes in the plane registers
434 * we must always disallow CxSR prior to making changes to those registers.
435 * Unfortunately the system will re-evaluate the CxSR conditions at
436 * frame start which happens after vblank start (which is when the plane
437 * registers would get latched), so we can't proceed with the plane update
438 * during the same frame where we disallowed CxSR.
440 * Certain platforms also have a deeper HPLL SR mode. Fortunately the
441 * HPLL SR mode depends on CxSR itself, so we don't have to hand hold
442 * the hardware w.r.t. HPLL SR when writing to plane registers.
443 * Disallowing just CxSR is sufficient.
445 bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
449 mutex_lock(&dev_priv
->wm
.wm_mutex
);
450 ret
= _intel_set_memory_cxsr(dev_priv
, enable
);
451 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
452 dev_priv
->wm
.vlv
.cxsr
= enable
;
453 else if (IS_G4X(dev_priv
))
454 dev_priv
->wm
.g4x
.cxsr
= enable
;
455 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
461 * Latency for FIFO fetches is dependent on several factors:
462 * - memory configuration (speed, channels)
464 * - current MCH state
465 * It can be fairly high in some situations, so here we assume a fairly
466 * pessimal value. It's a tradeoff between extra memory fetches (if we
467 * set this value too high, the FIFO will fetch frequently to stay full)
468 * and power consumption (set it too low to save power and we might see
469 * FIFO underruns and display "flicker").
471 * A value of 5us seems to be a good balance; safe for very low end
472 * platforms but not overly aggressive on lower latency configs.
474 static const int pessimal_latency_ns
= 5000;
476 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
477 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
479 static void vlv_get_fifo_size(struct intel_crtc_state
*crtc_state
)
481 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
482 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
483 struct vlv_fifo_state
*fifo_state
= &crtc_state
->wm
.vlv
.fifo_state
;
484 enum pipe pipe
= crtc
->pipe
;
485 int sprite0_start
, sprite1_start
;
488 uint32_t dsparb
, dsparb2
, dsparb3
;
490 dsparb
= I915_READ(DSPARB
);
491 dsparb2
= I915_READ(DSPARB2
);
492 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 0, 0);
493 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 8, 4);
496 dsparb
= I915_READ(DSPARB
);
497 dsparb2
= I915_READ(DSPARB2
);
498 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 16, 8);
499 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 24, 12);
502 dsparb2
= I915_READ(DSPARB2
);
503 dsparb3
= I915_READ(DSPARB3
);
504 sprite0_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 0, 16);
505 sprite1_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 8, 20);
512 fifo_state
->plane
[PLANE_PRIMARY
] = sprite0_start
;
513 fifo_state
->plane
[PLANE_SPRITE0
] = sprite1_start
- sprite0_start
;
514 fifo_state
->plane
[PLANE_SPRITE1
] = 511 - sprite1_start
;
515 fifo_state
->plane
[PLANE_CURSOR
] = 63;
518 static int i9xx_get_fifo_size(struct drm_i915_private
*dev_priv
, int plane
)
520 uint32_t dsparb
= I915_READ(DSPARB
);
523 size
= dsparb
& 0x7f;
525 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
527 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
528 plane
? "B" : "A", size
);
533 static int i830_get_fifo_size(struct drm_i915_private
*dev_priv
, int plane
)
535 uint32_t dsparb
= I915_READ(DSPARB
);
538 size
= dsparb
& 0x1ff;
540 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
541 size
>>= 1; /* Convert to cachelines */
543 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
544 plane
? "B" : "A", size
);
549 static int i845_get_fifo_size(struct drm_i915_private
*dev_priv
, int plane
)
551 uint32_t dsparb
= I915_READ(DSPARB
);
554 size
= dsparb
& 0x7f;
555 size
>>= 2; /* Convert to cachelines */
557 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
564 /* Pineview has different values for various configs */
565 static const struct intel_watermark_params pineview_display_wm
= {
566 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
567 .max_wm
= PINEVIEW_MAX_WM
,
568 .default_wm
= PINEVIEW_DFT_WM
,
569 .guard_size
= PINEVIEW_GUARD_WM
,
570 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
572 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
573 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
574 .max_wm
= PINEVIEW_MAX_WM
,
575 .default_wm
= PINEVIEW_DFT_HPLLOFF_WM
,
576 .guard_size
= PINEVIEW_GUARD_WM
,
577 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
579 static const struct intel_watermark_params pineview_cursor_wm
= {
580 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
581 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
582 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
583 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
584 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
586 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
587 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
588 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
589 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
590 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
591 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
593 static const struct intel_watermark_params i965_cursor_wm_info
= {
594 .fifo_size
= I965_CURSOR_FIFO
,
595 .max_wm
= I965_CURSOR_MAX_WM
,
596 .default_wm
= I965_CURSOR_DFT_WM
,
598 .cacheline_size
= I915_FIFO_LINE_SIZE
,
600 static const struct intel_watermark_params i945_wm_info
= {
601 .fifo_size
= I945_FIFO_SIZE
,
602 .max_wm
= I915_MAX_WM
,
605 .cacheline_size
= I915_FIFO_LINE_SIZE
,
607 static const struct intel_watermark_params i915_wm_info
= {
608 .fifo_size
= I915_FIFO_SIZE
,
609 .max_wm
= I915_MAX_WM
,
612 .cacheline_size
= I915_FIFO_LINE_SIZE
,
614 static const struct intel_watermark_params i830_a_wm_info
= {
615 .fifo_size
= I855GM_FIFO_SIZE
,
616 .max_wm
= I915_MAX_WM
,
619 .cacheline_size
= I830_FIFO_LINE_SIZE
,
621 static const struct intel_watermark_params i830_bc_wm_info
= {
622 .fifo_size
= I855GM_FIFO_SIZE
,
623 .max_wm
= I915_MAX_WM
/2,
626 .cacheline_size
= I830_FIFO_LINE_SIZE
,
628 static const struct intel_watermark_params i845_wm_info
= {
629 .fifo_size
= I830_FIFO_SIZE
,
630 .max_wm
= I915_MAX_WM
,
633 .cacheline_size
= I830_FIFO_LINE_SIZE
,
637 * intel_wm_method1 - Method 1 / "small buffer" watermark formula
638 * @pixel_rate: Pipe pixel rate in kHz
639 * @cpp: Plane bytes per pixel
640 * @latency: Memory wakeup latency in 0.1us units
642 * Compute the watermark using the method 1 or "small buffer"
643 * formula. The caller may additonally add extra cachelines
644 * to account for TLB misses and clock crossings.
646 * This method is concerned with the short term drain rate
647 * of the FIFO, ie. it does not account for blanking periods
648 * which would effectively reduce the average drain rate across
649 * a longer period. The name "small" refers to the fact the
650 * FIFO is relatively small compared to the amount of data
653 * The FIFO level vs. time graph might look something like:
657 * __---__---__ (- plane active, _ blanking)
660 * or perhaps like this:
663 * __----__----__ (- plane active, _ blanking)
667 * The watermark in bytes
669 static unsigned int intel_wm_method1(unsigned int pixel_rate
,
671 unsigned int latency
)
675 ret
= (uint64_t) pixel_rate
* cpp
* latency
;
676 ret
= DIV_ROUND_UP_ULL(ret
, 10000);
682 * intel_wm_method2 - Method 2 / "large buffer" watermark formula
683 * @pixel_rate: Pipe pixel rate in kHz
684 * @htotal: Pipe horizontal total
685 * @width: Plane width in pixels
686 * @cpp: Plane bytes per pixel
687 * @latency: Memory wakeup latency in 0.1us units
689 * Compute the watermark using the method 2 or "large buffer"
690 * formula. The caller may additonally add extra cachelines
691 * to account for TLB misses and clock crossings.
693 * This method is concerned with the long term drain rate
694 * of the FIFO, ie. it does account for blanking periods
695 * which effectively reduce the average drain rate across
696 * a longer period. The name "large" refers to the fact the
697 * FIFO is relatively large compared to the amount of data
700 * The FIFO level vs. time graph might look something like:
705 * __ --__--__--__--__--__--__ (- plane active, _ blanking)
709 * The watermark in bytes
711 static unsigned int intel_wm_method2(unsigned int pixel_rate
,
715 unsigned int latency
)
720 * FIXME remove once all users are computing
721 * watermarks in the correct place.
723 if (WARN_ON_ONCE(htotal
== 0))
726 ret
= (latency
* pixel_rate
) / (htotal
* 10000);
727 ret
= (ret
+ 1) * width
* cpp
;
733 * intel_calculate_wm - calculate watermark level
734 * @pixel_rate: pixel clock
735 * @wm: chip FIFO params
736 * @cpp: bytes per pixel
737 * @latency_ns: memory latency for the platform
739 * Calculate the watermark level (the level at which the display plane will
740 * start fetching from memory again). Each chip has a different display
741 * FIFO size and allocation, so the caller needs to figure that out and pass
742 * in the correct intel_watermark_params structure.
744 * As the pixel clock runs, the FIFO will be drained at a rate that depends
745 * on the pixel size. When it reaches the watermark level, it'll start
746 * fetching FIFO line sized based chunks from memory until the FIFO fills
747 * past the watermark point. If the FIFO drains completely, a FIFO underrun
748 * will occur, and a display engine hang could result.
750 static unsigned int intel_calculate_wm(int pixel_rate
,
751 const struct intel_watermark_params
*wm
,
752 int fifo_size
, int cpp
,
753 unsigned int latency_ns
)
755 int entries
, wm_size
;
758 * Note: we need to make sure we don't overflow for various clock &
760 * clocks go from a few thousand to several hundred thousand.
761 * latency is usually a few thousand
763 entries
= intel_wm_method1(pixel_rate
, cpp
,
765 entries
= DIV_ROUND_UP(entries
, wm
->cacheline_size
) +
767 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries
);
769 wm_size
= fifo_size
- entries
;
770 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size
);
772 /* Don't promote wm_size to unsigned... */
773 if (wm_size
> wm
->max_wm
)
774 wm_size
= wm
->max_wm
;
776 wm_size
= wm
->default_wm
;
779 * Bspec seems to indicate that the value shouldn't be lower than
780 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
781 * Lets go for 8 which is the burst size since certain platforms
782 * already use a hardcoded 8 (which is what the spec says should be
791 static bool is_disabling(int old
, int new, int threshold
)
793 return old
>= threshold
&& new < threshold
;
796 static bool is_enabling(int old
, int new, int threshold
)
798 return old
< threshold
&& new >= threshold
;
801 static int intel_wm_num_levels(struct drm_i915_private
*dev_priv
)
803 return dev_priv
->wm
.max_level
+ 1;
806 static bool intel_wm_plane_visible(const struct intel_crtc_state
*crtc_state
,
807 const struct intel_plane_state
*plane_state
)
809 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
811 /* FIXME check the 'enable' instead */
812 if (!crtc_state
->base
.active
)
816 * Treat cursor with fb as always visible since cursor updates
817 * can happen faster than the vrefresh rate, and the current
818 * watermark code doesn't handle that correctly. Cursor updates
819 * which set/clear the fb or change the cursor size are going
820 * to get throttled by intel_legacy_cursor_update() to work
821 * around this problem with the watermark code.
823 if (plane
->id
== PLANE_CURSOR
)
824 return plane_state
->base
.fb
!= NULL
;
826 return plane_state
->base
.visible
;
829 static struct intel_crtc
*single_enabled_crtc(struct drm_i915_private
*dev_priv
)
831 struct intel_crtc
*crtc
, *enabled
= NULL
;
833 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
834 if (intel_crtc_active(crtc
)) {
844 static void pineview_update_wm(struct intel_crtc
*unused_crtc
)
846 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
847 struct intel_crtc
*crtc
;
848 const struct cxsr_latency
*latency
;
852 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv
),
857 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
858 intel_set_memory_cxsr(dev_priv
, false);
862 crtc
= single_enabled_crtc(dev_priv
);
864 const struct drm_display_mode
*adjusted_mode
=
865 &crtc
->config
->base
.adjusted_mode
;
866 const struct drm_framebuffer
*fb
=
867 crtc
->base
.primary
->state
->fb
;
868 int cpp
= fb
->format
->cpp
[0];
869 int clock
= adjusted_mode
->crtc_clock
;
872 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
873 pineview_display_wm
.fifo_size
,
874 cpp
, latency
->display_sr
);
875 reg
= I915_READ(DSPFW1
);
876 reg
&= ~DSPFW_SR_MASK
;
877 reg
|= FW_WM(wm
, SR
);
878 I915_WRITE(DSPFW1
, reg
);
879 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
882 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
883 pineview_display_wm
.fifo_size
,
884 4, latency
->cursor_sr
);
885 reg
= I915_READ(DSPFW3
);
886 reg
&= ~DSPFW_CURSOR_SR_MASK
;
887 reg
|= FW_WM(wm
, CURSOR_SR
);
888 I915_WRITE(DSPFW3
, reg
);
890 /* Display HPLL off SR */
891 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
892 pineview_display_hplloff_wm
.fifo_size
,
893 cpp
, latency
->display_hpll_disable
);
894 reg
= I915_READ(DSPFW3
);
895 reg
&= ~DSPFW_HPLL_SR_MASK
;
896 reg
|= FW_WM(wm
, HPLL_SR
);
897 I915_WRITE(DSPFW3
, reg
);
899 /* cursor HPLL off SR */
900 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
901 pineview_display_hplloff_wm
.fifo_size
,
902 4, latency
->cursor_hpll_disable
);
903 reg
= I915_READ(DSPFW3
);
904 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
905 reg
|= FW_WM(wm
, HPLL_CURSOR
);
906 I915_WRITE(DSPFW3
, reg
);
907 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
909 intel_set_memory_cxsr(dev_priv
, true);
911 intel_set_memory_cxsr(dev_priv
, false);
916 * Documentation says:
917 * "If the line size is small, the TLB fetches can get in the way of the
918 * data fetches, causing some lag in the pixel data return which is not
919 * accounted for in the above formulas. The following adjustment only
920 * needs to be applied if eight whole lines fit in the buffer at once.
921 * The WM is adjusted upwards by the difference between the FIFO size
922 * and the size of 8 whole lines. This adjustment is always performed
923 * in the actual pixel depth regardless of whether FBC is enabled or not."
925 static int g4x_tlb_miss_wa(int fifo_size
, int width
, int cpp
)
927 int tlb_miss
= fifo_size
* 64 - width
* cpp
* 8;
929 return max(0, tlb_miss
);
932 static void g4x_write_wm_values(struct drm_i915_private
*dev_priv
,
933 const struct g4x_wm_values
*wm
)
937 for_each_pipe(dev_priv
, pipe
)
938 trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv
, pipe
), wm
);
941 FW_WM(wm
->sr
.plane
, SR
) |
942 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_CURSOR
], CURSORB
) |
943 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
], PLANEB
) |
944 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
], PLANEA
));
946 (wm
->fbc_en
? DSPFW_FBC_SR_EN
: 0) |
947 FW_WM(wm
->sr
.fbc
, FBC_SR
) |
948 FW_WM(wm
->hpll
.fbc
, FBC_HPLL_SR
) |
949 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
], SPRITEB
) |
950 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_CURSOR
], CURSORA
) |
951 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
], SPRITEA
));
953 (wm
->hpll_en
? DSPFW_HPLL_SR_EN
: 0) |
954 FW_WM(wm
->sr
.cursor
, CURSOR_SR
) |
955 FW_WM(wm
->hpll
.cursor
, HPLL_CURSOR
) |
956 FW_WM(wm
->hpll
.plane
, HPLL_SR
));
958 POSTING_READ(DSPFW1
);
961 #define FW_WM_VLV(value, plane) \
962 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
964 static void vlv_write_wm_values(struct drm_i915_private
*dev_priv
,
965 const struct vlv_wm_values
*wm
)
969 for_each_pipe(dev_priv
, pipe
) {
970 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv
, pipe
), wm
);
972 I915_WRITE(VLV_DDL(pipe
),
973 (wm
->ddl
[pipe
].plane
[PLANE_CURSOR
] << DDL_CURSOR_SHIFT
) |
974 (wm
->ddl
[pipe
].plane
[PLANE_SPRITE1
] << DDL_SPRITE_SHIFT(1)) |
975 (wm
->ddl
[pipe
].plane
[PLANE_SPRITE0
] << DDL_SPRITE_SHIFT(0)) |
976 (wm
->ddl
[pipe
].plane
[PLANE_PRIMARY
] << DDL_PLANE_SHIFT
));
980 * Zero the (unused) WM1 watermarks, and also clear all the
981 * high order bits so that there are no out of bounds values
982 * present in the registers during the reprogramming.
984 I915_WRITE(DSPHOWM
, 0);
985 I915_WRITE(DSPHOWM1
, 0);
986 I915_WRITE(DSPFW4
, 0);
987 I915_WRITE(DSPFW5
, 0);
988 I915_WRITE(DSPFW6
, 0);
991 FW_WM(wm
->sr
.plane
, SR
) |
992 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_CURSOR
], CURSORB
) |
993 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
], PLANEB
) |
994 FW_WM_VLV(wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
], PLANEA
));
996 FW_WM_VLV(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
], SPRITEB
) |
997 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_CURSOR
], CURSORA
) |
998 FW_WM_VLV(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
], SPRITEA
));
1000 FW_WM(wm
->sr
.cursor
, CURSOR_SR
));
1002 if (IS_CHERRYVIEW(dev_priv
)) {
1003 I915_WRITE(DSPFW7_CHV
,
1004 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
], SPRITED
) |
1005 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
], SPRITEC
));
1006 I915_WRITE(DSPFW8_CHV
,
1007 FW_WM_VLV(wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE1
], SPRITEF
) |
1008 FW_WM_VLV(wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE0
], SPRITEE
));
1009 I915_WRITE(DSPFW9_CHV
,
1010 FW_WM_VLV(wm
->pipe
[PIPE_C
].plane
[PLANE_PRIMARY
], PLANEC
) |
1011 FW_WM(wm
->pipe
[PIPE_C
].plane
[PLANE_CURSOR
], CURSORC
));
1013 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
1014 FW_WM(wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE1
] >> 8, SPRITEF_HI
) |
1015 FW_WM(wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE0
] >> 8, SPRITEE_HI
) |
1016 FW_WM(wm
->pipe
[PIPE_C
].plane
[PLANE_PRIMARY
] >> 8, PLANEC_HI
) |
1017 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] >> 8, SPRITED_HI
) |
1018 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] >> 8, SPRITEC_HI
) |
1019 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] >> 8, PLANEB_HI
) |
1020 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] >> 8, SPRITEB_HI
) |
1021 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] >> 8, SPRITEA_HI
) |
1022 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] >> 8, PLANEA_HI
));
1025 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
], SPRITED
) |
1026 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
], SPRITEC
));
1028 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
1029 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] >> 8, SPRITED_HI
) |
1030 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] >> 8, SPRITEC_HI
) |
1031 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] >> 8, PLANEB_HI
) |
1032 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] >> 8, SPRITEB_HI
) |
1033 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] >> 8, SPRITEA_HI
) |
1034 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] >> 8, PLANEA_HI
));
1037 POSTING_READ(DSPFW1
);
1042 static void g4x_setup_wm_latency(struct drm_i915_private
*dev_priv
)
1044 /* all latencies in usec */
1045 dev_priv
->wm
.pri_latency
[G4X_WM_LEVEL_NORMAL
] = 5;
1046 dev_priv
->wm
.pri_latency
[G4X_WM_LEVEL_SR
] = 12;
1047 dev_priv
->wm
.pri_latency
[G4X_WM_LEVEL_HPLL
] = 35;
1049 dev_priv
->wm
.max_level
= G4X_WM_LEVEL_HPLL
;
1052 static int g4x_plane_fifo_size(enum plane_id plane_id
, int level
)
1055 * DSPCNTR[13] supposedly controls whether the
1056 * primary plane can use the FIFO space otherwise
1057 * reserved for the sprite plane. It's not 100% clear
1058 * what the actual FIFO size is, but it looks like we
1059 * can happily set both primary and sprite watermarks
1060 * up to 127 cachelines. So that would seem to mean
1061 * that either DSPCNTR[13] doesn't do anything, or that
1062 * the total FIFO is >= 256 cachelines in size. Either
1063 * way, we don't seem to have to worry about this
1064 * repartitioning as the maximum watermark value the
1065 * register can hold for each plane is lower than the
1066 * minimum FIFO size.
1072 return level
== G4X_WM_LEVEL_NORMAL
? 127 : 511;
1074 return level
== G4X_WM_LEVEL_NORMAL
? 127 : 0;
1076 MISSING_CASE(plane_id
);
1081 static int g4x_fbc_fifo_size(int level
)
1084 case G4X_WM_LEVEL_SR
:
1086 case G4X_WM_LEVEL_HPLL
:
1089 MISSING_CASE(level
);
1094 static uint16_t g4x_compute_wm(const struct intel_crtc_state
*crtc_state
,
1095 const struct intel_plane_state
*plane_state
,
1098 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
1099 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
1100 const struct drm_display_mode
*adjusted_mode
=
1101 &crtc_state
->base
.adjusted_mode
;
1102 int clock
, htotal
, cpp
, width
, wm
;
1103 int latency
= dev_priv
->wm
.pri_latency
[level
] * 10;
1108 if (!intel_wm_plane_visible(crtc_state
, plane_state
))
1112 * Not 100% sure which way ELK should go here as the
1113 * spec only says CL/CTG should assume 32bpp and BW
1114 * doesn't need to. But as these things followed the
1115 * mobile vs. desktop lines on gen3 as well, let's
1116 * assume ELK doesn't need this.
1118 * The spec also fails to list such a restriction for
1119 * the HPLL watermark, which seems a little strange.
1120 * Let's use 32bpp for the HPLL watermark as well.
1122 if (IS_GM45(dev_priv
) && plane
->id
== PLANE_PRIMARY
&&
1123 level
!= G4X_WM_LEVEL_NORMAL
)
1126 cpp
= plane_state
->base
.fb
->format
->cpp
[0];
1128 clock
= adjusted_mode
->crtc_clock
;
1129 htotal
= adjusted_mode
->crtc_htotal
;
1131 if (plane
->id
== PLANE_CURSOR
)
1132 width
= plane_state
->base
.crtc_w
;
1134 width
= drm_rect_width(&plane_state
->base
.dst
);
1136 if (plane
->id
== PLANE_CURSOR
) {
1137 wm
= intel_wm_method2(clock
, htotal
, width
, cpp
, latency
);
1138 } else if (plane
->id
== PLANE_PRIMARY
&&
1139 level
== G4X_WM_LEVEL_NORMAL
) {
1140 wm
= intel_wm_method1(clock
, cpp
, latency
);
1144 small
= intel_wm_method1(clock
, cpp
, latency
);
1145 large
= intel_wm_method2(clock
, htotal
, width
, cpp
, latency
);
1147 wm
= min(small
, large
);
1150 wm
+= g4x_tlb_miss_wa(g4x_plane_fifo_size(plane
->id
, level
),
1153 wm
= DIV_ROUND_UP(wm
, 64) + 2;
1155 return min_t(int, wm
, USHRT_MAX
);
1158 static bool g4x_raw_plane_wm_set(struct intel_crtc_state
*crtc_state
,
1159 int level
, enum plane_id plane_id
, u16 value
)
1161 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1164 for (; level
< intel_wm_num_levels(dev_priv
); level
++) {
1165 struct g4x_pipe_wm
*raw
= &crtc_state
->wm
.g4x
.raw
[level
];
1167 dirty
|= raw
->plane
[plane_id
] != value
;
1168 raw
->plane
[plane_id
] = value
;
1174 static bool g4x_raw_fbc_wm_set(struct intel_crtc_state
*crtc_state
,
1175 int level
, u16 value
)
1177 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1180 /* NORMAL level doesn't have an FBC watermark */
1181 level
= max(level
, G4X_WM_LEVEL_SR
);
1183 for (; level
< intel_wm_num_levels(dev_priv
); level
++) {
1184 struct g4x_pipe_wm
*raw
= &crtc_state
->wm
.g4x
.raw
[level
];
1186 dirty
|= raw
->fbc
!= value
;
1193 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state
*cstate
,
1194 const struct intel_plane_state
*pstate
,
1197 static bool g4x_raw_plane_wm_compute(struct intel_crtc_state
*crtc_state
,
1198 const struct intel_plane_state
*plane_state
)
1200 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
1201 int num_levels
= intel_wm_num_levels(to_i915(plane
->base
.dev
));
1202 enum plane_id plane_id
= plane
->id
;
1206 if (!intel_wm_plane_visible(crtc_state
, plane_state
)) {
1207 dirty
|= g4x_raw_plane_wm_set(crtc_state
, 0, plane_id
, 0);
1208 if (plane_id
== PLANE_PRIMARY
)
1209 dirty
|= g4x_raw_fbc_wm_set(crtc_state
, 0, 0);
1213 for (level
= 0; level
< num_levels
; level
++) {
1214 struct g4x_pipe_wm
*raw
= &crtc_state
->wm
.g4x
.raw
[level
];
1217 wm
= g4x_compute_wm(crtc_state
, plane_state
, level
);
1218 max_wm
= g4x_plane_fifo_size(plane_id
, level
);
1223 dirty
|= raw
->plane
[plane_id
] != wm
;
1224 raw
->plane
[plane_id
] = wm
;
1226 if (plane_id
!= PLANE_PRIMARY
||
1227 level
== G4X_WM_LEVEL_NORMAL
)
1230 wm
= ilk_compute_fbc_wm(crtc_state
, plane_state
,
1231 raw
->plane
[plane_id
]);
1232 max_wm
= g4x_fbc_fifo_size(level
);
1235 * FBC wm is not mandatory as we
1236 * can always just disable its use.
1241 dirty
|= raw
->fbc
!= wm
;
1245 /* mark watermarks as invalid */
1246 dirty
|= g4x_raw_plane_wm_set(crtc_state
, level
, plane_id
, USHRT_MAX
);
1248 if (plane_id
== PLANE_PRIMARY
)
1249 dirty
|= g4x_raw_fbc_wm_set(crtc_state
, level
, USHRT_MAX
);
1253 DRM_DEBUG_KMS("%s watermarks: normal=%d, SR=%d, HPLL=%d\n",
1255 crtc_state
->wm
.g4x
.raw
[G4X_WM_LEVEL_NORMAL
].plane
[plane_id
],
1256 crtc_state
->wm
.g4x
.raw
[G4X_WM_LEVEL_SR
].plane
[plane_id
],
1257 crtc_state
->wm
.g4x
.raw
[G4X_WM_LEVEL_HPLL
].plane
[plane_id
]);
1259 if (plane_id
== PLANE_PRIMARY
)
1260 DRM_DEBUG_KMS("FBC watermarks: SR=%d, HPLL=%d\n",
1261 crtc_state
->wm
.g4x
.raw
[G4X_WM_LEVEL_SR
].fbc
,
1262 crtc_state
->wm
.g4x
.raw
[G4X_WM_LEVEL_HPLL
].fbc
);
1268 static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state
*crtc_state
,
1269 enum plane_id plane_id
, int level
)
1271 const struct g4x_pipe_wm
*raw
= &crtc_state
->wm
.g4x
.raw
[level
];
1273 return raw
->plane
[plane_id
] <= g4x_plane_fifo_size(plane_id
, level
);
1276 static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state
*crtc_state
,
1279 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1281 if (level
> dev_priv
->wm
.max_level
)
1284 return g4x_raw_plane_wm_is_valid(crtc_state
, PLANE_PRIMARY
, level
) &&
1285 g4x_raw_plane_wm_is_valid(crtc_state
, PLANE_SPRITE0
, level
) &&
1286 g4x_raw_plane_wm_is_valid(crtc_state
, PLANE_CURSOR
, level
);
1289 /* mark all levels starting from 'level' as invalid */
1290 static void g4x_invalidate_wms(struct intel_crtc
*crtc
,
1291 struct g4x_wm_state
*wm_state
, int level
)
1293 if (level
<= G4X_WM_LEVEL_NORMAL
) {
1294 enum plane_id plane_id
;
1296 for_each_plane_id_on_crtc(crtc
, plane_id
)
1297 wm_state
->wm
.plane
[plane_id
] = USHRT_MAX
;
1300 if (level
<= G4X_WM_LEVEL_SR
) {
1301 wm_state
->cxsr
= false;
1302 wm_state
->sr
.cursor
= USHRT_MAX
;
1303 wm_state
->sr
.plane
= USHRT_MAX
;
1304 wm_state
->sr
.fbc
= USHRT_MAX
;
1307 if (level
<= G4X_WM_LEVEL_HPLL
) {
1308 wm_state
->hpll_en
= false;
1309 wm_state
->hpll
.cursor
= USHRT_MAX
;
1310 wm_state
->hpll
.plane
= USHRT_MAX
;
1311 wm_state
->hpll
.fbc
= USHRT_MAX
;
1315 static int g4x_compute_pipe_wm(struct intel_crtc_state
*crtc_state
)
1317 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1318 struct intel_atomic_state
*state
=
1319 to_intel_atomic_state(crtc_state
->base
.state
);
1320 struct g4x_wm_state
*wm_state
= &crtc_state
->wm
.g4x
.optimal
;
1321 int num_active_planes
= hweight32(crtc_state
->active_planes
&
1322 ~BIT(PLANE_CURSOR
));
1323 const struct g4x_pipe_wm
*raw
;
1324 const struct intel_plane_state
*old_plane_state
;
1325 const struct intel_plane_state
*new_plane_state
;
1326 struct intel_plane
*plane
;
1327 enum plane_id plane_id
;
1329 unsigned int dirty
= 0;
1331 for_each_oldnew_intel_plane_in_state(state
, plane
,
1333 new_plane_state
, i
) {
1334 if (new_plane_state
->base
.crtc
!= &crtc
->base
&&
1335 old_plane_state
->base
.crtc
!= &crtc
->base
)
1338 if (g4x_raw_plane_wm_compute(crtc_state
, new_plane_state
))
1339 dirty
|= BIT(plane
->id
);
1345 level
= G4X_WM_LEVEL_NORMAL
;
1346 if (!g4x_raw_crtc_wm_is_valid(crtc_state
, level
))
1349 raw
= &crtc_state
->wm
.g4x
.raw
[level
];
1350 for_each_plane_id_on_crtc(crtc
, plane_id
)
1351 wm_state
->wm
.plane
[plane_id
] = raw
->plane
[plane_id
];
1353 level
= G4X_WM_LEVEL_SR
;
1355 if (!g4x_raw_crtc_wm_is_valid(crtc_state
, level
))
1358 raw
= &crtc_state
->wm
.g4x
.raw
[level
];
1359 wm_state
->sr
.plane
= raw
->plane
[PLANE_PRIMARY
];
1360 wm_state
->sr
.cursor
= raw
->plane
[PLANE_CURSOR
];
1361 wm_state
->sr
.fbc
= raw
->fbc
;
1363 wm_state
->cxsr
= num_active_planes
== BIT(PLANE_PRIMARY
);
1365 level
= G4X_WM_LEVEL_HPLL
;
1367 if (!g4x_raw_crtc_wm_is_valid(crtc_state
, level
))
1370 raw
= &crtc_state
->wm
.g4x
.raw
[level
];
1371 wm_state
->hpll
.plane
= raw
->plane
[PLANE_PRIMARY
];
1372 wm_state
->hpll
.cursor
= raw
->plane
[PLANE_CURSOR
];
1373 wm_state
->hpll
.fbc
= raw
->fbc
;
1375 wm_state
->hpll_en
= wm_state
->cxsr
;
1380 if (level
== G4X_WM_LEVEL_NORMAL
)
1383 /* invalidate the higher levels */
1384 g4x_invalidate_wms(crtc
, wm_state
, level
);
1387 * Determine if the FBC watermark(s) can be used. IF
1388 * this isn't the case we prefer to disable the FBC
1389 ( watermark(s) rather than disable the SR/HPLL
1390 * level(s) entirely.
1392 wm_state
->fbc_en
= level
> G4X_WM_LEVEL_NORMAL
;
1394 if (level
>= G4X_WM_LEVEL_SR
&&
1395 wm_state
->sr
.fbc
> g4x_fbc_fifo_size(G4X_WM_LEVEL_SR
))
1396 wm_state
->fbc_en
= false;
1397 else if (level
>= G4X_WM_LEVEL_HPLL
&&
1398 wm_state
->hpll
.fbc
> g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL
))
1399 wm_state
->fbc_en
= false;
1404 static int g4x_compute_intermediate_wm(struct drm_device
*dev
,
1405 struct intel_crtc
*crtc
,
1406 struct intel_crtc_state
*crtc_state
)
1408 struct g4x_wm_state
*intermediate
= &crtc_state
->wm
.g4x
.intermediate
;
1409 const struct g4x_wm_state
*optimal
= &crtc_state
->wm
.g4x
.optimal
;
1410 const struct g4x_wm_state
*active
= &crtc
->wm
.active
.g4x
;
1411 enum plane_id plane_id
;
1413 intermediate
->cxsr
= optimal
->cxsr
&& active
->cxsr
&&
1414 !crtc_state
->disable_cxsr
;
1415 intermediate
->hpll_en
= optimal
->hpll_en
&& active
->hpll_en
&&
1416 !crtc_state
->disable_cxsr
;
1417 intermediate
->fbc_en
= optimal
->fbc_en
&& active
->fbc_en
;
1419 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1420 intermediate
->wm
.plane
[plane_id
] =
1421 max(optimal
->wm
.plane
[plane_id
],
1422 active
->wm
.plane
[plane_id
]);
1424 WARN_ON(intermediate
->wm
.plane
[plane_id
] >
1425 g4x_plane_fifo_size(plane_id
, G4X_WM_LEVEL_NORMAL
));
1428 intermediate
->sr
.plane
= max(optimal
->sr
.plane
,
1430 intermediate
->sr
.cursor
= max(optimal
->sr
.cursor
,
1432 intermediate
->sr
.fbc
= max(optimal
->sr
.fbc
,
1435 intermediate
->hpll
.plane
= max(optimal
->hpll
.plane
,
1436 active
->hpll
.plane
);
1437 intermediate
->hpll
.cursor
= max(optimal
->hpll
.cursor
,
1438 active
->hpll
.cursor
);
1439 intermediate
->hpll
.fbc
= max(optimal
->hpll
.fbc
,
1442 WARN_ON((intermediate
->sr
.plane
>
1443 g4x_plane_fifo_size(PLANE_PRIMARY
, G4X_WM_LEVEL_SR
) ||
1444 intermediate
->sr
.cursor
>
1445 g4x_plane_fifo_size(PLANE_CURSOR
, G4X_WM_LEVEL_SR
)) &&
1446 intermediate
->cxsr
);
1447 WARN_ON((intermediate
->sr
.plane
>
1448 g4x_plane_fifo_size(PLANE_PRIMARY
, G4X_WM_LEVEL_HPLL
) ||
1449 intermediate
->sr
.cursor
>
1450 g4x_plane_fifo_size(PLANE_CURSOR
, G4X_WM_LEVEL_HPLL
)) &&
1451 intermediate
->hpll_en
);
1453 WARN_ON(intermediate
->sr
.fbc
> g4x_fbc_fifo_size(1) &&
1454 intermediate
->fbc_en
&& intermediate
->cxsr
);
1455 WARN_ON(intermediate
->hpll
.fbc
> g4x_fbc_fifo_size(2) &&
1456 intermediate
->fbc_en
&& intermediate
->hpll_en
);
1459 * If our intermediate WM are identical to the final WM, then we can
1460 * omit the post-vblank programming; only update if it's different.
1462 if (memcmp(intermediate
, optimal
, sizeof(*intermediate
)) != 0)
1463 crtc_state
->wm
.need_postvbl_update
= true;
1468 static void g4x_merge_wm(struct drm_i915_private
*dev_priv
,
1469 struct g4x_wm_values
*wm
)
1471 struct intel_crtc
*crtc
;
1472 int num_active_crtcs
= 0;
1478 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
1479 const struct g4x_wm_state
*wm_state
= &crtc
->wm
.active
.g4x
;
1484 if (!wm_state
->cxsr
)
1486 if (!wm_state
->hpll_en
)
1487 wm
->hpll_en
= false;
1488 if (!wm_state
->fbc_en
)
1494 if (num_active_crtcs
!= 1) {
1496 wm
->hpll_en
= false;
1500 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
1501 const struct g4x_wm_state
*wm_state
= &crtc
->wm
.active
.g4x
;
1502 enum pipe pipe
= crtc
->pipe
;
1504 wm
->pipe
[pipe
] = wm_state
->wm
;
1505 if (crtc
->active
&& wm
->cxsr
)
1506 wm
->sr
= wm_state
->sr
;
1507 if (crtc
->active
&& wm
->hpll_en
)
1508 wm
->hpll
= wm_state
->hpll
;
1512 static void g4x_program_watermarks(struct drm_i915_private
*dev_priv
)
1514 struct g4x_wm_values
*old_wm
= &dev_priv
->wm
.g4x
;
1515 struct g4x_wm_values new_wm
= {};
1517 g4x_merge_wm(dev_priv
, &new_wm
);
1519 if (memcmp(old_wm
, &new_wm
, sizeof(new_wm
)) == 0)
1522 if (is_disabling(old_wm
->cxsr
, new_wm
.cxsr
, true))
1523 _intel_set_memory_cxsr(dev_priv
, false);
1525 g4x_write_wm_values(dev_priv
, &new_wm
);
1527 if (is_enabling(old_wm
->cxsr
, new_wm
.cxsr
, true))
1528 _intel_set_memory_cxsr(dev_priv
, true);
1533 static void g4x_initial_watermarks(struct intel_atomic_state
*state
,
1534 struct intel_crtc_state
*crtc_state
)
1536 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1537 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1539 mutex_lock(&dev_priv
->wm
.wm_mutex
);
1540 crtc
->wm
.active
.g4x
= crtc_state
->wm
.g4x
.intermediate
;
1541 g4x_program_watermarks(dev_priv
);
1542 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
1545 static void g4x_optimize_watermarks(struct intel_atomic_state
*state
,
1546 struct intel_crtc_state
*crtc_state
)
1548 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1549 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1551 if (!crtc_state
->wm
.need_postvbl_update
)
1554 mutex_lock(&dev_priv
->wm
.wm_mutex
);
1555 intel_crtc
->wm
.active
.g4x
= crtc_state
->wm
.g4x
.optimal
;
1556 g4x_program_watermarks(dev_priv
);
1557 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
1560 /* latency must be in 0.1us units. */
1561 static unsigned int vlv_wm_method2(unsigned int pixel_rate
,
1562 unsigned int htotal
,
1565 unsigned int latency
)
1569 ret
= intel_wm_method2(pixel_rate
, htotal
,
1570 width
, cpp
, latency
);
1571 ret
= DIV_ROUND_UP(ret
, 64);
1576 static void vlv_setup_wm_latency(struct drm_i915_private
*dev_priv
)
1578 /* all latencies in usec */
1579 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM2
] = 3;
1581 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM2
;
1583 if (IS_CHERRYVIEW(dev_priv
)) {
1584 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM5
] = 12;
1585 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_DDR_DVFS
] = 33;
1587 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_DDR_DVFS
;
1591 static uint16_t vlv_compute_wm_level(const struct intel_crtc_state
*crtc_state
,
1592 const struct intel_plane_state
*plane_state
,
1595 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
1596 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
1597 const struct drm_display_mode
*adjusted_mode
=
1598 &crtc_state
->base
.adjusted_mode
;
1599 int clock
, htotal
, cpp
, width
, wm
;
1601 if (dev_priv
->wm
.pri_latency
[level
] == 0)
1604 if (!intel_wm_plane_visible(crtc_state
, plane_state
))
1607 cpp
= plane_state
->base
.fb
->format
->cpp
[0];
1608 clock
= adjusted_mode
->crtc_clock
;
1609 htotal
= adjusted_mode
->crtc_htotal
;
1610 width
= crtc_state
->pipe_src_w
;
1612 if (plane
->id
== PLANE_CURSOR
) {
1614 * FIXME the formula gives values that are
1615 * too big for the cursor FIFO, and hence we
1616 * would never be able to use cursors. For
1617 * now just hardcode the watermark.
1621 wm
= vlv_wm_method2(clock
, htotal
, width
, cpp
,
1622 dev_priv
->wm
.pri_latency
[level
] * 10);
1625 return min_t(int, wm
, USHRT_MAX
);
1628 static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes
)
1630 return (active_planes
& (BIT(PLANE_SPRITE0
) |
1631 BIT(PLANE_SPRITE1
))) == BIT(PLANE_SPRITE1
);
1634 static int vlv_compute_fifo(struct intel_crtc_state
*crtc_state
)
1636 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1637 const struct g4x_pipe_wm
*raw
=
1638 &crtc_state
->wm
.vlv
.raw
[VLV_WM_LEVEL_PM2
];
1639 struct vlv_fifo_state
*fifo_state
= &crtc_state
->wm
.vlv
.fifo_state
;
1640 unsigned int active_planes
= crtc_state
->active_planes
& ~BIT(PLANE_CURSOR
);
1641 int num_active_planes
= hweight32(active_planes
);
1642 const int fifo_size
= 511;
1643 int fifo_extra
, fifo_left
= fifo_size
;
1644 int sprite0_fifo_extra
= 0;
1645 unsigned int total_rate
;
1646 enum plane_id plane_id
;
1649 * When enabling sprite0 after sprite1 has already been enabled
1650 * we tend to get an underrun unless sprite0 already has some
1651 * FIFO space allcoated. Hence we always allocate at least one
1652 * cacheline for sprite0 whenever sprite1 is enabled.
1654 * All other plane enable sequences appear immune to this problem.
1656 if (vlv_need_sprite0_fifo_workaround(active_planes
))
1657 sprite0_fifo_extra
= 1;
1659 total_rate
= raw
->plane
[PLANE_PRIMARY
] +
1660 raw
->plane
[PLANE_SPRITE0
] +
1661 raw
->plane
[PLANE_SPRITE1
] +
1664 if (total_rate
> fifo_size
)
1667 if (total_rate
== 0)
1670 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1673 if ((active_planes
& BIT(plane_id
)) == 0) {
1674 fifo_state
->plane
[plane_id
] = 0;
1678 rate
= raw
->plane
[plane_id
];
1679 fifo_state
->plane
[plane_id
] = fifo_size
* rate
/ total_rate
;
1680 fifo_left
-= fifo_state
->plane
[plane_id
];
1683 fifo_state
->plane
[PLANE_SPRITE0
] += sprite0_fifo_extra
;
1684 fifo_left
-= sprite0_fifo_extra
;
1686 fifo_state
->plane
[PLANE_CURSOR
] = 63;
1688 fifo_extra
= DIV_ROUND_UP(fifo_left
, num_active_planes
?: 1);
1690 /* spread the remainder evenly */
1691 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1697 if ((active_planes
& BIT(plane_id
)) == 0)
1700 plane_extra
= min(fifo_extra
, fifo_left
);
1701 fifo_state
->plane
[plane_id
] += plane_extra
;
1702 fifo_left
-= plane_extra
;
1705 WARN_ON(active_planes
!= 0 && fifo_left
!= 0);
1707 /* give it all to the first plane if none are active */
1708 if (active_planes
== 0) {
1709 WARN_ON(fifo_left
!= fifo_size
);
1710 fifo_state
->plane
[PLANE_PRIMARY
] = fifo_left
;
1716 /* mark all levels starting from 'level' as invalid */
1717 static void vlv_invalidate_wms(struct intel_crtc
*crtc
,
1718 struct vlv_wm_state
*wm_state
, int level
)
1720 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1722 for (; level
< intel_wm_num_levels(dev_priv
); level
++) {
1723 enum plane_id plane_id
;
1725 for_each_plane_id_on_crtc(crtc
, plane_id
)
1726 wm_state
->wm
[level
].plane
[plane_id
] = USHRT_MAX
;
1728 wm_state
->sr
[level
].cursor
= USHRT_MAX
;
1729 wm_state
->sr
[level
].plane
= USHRT_MAX
;
1733 static u16
vlv_invert_wm_value(u16 wm
, u16 fifo_size
)
1738 return fifo_size
- wm
;
1742 * Starting from 'level' set all higher
1743 * levels to 'value' in the "raw" watermarks.
1745 static bool vlv_raw_plane_wm_set(struct intel_crtc_state
*crtc_state
,
1746 int level
, enum plane_id plane_id
, u16 value
)
1748 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1749 int num_levels
= intel_wm_num_levels(dev_priv
);
1752 for (; level
< num_levels
; level
++) {
1753 struct g4x_pipe_wm
*raw
= &crtc_state
->wm
.vlv
.raw
[level
];
1755 dirty
|= raw
->plane
[plane_id
] != value
;
1756 raw
->plane
[plane_id
] = value
;
1762 static bool vlv_raw_plane_wm_compute(struct intel_crtc_state
*crtc_state
,
1763 const struct intel_plane_state
*plane_state
)
1765 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
1766 enum plane_id plane_id
= plane
->id
;
1767 int num_levels
= intel_wm_num_levels(to_i915(plane
->base
.dev
));
1771 if (!intel_wm_plane_visible(crtc_state
, plane_state
)) {
1772 dirty
|= vlv_raw_plane_wm_set(crtc_state
, 0, plane_id
, 0);
1776 for (level
= 0; level
< num_levels
; level
++) {
1777 struct g4x_pipe_wm
*raw
= &crtc_state
->wm
.vlv
.raw
[level
];
1778 int wm
= vlv_compute_wm_level(crtc_state
, plane_state
, level
);
1779 int max_wm
= plane_id
== PLANE_CURSOR
? 63 : 511;
1784 dirty
|= raw
->plane
[plane_id
] != wm
;
1785 raw
->plane
[plane_id
] = wm
;
1788 /* mark all higher levels as invalid */
1789 dirty
|= vlv_raw_plane_wm_set(crtc_state
, level
, plane_id
, USHRT_MAX
);
1793 DRM_DEBUG_KMS("%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n",
1795 crtc_state
->wm
.vlv
.raw
[VLV_WM_LEVEL_PM2
].plane
[plane_id
],
1796 crtc_state
->wm
.vlv
.raw
[VLV_WM_LEVEL_PM5
].plane
[plane_id
],
1797 crtc_state
->wm
.vlv
.raw
[VLV_WM_LEVEL_DDR_DVFS
].plane
[plane_id
]);
1802 static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state
*crtc_state
,
1803 enum plane_id plane_id
, int level
)
1805 const struct g4x_pipe_wm
*raw
=
1806 &crtc_state
->wm
.vlv
.raw
[level
];
1807 const struct vlv_fifo_state
*fifo_state
=
1808 &crtc_state
->wm
.vlv
.fifo_state
;
1810 return raw
->plane
[plane_id
] <= fifo_state
->plane
[plane_id
];
1813 static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state
*crtc_state
, int level
)
1815 return vlv_raw_plane_wm_is_valid(crtc_state
, PLANE_PRIMARY
, level
) &&
1816 vlv_raw_plane_wm_is_valid(crtc_state
, PLANE_SPRITE0
, level
) &&
1817 vlv_raw_plane_wm_is_valid(crtc_state
, PLANE_SPRITE1
, level
) &&
1818 vlv_raw_plane_wm_is_valid(crtc_state
, PLANE_CURSOR
, level
);
1821 static int vlv_compute_pipe_wm(struct intel_crtc_state
*crtc_state
)
1823 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1824 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1825 struct intel_atomic_state
*state
=
1826 to_intel_atomic_state(crtc_state
->base
.state
);
1827 struct vlv_wm_state
*wm_state
= &crtc_state
->wm
.vlv
.optimal
;
1828 const struct vlv_fifo_state
*fifo_state
=
1829 &crtc_state
->wm
.vlv
.fifo_state
;
1830 int num_active_planes
= hweight32(crtc_state
->active_planes
&
1831 ~BIT(PLANE_CURSOR
));
1832 bool needs_modeset
= drm_atomic_crtc_needs_modeset(&crtc_state
->base
);
1833 const struct intel_plane_state
*old_plane_state
;
1834 const struct intel_plane_state
*new_plane_state
;
1835 struct intel_plane
*plane
;
1836 enum plane_id plane_id
;
1838 unsigned int dirty
= 0;
1840 for_each_oldnew_intel_plane_in_state(state
, plane
,
1842 new_plane_state
, i
) {
1843 if (new_plane_state
->base
.crtc
!= &crtc
->base
&&
1844 old_plane_state
->base
.crtc
!= &crtc
->base
)
1847 if (vlv_raw_plane_wm_compute(crtc_state
, new_plane_state
))
1848 dirty
|= BIT(plane
->id
);
1852 * DSPARB registers may have been reset due to the
1853 * power well being turned off. Make sure we restore
1854 * them to a consistent state even if no primary/sprite
1855 * planes are initially active.
1858 crtc_state
->fifo_changed
= true;
1863 /* cursor changes don't warrant a FIFO recompute */
1864 if (dirty
& ~BIT(PLANE_CURSOR
)) {
1865 const struct intel_crtc_state
*old_crtc_state
=
1866 intel_atomic_get_old_crtc_state(state
, crtc
);
1867 const struct vlv_fifo_state
*old_fifo_state
=
1868 &old_crtc_state
->wm
.vlv
.fifo_state
;
1870 ret
= vlv_compute_fifo(crtc_state
);
1874 if (needs_modeset
||
1875 memcmp(old_fifo_state
, fifo_state
,
1876 sizeof(*fifo_state
)) != 0)
1877 crtc_state
->fifo_changed
= true;
1880 /* initially allow all levels */
1881 wm_state
->num_levels
= intel_wm_num_levels(dev_priv
);
1883 * Note that enabling cxsr with no primary/sprite planes
1884 * enabled can wedge the pipe. Hence we only allow cxsr
1885 * with exactly one enabled primary/sprite plane.
1887 wm_state
->cxsr
= crtc
->pipe
!= PIPE_C
&& num_active_planes
== 1;
1889 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1890 const struct g4x_pipe_wm
*raw
= &crtc_state
->wm
.vlv
.raw
[level
];
1891 const int sr_fifo_size
= INTEL_INFO(dev_priv
)->num_pipes
* 512 - 1;
1893 if (!vlv_raw_crtc_wm_is_valid(crtc_state
, level
))
1896 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1897 wm_state
->wm
[level
].plane
[plane_id
] =
1898 vlv_invert_wm_value(raw
->plane
[plane_id
],
1899 fifo_state
->plane
[plane_id
]);
1902 wm_state
->sr
[level
].plane
=
1903 vlv_invert_wm_value(max3(raw
->plane
[PLANE_PRIMARY
],
1904 raw
->plane
[PLANE_SPRITE0
],
1905 raw
->plane
[PLANE_SPRITE1
]),
1908 wm_state
->sr
[level
].cursor
=
1909 vlv_invert_wm_value(raw
->plane
[PLANE_CURSOR
],
1916 /* limit to only levels we can actually handle */
1917 wm_state
->num_levels
= level
;
1919 /* invalidate the higher levels */
1920 vlv_invalidate_wms(crtc
, wm_state
, level
);
1925 #define VLV_FIFO(plane, value) \
1926 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1928 static void vlv_atomic_update_fifo(struct intel_atomic_state
*state
,
1929 struct intel_crtc_state
*crtc_state
)
1931 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1932 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1933 const struct vlv_fifo_state
*fifo_state
=
1934 &crtc_state
->wm
.vlv
.fifo_state
;
1935 int sprite0_start
, sprite1_start
, fifo_size
;
1937 if (!crtc_state
->fifo_changed
)
1940 sprite0_start
= fifo_state
->plane
[PLANE_PRIMARY
];
1941 sprite1_start
= fifo_state
->plane
[PLANE_SPRITE0
] + sprite0_start
;
1942 fifo_size
= fifo_state
->plane
[PLANE_SPRITE1
] + sprite1_start
;
1944 WARN_ON(fifo_state
->plane
[PLANE_CURSOR
] != 63);
1945 WARN_ON(fifo_size
!= 511);
1947 trace_vlv_fifo_size(crtc
, sprite0_start
, sprite1_start
, fifo_size
);
1950 * uncore.lock serves a double purpose here. It allows us to
1951 * use the less expensive I915_{READ,WRITE}_FW() functions, and
1952 * it protects the DSPARB registers from getting clobbered by
1953 * parallel updates from multiple pipes.
1955 * intel_pipe_update_start() has already disabled interrupts
1956 * for us, so a plain spin_lock() is sufficient here.
1958 spin_lock(&dev_priv
->uncore
.lock
);
1960 switch (crtc
->pipe
) {
1961 uint32_t dsparb
, dsparb2
, dsparb3
;
1963 dsparb
= I915_READ_FW(DSPARB
);
1964 dsparb2
= I915_READ_FW(DSPARB2
);
1966 dsparb
&= ~(VLV_FIFO(SPRITEA
, 0xff) |
1967 VLV_FIFO(SPRITEB
, 0xff));
1968 dsparb
|= (VLV_FIFO(SPRITEA
, sprite0_start
) |
1969 VLV_FIFO(SPRITEB
, sprite1_start
));
1971 dsparb2
&= ~(VLV_FIFO(SPRITEA_HI
, 0x1) |
1972 VLV_FIFO(SPRITEB_HI
, 0x1));
1973 dsparb2
|= (VLV_FIFO(SPRITEA_HI
, sprite0_start
>> 8) |
1974 VLV_FIFO(SPRITEB_HI
, sprite1_start
>> 8));
1976 I915_WRITE_FW(DSPARB
, dsparb
);
1977 I915_WRITE_FW(DSPARB2
, dsparb2
);
1980 dsparb
= I915_READ_FW(DSPARB
);
1981 dsparb2
= I915_READ_FW(DSPARB2
);
1983 dsparb
&= ~(VLV_FIFO(SPRITEC
, 0xff) |
1984 VLV_FIFO(SPRITED
, 0xff));
1985 dsparb
|= (VLV_FIFO(SPRITEC
, sprite0_start
) |
1986 VLV_FIFO(SPRITED
, sprite1_start
));
1988 dsparb2
&= ~(VLV_FIFO(SPRITEC_HI
, 0xff) |
1989 VLV_FIFO(SPRITED_HI
, 0xff));
1990 dsparb2
|= (VLV_FIFO(SPRITEC_HI
, sprite0_start
>> 8) |
1991 VLV_FIFO(SPRITED_HI
, sprite1_start
>> 8));
1993 I915_WRITE_FW(DSPARB
, dsparb
);
1994 I915_WRITE_FW(DSPARB2
, dsparb2
);
1997 dsparb3
= I915_READ_FW(DSPARB3
);
1998 dsparb2
= I915_READ_FW(DSPARB2
);
2000 dsparb3
&= ~(VLV_FIFO(SPRITEE
, 0xff) |
2001 VLV_FIFO(SPRITEF
, 0xff));
2002 dsparb3
|= (VLV_FIFO(SPRITEE
, sprite0_start
) |
2003 VLV_FIFO(SPRITEF
, sprite1_start
));
2005 dsparb2
&= ~(VLV_FIFO(SPRITEE_HI
, 0xff) |
2006 VLV_FIFO(SPRITEF_HI
, 0xff));
2007 dsparb2
|= (VLV_FIFO(SPRITEE_HI
, sprite0_start
>> 8) |
2008 VLV_FIFO(SPRITEF_HI
, sprite1_start
>> 8));
2010 I915_WRITE_FW(DSPARB3
, dsparb3
);
2011 I915_WRITE_FW(DSPARB2
, dsparb2
);
2017 POSTING_READ_FW(DSPARB
);
2019 spin_unlock(&dev_priv
->uncore
.lock
);
2024 static int vlv_compute_intermediate_wm(struct drm_device
*dev
,
2025 struct intel_crtc
*crtc
,
2026 struct intel_crtc_state
*crtc_state
)
2028 struct vlv_wm_state
*intermediate
= &crtc_state
->wm
.vlv
.intermediate
;
2029 const struct vlv_wm_state
*optimal
= &crtc_state
->wm
.vlv
.optimal
;
2030 const struct vlv_wm_state
*active
= &crtc
->wm
.active
.vlv
;
2033 intermediate
->num_levels
= min(optimal
->num_levels
, active
->num_levels
);
2034 intermediate
->cxsr
= optimal
->cxsr
&& active
->cxsr
&&
2035 !crtc_state
->disable_cxsr
;
2037 for (level
= 0; level
< intermediate
->num_levels
; level
++) {
2038 enum plane_id plane_id
;
2040 for_each_plane_id_on_crtc(crtc
, plane_id
) {
2041 intermediate
->wm
[level
].plane
[plane_id
] =
2042 min(optimal
->wm
[level
].plane
[plane_id
],
2043 active
->wm
[level
].plane
[plane_id
]);
2046 intermediate
->sr
[level
].plane
= min(optimal
->sr
[level
].plane
,
2047 active
->sr
[level
].plane
);
2048 intermediate
->sr
[level
].cursor
= min(optimal
->sr
[level
].cursor
,
2049 active
->sr
[level
].cursor
);
2052 vlv_invalidate_wms(crtc
, intermediate
, level
);
2055 * If our intermediate WM are identical to the final WM, then we can
2056 * omit the post-vblank programming; only update if it's different.
2058 if (memcmp(intermediate
, optimal
, sizeof(*intermediate
)) != 0)
2059 crtc_state
->wm
.need_postvbl_update
= true;
2064 static void vlv_merge_wm(struct drm_i915_private
*dev_priv
,
2065 struct vlv_wm_values
*wm
)
2067 struct intel_crtc
*crtc
;
2068 int num_active_crtcs
= 0;
2070 wm
->level
= dev_priv
->wm
.max_level
;
2073 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
2074 const struct vlv_wm_state
*wm_state
= &crtc
->wm
.active
.vlv
;
2079 if (!wm_state
->cxsr
)
2083 wm
->level
= min_t(int, wm
->level
, wm_state
->num_levels
- 1);
2086 if (num_active_crtcs
!= 1)
2089 if (num_active_crtcs
> 1)
2090 wm
->level
= VLV_WM_LEVEL_PM2
;
2092 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
2093 const struct vlv_wm_state
*wm_state
= &crtc
->wm
.active
.vlv
;
2094 enum pipe pipe
= crtc
->pipe
;
2096 wm
->pipe
[pipe
] = wm_state
->wm
[wm
->level
];
2097 if (crtc
->active
&& wm
->cxsr
)
2098 wm
->sr
= wm_state
->sr
[wm
->level
];
2100 wm
->ddl
[pipe
].plane
[PLANE_PRIMARY
] = DDL_PRECISION_HIGH
| 2;
2101 wm
->ddl
[pipe
].plane
[PLANE_SPRITE0
] = DDL_PRECISION_HIGH
| 2;
2102 wm
->ddl
[pipe
].plane
[PLANE_SPRITE1
] = DDL_PRECISION_HIGH
| 2;
2103 wm
->ddl
[pipe
].plane
[PLANE_CURSOR
] = DDL_PRECISION_HIGH
| 2;
2107 static void vlv_program_watermarks(struct drm_i915_private
*dev_priv
)
2109 struct vlv_wm_values
*old_wm
= &dev_priv
->wm
.vlv
;
2110 struct vlv_wm_values new_wm
= {};
2112 vlv_merge_wm(dev_priv
, &new_wm
);
2114 if (memcmp(old_wm
, &new_wm
, sizeof(new_wm
)) == 0)
2117 if (is_disabling(old_wm
->level
, new_wm
.level
, VLV_WM_LEVEL_DDR_DVFS
))
2118 chv_set_memory_dvfs(dev_priv
, false);
2120 if (is_disabling(old_wm
->level
, new_wm
.level
, VLV_WM_LEVEL_PM5
))
2121 chv_set_memory_pm5(dev_priv
, false);
2123 if (is_disabling(old_wm
->cxsr
, new_wm
.cxsr
, true))
2124 _intel_set_memory_cxsr(dev_priv
, false);
2126 vlv_write_wm_values(dev_priv
, &new_wm
);
2128 if (is_enabling(old_wm
->cxsr
, new_wm
.cxsr
, true))
2129 _intel_set_memory_cxsr(dev_priv
, true);
2131 if (is_enabling(old_wm
->level
, new_wm
.level
, VLV_WM_LEVEL_PM5
))
2132 chv_set_memory_pm5(dev_priv
, true);
2134 if (is_enabling(old_wm
->level
, new_wm
.level
, VLV_WM_LEVEL_DDR_DVFS
))
2135 chv_set_memory_dvfs(dev_priv
, true);
2140 static void vlv_initial_watermarks(struct intel_atomic_state
*state
,
2141 struct intel_crtc_state
*crtc_state
)
2143 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
2144 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
2146 mutex_lock(&dev_priv
->wm
.wm_mutex
);
2147 crtc
->wm
.active
.vlv
= crtc_state
->wm
.vlv
.intermediate
;
2148 vlv_program_watermarks(dev_priv
);
2149 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
2152 static void vlv_optimize_watermarks(struct intel_atomic_state
*state
,
2153 struct intel_crtc_state
*crtc_state
)
2155 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
2156 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
2158 if (!crtc_state
->wm
.need_postvbl_update
)
2161 mutex_lock(&dev_priv
->wm
.wm_mutex
);
2162 intel_crtc
->wm
.active
.vlv
= crtc_state
->wm
.vlv
.optimal
;
2163 vlv_program_watermarks(dev_priv
);
2164 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
2167 static void i965_update_wm(struct intel_crtc
*unused_crtc
)
2169 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
2170 struct intel_crtc
*crtc
;
2175 /* Calc sr entries for one plane configs */
2176 crtc
= single_enabled_crtc(dev_priv
);
2178 /* self-refresh has much higher latency */
2179 static const int sr_latency_ns
= 12000;
2180 const struct drm_display_mode
*adjusted_mode
=
2181 &crtc
->config
->base
.adjusted_mode
;
2182 const struct drm_framebuffer
*fb
=
2183 crtc
->base
.primary
->state
->fb
;
2184 int clock
= adjusted_mode
->crtc_clock
;
2185 int htotal
= adjusted_mode
->crtc_htotal
;
2186 int hdisplay
= crtc
->config
->pipe_src_w
;
2187 int cpp
= fb
->format
->cpp
[0];
2190 entries
= intel_wm_method2(clock
, htotal
,
2191 hdisplay
, cpp
, sr_latency_ns
/ 100);
2192 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
2193 srwm
= I965_FIFO_SIZE
- entries
;
2197 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
2200 entries
= intel_wm_method2(clock
, htotal
,
2201 crtc
->base
.cursor
->state
->crtc_w
, 4,
2202 sr_latency_ns
/ 100);
2203 entries
= DIV_ROUND_UP(entries
,
2204 i965_cursor_wm_info
.cacheline_size
) +
2205 i965_cursor_wm_info
.guard_size
;
2207 cursor_sr
= i965_cursor_wm_info
.fifo_size
- entries
;
2208 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
2209 cursor_sr
= i965_cursor_wm_info
.max_wm
;
2211 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
2212 "cursor %d\n", srwm
, cursor_sr
);
2214 cxsr_enabled
= true;
2216 cxsr_enabled
= false;
2217 /* Turn off self refresh if both pipes are enabled */
2218 intel_set_memory_cxsr(dev_priv
, false);
2221 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2224 /* 965 has limitations... */
2225 I915_WRITE(DSPFW1
, FW_WM(srwm
, SR
) |
2229 I915_WRITE(DSPFW2
, FW_WM(8, CURSORA
) |
2230 FW_WM(8, PLANEC_OLD
));
2231 /* update cursor SR watermark */
2232 I915_WRITE(DSPFW3
, FW_WM(cursor_sr
, CURSOR_SR
));
2235 intel_set_memory_cxsr(dev_priv
, true);
2240 static void i9xx_update_wm(struct intel_crtc
*unused_crtc
)
2242 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
2243 const struct intel_watermark_params
*wm_info
;
2248 int planea_wm
, planeb_wm
;
2249 struct intel_crtc
*crtc
, *enabled
= NULL
;
2251 if (IS_I945GM(dev_priv
))
2252 wm_info
= &i945_wm_info
;
2253 else if (!IS_GEN2(dev_priv
))
2254 wm_info
= &i915_wm_info
;
2256 wm_info
= &i830_a_wm_info
;
2258 fifo_size
= dev_priv
->display
.get_fifo_size(dev_priv
, 0);
2259 crtc
= intel_get_crtc_for_plane(dev_priv
, 0);
2260 if (intel_crtc_active(crtc
)) {
2261 const struct drm_display_mode
*adjusted_mode
=
2262 &crtc
->config
->base
.adjusted_mode
;
2263 const struct drm_framebuffer
*fb
=
2264 crtc
->base
.primary
->state
->fb
;
2267 if (IS_GEN2(dev_priv
))
2270 cpp
= fb
->format
->cpp
[0];
2272 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
2273 wm_info
, fifo_size
, cpp
,
2274 pessimal_latency_ns
);
2277 planea_wm
= fifo_size
- wm_info
->guard_size
;
2278 if (planea_wm
> (long)wm_info
->max_wm
)
2279 planea_wm
= wm_info
->max_wm
;
2282 if (IS_GEN2(dev_priv
))
2283 wm_info
= &i830_bc_wm_info
;
2285 fifo_size
= dev_priv
->display
.get_fifo_size(dev_priv
, 1);
2286 crtc
= intel_get_crtc_for_plane(dev_priv
, 1);
2287 if (intel_crtc_active(crtc
)) {
2288 const struct drm_display_mode
*adjusted_mode
=
2289 &crtc
->config
->base
.adjusted_mode
;
2290 const struct drm_framebuffer
*fb
=
2291 crtc
->base
.primary
->state
->fb
;
2294 if (IS_GEN2(dev_priv
))
2297 cpp
= fb
->format
->cpp
[0];
2299 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
2300 wm_info
, fifo_size
, cpp
,
2301 pessimal_latency_ns
);
2302 if (enabled
== NULL
)
2307 planeb_wm
= fifo_size
- wm_info
->guard_size
;
2308 if (planeb_wm
> (long)wm_info
->max_wm
)
2309 planeb_wm
= wm_info
->max_wm
;
2312 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
2314 if (IS_I915GM(dev_priv
) && enabled
) {
2315 struct drm_i915_gem_object
*obj
;
2317 obj
= intel_fb_obj(enabled
->base
.primary
->state
->fb
);
2319 /* self-refresh seems busted with untiled */
2320 if (!i915_gem_object_is_tiled(obj
))
2325 * Overlay gets an aggressive default since video jitter is bad.
2329 /* Play safe and disable self-refresh before adjusting watermarks. */
2330 intel_set_memory_cxsr(dev_priv
, false);
2332 /* Calc sr entries for one plane configs */
2333 if (HAS_FW_BLC(dev_priv
) && enabled
) {
2334 /* self-refresh has much higher latency */
2335 static const int sr_latency_ns
= 6000;
2336 const struct drm_display_mode
*adjusted_mode
=
2337 &enabled
->config
->base
.adjusted_mode
;
2338 const struct drm_framebuffer
*fb
=
2339 enabled
->base
.primary
->state
->fb
;
2340 int clock
= adjusted_mode
->crtc_clock
;
2341 int htotal
= adjusted_mode
->crtc_htotal
;
2342 int hdisplay
= enabled
->config
->pipe_src_w
;
2346 if (IS_I915GM(dev_priv
) || IS_I945GM(dev_priv
))
2349 cpp
= fb
->format
->cpp
[0];
2351 entries
= intel_wm_method2(clock
, htotal
, hdisplay
, cpp
,
2352 sr_latency_ns
/ 100);
2353 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
2354 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
2355 srwm
= wm_info
->fifo_size
- entries
;
2359 if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
))
2360 I915_WRITE(FW_BLC_SELF
,
2361 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
2363 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
2366 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2367 planea_wm
, planeb_wm
, cwm
, srwm
);
2369 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
2370 fwater_hi
= (cwm
& 0x1f);
2372 /* Set request length to 8 cachelines per fetch */
2373 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
2374 fwater_hi
= fwater_hi
| (1 << 8);
2376 I915_WRITE(FW_BLC
, fwater_lo
);
2377 I915_WRITE(FW_BLC2
, fwater_hi
);
2380 intel_set_memory_cxsr(dev_priv
, true);
2383 static void i845_update_wm(struct intel_crtc
*unused_crtc
)
2385 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
2386 struct intel_crtc
*crtc
;
2387 const struct drm_display_mode
*adjusted_mode
;
2391 crtc
= single_enabled_crtc(dev_priv
);
2395 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
2396 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
2398 dev_priv
->display
.get_fifo_size(dev_priv
, 0),
2399 4, pessimal_latency_ns
);
2400 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
2401 fwater_lo
|= (3<<8) | planea_wm
;
2403 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
2405 I915_WRITE(FW_BLC
, fwater_lo
);
2408 /* latency must be in 0.1us units. */
2409 static unsigned int ilk_wm_method1(unsigned int pixel_rate
,
2411 unsigned int latency
)
2415 ret
= intel_wm_method1(pixel_rate
, cpp
, latency
);
2416 ret
= DIV_ROUND_UP(ret
, 64) + 2;
2421 /* latency must be in 0.1us units. */
2422 static unsigned int ilk_wm_method2(unsigned int pixel_rate
,
2423 unsigned int htotal
,
2426 unsigned int latency
)
2430 ret
= intel_wm_method2(pixel_rate
, htotal
,
2431 width
, cpp
, latency
);
2432 ret
= DIV_ROUND_UP(ret
, 64) + 2;
2437 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
2441 * Neither of these should be possible since this function shouldn't be
2442 * called if the CRTC is off or the plane is invisible. But let's be
2443 * extra paranoid to avoid a potential divide-by-zero if we screw up
2444 * elsewhere in the driver.
2448 if (WARN_ON(!horiz_pixels
))
2451 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* cpp
) + 2;
2454 struct ilk_wm_maximums
{
2462 * For both WM_PIPE and WM_LP.
2463 * mem_value must be in 0.1us units.
2465 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state
*cstate
,
2466 const struct intel_plane_state
*pstate
,
2470 uint32_t method1
, method2
;
2473 if (!intel_wm_plane_visible(cstate
, pstate
))
2476 cpp
= pstate
->base
.fb
->format
->cpp
[0];
2478 method1
= ilk_wm_method1(cstate
->pixel_rate
, cpp
, mem_value
);
2483 method2
= ilk_wm_method2(cstate
->pixel_rate
,
2484 cstate
->base
.adjusted_mode
.crtc_htotal
,
2485 drm_rect_width(&pstate
->base
.dst
),
2488 return min(method1
, method2
);
2492 * For both WM_PIPE and WM_LP.
2493 * mem_value must be in 0.1us units.
2495 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state
*cstate
,
2496 const struct intel_plane_state
*pstate
,
2499 uint32_t method1
, method2
;
2502 if (!intel_wm_plane_visible(cstate
, pstate
))
2505 cpp
= pstate
->base
.fb
->format
->cpp
[0];
2507 method1
= ilk_wm_method1(cstate
->pixel_rate
, cpp
, mem_value
);
2508 method2
= ilk_wm_method2(cstate
->pixel_rate
,
2509 cstate
->base
.adjusted_mode
.crtc_htotal
,
2510 drm_rect_width(&pstate
->base
.dst
),
2512 return min(method1
, method2
);
2516 * For both WM_PIPE and WM_LP.
2517 * mem_value must be in 0.1us units.
2519 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state
*cstate
,
2520 const struct intel_plane_state
*pstate
,
2525 if (!intel_wm_plane_visible(cstate
, pstate
))
2528 cpp
= pstate
->base
.fb
->format
->cpp
[0];
2530 return ilk_wm_method2(cstate
->pixel_rate
,
2531 cstate
->base
.adjusted_mode
.crtc_htotal
,
2532 pstate
->base
.crtc_w
, cpp
, mem_value
);
2535 /* Only for WM_LP. */
2536 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state
*cstate
,
2537 const struct intel_plane_state
*pstate
,
2542 if (!intel_wm_plane_visible(cstate
, pstate
))
2545 cpp
= pstate
->base
.fb
->format
->cpp
[0];
2547 return ilk_wm_fbc(pri_val
, drm_rect_width(&pstate
->base
.dst
), cpp
);
2551 ilk_display_fifo_size(const struct drm_i915_private
*dev_priv
)
2553 if (INTEL_GEN(dev_priv
) >= 8)
2555 else if (INTEL_GEN(dev_priv
) >= 7)
2562 ilk_plane_wm_reg_max(const struct drm_i915_private
*dev_priv
,
2563 int level
, bool is_sprite
)
2565 if (INTEL_GEN(dev_priv
) >= 8)
2566 /* BDW primary/sprite plane watermarks */
2567 return level
== 0 ? 255 : 2047;
2568 else if (INTEL_GEN(dev_priv
) >= 7)
2569 /* IVB/HSW primary/sprite plane watermarks */
2570 return level
== 0 ? 127 : 1023;
2571 else if (!is_sprite
)
2572 /* ILK/SNB primary plane watermarks */
2573 return level
== 0 ? 127 : 511;
2575 /* ILK/SNB sprite plane watermarks */
2576 return level
== 0 ? 63 : 255;
2580 ilk_cursor_wm_reg_max(const struct drm_i915_private
*dev_priv
, int level
)
2582 if (INTEL_GEN(dev_priv
) >= 7)
2583 return level
== 0 ? 63 : 255;
2585 return level
== 0 ? 31 : 63;
2588 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private
*dev_priv
)
2590 if (INTEL_GEN(dev_priv
) >= 8)
2596 /* Calculate the maximum primary/sprite plane watermark */
2597 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
2599 const struct intel_wm_config
*config
,
2600 enum intel_ddb_partitioning ddb_partitioning
,
2603 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2604 unsigned int fifo_size
= ilk_display_fifo_size(dev_priv
);
2606 /* if sprites aren't enabled, sprites get nothing */
2607 if (is_sprite
&& !config
->sprites_enabled
)
2610 /* HSW allows LP1+ watermarks even with multiple pipes */
2611 if (level
== 0 || config
->num_pipes_active
> 1) {
2612 fifo_size
/= INTEL_INFO(dev_priv
)->num_pipes
;
2615 * For some reason the non self refresh
2616 * FIFO size is only half of the self
2617 * refresh FIFO size on ILK/SNB.
2619 if (INTEL_GEN(dev_priv
) <= 6)
2623 if (config
->sprites_enabled
) {
2624 /* level 0 is always calculated with 1:1 split */
2625 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
2634 /* clamp to max that the registers can hold */
2635 return min(fifo_size
, ilk_plane_wm_reg_max(dev_priv
, level
, is_sprite
));
2638 /* Calculate the maximum cursor plane watermark */
2639 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
2641 const struct intel_wm_config
*config
)
2643 /* HSW LP1+ watermarks w/ multiple pipes */
2644 if (level
> 0 && config
->num_pipes_active
> 1)
2647 /* otherwise just report max that registers can hold */
2648 return ilk_cursor_wm_reg_max(to_i915(dev
), level
);
2651 static void ilk_compute_wm_maximums(const struct drm_device
*dev
,
2653 const struct intel_wm_config
*config
,
2654 enum intel_ddb_partitioning ddb_partitioning
,
2655 struct ilk_wm_maximums
*max
)
2657 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
2658 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
2659 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
2660 max
->fbc
= ilk_fbc_wm_reg_max(to_i915(dev
));
2663 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private
*dev_priv
,
2665 struct ilk_wm_maximums
*max
)
2667 max
->pri
= ilk_plane_wm_reg_max(dev_priv
, level
, false);
2668 max
->spr
= ilk_plane_wm_reg_max(dev_priv
, level
, true);
2669 max
->cur
= ilk_cursor_wm_reg_max(dev_priv
, level
);
2670 max
->fbc
= ilk_fbc_wm_reg_max(dev_priv
);
2673 static bool ilk_validate_wm_level(int level
,
2674 const struct ilk_wm_maximums
*max
,
2675 struct intel_wm_level
*result
)
2679 /* already determined to be invalid? */
2680 if (!result
->enable
)
2683 result
->enable
= result
->pri_val
<= max
->pri
&&
2684 result
->spr_val
<= max
->spr
&&
2685 result
->cur_val
<= max
->cur
;
2687 ret
= result
->enable
;
2690 * HACK until we can pre-compute everything,
2691 * and thus fail gracefully if LP0 watermarks
2694 if (level
== 0 && !result
->enable
) {
2695 if (result
->pri_val
> max
->pri
)
2696 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2697 level
, result
->pri_val
, max
->pri
);
2698 if (result
->spr_val
> max
->spr
)
2699 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2700 level
, result
->spr_val
, max
->spr
);
2701 if (result
->cur_val
> max
->cur
)
2702 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2703 level
, result
->cur_val
, max
->cur
);
2705 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
2706 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
2707 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
2708 result
->enable
= true;
2714 static void ilk_compute_wm_level(const struct drm_i915_private
*dev_priv
,
2715 const struct intel_crtc
*intel_crtc
,
2717 struct intel_crtc_state
*cstate
,
2718 const struct intel_plane_state
*pristate
,
2719 const struct intel_plane_state
*sprstate
,
2720 const struct intel_plane_state
*curstate
,
2721 struct intel_wm_level
*result
)
2723 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
2724 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
2725 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
2727 /* WM1+ latency values stored in 0.5us units */
2735 result
->pri_val
= ilk_compute_pri_wm(cstate
, pristate
,
2736 pri_latency
, level
);
2737 result
->fbc_val
= ilk_compute_fbc_wm(cstate
, pristate
, result
->pri_val
);
2741 result
->spr_val
= ilk_compute_spr_wm(cstate
, sprstate
, spr_latency
);
2744 result
->cur_val
= ilk_compute_cur_wm(cstate
, curstate
, cur_latency
);
2746 result
->enable
= true;
2750 hsw_compute_linetime_wm(const struct intel_crtc_state
*cstate
)
2752 const struct intel_atomic_state
*intel_state
=
2753 to_intel_atomic_state(cstate
->base
.state
);
2754 const struct drm_display_mode
*adjusted_mode
=
2755 &cstate
->base
.adjusted_mode
;
2756 u32 linetime
, ips_linetime
;
2758 if (!cstate
->base
.active
)
2760 if (WARN_ON(adjusted_mode
->crtc_clock
== 0))
2762 if (WARN_ON(intel_state
->cdclk
.logical
.cdclk
== 0))
2765 /* The WM are computed with base on how long it takes to fill a single
2766 * row at the given clock rate, multiplied by 8.
2768 linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2769 adjusted_mode
->crtc_clock
);
2770 ips_linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2771 intel_state
->cdclk
.logical
.cdclk
);
2773 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2774 PIPE_WM_LINETIME_TIME(linetime
);
2777 static void intel_read_wm_latency(struct drm_i915_private
*dev_priv
,
2780 if (INTEL_GEN(dev_priv
) >= 9) {
2783 int level
, max_level
= ilk_wm_max_level(dev_priv
);
2785 /* read the first set of memory latencies[0:3] */
2786 val
= 0; /* data0 to be programmed to 0 for first set */
2787 mutex_lock(&dev_priv
->pcu_lock
);
2788 ret
= sandybridge_pcode_read(dev_priv
,
2789 GEN9_PCODE_READ_MEM_LATENCY
,
2791 mutex_unlock(&dev_priv
->pcu_lock
);
2794 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2798 wm
[0] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2799 wm
[1] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2800 GEN9_MEM_LATENCY_LEVEL_MASK
;
2801 wm
[2] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2802 GEN9_MEM_LATENCY_LEVEL_MASK
;
2803 wm
[3] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2804 GEN9_MEM_LATENCY_LEVEL_MASK
;
2806 /* read the second set of memory latencies[4:7] */
2807 val
= 1; /* data0 to be programmed to 1 for second set */
2808 mutex_lock(&dev_priv
->pcu_lock
);
2809 ret
= sandybridge_pcode_read(dev_priv
,
2810 GEN9_PCODE_READ_MEM_LATENCY
,
2812 mutex_unlock(&dev_priv
->pcu_lock
);
2814 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2818 wm
[4] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2819 wm
[5] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2820 GEN9_MEM_LATENCY_LEVEL_MASK
;
2821 wm
[6] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2822 GEN9_MEM_LATENCY_LEVEL_MASK
;
2823 wm
[7] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2824 GEN9_MEM_LATENCY_LEVEL_MASK
;
2827 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2828 * need to be disabled. We make sure to sanitize the values out
2829 * of the punit to satisfy this requirement.
2831 for (level
= 1; level
<= max_level
; level
++) {
2832 if (wm
[level
] == 0) {
2833 for (i
= level
+ 1; i
<= max_level
; i
++)
2840 * WaWmMemoryReadLatency:skl+,glk
2842 * punit doesn't take into account the read latency so we need
2843 * to add 2us to the various latency levels we retrieve from the
2844 * punit when level 0 response data us 0us.
2848 for (level
= 1; level
<= max_level
; level
++) {
2855 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2856 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2858 wm
[0] = (sskpd
>> 56) & 0xFF;
2860 wm
[0] = sskpd
& 0xF;
2861 wm
[1] = (sskpd
>> 4) & 0xFF;
2862 wm
[2] = (sskpd
>> 12) & 0xFF;
2863 wm
[3] = (sskpd
>> 20) & 0x1FF;
2864 wm
[4] = (sskpd
>> 32) & 0x1FF;
2865 } else if (INTEL_GEN(dev_priv
) >= 6) {
2866 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
2868 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
2869 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
2870 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
2871 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
2872 } else if (INTEL_GEN(dev_priv
) >= 5) {
2873 uint32_t mltr
= I915_READ(MLTR_ILK
);
2875 /* ILK primary LP0 latency is 700 ns */
2877 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
2878 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
2880 MISSING_CASE(INTEL_DEVID(dev_priv
));
2884 static void intel_fixup_spr_wm_latency(struct drm_i915_private
*dev_priv
,
2887 /* ILK sprite LP0 latency is 1300 ns */
2888 if (IS_GEN5(dev_priv
))
2892 static void intel_fixup_cur_wm_latency(struct drm_i915_private
*dev_priv
,
2895 /* ILK cursor LP0 latency is 1300 ns */
2896 if (IS_GEN5(dev_priv
))
2899 /* WaDoubleCursorLP3Latency:ivb */
2900 if (IS_IVYBRIDGE(dev_priv
))
2904 int ilk_wm_max_level(const struct drm_i915_private
*dev_priv
)
2906 /* how many WM levels are we expecting */
2907 if (INTEL_GEN(dev_priv
) >= 9)
2909 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
2911 else if (INTEL_GEN(dev_priv
) >= 6)
2917 static void intel_print_wm_latency(struct drm_i915_private
*dev_priv
,
2919 const uint16_t wm
[8])
2921 int level
, max_level
= ilk_wm_max_level(dev_priv
);
2923 for (level
= 0; level
<= max_level
; level
++) {
2924 unsigned int latency
= wm
[level
];
2927 DRM_ERROR("%s WM%d latency not provided\n",
2933 * - latencies are in us on gen9.
2934 * - before then, WM1+ latency values are in 0.5us units
2936 if (INTEL_GEN(dev_priv
) >= 9)
2941 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2942 name
, level
, wm
[level
],
2943 latency
/ 10, latency
% 10);
2947 static bool ilk_increase_wm_latency(struct drm_i915_private
*dev_priv
,
2948 uint16_t wm
[5], uint16_t min
)
2950 int level
, max_level
= ilk_wm_max_level(dev_priv
);
2955 wm
[0] = max(wm
[0], min
);
2956 for (level
= 1; level
<= max_level
; level
++)
2957 wm
[level
] = max_t(uint16_t, wm
[level
], DIV_ROUND_UP(min
, 5));
2962 static void snb_wm_latency_quirk(struct drm_i915_private
*dev_priv
)
2967 * The BIOS provided WM memory latency values are often
2968 * inadequate for high resolution displays. Adjust them.
2970 changed
= ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
, 12) |
2971 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
, 12) |
2972 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
, 12);
2977 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2978 intel_print_wm_latency(dev_priv
, "Primary", dev_priv
->wm
.pri_latency
);
2979 intel_print_wm_latency(dev_priv
, "Sprite", dev_priv
->wm
.spr_latency
);
2980 intel_print_wm_latency(dev_priv
, "Cursor", dev_priv
->wm
.cur_latency
);
2983 static void ilk_setup_wm_latency(struct drm_i915_private
*dev_priv
)
2985 intel_read_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
);
2987 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
2988 sizeof(dev_priv
->wm
.pri_latency
));
2989 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
2990 sizeof(dev_priv
->wm
.pri_latency
));
2992 intel_fixup_spr_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
);
2993 intel_fixup_cur_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
);
2995 intel_print_wm_latency(dev_priv
, "Primary", dev_priv
->wm
.pri_latency
);
2996 intel_print_wm_latency(dev_priv
, "Sprite", dev_priv
->wm
.spr_latency
);
2997 intel_print_wm_latency(dev_priv
, "Cursor", dev_priv
->wm
.cur_latency
);
2999 if (IS_GEN6(dev_priv
))
3000 snb_wm_latency_quirk(dev_priv
);
3003 static void skl_setup_wm_latency(struct drm_i915_private
*dev_priv
)
3005 intel_read_wm_latency(dev_priv
, dev_priv
->wm
.skl_latency
);
3006 intel_print_wm_latency(dev_priv
, "Gen9 Plane", dev_priv
->wm
.skl_latency
);
3009 static bool ilk_validate_pipe_wm(struct drm_device
*dev
,
3010 struct intel_pipe_wm
*pipe_wm
)
3012 /* LP0 watermark maximums depend on this pipe alone */
3013 const struct intel_wm_config config
= {
3014 .num_pipes_active
= 1,
3015 .sprites_enabled
= pipe_wm
->sprites_enabled
,
3016 .sprites_scaled
= pipe_wm
->sprites_scaled
,
3018 struct ilk_wm_maximums max
;
3020 /* LP0 watermarks always use 1/2 DDB partitioning */
3021 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
3023 /* At least LP0 must be valid */
3024 if (!ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0])) {
3025 DRM_DEBUG_KMS("LP0 watermark invalid\n");
3032 /* Compute new watermarks for the pipe */
3033 static int ilk_compute_pipe_wm(struct intel_crtc_state
*cstate
)
3035 struct drm_atomic_state
*state
= cstate
->base
.state
;
3036 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
3037 struct intel_pipe_wm
*pipe_wm
;
3038 struct drm_device
*dev
= state
->dev
;
3039 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
3040 struct drm_plane
*plane
;
3041 const struct drm_plane_state
*plane_state
;
3042 const struct intel_plane_state
*pristate
= NULL
;
3043 const struct intel_plane_state
*sprstate
= NULL
;
3044 const struct intel_plane_state
*curstate
= NULL
;
3045 int level
, max_level
= ilk_wm_max_level(dev_priv
), usable_level
;
3046 struct ilk_wm_maximums max
;
3048 pipe_wm
= &cstate
->wm
.ilk
.optimal
;
3050 drm_atomic_crtc_state_for_each_plane_state(plane
, plane_state
, &cstate
->base
) {
3051 const struct intel_plane_state
*ps
= to_intel_plane_state(plane_state
);
3053 if (plane
->type
== DRM_PLANE_TYPE_PRIMARY
)
3055 else if (plane
->type
== DRM_PLANE_TYPE_OVERLAY
)
3057 else if (plane
->type
== DRM_PLANE_TYPE_CURSOR
)
3061 pipe_wm
->pipe_enabled
= cstate
->base
.active
;
3063 pipe_wm
->sprites_enabled
= sprstate
->base
.visible
;
3064 pipe_wm
->sprites_scaled
= sprstate
->base
.visible
&&
3065 (drm_rect_width(&sprstate
->base
.dst
) != drm_rect_width(&sprstate
->base
.src
) >> 16 ||
3066 drm_rect_height(&sprstate
->base
.dst
) != drm_rect_height(&sprstate
->base
.src
) >> 16);
3069 usable_level
= max_level
;
3071 /* ILK/SNB: LP2+ watermarks only w/o sprites */
3072 if (INTEL_GEN(dev_priv
) <= 6 && pipe_wm
->sprites_enabled
)
3075 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
3076 if (pipe_wm
->sprites_scaled
)
3079 memset(&pipe_wm
->wm
, 0, sizeof(pipe_wm
->wm
));
3080 ilk_compute_wm_level(dev_priv
, intel_crtc
, 0, cstate
,
3081 pristate
, sprstate
, curstate
, &pipe_wm
->wm
[0]);
3083 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
3084 pipe_wm
->linetime
= hsw_compute_linetime_wm(cstate
);
3086 if (!ilk_validate_pipe_wm(dev
, pipe_wm
))
3089 ilk_compute_wm_reg_maximums(dev_priv
, 1, &max
);
3091 for (level
= 1; level
<= usable_level
; level
++) {
3092 struct intel_wm_level
*wm
= &pipe_wm
->wm
[level
];
3094 ilk_compute_wm_level(dev_priv
, intel_crtc
, level
, cstate
,
3095 pristate
, sprstate
, curstate
, wm
);
3098 * Disable any watermark level that exceeds the
3099 * register maximums since such watermarks are
3102 if (!ilk_validate_wm_level(level
, &max
, wm
)) {
3103 memset(wm
, 0, sizeof(*wm
));
3112 * Build a set of 'intermediate' watermark values that satisfy both the old
3113 * state and the new state. These can be programmed to the hardware
3116 static int ilk_compute_intermediate_wm(struct drm_device
*dev
,
3117 struct intel_crtc
*intel_crtc
,
3118 struct intel_crtc_state
*newstate
)
3120 struct intel_pipe_wm
*a
= &newstate
->wm
.ilk
.intermediate
;
3121 struct intel_atomic_state
*intel_state
=
3122 to_intel_atomic_state(newstate
->base
.state
);
3123 const struct intel_crtc_state
*oldstate
=
3124 intel_atomic_get_old_crtc_state(intel_state
, intel_crtc
);
3125 const struct intel_pipe_wm
*b
= &oldstate
->wm
.ilk
.optimal
;
3126 int level
, max_level
= ilk_wm_max_level(to_i915(dev
));
3129 * Start with the final, target watermarks, then combine with the
3130 * currently active watermarks to get values that are safe both before
3131 * and after the vblank.
3133 *a
= newstate
->wm
.ilk
.optimal
;
3134 if (!newstate
->base
.active
|| drm_atomic_crtc_needs_modeset(&newstate
->base
))
3137 a
->pipe_enabled
|= b
->pipe_enabled
;
3138 a
->sprites_enabled
|= b
->sprites_enabled
;
3139 a
->sprites_scaled
|= b
->sprites_scaled
;
3141 for (level
= 0; level
<= max_level
; level
++) {
3142 struct intel_wm_level
*a_wm
= &a
->wm
[level
];
3143 const struct intel_wm_level
*b_wm
= &b
->wm
[level
];
3145 a_wm
->enable
&= b_wm
->enable
;
3146 a_wm
->pri_val
= max(a_wm
->pri_val
, b_wm
->pri_val
);
3147 a_wm
->spr_val
= max(a_wm
->spr_val
, b_wm
->spr_val
);
3148 a_wm
->cur_val
= max(a_wm
->cur_val
, b_wm
->cur_val
);
3149 a_wm
->fbc_val
= max(a_wm
->fbc_val
, b_wm
->fbc_val
);
3153 * We need to make sure that these merged watermark values are
3154 * actually a valid configuration themselves. If they're not,
3155 * there's no safe way to transition from the old state to
3156 * the new state, so we need to fail the atomic transaction.
3158 if (!ilk_validate_pipe_wm(dev
, a
))
3162 * If our intermediate WM are identical to the final WM, then we can
3163 * omit the post-vblank programming; only update if it's different.
3165 if (memcmp(a
, &newstate
->wm
.ilk
.optimal
, sizeof(*a
)) != 0)
3166 newstate
->wm
.need_postvbl_update
= true;
3172 * Merge the watermarks from all active pipes for a specific level.
3174 static void ilk_merge_wm_level(struct drm_device
*dev
,
3176 struct intel_wm_level
*ret_wm
)
3178 const struct intel_crtc
*intel_crtc
;
3180 ret_wm
->enable
= true;
3182 for_each_intel_crtc(dev
, intel_crtc
) {
3183 const struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
.ilk
;
3184 const struct intel_wm_level
*wm
= &active
->wm
[level
];
3186 if (!active
->pipe_enabled
)
3190 * The watermark values may have been used in the past,
3191 * so we must maintain them in the registers for some
3192 * time even if the level is now disabled.
3195 ret_wm
->enable
= false;
3197 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
3198 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
3199 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
3200 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
3205 * Merge all low power watermarks for all active pipes.
3207 static void ilk_wm_merge(struct drm_device
*dev
,
3208 const struct intel_wm_config
*config
,
3209 const struct ilk_wm_maximums
*max
,
3210 struct intel_pipe_wm
*merged
)
3212 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3213 int level
, max_level
= ilk_wm_max_level(dev_priv
);
3214 int last_enabled_level
= max_level
;
3216 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
3217 if ((INTEL_GEN(dev_priv
) <= 6 || IS_IVYBRIDGE(dev_priv
)) &&
3218 config
->num_pipes_active
> 1)
3219 last_enabled_level
= 0;
3221 /* ILK: FBC WM must be disabled always */
3222 merged
->fbc_wm_enabled
= INTEL_GEN(dev_priv
) >= 6;
3224 /* merge each WM1+ level */
3225 for (level
= 1; level
<= max_level
; level
++) {
3226 struct intel_wm_level
*wm
= &merged
->wm
[level
];
3228 ilk_merge_wm_level(dev
, level
, wm
);
3230 if (level
> last_enabled_level
)
3232 else if (!ilk_validate_wm_level(level
, max
, wm
))
3233 /* make sure all following levels get disabled */
3234 last_enabled_level
= level
- 1;
3237 * The spec says it is preferred to disable
3238 * FBC WMs instead of disabling a WM level.
3240 if (wm
->fbc_val
> max
->fbc
) {
3242 merged
->fbc_wm_enabled
= false;
3247 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
3249 * FIXME this is racy. FBC might get enabled later.
3250 * What we should check here is whether FBC can be
3251 * enabled sometime later.
3253 if (IS_GEN5(dev_priv
) && !merged
->fbc_wm_enabled
&&
3254 intel_fbc_is_active(dev_priv
)) {
3255 for (level
= 2; level
<= max_level
; level
++) {
3256 struct intel_wm_level
*wm
= &merged
->wm
[level
];
3263 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
3265 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
3266 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
3269 /* The value we need to program into the WM_LPx latency field */
3270 static unsigned int ilk_wm_lp_latency(struct drm_device
*dev
, int level
)
3272 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3274 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
3277 return dev_priv
->wm
.pri_latency
[level
];
3280 static void ilk_compute_wm_results(struct drm_device
*dev
,
3281 const struct intel_pipe_wm
*merged
,
3282 enum intel_ddb_partitioning partitioning
,
3283 struct ilk_wm_values
*results
)
3285 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3286 struct intel_crtc
*intel_crtc
;
3289 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
3290 results
->partitioning
= partitioning
;
3292 /* LP1+ register values */
3293 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
3294 const struct intel_wm_level
*r
;
3296 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
3298 r
= &merged
->wm
[level
];
3301 * Maintain the watermark values even if the level is
3302 * disabled. Doing otherwise could cause underruns.
3304 results
->wm_lp
[wm_lp
- 1] =
3305 (ilk_wm_lp_latency(dev
, level
) << WM1_LP_LATENCY_SHIFT
) |
3306 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
3310 results
->wm_lp
[wm_lp
- 1] |= WM1_LP_SR_EN
;
3312 if (INTEL_GEN(dev_priv
) >= 8)
3313 results
->wm_lp
[wm_lp
- 1] |=
3314 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
3316 results
->wm_lp
[wm_lp
- 1] |=
3317 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
3320 * Always set WM1S_LP_EN when spr_val != 0, even if the
3321 * level is disabled. Doing otherwise could cause underruns.
3323 if (INTEL_GEN(dev_priv
) <= 6 && r
->spr_val
) {
3324 WARN_ON(wm_lp
!= 1);
3325 results
->wm_lp_spr
[wm_lp
- 1] = WM1S_LP_EN
| r
->spr_val
;
3327 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
3330 /* LP0 register values */
3331 for_each_intel_crtc(dev
, intel_crtc
) {
3332 enum pipe pipe
= intel_crtc
->pipe
;
3333 const struct intel_wm_level
*r
=
3334 &intel_crtc
->wm
.active
.ilk
.wm
[0];
3336 if (WARN_ON(!r
->enable
))
3339 results
->wm_linetime
[pipe
] = intel_crtc
->wm
.active
.ilk
.linetime
;
3341 results
->wm_pipe
[pipe
] =
3342 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
3343 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
3348 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
3349 * case both are at the same level. Prefer r1 in case they're the same. */
3350 static struct intel_pipe_wm
*ilk_find_best_result(struct drm_device
*dev
,
3351 struct intel_pipe_wm
*r1
,
3352 struct intel_pipe_wm
*r2
)
3354 int level
, max_level
= ilk_wm_max_level(to_i915(dev
));
3355 int level1
= 0, level2
= 0;
3357 for (level
= 1; level
<= max_level
; level
++) {
3358 if (r1
->wm
[level
].enable
)
3360 if (r2
->wm
[level
].enable
)
3364 if (level1
== level2
) {
3365 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
3369 } else if (level1
> level2
) {
3376 /* dirty bits used to track which watermarks need changes */
3377 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
3378 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
3379 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
3380 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
3381 #define WM_DIRTY_FBC (1 << 24)
3382 #define WM_DIRTY_DDB (1 << 25)
3384 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private
*dev_priv
,
3385 const struct ilk_wm_values
*old
,
3386 const struct ilk_wm_values
*new)
3388 unsigned int dirty
= 0;
3392 for_each_pipe(dev_priv
, pipe
) {
3393 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
3394 dirty
|= WM_DIRTY_LINETIME(pipe
);
3395 /* Must disable LP1+ watermarks too */
3396 dirty
|= WM_DIRTY_LP_ALL
;
3399 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
3400 dirty
|= WM_DIRTY_PIPE(pipe
);
3401 /* Must disable LP1+ watermarks too */
3402 dirty
|= WM_DIRTY_LP_ALL
;
3406 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
3407 dirty
|= WM_DIRTY_FBC
;
3408 /* Must disable LP1+ watermarks too */
3409 dirty
|= WM_DIRTY_LP_ALL
;
3412 if (old
->partitioning
!= new->partitioning
) {
3413 dirty
|= WM_DIRTY_DDB
;
3414 /* Must disable LP1+ watermarks too */
3415 dirty
|= WM_DIRTY_LP_ALL
;
3418 /* LP1+ watermarks already deemed dirty, no need to continue */
3419 if (dirty
& WM_DIRTY_LP_ALL
)
3422 /* Find the lowest numbered LP1+ watermark in need of an update... */
3423 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
3424 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
3425 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
3429 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
3430 for (; wm_lp
<= 3; wm_lp
++)
3431 dirty
|= WM_DIRTY_LP(wm_lp
);
3436 static bool _ilk_disable_lp_wm(struct drm_i915_private
*dev_priv
,
3439 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
3440 bool changed
= false;
3442 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] & WM1_LP_SR_EN
) {
3443 previous
->wm_lp
[2] &= ~WM1_LP_SR_EN
;
3444 I915_WRITE(WM3_LP_ILK
, previous
->wm_lp
[2]);
3447 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] & WM1_LP_SR_EN
) {
3448 previous
->wm_lp
[1] &= ~WM1_LP_SR_EN
;
3449 I915_WRITE(WM2_LP_ILK
, previous
->wm_lp
[1]);
3452 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] & WM1_LP_SR_EN
) {
3453 previous
->wm_lp
[0] &= ~WM1_LP_SR_EN
;
3454 I915_WRITE(WM1_LP_ILK
, previous
->wm_lp
[0]);
3459 * Don't touch WM1S_LP_EN here.
3460 * Doing so could cause underruns.
3467 * The spec says we shouldn't write when we don't need, because every write
3468 * causes WMs to be re-evaluated, expending some power.
3470 static void ilk_write_wm_values(struct drm_i915_private
*dev_priv
,
3471 struct ilk_wm_values
*results
)
3473 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
3477 dirty
= ilk_compute_wm_dirty(dev_priv
, previous
, results
);
3481 _ilk_disable_lp_wm(dev_priv
, dirty
);
3483 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
3484 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
3485 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
3486 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
3487 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
3488 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
3490 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
3491 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
3492 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
3493 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
3494 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
3495 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
3497 if (dirty
& WM_DIRTY_DDB
) {
3498 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3499 val
= I915_READ(WM_MISC
);
3500 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
3501 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
3503 val
|= WM_MISC_DATA_PARTITION_5_6
;
3504 I915_WRITE(WM_MISC
, val
);
3506 val
= I915_READ(DISP_ARB_CTL2
);
3507 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
3508 val
&= ~DISP_DATA_PARTITION_5_6
;
3510 val
|= DISP_DATA_PARTITION_5_6
;
3511 I915_WRITE(DISP_ARB_CTL2
, val
);
3515 if (dirty
& WM_DIRTY_FBC
) {
3516 val
= I915_READ(DISP_ARB_CTL
);
3517 if (results
->enable_fbc_wm
)
3518 val
&= ~DISP_FBC_WM_DIS
;
3520 val
|= DISP_FBC_WM_DIS
;
3521 I915_WRITE(DISP_ARB_CTL
, val
);
3524 if (dirty
& WM_DIRTY_LP(1) &&
3525 previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
3526 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
3528 if (INTEL_GEN(dev_priv
) >= 7) {
3529 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
3530 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
3531 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
3532 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
3535 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != results
->wm_lp
[0])
3536 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
3537 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != results
->wm_lp
[1])
3538 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
3539 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != results
->wm_lp
[2])
3540 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
3542 dev_priv
->wm
.hw
= *results
;
3545 bool ilk_disable_lp_wm(struct drm_device
*dev
)
3547 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3549 return _ilk_disable_lp_wm(dev_priv
, WM_DIRTY_LP_ALL
);
3553 * FIXME: We still don't have the proper code detect if we need to apply the WA,
3554 * so assume we'll always need it in order to avoid underruns.
3556 static bool skl_needs_memory_bw_wa(struct intel_atomic_state
*state
)
3558 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
3560 if (IS_GEN9_BC(dev_priv
) || IS_BROXTON(dev_priv
))
3567 intel_has_sagv(struct drm_i915_private
*dev_priv
)
3569 if (IS_KABYLAKE(dev_priv
) || IS_COFFEELAKE(dev_priv
) ||
3570 IS_CANNONLAKE(dev_priv
))
3573 if (IS_SKYLAKE(dev_priv
) &&
3574 dev_priv
->sagv_status
!= I915_SAGV_NOT_CONTROLLED
)
3581 * SAGV dynamically adjusts the system agent voltage and clock frequencies
3582 * depending on power and performance requirements. The display engine access
3583 * to system memory is blocked during the adjustment time. Because of the
3584 * blocking time, having this enabled can cause full system hangs and/or pipe
3585 * underruns if we don't meet all of the following requirements:
3587 * - <= 1 pipe enabled
3588 * - All planes can enable watermarks for latencies >= SAGV engine block time
3589 * - We're not using an interlaced display configuration
3592 intel_enable_sagv(struct drm_i915_private
*dev_priv
)
3596 if (!intel_has_sagv(dev_priv
))
3599 if (dev_priv
->sagv_status
== I915_SAGV_ENABLED
)
3602 DRM_DEBUG_KMS("Enabling the SAGV\n");
3603 mutex_lock(&dev_priv
->pcu_lock
);
3605 ret
= sandybridge_pcode_write(dev_priv
, GEN9_PCODE_SAGV_CONTROL
,
3608 /* We don't need to wait for the SAGV when enabling */
3609 mutex_unlock(&dev_priv
->pcu_lock
);
3612 * Some skl systems, pre-release machines in particular,
3613 * don't actually have an SAGV.
3615 if (IS_SKYLAKE(dev_priv
) && ret
== -ENXIO
) {
3616 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3617 dev_priv
->sagv_status
= I915_SAGV_NOT_CONTROLLED
;
3619 } else if (ret
< 0) {
3620 DRM_ERROR("Failed to enable the SAGV\n");
3624 dev_priv
->sagv_status
= I915_SAGV_ENABLED
;
3629 intel_disable_sagv(struct drm_i915_private
*dev_priv
)
3633 if (!intel_has_sagv(dev_priv
))
3636 if (dev_priv
->sagv_status
== I915_SAGV_DISABLED
)
3639 DRM_DEBUG_KMS("Disabling the SAGV\n");
3640 mutex_lock(&dev_priv
->pcu_lock
);
3642 /* bspec says to keep retrying for at least 1 ms */
3643 ret
= skl_pcode_request(dev_priv
, GEN9_PCODE_SAGV_CONTROL
,
3645 GEN9_SAGV_IS_DISABLED
, GEN9_SAGV_IS_DISABLED
,
3647 mutex_unlock(&dev_priv
->pcu_lock
);
3650 * Some skl systems, pre-release machines in particular,
3651 * don't actually have an SAGV.
3653 if (IS_SKYLAKE(dev_priv
) && ret
== -ENXIO
) {
3654 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3655 dev_priv
->sagv_status
= I915_SAGV_NOT_CONTROLLED
;
3657 } else if (ret
< 0) {
3658 DRM_ERROR("Failed to disable the SAGV (%d)\n", ret
);
3662 dev_priv
->sagv_status
= I915_SAGV_DISABLED
;
3666 bool intel_can_enable_sagv(struct drm_atomic_state
*state
)
3668 struct drm_device
*dev
= state
->dev
;
3669 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3670 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
3671 struct intel_crtc
*crtc
;
3672 struct intel_plane
*plane
;
3673 struct intel_crtc_state
*cstate
;
3676 int sagv_block_time_us
= IS_GEN9(dev_priv
) ? 30 : 20;
3678 if (!intel_has_sagv(dev_priv
))
3682 * SKL+ workaround: bspec recommends we disable the SAGV when we have
3683 * more then one pipe enabled
3685 * If there are no active CRTCs, no additional checks need be performed
3687 if (hweight32(intel_state
->active_crtcs
) == 0)
3689 else if (hweight32(intel_state
->active_crtcs
) > 1)
3692 /* Since we're now guaranteed to only have one active CRTC... */
3693 pipe
= ffs(intel_state
->active_crtcs
) - 1;
3694 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
3695 cstate
= to_intel_crtc_state(crtc
->base
.state
);
3697 if (crtc
->base
.state
->adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
3700 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
3701 struct skl_plane_wm
*wm
=
3702 &cstate
->wm
.skl
.optimal
.planes
[plane
->id
];
3704 /* Skip this plane if it's not enabled */
3705 if (!wm
->wm
[0].plane_en
)
3708 /* Find the highest enabled wm level for this plane */
3709 for (level
= ilk_wm_max_level(dev_priv
);
3710 !wm
->wm
[level
].plane_en
; --level
)
3713 latency
= dev_priv
->wm
.skl_latency
[level
];
3715 if (skl_needs_memory_bw_wa(intel_state
) &&
3716 plane
->base
.state
->fb
->modifier
==
3717 I915_FORMAT_MOD_X_TILED
)
3721 * If any of the planes on this pipe don't enable wm levels that
3722 * incur memory latencies higher than sagv_block_time_us we
3723 * can't enable the SAGV.
3725 if (latency
< sagv_block_time_us
)
3733 skl_ddb_get_pipe_allocation_limits(struct drm_device
*dev
,
3734 const struct intel_crtc_state
*cstate
,
3735 struct skl_ddb_entry
*alloc
, /* out */
3736 int *num_active
/* out */)
3738 struct drm_atomic_state
*state
= cstate
->base
.state
;
3739 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
3740 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3741 struct drm_crtc
*for_crtc
= cstate
->base
.crtc
;
3742 unsigned int pipe_size
, ddb_size
;
3743 int nth_active_pipe
;
3745 if (WARN_ON(!state
) || !cstate
->base
.active
) {
3748 *num_active
= hweight32(dev_priv
->active_crtcs
);
3752 if (intel_state
->active_pipe_changes
)
3753 *num_active
= hweight32(intel_state
->active_crtcs
);
3755 *num_active
= hweight32(dev_priv
->active_crtcs
);
3757 ddb_size
= INTEL_INFO(dev_priv
)->ddb_size
;
3758 WARN_ON(ddb_size
== 0);
3760 ddb_size
-= 4; /* 4 blocks for bypass path allocation */
3763 * If the state doesn't change the active CRTC's, then there's
3764 * no need to recalculate; the existing pipe allocation limits
3765 * should remain unchanged. Note that we're safe from racing
3766 * commits since any racing commit that changes the active CRTC
3767 * list would need to grab _all_ crtc locks, including the one
3768 * we currently hold.
3770 if (!intel_state
->active_pipe_changes
) {
3772 * alloc may be cleared by clear_intel_crtc_state,
3773 * copy from old state to be sure
3775 *alloc
= to_intel_crtc_state(for_crtc
->state
)->wm
.skl
.ddb
;
3779 nth_active_pipe
= hweight32(intel_state
->active_crtcs
&
3780 (drm_crtc_mask(for_crtc
) - 1));
3781 pipe_size
= ddb_size
/ hweight32(intel_state
->active_crtcs
);
3782 alloc
->start
= nth_active_pipe
* ddb_size
/ *num_active
;
3783 alloc
->end
= alloc
->start
+ pipe_size
;
3786 static unsigned int skl_cursor_allocation(int num_active
)
3788 if (num_active
== 1)
3794 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry
*entry
, u32 reg
)
3796 entry
->start
= reg
& 0x3ff;
3797 entry
->end
= (reg
>> 16) & 0x3ff;
3802 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
3803 struct skl_ddb_allocation
*ddb
/* out */)
3805 struct intel_crtc
*crtc
;
3807 memset(ddb
, 0, sizeof(*ddb
));
3809 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
3810 enum intel_display_power_domain power_domain
;
3811 enum plane_id plane_id
;
3812 enum pipe pipe
= crtc
->pipe
;
3814 power_domain
= POWER_DOMAIN_PIPE(pipe
);
3815 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
3818 for_each_plane_id_on_crtc(crtc
, plane_id
) {
3821 if (plane_id
!= PLANE_CURSOR
)
3822 val
= I915_READ(PLANE_BUF_CFG(pipe
, plane_id
));
3824 val
= I915_READ(CUR_BUF_CFG(pipe
));
3826 skl_ddb_entry_init_from_hw(&ddb
->plane
[pipe
][plane_id
], val
);
3829 intel_display_power_put(dev_priv
, power_domain
);
3834 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3835 * The bspec defines downscale amount as:
3838 * Horizontal down scale amount = maximum[1, Horizontal source size /
3839 * Horizontal destination size]
3840 * Vertical down scale amount = maximum[1, Vertical source size /
3841 * Vertical destination size]
3842 * Total down scale amount = Horizontal down scale amount *
3843 * Vertical down scale amount
3846 * Return value is provided in 16.16 fixed point form to retain fractional part.
3847 * Caller should take care of dividing & rounding off the value.
3849 static uint_fixed_16_16_t
3850 skl_plane_downscale_amount(const struct intel_crtc_state
*cstate
,
3851 const struct intel_plane_state
*pstate
)
3853 struct intel_plane
*plane
= to_intel_plane(pstate
->base
.plane
);
3854 uint32_t src_w
, src_h
, dst_w
, dst_h
;
3855 uint_fixed_16_16_t fp_w_ratio
, fp_h_ratio
;
3856 uint_fixed_16_16_t downscale_h
, downscale_w
;
3858 if (WARN_ON(!intel_wm_plane_visible(cstate
, pstate
)))
3859 return u32_to_fixed16(0);
3861 /* n.b., src is 16.16 fixed point, dst is whole integer */
3862 if (plane
->id
== PLANE_CURSOR
) {
3864 * Cursors only support 0/180 degree rotation,
3865 * hence no need to account for rotation here.
3867 src_w
= pstate
->base
.src_w
>> 16;
3868 src_h
= pstate
->base
.src_h
>> 16;
3869 dst_w
= pstate
->base
.crtc_w
;
3870 dst_h
= pstate
->base
.crtc_h
;
3873 * Src coordinates are already rotated by 270 degrees for
3874 * the 90/270 degree plane rotation cases (to match the
3875 * GTT mapping), hence no need to account for rotation here.
3877 src_w
= drm_rect_width(&pstate
->base
.src
) >> 16;
3878 src_h
= drm_rect_height(&pstate
->base
.src
) >> 16;
3879 dst_w
= drm_rect_width(&pstate
->base
.dst
);
3880 dst_h
= drm_rect_height(&pstate
->base
.dst
);
3883 fp_w_ratio
= div_fixed16(src_w
, dst_w
);
3884 fp_h_ratio
= div_fixed16(src_h
, dst_h
);
3885 downscale_w
= max_fixed16(fp_w_ratio
, u32_to_fixed16(1));
3886 downscale_h
= max_fixed16(fp_h_ratio
, u32_to_fixed16(1));
3888 return mul_fixed16(downscale_w
, downscale_h
);
3891 static uint_fixed_16_16_t
3892 skl_pipe_downscale_amount(const struct intel_crtc_state
*crtc_state
)
3894 uint_fixed_16_16_t pipe_downscale
= u32_to_fixed16(1);
3896 if (!crtc_state
->base
.enable
)
3897 return pipe_downscale
;
3899 if (crtc_state
->pch_pfit
.enabled
) {
3900 uint32_t src_w
, src_h
, dst_w
, dst_h
;
3901 uint32_t pfit_size
= crtc_state
->pch_pfit
.size
;
3902 uint_fixed_16_16_t fp_w_ratio
, fp_h_ratio
;
3903 uint_fixed_16_16_t downscale_h
, downscale_w
;
3905 src_w
= crtc_state
->pipe_src_w
;
3906 src_h
= crtc_state
->pipe_src_h
;
3907 dst_w
= pfit_size
>> 16;
3908 dst_h
= pfit_size
& 0xffff;
3910 if (!dst_w
|| !dst_h
)
3911 return pipe_downscale
;
3913 fp_w_ratio
= div_fixed16(src_w
, dst_w
);
3914 fp_h_ratio
= div_fixed16(src_h
, dst_h
);
3915 downscale_w
= max_fixed16(fp_w_ratio
, u32_to_fixed16(1));
3916 downscale_h
= max_fixed16(fp_h_ratio
, u32_to_fixed16(1));
3918 pipe_downscale
= mul_fixed16(downscale_w
, downscale_h
);
3921 return pipe_downscale
;
3924 int skl_check_pipe_max_pixel_rate(struct intel_crtc
*intel_crtc
,
3925 struct intel_crtc_state
*cstate
)
3927 struct drm_crtc_state
*crtc_state
= &cstate
->base
;
3928 struct drm_atomic_state
*state
= crtc_state
->state
;
3929 struct drm_plane
*plane
;
3930 const struct drm_plane_state
*pstate
;
3931 struct intel_plane_state
*intel_pstate
;
3932 int crtc_clock
, dotclk
;
3933 uint32_t pipe_max_pixel_rate
;
3934 uint_fixed_16_16_t pipe_downscale
;
3935 uint_fixed_16_16_t max_downscale
= u32_to_fixed16(1);
3937 if (!cstate
->base
.enable
)
3940 drm_atomic_crtc_state_for_each_plane_state(plane
, pstate
, crtc_state
) {
3941 uint_fixed_16_16_t plane_downscale
;
3942 uint_fixed_16_16_t fp_9_div_8
= div_fixed16(9, 8);
3945 if (!intel_wm_plane_visible(cstate
,
3946 to_intel_plane_state(pstate
)))
3949 if (WARN_ON(!pstate
->fb
))
3952 intel_pstate
= to_intel_plane_state(pstate
);
3953 plane_downscale
= skl_plane_downscale_amount(cstate
,
3955 bpp
= pstate
->fb
->format
->cpp
[0] * 8;
3957 plane_downscale
= mul_fixed16(plane_downscale
,
3960 max_downscale
= max_fixed16(plane_downscale
, max_downscale
);
3962 pipe_downscale
= skl_pipe_downscale_amount(cstate
);
3964 pipe_downscale
= mul_fixed16(pipe_downscale
, max_downscale
);
3966 crtc_clock
= crtc_state
->adjusted_mode
.crtc_clock
;
3967 dotclk
= to_intel_atomic_state(state
)->cdclk
.logical
.cdclk
;
3969 if (IS_GEMINILAKE(to_i915(intel_crtc
->base
.dev
)))
3972 pipe_max_pixel_rate
= div_round_up_u32_fixed16(dotclk
, pipe_downscale
);
3974 if (pipe_max_pixel_rate
< crtc_clock
) {
3975 DRM_DEBUG_KMS("Max supported pixel clock with scaling exceeded\n");
3983 skl_plane_relative_data_rate(const struct intel_crtc_state
*cstate
,
3984 const struct drm_plane_state
*pstate
,
3987 struct intel_plane
*plane
= to_intel_plane(pstate
->plane
);
3988 struct intel_plane_state
*intel_pstate
= to_intel_plane_state(pstate
);
3990 uint32_t width
= 0, height
= 0;
3991 struct drm_framebuffer
*fb
;
3993 uint_fixed_16_16_t down_scale_amount
;
3995 if (!intel_pstate
->base
.visible
)
3999 format
= fb
->format
->format
;
4001 if (plane
->id
== PLANE_CURSOR
)
4003 if (y
&& format
!= DRM_FORMAT_NV12
)
4007 * Src coordinates are already rotated by 270 degrees for
4008 * the 90/270 degree plane rotation cases (to match the
4009 * GTT mapping), hence no need to account for rotation here.
4011 width
= drm_rect_width(&intel_pstate
->base
.src
) >> 16;
4012 height
= drm_rect_height(&intel_pstate
->base
.src
) >> 16;
4014 /* for planar format */
4015 if (format
== DRM_FORMAT_NV12
) {
4016 if (y
) /* y-plane data rate */
4017 data_rate
= width
* height
*
4019 else /* uv-plane data rate */
4020 data_rate
= (width
/ 2) * (height
/ 2) *
4023 /* for packed formats */
4024 data_rate
= width
* height
* fb
->format
->cpp
[0];
4027 down_scale_amount
= skl_plane_downscale_amount(cstate
, intel_pstate
);
4029 return mul_round_up_u32_fixed16(data_rate
, down_scale_amount
);
4033 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
4034 * a 8192x4096@32bpp framebuffer:
4035 * 3 * 4096 * 8192 * 4 < 2^32
4038 skl_get_total_relative_data_rate(struct intel_crtc_state
*intel_cstate
,
4039 unsigned *plane_data_rate
,
4040 unsigned *plane_y_data_rate
)
4042 struct drm_crtc_state
*cstate
= &intel_cstate
->base
;
4043 struct drm_atomic_state
*state
= cstate
->state
;
4044 struct drm_plane
*plane
;
4045 const struct drm_plane_state
*pstate
;
4046 unsigned int total_data_rate
= 0;
4048 if (WARN_ON(!state
))
4051 /* Calculate and cache data rate for each plane */
4052 drm_atomic_crtc_state_for_each_plane_state(plane
, pstate
, cstate
) {
4053 enum plane_id plane_id
= to_intel_plane(plane
)->id
;
4057 rate
= skl_plane_relative_data_rate(intel_cstate
,
4059 plane_data_rate
[plane_id
] = rate
;
4061 total_data_rate
+= rate
;
4064 rate
= skl_plane_relative_data_rate(intel_cstate
,
4066 plane_y_data_rate
[plane_id
] = rate
;
4068 total_data_rate
+= rate
;
4071 return total_data_rate
;
4075 skl_ddb_min_alloc(const struct drm_plane_state
*pstate
,
4078 struct drm_framebuffer
*fb
= pstate
->fb
;
4079 struct intel_plane_state
*intel_pstate
= to_intel_plane_state(pstate
);
4080 uint32_t src_w
, src_h
;
4081 uint32_t min_scanlines
= 8;
4087 /* For packed formats, no y-plane, return 0 */
4088 if (y
&& fb
->format
->format
!= DRM_FORMAT_NV12
)
4091 /* For Non Y-tile return 8-blocks */
4092 if (fb
->modifier
!= I915_FORMAT_MOD_Y_TILED
&&
4093 fb
->modifier
!= I915_FORMAT_MOD_Yf_TILED
&&
4094 fb
->modifier
!= I915_FORMAT_MOD_Y_TILED_CCS
&&
4095 fb
->modifier
!= I915_FORMAT_MOD_Yf_TILED_CCS
)
4099 * Src coordinates are already rotated by 270 degrees for
4100 * the 90/270 degree plane rotation cases (to match the
4101 * GTT mapping), hence no need to account for rotation here.
4103 src_w
= drm_rect_width(&intel_pstate
->base
.src
) >> 16;
4104 src_h
= drm_rect_height(&intel_pstate
->base
.src
) >> 16;
4106 /* Halve UV plane width and height for NV12 */
4107 if (fb
->format
->format
== DRM_FORMAT_NV12
&& !y
) {
4112 if (fb
->format
->format
== DRM_FORMAT_NV12
&& !y
)
4113 plane_bpp
= fb
->format
->cpp
[1];
4115 plane_bpp
= fb
->format
->cpp
[0];
4117 if (drm_rotation_90_or_270(pstate
->rotation
)) {
4118 switch (plane_bpp
) {
4132 WARN(1, "Unsupported pixel depth %u for rotation",
4138 return DIV_ROUND_UP((4 * src_w
* plane_bpp
), 512) * min_scanlines
/4 + 3;
4142 skl_ddb_calc_min(const struct intel_crtc_state
*cstate
, int num_active
,
4143 uint16_t *minimum
, uint16_t *y_minimum
)
4145 const struct drm_plane_state
*pstate
;
4146 struct drm_plane
*plane
;
4148 drm_atomic_crtc_state_for_each_plane_state(plane
, pstate
, &cstate
->base
) {
4149 enum plane_id plane_id
= to_intel_plane(plane
)->id
;
4151 if (plane_id
== PLANE_CURSOR
)
4154 if (!pstate
->visible
)
4157 minimum
[plane_id
] = skl_ddb_min_alloc(pstate
, 0);
4158 y_minimum
[plane_id
] = skl_ddb_min_alloc(pstate
, 1);
4161 minimum
[PLANE_CURSOR
] = skl_cursor_allocation(num_active
);
4165 skl_allocate_pipe_ddb(struct intel_crtc_state
*cstate
,
4166 struct skl_ddb_allocation
*ddb
/* out */)
4168 struct drm_atomic_state
*state
= cstate
->base
.state
;
4169 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
4170 struct drm_device
*dev
= crtc
->dev
;
4171 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4172 enum pipe pipe
= intel_crtc
->pipe
;
4173 struct skl_ddb_entry
*alloc
= &cstate
->wm
.skl
.ddb
;
4174 uint16_t alloc_size
, start
;
4175 uint16_t minimum
[I915_MAX_PLANES
] = {};
4176 uint16_t y_minimum
[I915_MAX_PLANES
] = {};
4177 unsigned int total_data_rate
;
4178 enum plane_id plane_id
;
4180 unsigned plane_data_rate
[I915_MAX_PLANES
] = {};
4181 unsigned plane_y_data_rate
[I915_MAX_PLANES
] = {};
4182 uint16_t total_min_blocks
= 0;
4184 /* Clear the partitioning for disabled planes. */
4185 memset(ddb
->plane
[pipe
], 0, sizeof(ddb
->plane
[pipe
]));
4186 memset(ddb
->y_plane
[pipe
], 0, sizeof(ddb
->y_plane
[pipe
]));
4188 if (WARN_ON(!state
))
4191 if (!cstate
->base
.active
) {
4192 alloc
->start
= alloc
->end
= 0;
4196 skl_ddb_get_pipe_allocation_limits(dev
, cstate
, alloc
, &num_active
);
4197 alloc_size
= skl_ddb_entry_size(alloc
);
4198 if (alloc_size
== 0)
4201 skl_ddb_calc_min(cstate
, num_active
, minimum
, y_minimum
);
4204 * 1. Allocate the mininum required blocks for each active plane
4205 * and allocate the cursor, it doesn't require extra allocation
4206 * proportional to the data rate.
4209 for_each_plane_id_on_crtc(intel_crtc
, plane_id
) {
4210 total_min_blocks
+= minimum
[plane_id
];
4211 total_min_blocks
+= y_minimum
[plane_id
];
4214 if (total_min_blocks
> alloc_size
) {
4215 DRM_DEBUG_KMS("Requested display configuration exceeds system DDB limitations");
4216 DRM_DEBUG_KMS("minimum required %d/%d\n", total_min_blocks
,
4221 alloc_size
-= total_min_blocks
;
4222 ddb
->plane
[pipe
][PLANE_CURSOR
].start
= alloc
->end
- minimum
[PLANE_CURSOR
];
4223 ddb
->plane
[pipe
][PLANE_CURSOR
].end
= alloc
->end
;
4226 * 2. Distribute the remaining space in proportion to the amount of
4227 * data each plane needs to fetch from memory.
4229 * FIXME: we may not allocate every single block here.
4231 total_data_rate
= skl_get_total_relative_data_rate(cstate
,
4234 if (total_data_rate
== 0)
4237 start
= alloc
->start
;
4238 for_each_plane_id_on_crtc(intel_crtc
, plane_id
) {
4239 unsigned int data_rate
, y_data_rate
;
4240 uint16_t plane_blocks
, y_plane_blocks
= 0;
4242 if (plane_id
== PLANE_CURSOR
)
4245 data_rate
= plane_data_rate
[plane_id
];
4248 * allocation for (packed formats) or (uv-plane part of planar format):
4249 * promote the expression to 64 bits to avoid overflowing, the
4250 * result is < available as data_rate / total_data_rate < 1
4252 plane_blocks
= minimum
[plane_id
];
4253 plane_blocks
+= div_u64((uint64_t)alloc_size
* data_rate
,
4256 /* Leave disabled planes at (0,0) */
4258 ddb
->plane
[pipe
][plane_id
].start
= start
;
4259 ddb
->plane
[pipe
][plane_id
].end
= start
+ plane_blocks
;
4262 start
+= plane_blocks
;
4265 * allocation for y_plane part of planar format:
4267 y_data_rate
= plane_y_data_rate
[plane_id
];
4269 y_plane_blocks
= y_minimum
[plane_id
];
4270 y_plane_blocks
+= div_u64((uint64_t)alloc_size
* y_data_rate
,
4274 ddb
->y_plane
[pipe
][plane_id
].start
= start
;
4275 ddb
->y_plane
[pipe
][plane_id
].end
= start
+ y_plane_blocks
;
4278 start
+= y_plane_blocks
;
4285 * The max latency should be 257 (max the punit can code is 255 and we add 2us
4286 * for the read latency) and cpp should always be <= 8, so that
4287 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
4288 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
4290 static uint_fixed_16_16_t
4291 skl_wm_method1(const struct drm_i915_private
*dev_priv
, uint32_t pixel_rate
,
4292 uint8_t cpp
, uint32_t latency
)
4294 uint32_t wm_intermediate_val
;
4295 uint_fixed_16_16_t ret
;
4298 return FP_16_16_MAX
;
4300 wm_intermediate_val
= latency
* pixel_rate
* cpp
;
4301 ret
= div_fixed16(wm_intermediate_val
, 1000 * 512);
4303 if (INTEL_GEN(dev_priv
) >= 10)
4304 ret
= add_fixed16_u32(ret
, 1);
4309 static uint_fixed_16_16_t
skl_wm_method2(uint32_t pixel_rate
,
4310 uint32_t pipe_htotal
,
4312 uint_fixed_16_16_t plane_blocks_per_line
)
4314 uint32_t wm_intermediate_val
;
4315 uint_fixed_16_16_t ret
;
4318 return FP_16_16_MAX
;
4320 wm_intermediate_val
= latency
* pixel_rate
;
4321 wm_intermediate_val
= DIV_ROUND_UP(wm_intermediate_val
,
4322 pipe_htotal
* 1000);
4323 ret
= mul_u32_fixed16(wm_intermediate_val
, plane_blocks_per_line
);
4327 static uint_fixed_16_16_t
4328 intel_get_linetime_us(struct intel_crtc_state
*cstate
)
4330 uint32_t pixel_rate
;
4331 uint32_t crtc_htotal
;
4332 uint_fixed_16_16_t linetime_us
;
4334 if (!cstate
->base
.active
)
4335 return u32_to_fixed16(0);
4337 pixel_rate
= cstate
->pixel_rate
;
4339 if (WARN_ON(pixel_rate
== 0))
4340 return u32_to_fixed16(0);
4342 crtc_htotal
= cstate
->base
.adjusted_mode
.crtc_htotal
;
4343 linetime_us
= div_fixed16(crtc_htotal
* 1000, pixel_rate
);
4349 skl_adjusted_plane_pixel_rate(const struct intel_crtc_state
*cstate
,
4350 const struct intel_plane_state
*pstate
)
4352 uint64_t adjusted_pixel_rate
;
4353 uint_fixed_16_16_t downscale_amount
;
4355 /* Shouldn't reach here on disabled planes... */
4356 if (WARN_ON(!intel_wm_plane_visible(cstate
, pstate
)))
4360 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
4361 * with additional adjustments for plane-specific scaling.
4363 adjusted_pixel_rate
= cstate
->pixel_rate
;
4364 downscale_amount
= skl_plane_downscale_amount(cstate
, pstate
);
4366 return mul_round_up_u32_fixed16(adjusted_pixel_rate
,
4371 skl_compute_plane_wm_params(const struct drm_i915_private
*dev_priv
,
4372 struct intel_crtc_state
*cstate
,
4373 const struct intel_plane_state
*intel_pstate
,
4374 struct skl_wm_params
*wp
)
4376 struct intel_plane
*plane
= to_intel_plane(intel_pstate
->base
.plane
);
4377 const struct drm_plane_state
*pstate
= &intel_pstate
->base
;
4378 const struct drm_framebuffer
*fb
= pstate
->fb
;
4379 uint32_t interm_pbpl
;
4380 struct intel_atomic_state
*state
=
4381 to_intel_atomic_state(cstate
->base
.state
);
4382 bool apply_memory_bw_wa
= skl_needs_memory_bw_wa(state
);
4384 if (!intel_wm_plane_visible(cstate
, intel_pstate
))
4387 wp
->y_tiled
= fb
->modifier
== I915_FORMAT_MOD_Y_TILED
||
4388 fb
->modifier
== I915_FORMAT_MOD_Yf_TILED
||
4389 fb
->modifier
== I915_FORMAT_MOD_Y_TILED_CCS
||
4390 fb
->modifier
== I915_FORMAT_MOD_Yf_TILED_CCS
;
4391 wp
->x_tiled
= fb
->modifier
== I915_FORMAT_MOD_X_TILED
;
4392 wp
->rc_surface
= fb
->modifier
== I915_FORMAT_MOD_Y_TILED_CCS
||
4393 fb
->modifier
== I915_FORMAT_MOD_Yf_TILED_CCS
;
4395 if (plane
->id
== PLANE_CURSOR
) {
4396 wp
->width
= intel_pstate
->base
.crtc_w
;
4399 * Src coordinates are already rotated by 270 degrees for
4400 * the 90/270 degree plane rotation cases (to match the
4401 * GTT mapping), hence no need to account for rotation here.
4403 wp
->width
= drm_rect_width(&intel_pstate
->base
.src
) >> 16;
4406 wp
->cpp
= (fb
->format
->format
== DRM_FORMAT_NV12
) ? fb
->format
->cpp
[1] :
4408 wp
->plane_pixel_rate
= skl_adjusted_plane_pixel_rate(cstate
,
4411 if (drm_rotation_90_or_270(pstate
->rotation
)) {
4415 wp
->y_min_scanlines
= 16;
4418 wp
->y_min_scanlines
= 8;
4421 wp
->y_min_scanlines
= 4;
4424 MISSING_CASE(wp
->cpp
);
4428 wp
->y_min_scanlines
= 4;
4431 if (apply_memory_bw_wa
)
4432 wp
->y_min_scanlines
*= 2;
4434 wp
->plane_bytes_per_line
= wp
->width
* wp
->cpp
;
4436 interm_pbpl
= DIV_ROUND_UP(wp
->plane_bytes_per_line
*
4437 wp
->y_min_scanlines
, 512);
4439 if (INTEL_GEN(dev_priv
) >= 10)
4442 wp
->plane_blocks_per_line
= div_fixed16(interm_pbpl
,
4443 wp
->y_min_scanlines
);
4444 } else if (wp
->x_tiled
&& IS_GEN9(dev_priv
)) {
4445 interm_pbpl
= DIV_ROUND_UP(wp
->plane_bytes_per_line
, 512);
4446 wp
->plane_blocks_per_line
= u32_to_fixed16(interm_pbpl
);
4448 interm_pbpl
= DIV_ROUND_UP(wp
->plane_bytes_per_line
, 512) + 1;
4449 wp
->plane_blocks_per_line
= u32_to_fixed16(interm_pbpl
);
4452 wp
->y_tile_minimum
= mul_u32_fixed16(wp
->y_min_scanlines
,
4453 wp
->plane_blocks_per_line
);
4454 wp
->linetime_us
= fixed16_to_u32_round_up(
4455 intel_get_linetime_us(cstate
));
4460 static int skl_compute_plane_wm(const struct drm_i915_private
*dev_priv
,
4461 struct intel_crtc_state
*cstate
,
4462 const struct intel_plane_state
*intel_pstate
,
4463 uint16_t ddb_allocation
,
4465 const struct skl_wm_params
*wp
,
4466 uint16_t *out_blocks
, /* out */
4467 uint8_t *out_lines
, /* out */
4468 bool *enabled
/* out */)
4470 const struct drm_plane_state
*pstate
= &intel_pstate
->base
;
4471 uint32_t latency
= dev_priv
->wm
.skl_latency
[level
];
4472 uint_fixed_16_16_t method1
, method2
;
4473 uint_fixed_16_16_t selected_result
;
4474 uint32_t res_blocks
, res_lines
;
4475 struct intel_atomic_state
*state
=
4476 to_intel_atomic_state(cstate
->base
.state
);
4477 bool apply_memory_bw_wa
= skl_needs_memory_bw_wa(state
);
4480 !intel_wm_plane_visible(cstate
, intel_pstate
)) {
4485 /* Display WA #1141: kbl,cfl */
4486 if ((IS_KABYLAKE(dev_priv
) || IS_COFFEELAKE(dev_priv
) ||
4487 IS_CNL_REVID(dev_priv
, CNL_REVID_A0
, CNL_REVID_B0
)) &&
4488 dev_priv
->ipc_enabled
)
4491 if (apply_memory_bw_wa
&& wp
->x_tiled
)
4494 method1
= skl_wm_method1(dev_priv
, wp
->plane_pixel_rate
,
4496 method2
= skl_wm_method2(wp
->plane_pixel_rate
,
4497 cstate
->base
.adjusted_mode
.crtc_htotal
,
4499 wp
->plane_blocks_per_line
);
4502 selected_result
= max_fixed16(method2
, wp
->y_tile_minimum
);
4504 if ((wp
->cpp
* cstate
->base
.adjusted_mode
.crtc_htotal
/
4505 512 < 1) && (wp
->plane_bytes_per_line
/ 512 < 1))
4506 selected_result
= method2
;
4507 else if (ddb_allocation
>=
4508 fixed16_to_u32_round_up(wp
->plane_blocks_per_line
))
4509 selected_result
= min_fixed16(method1
, method2
);
4510 else if (latency
>= wp
->linetime_us
)
4511 selected_result
= min_fixed16(method1
, method2
);
4513 selected_result
= method1
;
4516 res_blocks
= fixed16_to_u32_round_up(selected_result
) + 1;
4517 res_lines
= div_round_up_fixed16(selected_result
,
4518 wp
->plane_blocks_per_line
);
4520 /* Display WA #1125: skl,bxt,kbl,glk */
4521 if (level
== 0 && wp
->rc_surface
)
4522 res_blocks
+= fixed16_to_u32_round_up(wp
->y_tile_minimum
);
4524 /* Display WA #1126: skl,bxt,kbl,glk */
4525 if (level
>= 1 && level
<= 7) {
4527 res_blocks
+= fixed16_to_u32_round_up(
4528 wp
->y_tile_minimum
);
4529 res_lines
+= wp
->y_min_scanlines
;
4535 if (res_blocks
>= ddb_allocation
|| res_lines
> 31) {
4539 * If there are no valid level 0 watermarks, then we can't
4540 * support this display configuration.
4545 struct drm_plane
*plane
= pstate
->plane
;
4547 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
4548 DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n",
4549 plane
->base
.id
, plane
->name
,
4550 res_blocks
, ddb_allocation
, res_lines
);
4555 *out_blocks
= res_blocks
;
4556 *out_lines
= res_lines
;
4563 skl_compute_wm_levels(const struct drm_i915_private
*dev_priv
,
4564 struct skl_ddb_allocation
*ddb
,
4565 struct intel_crtc_state
*cstate
,
4566 const struct intel_plane_state
*intel_pstate
,
4567 const struct skl_wm_params
*wm_params
,
4568 struct skl_plane_wm
*wm
)
4570 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
4571 struct drm_plane
*plane
= intel_pstate
->base
.plane
;
4572 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
4573 uint16_t ddb_blocks
;
4574 enum pipe pipe
= intel_crtc
->pipe
;
4575 int level
, max_level
= ilk_wm_max_level(dev_priv
);
4578 if (WARN_ON(!intel_pstate
->base
.fb
))
4581 ddb_blocks
= skl_ddb_entry_size(&ddb
->plane
[pipe
][intel_plane
->id
]);
4583 for (level
= 0; level
<= max_level
; level
++) {
4584 struct skl_wm_level
*result
= &wm
->wm
[level
];
4586 ret
= skl_compute_plane_wm(dev_priv
,
4592 &result
->plane_res_b
,
4593 &result
->plane_res_l
,
4603 skl_compute_linetime_wm(struct intel_crtc_state
*cstate
)
4605 struct drm_atomic_state
*state
= cstate
->base
.state
;
4606 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
4607 uint_fixed_16_16_t linetime_us
;
4608 uint32_t linetime_wm
;
4610 linetime_us
= intel_get_linetime_us(cstate
);
4612 if (is_fixed16_zero(linetime_us
))
4615 linetime_wm
= fixed16_to_u32_round_up(mul_u32_fixed16(8, linetime_us
));
4617 /* Display WA #1135: bxt:ALL GLK:ALL */
4618 if ((IS_BROXTON(dev_priv
) || IS_GEMINILAKE(dev_priv
)) &&
4619 dev_priv
->ipc_enabled
)
4625 static void skl_compute_transition_wm(struct intel_crtc_state
*cstate
,
4626 struct skl_wm_params
*wp
,
4627 struct skl_wm_level
*wm_l0
,
4628 uint16_t ddb_allocation
,
4629 struct skl_wm_level
*trans_wm
/* out */)
4631 struct drm_device
*dev
= cstate
->base
.crtc
->dev
;
4632 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
4633 uint16_t trans_min
, trans_y_tile_min
;
4634 const uint16_t trans_amount
= 10; /* This is configurable amount */
4635 uint16_t trans_offset_b
, res_blocks
;
4637 if (!cstate
->base
.active
)
4640 /* Transition WM are not recommended by HW team for GEN9 */
4641 if (INTEL_GEN(dev_priv
) <= 9)
4644 /* Transition WM don't make any sense if ipc is disabled */
4645 if (!dev_priv
->ipc_enabled
)
4648 if (INTEL_GEN(dev_priv
) >= 10)
4651 trans_offset_b
= trans_min
+ trans_amount
;
4654 trans_y_tile_min
= (uint16_t) mul_round_up_u32_fixed16(2,
4655 wp
->y_tile_minimum
);
4656 res_blocks
= max(wm_l0
->plane_res_b
, trans_y_tile_min
) +
4659 res_blocks
= wm_l0
->plane_res_b
+ trans_offset_b
;
4661 /* WA BUG:1938466 add one block for non y-tile planes */
4662 if (IS_CNL_REVID(dev_priv
, CNL_REVID_A0
, CNL_REVID_A0
))
4669 if (res_blocks
< ddb_allocation
) {
4670 trans_wm
->plane_res_b
= res_blocks
;
4671 trans_wm
->plane_en
= true;
4676 trans_wm
->plane_en
= false;
4679 static int skl_build_pipe_wm(struct intel_crtc_state
*cstate
,
4680 struct skl_ddb_allocation
*ddb
,
4681 struct skl_pipe_wm
*pipe_wm
)
4683 struct drm_device
*dev
= cstate
->base
.crtc
->dev
;
4684 struct drm_crtc_state
*crtc_state
= &cstate
->base
;
4685 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
4686 struct drm_plane
*plane
;
4687 const struct drm_plane_state
*pstate
;
4688 struct skl_plane_wm
*wm
;
4692 * We'll only calculate watermarks for planes that are actually
4693 * enabled, so make sure all other planes are set as disabled.
4695 memset(pipe_wm
->planes
, 0, sizeof(pipe_wm
->planes
));
4697 drm_atomic_crtc_state_for_each_plane_state(plane
, pstate
, crtc_state
) {
4698 const struct intel_plane_state
*intel_pstate
=
4699 to_intel_plane_state(pstate
);
4700 enum plane_id plane_id
= to_intel_plane(plane
)->id
;
4701 struct skl_wm_params wm_params
;
4702 enum pipe pipe
= to_intel_crtc(cstate
->base
.crtc
)->pipe
;
4703 uint16_t ddb_blocks
;
4705 wm
= &pipe_wm
->planes
[plane_id
];
4706 ddb_blocks
= skl_ddb_entry_size(&ddb
->plane
[pipe
][plane_id
]);
4707 memset(&wm_params
, 0, sizeof(struct skl_wm_params
));
4709 ret
= skl_compute_plane_wm_params(dev_priv
, cstate
,
4710 intel_pstate
, &wm_params
);
4714 ret
= skl_compute_wm_levels(dev_priv
, ddb
, cstate
,
4715 intel_pstate
, &wm_params
, wm
);
4718 skl_compute_transition_wm(cstate
, &wm_params
, &wm
->wm
[0],
4719 ddb_blocks
, &wm
->trans_wm
);
4721 pipe_wm
->linetime
= skl_compute_linetime_wm(cstate
);
4726 static void skl_ddb_entry_write(struct drm_i915_private
*dev_priv
,
4728 const struct skl_ddb_entry
*entry
)
4731 I915_WRITE(reg
, (entry
->end
- 1) << 16 | entry
->start
);
4736 static void skl_write_wm_level(struct drm_i915_private
*dev_priv
,
4738 const struct skl_wm_level
*level
)
4742 if (level
->plane_en
) {
4744 val
|= level
->plane_res_b
;
4745 val
|= level
->plane_res_l
<< PLANE_WM_LINES_SHIFT
;
4748 I915_WRITE(reg
, val
);
4751 static void skl_write_plane_wm(struct intel_crtc
*intel_crtc
,
4752 const struct skl_plane_wm
*wm
,
4753 const struct skl_ddb_allocation
*ddb
,
4754 enum plane_id plane_id
)
4756 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4757 struct drm_device
*dev
= crtc
->dev
;
4758 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4759 int level
, max_level
= ilk_wm_max_level(dev_priv
);
4760 enum pipe pipe
= intel_crtc
->pipe
;
4762 for (level
= 0; level
<= max_level
; level
++) {
4763 skl_write_wm_level(dev_priv
, PLANE_WM(pipe
, plane_id
, level
),
4766 skl_write_wm_level(dev_priv
, PLANE_WM_TRANS(pipe
, plane_id
),
4769 skl_ddb_entry_write(dev_priv
, PLANE_BUF_CFG(pipe
, plane_id
),
4770 &ddb
->plane
[pipe
][plane_id
]);
4771 skl_ddb_entry_write(dev_priv
, PLANE_NV12_BUF_CFG(pipe
, plane_id
),
4772 &ddb
->y_plane
[pipe
][plane_id
]);
4775 static void skl_write_cursor_wm(struct intel_crtc
*intel_crtc
,
4776 const struct skl_plane_wm
*wm
,
4777 const struct skl_ddb_allocation
*ddb
)
4779 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4780 struct drm_device
*dev
= crtc
->dev
;
4781 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4782 int level
, max_level
= ilk_wm_max_level(dev_priv
);
4783 enum pipe pipe
= intel_crtc
->pipe
;
4785 for (level
= 0; level
<= max_level
; level
++) {
4786 skl_write_wm_level(dev_priv
, CUR_WM(pipe
, level
),
4789 skl_write_wm_level(dev_priv
, CUR_WM_TRANS(pipe
), &wm
->trans_wm
);
4791 skl_ddb_entry_write(dev_priv
, CUR_BUF_CFG(pipe
),
4792 &ddb
->plane
[pipe
][PLANE_CURSOR
]);
4795 bool skl_wm_level_equals(const struct skl_wm_level
*l1
,
4796 const struct skl_wm_level
*l2
)
4798 if (l1
->plane_en
!= l2
->plane_en
)
4801 /* If both planes aren't enabled, the rest shouldn't matter */
4805 return (l1
->plane_res_l
== l2
->plane_res_l
&&
4806 l1
->plane_res_b
== l2
->plane_res_b
);
4809 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry
*a
,
4810 const struct skl_ddb_entry
*b
)
4812 return a
->start
< b
->end
&& b
->start
< a
->end
;
4815 bool skl_ddb_allocation_overlaps(struct drm_i915_private
*dev_priv
,
4816 const struct skl_ddb_entry
**entries
,
4817 const struct skl_ddb_entry
*ddb
,
4822 for_each_pipe(dev_priv
, pipe
) {
4823 if (pipe
!= ignore
&& entries
[pipe
] &&
4824 skl_ddb_entries_overlap(ddb
, entries
[pipe
]))
4831 static int skl_update_pipe_wm(struct drm_crtc_state
*cstate
,
4832 const struct skl_pipe_wm
*old_pipe_wm
,
4833 struct skl_pipe_wm
*pipe_wm
, /* out */
4834 struct skl_ddb_allocation
*ddb
, /* out */
4835 bool *changed
/* out */)
4837 struct intel_crtc_state
*intel_cstate
= to_intel_crtc_state(cstate
);
4840 ret
= skl_build_pipe_wm(intel_cstate
, ddb
, pipe_wm
);
4844 if (!memcmp(old_pipe_wm
, pipe_wm
, sizeof(*pipe_wm
)))
4853 pipes_modified(struct drm_atomic_state
*state
)
4855 struct drm_crtc
*crtc
;
4856 struct drm_crtc_state
*cstate
;
4857 uint32_t i
, ret
= 0;
4859 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
)
4860 ret
|= drm_crtc_mask(crtc
);
4866 skl_ddb_add_affected_planes(struct intel_crtc_state
*cstate
)
4868 struct drm_atomic_state
*state
= cstate
->base
.state
;
4869 struct drm_device
*dev
= state
->dev
;
4870 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
4871 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4872 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4873 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
4874 struct skl_ddb_allocation
*new_ddb
= &intel_state
->wm_results
.ddb
;
4875 struct skl_ddb_allocation
*cur_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
4876 struct drm_plane_state
*plane_state
;
4877 struct drm_plane
*plane
;
4878 enum pipe pipe
= intel_crtc
->pipe
;
4880 WARN_ON(!drm_atomic_get_existing_crtc_state(state
, crtc
));
4882 drm_for_each_plane_mask(plane
, dev
, cstate
->base
.plane_mask
) {
4883 enum plane_id plane_id
= to_intel_plane(plane
)->id
;
4885 if (skl_ddb_entry_equal(&cur_ddb
->plane
[pipe
][plane_id
],
4886 &new_ddb
->plane
[pipe
][plane_id
]) &&
4887 skl_ddb_entry_equal(&cur_ddb
->y_plane
[pipe
][plane_id
],
4888 &new_ddb
->y_plane
[pipe
][plane_id
]))
4891 plane_state
= drm_atomic_get_plane_state(state
, plane
);
4892 if (IS_ERR(plane_state
))
4893 return PTR_ERR(plane_state
);
4900 skl_compute_ddb(struct drm_atomic_state
*state
)
4902 struct drm_device
*dev
= state
->dev
;
4903 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4904 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
4905 struct intel_crtc
*intel_crtc
;
4906 struct skl_ddb_allocation
*ddb
= &intel_state
->wm_results
.ddb
;
4907 uint32_t realloc_pipes
= pipes_modified(state
);
4911 * If this is our first atomic update following hardware readout,
4912 * we can't trust the DDB that the BIOS programmed for us. Let's
4913 * pretend that all pipes switched active status so that we'll
4914 * ensure a full DDB recompute.
4916 if (dev_priv
->wm
.distrust_bios_wm
) {
4917 ret
= drm_modeset_lock(&dev
->mode_config
.connection_mutex
,
4918 state
->acquire_ctx
);
4922 intel_state
->active_pipe_changes
= ~0;
4925 * We usually only initialize intel_state->active_crtcs if we
4926 * we're doing a modeset; make sure this field is always
4927 * initialized during the sanitization process that happens
4928 * on the first commit too.
4930 if (!intel_state
->modeset
)
4931 intel_state
->active_crtcs
= dev_priv
->active_crtcs
;
4935 * If the modeset changes which CRTC's are active, we need to
4936 * recompute the DDB allocation for *all* active pipes, even
4937 * those that weren't otherwise being modified in any way by this
4938 * atomic commit. Due to the shrinking of the per-pipe allocations
4939 * when new active CRTC's are added, it's possible for a pipe that
4940 * we were already using and aren't changing at all here to suddenly
4941 * become invalid if its DDB needs exceeds its new allocation.
4943 * Note that if we wind up doing a full DDB recompute, we can't let
4944 * any other display updates race with this transaction, so we need
4945 * to grab the lock on *all* CRTC's.
4947 if (intel_state
->active_pipe_changes
) {
4949 intel_state
->wm_results
.dirty_pipes
= ~0;
4953 * We're not recomputing for the pipes not included in the commit, so
4954 * make sure we start with the current state.
4956 memcpy(ddb
, &dev_priv
->wm
.skl_hw
.ddb
, sizeof(*ddb
));
4958 for_each_intel_crtc_mask(dev
, intel_crtc
, realloc_pipes
) {
4959 struct intel_crtc_state
*cstate
;
4961 cstate
= intel_atomic_get_crtc_state(state
, intel_crtc
);
4963 return PTR_ERR(cstate
);
4965 ret
= skl_allocate_pipe_ddb(cstate
, ddb
);
4969 ret
= skl_ddb_add_affected_planes(cstate
);
4978 skl_copy_wm_for_pipe(struct skl_wm_values
*dst
,
4979 struct skl_wm_values
*src
,
4982 memcpy(dst
->ddb
.y_plane
[pipe
], src
->ddb
.y_plane
[pipe
],
4983 sizeof(dst
->ddb
.y_plane
[pipe
]));
4984 memcpy(dst
->ddb
.plane
[pipe
], src
->ddb
.plane
[pipe
],
4985 sizeof(dst
->ddb
.plane
[pipe
]));
4989 skl_print_wm_changes(const struct drm_atomic_state
*state
)
4991 const struct drm_device
*dev
= state
->dev
;
4992 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
4993 const struct intel_atomic_state
*intel_state
=
4994 to_intel_atomic_state(state
);
4995 const struct drm_crtc
*crtc
;
4996 const struct drm_crtc_state
*cstate
;
4997 const struct intel_plane
*intel_plane
;
4998 const struct skl_ddb_allocation
*old_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
4999 const struct skl_ddb_allocation
*new_ddb
= &intel_state
->wm_results
.ddb
;
5002 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
) {
5003 const struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5004 enum pipe pipe
= intel_crtc
->pipe
;
5006 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
5007 enum plane_id plane_id
= intel_plane
->id
;
5008 const struct skl_ddb_entry
*old
, *new;
5010 old
= &old_ddb
->plane
[pipe
][plane_id
];
5011 new = &new_ddb
->plane
[pipe
][plane_id
];
5013 if (skl_ddb_entry_equal(old
, new))
5016 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
5017 intel_plane
->base
.base
.id
,
5018 intel_plane
->base
.name
,
5019 old
->start
, old
->end
,
5020 new->start
, new->end
);
5026 skl_compute_wm(struct drm_atomic_state
*state
)
5028 struct drm_crtc
*crtc
;
5029 struct drm_crtc_state
*cstate
;
5030 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
5031 struct skl_wm_values
*results
= &intel_state
->wm_results
;
5032 struct drm_device
*dev
= state
->dev
;
5033 struct skl_pipe_wm
*pipe_wm
;
5034 bool changed
= false;
5038 * When we distrust bios wm we always need to recompute to set the
5039 * expected DDB allocations for each CRTC.
5041 if (to_i915(dev
)->wm
.distrust_bios_wm
)
5045 * If this transaction isn't actually touching any CRTC's, don't
5046 * bother with watermark calculation. Note that if we pass this
5047 * test, we're guaranteed to hold at least one CRTC state mutex,
5048 * which means we can safely use values like dev_priv->active_crtcs
5049 * since any racing commits that want to update them would need to
5050 * hold _all_ CRTC state mutexes.
5052 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
)
5058 /* Clear all dirty flags */
5059 results
->dirty_pipes
= 0;
5061 ret
= skl_compute_ddb(state
);
5066 * Calculate WM's for all pipes that are part of this transaction.
5067 * Note that the DDB allocation above may have added more CRTC's that
5068 * weren't otherwise being modified (and set bits in dirty_pipes) if
5069 * pipe allocations had to change.
5071 * FIXME: Now that we're doing this in the atomic check phase, we
5072 * should allow skl_update_pipe_wm() to return failure in cases where
5073 * no suitable watermark values can be found.
5075 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
) {
5076 struct intel_crtc_state
*intel_cstate
=
5077 to_intel_crtc_state(cstate
);
5078 const struct skl_pipe_wm
*old_pipe_wm
=
5079 &to_intel_crtc_state(crtc
->state
)->wm
.skl
.optimal
;
5081 pipe_wm
= &intel_cstate
->wm
.skl
.optimal
;
5082 ret
= skl_update_pipe_wm(cstate
, old_pipe_wm
, pipe_wm
,
5083 &results
->ddb
, &changed
);
5088 results
->dirty_pipes
|= drm_crtc_mask(crtc
);
5090 if ((results
->dirty_pipes
& drm_crtc_mask(crtc
)) == 0)
5091 /* This pipe's WM's did not change */
5094 intel_cstate
->update_wm_pre
= true;
5097 skl_print_wm_changes(state
);
5102 static void skl_atomic_update_crtc_wm(struct intel_atomic_state
*state
,
5103 struct intel_crtc_state
*cstate
)
5105 struct intel_crtc
*crtc
= to_intel_crtc(cstate
->base
.crtc
);
5106 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
5107 struct skl_pipe_wm
*pipe_wm
= &cstate
->wm
.skl
.optimal
;
5108 const struct skl_ddb_allocation
*ddb
= &state
->wm_results
.ddb
;
5109 enum pipe pipe
= crtc
->pipe
;
5110 enum plane_id plane_id
;
5112 if (!(state
->wm_results
.dirty_pipes
& drm_crtc_mask(&crtc
->base
)))
5115 I915_WRITE(PIPE_WM_LINETIME(pipe
), pipe_wm
->linetime
);
5117 for_each_plane_id_on_crtc(crtc
, plane_id
) {
5118 if (plane_id
!= PLANE_CURSOR
)
5119 skl_write_plane_wm(crtc
, &pipe_wm
->planes
[plane_id
],
5122 skl_write_cursor_wm(crtc
, &pipe_wm
->planes
[plane_id
],
5127 static void skl_initial_wm(struct intel_atomic_state
*state
,
5128 struct intel_crtc_state
*cstate
)
5130 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
5131 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5132 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5133 struct skl_wm_values
*results
= &state
->wm_results
;
5134 struct skl_wm_values
*hw_vals
= &dev_priv
->wm
.skl_hw
;
5135 enum pipe pipe
= intel_crtc
->pipe
;
5137 if ((results
->dirty_pipes
& drm_crtc_mask(&intel_crtc
->base
)) == 0)
5140 mutex_lock(&dev_priv
->wm
.wm_mutex
);
5142 if (cstate
->base
.active_changed
)
5143 skl_atomic_update_crtc_wm(state
, cstate
);
5145 skl_copy_wm_for_pipe(hw_vals
, results
, pipe
);
5147 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
5150 static void ilk_compute_wm_config(struct drm_device
*dev
,
5151 struct intel_wm_config
*config
)
5153 struct intel_crtc
*crtc
;
5155 /* Compute the currently _active_ config */
5156 for_each_intel_crtc(dev
, crtc
) {
5157 const struct intel_pipe_wm
*wm
= &crtc
->wm
.active
.ilk
;
5159 if (!wm
->pipe_enabled
)
5162 config
->sprites_enabled
|= wm
->sprites_enabled
;
5163 config
->sprites_scaled
|= wm
->sprites_scaled
;
5164 config
->num_pipes_active
++;
5168 static void ilk_program_watermarks(struct drm_i915_private
*dev_priv
)
5170 struct drm_device
*dev
= &dev_priv
->drm
;
5171 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
5172 struct ilk_wm_maximums max
;
5173 struct intel_wm_config config
= {};
5174 struct ilk_wm_values results
= {};
5175 enum intel_ddb_partitioning partitioning
;
5177 ilk_compute_wm_config(dev
, &config
);
5179 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_1_2
, &max
);
5180 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_1_2
);
5182 /* 5/6 split only in single pipe config on IVB+ */
5183 if (INTEL_GEN(dev_priv
) >= 7 &&
5184 config
.num_pipes_active
== 1 && config
.sprites_enabled
) {
5185 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_5_6
, &max
);
5186 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_5_6
);
5188 best_lp_wm
= ilk_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
5190 best_lp_wm
= &lp_wm_1_2
;
5193 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
5194 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
5196 ilk_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
5198 ilk_write_wm_values(dev_priv
, &results
);
5201 static void ilk_initial_watermarks(struct intel_atomic_state
*state
,
5202 struct intel_crtc_state
*cstate
)
5204 struct drm_i915_private
*dev_priv
= to_i915(cstate
->base
.crtc
->dev
);
5205 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
5207 mutex_lock(&dev_priv
->wm
.wm_mutex
);
5208 intel_crtc
->wm
.active
.ilk
= cstate
->wm
.ilk
.intermediate
;
5209 ilk_program_watermarks(dev_priv
);
5210 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
5213 static void ilk_optimize_watermarks(struct intel_atomic_state
*state
,
5214 struct intel_crtc_state
*cstate
)
5216 struct drm_i915_private
*dev_priv
= to_i915(cstate
->base
.crtc
->dev
);
5217 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
5219 mutex_lock(&dev_priv
->wm
.wm_mutex
);
5220 if (cstate
->wm
.need_postvbl_update
) {
5221 intel_crtc
->wm
.active
.ilk
= cstate
->wm
.ilk
.optimal
;
5222 ilk_program_watermarks(dev_priv
);
5224 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
5227 static inline void skl_wm_level_from_reg_val(uint32_t val
,
5228 struct skl_wm_level
*level
)
5230 level
->plane_en
= val
& PLANE_WM_EN
;
5231 level
->plane_res_b
= val
& PLANE_WM_BLOCKS_MASK
;
5232 level
->plane_res_l
= (val
>> PLANE_WM_LINES_SHIFT
) &
5233 PLANE_WM_LINES_MASK
;
5236 void skl_pipe_wm_get_hw_state(struct drm_crtc
*crtc
,
5237 struct skl_pipe_wm
*out
)
5239 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
5240 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5241 enum pipe pipe
= intel_crtc
->pipe
;
5242 int level
, max_level
;
5243 enum plane_id plane_id
;
5246 max_level
= ilk_wm_max_level(dev_priv
);
5248 for_each_plane_id_on_crtc(intel_crtc
, plane_id
) {
5249 struct skl_plane_wm
*wm
= &out
->planes
[plane_id
];
5251 for (level
= 0; level
<= max_level
; level
++) {
5252 if (plane_id
!= PLANE_CURSOR
)
5253 val
= I915_READ(PLANE_WM(pipe
, plane_id
, level
));
5255 val
= I915_READ(CUR_WM(pipe
, level
));
5257 skl_wm_level_from_reg_val(val
, &wm
->wm
[level
]);
5260 if (plane_id
!= PLANE_CURSOR
)
5261 val
= I915_READ(PLANE_WM_TRANS(pipe
, plane_id
));
5263 val
= I915_READ(CUR_WM_TRANS(pipe
));
5265 skl_wm_level_from_reg_val(val
, &wm
->trans_wm
);
5268 if (!intel_crtc
->active
)
5271 out
->linetime
= I915_READ(PIPE_WM_LINETIME(pipe
));
5274 void skl_wm_get_hw_state(struct drm_device
*dev
)
5276 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5277 struct skl_wm_values
*hw
= &dev_priv
->wm
.skl_hw
;
5278 struct skl_ddb_allocation
*ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
5279 struct drm_crtc
*crtc
;
5280 struct intel_crtc
*intel_crtc
;
5281 struct intel_crtc_state
*cstate
;
5283 skl_ddb_get_hw_state(dev_priv
, ddb
);
5284 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
5285 intel_crtc
= to_intel_crtc(crtc
);
5286 cstate
= to_intel_crtc_state(crtc
->state
);
5288 skl_pipe_wm_get_hw_state(crtc
, &cstate
->wm
.skl
.optimal
);
5290 if (intel_crtc
->active
)
5291 hw
->dirty_pipes
|= drm_crtc_mask(crtc
);
5294 if (dev_priv
->active_crtcs
) {
5295 /* Fully recompute DDB on first atomic commit */
5296 dev_priv
->wm
.distrust_bios_wm
= true;
5298 /* Easy/common case; just sanitize DDB now if everything off */
5299 memset(ddb
, 0, sizeof(*ddb
));
5303 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
5305 struct drm_device
*dev
= crtc
->dev
;
5306 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5307 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
5308 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5309 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
5310 struct intel_pipe_wm
*active
= &cstate
->wm
.ilk
.optimal
;
5311 enum pipe pipe
= intel_crtc
->pipe
;
5312 static const i915_reg_t wm0_pipe_reg
[] = {
5313 [PIPE_A
] = WM0_PIPEA_ILK
,
5314 [PIPE_B
] = WM0_PIPEB_ILK
,
5315 [PIPE_C
] = WM0_PIPEC_IVB
,
5318 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
5319 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5320 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
5322 memset(active
, 0, sizeof(*active
));
5324 active
->pipe_enabled
= intel_crtc
->active
;
5326 if (active
->pipe_enabled
) {
5327 u32 tmp
= hw
->wm_pipe
[pipe
];
5330 * For active pipes LP0 watermark is marked as
5331 * enabled, and LP1+ watermaks as disabled since
5332 * we can't really reverse compute them in case
5333 * multiple pipes are active.
5335 active
->wm
[0].enable
= true;
5336 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
5337 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
5338 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
5339 active
->linetime
= hw
->wm_linetime
[pipe
];
5341 int level
, max_level
= ilk_wm_max_level(dev_priv
);
5344 * For inactive pipes, all watermark levels
5345 * should be marked as enabled but zeroed,
5346 * which is what we'd compute them to.
5348 for (level
= 0; level
<= max_level
; level
++)
5349 active
->wm
[level
].enable
= true;
5352 intel_crtc
->wm
.active
.ilk
= *active
;
5355 #define _FW_WM(value, plane) \
5356 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
5357 #define _FW_WM_VLV(value, plane) \
5358 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
5360 static void g4x_read_wm_values(struct drm_i915_private
*dev_priv
,
5361 struct g4x_wm_values
*wm
)
5365 tmp
= I915_READ(DSPFW1
);
5366 wm
->sr
.plane
= _FW_WM(tmp
, SR
);
5367 wm
->pipe
[PIPE_B
].plane
[PLANE_CURSOR
] = _FW_WM(tmp
, CURSORB
);
5368 wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] = _FW_WM(tmp
, PLANEB
);
5369 wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] = _FW_WM(tmp
, PLANEA
);
5371 tmp
= I915_READ(DSPFW2
);
5372 wm
->fbc_en
= tmp
& DSPFW_FBC_SR_EN
;
5373 wm
->sr
.fbc
= _FW_WM(tmp
, FBC_SR
);
5374 wm
->hpll
.fbc
= _FW_WM(tmp
, FBC_HPLL_SR
);
5375 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] = _FW_WM(tmp
, SPRITEB
);
5376 wm
->pipe
[PIPE_A
].plane
[PLANE_CURSOR
] = _FW_WM(tmp
, CURSORA
);
5377 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] = _FW_WM(tmp
, SPRITEA
);
5379 tmp
= I915_READ(DSPFW3
);
5380 wm
->hpll_en
= tmp
& DSPFW_HPLL_SR_EN
;
5381 wm
->sr
.cursor
= _FW_WM(tmp
, CURSOR_SR
);
5382 wm
->hpll
.cursor
= _FW_WM(tmp
, HPLL_CURSOR
);
5383 wm
->hpll
.plane
= _FW_WM(tmp
, HPLL_SR
);
5386 static void vlv_read_wm_values(struct drm_i915_private
*dev_priv
,
5387 struct vlv_wm_values
*wm
)
5392 for_each_pipe(dev_priv
, pipe
) {
5393 tmp
= I915_READ(VLV_DDL(pipe
));
5395 wm
->ddl
[pipe
].plane
[PLANE_PRIMARY
] =
5396 (tmp
>> DDL_PLANE_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
5397 wm
->ddl
[pipe
].plane
[PLANE_CURSOR
] =
5398 (tmp
>> DDL_CURSOR_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
5399 wm
->ddl
[pipe
].plane
[PLANE_SPRITE0
] =
5400 (tmp
>> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
5401 wm
->ddl
[pipe
].plane
[PLANE_SPRITE1
] =
5402 (tmp
>> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
5405 tmp
= I915_READ(DSPFW1
);
5406 wm
->sr
.plane
= _FW_WM(tmp
, SR
);
5407 wm
->pipe
[PIPE_B
].plane
[PLANE_CURSOR
] = _FW_WM(tmp
, CURSORB
);
5408 wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] = _FW_WM_VLV(tmp
, PLANEB
);
5409 wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] = _FW_WM_VLV(tmp
, PLANEA
);
5411 tmp
= I915_READ(DSPFW2
);
5412 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] = _FW_WM_VLV(tmp
, SPRITEB
);
5413 wm
->pipe
[PIPE_A
].plane
[PLANE_CURSOR
] = _FW_WM(tmp
, CURSORA
);
5414 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] = _FW_WM_VLV(tmp
, SPRITEA
);
5416 tmp
= I915_READ(DSPFW3
);
5417 wm
->sr
.cursor
= _FW_WM(tmp
, CURSOR_SR
);
5419 if (IS_CHERRYVIEW(dev_priv
)) {
5420 tmp
= I915_READ(DSPFW7_CHV
);
5421 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] = _FW_WM_VLV(tmp
, SPRITED
);
5422 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] = _FW_WM_VLV(tmp
, SPRITEC
);
5424 tmp
= I915_READ(DSPFW8_CHV
);
5425 wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE1
] = _FW_WM_VLV(tmp
, SPRITEF
);
5426 wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE0
] = _FW_WM_VLV(tmp
, SPRITEE
);
5428 tmp
= I915_READ(DSPFW9_CHV
);
5429 wm
->pipe
[PIPE_C
].plane
[PLANE_PRIMARY
] = _FW_WM_VLV(tmp
, PLANEC
);
5430 wm
->pipe
[PIPE_C
].plane
[PLANE_CURSOR
] = _FW_WM(tmp
, CURSORC
);
5432 tmp
= I915_READ(DSPHOWM
);
5433 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
5434 wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITEF_HI
) << 8;
5435 wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEE_HI
) << 8;
5436 wm
->pipe
[PIPE_C
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEC_HI
) << 8;
5437 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
5438 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
5439 wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEB_HI
) << 8;
5440 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
5441 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
5442 wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEA_HI
) << 8;
5444 tmp
= I915_READ(DSPFW7
);
5445 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] = _FW_WM_VLV(tmp
, SPRITED
);
5446 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] = _FW_WM_VLV(tmp
, SPRITEC
);
5448 tmp
= I915_READ(DSPHOWM
);
5449 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
5450 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
5451 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
5452 wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEB_HI
) << 8;
5453 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
5454 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
5455 wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEA_HI
) << 8;
5462 void g4x_wm_get_hw_state(struct drm_device
*dev
)
5464 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5465 struct g4x_wm_values
*wm
= &dev_priv
->wm
.g4x
;
5466 struct intel_crtc
*crtc
;
5468 g4x_read_wm_values(dev_priv
, wm
);
5470 wm
->cxsr
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
5472 for_each_intel_crtc(dev
, crtc
) {
5473 struct intel_crtc_state
*crtc_state
=
5474 to_intel_crtc_state(crtc
->base
.state
);
5475 struct g4x_wm_state
*active
= &crtc
->wm
.active
.g4x
;
5476 struct g4x_pipe_wm
*raw
;
5477 enum pipe pipe
= crtc
->pipe
;
5478 enum plane_id plane_id
;
5479 int level
, max_level
;
5481 active
->cxsr
= wm
->cxsr
;
5482 active
->hpll_en
= wm
->hpll_en
;
5483 active
->fbc_en
= wm
->fbc_en
;
5485 active
->sr
= wm
->sr
;
5486 active
->hpll
= wm
->hpll
;
5488 for_each_plane_id_on_crtc(crtc
, plane_id
) {
5489 active
->wm
.plane
[plane_id
] =
5490 wm
->pipe
[pipe
].plane
[plane_id
];
5493 if (wm
->cxsr
&& wm
->hpll_en
)
5494 max_level
= G4X_WM_LEVEL_HPLL
;
5496 max_level
= G4X_WM_LEVEL_SR
;
5498 max_level
= G4X_WM_LEVEL_NORMAL
;
5500 level
= G4X_WM_LEVEL_NORMAL
;
5501 raw
= &crtc_state
->wm
.g4x
.raw
[level
];
5502 for_each_plane_id_on_crtc(crtc
, plane_id
)
5503 raw
->plane
[plane_id
] = active
->wm
.plane
[plane_id
];
5505 if (++level
> max_level
)
5508 raw
= &crtc_state
->wm
.g4x
.raw
[level
];
5509 raw
->plane
[PLANE_PRIMARY
] = active
->sr
.plane
;
5510 raw
->plane
[PLANE_CURSOR
] = active
->sr
.cursor
;
5511 raw
->plane
[PLANE_SPRITE0
] = 0;
5512 raw
->fbc
= active
->sr
.fbc
;
5514 if (++level
> max_level
)
5517 raw
= &crtc_state
->wm
.g4x
.raw
[level
];
5518 raw
->plane
[PLANE_PRIMARY
] = active
->hpll
.plane
;
5519 raw
->plane
[PLANE_CURSOR
] = active
->hpll
.cursor
;
5520 raw
->plane
[PLANE_SPRITE0
] = 0;
5521 raw
->fbc
= active
->hpll
.fbc
;
5524 for_each_plane_id_on_crtc(crtc
, plane_id
)
5525 g4x_raw_plane_wm_set(crtc_state
, level
,
5526 plane_id
, USHRT_MAX
);
5527 g4x_raw_fbc_wm_set(crtc_state
, level
, USHRT_MAX
);
5529 crtc_state
->wm
.g4x
.optimal
= *active
;
5530 crtc_state
->wm
.g4x
.intermediate
= *active
;
5532 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n",
5534 wm
->pipe
[pipe
].plane
[PLANE_PRIMARY
],
5535 wm
->pipe
[pipe
].plane
[PLANE_CURSOR
],
5536 wm
->pipe
[pipe
].plane
[PLANE_SPRITE0
]);
5539 DRM_DEBUG_KMS("Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n",
5540 wm
->sr
.plane
, wm
->sr
.cursor
, wm
->sr
.fbc
);
5541 DRM_DEBUG_KMS("Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n",
5542 wm
->hpll
.plane
, wm
->hpll
.cursor
, wm
->hpll
.fbc
);
5543 DRM_DEBUG_KMS("Initial SR=%s HPLL=%s FBC=%s\n",
5544 yesno(wm
->cxsr
), yesno(wm
->hpll_en
), yesno(wm
->fbc_en
));
5547 void g4x_wm_sanitize(struct drm_i915_private
*dev_priv
)
5549 struct intel_plane
*plane
;
5550 struct intel_crtc
*crtc
;
5552 mutex_lock(&dev_priv
->wm
.wm_mutex
);
5554 for_each_intel_plane(&dev_priv
->drm
, plane
) {
5555 struct intel_crtc
*crtc
=
5556 intel_get_crtc_for_pipe(dev_priv
, plane
->pipe
);
5557 struct intel_crtc_state
*crtc_state
=
5558 to_intel_crtc_state(crtc
->base
.state
);
5559 struct intel_plane_state
*plane_state
=
5560 to_intel_plane_state(plane
->base
.state
);
5561 struct g4x_wm_state
*wm_state
= &crtc_state
->wm
.g4x
.optimal
;
5562 enum plane_id plane_id
= plane
->id
;
5565 if (plane_state
->base
.visible
)
5568 for (level
= 0; level
< 3; level
++) {
5569 struct g4x_pipe_wm
*raw
=
5570 &crtc_state
->wm
.g4x
.raw
[level
];
5572 raw
->plane
[plane_id
] = 0;
5573 wm_state
->wm
.plane
[plane_id
] = 0;
5576 if (plane_id
== PLANE_PRIMARY
) {
5577 for (level
= 0; level
< 3; level
++) {
5578 struct g4x_pipe_wm
*raw
=
5579 &crtc_state
->wm
.g4x
.raw
[level
];
5583 wm_state
->sr
.fbc
= 0;
5584 wm_state
->hpll
.fbc
= 0;
5585 wm_state
->fbc_en
= false;
5589 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
5590 struct intel_crtc_state
*crtc_state
=
5591 to_intel_crtc_state(crtc
->base
.state
);
5593 crtc_state
->wm
.g4x
.intermediate
=
5594 crtc_state
->wm
.g4x
.optimal
;
5595 crtc
->wm
.active
.g4x
= crtc_state
->wm
.g4x
.optimal
;
5598 g4x_program_watermarks(dev_priv
);
5600 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
5603 void vlv_wm_get_hw_state(struct drm_device
*dev
)
5605 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5606 struct vlv_wm_values
*wm
= &dev_priv
->wm
.vlv
;
5607 struct intel_crtc
*crtc
;
5610 vlv_read_wm_values(dev_priv
, wm
);
5612 wm
->cxsr
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
5613 wm
->level
= VLV_WM_LEVEL_PM2
;
5615 if (IS_CHERRYVIEW(dev_priv
)) {
5616 mutex_lock(&dev_priv
->pcu_lock
);
5618 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5619 if (val
& DSP_MAXFIFO_PM5_ENABLE
)
5620 wm
->level
= VLV_WM_LEVEL_PM5
;
5623 * If DDR DVFS is disabled in the BIOS, Punit
5624 * will never ack the request. So if that happens
5625 * assume we don't have to enable/disable DDR DVFS
5626 * dynamically. To test that just set the REQ_ACK
5627 * bit to poke the Punit, but don't change the
5628 * HIGH/LOW bits so that we don't actually change
5629 * the current state.
5631 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
5632 val
|= FORCE_DDR_FREQ_REQ_ACK
;
5633 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
5635 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
5636 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3)) {
5637 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
5638 "assuming DDR DVFS is disabled\n");
5639 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM5
;
5641 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
5642 if ((val
& FORCE_DDR_HIGH_FREQ
) == 0)
5643 wm
->level
= VLV_WM_LEVEL_DDR_DVFS
;
5646 mutex_unlock(&dev_priv
->pcu_lock
);
5649 for_each_intel_crtc(dev
, crtc
) {
5650 struct intel_crtc_state
*crtc_state
=
5651 to_intel_crtc_state(crtc
->base
.state
);
5652 struct vlv_wm_state
*active
= &crtc
->wm
.active
.vlv
;
5653 const struct vlv_fifo_state
*fifo_state
=
5654 &crtc_state
->wm
.vlv
.fifo_state
;
5655 enum pipe pipe
= crtc
->pipe
;
5656 enum plane_id plane_id
;
5659 vlv_get_fifo_size(crtc_state
);
5661 active
->num_levels
= wm
->level
+ 1;
5662 active
->cxsr
= wm
->cxsr
;
5664 for (level
= 0; level
< active
->num_levels
; level
++) {
5665 struct g4x_pipe_wm
*raw
=
5666 &crtc_state
->wm
.vlv
.raw
[level
];
5668 active
->sr
[level
].plane
= wm
->sr
.plane
;
5669 active
->sr
[level
].cursor
= wm
->sr
.cursor
;
5671 for_each_plane_id_on_crtc(crtc
, plane_id
) {
5672 active
->wm
[level
].plane
[plane_id
] =
5673 wm
->pipe
[pipe
].plane
[plane_id
];
5675 raw
->plane
[plane_id
] =
5676 vlv_invert_wm_value(active
->wm
[level
].plane
[plane_id
],
5677 fifo_state
->plane
[plane_id
]);
5681 for_each_plane_id_on_crtc(crtc
, plane_id
)
5682 vlv_raw_plane_wm_set(crtc_state
, level
,
5683 plane_id
, USHRT_MAX
);
5684 vlv_invalidate_wms(crtc
, active
, level
);
5686 crtc_state
->wm
.vlv
.optimal
= *active
;
5687 crtc_state
->wm
.vlv
.intermediate
= *active
;
5689 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
5691 wm
->pipe
[pipe
].plane
[PLANE_PRIMARY
],
5692 wm
->pipe
[pipe
].plane
[PLANE_CURSOR
],
5693 wm
->pipe
[pipe
].plane
[PLANE_SPRITE0
],
5694 wm
->pipe
[pipe
].plane
[PLANE_SPRITE1
]);
5697 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
5698 wm
->sr
.plane
, wm
->sr
.cursor
, wm
->level
, wm
->cxsr
);
5701 void vlv_wm_sanitize(struct drm_i915_private
*dev_priv
)
5703 struct intel_plane
*plane
;
5704 struct intel_crtc
*crtc
;
5706 mutex_lock(&dev_priv
->wm
.wm_mutex
);
5708 for_each_intel_plane(&dev_priv
->drm
, plane
) {
5709 struct intel_crtc
*crtc
=
5710 intel_get_crtc_for_pipe(dev_priv
, plane
->pipe
);
5711 struct intel_crtc_state
*crtc_state
=
5712 to_intel_crtc_state(crtc
->base
.state
);
5713 struct intel_plane_state
*plane_state
=
5714 to_intel_plane_state(plane
->base
.state
);
5715 struct vlv_wm_state
*wm_state
= &crtc_state
->wm
.vlv
.optimal
;
5716 const struct vlv_fifo_state
*fifo_state
=
5717 &crtc_state
->wm
.vlv
.fifo_state
;
5718 enum plane_id plane_id
= plane
->id
;
5721 if (plane_state
->base
.visible
)
5724 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
5725 struct g4x_pipe_wm
*raw
=
5726 &crtc_state
->wm
.vlv
.raw
[level
];
5728 raw
->plane
[plane_id
] = 0;
5730 wm_state
->wm
[level
].plane
[plane_id
] =
5731 vlv_invert_wm_value(raw
->plane
[plane_id
],
5732 fifo_state
->plane
[plane_id
]);
5736 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
5737 struct intel_crtc_state
*crtc_state
=
5738 to_intel_crtc_state(crtc
->base
.state
);
5740 crtc_state
->wm
.vlv
.intermediate
=
5741 crtc_state
->wm
.vlv
.optimal
;
5742 crtc
->wm
.active
.vlv
= crtc_state
->wm
.vlv
.optimal
;
5745 vlv_program_watermarks(dev_priv
);
5747 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
5751 * FIXME should probably kill this and improve
5752 * the real watermark readout/sanitation instead
5754 static void ilk_init_lp_watermarks(struct drm_i915_private
*dev_priv
)
5756 I915_WRITE(WM3_LP_ILK
, I915_READ(WM3_LP_ILK
) & ~WM1_LP_SR_EN
);
5757 I915_WRITE(WM2_LP_ILK
, I915_READ(WM2_LP_ILK
) & ~WM1_LP_SR_EN
);
5758 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
5761 * Don't touch WM1S_LP_EN here.
5762 * Doing so could cause underruns.
5766 void ilk_wm_get_hw_state(struct drm_device
*dev
)
5768 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5769 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
5770 struct drm_crtc
*crtc
;
5772 ilk_init_lp_watermarks(dev_priv
);
5774 for_each_crtc(dev
, crtc
)
5775 ilk_pipe_wm_get_hw_state(crtc
);
5777 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
5778 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
5779 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
5781 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
5782 if (INTEL_GEN(dev_priv
) >= 7) {
5783 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
5784 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
5787 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5788 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
5789 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
5790 else if (IS_IVYBRIDGE(dev_priv
))
5791 hw
->partitioning
= (I915_READ(DISP_ARB_CTL2
) & DISP_DATA_PARTITION_5_6
) ?
5792 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
5795 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
5799 * intel_update_watermarks - update FIFO watermark values based on current modes
5801 * Calculate watermark values for the various WM regs based on current mode
5802 * and plane configuration.
5804 * There are several cases to deal with here:
5805 * - normal (i.e. non-self-refresh)
5806 * - self-refresh (SR) mode
5807 * - lines are large relative to FIFO size (buffer can hold up to 2)
5808 * - lines are small relative to FIFO size (buffer can hold more than 2
5809 * lines), so need to account for TLB latency
5811 * The normal calculation is:
5812 * watermark = dotclock * bytes per pixel * latency
5813 * where latency is platform & configuration dependent (we assume pessimal
5816 * The SR calculation is:
5817 * watermark = (trunc(latency/line time)+1) * surface width *
5820 * line time = htotal / dotclock
5821 * surface width = hdisplay for normal plane and 64 for cursor
5822 * and latency is assumed to be high, as above.
5824 * The final value programmed to the register should always be rounded up,
5825 * and include an extra 2 entries to account for clock crossings.
5827 * We don't use the sprite, so we can ignore that. And on Crestline we have
5828 * to set the non-SR watermarks to 8.
5830 void intel_update_watermarks(struct intel_crtc
*crtc
)
5832 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5834 if (dev_priv
->display
.update_wm
)
5835 dev_priv
->display
.update_wm(crtc
);
5838 void intel_enable_ipc(struct drm_i915_private
*dev_priv
)
5842 /* Display WA #0477 WaDisableIPC: skl */
5843 if (IS_SKYLAKE(dev_priv
)) {
5844 dev_priv
->ipc_enabled
= false;
5848 val
= I915_READ(DISP_ARB_CTL2
);
5850 if (dev_priv
->ipc_enabled
)
5851 val
|= DISP_IPC_ENABLE
;
5853 val
&= ~DISP_IPC_ENABLE
;
5855 I915_WRITE(DISP_ARB_CTL2
, val
);
5858 void intel_init_ipc(struct drm_i915_private
*dev_priv
)
5860 dev_priv
->ipc_enabled
= false;
5861 if (!HAS_IPC(dev_priv
))
5864 dev_priv
->ipc_enabled
= true;
5865 intel_enable_ipc(dev_priv
);
5869 * Lock protecting IPS related data structures
5871 DEFINE_SPINLOCK(mchdev_lock
);
5873 /* Global for IPS driver to get at the current i915 device. Protected by
5875 static struct drm_i915_private
*i915_mch_dev
;
5877 bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
)
5881 lockdep_assert_held(&mchdev_lock
);
5883 rgvswctl
= I915_READ16(MEMSWCTL
);
5884 if (rgvswctl
& MEMCTL_CMD_STS
) {
5885 DRM_DEBUG("gpu busy, RCS change rejected\n");
5886 return false; /* still busy with another command */
5889 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
5890 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
5891 I915_WRITE16(MEMSWCTL
, rgvswctl
);
5892 POSTING_READ16(MEMSWCTL
);
5894 rgvswctl
|= MEMCTL_CMD_STS
;
5895 I915_WRITE16(MEMSWCTL
, rgvswctl
);
5900 static void ironlake_enable_drps(struct drm_i915_private
*dev_priv
)
5903 u8 fmax
, fmin
, fstart
, vstart
;
5905 spin_lock_irq(&mchdev_lock
);
5907 rgvmodectl
= I915_READ(MEMMODECTL
);
5909 /* Enable temp reporting */
5910 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
5911 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
5913 /* 100ms RC evaluation intervals */
5914 I915_WRITE(RCUPEI
, 100000);
5915 I915_WRITE(RCDNEI
, 100000);
5917 /* Set max/min thresholds to 90ms and 80ms respectively */
5918 I915_WRITE(RCBMAXAVG
, 90000);
5919 I915_WRITE(RCBMINAVG
, 80000);
5921 I915_WRITE(MEMIHYST
, 1);
5923 /* Set up min, max, and cur for interrupt handling */
5924 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
5925 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
5926 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
5927 MEMMODE_FSTART_SHIFT
;
5929 vstart
= (I915_READ(PXVFREQ(fstart
)) & PXVFREQ_PX_MASK
) >>
5932 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
5933 dev_priv
->ips
.fstart
= fstart
;
5935 dev_priv
->ips
.max_delay
= fstart
;
5936 dev_priv
->ips
.min_delay
= fmin
;
5937 dev_priv
->ips
.cur_delay
= fstart
;
5939 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5940 fmax
, fmin
, fstart
);
5942 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
5945 * Interrupts will be enabled in ironlake_irq_postinstall
5948 I915_WRITE(VIDSTART
, vstart
);
5949 POSTING_READ(VIDSTART
);
5951 rgvmodectl
|= MEMMODE_SWMODE_EN
;
5952 I915_WRITE(MEMMODECTL
, rgvmodectl
);
5954 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
5955 DRM_ERROR("stuck trying to change perf mode\n");
5958 ironlake_set_drps(dev_priv
, fstart
);
5960 dev_priv
->ips
.last_count1
= I915_READ(DMIEC
) +
5961 I915_READ(DDREC
) + I915_READ(CSIEC
);
5962 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
5963 dev_priv
->ips
.last_count2
= I915_READ(GFXEC
);
5964 dev_priv
->ips
.last_time2
= ktime_get_raw_ns();
5966 spin_unlock_irq(&mchdev_lock
);
5969 static void ironlake_disable_drps(struct drm_i915_private
*dev_priv
)
5973 spin_lock_irq(&mchdev_lock
);
5975 rgvswctl
= I915_READ16(MEMSWCTL
);
5977 /* Ack interrupts, disable EFC interrupt */
5978 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
5979 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
5980 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
5981 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
5982 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
5984 /* Go back to the starting frequency */
5985 ironlake_set_drps(dev_priv
, dev_priv
->ips
.fstart
);
5987 rgvswctl
|= MEMCTL_CMD_STS
;
5988 I915_WRITE(MEMSWCTL
, rgvswctl
);
5991 spin_unlock_irq(&mchdev_lock
);
5994 /* There's a funny hw issue where the hw returns all 0 when reading from
5995 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
5996 * ourselves, instead of doing a rmw cycle (which might result in us clearing
5997 * all limits and the gpu stuck at whatever frequency it is at atm).
5999 static u32
intel_rps_limits(struct drm_i915_private
*dev_priv
, u8 val
)
6001 struct intel_rps
*rps
= &dev_priv
->gt_pm
.rps
;
6004 /* Only set the down limit when we've reached the lowest level to avoid
6005 * getting more interrupts, otherwise leave this clear. This prevents a
6006 * race in the hw when coming out of rc6: There's a tiny window where
6007 * the hw runs at the minimal clock before selecting the desired
6008 * frequency, if the down threshold expires in that window we will not
6009 * receive a down interrupt. */
6010 if (INTEL_GEN(dev_priv
) >= 9) {
6011 limits
= (rps
->max_freq_softlimit
) << 23;
6012 if (val
<= rps
->min_freq_softlimit
)
6013 limits
|= (rps
->min_freq_softlimit
) << 14;
6015 limits
= rps
->max_freq_softlimit
<< 24;
6016 if (val
<= rps
->min_freq_softlimit
)
6017 limits
|= rps
->min_freq_softlimit
<< 16;
6023 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
6025 struct intel_rps
*rps
= &dev_priv
->gt_pm
.rps
;
6027 u32 threshold_up
= 0, threshold_down
= 0; /* in % */
6028 u32 ei_up
= 0, ei_down
= 0;
6030 new_power
= rps
->power
;
6031 switch (rps
->power
) {
6033 if (val
> rps
->efficient_freq
+ 1 &&
6034 val
> rps
->cur_freq
)
6035 new_power
= BETWEEN
;
6039 if (val
<= rps
->efficient_freq
&&
6040 val
< rps
->cur_freq
)
6041 new_power
= LOW_POWER
;
6042 else if (val
>= rps
->rp0_freq
&&
6043 val
> rps
->cur_freq
)
6044 new_power
= HIGH_POWER
;
6048 if (val
< (rps
->rp1_freq
+ rps
->rp0_freq
) >> 1 &&
6049 val
< rps
->cur_freq
)
6050 new_power
= BETWEEN
;
6053 /* Max/min bins are special */
6054 if (val
<= rps
->min_freq_softlimit
)
6055 new_power
= LOW_POWER
;
6056 if (val
>= rps
->max_freq_softlimit
)
6057 new_power
= HIGH_POWER
;
6058 if (new_power
== rps
->power
)
6061 /* Note the units here are not exactly 1us, but 1280ns. */
6062 switch (new_power
) {
6064 /* Upclock if more than 95% busy over 16ms */
6068 /* Downclock if less than 85% busy over 32ms */
6070 threshold_down
= 85;
6074 /* Upclock if more than 90% busy over 13ms */
6078 /* Downclock if less than 75% busy over 32ms */
6080 threshold_down
= 75;
6084 /* Upclock if more than 85% busy over 10ms */
6088 /* Downclock if less than 60% busy over 32ms */
6090 threshold_down
= 60;
6094 /* When byt can survive without system hang with dynamic
6095 * sw freq adjustments, this restriction can be lifted.
6097 if (IS_VALLEYVIEW(dev_priv
))
6100 I915_WRITE(GEN6_RP_UP_EI
,
6101 GT_INTERVAL_FROM_US(dev_priv
, ei_up
));
6102 I915_WRITE(GEN6_RP_UP_THRESHOLD
,
6103 GT_INTERVAL_FROM_US(dev_priv
,
6104 ei_up
* threshold_up
/ 100));
6106 I915_WRITE(GEN6_RP_DOWN_EI
,
6107 GT_INTERVAL_FROM_US(dev_priv
, ei_down
));
6108 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
,
6109 GT_INTERVAL_FROM_US(dev_priv
,
6110 ei_down
* threshold_down
/ 100));
6112 I915_WRITE(GEN6_RP_CONTROL
,
6113 GEN6_RP_MEDIA_TURBO
|
6114 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
6115 GEN6_RP_MEDIA_IS_GFX
|
6117 GEN6_RP_UP_BUSY_AVG
|
6118 GEN6_RP_DOWN_IDLE_AVG
);
6121 rps
->power
= new_power
;
6122 rps
->up_threshold
= threshold_up
;
6123 rps
->down_threshold
= threshold_down
;
6127 static u32
gen6_rps_pm_mask(struct drm_i915_private
*dev_priv
, u8 val
)
6129 struct intel_rps
*rps
= &dev_priv
->gt_pm
.rps
;
6132 /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
6133 if (val
> rps
->min_freq_softlimit
)
6134 mask
|= GEN6_PM_RP_UP_EI_EXPIRED
| GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT
;
6135 if (val
< rps
->max_freq_softlimit
)
6136 mask
|= GEN6_PM_RP_UP_EI_EXPIRED
| GEN6_PM_RP_UP_THRESHOLD
;
6138 mask
&= dev_priv
->pm_rps_events
;
6140 return gen6_sanitize_rps_pm_mask(dev_priv
, ~mask
);
6143 /* gen6_set_rps is called to update the frequency request, but should also be
6144 * called when the range (min_delay and max_delay) is modified so that we can
6145 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
6146 static int gen6_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
6148 struct intel_rps
*rps
= &dev_priv
->gt_pm
.rps
;
6150 /* min/max delay may still have been modified so be sure to
6151 * write the limits value.
6153 if (val
!= rps
->cur_freq
) {
6154 gen6_set_rps_thresholds(dev_priv
, val
);
6156 if (INTEL_GEN(dev_priv
) >= 9)
6157 I915_WRITE(GEN6_RPNSWREQ
,
6158 GEN9_FREQUENCY(val
));
6159 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
6160 I915_WRITE(GEN6_RPNSWREQ
,
6161 HSW_FREQUENCY(val
));
6163 I915_WRITE(GEN6_RPNSWREQ
,
6164 GEN6_FREQUENCY(val
) |
6166 GEN6_AGGRESSIVE_TURBO
);
6169 /* Make sure we continue to get interrupts
6170 * until we hit the minimum or maximum frequencies.
6172 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, intel_rps_limits(dev_priv
, val
));
6173 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
6175 rps
->cur_freq
= val
;
6176 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
6181 static int valleyview_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
6185 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv
) && (val
& 1),
6186 "Odd GPU freq value\n"))
6189 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
6191 if (val
!= dev_priv
->gt_pm
.rps
.cur_freq
) {
6192 err
= vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
6196 gen6_set_rps_thresholds(dev_priv
, val
);
6199 dev_priv
->gt_pm
.rps
.cur_freq
= val
;
6200 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
6205 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
6207 * * If Gfx is Idle, then
6208 * 1. Forcewake Media well.
6209 * 2. Request idle freq.
6210 * 3. Release Forcewake of Media well.
6212 static void vlv_set_rps_idle(struct drm_i915_private
*dev_priv
)
6214 struct intel_rps
*rps
= &dev_priv
->gt_pm
.rps
;
6215 u32 val
= rps
->idle_freq
;
6218 if (rps
->cur_freq
<= val
)
6221 /* The punit delays the write of the frequency and voltage until it
6222 * determines the GPU is awake. During normal usage we don't want to
6223 * waste power changing the frequency if the GPU is sleeping (rc6).
6224 * However, the GPU and driver is now idle and we do not want to delay
6225 * switching to minimum voltage (reducing power whilst idle) as we do
6226 * not expect to be woken in the near future and so must flush the
6227 * change by waking the device.
6229 * We choose to take the media powerwell (either would do to trick the
6230 * punit into committing the voltage change) as that takes a lot less
6231 * power than the render powerwell.
6233 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_MEDIA
);
6234 err
= valleyview_set_rps(dev_priv
, val
);
6235 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_MEDIA
);
6238 DRM_ERROR("Failed to set RPS for idle\n");
6241 void gen6_rps_busy(struct drm_i915_private
*dev_priv
)
6243 struct intel_rps
*rps
= &dev_priv
->gt_pm
.rps
;
6245 mutex_lock(&dev_priv
->pcu_lock
);
6249 if (dev_priv
->pm_rps_events
& GEN6_PM_RP_UP_EI_EXPIRED
)
6250 gen6_rps_reset_ei(dev_priv
);
6251 I915_WRITE(GEN6_PMINTRMSK
,
6252 gen6_rps_pm_mask(dev_priv
, rps
->cur_freq
));
6254 gen6_enable_rps_interrupts(dev_priv
);
6256 /* Use the user's desired frequency as a guide, but for better
6257 * performance, jump directly to RPe as our starting frequency.
6259 freq
= max(rps
->cur_freq
,
6260 rps
->efficient_freq
);
6262 if (intel_set_rps(dev_priv
,
6264 rps
->min_freq_softlimit
,
6265 rps
->max_freq_softlimit
)))
6266 DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
6268 mutex_unlock(&dev_priv
->pcu_lock
);
6271 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
6273 struct intel_rps
*rps
= &dev_priv
->gt_pm
.rps
;
6275 /* Flush our bottom-half so that it does not race with us
6276 * setting the idle frequency and so that it is bounded by
6277 * our rpm wakeref. And then disable the interrupts to stop any
6278 * futher RPS reclocking whilst we are asleep.
6280 gen6_disable_rps_interrupts(dev_priv
);
6282 mutex_lock(&dev_priv
->pcu_lock
);
6284 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
6285 vlv_set_rps_idle(dev_priv
);
6287 gen6_set_rps(dev_priv
, rps
->idle_freq
);
6289 I915_WRITE(GEN6_PMINTRMSK
,
6290 gen6_sanitize_rps_pm_mask(dev_priv
, ~0));
6292 mutex_unlock(&dev_priv
->pcu_lock
);
6295 void gen6_rps_boost(struct drm_i915_gem_request
*rq
,
6296 struct intel_rps_client
*rps_client
)
6298 struct intel_rps
*rps
= &rq
->i915
->gt_pm
.rps
;
6299 unsigned long flags
;
6302 /* This is intentionally racy! We peek at the state here, then
6303 * validate inside the RPS worker.
6309 spin_lock_irqsave(&rq
->lock
, flags
);
6310 if (!rq
->waitboost
&& !i915_gem_request_completed(rq
)) {
6311 atomic_inc(&rps
->num_waiters
);
6312 rq
->waitboost
= true;
6315 spin_unlock_irqrestore(&rq
->lock
, flags
);
6319 if (READ_ONCE(rps
->cur_freq
) < rps
->boost_freq
)
6320 schedule_work(&rps
->work
);
6322 atomic_inc(rps_client
? &rps_client
->boosts
: &rps
->boosts
);
6325 int intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
6327 struct intel_rps
*rps
= &dev_priv
->gt_pm
.rps
;
6330 lockdep_assert_held(&dev_priv
->pcu_lock
);
6331 GEM_BUG_ON(val
> rps
->max_freq
);
6332 GEM_BUG_ON(val
< rps
->min_freq
);
6334 if (!rps
->enabled
) {
6335 rps
->cur_freq
= val
;
6339 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
6340 err
= valleyview_set_rps(dev_priv
, val
);
6342 err
= gen6_set_rps(dev_priv
, val
);
6347 static void gen9_disable_rc6(struct drm_i915_private
*dev_priv
)
6349 I915_WRITE(GEN6_RC_CONTROL
, 0);
6350 I915_WRITE(GEN9_PG_ENABLE
, 0);
6353 static void gen9_disable_rps(struct drm_i915_private
*dev_priv
)
6355 I915_WRITE(GEN6_RP_CONTROL
, 0);
6358 static void gen6_disable_rc6(struct drm_i915_private
*dev_priv
)
6360 I915_WRITE(GEN6_RC_CONTROL
, 0);
6363 static void gen6_disable_rps(struct drm_i915_private
*dev_priv
)
6365 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
6366 I915_WRITE(GEN6_RP_CONTROL
, 0);
6369 static void cherryview_disable_rc6(struct drm_i915_private
*dev_priv
)
6371 I915_WRITE(GEN6_RC_CONTROL
, 0);
6374 static void cherryview_disable_rps(struct drm_i915_private
*dev_priv
)
6376 I915_WRITE(GEN6_RP_CONTROL
, 0);
6379 static void valleyview_disable_rc6(struct drm_i915_private
*dev_priv
)
6381 /* We're doing forcewake before Disabling RC6,
6382 * This what the BIOS expects when going into suspend */
6383 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6385 I915_WRITE(GEN6_RC_CONTROL
, 0);
6387 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6390 static void valleyview_disable_rps(struct drm_i915_private
*dev_priv
)
6392 I915_WRITE(GEN6_RP_CONTROL
, 0);
6395 static void intel_print_rc6_info(struct drm_i915_private
*dev_priv
, u32 mode
)
6397 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
6398 if (mode
& (GEN7_RC_CTL_TO_MODE
| GEN6_RC_CTL_EI_MODE(1)))
6399 mode
= GEN6_RC_CTL_RC6_ENABLE
;
6403 if (HAS_RC6p(dev_priv
))
6404 DRM_DEBUG_DRIVER("Enabling RC6 states: "
6405 "RC6 %s RC6p %s RC6pp %s\n",
6406 onoff(mode
& GEN6_RC_CTL_RC6_ENABLE
),
6407 onoff(mode
& GEN6_RC_CTL_RC6p_ENABLE
),
6408 onoff(mode
& GEN6_RC_CTL_RC6pp_ENABLE
));
6411 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
6412 onoff(mode
& GEN6_RC_CTL_RC6_ENABLE
));
6415 static bool bxt_check_bios_rc6_setup(struct drm_i915_private
*dev_priv
)
6417 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
6418 bool enable_rc6
= true;
6419 unsigned long rc6_ctx_base
;
6423 rc_ctl
= I915_READ(GEN6_RC_CONTROL
);
6424 rc_sw_target
= (I915_READ(GEN6_RC_STATE
) & RC_SW_TARGET_STATE_MASK
) >>
6425 RC_SW_TARGET_STATE_SHIFT
;
6426 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
6427 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
6428 onoff(rc_ctl
& GEN6_RC_CTL_HW_ENABLE
),
6429 onoff(rc_ctl
& GEN6_RC_CTL_RC6_ENABLE
),
6432 if (!(I915_READ(RC6_LOCATION
) & RC6_CTX_IN_DRAM
)) {
6433 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
6438 * The exact context size is not known for BXT, so assume a page size
6441 rc6_ctx_base
= I915_READ(RC6_CTX_BASE
) & RC6_CTX_BASE_MASK
;
6442 if (!((rc6_ctx_base
>= ggtt
->stolen_reserved_base
) &&
6443 (rc6_ctx_base
+ PAGE_SIZE
<= ggtt
->stolen_reserved_base
+
6444 ggtt
->stolen_reserved_size
))) {
6445 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
6449 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT
) & IDLE_TIME_MASK
) > 1) &&
6450 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0
) & IDLE_TIME_MASK
) > 1) &&
6451 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT
) & IDLE_TIME_MASK
) > 1) &&
6452 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT
) & IDLE_TIME_MASK
) > 1))) {
6453 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
6457 if (!I915_READ(GEN8_PUSHBUS_CONTROL
) ||
6458 !I915_READ(GEN8_PUSHBUS_ENABLE
) ||
6459 !I915_READ(GEN8_PUSHBUS_SHIFT
)) {
6460 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
6464 if (!I915_READ(GEN6_GFXPAUSE
)) {
6465 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
6469 if (!I915_READ(GEN8_MISC_CTRL0
)) {
6470 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
6477 int sanitize_rc6_option(struct drm_i915_private
*dev_priv
, int enable_rc6
)
6479 /* No RC6 before Ironlake and code is gone for ilk. */
6480 if (INTEL_INFO(dev_priv
)->gen
< 6)
6486 if (IS_GEN9_LP(dev_priv
) && !bxt_check_bios_rc6_setup(dev_priv
)) {
6487 DRM_INFO("RC6 disabled by BIOS\n");
6491 /* Respect the kernel parameter if it is set */
6492 if (enable_rc6
>= 0) {
6495 if (HAS_RC6p(dev_priv
))
6496 mask
= INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
|
6499 mask
= INTEL_RC6_ENABLE
;
6501 if ((enable_rc6
& mask
) != enable_rc6
)
6502 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
6503 "(requested %d, valid %d)\n",
6504 enable_rc6
& mask
, enable_rc6
, mask
);
6506 return enable_rc6
& mask
;
6509 if (IS_IVYBRIDGE(dev_priv
))
6510 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
6512 return INTEL_RC6_ENABLE
;
6515 static void gen6_init_rps_frequencies(struct drm_i915_private
*dev_priv
)
6517 struct intel_rps
*rps
= &dev_priv
->gt_pm
.rps
;
6519 /* All of these values are in units of 50MHz */
6521 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
6522 if (IS_GEN9_LP(dev_priv
)) {
6523 u32 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
6524 rps
->rp0_freq
= (rp_state_cap
>> 16) & 0xff;
6525 rps
->rp1_freq
= (rp_state_cap
>> 8) & 0xff;
6526 rps
->min_freq
= (rp_state_cap
>> 0) & 0xff;
6528 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
6529 rps
->rp0_freq
= (rp_state_cap
>> 0) & 0xff;
6530 rps
->rp1_freq
= (rp_state_cap
>> 8) & 0xff;
6531 rps
->min_freq
= (rp_state_cap
>> 16) & 0xff;
6533 /* hw_max = RP0 until we check for overclocking */
6534 rps
->max_freq
= rps
->rp0_freq
;
6536 rps
->efficient_freq
= rps
->rp1_freq
;
6537 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
) ||
6538 IS_GEN9_BC(dev_priv
) || IS_CANNONLAKE(dev_priv
)) {
6539 u32 ddcc_status
= 0;
6541 if (sandybridge_pcode_read(dev_priv
,
6542 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL
,
6544 rps
->efficient_freq
=
6546 ((ddcc_status
>> 8) & 0xff),
6551 if (IS_GEN9_BC(dev_priv
) || IS_CANNONLAKE(dev_priv
)) {
6552 /* Store the frequency values in 16.66 MHZ units, which is
6553 * the natural hardware unit for SKL
6555 rps
->rp0_freq
*= GEN9_FREQ_SCALER
;
6556 rps
->rp1_freq
*= GEN9_FREQ_SCALER
;
6557 rps
->min_freq
*= GEN9_FREQ_SCALER
;
6558 rps
->max_freq
*= GEN9_FREQ_SCALER
;
6559 rps
->efficient_freq
*= GEN9_FREQ_SCALER
;
6563 static void reset_rps(struct drm_i915_private
*dev_priv
,
6564 int (*set
)(struct drm_i915_private
*, u8
))
6566 struct intel_rps
*rps
= &dev_priv
->gt_pm
.rps
;
6567 u8 freq
= rps
->cur_freq
;
6573 if (set(dev_priv
, freq
))
6574 DRM_ERROR("Failed to reset RPS to initial values\n");
6577 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
6578 static void gen9_enable_rps(struct drm_i915_private
*dev_priv
)
6580 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6582 /* Program defaults and thresholds for RPS*/
6583 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
6584 GEN9_FREQUENCY(dev_priv
->gt_pm
.rps
.rp1_freq
));
6586 /* 1 second timeout*/
6587 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,
6588 GT_INTERVAL_FROM_US(dev_priv
, 1000000));
6590 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 0xa);
6592 /* Leaning on the below call to gen6_set_rps to program/setup the
6593 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
6594 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
6595 reset_rps(dev_priv
, gen6_set_rps
);
6597 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6600 static void gen9_enable_rc6(struct drm_i915_private
*dev_priv
)
6602 struct intel_engine_cs
*engine
;
6603 enum intel_engine_id id
;
6604 u32 rc6_mode
, rc6_mask
= 0;
6606 /* 1a: Software RC state - RC0 */
6607 I915_WRITE(GEN6_RC_STATE
, 0);
6609 /* 1b: Get forcewake during program sequence. Although the driver
6610 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6611 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6613 /* 2a: Disable RC states. */
6614 I915_WRITE(GEN6_RC_CONTROL
, 0);
6616 /* 2b: Program RC6 thresholds.*/
6618 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
6619 if (IS_SKYLAKE(dev_priv
))
6620 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 108 << 16);
6622 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 54 << 16);
6623 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
6624 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
6625 for_each_engine(engine
, dev_priv
, id
)
6626 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
6628 if (HAS_GUC(dev_priv
))
6629 I915_WRITE(GUC_MAX_IDLE_COUNT
, 0xA);
6631 I915_WRITE(GEN6_RC_SLEEP
, 0);
6633 /* 2c: Program Coarse Power Gating Policies. */
6634 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS
, 25);
6635 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS
, 25);
6637 /* 3a: Enable RC6 */
6638 if (intel_rc6_enabled() & INTEL_RC6_ENABLE
)
6639 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
6640 DRM_INFO("RC6 %s\n", onoff(rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
));
6641 I915_WRITE(GEN6_RC6_THRESHOLD
, 37500); /* 37.5/125ms per EI */
6643 /* WaRsUseTimeoutMode:cnl (pre-prod) */
6644 if (IS_CNL_REVID(dev_priv
, CNL_REVID_A0
, CNL_REVID_C0
))
6645 rc6_mode
= GEN7_RC_CTL_TO_MODE
;
6647 rc6_mode
= GEN6_RC_CTL_EI_MODE(1);
6649 I915_WRITE(GEN6_RC_CONTROL
,
6650 GEN6_RC_CTL_HW_ENABLE
| rc6_mode
| rc6_mask
);
6653 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
6654 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
6656 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv
))
6657 I915_WRITE(GEN9_PG_ENABLE
, 0);
6659 I915_WRITE(GEN9_PG_ENABLE
, (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ?
6660 (GEN9_RENDER_PG_ENABLE
| GEN9_MEDIA_PG_ENABLE
) : 0);
6662 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6665 static void gen8_enable_rc6(struct drm_i915_private
*dev_priv
)
6667 struct intel_engine_cs
*engine
;
6668 enum intel_engine_id id
;
6669 uint32_t rc6_mask
= 0;
6671 /* 1a: Software RC state - RC0 */
6672 I915_WRITE(GEN6_RC_STATE
, 0);
6674 /* 1b: Get forcewake during program sequence. Although the driver
6675 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6676 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6678 /* 2a: Disable RC states. */
6679 I915_WRITE(GEN6_RC_CONTROL
, 0);
6681 /* 2b: Program RC6 thresholds.*/
6682 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
6683 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
6684 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
6685 for_each_engine(engine
, dev_priv
, id
)
6686 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
6687 I915_WRITE(GEN6_RC_SLEEP
, 0);
6688 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us/1.28 for TO */
6691 if (intel_rc6_enabled() & INTEL_RC6_ENABLE
)
6692 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
6693 intel_print_rc6_info(dev_priv
, rc6_mask
);
6695 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
6696 GEN7_RC_CTL_TO_MODE
|
6699 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6702 static void gen8_enable_rps(struct drm_i915_private
*dev_priv
)
6704 struct intel_rps
*rps
= &dev_priv
->gt_pm
.rps
;
6706 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6708 /* 1 Program defaults and thresholds for RPS*/
6709 I915_WRITE(GEN6_RPNSWREQ
,
6710 HSW_FREQUENCY(rps
->rp1_freq
));
6711 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
6712 HSW_FREQUENCY(rps
->rp1_freq
));
6713 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
6714 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 100000000 / 128); /* 1 second timeout */
6716 /* Docs recommend 900MHz, and 300 MHz respectively */
6717 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
6718 rps
->max_freq_softlimit
<< 24 |
6719 rps
->min_freq_softlimit
<< 16);
6721 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 7600000 / 128); /* 76ms busyness per EI, 90% */
6722 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 31300000 / 128); /* 313ms busyness per EI, 70%*/
6723 I915_WRITE(GEN6_RP_UP_EI
, 66000); /* 84.48ms, XXX: random? */
6724 I915_WRITE(GEN6_RP_DOWN_EI
, 350000); /* 448ms, XXX: random? */
6726 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
6729 I915_WRITE(GEN6_RP_CONTROL
,
6730 GEN6_RP_MEDIA_TURBO
|
6731 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
6732 GEN6_RP_MEDIA_IS_GFX
|
6734 GEN6_RP_UP_BUSY_AVG
|
6735 GEN6_RP_DOWN_IDLE_AVG
);
6737 reset_rps(dev_priv
, gen6_set_rps
);
6739 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6742 static void gen6_enable_rc6(struct drm_i915_private
*dev_priv
)
6744 struct intel_engine_cs
*engine
;
6745 enum intel_engine_id id
;
6746 u32 rc6vids
, rc6_mask
= 0;
6751 I915_WRITE(GEN6_RC_STATE
, 0);
6753 /* Clear the DBG now so we don't confuse earlier errors */
6754 gtfifodbg
= I915_READ(GTFIFODBG
);
6756 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
6757 I915_WRITE(GTFIFODBG
, gtfifodbg
);
6760 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6762 /* disable the counters and set deterministic thresholds */
6763 I915_WRITE(GEN6_RC_CONTROL
, 0);
6765 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
6766 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
6767 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
6768 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
6769 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
6771 for_each_engine(engine
, dev_priv
, id
)
6772 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
6774 I915_WRITE(GEN6_RC_SLEEP
, 0);
6775 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
6776 if (IS_IVYBRIDGE(dev_priv
))
6777 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
6779 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
6780 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
6781 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
6783 /* Check if we are enabling RC6 */
6784 rc6_mode
= intel_rc6_enabled();
6785 if (rc6_mode
& INTEL_RC6_ENABLE
)
6786 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
6788 /* We don't use those on Haswell */
6789 if (!IS_HASWELL(dev_priv
)) {
6790 if (rc6_mode
& INTEL_RC6p_ENABLE
)
6791 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
6793 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
6794 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
6797 intel_print_rc6_info(dev_priv
, rc6_mask
);
6799 I915_WRITE(GEN6_RC_CONTROL
,
6801 GEN6_RC_CTL_EI_MODE(1) |
6802 GEN6_RC_CTL_HW_ENABLE
);
6805 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
6806 if (IS_GEN6(dev_priv
) && ret
) {
6807 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
6808 } else if (IS_GEN6(dev_priv
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
6809 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
6810 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
6811 rc6vids
&= 0xffff00;
6812 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
6813 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
6815 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
6818 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6821 static void gen6_enable_rps(struct drm_i915_private
*dev_priv
)
6823 /* Here begins a magic sequence of register writes to enable
6824 * auto-downclocking.
6826 * Perhaps there might be some value in exposing these to
6829 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6831 /* Power down if completely idle for over 50ms */
6832 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
6833 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
6835 reset_rps(dev_priv
, gen6_set_rps
);
6837 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6840 static void gen6_update_ring_freq(struct drm_i915_private
*dev_priv
)
6842 struct intel_rps
*rps
= &dev_priv
->gt_pm
.rps
;
6844 unsigned int gpu_freq
;
6845 unsigned int max_ia_freq
, min_ring_freq
;
6846 unsigned int max_gpu_freq
, min_gpu_freq
;
6847 int scaling_factor
= 180;
6848 struct cpufreq_policy
*policy
;
6850 WARN_ON(!mutex_is_locked(&dev_priv
->pcu_lock
));
6852 policy
= cpufreq_cpu_get(0);
6854 max_ia_freq
= policy
->cpuinfo
.max_freq
;
6855 cpufreq_cpu_put(policy
);
6858 * Default to measured freq if none found, PCU will ensure we
6861 max_ia_freq
= tsc_khz
;
6864 /* Convert from kHz to MHz */
6865 max_ia_freq
/= 1000;
6867 min_ring_freq
= I915_READ(DCLK
) & 0xf;
6868 /* convert DDR frequency from units of 266.6MHz to bandwidth */
6869 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
6871 if (IS_GEN9_BC(dev_priv
) || IS_CANNONLAKE(dev_priv
)) {
6872 /* Convert GT frequency to 50 HZ units */
6873 min_gpu_freq
= rps
->min_freq
/ GEN9_FREQ_SCALER
;
6874 max_gpu_freq
= rps
->max_freq
/ GEN9_FREQ_SCALER
;
6876 min_gpu_freq
= rps
->min_freq
;
6877 max_gpu_freq
= rps
->max_freq
;
6881 * For each potential GPU frequency, load a ring frequency we'd like
6882 * to use for memory access. We do this by specifying the IA frequency
6883 * the PCU should use as a reference to determine the ring frequency.
6885 for (gpu_freq
= max_gpu_freq
; gpu_freq
>= min_gpu_freq
; gpu_freq
--) {
6886 int diff
= max_gpu_freq
- gpu_freq
;
6887 unsigned int ia_freq
= 0, ring_freq
= 0;
6889 if (IS_GEN9_BC(dev_priv
) || IS_CANNONLAKE(dev_priv
)) {
6891 * ring_freq = 2 * GT. ring_freq is in 100MHz units
6892 * No floor required for ring frequency on SKL.
6894 ring_freq
= gpu_freq
;
6895 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
6896 /* max(2 * GT, DDR). NB: GT is 50MHz units */
6897 ring_freq
= max(min_ring_freq
, gpu_freq
);
6898 } else if (IS_HASWELL(dev_priv
)) {
6899 ring_freq
= mult_frac(gpu_freq
, 5, 4);
6900 ring_freq
= max(min_ring_freq
, ring_freq
);
6901 /* leave ia_freq as the default, chosen by cpufreq */
6903 /* On older processors, there is no separate ring
6904 * clock domain, so in order to boost the bandwidth
6905 * of the ring, we need to upclock the CPU (ia_freq).
6907 * For GPU frequencies less than 750MHz,
6908 * just use the lowest ring freq.
6910 if (gpu_freq
< min_freq
)
6913 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
6914 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
6917 sandybridge_pcode_write(dev_priv
,
6918 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
6919 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
6920 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
6925 static int cherryview_rps_max_freq(struct drm_i915_private
*dev_priv
)
6929 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
6931 switch (INTEL_INFO(dev_priv
)->sseu
.eu_total
) {
6933 /* (2 * 4) config */
6934 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT
);
6937 /* (2 * 6) config */
6938 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT
);
6941 /* (2 * 8) config */
6943 /* Setting (2 * 8) Min RP0 for any other combination */
6944 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT
);
6948 rp0
= (rp0
& FB_GFX_FREQ_FUSE_MASK
);
6953 static int cherryview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
6957 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_DUTYCYCLE_REG
);
6958 rpe
= (val
>> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT
) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK
;
6963 static int cherryview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
6967 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
6968 rp1
= (val
& FB_GFX_FREQ_FUSE_MASK
);
6973 static u32
cherryview_rps_min_freq(struct drm_i915_private
*dev_priv
)
6977 val
= vlv_punit_read(dev_priv
, FB_GFX_FMIN_AT_VMIN_FUSE
);
6978 rpn
= ((val
>> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT
) &
6979 FB_GFX_FREQ_FUSE_MASK
);
6984 static int valleyview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
6988 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
6990 rp1
= (val
& FB_GFX_FGUARANTEED_FREQ_FUSE_MASK
) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT
;
6995 static int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
6999 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
7001 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
7003 rp0
= min_t(u32
, rp0
, 0xea);
7008 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
7012 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
7013 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
7014 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
7015 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
7020 static int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
7024 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
7026 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
7027 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
7028 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
7029 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
7030 * to make sure it matches what Punit accepts.
7032 return max_t(u32
, val
, 0xc0);
7035 /* Check that the pctx buffer wasn't move under us. */
7036 static void valleyview_check_pctx(struct drm_i915_private
*dev_priv
)
7038 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
7040 WARN_ON(pctx_addr
!= dev_priv
->mm
.stolen_base
+
7041 dev_priv
->vlv_pctx
->stolen
->start
);
7045 /* Check that the pcbr address is not empty. */
7046 static void cherryview_check_pctx(struct drm_i915_private
*dev_priv
)
7048 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
7050 WARN_ON((pctx_addr
>> VLV_PCBR_ADDR_SHIFT
) == 0);
7053 static void cherryview_setup_pctx(struct drm_i915_private
*dev_priv
)
7055 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
7056 unsigned long pctx_paddr
, paddr
;
7058 int pctx_size
= 32*1024;
7060 pcbr
= I915_READ(VLV_PCBR
);
7061 if ((pcbr
>> VLV_PCBR_ADDR_SHIFT
) == 0) {
7062 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
7063 paddr
= (dev_priv
->mm
.stolen_base
+
7064 (ggtt
->stolen_size
- pctx_size
));
7066 pctx_paddr
= (paddr
& (~4095));
7067 I915_WRITE(VLV_PCBR
, pctx_paddr
);
7070 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
7073 static void valleyview_setup_pctx(struct drm_i915_private
*dev_priv
)
7075 struct drm_i915_gem_object
*pctx
;
7076 unsigned long pctx_paddr
;
7078 int pctx_size
= 24*1024;
7080 pcbr
= I915_READ(VLV_PCBR
);
7082 /* BIOS set it up already, grab the pre-alloc'd space */
7085 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
7086 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
,
7088 I915_GTT_OFFSET_NONE
,
7093 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
7096 * From the Gunit register HAS:
7097 * The Gfx driver is expected to program this register and ensure
7098 * proper allocation within Gfx stolen memory. For example, this
7099 * register should be programmed such than the PCBR range does not
7100 * overlap with other ranges, such as the frame buffer, protected
7101 * memory, or any other relevant ranges.
7103 pctx
= i915_gem_object_create_stolen(dev_priv
, pctx_size
);
7105 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
7109 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
7110 I915_WRITE(VLV_PCBR
, pctx_paddr
);
7113 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
7114 dev_priv
->vlv_pctx
= pctx
;
7117 static void valleyview_cleanup_pctx(struct drm_i915_private
*dev_priv
)
7119 if (WARN_ON(!dev_priv
->vlv_pctx
))
7122 i915_gem_object_put(dev_priv
->vlv_pctx
);
7123 dev_priv
->vlv_pctx
= NULL
;
7126 static void vlv_init_gpll_ref_freq(struct drm_i915_private
*dev_priv
)
7128 dev_priv
->gt_pm
.rps
.gpll_ref_freq
=
7129 vlv_get_cck_clock(dev_priv
, "GPLL ref",
7130 CCK_GPLL_CLOCK_CONTROL
,
7131 dev_priv
->czclk_freq
);
7133 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
7134 dev_priv
->gt_pm
.rps
.gpll_ref_freq
);
7137 static void valleyview_init_gt_powersave(struct drm_i915_private
*dev_priv
)
7139 struct intel_rps
*rps
= &dev_priv
->gt_pm
.rps
;
7142 valleyview_setup_pctx(dev_priv
);
7144 vlv_init_gpll_ref_freq(dev_priv
);
7146 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
7147 switch ((val
>> 6) & 3) {
7150 dev_priv
->mem_freq
= 800;
7153 dev_priv
->mem_freq
= 1066;
7156 dev_priv
->mem_freq
= 1333;
7159 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
7161 rps
->max_freq
= valleyview_rps_max_freq(dev_priv
);
7162 rps
->rp0_freq
= rps
->max_freq
;
7163 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7164 intel_gpu_freq(dev_priv
, rps
->max_freq
),
7167 rps
->efficient_freq
= valleyview_rps_rpe_freq(dev_priv
);
7168 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7169 intel_gpu_freq(dev_priv
, rps
->efficient_freq
),
7170 rps
->efficient_freq
);
7172 rps
->rp1_freq
= valleyview_rps_guar_freq(dev_priv
);
7173 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7174 intel_gpu_freq(dev_priv
, rps
->rp1_freq
),
7177 rps
->min_freq
= valleyview_rps_min_freq(dev_priv
);
7178 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7179 intel_gpu_freq(dev_priv
, rps
->min_freq
),
7183 static void cherryview_init_gt_powersave(struct drm_i915_private
*dev_priv
)
7185 struct intel_rps
*rps
= &dev_priv
->gt_pm
.rps
;
7188 cherryview_setup_pctx(dev_priv
);
7190 vlv_init_gpll_ref_freq(dev_priv
);
7192 mutex_lock(&dev_priv
->sb_lock
);
7193 val
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
);
7194 mutex_unlock(&dev_priv
->sb_lock
);
7196 switch ((val
>> 2) & 0x7) {
7198 dev_priv
->mem_freq
= 2000;
7201 dev_priv
->mem_freq
= 1600;
7204 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
7206 rps
->max_freq
= cherryview_rps_max_freq(dev_priv
);
7207 rps
->rp0_freq
= rps
->max_freq
;
7208 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7209 intel_gpu_freq(dev_priv
, rps
->max_freq
),
7212 rps
->efficient_freq
= cherryview_rps_rpe_freq(dev_priv
);
7213 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7214 intel_gpu_freq(dev_priv
, rps
->efficient_freq
),
7215 rps
->efficient_freq
);
7217 rps
->rp1_freq
= cherryview_rps_guar_freq(dev_priv
);
7218 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7219 intel_gpu_freq(dev_priv
, rps
->rp1_freq
),
7222 rps
->min_freq
= cherryview_rps_min_freq(dev_priv
);
7223 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7224 intel_gpu_freq(dev_priv
, rps
->min_freq
),
7227 WARN_ONCE((rps
->max_freq
| rps
->efficient_freq
| rps
->rp1_freq
|
7229 "Odd GPU freq values\n");
7232 static void valleyview_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
)
7234 valleyview_cleanup_pctx(dev_priv
);
7237 static void cherryview_enable_rc6(struct drm_i915_private
*dev_priv
)
7239 struct intel_engine_cs
*engine
;
7240 enum intel_engine_id id
;
7241 u32 gtfifodbg
, rc6_mode
= 0, pcbr
;
7243 gtfifodbg
= I915_READ(GTFIFODBG
) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV
|
7244 GT_FIFO_FREE_ENTRIES_CHV
);
7246 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
7248 I915_WRITE(GTFIFODBG
, gtfifodbg
);
7251 cherryview_check_pctx(dev_priv
);
7253 /* 1a & 1b: Get forcewake during program sequence. Although the driver
7254 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
7255 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
7257 /* Disable RC states. */
7258 I915_WRITE(GEN6_RC_CONTROL
, 0);
7260 /* 2a: Program RC6 thresholds.*/
7261 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
7262 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
7263 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
7265 for_each_engine(engine
, dev_priv
, id
)
7266 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
7267 I915_WRITE(GEN6_RC_SLEEP
, 0);
7269 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
7270 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x186);
7272 /* Allows RC6 residency counter to work */
7273 I915_WRITE(VLV_COUNTER_CONTROL
,
7274 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
7275 VLV_MEDIA_RC6_COUNT_EN
|
7276 VLV_RENDER_RC6_COUNT_EN
));
7278 /* For now we assume BIOS is allocating and populating the PCBR */
7279 pcbr
= I915_READ(VLV_PCBR
);
7282 if ((intel_rc6_enabled() & INTEL_RC6_ENABLE
) &&
7283 (pcbr
>> VLV_PCBR_ADDR_SHIFT
))
7284 rc6_mode
= GEN7_RC_CTL_TO_MODE
;
7286 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
7288 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
7291 static void cherryview_enable_rps(struct drm_i915_private
*dev_priv
)
7295 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
7297 /* 1: Program defaults and thresholds for RPS*/
7298 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
7299 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
7300 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
7301 I915_WRITE(GEN6_RP_UP_EI
, 66000);
7302 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
7304 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
7307 I915_WRITE(GEN6_RP_CONTROL
,
7308 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
7309 GEN6_RP_MEDIA_IS_GFX
|
7311 GEN6_RP_UP_BUSY_AVG
|
7312 GEN6_RP_DOWN_IDLE_AVG
);
7314 /* Setting Fixed Bias */
7315 val
= VLV_OVERRIDE_EN
|
7317 CHV_BIAS_CPU_50_SOC_50
;
7318 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
7320 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
7322 /* RPS code assumes GPLL is used */
7323 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
7325 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
7326 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
7328 reset_rps(dev_priv
, valleyview_set_rps
);
7330 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
7333 static void valleyview_enable_rc6(struct drm_i915_private
*dev_priv
)
7335 struct intel_engine_cs
*engine
;
7336 enum intel_engine_id id
;
7337 u32 gtfifodbg
, rc6_mode
= 0;
7339 valleyview_check_pctx(dev_priv
);
7341 gtfifodbg
= I915_READ(GTFIFODBG
);
7343 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
7345 I915_WRITE(GTFIFODBG
, gtfifodbg
);
7348 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
7350 /* Disable RC states. */
7351 I915_WRITE(GEN6_RC_CONTROL
, 0);
7353 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
7354 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
7355 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
7357 for_each_engine(engine
, dev_priv
, id
)
7358 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
7360 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
7362 /* Allows RC6 residency counter to work */
7363 I915_WRITE(VLV_COUNTER_CONTROL
,
7364 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
7365 VLV_MEDIA_RC0_COUNT_EN
|
7366 VLV_RENDER_RC0_COUNT_EN
|
7367 VLV_MEDIA_RC6_COUNT_EN
|
7368 VLV_RENDER_RC6_COUNT_EN
));
7370 if (intel_rc6_enabled() & INTEL_RC6_ENABLE
)
7371 rc6_mode
= GEN7_RC_CTL_TO_MODE
| VLV_RC_CTL_CTX_RST_PARALLEL
;
7373 intel_print_rc6_info(dev_priv
, rc6_mode
);
7375 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
7377 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
7380 static void valleyview_enable_rps(struct drm_i915_private
*dev_priv
)
7384 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
7386 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
7387 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
7388 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
7389 I915_WRITE(GEN6_RP_UP_EI
, 66000);
7390 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
7392 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
7394 I915_WRITE(GEN6_RP_CONTROL
,
7395 GEN6_RP_MEDIA_TURBO
|
7396 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
7397 GEN6_RP_MEDIA_IS_GFX
|
7399 GEN6_RP_UP_BUSY_AVG
|
7400 GEN6_RP_DOWN_IDLE_CONT
);
7402 /* Setting Fixed Bias */
7403 val
= VLV_OVERRIDE_EN
|
7405 VLV_BIAS_CPU_125_SOC_875
;
7406 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
7408 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
7410 /* RPS code assumes GPLL is used */
7411 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
7413 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
7414 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
7416 reset_rps(dev_priv
, valleyview_set_rps
);
7418 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
7421 static unsigned long intel_pxfreq(u32 vidfreq
)
7424 int div
= (vidfreq
& 0x3f0000) >> 16;
7425 int post
= (vidfreq
& 0x3000) >> 12;
7426 int pre
= (vidfreq
& 0x7);
7431 freq
= ((div
* 133333) / ((1<<post
) * pre
));
7436 static const struct cparams
{
7442 { 1, 1333, 301, 28664 },
7443 { 1, 1066, 294, 24460 },
7444 { 1, 800, 294, 25192 },
7445 { 0, 1333, 276, 27605 },
7446 { 0, 1066, 276, 27605 },
7447 { 0, 800, 231, 23784 },
7450 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
7452 u64 total_count
, diff
, ret
;
7453 u32 count1
, count2
, count3
, m
= 0, c
= 0;
7454 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
7457 lockdep_assert_held(&mchdev_lock
);
7459 diff1
= now
- dev_priv
->ips
.last_time1
;
7461 /* Prevent division-by-zero if we are asking too fast.
7462 * Also, we don't get interesting results if we are polling
7463 * faster than once in 10ms, so just return the saved value
7467 return dev_priv
->ips
.chipset_power
;
7469 count1
= I915_READ(DMIEC
);
7470 count2
= I915_READ(DDREC
);
7471 count3
= I915_READ(CSIEC
);
7473 total_count
= count1
+ count2
+ count3
;
7475 /* FIXME: handle per-counter overflow */
7476 if (total_count
< dev_priv
->ips
.last_count1
) {
7477 diff
= ~0UL - dev_priv
->ips
.last_count1
;
7478 diff
+= total_count
;
7480 diff
= total_count
- dev_priv
->ips
.last_count1
;
7483 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
7484 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
7485 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
7492 diff
= div_u64(diff
, diff1
);
7493 ret
= ((m
* diff
) + c
);
7494 ret
= div_u64(ret
, 10);
7496 dev_priv
->ips
.last_count1
= total_count
;
7497 dev_priv
->ips
.last_time1
= now
;
7499 dev_priv
->ips
.chipset_power
= ret
;
7504 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
7508 if (INTEL_INFO(dev_priv
)->gen
!= 5)
7511 spin_lock_irq(&mchdev_lock
);
7513 val
= __i915_chipset_val(dev_priv
);
7515 spin_unlock_irq(&mchdev_lock
);
7520 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
7522 unsigned long m
, x
, b
;
7525 tsfs
= I915_READ(TSFS
);
7527 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
7528 x
= I915_READ8(TR1
);
7530 b
= tsfs
& TSFS_INTR_MASK
;
7532 return ((m
* x
) / 127) - b
;
7535 static int _pxvid_to_vd(u8 pxvid
)
7540 if (pxvid
>= 8 && pxvid
< 31)
7543 return (pxvid
+ 2) * 125;
7546 static u32
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
7548 const int vd
= _pxvid_to_vd(pxvid
);
7549 const int vm
= vd
- 1125;
7551 if (INTEL_INFO(dev_priv
)->is_mobile
)
7552 return vm
> 0 ? vm
: 0;
7557 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
7559 u64 now
, diff
, diffms
;
7562 lockdep_assert_held(&mchdev_lock
);
7564 now
= ktime_get_raw_ns();
7565 diffms
= now
- dev_priv
->ips
.last_time2
;
7566 do_div(diffms
, NSEC_PER_MSEC
);
7568 /* Don't divide by 0 */
7572 count
= I915_READ(GFXEC
);
7574 if (count
< dev_priv
->ips
.last_count2
) {
7575 diff
= ~0UL - dev_priv
->ips
.last_count2
;
7578 diff
= count
- dev_priv
->ips
.last_count2
;
7581 dev_priv
->ips
.last_count2
= count
;
7582 dev_priv
->ips
.last_time2
= now
;
7584 /* More magic constants... */
7586 diff
= div_u64(diff
, diffms
* 10);
7587 dev_priv
->ips
.gfx_power
= diff
;
7590 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
7592 if (INTEL_INFO(dev_priv
)->gen
!= 5)
7595 spin_lock_irq(&mchdev_lock
);
7597 __i915_update_gfx_val(dev_priv
);
7599 spin_unlock_irq(&mchdev_lock
);
7602 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
7604 unsigned long t
, corr
, state1
, corr2
, state2
;
7607 lockdep_assert_held(&mchdev_lock
);
7609 pxvid
= I915_READ(PXVFREQ(dev_priv
->gt_pm
.rps
.cur_freq
));
7610 pxvid
= (pxvid
>> 24) & 0x7f;
7611 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
7615 t
= i915_mch_val(dev_priv
);
7617 /* Revel in the empirically derived constants */
7619 /* Correction factor in 1/100000 units */
7621 corr
= ((t
* 2349) + 135940);
7623 corr
= ((t
* 964) + 29317);
7625 corr
= ((t
* 301) + 1004);
7627 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
7629 corr2
= (corr
* dev_priv
->ips
.corr
);
7631 state2
= (corr2
* state1
) / 10000;
7632 state2
/= 100; /* convert to mW */
7634 __i915_update_gfx_val(dev_priv
);
7636 return dev_priv
->ips
.gfx_power
+ state2
;
7639 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
7643 if (INTEL_INFO(dev_priv
)->gen
!= 5)
7646 spin_lock_irq(&mchdev_lock
);
7648 val
= __i915_gfx_val(dev_priv
);
7650 spin_unlock_irq(&mchdev_lock
);
7656 * i915_read_mch_val - return value for IPS use
7658 * Calculate and return a value for the IPS driver to use when deciding whether
7659 * we have thermal and power headroom to increase CPU or GPU power budget.
7661 unsigned long i915_read_mch_val(void)
7663 struct drm_i915_private
*dev_priv
;
7664 unsigned long chipset_val
, graphics_val
, ret
= 0;
7666 spin_lock_irq(&mchdev_lock
);
7669 dev_priv
= i915_mch_dev
;
7671 chipset_val
= __i915_chipset_val(dev_priv
);
7672 graphics_val
= __i915_gfx_val(dev_priv
);
7674 ret
= chipset_val
+ graphics_val
;
7677 spin_unlock_irq(&mchdev_lock
);
7681 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
7684 * i915_gpu_raise - raise GPU frequency limit
7686 * Raise the limit; IPS indicates we have thermal headroom.
7688 bool i915_gpu_raise(void)
7690 struct drm_i915_private
*dev_priv
;
7693 spin_lock_irq(&mchdev_lock
);
7694 if (!i915_mch_dev
) {
7698 dev_priv
= i915_mch_dev
;
7700 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
7701 dev_priv
->ips
.max_delay
--;
7704 spin_unlock_irq(&mchdev_lock
);
7708 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
7711 * i915_gpu_lower - lower GPU frequency limit
7713 * IPS indicates we're close to a thermal limit, so throttle back the GPU
7714 * frequency maximum.
7716 bool i915_gpu_lower(void)
7718 struct drm_i915_private
*dev_priv
;
7721 spin_lock_irq(&mchdev_lock
);
7722 if (!i915_mch_dev
) {
7726 dev_priv
= i915_mch_dev
;
7728 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
7729 dev_priv
->ips
.max_delay
++;
7732 spin_unlock_irq(&mchdev_lock
);
7736 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
7739 * i915_gpu_busy - indicate GPU business to IPS
7741 * Tell the IPS driver whether or not the GPU is busy.
7743 bool i915_gpu_busy(void)
7747 spin_lock_irq(&mchdev_lock
);
7749 ret
= i915_mch_dev
->gt
.awake
;
7750 spin_unlock_irq(&mchdev_lock
);
7754 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
7757 * i915_gpu_turbo_disable - disable graphics turbo
7759 * Disable graphics turbo by resetting the max frequency and setting the
7760 * current frequency to the default.
7762 bool i915_gpu_turbo_disable(void)
7764 struct drm_i915_private
*dev_priv
;
7767 spin_lock_irq(&mchdev_lock
);
7768 if (!i915_mch_dev
) {
7772 dev_priv
= i915_mch_dev
;
7774 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
7776 if (!ironlake_set_drps(dev_priv
, dev_priv
->ips
.fstart
))
7780 spin_unlock_irq(&mchdev_lock
);
7784 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
7787 * Tells the intel_ips driver that the i915 driver is now loaded, if
7788 * IPS got loaded first.
7790 * This awkward dance is so that neither module has to depend on the
7791 * other in order for IPS to do the appropriate communication of
7792 * GPU turbo limits to i915.
7795 ips_ping_for_i915_load(void)
7799 link
= symbol_get(ips_link_to_i915_driver
);
7802 symbol_put(ips_link_to_i915_driver
);
7806 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
7808 /* We only register the i915 ips part with intel-ips once everything is
7809 * set up, to avoid intel-ips sneaking in and reading bogus values. */
7810 spin_lock_irq(&mchdev_lock
);
7811 i915_mch_dev
= dev_priv
;
7812 spin_unlock_irq(&mchdev_lock
);
7814 ips_ping_for_i915_load();
7817 void intel_gpu_ips_teardown(void)
7819 spin_lock_irq(&mchdev_lock
);
7820 i915_mch_dev
= NULL
;
7821 spin_unlock_irq(&mchdev_lock
);
7824 static void intel_init_emon(struct drm_i915_private
*dev_priv
)
7830 /* Disable to program */
7834 /* Program energy weights for various events */
7835 I915_WRITE(SDEW
, 0x15040d00);
7836 I915_WRITE(CSIEW0
, 0x007f0000);
7837 I915_WRITE(CSIEW1
, 0x1e220004);
7838 I915_WRITE(CSIEW2
, 0x04000004);
7840 for (i
= 0; i
< 5; i
++)
7841 I915_WRITE(PEW(i
), 0);
7842 for (i
= 0; i
< 3; i
++)
7843 I915_WRITE(DEW(i
), 0);
7845 /* Program P-state weights to account for frequency power adjustment */
7846 for (i
= 0; i
< 16; i
++) {
7847 u32 pxvidfreq
= I915_READ(PXVFREQ(i
));
7848 unsigned long freq
= intel_pxfreq(pxvidfreq
);
7849 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
7854 val
*= (freq
/ 1000);
7856 val
/= (127*127*900);
7858 DRM_ERROR("bad pxval: %ld\n", val
);
7861 /* Render standby states get 0 weight */
7865 for (i
= 0; i
< 4; i
++) {
7866 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
7867 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
7868 I915_WRITE(PXW(i
), val
);
7871 /* Adjust magic regs to magic values (more experimental results) */
7872 I915_WRITE(OGW0
, 0);
7873 I915_WRITE(OGW1
, 0);
7874 I915_WRITE(EG0
, 0x00007f00);
7875 I915_WRITE(EG1
, 0x0000000e);
7876 I915_WRITE(EG2
, 0x000e0000);
7877 I915_WRITE(EG3
, 0x68000300);
7878 I915_WRITE(EG4
, 0x42000000);
7879 I915_WRITE(EG5
, 0x00140031);
7883 for (i
= 0; i
< 8; i
++)
7884 I915_WRITE(PXWL(i
), 0);
7886 /* Enable PMON + select events */
7887 I915_WRITE(ECR
, 0x80000019);
7889 lcfuse
= I915_READ(LCFUSE02
);
7891 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
7894 void intel_init_gt_powersave(struct drm_i915_private
*dev_priv
)
7896 struct intel_rps
*rps
= &dev_priv
->gt_pm
.rps
;
7899 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7902 if (!i915_modparams
.enable_rc6
) {
7903 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7904 intel_runtime_pm_get(dev_priv
);
7907 mutex_lock(&dev_priv
->drm
.struct_mutex
);
7908 mutex_lock(&dev_priv
->pcu_lock
);
7910 /* Initialize RPS limits (for userspace) */
7911 if (IS_CHERRYVIEW(dev_priv
))
7912 cherryview_init_gt_powersave(dev_priv
);
7913 else if (IS_VALLEYVIEW(dev_priv
))
7914 valleyview_init_gt_powersave(dev_priv
);
7915 else if (INTEL_GEN(dev_priv
) >= 6)
7916 gen6_init_rps_frequencies(dev_priv
);
7918 /* Derive initial user preferences/limits from the hardware limits */
7919 rps
->idle_freq
= rps
->min_freq
;
7920 rps
->cur_freq
= rps
->idle_freq
;
7922 rps
->max_freq_softlimit
= rps
->max_freq
;
7923 rps
->min_freq_softlimit
= rps
->min_freq
;
7925 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
7926 rps
->min_freq_softlimit
=
7928 rps
->efficient_freq
,
7929 intel_freq_opcode(dev_priv
, 450));
7931 /* After setting max-softlimit, find the overclock max freq */
7932 if (IS_GEN6(dev_priv
) ||
7933 IS_IVYBRIDGE(dev_priv
) || IS_HASWELL(dev_priv
)) {
7936 sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, ¶ms
);
7937 if (params
& BIT(31)) { /* OC supported */
7938 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
7939 (rps
->max_freq
& 0xff) * 50,
7940 (params
& 0xff) * 50);
7941 rps
->max_freq
= params
& 0xff;
7945 /* Finally allow us to boost to max by default */
7946 rps
->boost_freq
= rps
->max_freq
;
7948 mutex_unlock(&dev_priv
->pcu_lock
);
7949 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
7951 intel_autoenable_gt_powersave(dev_priv
);
7954 void intel_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
)
7956 if (IS_VALLEYVIEW(dev_priv
))
7957 valleyview_cleanup_gt_powersave(dev_priv
);
7959 if (!i915_modparams
.enable_rc6
)
7960 intel_runtime_pm_put(dev_priv
);
7964 * intel_suspend_gt_powersave - suspend PM work and helper threads
7965 * @dev_priv: i915 device
7967 * We don't want to disable RC6 or other features here, we just want
7968 * to make sure any work we've queued has finished and won't bother
7969 * us while we're suspended.
7971 void intel_suspend_gt_powersave(struct drm_i915_private
*dev_priv
)
7973 if (INTEL_GEN(dev_priv
) < 6)
7976 if (cancel_delayed_work_sync(&dev_priv
->gt_pm
.autoenable_work
))
7977 intel_runtime_pm_put(dev_priv
);
7979 /* gen6_rps_idle() will be called later to disable interrupts */
7982 void intel_sanitize_gt_powersave(struct drm_i915_private
*dev_priv
)
7984 dev_priv
->gt_pm
.rps
.enabled
= true; /* force RPS disabling */
7985 dev_priv
->gt_pm
.rc6
.enabled
= true; /* force RC6 disabling */
7986 intel_disable_gt_powersave(dev_priv
);
7988 gen6_reset_rps_interrupts(dev_priv
);
7991 static inline void intel_disable_llc_pstate(struct drm_i915_private
*i915
)
7993 lockdep_assert_held(&i915
->pcu_lock
);
7995 if (!i915
->gt_pm
.llc_pstate
.enabled
)
7998 /* Currently there is no HW configuration to be done to disable. */
8000 i915
->gt_pm
.llc_pstate
.enabled
= false;
8003 static void intel_disable_rc6(struct drm_i915_private
*dev_priv
)
8005 lockdep_assert_held(&dev_priv
->pcu_lock
);
8007 if (!dev_priv
->gt_pm
.rc6
.enabled
)
8010 if (INTEL_GEN(dev_priv
) >= 9)
8011 gen9_disable_rc6(dev_priv
);
8012 else if (IS_CHERRYVIEW(dev_priv
))
8013 cherryview_disable_rc6(dev_priv
);
8014 else if (IS_VALLEYVIEW(dev_priv
))
8015 valleyview_disable_rc6(dev_priv
);
8016 else if (INTEL_GEN(dev_priv
) >= 6)
8017 gen6_disable_rc6(dev_priv
);
8019 dev_priv
->gt_pm
.rc6
.enabled
= false;
8022 static void intel_disable_rps(struct drm_i915_private
*dev_priv
)
8024 lockdep_assert_held(&dev_priv
->pcu_lock
);
8026 if (!dev_priv
->gt_pm
.rps
.enabled
)
8029 if (INTEL_GEN(dev_priv
) >= 9)
8030 gen9_disable_rps(dev_priv
);
8031 else if (IS_CHERRYVIEW(dev_priv
))
8032 cherryview_disable_rps(dev_priv
);
8033 else if (IS_VALLEYVIEW(dev_priv
))
8034 valleyview_disable_rps(dev_priv
);
8035 else if (INTEL_GEN(dev_priv
) >= 6)
8036 gen6_disable_rps(dev_priv
);
8037 else if (IS_IRONLAKE_M(dev_priv
))
8038 ironlake_disable_drps(dev_priv
);
8040 dev_priv
->gt_pm
.rps
.enabled
= false;
8043 void intel_disable_gt_powersave(struct drm_i915_private
*dev_priv
)
8045 mutex_lock(&dev_priv
->pcu_lock
);
8047 intel_disable_rc6(dev_priv
);
8048 intel_disable_rps(dev_priv
);
8049 if (HAS_LLC(dev_priv
))
8050 intel_disable_llc_pstate(dev_priv
);
8052 mutex_unlock(&dev_priv
->pcu_lock
);
8055 static inline void intel_enable_llc_pstate(struct drm_i915_private
*i915
)
8057 lockdep_assert_held(&i915
->pcu_lock
);
8059 if (i915
->gt_pm
.llc_pstate
.enabled
)
8062 gen6_update_ring_freq(i915
);
8064 i915
->gt_pm
.llc_pstate
.enabled
= true;
8067 static void intel_enable_rc6(struct drm_i915_private
*dev_priv
)
8069 lockdep_assert_held(&dev_priv
->pcu_lock
);
8071 if (dev_priv
->gt_pm
.rc6
.enabled
)
8074 if (IS_CHERRYVIEW(dev_priv
))
8075 cherryview_enable_rc6(dev_priv
);
8076 else if (IS_VALLEYVIEW(dev_priv
))
8077 valleyview_enable_rc6(dev_priv
);
8078 else if (INTEL_GEN(dev_priv
) >= 9)
8079 gen9_enable_rc6(dev_priv
);
8080 else if (IS_BROADWELL(dev_priv
))
8081 gen8_enable_rc6(dev_priv
);
8082 else if (INTEL_GEN(dev_priv
) >= 6)
8083 gen6_enable_rc6(dev_priv
);
8085 dev_priv
->gt_pm
.rc6
.enabled
= true;
8088 static void intel_enable_rps(struct drm_i915_private
*dev_priv
)
8090 struct intel_rps
*rps
= &dev_priv
->gt_pm
.rps
;
8092 lockdep_assert_held(&dev_priv
->pcu_lock
);
8097 if (IS_CHERRYVIEW(dev_priv
)) {
8098 cherryview_enable_rps(dev_priv
);
8099 } else if (IS_VALLEYVIEW(dev_priv
)) {
8100 valleyview_enable_rps(dev_priv
);
8101 } else if (INTEL_GEN(dev_priv
) >= 9) {
8102 gen9_enable_rps(dev_priv
);
8103 } else if (IS_BROADWELL(dev_priv
)) {
8104 gen8_enable_rps(dev_priv
);
8105 } else if (INTEL_GEN(dev_priv
) >= 6) {
8106 gen6_enable_rps(dev_priv
);
8107 } else if (IS_IRONLAKE_M(dev_priv
)) {
8108 ironlake_enable_drps(dev_priv
);
8109 intel_init_emon(dev_priv
);
8112 WARN_ON(rps
->max_freq
< rps
->min_freq
);
8113 WARN_ON(rps
->idle_freq
> rps
->max_freq
);
8115 WARN_ON(rps
->efficient_freq
< rps
->min_freq
);
8116 WARN_ON(rps
->efficient_freq
> rps
->max_freq
);
8118 rps
->enabled
= true;
8121 void intel_enable_gt_powersave(struct drm_i915_private
*dev_priv
)
8123 /* Powersaving is controlled by the host when inside a VM */
8124 if (intel_vgpu_active(dev_priv
))
8127 mutex_lock(&dev_priv
->pcu_lock
);
8129 intel_enable_rc6(dev_priv
);
8130 intel_enable_rps(dev_priv
);
8131 if (HAS_LLC(dev_priv
))
8132 intel_enable_llc_pstate(dev_priv
);
8134 mutex_unlock(&dev_priv
->pcu_lock
);
8137 static void __intel_autoenable_gt_powersave(struct work_struct
*work
)
8139 struct drm_i915_private
*dev_priv
=
8142 gt_pm
.autoenable_work
.work
);
8143 struct intel_engine_cs
*rcs
;
8144 struct drm_i915_gem_request
*req
;
8146 rcs
= dev_priv
->engine
[RCS
];
8147 if (rcs
->last_retired_context
)
8150 if (!rcs
->init_context
)
8153 mutex_lock(&dev_priv
->drm
.struct_mutex
);
8155 req
= i915_gem_request_alloc(rcs
, dev_priv
->kernel_context
);
8159 if (!i915_modparams
.enable_execlists
&& i915_switch_context(req
) == 0)
8160 rcs
->init_context(req
);
8162 /* Mark the device busy, calling intel_enable_gt_powersave() */
8163 i915_add_request(req
);
8166 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
8168 intel_runtime_pm_put(dev_priv
);
8171 void intel_autoenable_gt_powersave(struct drm_i915_private
*dev_priv
)
8173 if (IS_IRONLAKE_M(dev_priv
)) {
8174 ironlake_enable_drps(dev_priv
);
8175 intel_init_emon(dev_priv
);
8176 } else if (INTEL_INFO(dev_priv
)->gen
>= 6) {
8178 * PCU communication is slow and this doesn't need to be
8179 * done at any specific time, so do this out of our fast path
8180 * to make resume and init faster.
8182 * We depend on the HW RC6 power context save/restore
8183 * mechanism when entering D3 through runtime PM suspend. So
8184 * disable RPM until RPS/RC6 is properly setup. We can only
8185 * get here via the driver load/system resume/runtime resume
8186 * paths, so the _noresume version is enough (and in case of
8187 * runtime resume it's necessary).
8189 if (queue_delayed_work(dev_priv
->wq
,
8190 &dev_priv
->gt_pm
.autoenable_work
,
8191 round_jiffies_up_relative(HZ
)))
8192 intel_runtime_pm_get_noresume(dev_priv
);
8196 static void ibx_init_clock_gating(struct drm_i915_private
*dev_priv
)
8199 * On Ibex Peak and Cougar Point, we need to disable clock
8200 * gating for the panel power sequencer or it will fail to
8201 * start up when no ports are active.
8203 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
8206 static void g4x_disable_trickle_feed(struct drm_i915_private
*dev_priv
)
8210 for_each_pipe(dev_priv
, pipe
) {
8211 I915_WRITE(DSPCNTR(pipe
),
8212 I915_READ(DSPCNTR(pipe
)) |
8213 DISPPLANE_TRICKLE_FEED_DISABLE
);
8215 I915_WRITE(DSPSURF(pipe
), I915_READ(DSPSURF(pipe
)));
8216 POSTING_READ(DSPSURF(pipe
));
8220 static void ilk_init_clock_gating(struct drm_i915_private
*dev_priv
)
8222 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
8226 * WaFbcDisableDpfcClockGating:ilk
8228 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
8229 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
8230 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
8232 I915_WRITE(PCH_3DCGDIS0
,
8233 MARIUNIT_CLOCK_GATE_DISABLE
|
8234 SVSMUNIT_CLOCK_GATE_DISABLE
);
8235 I915_WRITE(PCH_3DCGDIS1
,
8236 VFMUNIT_CLOCK_GATE_DISABLE
);
8239 * According to the spec the following bits should be set in
8240 * order to enable memory self-refresh
8241 * The bit 22/21 of 0x42004
8242 * The bit 5 of 0x42020
8243 * The bit 15 of 0x45000
8245 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8246 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
8247 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
8248 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
8249 I915_WRITE(DISP_ARB_CTL
,
8250 (I915_READ(DISP_ARB_CTL
) |
8254 * Based on the document from hardware guys the following bits
8255 * should be set unconditionally in order to enable FBC.
8256 * The bit 22 of 0x42000
8257 * The bit 22 of 0x42004
8258 * The bit 7,8,9 of 0x42020.
8260 if (IS_IRONLAKE_M(dev_priv
)) {
8261 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
8262 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
8263 I915_READ(ILK_DISPLAY_CHICKEN1
) |
8265 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8266 I915_READ(ILK_DISPLAY_CHICKEN2
) |
8270 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
8272 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8273 I915_READ(ILK_DISPLAY_CHICKEN2
) |
8274 ILK_ELPIN_409_SELECT
);
8275 I915_WRITE(_3D_CHICKEN2
,
8276 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
8277 _3D_CHICKEN2_WM_READ_PIPELINED
);
8279 /* WaDisableRenderCachePipelinedFlush:ilk */
8280 I915_WRITE(CACHE_MODE_0
,
8281 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
8283 /* WaDisable_RenderCache_OperationalFlush:ilk */
8284 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8286 g4x_disable_trickle_feed(dev_priv
);
8288 ibx_init_clock_gating(dev_priv
);
8291 static void cpt_init_clock_gating(struct drm_i915_private
*dev_priv
)
8297 * On Ibex Peak and Cougar Point, we need to disable clock
8298 * gating for the panel power sequencer or it will fail to
8299 * start up when no ports are active.
8301 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
8302 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
8303 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
8304 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
8305 DPLS_EDP_PPS_FIX_DIS
);
8306 /* The below fixes the weird display corruption, a few pixels shifted
8307 * downward, on (only) LVDS of some HP laptops with IVY.
8309 for_each_pipe(dev_priv
, pipe
) {
8310 val
= I915_READ(TRANS_CHICKEN2(pipe
));
8311 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
8312 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
8313 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
8314 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
8315 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
8316 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
8317 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
8318 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
8320 /* WADP0ClockGatingDisable */
8321 for_each_pipe(dev_priv
, pipe
) {
8322 I915_WRITE(TRANS_CHICKEN1(pipe
),
8323 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
8327 static void gen6_check_mch_setup(struct drm_i915_private
*dev_priv
)
8331 tmp
= I915_READ(MCH_SSKPD
);
8332 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
)
8333 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
8337 static void gen6_init_clock_gating(struct drm_i915_private
*dev_priv
)
8339 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
8341 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
8343 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8344 I915_READ(ILK_DISPLAY_CHICKEN2
) |
8345 ILK_ELPIN_409_SELECT
);
8347 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
8348 I915_WRITE(_3D_CHICKEN
,
8349 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
8351 /* WaDisable_RenderCache_OperationalFlush:snb */
8352 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8355 * BSpec recoomends 8x4 when MSAA is used,
8356 * however in practice 16x4 seems fastest.
8358 * Note that PS/WM thread counts depend on the WIZ hashing
8359 * disable bit, which we don't touch here, but it's good
8360 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8362 I915_WRITE(GEN6_GT_MODE
,
8363 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
8365 I915_WRITE(CACHE_MODE_0
,
8366 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
8368 I915_WRITE(GEN6_UCGCTL1
,
8369 I915_READ(GEN6_UCGCTL1
) |
8370 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
8371 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
8373 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8374 * gating disable must be set. Failure to set it results in
8375 * flickering pixels due to Z write ordering failures after
8376 * some amount of runtime in the Mesa "fire" demo, and Unigine
8377 * Sanctuary and Tropics, and apparently anything else with
8378 * alpha test or pixel discard.
8380 * According to the spec, bit 11 (RCCUNIT) must also be set,
8381 * but we didn't debug actual testcases to find it out.
8383 * WaDisableRCCUnitClockGating:snb
8384 * WaDisableRCPBUnitClockGating:snb
8386 I915_WRITE(GEN6_UCGCTL2
,
8387 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
8388 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
8390 /* WaStripsFansDisableFastClipPerformanceFix:snb */
8391 I915_WRITE(_3D_CHICKEN3
,
8392 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
));
8396 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
8397 * 3DSTATE_SF number of SF output attributes is more than 16."
8399 I915_WRITE(_3D_CHICKEN3
,
8400 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH
));
8403 * According to the spec the following bits should be
8404 * set in order to enable memory self-refresh and fbc:
8405 * The bit21 and bit22 of 0x42000
8406 * The bit21 and bit22 of 0x42004
8407 * The bit5 and bit7 of 0x42020
8408 * The bit14 of 0x70180
8409 * The bit14 of 0x71180
8411 * WaFbcAsynchFlipDisableFbcQueue:snb
8413 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
8414 I915_READ(ILK_DISPLAY_CHICKEN1
) |
8415 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
8416 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8417 I915_READ(ILK_DISPLAY_CHICKEN2
) |
8418 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
8419 I915_WRITE(ILK_DSPCLK_GATE_D
,
8420 I915_READ(ILK_DSPCLK_GATE_D
) |
8421 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
8422 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
8424 g4x_disable_trickle_feed(dev_priv
);
8426 cpt_init_clock_gating(dev_priv
);
8428 gen6_check_mch_setup(dev_priv
);
8431 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
8433 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
8436 * WaVSThreadDispatchOverride:ivb,vlv
8438 * This actually overrides the dispatch
8439 * mode for all thread types.
8441 reg
&= ~GEN7_FF_SCHED_MASK
;
8442 reg
|= GEN7_FF_TS_SCHED_HW
;
8443 reg
|= GEN7_FF_VS_SCHED_HW
;
8444 reg
|= GEN7_FF_DS_SCHED_HW
;
8446 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
8449 static void lpt_init_clock_gating(struct drm_i915_private
*dev_priv
)
8452 * TODO: this bit should only be enabled when really needed, then
8453 * disabled when not needed anymore in order to save power.
8455 if (HAS_PCH_LPT_LP(dev_priv
))
8456 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
8457 I915_READ(SOUTH_DSPCLK_GATE_D
) |
8458 PCH_LP_PARTITION_LEVEL_DISABLE
);
8460 /* WADPOClockGatingDisable:hsw */
8461 I915_WRITE(TRANS_CHICKEN1(PIPE_A
),
8462 I915_READ(TRANS_CHICKEN1(PIPE_A
)) |
8463 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
8466 static void lpt_suspend_hw(struct drm_i915_private
*dev_priv
)
8468 if (HAS_PCH_LPT_LP(dev_priv
)) {
8469 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
8471 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
8472 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
8476 static void gen8_set_l3sqc_credits(struct drm_i915_private
*dev_priv
,
8477 int general_prio_credits
,
8478 int high_prio_credits
)
8483 /* WaTempDisableDOPClkGating:bdw */
8484 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
8485 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
8487 val
= I915_READ(GEN8_L3SQCREG1
);
8488 val
&= ~L3_PRIO_CREDITS_MASK
;
8489 val
|= L3_GENERAL_PRIO_CREDITS(general_prio_credits
);
8490 val
|= L3_HIGH_PRIO_CREDITS(high_prio_credits
);
8491 I915_WRITE(GEN8_L3SQCREG1
, val
);
8494 * Wait at least 100 clocks before re-enabling clock gating.
8495 * See the definition of L3SQCREG1 in BSpec.
8497 POSTING_READ(GEN8_L3SQCREG1
);
8499 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
8502 static void cnp_init_clock_gating(struct drm_i915_private
*dev_priv
)
8504 if (!HAS_PCH_CNP(dev_priv
))
8508 I915_WRITE(SOUTH_DSPCLK_GATE_D
, I915_READ(SOUTH_DSPCLK_GATE_D
) |
8509 CNP_PWM_CGE_GATING_DISABLE
);
8512 static void cnl_init_clock_gating(struct drm_i915_private
*dev_priv
)
8514 cnp_init_clock_gating(dev_priv
);
8516 /* This is not an Wa. Enable for better image quality */
8517 I915_WRITE(_3D_CHICKEN3
,
8518 _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE
));
8520 /* WaEnableChickenDCPR:cnl */
8521 I915_WRITE(GEN8_CHICKEN_DCPR_1
,
8522 I915_READ(GEN8_CHICKEN_DCPR_1
) | MASK_WAKEMEM
);
8524 /* WaFbcWakeMemOn:cnl */
8525 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
8526 DISP_FBC_MEMORY_WAKE
);
8528 /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
8529 if (IS_CNL_REVID(dev_priv
, CNL_REVID_A0
, CNL_REVID_B0
))
8530 I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE
,
8531 I915_READ(SLICE_UNIT_LEVEL_CLKGATE
) |
8532 SARBUNIT_CLKGATE_DIS
);
8535 static void cfl_init_clock_gating(struct drm_i915_private
*dev_priv
)
8537 cnp_init_clock_gating(dev_priv
);
8538 gen9_init_clock_gating(dev_priv
);
8540 /* WaFbcNukeOnHostModify:cfl */
8541 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
8542 ILK_DPFC_NUKE_ON_ANY_MODIFICATION
);
8545 static void kbl_init_clock_gating(struct drm_i915_private
*dev_priv
)
8547 gen9_init_clock_gating(dev_priv
);
8549 /* WaDisableSDEUnitClockGating:kbl */
8550 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
8551 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
8552 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
8554 /* WaDisableGamClockGating:kbl */
8555 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
8556 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
8557 GEN6_GAMUNIT_CLOCK_GATE_DISABLE
);
8559 /* WaFbcNukeOnHostModify:kbl */
8560 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
8561 ILK_DPFC_NUKE_ON_ANY_MODIFICATION
);
8564 static void skl_init_clock_gating(struct drm_i915_private
*dev_priv
)
8566 gen9_init_clock_gating(dev_priv
);
8568 /* WAC6entrylatency:skl */
8569 I915_WRITE(FBC_LLC_READ_CTRL
, I915_READ(FBC_LLC_READ_CTRL
) |
8570 FBC_LLC_FULLY_OPEN
);
8572 /* WaFbcNukeOnHostModify:skl */
8573 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
8574 ILK_DPFC_NUKE_ON_ANY_MODIFICATION
);
8577 static void bdw_init_clock_gating(struct drm_i915_private
*dev_priv
)
8579 /* The GTT cache must be disabled if the system is using 2M pages. */
8580 bool can_use_gtt_cache
= !HAS_PAGE_SIZES(dev_priv
,
8581 I915_GTT_PAGE_SIZE_2M
);
8584 /* WaSwitchSolVfFArbitrationPriority:bdw */
8585 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
8587 /* WaPsrDPAMaskVBlankInSRD:bdw */
8588 I915_WRITE(CHICKEN_PAR1_1
,
8589 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
8591 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
8592 for_each_pipe(dev_priv
, pipe
) {
8593 I915_WRITE(CHICKEN_PIPESL_1(pipe
),
8594 I915_READ(CHICKEN_PIPESL_1(pipe
)) |
8595 BDW_DPRS_MASK_VBLANK_SRD
);
8598 /* WaVSRefCountFullforceMissDisable:bdw */
8599 /* WaDSRefCountFullforceMissDisable:bdw */
8600 I915_WRITE(GEN7_FF_THREAD_MODE
,
8601 I915_READ(GEN7_FF_THREAD_MODE
) &
8602 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
8604 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
8605 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
8607 /* WaDisableSDEUnitClockGating:bdw */
8608 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
8609 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
8611 /* WaProgramL3SqcReg1Default:bdw */
8612 gen8_set_l3sqc_credits(dev_priv
, 30, 2);
8614 /* WaGttCachingOffByDefault:bdw */
8615 I915_WRITE(HSW_GTT_CACHE_EN
, can_use_gtt_cache
? GTT_CACHE_EN_ALL
: 0);
8617 /* WaKVMNotificationOnConfigChange:bdw */
8618 I915_WRITE(CHICKEN_PAR2_1
, I915_READ(CHICKEN_PAR2_1
)
8619 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT
);
8621 lpt_init_clock_gating(dev_priv
);
8623 /* WaDisableDopClockGating:bdw
8625 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
8628 I915_WRITE(GEN6_UCGCTL1
,
8629 I915_READ(GEN6_UCGCTL1
) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE
);
8632 static void hsw_init_clock_gating(struct drm_i915_private
*dev_priv
)
8634 /* L3 caching of data atomics doesn't work -- disable it. */
8635 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
8636 I915_WRITE(HSW_ROW_CHICKEN3
,
8637 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
8639 /* This is required by WaCatErrorRejectionIssue:hsw */
8640 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
8641 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
8642 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
8644 /* WaVSRefCountFullforceMissDisable:hsw */
8645 I915_WRITE(GEN7_FF_THREAD_MODE
,
8646 I915_READ(GEN7_FF_THREAD_MODE
) & ~GEN7_FF_VS_REF_CNT_FFME
);
8648 /* WaDisable_RenderCache_OperationalFlush:hsw */
8649 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8651 /* enable HiZ Raw Stall Optimization */
8652 I915_WRITE(CACHE_MODE_0_GEN7
,
8653 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
8655 /* WaDisable4x2SubspanOptimization:hsw */
8656 I915_WRITE(CACHE_MODE_1
,
8657 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
8660 * BSpec recommends 8x4 when MSAA is used,
8661 * however in practice 16x4 seems fastest.
8663 * Note that PS/WM thread counts depend on the WIZ hashing
8664 * disable bit, which we don't touch here, but it's good
8665 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8667 I915_WRITE(GEN7_GT_MODE
,
8668 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
8670 /* WaSampleCChickenBitEnable:hsw */
8671 I915_WRITE(HALF_SLICE_CHICKEN3
,
8672 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE
));
8674 /* WaSwitchSolVfFArbitrationPriority:hsw */
8675 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
8677 lpt_init_clock_gating(dev_priv
);
8680 static void ivb_init_clock_gating(struct drm_i915_private
*dev_priv
)
8684 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
8686 /* WaDisableEarlyCull:ivb */
8687 I915_WRITE(_3D_CHICKEN3
,
8688 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
8690 /* WaDisableBackToBackFlipFix:ivb */
8691 I915_WRITE(IVB_CHICKEN3
,
8692 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
8693 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
8695 /* WaDisablePSDDualDispatchEnable:ivb */
8696 if (IS_IVB_GT1(dev_priv
))
8697 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
8698 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
8700 /* WaDisable_RenderCache_OperationalFlush:ivb */
8701 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8703 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
8704 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
8705 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
8707 /* WaApplyL3ControlAndL3ChickenMode:ivb */
8708 I915_WRITE(GEN7_L3CNTLREG1
,
8709 GEN7_WA_FOR_GEN7_L3_CONTROL
);
8710 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
8711 GEN7_WA_L3_CHICKEN_MODE
);
8712 if (IS_IVB_GT1(dev_priv
))
8713 I915_WRITE(GEN7_ROW_CHICKEN2
,
8714 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
8716 /* must write both registers */
8717 I915_WRITE(GEN7_ROW_CHICKEN2
,
8718 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
8719 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
8720 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
8723 /* WaForceL3Serialization:ivb */
8724 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
8725 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
8728 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8729 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
8731 I915_WRITE(GEN6_UCGCTL2
,
8732 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
8734 /* This is required by WaCatErrorRejectionIssue:ivb */
8735 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
8736 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
8737 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
8739 g4x_disable_trickle_feed(dev_priv
);
8741 gen7_setup_fixed_func_scheduler(dev_priv
);
8743 if (0) { /* causes HiZ corruption on ivb:gt1 */
8744 /* enable HiZ Raw Stall Optimization */
8745 I915_WRITE(CACHE_MODE_0_GEN7
,
8746 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
8749 /* WaDisable4x2SubspanOptimization:ivb */
8750 I915_WRITE(CACHE_MODE_1
,
8751 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
8754 * BSpec recommends 8x4 when MSAA is used,
8755 * however in practice 16x4 seems fastest.
8757 * Note that PS/WM thread counts depend on the WIZ hashing
8758 * disable bit, which we don't touch here, but it's good
8759 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8761 I915_WRITE(GEN7_GT_MODE
,
8762 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
8764 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
8765 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
8766 snpcr
|= GEN6_MBC_SNPCR_MED
;
8767 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
8769 if (!HAS_PCH_NOP(dev_priv
))
8770 cpt_init_clock_gating(dev_priv
);
8772 gen6_check_mch_setup(dev_priv
);
8775 static void vlv_init_clock_gating(struct drm_i915_private
*dev_priv
)
8777 /* WaDisableEarlyCull:vlv */
8778 I915_WRITE(_3D_CHICKEN3
,
8779 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
8781 /* WaDisableBackToBackFlipFix:vlv */
8782 I915_WRITE(IVB_CHICKEN3
,
8783 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
8784 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
8786 /* WaPsdDispatchEnable:vlv */
8787 /* WaDisablePSDDualDispatchEnable:vlv */
8788 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
8789 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
8790 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
8792 /* WaDisable_RenderCache_OperationalFlush:vlv */
8793 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8795 /* WaForceL3Serialization:vlv */
8796 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
8797 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
8799 /* WaDisableDopClockGating:vlv */
8800 I915_WRITE(GEN7_ROW_CHICKEN2
,
8801 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
8803 /* This is required by WaCatErrorRejectionIssue:vlv */
8804 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
8805 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
8806 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
8808 gen7_setup_fixed_func_scheduler(dev_priv
);
8811 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8812 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
8814 I915_WRITE(GEN6_UCGCTL2
,
8815 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
8817 /* WaDisableL3Bank2xClockGate:vlv
8818 * Disabling L3 clock gating- MMIO 940c[25] = 1
8819 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
8820 I915_WRITE(GEN7_UCGCTL4
,
8821 I915_READ(GEN7_UCGCTL4
) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
8824 * BSpec says this must be set, even though
8825 * WaDisable4x2SubspanOptimization isn't listed for VLV.
8827 I915_WRITE(CACHE_MODE_1
,
8828 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
8831 * BSpec recommends 8x4 when MSAA is used,
8832 * however in practice 16x4 seems fastest.
8834 * Note that PS/WM thread counts depend on the WIZ hashing
8835 * disable bit, which we don't touch here, but it's good
8836 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8838 I915_WRITE(GEN7_GT_MODE
,
8839 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
8842 * WaIncreaseL3CreditsForVLVB0:vlv
8843 * This is the hardware default actually.
8845 I915_WRITE(GEN7_L3SQCREG1
, VLV_B0_WA_L3SQCREG1_VALUE
);
8848 * WaDisableVLVClockGating_VBIIssue:vlv
8849 * Disable clock gating on th GCFG unit to prevent a delay
8850 * in the reporting of vblank events.
8852 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, GCFG_DIS
);
8855 static void chv_init_clock_gating(struct drm_i915_private
*dev_priv
)
8857 /* WaVSRefCountFullforceMissDisable:chv */
8858 /* WaDSRefCountFullforceMissDisable:chv */
8859 I915_WRITE(GEN7_FF_THREAD_MODE
,
8860 I915_READ(GEN7_FF_THREAD_MODE
) &
8861 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
8863 /* WaDisableSemaphoreAndSyncFlipWait:chv */
8864 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
8865 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
8867 /* WaDisableCSUnitClockGating:chv */
8868 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
8869 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
8871 /* WaDisableSDEUnitClockGating:chv */
8872 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
8873 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
8876 * WaProgramL3SqcReg1Default:chv
8877 * See gfxspecs/Related Documents/Performance Guide/
8878 * LSQC Setting Recommendations.
8880 gen8_set_l3sqc_credits(dev_priv
, 38, 2);
8883 * GTT cache may not work with big pages, so if those
8884 * are ever enabled GTT cache may need to be disabled.
8886 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
8889 static void g4x_init_clock_gating(struct drm_i915_private
*dev_priv
)
8891 uint32_t dspclk_gate
;
8893 I915_WRITE(RENCLK_GATE_D1
, 0);
8894 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
8895 GS_UNIT_CLOCK_GATE_DISABLE
|
8896 CL_UNIT_CLOCK_GATE_DISABLE
);
8897 I915_WRITE(RAMCLK_GATE_D
, 0);
8898 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
8899 OVRUNIT_CLOCK_GATE_DISABLE
|
8900 OVCUNIT_CLOCK_GATE_DISABLE
;
8901 if (IS_GM45(dev_priv
))
8902 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
8903 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
8905 /* WaDisableRenderCachePipelinedFlush */
8906 I915_WRITE(CACHE_MODE_0
,
8907 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
8909 /* WaDisable_RenderCache_OperationalFlush:g4x */
8910 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8912 g4x_disable_trickle_feed(dev_priv
);
8915 static void i965gm_init_clock_gating(struct drm_i915_private
*dev_priv
)
8917 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
8918 I915_WRITE(RENCLK_GATE_D2
, 0);
8919 I915_WRITE(DSPCLK_GATE_D
, 0);
8920 I915_WRITE(RAMCLK_GATE_D
, 0);
8921 I915_WRITE16(DEUC
, 0);
8922 I915_WRITE(MI_ARB_STATE
,
8923 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
8925 /* WaDisable_RenderCache_OperationalFlush:gen4 */
8926 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8929 static void i965g_init_clock_gating(struct drm_i915_private
*dev_priv
)
8931 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
8932 I965_RCC_CLOCK_GATE_DISABLE
|
8933 I965_RCPB_CLOCK_GATE_DISABLE
|
8934 I965_ISC_CLOCK_GATE_DISABLE
|
8935 I965_FBC_CLOCK_GATE_DISABLE
);
8936 I915_WRITE(RENCLK_GATE_D2
, 0);
8937 I915_WRITE(MI_ARB_STATE
,
8938 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
8940 /* WaDisable_RenderCache_OperationalFlush:gen4 */
8941 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8944 static void gen3_init_clock_gating(struct drm_i915_private
*dev_priv
)
8946 u32 dstate
= I915_READ(D_STATE
);
8948 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
8949 DSTATE_DOT_CLOCK_GATING
;
8950 I915_WRITE(D_STATE
, dstate
);
8952 if (IS_PINEVIEW(dev_priv
))
8953 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
8955 /* IIR "flip pending" means done if this bit is set */
8956 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
8958 /* interrupts should cause a wake up from C3 */
8959 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN
));
8961 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
8962 I915_WRITE(MI_ARB_STATE
, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
8964 I915_WRITE(MI_ARB_STATE
,
8965 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
8968 static void i85x_init_clock_gating(struct drm_i915_private
*dev_priv
)
8970 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
8972 /* interrupts should cause a wake up from C3 */
8973 I915_WRITE(MI_STATE
, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN
) |
8974 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE
));
8976 I915_WRITE(MEM_MODE
,
8977 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE
));
8980 static void i830_init_clock_gating(struct drm_i915_private
*dev_priv
)
8982 I915_WRITE(MEM_MODE
,
8983 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE
) |
8984 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE
));
8987 void intel_init_clock_gating(struct drm_i915_private
*dev_priv
)
8989 dev_priv
->display
.init_clock_gating(dev_priv
);
8992 void intel_suspend_hw(struct drm_i915_private
*dev_priv
)
8994 if (HAS_PCH_LPT(dev_priv
))
8995 lpt_suspend_hw(dev_priv
);
8998 static void nop_init_clock_gating(struct drm_i915_private
*dev_priv
)
9000 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
9004 * intel_init_clock_gating_hooks - setup the clock gating hooks
9005 * @dev_priv: device private
9007 * Setup the hooks that configure which clocks of a given platform can be
9008 * gated and also apply various GT and display specific workarounds for these
9009 * platforms. Note that some GT specific workarounds are applied separately
9010 * when GPU contexts or batchbuffers start their execution.
9012 void intel_init_clock_gating_hooks(struct drm_i915_private
*dev_priv
)
9014 if (IS_CANNONLAKE(dev_priv
))
9015 dev_priv
->display
.init_clock_gating
= cnl_init_clock_gating
;
9016 else if (IS_COFFEELAKE(dev_priv
))
9017 dev_priv
->display
.init_clock_gating
= cfl_init_clock_gating
;
9018 else if (IS_SKYLAKE(dev_priv
))
9019 dev_priv
->display
.init_clock_gating
= skl_init_clock_gating
;
9020 else if (IS_KABYLAKE(dev_priv
))
9021 dev_priv
->display
.init_clock_gating
= kbl_init_clock_gating
;
9022 else if (IS_BROXTON(dev_priv
))
9023 dev_priv
->display
.init_clock_gating
= bxt_init_clock_gating
;
9024 else if (IS_GEMINILAKE(dev_priv
))
9025 dev_priv
->display
.init_clock_gating
= glk_init_clock_gating
;
9026 else if (IS_BROADWELL(dev_priv
))
9027 dev_priv
->display
.init_clock_gating
= bdw_init_clock_gating
;
9028 else if (IS_CHERRYVIEW(dev_priv
))
9029 dev_priv
->display
.init_clock_gating
= chv_init_clock_gating
;
9030 else if (IS_HASWELL(dev_priv
))
9031 dev_priv
->display
.init_clock_gating
= hsw_init_clock_gating
;
9032 else if (IS_IVYBRIDGE(dev_priv
))
9033 dev_priv
->display
.init_clock_gating
= ivb_init_clock_gating
;
9034 else if (IS_VALLEYVIEW(dev_priv
))
9035 dev_priv
->display
.init_clock_gating
= vlv_init_clock_gating
;
9036 else if (IS_GEN6(dev_priv
))
9037 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
9038 else if (IS_GEN5(dev_priv
))
9039 dev_priv
->display
.init_clock_gating
= ilk_init_clock_gating
;
9040 else if (IS_G4X(dev_priv
))
9041 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
9042 else if (IS_I965GM(dev_priv
))
9043 dev_priv
->display
.init_clock_gating
= i965gm_init_clock_gating
;
9044 else if (IS_I965G(dev_priv
))
9045 dev_priv
->display
.init_clock_gating
= i965g_init_clock_gating
;
9046 else if (IS_GEN3(dev_priv
))
9047 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
9048 else if (IS_I85X(dev_priv
) || IS_I865G(dev_priv
))
9049 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
9050 else if (IS_GEN2(dev_priv
))
9051 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
9053 MISSING_CASE(INTEL_DEVID(dev_priv
));
9054 dev_priv
->display
.init_clock_gating
= nop_init_clock_gating
;
9058 /* Set up chip specific power management-related functions */
9059 void intel_init_pm(struct drm_i915_private
*dev_priv
)
9061 intel_fbc_init(dev_priv
);
9064 if (IS_PINEVIEW(dev_priv
))
9065 i915_pineview_get_mem_freq(dev_priv
);
9066 else if (IS_GEN5(dev_priv
))
9067 i915_ironlake_get_mem_freq(dev_priv
);
9069 /* For FIFO watermark updates */
9070 if (INTEL_GEN(dev_priv
) >= 9) {
9071 skl_setup_wm_latency(dev_priv
);
9072 dev_priv
->display
.initial_watermarks
= skl_initial_wm
;
9073 dev_priv
->display
.atomic_update_watermarks
= skl_atomic_update_crtc_wm
;
9074 dev_priv
->display
.compute_global_watermarks
= skl_compute_wm
;
9075 } else if (HAS_PCH_SPLIT(dev_priv
)) {
9076 ilk_setup_wm_latency(dev_priv
);
9078 if ((IS_GEN5(dev_priv
) && dev_priv
->wm
.pri_latency
[1] &&
9079 dev_priv
->wm
.spr_latency
[1] && dev_priv
->wm
.cur_latency
[1]) ||
9080 (!IS_GEN5(dev_priv
) && dev_priv
->wm
.pri_latency
[0] &&
9081 dev_priv
->wm
.spr_latency
[0] && dev_priv
->wm
.cur_latency
[0])) {
9082 dev_priv
->display
.compute_pipe_wm
= ilk_compute_pipe_wm
;
9083 dev_priv
->display
.compute_intermediate_wm
=
9084 ilk_compute_intermediate_wm
;
9085 dev_priv
->display
.initial_watermarks
=
9086 ilk_initial_watermarks
;
9087 dev_priv
->display
.optimize_watermarks
=
9088 ilk_optimize_watermarks
;
9090 DRM_DEBUG_KMS("Failed to read display plane latency. "
9093 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
9094 vlv_setup_wm_latency(dev_priv
);
9095 dev_priv
->display
.compute_pipe_wm
= vlv_compute_pipe_wm
;
9096 dev_priv
->display
.compute_intermediate_wm
= vlv_compute_intermediate_wm
;
9097 dev_priv
->display
.initial_watermarks
= vlv_initial_watermarks
;
9098 dev_priv
->display
.optimize_watermarks
= vlv_optimize_watermarks
;
9099 dev_priv
->display
.atomic_update_watermarks
= vlv_atomic_update_fifo
;
9100 } else if (IS_G4X(dev_priv
)) {
9101 g4x_setup_wm_latency(dev_priv
);
9102 dev_priv
->display
.compute_pipe_wm
= g4x_compute_pipe_wm
;
9103 dev_priv
->display
.compute_intermediate_wm
= g4x_compute_intermediate_wm
;
9104 dev_priv
->display
.initial_watermarks
= g4x_initial_watermarks
;
9105 dev_priv
->display
.optimize_watermarks
= g4x_optimize_watermarks
;
9106 } else if (IS_PINEVIEW(dev_priv
)) {
9107 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv
),
9110 dev_priv
->mem_freq
)) {
9111 DRM_INFO("failed to find known CxSR latency "
9112 "(found ddr%s fsb freq %d, mem freq %d), "
9114 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
9115 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
9116 /* Disable CxSR and never update its watermark again */
9117 intel_set_memory_cxsr(dev_priv
, false);
9118 dev_priv
->display
.update_wm
= NULL
;
9120 dev_priv
->display
.update_wm
= pineview_update_wm
;
9121 } else if (IS_GEN4(dev_priv
)) {
9122 dev_priv
->display
.update_wm
= i965_update_wm
;
9123 } else if (IS_GEN3(dev_priv
)) {
9124 dev_priv
->display
.update_wm
= i9xx_update_wm
;
9125 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
9126 } else if (IS_GEN2(dev_priv
)) {
9127 if (INTEL_INFO(dev_priv
)->num_pipes
== 1) {
9128 dev_priv
->display
.update_wm
= i845_update_wm
;
9129 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
9131 dev_priv
->display
.update_wm
= i9xx_update_wm
;
9132 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
9135 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
9139 static inline int gen6_check_mailbox_status(struct drm_i915_private
*dev_priv
)
9142 I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_ERROR_MASK
;
9145 case GEN6_PCODE_SUCCESS
:
9147 case GEN6_PCODE_UNIMPLEMENTED_CMD
:
9149 case GEN6_PCODE_ILLEGAL_CMD
:
9151 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
:
9152 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
:
9154 case GEN6_PCODE_TIMEOUT
:
9157 MISSING_CASE(flags
);
9162 static inline int gen7_check_mailbox_status(struct drm_i915_private
*dev_priv
)
9165 I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_ERROR_MASK
;
9168 case GEN6_PCODE_SUCCESS
:
9170 case GEN6_PCODE_ILLEGAL_CMD
:
9172 case GEN7_PCODE_TIMEOUT
:
9174 case GEN7_PCODE_ILLEGAL_DATA
:
9176 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
:
9179 MISSING_CASE(flags
);
9184 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
)
9188 WARN_ON(!mutex_is_locked(&dev_priv
->pcu_lock
));
9190 /* GEN6_PCODE_* are outside of the forcewake domain, we can
9191 * use te fw I915_READ variants to reduce the amount of work
9192 * required when reading/writing.
9195 if (I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
9196 DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps\n",
9197 mbox
, __builtin_return_address(0));
9201 I915_WRITE_FW(GEN6_PCODE_DATA
, *val
);
9202 I915_WRITE_FW(GEN6_PCODE_DATA1
, 0);
9203 I915_WRITE_FW(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
9205 if (__intel_wait_for_register_fw(dev_priv
,
9206 GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
, 0,
9208 DRM_ERROR("timeout waiting for pcode read (from mbox %x) to finish for %ps\n",
9209 mbox
, __builtin_return_address(0));
9213 *val
= I915_READ_FW(GEN6_PCODE_DATA
);
9214 I915_WRITE_FW(GEN6_PCODE_DATA
, 0);
9216 if (INTEL_GEN(dev_priv
) > 6)
9217 status
= gen7_check_mailbox_status(dev_priv
);
9219 status
= gen6_check_mailbox_status(dev_priv
);
9222 DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
9223 mbox
, __builtin_return_address(0), status
);
9230 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
,
9235 WARN_ON(!mutex_is_locked(&dev_priv
->pcu_lock
));
9237 /* GEN6_PCODE_* are outside of the forcewake domain, we can
9238 * use te fw I915_READ variants to reduce the amount of work
9239 * required when reading/writing.
9242 if (I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
9243 DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps\n",
9244 val
, mbox
, __builtin_return_address(0));
9248 I915_WRITE_FW(GEN6_PCODE_DATA
, val
);
9249 I915_WRITE_FW(GEN6_PCODE_DATA1
, 0);
9250 I915_WRITE_FW(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
9252 if (__intel_wait_for_register_fw(dev_priv
,
9253 GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
, 0,
9255 DRM_ERROR("timeout waiting for pcode write of 0x%08x to mbox %x to finish for %ps\n",
9256 val
, mbox
, __builtin_return_address(0));
9260 I915_WRITE_FW(GEN6_PCODE_DATA
, 0);
9262 if (INTEL_GEN(dev_priv
) > 6)
9263 status
= gen7_check_mailbox_status(dev_priv
);
9265 status
= gen6_check_mailbox_status(dev_priv
);
9268 DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
9269 val
, mbox
, __builtin_return_address(0), status
);
9276 static bool skl_pcode_try_request(struct drm_i915_private
*dev_priv
, u32 mbox
,
9277 u32 request
, u32 reply_mask
, u32 reply
,
9282 *status
= sandybridge_pcode_read(dev_priv
, mbox
, &val
);
9284 return *status
|| ((val
& reply_mask
) == reply
);
9288 * skl_pcode_request - send PCODE request until acknowledgment
9289 * @dev_priv: device private
9290 * @mbox: PCODE mailbox ID the request is targeted for
9291 * @request: request ID
9292 * @reply_mask: mask used to check for request acknowledgment
9293 * @reply: value used to check for request acknowledgment
9294 * @timeout_base_ms: timeout for polling with preemption enabled
9296 * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
9297 * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
9298 * The request is acknowledged once the PCODE reply dword equals @reply after
9299 * applying @reply_mask. Polling is first attempted with preemption enabled
9300 * for @timeout_base_ms and if this times out for another 50 ms with
9301 * preemption disabled.
9303 * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
9304 * other error as reported by PCODE.
9306 int skl_pcode_request(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 request
,
9307 u32 reply_mask
, u32 reply
, int timeout_base_ms
)
9312 WARN_ON(!mutex_is_locked(&dev_priv
->pcu_lock
));
9314 #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
9318 * Prime the PCODE by doing a request first. Normally it guarantees
9319 * that a subsequent request, at most @timeout_base_ms later, succeeds.
9320 * _wait_for() doesn't guarantee when its passed condition is evaluated
9321 * first, so send the first request explicitly.
9327 ret
= _wait_for(COND
, timeout_base_ms
* 1000, 10);
9332 * The above can time out if the number of requests was low (2 in the
9333 * worst case) _and_ PCODE was busy for some reason even after a
9334 * (queued) request and @timeout_base_ms delay. As a workaround retry
9335 * the poll with preemption disabled to maximize the number of
9336 * requests. Increase the timeout from @timeout_base_ms to 50ms to
9337 * account for interrupts that could reduce the number of these
9338 * requests, and for any quirks of the PCODE firmware that delays
9339 * the request completion.
9341 DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
9342 WARN_ON_ONCE(timeout_base_ms
> 3);
9344 ret
= wait_for_atomic(COND
, 50);
9348 return ret
? ret
: status
;
9352 static int byt_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
9354 struct intel_rps
*rps
= &dev_priv
->gt_pm
.rps
;
9358 * Slow = Fast = GPLL ref * N
9360 return DIV_ROUND_CLOSEST(rps
->gpll_ref_freq
* (val
- 0xb7), 1000);
9363 static int byt_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
9365 struct intel_rps
*rps
= &dev_priv
->gt_pm
.rps
;
9367 return DIV_ROUND_CLOSEST(1000 * val
, rps
->gpll_ref_freq
) + 0xb7;
9370 static int chv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
9372 struct intel_rps
*rps
= &dev_priv
->gt_pm
.rps
;
9376 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
9378 return DIV_ROUND_CLOSEST(rps
->gpll_ref_freq
* val
, 2 * 2 * 1000);
9381 static int chv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
9383 struct intel_rps
*rps
= &dev_priv
->gt_pm
.rps
;
9385 /* CHV needs even values */
9386 return DIV_ROUND_CLOSEST(2 * 1000 * val
, rps
->gpll_ref_freq
) * 2;
9389 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
9391 if (INTEL_GEN(dev_priv
) >= 9)
9392 return DIV_ROUND_CLOSEST(val
* GT_FREQUENCY_MULTIPLIER
,
9394 else if (IS_CHERRYVIEW(dev_priv
))
9395 return chv_gpu_freq(dev_priv
, val
);
9396 else if (IS_VALLEYVIEW(dev_priv
))
9397 return byt_gpu_freq(dev_priv
, val
);
9399 return val
* GT_FREQUENCY_MULTIPLIER
;
9402 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
9404 if (INTEL_GEN(dev_priv
) >= 9)
9405 return DIV_ROUND_CLOSEST(val
* GEN9_FREQ_SCALER
,
9406 GT_FREQUENCY_MULTIPLIER
);
9407 else if (IS_CHERRYVIEW(dev_priv
))
9408 return chv_freq_opcode(dev_priv
, val
);
9409 else if (IS_VALLEYVIEW(dev_priv
))
9410 return byt_freq_opcode(dev_priv
, val
);
9412 return DIV_ROUND_CLOSEST(val
, GT_FREQUENCY_MULTIPLIER
);
9415 void intel_pm_setup(struct drm_i915_private
*dev_priv
)
9417 mutex_init(&dev_priv
->pcu_lock
);
9419 INIT_DELAYED_WORK(&dev_priv
->gt_pm
.autoenable_work
,
9420 __intel_autoenable_gt_powersave
);
9421 atomic_set(&dev_priv
->gt_pm
.rps
.num_waiters
, 0);
9423 dev_priv
->runtime_pm
.suspended
= false;
9424 atomic_set(&dev_priv
->runtime_pm
.wakeref_count
, 0);
9427 static u64
vlv_residency_raw(struct drm_i915_private
*dev_priv
,
9428 const i915_reg_t reg
)
9430 u32 lower
, upper
, tmp
;
9433 /* The register accessed do not need forcewake. We borrow
9434 * uncore lock to prevent concurrent access to range reg.
9436 spin_lock_irq(&dev_priv
->uncore
.lock
);
9438 /* vlv and chv residency counters are 40 bits in width.
9439 * With a control bit, we can choose between upper or lower
9440 * 32bit window into this counter.
9442 * Although we always use the counter in high-range mode elsewhere,
9443 * userspace may attempt to read the value before rc6 is initialised,
9444 * before we have set the default VLV_COUNTER_CONTROL value. So always
9445 * set the high bit to be safe.
9447 I915_WRITE_FW(VLV_COUNTER_CONTROL
,
9448 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
));
9449 upper
= I915_READ_FW(reg
);
9453 I915_WRITE_FW(VLV_COUNTER_CONTROL
,
9454 _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH
));
9455 lower
= I915_READ_FW(reg
);
9457 I915_WRITE_FW(VLV_COUNTER_CONTROL
,
9458 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
));
9459 upper
= I915_READ_FW(reg
);
9460 } while (upper
!= tmp
&& --loop
);
9462 /* Everywhere else we always use VLV_COUNTER_CONTROL with the
9463 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
9467 spin_unlock_irq(&dev_priv
->uncore
.lock
);
9469 return lower
| (u64
)upper
<< 8;
9472 u64
intel_rc6_residency_us(struct drm_i915_private
*dev_priv
,
9473 const i915_reg_t reg
)
9475 u64 time_hw
, units
, div
;
9477 if (!intel_rc6_enabled())
9480 intel_runtime_pm_get(dev_priv
);
9482 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
9483 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
9485 div
= dev_priv
->czclk_freq
;
9487 time_hw
= vlv_residency_raw(dev_priv
, reg
);
9488 } else if (IS_GEN9_LP(dev_priv
)) {
9490 div
= 1200; /* 833.33ns */
9492 time_hw
= I915_READ(reg
);
9494 units
= 128000; /* 1.28us */
9497 time_hw
= I915_READ(reg
);
9500 intel_runtime_pm_put(dev_priv
);
9501 return DIV_ROUND_UP_ULL(time_hw
* units
, div
);