2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
29 #include <drm/drm_plane_helper.h>
31 #include "intel_drv.h"
32 #include "../../../platform/x86/intel_ips.h"
33 #include <linux/module.h>
34 #include <drm/drm_atomic_helper.h>
39 * RC6 is a special power stage which allows the GPU to enter an very
40 * low-voltage mode when idle, using down to 0V while at this stage. This
41 * stage is entered automatically when the GPU is idle when RC6 support is
42 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
44 * There are different RC6 modes available in Intel GPU, which differentiate
45 * among each other with the latency required to enter and leave RC6 and
46 * voltage consumed by the GPU in different states.
48 * The combination of the following flags define which states GPU is allowed
49 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
50 * RC6pp is deepest RC6. Their support by hardware varies according to the
51 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
52 * which brings the most power savings; deeper states save more power, but
53 * require higher latency to switch to and wake up.
55 #define INTEL_RC6_ENABLE (1<<0)
56 #define INTEL_RC6p_ENABLE (1<<1)
57 #define INTEL_RC6pp_ENABLE (1<<2)
59 static void gen9_init_clock_gating(struct drm_i915_private
*dev_priv
)
61 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
62 I915_WRITE(CHICKEN_PAR1_1
,
63 I915_READ(CHICKEN_PAR1_1
) | SKL_EDP_PSR_FIX_RDWRAP
);
65 I915_WRITE(GEN8_CONFIG0
,
66 I915_READ(GEN8_CONFIG0
) | GEN9_DEFAULT_FIXES
);
68 /* WaEnableChickenDCPR:skl,bxt,kbl,glk */
69 I915_WRITE(GEN8_CHICKEN_DCPR_1
,
70 I915_READ(GEN8_CHICKEN_DCPR_1
) | MASK_WAKEMEM
);
72 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
73 /* WaFbcWakeMemOn:skl,bxt,kbl,glk */
74 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
76 DISP_FBC_MEMORY_WAKE
);
78 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
79 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
80 ILK_DPFC_DISABLE_DUMMY0
);
83 static void bxt_init_clock_gating(struct drm_i915_private
*dev_priv
)
85 gen9_init_clock_gating(dev_priv
);
87 /* WaDisableSDEUnitClockGating:bxt */
88 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
89 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
93 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
95 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
96 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ
);
99 * Wa: Backlight PWM may stop in the asserted state, causing backlight
102 I915_WRITE(GEN9_CLKGATE_DIS_0
, I915_READ(GEN9_CLKGATE_DIS_0
) |
103 PWM1_GATING_DIS
| PWM2_GATING_DIS
);
106 static void glk_init_clock_gating(struct drm_i915_private
*dev_priv
)
108 gen9_init_clock_gating(dev_priv
);
111 * WaDisablePWMClockGating:glk
112 * Backlight PWM may stop in the asserted state, causing backlight
115 I915_WRITE(GEN9_CLKGATE_DIS_0
, I915_READ(GEN9_CLKGATE_DIS_0
) |
116 PWM1_GATING_DIS
| PWM2_GATING_DIS
);
118 /* WaDDIIOTimeout:glk */
119 if (IS_GLK_REVID(dev_priv
, 0, GLK_REVID_A1
)) {
120 u32 val
= I915_READ(CHICKEN_MISC_2
);
121 val
&= ~(GLK_CL0_PWR_DOWN
|
124 I915_WRITE(CHICKEN_MISC_2
, val
);
129 static void i915_pineview_get_mem_freq(struct drm_i915_private
*dev_priv
)
133 tmp
= I915_READ(CLKCFG
);
135 switch (tmp
& CLKCFG_FSB_MASK
) {
137 dev_priv
->fsb_freq
= 533; /* 133*4 */
140 dev_priv
->fsb_freq
= 800; /* 200*4 */
143 dev_priv
->fsb_freq
= 667; /* 167*4 */
146 dev_priv
->fsb_freq
= 400; /* 100*4 */
150 switch (tmp
& CLKCFG_MEM_MASK
) {
152 dev_priv
->mem_freq
= 533;
155 dev_priv
->mem_freq
= 667;
158 dev_priv
->mem_freq
= 800;
162 /* detect pineview DDR3 setting */
163 tmp
= I915_READ(CSHRDDR3CTL
);
164 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
167 static void i915_ironlake_get_mem_freq(struct drm_i915_private
*dev_priv
)
171 ddrpll
= I915_READ16(DDRMPLL1
);
172 csipll
= I915_READ16(CSIPLL0
);
174 switch (ddrpll
& 0xff) {
176 dev_priv
->mem_freq
= 800;
179 dev_priv
->mem_freq
= 1066;
182 dev_priv
->mem_freq
= 1333;
185 dev_priv
->mem_freq
= 1600;
188 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
190 dev_priv
->mem_freq
= 0;
194 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
196 switch (csipll
& 0x3ff) {
198 dev_priv
->fsb_freq
= 3200;
201 dev_priv
->fsb_freq
= 3733;
204 dev_priv
->fsb_freq
= 4266;
207 dev_priv
->fsb_freq
= 4800;
210 dev_priv
->fsb_freq
= 5333;
213 dev_priv
->fsb_freq
= 5866;
216 dev_priv
->fsb_freq
= 6400;
219 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
221 dev_priv
->fsb_freq
= 0;
225 if (dev_priv
->fsb_freq
== 3200) {
226 dev_priv
->ips
.c_m
= 0;
227 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
228 dev_priv
->ips
.c_m
= 1;
230 dev_priv
->ips
.c_m
= 2;
234 static const struct cxsr_latency cxsr_latency_table
[] = {
235 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
236 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
237 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
238 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
239 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
241 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
242 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
243 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
244 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
245 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
247 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
248 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
249 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
250 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
251 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
253 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
254 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
255 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
256 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
257 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
259 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
260 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
261 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
262 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
263 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
265 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
266 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
267 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
268 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
269 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
272 static const struct cxsr_latency
*intel_get_cxsr_latency(bool is_desktop
,
277 const struct cxsr_latency
*latency
;
280 if (fsb
== 0 || mem
== 0)
283 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
284 latency
= &cxsr_latency_table
[i
];
285 if (is_desktop
== latency
->is_desktop
&&
286 is_ddr3
== latency
->is_ddr3
&&
287 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
291 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
296 static void chv_set_memory_dvfs(struct drm_i915_private
*dev_priv
, bool enable
)
300 mutex_lock(&dev_priv
->rps
.hw_lock
);
302 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
304 val
&= ~FORCE_DDR_HIGH_FREQ
;
306 val
|= FORCE_DDR_HIGH_FREQ
;
307 val
&= ~FORCE_DDR_LOW_FREQ
;
308 val
|= FORCE_DDR_FREQ_REQ_ACK
;
309 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
311 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
312 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3))
313 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
315 mutex_unlock(&dev_priv
->rps
.hw_lock
);
318 static void chv_set_memory_pm5(struct drm_i915_private
*dev_priv
, bool enable
)
322 mutex_lock(&dev_priv
->rps
.hw_lock
);
324 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
326 val
|= DSP_MAXFIFO_PM5_ENABLE
;
328 val
&= ~DSP_MAXFIFO_PM5_ENABLE
;
329 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
331 mutex_unlock(&dev_priv
->rps
.hw_lock
);
334 #define FW_WM(value, plane) \
335 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
337 static bool _intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
342 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
343 was_enabled
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
344 I915_WRITE(FW_BLC_SELF_VLV
, enable
? FW_CSPWRDWNEN
: 0);
345 POSTING_READ(FW_BLC_SELF_VLV
);
346 } else if (IS_G4X(dev_priv
) || IS_I965GM(dev_priv
)) {
347 was_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
348 I915_WRITE(FW_BLC_SELF
, enable
? FW_BLC_SELF_EN
: 0);
349 POSTING_READ(FW_BLC_SELF
);
350 } else if (IS_PINEVIEW(dev_priv
)) {
351 val
= I915_READ(DSPFW3
);
352 was_enabled
= val
& PINEVIEW_SELF_REFRESH_EN
;
354 val
|= PINEVIEW_SELF_REFRESH_EN
;
356 val
&= ~PINEVIEW_SELF_REFRESH_EN
;
357 I915_WRITE(DSPFW3
, val
);
358 POSTING_READ(DSPFW3
);
359 } else if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
)) {
360 was_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
361 val
= enable
? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN
) :
362 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN
);
363 I915_WRITE(FW_BLC_SELF
, val
);
364 POSTING_READ(FW_BLC_SELF
);
365 } else if (IS_I915GM(dev_priv
)) {
367 * FIXME can't find a bit like this for 915G, and
368 * and yet it does have the related watermark in
369 * FW_BLC_SELF. What's going on?
371 was_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
372 val
= enable
? _MASKED_BIT_ENABLE(INSTPM_SELF_EN
) :
373 _MASKED_BIT_DISABLE(INSTPM_SELF_EN
);
374 I915_WRITE(INSTPM
, val
);
375 POSTING_READ(INSTPM
);
380 trace_intel_memory_cxsr(dev_priv
, was_enabled
, enable
);
382 DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
383 enableddisabled(enable
),
384 enableddisabled(was_enabled
));
389 bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
393 mutex_lock(&dev_priv
->wm
.wm_mutex
);
394 ret
= _intel_set_memory_cxsr(dev_priv
, enable
);
395 dev_priv
->wm
.vlv
.cxsr
= enable
;
396 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
402 * Latency for FIFO fetches is dependent on several factors:
403 * - memory configuration (speed, channels)
405 * - current MCH state
406 * It can be fairly high in some situations, so here we assume a fairly
407 * pessimal value. It's a tradeoff between extra memory fetches (if we
408 * set this value too high, the FIFO will fetch frequently to stay full)
409 * and power consumption (set it too low to save power and we might see
410 * FIFO underruns and display "flicker").
412 * A value of 5us seems to be a good balance; safe for very low end
413 * platforms but not overly aggressive on lower latency configs.
415 static const int pessimal_latency_ns
= 5000;
417 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
418 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
420 static void vlv_get_fifo_size(struct intel_crtc_state
*crtc_state
)
422 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
423 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
424 struct vlv_fifo_state
*fifo_state
= &crtc_state
->wm
.vlv
.fifo_state
;
425 enum pipe pipe
= crtc
->pipe
;
426 int sprite0_start
, sprite1_start
;
429 uint32_t dsparb
, dsparb2
, dsparb3
;
431 dsparb
= I915_READ(DSPARB
);
432 dsparb2
= I915_READ(DSPARB2
);
433 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 0, 0);
434 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 8, 4);
437 dsparb
= I915_READ(DSPARB
);
438 dsparb2
= I915_READ(DSPARB2
);
439 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 16, 8);
440 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 24, 12);
443 dsparb2
= I915_READ(DSPARB2
);
444 dsparb3
= I915_READ(DSPARB3
);
445 sprite0_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 0, 16);
446 sprite1_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 8, 20);
453 fifo_state
->plane
[PLANE_PRIMARY
] = sprite0_start
;
454 fifo_state
->plane
[PLANE_SPRITE0
] = sprite1_start
- sprite0_start
;
455 fifo_state
->plane
[PLANE_SPRITE1
] = 511 - sprite1_start
;
456 fifo_state
->plane
[PLANE_CURSOR
] = 63;
458 DRM_DEBUG_KMS("Pipe %c FIFO size: %d/%d/%d/%d\n",
460 fifo_state
->plane
[PLANE_PRIMARY
],
461 fifo_state
->plane
[PLANE_SPRITE0
],
462 fifo_state
->plane
[PLANE_SPRITE1
],
463 fifo_state
->plane
[PLANE_CURSOR
]);
466 static int i9xx_get_fifo_size(struct drm_i915_private
*dev_priv
, int plane
)
468 uint32_t dsparb
= I915_READ(DSPARB
);
471 size
= dsparb
& 0x7f;
473 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
475 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
476 plane
? "B" : "A", size
);
481 static int i830_get_fifo_size(struct drm_i915_private
*dev_priv
, int plane
)
483 uint32_t dsparb
= I915_READ(DSPARB
);
486 size
= dsparb
& 0x1ff;
488 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
489 size
>>= 1; /* Convert to cachelines */
491 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
492 plane
? "B" : "A", size
);
497 static int i845_get_fifo_size(struct drm_i915_private
*dev_priv
, int plane
)
499 uint32_t dsparb
= I915_READ(DSPARB
);
502 size
= dsparb
& 0x7f;
503 size
>>= 2; /* Convert to cachelines */
505 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
512 /* Pineview has different values for various configs */
513 static const struct intel_watermark_params pineview_display_wm
= {
514 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
515 .max_wm
= PINEVIEW_MAX_WM
,
516 .default_wm
= PINEVIEW_DFT_WM
,
517 .guard_size
= PINEVIEW_GUARD_WM
,
518 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
520 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
521 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
522 .max_wm
= PINEVIEW_MAX_WM
,
523 .default_wm
= PINEVIEW_DFT_HPLLOFF_WM
,
524 .guard_size
= PINEVIEW_GUARD_WM
,
525 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
527 static const struct intel_watermark_params pineview_cursor_wm
= {
528 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
529 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
530 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
531 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
532 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
534 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
535 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
536 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
537 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
538 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
539 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
541 static const struct intel_watermark_params g4x_wm_info
= {
542 .fifo_size
= G4X_FIFO_SIZE
,
543 .max_wm
= G4X_MAX_WM
,
544 .default_wm
= G4X_MAX_WM
,
546 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
548 static const struct intel_watermark_params g4x_cursor_wm_info
= {
549 .fifo_size
= I965_CURSOR_FIFO
,
550 .max_wm
= I965_CURSOR_MAX_WM
,
551 .default_wm
= I965_CURSOR_DFT_WM
,
553 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
555 static const struct intel_watermark_params i965_cursor_wm_info
= {
556 .fifo_size
= I965_CURSOR_FIFO
,
557 .max_wm
= I965_CURSOR_MAX_WM
,
558 .default_wm
= I965_CURSOR_DFT_WM
,
560 .cacheline_size
= I915_FIFO_LINE_SIZE
,
562 static const struct intel_watermark_params i945_wm_info
= {
563 .fifo_size
= I945_FIFO_SIZE
,
564 .max_wm
= I915_MAX_WM
,
567 .cacheline_size
= I915_FIFO_LINE_SIZE
,
569 static const struct intel_watermark_params i915_wm_info
= {
570 .fifo_size
= I915_FIFO_SIZE
,
571 .max_wm
= I915_MAX_WM
,
574 .cacheline_size
= I915_FIFO_LINE_SIZE
,
576 static const struct intel_watermark_params i830_a_wm_info
= {
577 .fifo_size
= I855GM_FIFO_SIZE
,
578 .max_wm
= I915_MAX_WM
,
581 .cacheline_size
= I830_FIFO_LINE_SIZE
,
583 static const struct intel_watermark_params i830_bc_wm_info
= {
584 .fifo_size
= I855GM_FIFO_SIZE
,
585 .max_wm
= I915_MAX_WM
/2,
588 .cacheline_size
= I830_FIFO_LINE_SIZE
,
590 static const struct intel_watermark_params i845_wm_info
= {
591 .fifo_size
= I830_FIFO_SIZE
,
592 .max_wm
= I915_MAX_WM
,
595 .cacheline_size
= I830_FIFO_LINE_SIZE
,
599 * intel_calculate_wm - calculate watermark level
600 * @clock_in_khz: pixel clock
601 * @wm: chip FIFO params
602 * @cpp: bytes per pixel
603 * @latency_ns: memory latency for the platform
605 * Calculate the watermark level (the level at which the display plane will
606 * start fetching from memory again). Each chip has a different display
607 * FIFO size and allocation, so the caller needs to figure that out and pass
608 * in the correct intel_watermark_params structure.
610 * As the pixel clock runs, the FIFO will be drained at a rate that depends
611 * on the pixel size. When it reaches the watermark level, it'll start
612 * fetching FIFO line sized based chunks from memory until the FIFO fills
613 * past the watermark point. If the FIFO drains completely, a FIFO underrun
614 * will occur, and a display engine hang could result.
616 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
617 const struct intel_watermark_params
*wm
,
618 int fifo_size
, int cpp
,
619 unsigned long latency_ns
)
621 long entries_required
, wm_size
;
624 * Note: we need to make sure we don't overflow for various clock &
626 * clocks go from a few thousand to several hundred thousand.
627 * latency is usually a few thousand
629 entries_required
= ((clock_in_khz
/ 1000) * cpp
* latency_ns
) /
631 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
633 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
635 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
637 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
639 /* Don't promote wm_size to unsigned... */
640 if (wm_size
> (long)wm
->max_wm
)
641 wm_size
= wm
->max_wm
;
643 wm_size
= wm
->default_wm
;
646 * Bspec seems to indicate that the value shouldn't be lower than
647 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
648 * Lets go for 8 which is the burst size since certain platforms
649 * already use a hardcoded 8 (which is what the spec says should be
658 static bool intel_wm_plane_visible(const struct intel_crtc_state
*crtc_state
,
659 const struct intel_plane_state
*plane_state
)
661 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
663 /* FIXME check the 'enable' instead */
664 if (!crtc_state
->base
.active
)
668 * Treat cursor with fb as always visible since cursor updates
669 * can happen faster than the vrefresh rate, and the current
670 * watermark code doesn't handle that correctly. Cursor updates
671 * which set/clear the fb or change the cursor size are going
672 * to get throttled by intel_legacy_cursor_update() to work
673 * around this problem with the watermark code.
675 if (plane
->id
== PLANE_CURSOR
)
676 return plane_state
->base
.fb
!= NULL
;
678 return plane_state
->base
.visible
;
681 static struct intel_crtc
*single_enabled_crtc(struct drm_i915_private
*dev_priv
)
683 struct intel_crtc
*crtc
, *enabled
= NULL
;
685 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
686 if (intel_crtc_active(crtc
)) {
696 static void pineview_update_wm(struct intel_crtc
*unused_crtc
)
698 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
699 struct intel_crtc
*crtc
;
700 const struct cxsr_latency
*latency
;
704 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv
),
709 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
710 intel_set_memory_cxsr(dev_priv
, false);
714 crtc
= single_enabled_crtc(dev_priv
);
716 const struct drm_display_mode
*adjusted_mode
=
717 &crtc
->config
->base
.adjusted_mode
;
718 const struct drm_framebuffer
*fb
=
719 crtc
->base
.primary
->state
->fb
;
720 int cpp
= fb
->format
->cpp
[0];
721 int clock
= adjusted_mode
->crtc_clock
;
724 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
725 pineview_display_wm
.fifo_size
,
726 cpp
, latency
->display_sr
);
727 reg
= I915_READ(DSPFW1
);
728 reg
&= ~DSPFW_SR_MASK
;
729 reg
|= FW_WM(wm
, SR
);
730 I915_WRITE(DSPFW1
, reg
);
731 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
734 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
735 pineview_display_wm
.fifo_size
,
736 cpp
, latency
->cursor_sr
);
737 reg
= I915_READ(DSPFW3
);
738 reg
&= ~DSPFW_CURSOR_SR_MASK
;
739 reg
|= FW_WM(wm
, CURSOR_SR
);
740 I915_WRITE(DSPFW3
, reg
);
742 /* Display HPLL off SR */
743 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
744 pineview_display_hplloff_wm
.fifo_size
,
745 cpp
, latency
->display_hpll_disable
);
746 reg
= I915_READ(DSPFW3
);
747 reg
&= ~DSPFW_HPLL_SR_MASK
;
748 reg
|= FW_WM(wm
, HPLL_SR
);
749 I915_WRITE(DSPFW3
, reg
);
751 /* cursor HPLL off SR */
752 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
753 pineview_display_hplloff_wm
.fifo_size
,
754 cpp
, latency
->cursor_hpll_disable
);
755 reg
= I915_READ(DSPFW3
);
756 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
757 reg
|= FW_WM(wm
, HPLL_CURSOR
);
758 I915_WRITE(DSPFW3
, reg
);
759 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
761 intel_set_memory_cxsr(dev_priv
, true);
763 intel_set_memory_cxsr(dev_priv
, false);
767 static bool g4x_compute_wm0(struct drm_i915_private
*dev_priv
,
769 const struct intel_watermark_params
*display
,
770 int display_latency_ns
,
771 const struct intel_watermark_params
*cursor
,
772 int cursor_latency_ns
,
776 struct intel_crtc
*crtc
;
777 const struct drm_display_mode
*adjusted_mode
;
778 const struct drm_framebuffer
*fb
;
779 int htotal
, hdisplay
, clock
, cpp
;
780 int line_time_us
, line_count
;
781 int entries
, tlb_miss
;
783 crtc
= intel_get_crtc_for_plane(dev_priv
, plane
);
784 if (!intel_crtc_active(crtc
)) {
785 *cursor_wm
= cursor
->guard_size
;
786 *plane_wm
= display
->guard_size
;
790 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
791 fb
= crtc
->base
.primary
->state
->fb
;
792 clock
= adjusted_mode
->crtc_clock
;
793 htotal
= adjusted_mode
->crtc_htotal
;
794 hdisplay
= crtc
->config
->pipe_src_w
;
795 cpp
= fb
->format
->cpp
[0];
797 /* Use the small buffer method to calculate plane watermark */
798 entries
= ((clock
* cpp
/ 1000) * display_latency_ns
) / 1000;
799 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
802 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
803 *plane_wm
= entries
+ display
->guard_size
;
804 if (*plane_wm
> (int)display
->max_wm
)
805 *plane_wm
= display
->max_wm
;
807 /* Use the large buffer method to calculate cursor watermark */
808 line_time_us
= max(htotal
* 1000 / clock
, 1);
809 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
810 entries
= line_count
* crtc
->base
.cursor
->state
->crtc_w
* cpp
;
811 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
814 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
815 *cursor_wm
= entries
+ cursor
->guard_size
;
816 if (*cursor_wm
> (int)cursor
->max_wm
)
817 *cursor_wm
= (int)cursor
->max_wm
;
823 * Check the wm result.
825 * If any calculated watermark values is larger than the maximum value that
826 * can be programmed into the associated watermark register, that watermark
829 static bool g4x_check_srwm(struct drm_i915_private
*dev_priv
,
830 int display_wm
, int cursor_wm
,
831 const struct intel_watermark_params
*display
,
832 const struct intel_watermark_params
*cursor
)
834 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
835 display_wm
, cursor_wm
);
837 if (display_wm
> display
->max_wm
) {
838 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
839 display_wm
, display
->max_wm
);
843 if (cursor_wm
> cursor
->max_wm
) {
844 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
845 cursor_wm
, cursor
->max_wm
);
849 if (!(display_wm
|| cursor_wm
)) {
850 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
857 static bool g4x_compute_srwm(struct drm_i915_private
*dev_priv
,
860 const struct intel_watermark_params
*display
,
861 const struct intel_watermark_params
*cursor
,
862 int *display_wm
, int *cursor_wm
)
864 struct intel_crtc
*crtc
;
865 const struct drm_display_mode
*adjusted_mode
;
866 const struct drm_framebuffer
*fb
;
867 int hdisplay
, htotal
, cpp
, clock
;
868 unsigned long line_time_us
;
869 int line_count
, line_size
;
874 *display_wm
= *cursor_wm
= 0;
878 crtc
= intel_get_crtc_for_plane(dev_priv
, plane
);
879 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
880 fb
= crtc
->base
.primary
->state
->fb
;
881 clock
= adjusted_mode
->crtc_clock
;
882 htotal
= adjusted_mode
->crtc_htotal
;
883 hdisplay
= crtc
->config
->pipe_src_w
;
884 cpp
= fb
->format
->cpp
[0];
886 line_time_us
= max(htotal
* 1000 / clock
, 1);
887 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
888 line_size
= hdisplay
* cpp
;
890 /* Use the minimum of the small and large buffer method for primary */
891 small
= ((clock
* cpp
/ 1000) * latency_ns
) / 1000;
892 large
= line_count
* line_size
;
894 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
895 *display_wm
= entries
+ display
->guard_size
;
897 /* calculate the self-refresh watermark for display cursor */
898 entries
= line_count
* cpp
* crtc
->base
.cursor
->state
->crtc_w
;
899 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
900 *cursor_wm
= entries
+ cursor
->guard_size
;
902 return g4x_check_srwm(dev_priv
,
903 *display_wm
, *cursor_wm
,
907 #define FW_WM_VLV(value, plane) \
908 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
910 static void vlv_write_wm_values(struct drm_i915_private
*dev_priv
,
911 const struct vlv_wm_values
*wm
)
915 for_each_pipe(dev_priv
, pipe
) {
916 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv
, pipe
), wm
);
918 I915_WRITE(VLV_DDL(pipe
),
919 (wm
->ddl
[pipe
].plane
[PLANE_CURSOR
] << DDL_CURSOR_SHIFT
) |
920 (wm
->ddl
[pipe
].plane
[PLANE_SPRITE1
] << DDL_SPRITE_SHIFT(1)) |
921 (wm
->ddl
[pipe
].plane
[PLANE_SPRITE0
] << DDL_SPRITE_SHIFT(0)) |
922 (wm
->ddl
[pipe
].plane
[PLANE_PRIMARY
] << DDL_PLANE_SHIFT
));
926 * Zero the (unused) WM1 watermarks, and also clear all the
927 * high order bits so that there are no out of bounds values
928 * present in the registers during the reprogramming.
930 I915_WRITE(DSPHOWM
, 0);
931 I915_WRITE(DSPHOWM1
, 0);
932 I915_WRITE(DSPFW4
, 0);
933 I915_WRITE(DSPFW5
, 0);
934 I915_WRITE(DSPFW6
, 0);
937 FW_WM(wm
->sr
.plane
, SR
) |
938 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_CURSOR
], CURSORB
) |
939 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
], PLANEB
) |
940 FW_WM_VLV(wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
], PLANEA
));
942 FW_WM_VLV(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
], SPRITEB
) |
943 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_CURSOR
], CURSORA
) |
944 FW_WM_VLV(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
], SPRITEA
));
946 FW_WM(wm
->sr
.cursor
, CURSOR_SR
));
948 if (IS_CHERRYVIEW(dev_priv
)) {
949 I915_WRITE(DSPFW7_CHV
,
950 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
], SPRITED
) |
951 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
], SPRITEC
));
952 I915_WRITE(DSPFW8_CHV
,
953 FW_WM_VLV(wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE1
], SPRITEF
) |
954 FW_WM_VLV(wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE0
], SPRITEE
));
955 I915_WRITE(DSPFW9_CHV
,
956 FW_WM_VLV(wm
->pipe
[PIPE_C
].plane
[PLANE_PRIMARY
], PLANEC
) |
957 FW_WM(wm
->pipe
[PIPE_C
].plane
[PLANE_CURSOR
], CURSORC
));
959 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
960 FW_WM(wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE1
] >> 8, SPRITEF_HI
) |
961 FW_WM(wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE0
] >> 8, SPRITEE_HI
) |
962 FW_WM(wm
->pipe
[PIPE_C
].plane
[PLANE_PRIMARY
] >> 8, PLANEC_HI
) |
963 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] >> 8, SPRITED_HI
) |
964 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] >> 8, SPRITEC_HI
) |
965 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] >> 8, PLANEB_HI
) |
966 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] >> 8, SPRITEB_HI
) |
967 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] >> 8, SPRITEA_HI
) |
968 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] >> 8, PLANEA_HI
));
971 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
], SPRITED
) |
972 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
], SPRITEC
));
974 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
975 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] >> 8, SPRITED_HI
) |
976 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] >> 8, SPRITEC_HI
) |
977 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] >> 8, PLANEB_HI
) |
978 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] >> 8, SPRITEB_HI
) |
979 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] >> 8, SPRITEA_HI
) |
980 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] >> 8, PLANEA_HI
));
983 POSTING_READ(DSPFW1
);
988 /* latency must be in 0.1us units. */
989 static unsigned int vlv_wm_method2(unsigned int pixel_rate
,
990 unsigned int pipe_htotal
,
991 unsigned int horiz_pixels
,
993 unsigned int latency
)
997 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
998 ret
= (ret
+ 1) * horiz_pixels
* cpp
;
999 ret
= DIV_ROUND_UP(ret
, 64);
1004 static void vlv_setup_wm_latency(struct drm_i915_private
*dev_priv
)
1006 /* all latencies in usec */
1007 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM2
] = 3;
1009 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM2
;
1011 if (IS_CHERRYVIEW(dev_priv
)) {
1012 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM5
] = 12;
1013 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_DDR_DVFS
] = 33;
1015 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_DDR_DVFS
;
1019 static uint16_t vlv_compute_wm_level(const struct intel_crtc_state
*crtc_state
,
1020 const struct intel_plane_state
*plane_state
,
1023 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
1024 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
1025 const struct drm_display_mode
*adjusted_mode
=
1026 &crtc_state
->base
.adjusted_mode
;
1027 int clock
, htotal
, cpp
, width
, wm
;
1029 if (dev_priv
->wm
.pri_latency
[level
] == 0)
1032 if (!plane_state
->base
.visible
)
1035 cpp
= plane_state
->base
.fb
->format
->cpp
[0];
1036 clock
= adjusted_mode
->crtc_clock
;
1037 htotal
= adjusted_mode
->crtc_htotal
;
1038 width
= crtc_state
->pipe_src_w
;
1039 if (WARN_ON(htotal
== 0))
1042 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
1044 * FIXME the formula gives values that are
1045 * too big for the cursor FIFO, and hence we
1046 * would never be able to use cursors. For
1047 * now just hardcode the watermark.
1051 wm
= vlv_wm_method2(clock
, htotal
, width
, cpp
,
1052 dev_priv
->wm
.pri_latency
[level
] * 10);
1055 return min_t(int, wm
, USHRT_MAX
);
1058 static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes
)
1060 return (active_planes
& (BIT(PLANE_SPRITE0
) |
1061 BIT(PLANE_SPRITE1
))) == BIT(PLANE_SPRITE1
);
1064 static int vlv_compute_fifo(struct intel_crtc_state
*crtc_state
)
1066 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1067 const struct vlv_pipe_wm
*raw
=
1068 &crtc_state
->wm
.vlv
.raw
[VLV_WM_LEVEL_PM2
];
1069 struct vlv_fifo_state
*fifo_state
= &crtc_state
->wm
.vlv
.fifo_state
;
1070 unsigned int active_planes
= crtc_state
->active_planes
& ~BIT(PLANE_CURSOR
);
1071 int num_active_planes
= hweight32(active_planes
);
1072 const int fifo_size
= 511;
1073 int fifo_extra
, fifo_left
= fifo_size
;
1074 int sprite0_fifo_extra
= 0;
1075 unsigned int total_rate
;
1076 enum plane_id plane_id
;
1079 * When enabling sprite0 after sprite1 has already been enabled
1080 * we tend to get an underrun unless sprite0 already has some
1081 * FIFO space allcoated. Hence we always allocate at least one
1082 * cacheline for sprite0 whenever sprite1 is enabled.
1084 * All other plane enable sequences appear immune to this problem.
1086 if (vlv_need_sprite0_fifo_workaround(active_planes
))
1087 sprite0_fifo_extra
= 1;
1089 total_rate
= raw
->plane
[PLANE_PRIMARY
] +
1090 raw
->plane
[PLANE_SPRITE0
] +
1091 raw
->plane
[PLANE_SPRITE1
] +
1094 if (total_rate
> fifo_size
)
1097 if (total_rate
== 0)
1100 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1103 if ((active_planes
& BIT(plane_id
)) == 0) {
1104 fifo_state
->plane
[plane_id
] = 0;
1108 rate
= raw
->plane
[plane_id
];
1109 fifo_state
->plane
[plane_id
] = fifo_size
* rate
/ total_rate
;
1110 fifo_left
-= fifo_state
->plane
[plane_id
];
1113 fifo_state
->plane
[PLANE_SPRITE0
] += sprite0_fifo_extra
;
1114 fifo_left
-= sprite0_fifo_extra
;
1116 fifo_state
->plane
[PLANE_CURSOR
] = 63;
1118 fifo_extra
= DIV_ROUND_UP(fifo_left
, num_active_planes
?: 1);
1120 /* spread the remainder evenly */
1121 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1127 if ((active_planes
& BIT(plane_id
)) == 0)
1130 plane_extra
= min(fifo_extra
, fifo_left
);
1131 fifo_state
->plane
[plane_id
] += plane_extra
;
1132 fifo_left
-= plane_extra
;
1135 WARN_ON(active_planes
!= 0 && fifo_left
!= 0);
1137 /* give it all to the first plane if none are active */
1138 if (active_planes
== 0) {
1139 WARN_ON(fifo_left
!= fifo_size
);
1140 fifo_state
->plane
[PLANE_PRIMARY
] = fifo_left
;
1146 static int vlv_num_wm_levels(struct drm_i915_private
*dev_priv
)
1148 return dev_priv
->wm
.max_level
+ 1;
1151 /* mark all levels starting from 'level' as invalid */
1152 static void vlv_invalidate_wms(struct intel_crtc
*crtc
,
1153 struct vlv_wm_state
*wm_state
, int level
)
1155 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1157 for (; level
< vlv_num_wm_levels(dev_priv
); level
++) {
1158 enum plane_id plane_id
;
1160 for_each_plane_id_on_crtc(crtc
, plane_id
)
1161 wm_state
->wm
[level
].plane
[plane_id
] = USHRT_MAX
;
1163 wm_state
->sr
[level
].cursor
= USHRT_MAX
;
1164 wm_state
->sr
[level
].plane
= USHRT_MAX
;
1168 static u16
vlv_invert_wm_value(u16 wm
, u16 fifo_size
)
1173 return fifo_size
- wm
;
1177 * Starting from 'level' set all higher
1178 * levels to 'value' in the "raw" watermarks.
1180 static bool vlv_raw_plane_wm_set(struct intel_crtc_state
*crtc_state
,
1181 int level
, enum plane_id plane_id
, u16 value
)
1183 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1184 int num_levels
= vlv_num_wm_levels(dev_priv
);
1187 for (; level
< num_levels
; level
++) {
1188 struct vlv_pipe_wm
*raw
= &crtc_state
->wm
.vlv
.raw
[level
];
1190 dirty
|= raw
->plane
[plane_id
] != value
;
1191 raw
->plane
[plane_id
] = value
;
1197 static bool vlv_plane_wm_compute(struct intel_crtc_state
*crtc_state
,
1198 const struct intel_plane_state
*plane_state
)
1200 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
1201 enum plane_id plane_id
= plane
->id
;
1202 int num_levels
= vlv_num_wm_levels(to_i915(plane
->base
.dev
));
1206 if (!plane_state
->base
.visible
) {
1207 dirty
|= vlv_raw_plane_wm_set(crtc_state
, 0, plane_id
, 0);
1211 for (level
= 0; level
< num_levels
; level
++) {
1212 struct vlv_pipe_wm
*raw
= &crtc_state
->wm
.vlv
.raw
[level
];
1213 int wm
= vlv_compute_wm_level(crtc_state
, plane_state
, level
);
1214 int max_wm
= plane_id
== PLANE_CURSOR
? 63 : 511;
1219 dirty
|= raw
->plane
[plane_id
] != wm
;
1220 raw
->plane
[plane_id
] = wm
;
1223 /* mark all higher levels as invalid */
1224 dirty
|= vlv_raw_plane_wm_set(crtc_state
, level
, plane_id
, USHRT_MAX
);
1228 DRM_DEBUG_KMS("%s wms: [0]=%d,[1]=%d,[2]=%d\n",
1230 crtc_state
->wm
.vlv
.raw
[VLV_WM_LEVEL_PM2
].plane
[plane_id
],
1231 crtc_state
->wm
.vlv
.raw
[VLV_WM_LEVEL_PM5
].plane
[plane_id
],
1232 crtc_state
->wm
.vlv
.raw
[VLV_WM_LEVEL_DDR_DVFS
].plane
[plane_id
]);
1237 static bool vlv_plane_wm_is_valid(const struct intel_crtc_state
*crtc_state
,
1238 enum plane_id plane_id
, int level
)
1240 const struct vlv_pipe_wm
*raw
=
1241 &crtc_state
->wm
.vlv
.raw
[level
];
1242 const struct vlv_fifo_state
*fifo_state
=
1243 &crtc_state
->wm
.vlv
.fifo_state
;
1245 return raw
->plane
[plane_id
] <= fifo_state
->plane
[plane_id
];
1248 static bool vlv_crtc_wm_is_valid(const struct intel_crtc_state
*crtc_state
, int level
)
1250 return vlv_plane_wm_is_valid(crtc_state
, PLANE_PRIMARY
, level
) &&
1251 vlv_plane_wm_is_valid(crtc_state
, PLANE_SPRITE0
, level
) &&
1252 vlv_plane_wm_is_valid(crtc_state
, PLANE_SPRITE1
, level
) &&
1253 vlv_plane_wm_is_valid(crtc_state
, PLANE_CURSOR
, level
);
1256 static int vlv_compute_pipe_wm(struct intel_crtc_state
*crtc_state
)
1258 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1259 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1260 struct intel_atomic_state
*state
=
1261 to_intel_atomic_state(crtc_state
->base
.state
);
1262 struct vlv_wm_state
*wm_state
= &crtc_state
->wm
.vlv
.optimal
;
1263 const struct vlv_fifo_state
*fifo_state
=
1264 &crtc_state
->wm
.vlv
.fifo_state
;
1265 int num_active_planes
= hweight32(crtc_state
->active_planes
&
1266 ~BIT(PLANE_CURSOR
));
1267 bool needs_modeset
= drm_atomic_crtc_needs_modeset(&crtc_state
->base
);
1268 struct intel_plane_state
*plane_state
;
1269 struct intel_plane
*plane
;
1270 enum plane_id plane_id
;
1272 unsigned int dirty
= 0;
1274 for_each_intel_plane_in_state(state
, plane
, plane_state
, i
) {
1275 const struct intel_plane_state
*old_plane_state
=
1276 to_intel_plane_state(plane
->base
.state
);
1278 if (plane_state
->base
.crtc
!= &crtc
->base
&&
1279 old_plane_state
->base
.crtc
!= &crtc
->base
)
1282 if (vlv_plane_wm_compute(crtc_state
, plane_state
))
1283 dirty
|= BIT(plane
->id
);
1287 * DSPARB registers may have been reset due to the
1288 * power well being turned off. Make sure we restore
1289 * them to a consistent state even if no primary/sprite
1290 * planes are initially active.
1293 crtc_state
->fifo_changed
= true;
1298 /* cursor changes don't warrant a FIFO recompute */
1299 if (dirty
& ~BIT(PLANE_CURSOR
)) {
1300 const struct intel_crtc_state
*old_crtc_state
=
1301 to_intel_crtc_state(crtc
->base
.state
);
1302 const struct vlv_fifo_state
*old_fifo_state
=
1303 &old_crtc_state
->wm
.vlv
.fifo_state
;
1305 ret
= vlv_compute_fifo(crtc_state
);
1309 if (needs_modeset
||
1310 memcmp(old_fifo_state
, fifo_state
,
1311 sizeof(*fifo_state
)) != 0)
1312 crtc_state
->fifo_changed
= true;
1315 /* initially allow all levels */
1316 wm_state
->num_levels
= vlv_num_wm_levels(dev_priv
);
1318 * Note that enabling cxsr with no primary/sprite planes
1319 * enabled can wedge the pipe. Hence we only allow cxsr
1320 * with exactly one enabled primary/sprite plane.
1322 wm_state
->cxsr
= crtc
->pipe
!= PIPE_C
&& num_active_planes
== 1;
1324 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1325 const struct vlv_pipe_wm
*raw
= &crtc_state
->wm
.vlv
.raw
[level
];
1326 const int sr_fifo_size
= INTEL_INFO(dev_priv
)->num_pipes
* 512 - 1;
1328 if (!vlv_crtc_wm_is_valid(crtc_state
, level
))
1331 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1332 wm_state
->wm
[level
].plane
[plane_id
] =
1333 vlv_invert_wm_value(raw
->plane
[plane_id
],
1334 fifo_state
->plane
[plane_id
]);
1337 wm_state
->sr
[level
].plane
=
1338 vlv_invert_wm_value(max3(raw
->plane
[PLANE_PRIMARY
],
1339 raw
->plane
[PLANE_SPRITE0
],
1340 raw
->plane
[PLANE_SPRITE1
]),
1343 wm_state
->sr
[level
].cursor
=
1344 vlv_invert_wm_value(raw
->plane
[PLANE_CURSOR
],
1351 /* limit to only levels we can actually handle */
1352 wm_state
->num_levels
= level
;
1354 /* invalidate the higher levels */
1355 vlv_invalidate_wms(crtc
, wm_state
, level
);
1360 #define VLV_FIFO(plane, value) \
1361 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1363 static void vlv_atomic_update_fifo(struct intel_atomic_state
*state
,
1364 struct intel_crtc_state
*crtc_state
)
1366 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1367 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1368 const struct vlv_fifo_state
*fifo_state
=
1369 &crtc_state
->wm
.vlv
.fifo_state
;
1370 int sprite0_start
, sprite1_start
, fifo_size
;
1372 if (!crtc_state
->fifo_changed
)
1375 sprite0_start
= fifo_state
->plane
[PLANE_PRIMARY
];
1376 sprite1_start
= fifo_state
->plane
[PLANE_SPRITE0
] + sprite0_start
;
1377 fifo_size
= fifo_state
->plane
[PLANE_SPRITE1
] + sprite1_start
;
1379 WARN_ON(fifo_state
->plane
[PLANE_CURSOR
] != 63);
1380 WARN_ON(fifo_size
!= 511);
1382 trace_vlv_fifo_size(crtc
, sprite0_start
, sprite1_start
, fifo_size
);
1385 * uncore.lock serves a double purpose here. It allows us to
1386 * use the less expensive I915_{READ,WRITE}_FW() functions, and
1387 * it protects the DSPARB registers from getting clobbered by
1388 * parallel updates from multiple pipes.
1390 * intel_pipe_update_start() has already disabled interrupts
1391 * for us, so a plain spin_lock() is sufficient here.
1393 spin_lock(&dev_priv
->uncore
.lock
);
1395 switch (crtc
->pipe
) {
1396 uint32_t dsparb
, dsparb2
, dsparb3
;
1398 dsparb
= I915_READ_FW(DSPARB
);
1399 dsparb2
= I915_READ_FW(DSPARB2
);
1401 dsparb
&= ~(VLV_FIFO(SPRITEA
, 0xff) |
1402 VLV_FIFO(SPRITEB
, 0xff));
1403 dsparb
|= (VLV_FIFO(SPRITEA
, sprite0_start
) |
1404 VLV_FIFO(SPRITEB
, sprite1_start
));
1406 dsparb2
&= ~(VLV_FIFO(SPRITEA_HI
, 0x1) |
1407 VLV_FIFO(SPRITEB_HI
, 0x1));
1408 dsparb2
|= (VLV_FIFO(SPRITEA_HI
, sprite0_start
>> 8) |
1409 VLV_FIFO(SPRITEB_HI
, sprite1_start
>> 8));
1411 I915_WRITE_FW(DSPARB
, dsparb
);
1412 I915_WRITE_FW(DSPARB2
, dsparb2
);
1415 dsparb
= I915_READ_FW(DSPARB
);
1416 dsparb2
= I915_READ_FW(DSPARB2
);
1418 dsparb
&= ~(VLV_FIFO(SPRITEC
, 0xff) |
1419 VLV_FIFO(SPRITED
, 0xff));
1420 dsparb
|= (VLV_FIFO(SPRITEC
, sprite0_start
) |
1421 VLV_FIFO(SPRITED
, sprite1_start
));
1423 dsparb2
&= ~(VLV_FIFO(SPRITEC_HI
, 0xff) |
1424 VLV_FIFO(SPRITED_HI
, 0xff));
1425 dsparb2
|= (VLV_FIFO(SPRITEC_HI
, sprite0_start
>> 8) |
1426 VLV_FIFO(SPRITED_HI
, sprite1_start
>> 8));
1428 I915_WRITE_FW(DSPARB
, dsparb
);
1429 I915_WRITE_FW(DSPARB2
, dsparb2
);
1432 dsparb3
= I915_READ_FW(DSPARB3
);
1433 dsparb2
= I915_READ_FW(DSPARB2
);
1435 dsparb3
&= ~(VLV_FIFO(SPRITEE
, 0xff) |
1436 VLV_FIFO(SPRITEF
, 0xff));
1437 dsparb3
|= (VLV_FIFO(SPRITEE
, sprite0_start
) |
1438 VLV_FIFO(SPRITEF
, sprite1_start
));
1440 dsparb2
&= ~(VLV_FIFO(SPRITEE_HI
, 0xff) |
1441 VLV_FIFO(SPRITEF_HI
, 0xff));
1442 dsparb2
|= (VLV_FIFO(SPRITEE_HI
, sprite0_start
>> 8) |
1443 VLV_FIFO(SPRITEF_HI
, sprite1_start
>> 8));
1445 I915_WRITE_FW(DSPARB3
, dsparb3
);
1446 I915_WRITE_FW(DSPARB2
, dsparb2
);
1452 POSTING_READ_FW(DSPARB
);
1454 spin_unlock(&dev_priv
->uncore
.lock
);
1459 static int vlv_compute_intermediate_wm(struct drm_device
*dev
,
1460 struct intel_crtc
*crtc
,
1461 struct intel_crtc_state
*crtc_state
)
1463 struct vlv_wm_state
*intermediate
= &crtc_state
->wm
.vlv
.intermediate
;
1464 const struct vlv_wm_state
*optimal
= &crtc_state
->wm
.vlv
.optimal
;
1465 const struct vlv_wm_state
*active
= &crtc
->wm
.active
.vlv
;
1468 intermediate
->num_levels
= min(optimal
->num_levels
, active
->num_levels
);
1469 intermediate
->cxsr
= optimal
->cxsr
&& active
->cxsr
&&
1470 !crtc_state
->disable_cxsr
;
1472 for (level
= 0; level
< intermediate
->num_levels
; level
++) {
1473 enum plane_id plane_id
;
1475 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1476 intermediate
->wm
[level
].plane
[plane_id
] =
1477 min(optimal
->wm
[level
].plane
[plane_id
],
1478 active
->wm
[level
].plane
[plane_id
]);
1481 intermediate
->sr
[level
].plane
= min(optimal
->sr
[level
].plane
,
1482 active
->sr
[level
].plane
);
1483 intermediate
->sr
[level
].cursor
= min(optimal
->sr
[level
].cursor
,
1484 active
->sr
[level
].cursor
);
1487 vlv_invalidate_wms(crtc
, intermediate
, level
);
1490 * If our intermediate WM are identical to the final WM, then we can
1491 * omit the post-vblank programming; only update if it's different.
1493 if (memcmp(intermediate
, optimal
, sizeof(*intermediate
)) != 0)
1494 crtc_state
->wm
.need_postvbl_update
= true;
1499 static void vlv_merge_wm(struct drm_i915_private
*dev_priv
,
1500 struct vlv_wm_values
*wm
)
1502 struct intel_crtc
*crtc
;
1503 int num_active_crtcs
= 0;
1505 wm
->level
= dev_priv
->wm
.max_level
;
1508 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
1509 const struct vlv_wm_state
*wm_state
= &crtc
->wm
.active
.vlv
;
1514 if (!wm_state
->cxsr
)
1518 wm
->level
= min_t(int, wm
->level
, wm_state
->num_levels
- 1);
1521 if (num_active_crtcs
!= 1)
1524 if (num_active_crtcs
> 1)
1525 wm
->level
= VLV_WM_LEVEL_PM2
;
1527 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
1528 const struct vlv_wm_state
*wm_state
= &crtc
->wm
.active
.vlv
;
1529 enum pipe pipe
= crtc
->pipe
;
1531 wm
->pipe
[pipe
] = wm_state
->wm
[wm
->level
];
1532 if (crtc
->active
&& wm
->cxsr
)
1533 wm
->sr
= wm_state
->sr
[wm
->level
];
1535 wm
->ddl
[pipe
].plane
[PLANE_PRIMARY
] = DDL_PRECISION_HIGH
| 2;
1536 wm
->ddl
[pipe
].plane
[PLANE_SPRITE0
] = DDL_PRECISION_HIGH
| 2;
1537 wm
->ddl
[pipe
].plane
[PLANE_SPRITE1
] = DDL_PRECISION_HIGH
| 2;
1538 wm
->ddl
[pipe
].plane
[PLANE_CURSOR
] = DDL_PRECISION_HIGH
| 2;
1542 static bool is_disabling(int old
, int new, int threshold
)
1544 return old
>= threshold
&& new < threshold
;
1547 static bool is_enabling(int old
, int new, int threshold
)
1549 return old
< threshold
&& new >= threshold
;
1552 static void vlv_program_watermarks(struct drm_i915_private
*dev_priv
)
1554 struct vlv_wm_values
*old_wm
= &dev_priv
->wm
.vlv
;
1555 struct vlv_wm_values new_wm
= {};
1557 vlv_merge_wm(dev_priv
, &new_wm
);
1559 if (memcmp(old_wm
, &new_wm
, sizeof(new_wm
)) == 0)
1562 if (is_disabling(old_wm
->level
, new_wm
.level
, VLV_WM_LEVEL_DDR_DVFS
))
1563 chv_set_memory_dvfs(dev_priv
, false);
1565 if (is_disabling(old_wm
->level
, new_wm
.level
, VLV_WM_LEVEL_PM5
))
1566 chv_set_memory_pm5(dev_priv
, false);
1568 if (is_disabling(old_wm
->cxsr
, new_wm
.cxsr
, true))
1569 _intel_set_memory_cxsr(dev_priv
, false);
1571 vlv_write_wm_values(dev_priv
, &new_wm
);
1573 if (is_enabling(old_wm
->cxsr
, new_wm
.cxsr
, true))
1574 _intel_set_memory_cxsr(dev_priv
, true);
1576 if (is_enabling(old_wm
->level
, new_wm
.level
, VLV_WM_LEVEL_PM5
))
1577 chv_set_memory_pm5(dev_priv
, true);
1579 if (is_enabling(old_wm
->level
, new_wm
.level
, VLV_WM_LEVEL_DDR_DVFS
))
1580 chv_set_memory_dvfs(dev_priv
, true);
1585 static void vlv_initial_watermarks(struct intel_atomic_state
*state
,
1586 struct intel_crtc_state
*crtc_state
)
1588 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1589 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1591 mutex_lock(&dev_priv
->wm
.wm_mutex
);
1592 crtc
->wm
.active
.vlv
= crtc_state
->wm
.vlv
.intermediate
;
1593 vlv_program_watermarks(dev_priv
);
1594 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
1597 static void vlv_optimize_watermarks(struct intel_atomic_state
*state
,
1598 struct intel_crtc_state
*crtc_state
)
1600 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1601 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1603 if (!crtc_state
->wm
.need_postvbl_update
)
1606 mutex_lock(&dev_priv
->wm
.wm_mutex
);
1607 intel_crtc
->wm
.active
.vlv
= crtc_state
->wm
.vlv
.optimal
;
1608 vlv_program_watermarks(dev_priv
);
1609 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
1612 #define single_plane_enabled(mask) is_power_of_2(mask)
1614 static void g4x_update_wm(struct intel_crtc
*crtc
)
1616 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1617 static const int sr_latency_ns
= 12000;
1618 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1619 int plane_sr
, cursor_sr
;
1620 unsigned int enabled
= 0;
1623 if (g4x_compute_wm0(dev_priv
, PIPE_A
,
1624 &g4x_wm_info
, pessimal_latency_ns
,
1625 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1626 &planea_wm
, &cursora_wm
))
1627 enabled
|= 1 << PIPE_A
;
1629 if (g4x_compute_wm0(dev_priv
, PIPE_B
,
1630 &g4x_wm_info
, pessimal_latency_ns
,
1631 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1632 &planeb_wm
, &cursorb_wm
))
1633 enabled
|= 1 << PIPE_B
;
1635 if (single_plane_enabled(enabled
) &&
1636 g4x_compute_srwm(dev_priv
, ffs(enabled
) - 1,
1639 &g4x_cursor_wm_info
,
1640 &plane_sr
, &cursor_sr
)) {
1641 cxsr_enabled
= true;
1643 cxsr_enabled
= false;
1644 intel_set_memory_cxsr(dev_priv
, false);
1645 plane_sr
= cursor_sr
= 0;
1648 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1649 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1650 planea_wm
, cursora_wm
,
1651 planeb_wm
, cursorb_wm
,
1652 plane_sr
, cursor_sr
);
1655 FW_WM(plane_sr
, SR
) |
1656 FW_WM(cursorb_wm
, CURSORB
) |
1657 FW_WM(planeb_wm
, PLANEB
) |
1658 FW_WM(planea_wm
, PLANEA
));
1660 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1661 FW_WM(cursora_wm
, CURSORA
));
1662 /* HPLL off in SR has some issues on G4x... disable it */
1664 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1665 FW_WM(cursor_sr
, CURSOR_SR
));
1668 intel_set_memory_cxsr(dev_priv
, true);
1671 static void i965_update_wm(struct intel_crtc
*unused_crtc
)
1673 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
1674 struct intel_crtc
*crtc
;
1679 /* Calc sr entries for one plane configs */
1680 crtc
= single_enabled_crtc(dev_priv
);
1682 /* self-refresh has much higher latency */
1683 static const int sr_latency_ns
= 12000;
1684 const struct drm_display_mode
*adjusted_mode
=
1685 &crtc
->config
->base
.adjusted_mode
;
1686 const struct drm_framebuffer
*fb
=
1687 crtc
->base
.primary
->state
->fb
;
1688 int clock
= adjusted_mode
->crtc_clock
;
1689 int htotal
= adjusted_mode
->crtc_htotal
;
1690 int hdisplay
= crtc
->config
->pipe_src_w
;
1691 int cpp
= fb
->format
->cpp
[0];
1692 unsigned long line_time_us
;
1695 line_time_us
= max(htotal
* 1000 / clock
, 1);
1697 /* Use ns/us then divide to preserve precision */
1698 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1700 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1701 srwm
= I965_FIFO_SIZE
- entries
;
1705 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1708 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1709 cpp
* crtc
->base
.cursor
->state
->crtc_w
;
1710 entries
= DIV_ROUND_UP(entries
,
1711 i965_cursor_wm_info
.cacheline_size
);
1712 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1713 (entries
+ i965_cursor_wm_info
.guard_size
);
1715 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1716 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1718 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1719 "cursor %d\n", srwm
, cursor_sr
);
1721 cxsr_enabled
= true;
1723 cxsr_enabled
= false;
1724 /* Turn off self refresh if both pipes are enabled */
1725 intel_set_memory_cxsr(dev_priv
, false);
1728 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1731 /* 965 has limitations... */
1732 I915_WRITE(DSPFW1
, FW_WM(srwm
, SR
) |
1736 I915_WRITE(DSPFW2
, FW_WM(8, CURSORA
) |
1737 FW_WM(8, PLANEC_OLD
));
1738 /* update cursor SR watermark */
1739 I915_WRITE(DSPFW3
, FW_WM(cursor_sr
, CURSOR_SR
));
1742 intel_set_memory_cxsr(dev_priv
, true);
1747 static void i9xx_update_wm(struct intel_crtc
*unused_crtc
)
1749 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
1750 const struct intel_watermark_params
*wm_info
;
1755 int planea_wm
, planeb_wm
;
1756 struct intel_crtc
*crtc
, *enabled
= NULL
;
1758 if (IS_I945GM(dev_priv
))
1759 wm_info
= &i945_wm_info
;
1760 else if (!IS_GEN2(dev_priv
))
1761 wm_info
= &i915_wm_info
;
1763 wm_info
= &i830_a_wm_info
;
1765 fifo_size
= dev_priv
->display
.get_fifo_size(dev_priv
, 0);
1766 crtc
= intel_get_crtc_for_plane(dev_priv
, 0);
1767 if (intel_crtc_active(crtc
)) {
1768 const struct drm_display_mode
*adjusted_mode
=
1769 &crtc
->config
->base
.adjusted_mode
;
1770 const struct drm_framebuffer
*fb
=
1771 crtc
->base
.primary
->state
->fb
;
1774 if (IS_GEN2(dev_priv
))
1777 cpp
= fb
->format
->cpp
[0];
1779 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1780 wm_info
, fifo_size
, cpp
,
1781 pessimal_latency_ns
);
1784 planea_wm
= fifo_size
- wm_info
->guard_size
;
1785 if (planea_wm
> (long)wm_info
->max_wm
)
1786 planea_wm
= wm_info
->max_wm
;
1789 if (IS_GEN2(dev_priv
))
1790 wm_info
= &i830_bc_wm_info
;
1792 fifo_size
= dev_priv
->display
.get_fifo_size(dev_priv
, 1);
1793 crtc
= intel_get_crtc_for_plane(dev_priv
, 1);
1794 if (intel_crtc_active(crtc
)) {
1795 const struct drm_display_mode
*adjusted_mode
=
1796 &crtc
->config
->base
.adjusted_mode
;
1797 const struct drm_framebuffer
*fb
=
1798 crtc
->base
.primary
->state
->fb
;
1801 if (IS_GEN2(dev_priv
))
1804 cpp
= fb
->format
->cpp
[0];
1806 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1807 wm_info
, fifo_size
, cpp
,
1808 pessimal_latency_ns
);
1809 if (enabled
== NULL
)
1814 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1815 if (planeb_wm
> (long)wm_info
->max_wm
)
1816 planeb_wm
= wm_info
->max_wm
;
1819 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1821 if (IS_I915GM(dev_priv
) && enabled
) {
1822 struct drm_i915_gem_object
*obj
;
1824 obj
= intel_fb_obj(enabled
->base
.primary
->state
->fb
);
1826 /* self-refresh seems busted with untiled */
1827 if (!i915_gem_object_is_tiled(obj
))
1832 * Overlay gets an aggressive default since video jitter is bad.
1836 /* Play safe and disable self-refresh before adjusting watermarks. */
1837 intel_set_memory_cxsr(dev_priv
, false);
1839 /* Calc sr entries for one plane configs */
1840 if (HAS_FW_BLC(dev_priv
) && enabled
) {
1841 /* self-refresh has much higher latency */
1842 static const int sr_latency_ns
= 6000;
1843 const struct drm_display_mode
*adjusted_mode
=
1844 &enabled
->config
->base
.adjusted_mode
;
1845 const struct drm_framebuffer
*fb
=
1846 enabled
->base
.primary
->state
->fb
;
1847 int clock
= adjusted_mode
->crtc_clock
;
1848 int htotal
= adjusted_mode
->crtc_htotal
;
1849 int hdisplay
= enabled
->config
->pipe_src_w
;
1851 unsigned long line_time_us
;
1854 if (IS_I915GM(dev_priv
) || IS_I945GM(dev_priv
))
1857 cpp
= fb
->format
->cpp
[0];
1859 line_time_us
= max(htotal
* 1000 / clock
, 1);
1861 /* Use ns/us then divide to preserve precision */
1862 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1864 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1865 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1866 srwm
= wm_info
->fifo_size
- entries
;
1870 if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
))
1871 I915_WRITE(FW_BLC_SELF
,
1872 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1874 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1877 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1878 planea_wm
, planeb_wm
, cwm
, srwm
);
1880 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1881 fwater_hi
= (cwm
& 0x1f);
1883 /* Set request length to 8 cachelines per fetch */
1884 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1885 fwater_hi
= fwater_hi
| (1 << 8);
1887 I915_WRITE(FW_BLC
, fwater_lo
);
1888 I915_WRITE(FW_BLC2
, fwater_hi
);
1891 intel_set_memory_cxsr(dev_priv
, true);
1894 static void i845_update_wm(struct intel_crtc
*unused_crtc
)
1896 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
1897 struct intel_crtc
*crtc
;
1898 const struct drm_display_mode
*adjusted_mode
;
1902 crtc
= single_enabled_crtc(dev_priv
);
1906 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
1907 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1909 dev_priv
->display
.get_fifo_size(dev_priv
, 0),
1910 4, pessimal_latency_ns
);
1911 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1912 fwater_lo
|= (3<<8) | planea_wm
;
1914 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1916 I915_WRITE(FW_BLC
, fwater_lo
);
1919 /* latency must be in 0.1us units. */
1920 static uint32_t ilk_wm_method1(uint32_t pixel_rate
, uint8_t cpp
, uint32_t latency
)
1924 if (WARN(latency
== 0, "Latency value missing\n"))
1927 ret
= (uint64_t) pixel_rate
* cpp
* latency
;
1928 ret
= DIV_ROUND_UP_ULL(ret
, 64 * 10000) + 2;
1933 /* latency must be in 0.1us units. */
1934 static uint32_t ilk_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
1935 uint32_t horiz_pixels
, uint8_t cpp
,
1940 if (WARN(latency
== 0, "Latency value missing\n"))
1942 if (WARN_ON(!pipe_htotal
))
1945 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
1946 ret
= (ret
+ 1) * horiz_pixels
* cpp
;
1947 ret
= DIV_ROUND_UP(ret
, 64) + 2;
1951 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
1955 * Neither of these should be possible since this function shouldn't be
1956 * called if the CRTC is off or the plane is invisible. But let's be
1957 * extra paranoid to avoid a potential divide-by-zero if we screw up
1958 * elsewhere in the driver.
1962 if (WARN_ON(!horiz_pixels
))
1965 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* cpp
) + 2;
1968 struct ilk_wm_maximums
{
1976 * For both WM_PIPE and WM_LP.
1977 * mem_value must be in 0.1us units.
1979 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state
*cstate
,
1980 const struct intel_plane_state
*pstate
,
1984 uint32_t method1
, method2
;
1987 if (!intel_wm_plane_visible(cstate
, pstate
))
1990 cpp
= pstate
->base
.fb
->format
->cpp
[0];
1992 method1
= ilk_wm_method1(cstate
->pixel_rate
, cpp
, mem_value
);
1997 method2
= ilk_wm_method2(cstate
->pixel_rate
,
1998 cstate
->base
.adjusted_mode
.crtc_htotal
,
1999 drm_rect_width(&pstate
->base
.dst
),
2002 return min(method1
, method2
);
2006 * For both WM_PIPE and WM_LP.
2007 * mem_value must be in 0.1us units.
2009 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state
*cstate
,
2010 const struct intel_plane_state
*pstate
,
2013 uint32_t method1
, method2
;
2016 if (!intel_wm_plane_visible(cstate
, pstate
))
2019 cpp
= pstate
->base
.fb
->format
->cpp
[0];
2021 method1
= ilk_wm_method1(cstate
->pixel_rate
, cpp
, mem_value
);
2022 method2
= ilk_wm_method2(cstate
->pixel_rate
,
2023 cstate
->base
.adjusted_mode
.crtc_htotal
,
2024 drm_rect_width(&pstate
->base
.dst
),
2026 return min(method1
, method2
);
2030 * For both WM_PIPE and WM_LP.
2031 * mem_value must be in 0.1us units.
2033 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state
*cstate
,
2034 const struct intel_plane_state
*pstate
,
2039 if (!intel_wm_plane_visible(cstate
, pstate
))
2042 cpp
= pstate
->base
.fb
->format
->cpp
[0];
2044 return ilk_wm_method2(cstate
->pixel_rate
,
2045 cstate
->base
.adjusted_mode
.crtc_htotal
,
2046 pstate
->base
.crtc_w
, cpp
, mem_value
);
2049 /* Only for WM_LP. */
2050 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state
*cstate
,
2051 const struct intel_plane_state
*pstate
,
2056 if (!intel_wm_plane_visible(cstate
, pstate
))
2059 cpp
= pstate
->base
.fb
->format
->cpp
[0];
2061 return ilk_wm_fbc(pri_val
, drm_rect_width(&pstate
->base
.dst
), cpp
);
2065 ilk_display_fifo_size(const struct drm_i915_private
*dev_priv
)
2067 if (INTEL_GEN(dev_priv
) >= 8)
2069 else if (INTEL_GEN(dev_priv
) >= 7)
2076 ilk_plane_wm_reg_max(const struct drm_i915_private
*dev_priv
,
2077 int level
, bool is_sprite
)
2079 if (INTEL_GEN(dev_priv
) >= 8)
2080 /* BDW primary/sprite plane watermarks */
2081 return level
== 0 ? 255 : 2047;
2082 else if (INTEL_GEN(dev_priv
) >= 7)
2083 /* IVB/HSW primary/sprite plane watermarks */
2084 return level
== 0 ? 127 : 1023;
2085 else if (!is_sprite
)
2086 /* ILK/SNB primary plane watermarks */
2087 return level
== 0 ? 127 : 511;
2089 /* ILK/SNB sprite plane watermarks */
2090 return level
== 0 ? 63 : 255;
2094 ilk_cursor_wm_reg_max(const struct drm_i915_private
*dev_priv
, int level
)
2096 if (INTEL_GEN(dev_priv
) >= 7)
2097 return level
== 0 ? 63 : 255;
2099 return level
== 0 ? 31 : 63;
2102 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private
*dev_priv
)
2104 if (INTEL_GEN(dev_priv
) >= 8)
2110 /* Calculate the maximum primary/sprite plane watermark */
2111 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
2113 const struct intel_wm_config
*config
,
2114 enum intel_ddb_partitioning ddb_partitioning
,
2117 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2118 unsigned int fifo_size
= ilk_display_fifo_size(dev_priv
);
2120 /* if sprites aren't enabled, sprites get nothing */
2121 if (is_sprite
&& !config
->sprites_enabled
)
2124 /* HSW allows LP1+ watermarks even with multiple pipes */
2125 if (level
== 0 || config
->num_pipes_active
> 1) {
2126 fifo_size
/= INTEL_INFO(dev_priv
)->num_pipes
;
2129 * For some reason the non self refresh
2130 * FIFO size is only half of the self
2131 * refresh FIFO size on ILK/SNB.
2133 if (INTEL_GEN(dev_priv
) <= 6)
2137 if (config
->sprites_enabled
) {
2138 /* level 0 is always calculated with 1:1 split */
2139 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
2148 /* clamp to max that the registers can hold */
2149 return min(fifo_size
, ilk_plane_wm_reg_max(dev_priv
, level
, is_sprite
));
2152 /* Calculate the maximum cursor plane watermark */
2153 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
2155 const struct intel_wm_config
*config
)
2157 /* HSW LP1+ watermarks w/ multiple pipes */
2158 if (level
> 0 && config
->num_pipes_active
> 1)
2161 /* otherwise just report max that registers can hold */
2162 return ilk_cursor_wm_reg_max(to_i915(dev
), level
);
2165 static void ilk_compute_wm_maximums(const struct drm_device
*dev
,
2167 const struct intel_wm_config
*config
,
2168 enum intel_ddb_partitioning ddb_partitioning
,
2169 struct ilk_wm_maximums
*max
)
2171 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
2172 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
2173 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
2174 max
->fbc
= ilk_fbc_wm_reg_max(to_i915(dev
));
2177 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private
*dev_priv
,
2179 struct ilk_wm_maximums
*max
)
2181 max
->pri
= ilk_plane_wm_reg_max(dev_priv
, level
, false);
2182 max
->spr
= ilk_plane_wm_reg_max(dev_priv
, level
, true);
2183 max
->cur
= ilk_cursor_wm_reg_max(dev_priv
, level
);
2184 max
->fbc
= ilk_fbc_wm_reg_max(dev_priv
);
2187 static bool ilk_validate_wm_level(int level
,
2188 const struct ilk_wm_maximums
*max
,
2189 struct intel_wm_level
*result
)
2193 /* already determined to be invalid? */
2194 if (!result
->enable
)
2197 result
->enable
= result
->pri_val
<= max
->pri
&&
2198 result
->spr_val
<= max
->spr
&&
2199 result
->cur_val
<= max
->cur
;
2201 ret
= result
->enable
;
2204 * HACK until we can pre-compute everything,
2205 * and thus fail gracefully if LP0 watermarks
2208 if (level
== 0 && !result
->enable
) {
2209 if (result
->pri_val
> max
->pri
)
2210 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2211 level
, result
->pri_val
, max
->pri
);
2212 if (result
->spr_val
> max
->spr
)
2213 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2214 level
, result
->spr_val
, max
->spr
);
2215 if (result
->cur_val
> max
->cur
)
2216 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2217 level
, result
->cur_val
, max
->cur
);
2219 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
2220 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
2221 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
2222 result
->enable
= true;
2228 static void ilk_compute_wm_level(const struct drm_i915_private
*dev_priv
,
2229 const struct intel_crtc
*intel_crtc
,
2231 struct intel_crtc_state
*cstate
,
2232 struct intel_plane_state
*pristate
,
2233 struct intel_plane_state
*sprstate
,
2234 struct intel_plane_state
*curstate
,
2235 struct intel_wm_level
*result
)
2237 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
2238 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
2239 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
2241 /* WM1+ latency values stored in 0.5us units */
2249 result
->pri_val
= ilk_compute_pri_wm(cstate
, pristate
,
2250 pri_latency
, level
);
2251 result
->fbc_val
= ilk_compute_fbc_wm(cstate
, pristate
, result
->pri_val
);
2255 result
->spr_val
= ilk_compute_spr_wm(cstate
, sprstate
, spr_latency
);
2258 result
->cur_val
= ilk_compute_cur_wm(cstate
, curstate
, cur_latency
);
2260 result
->enable
= true;
2264 hsw_compute_linetime_wm(const struct intel_crtc_state
*cstate
)
2266 const struct intel_atomic_state
*intel_state
=
2267 to_intel_atomic_state(cstate
->base
.state
);
2268 const struct drm_display_mode
*adjusted_mode
=
2269 &cstate
->base
.adjusted_mode
;
2270 u32 linetime
, ips_linetime
;
2272 if (!cstate
->base
.active
)
2274 if (WARN_ON(adjusted_mode
->crtc_clock
== 0))
2276 if (WARN_ON(intel_state
->cdclk
.logical
.cdclk
== 0))
2279 /* The WM are computed with base on how long it takes to fill a single
2280 * row at the given clock rate, multiplied by 8.
2282 linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2283 adjusted_mode
->crtc_clock
);
2284 ips_linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2285 intel_state
->cdclk
.logical
.cdclk
);
2287 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2288 PIPE_WM_LINETIME_TIME(linetime
);
2291 static void intel_read_wm_latency(struct drm_i915_private
*dev_priv
,
2294 if (IS_GEN9(dev_priv
)) {
2297 int level
, max_level
= ilk_wm_max_level(dev_priv
);
2299 /* read the first set of memory latencies[0:3] */
2300 val
= 0; /* data0 to be programmed to 0 for first set */
2301 mutex_lock(&dev_priv
->rps
.hw_lock
);
2302 ret
= sandybridge_pcode_read(dev_priv
,
2303 GEN9_PCODE_READ_MEM_LATENCY
,
2305 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2308 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2312 wm
[0] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2313 wm
[1] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2314 GEN9_MEM_LATENCY_LEVEL_MASK
;
2315 wm
[2] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2316 GEN9_MEM_LATENCY_LEVEL_MASK
;
2317 wm
[3] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2318 GEN9_MEM_LATENCY_LEVEL_MASK
;
2320 /* read the second set of memory latencies[4:7] */
2321 val
= 1; /* data0 to be programmed to 1 for second set */
2322 mutex_lock(&dev_priv
->rps
.hw_lock
);
2323 ret
= sandybridge_pcode_read(dev_priv
,
2324 GEN9_PCODE_READ_MEM_LATENCY
,
2326 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2328 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2332 wm
[4] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2333 wm
[5] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2334 GEN9_MEM_LATENCY_LEVEL_MASK
;
2335 wm
[6] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2336 GEN9_MEM_LATENCY_LEVEL_MASK
;
2337 wm
[7] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2338 GEN9_MEM_LATENCY_LEVEL_MASK
;
2341 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2342 * need to be disabled. We make sure to sanitize the values out
2343 * of the punit to satisfy this requirement.
2345 for (level
= 1; level
<= max_level
; level
++) {
2346 if (wm
[level
] == 0) {
2347 for (i
= level
+ 1; i
<= max_level
; i
++)
2354 * WaWmMemoryReadLatency:skl,glk
2356 * punit doesn't take into account the read latency so we need
2357 * to add 2us to the various latency levels we retrieve from the
2358 * punit when level 0 response data us 0us.
2362 for (level
= 1; level
<= max_level
; level
++) {
2369 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2370 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2372 wm
[0] = (sskpd
>> 56) & 0xFF;
2374 wm
[0] = sskpd
& 0xF;
2375 wm
[1] = (sskpd
>> 4) & 0xFF;
2376 wm
[2] = (sskpd
>> 12) & 0xFF;
2377 wm
[3] = (sskpd
>> 20) & 0x1FF;
2378 wm
[4] = (sskpd
>> 32) & 0x1FF;
2379 } else if (INTEL_GEN(dev_priv
) >= 6) {
2380 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
2382 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
2383 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
2384 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
2385 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
2386 } else if (INTEL_GEN(dev_priv
) >= 5) {
2387 uint32_t mltr
= I915_READ(MLTR_ILK
);
2389 /* ILK primary LP0 latency is 700 ns */
2391 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
2392 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
2396 static void intel_fixup_spr_wm_latency(struct drm_i915_private
*dev_priv
,
2399 /* ILK sprite LP0 latency is 1300 ns */
2400 if (IS_GEN5(dev_priv
))
2404 static void intel_fixup_cur_wm_latency(struct drm_i915_private
*dev_priv
,
2407 /* ILK cursor LP0 latency is 1300 ns */
2408 if (IS_GEN5(dev_priv
))
2411 /* WaDoubleCursorLP3Latency:ivb */
2412 if (IS_IVYBRIDGE(dev_priv
))
2416 int ilk_wm_max_level(const struct drm_i915_private
*dev_priv
)
2418 /* how many WM levels are we expecting */
2419 if (INTEL_GEN(dev_priv
) >= 9)
2421 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
2423 else if (INTEL_GEN(dev_priv
) >= 6)
2429 static void intel_print_wm_latency(struct drm_i915_private
*dev_priv
,
2431 const uint16_t wm
[8])
2433 int level
, max_level
= ilk_wm_max_level(dev_priv
);
2435 for (level
= 0; level
<= max_level
; level
++) {
2436 unsigned int latency
= wm
[level
];
2439 DRM_ERROR("%s WM%d latency not provided\n",
2445 * - latencies are in us on gen9.
2446 * - before then, WM1+ latency values are in 0.5us units
2448 if (IS_GEN9(dev_priv
))
2453 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2454 name
, level
, wm
[level
],
2455 latency
/ 10, latency
% 10);
2459 static bool ilk_increase_wm_latency(struct drm_i915_private
*dev_priv
,
2460 uint16_t wm
[5], uint16_t min
)
2462 int level
, max_level
= ilk_wm_max_level(dev_priv
);
2467 wm
[0] = max(wm
[0], min
);
2468 for (level
= 1; level
<= max_level
; level
++)
2469 wm
[level
] = max_t(uint16_t, wm
[level
], DIV_ROUND_UP(min
, 5));
2474 static void snb_wm_latency_quirk(struct drm_i915_private
*dev_priv
)
2479 * The BIOS provided WM memory latency values are often
2480 * inadequate for high resolution displays. Adjust them.
2482 changed
= ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
, 12) |
2483 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
, 12) |
2484 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
, 12);
2489 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2490 intel_print_wm_latency(dev_priv
, "Primary", dev_priv
->wm
.pri_latency
);
2491 intel_print_wm_latency(dev_priv
, "Sprite", dev_priv
->wm
.spr_latency
);
2492 intel_print_wm_latency(dev_priv
, "Cursor", dev_priv
->wm
.cur_latency
);
2495 static void ilk_setup_wm_latency(struct drm_i915_private
*dev_priv
)
2497 intel_read_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
);
2499 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
2500 sizeof(dev_priv
->wm
.pri_latency
));
2501 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
2502 sizeof(dev_priv
->wm
.pri_latency
));
2504 intel_fixup_spr_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
);
2505 intel_fixup_cur_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
);
2507 intel_print_wm_latency(dev_priv
, "Primary", dev_priv
->wm
.pri_latency
);
2508 intel_print_wm_latency(dev_priv
, "Sprite", dev_priv
->wm
.spr_latency
);
2509 intel_print_wm_latency(dev_priv
, "Cursor", dev_priv
->wm
.cur_latency
);
2511 if (IS_GEN6(dev_priv
))
2512 snb_wm_latency_quirk(dev_priv
);
2515 static void skl_setup_wm_latency(struct drm_i915_private
*dev_priv
)
2517 intel_read_wm_latency(dev_priv
, dev_priv
->wm
.skl_latency
);
2518 intel_print_wm_latency(dev_priv
, "Gen9 Plane", dev_priv
->wm
.skl_latency
);
2521 static bool ilk_validate_pipe_wm(struct drm_device
*dev
,
2522 struct intel_pipe_wm
*pipe_wm
)
2524 /* LP0 watermark maximums depend on this pipe alone */
2525 const struct intel_wm_config config
= {
2526 .num_pipes_active
= 1,
2527 .sprites_enabled
= pipe_wm
->sprites_enabled
,
2528 .sprites_scaled
= pipe_wm
->sprites_scaled
,
2530 struct ilk_wm_maximums max
;
2532 /* LP0 watermarks always use 1/2 DDB partitioning */
2533 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
2535 /* At least LP0 must be valid */
2536 if (!ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0])) {
2537 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2544 /* Compute new watermarks for the pipe */
2545 static int ilk_compute_pipe_wm(struct intel_crtc_state
*cstate
)
2547 struct drm_atomic_state
*state
= cstate
->base
.state
;
2548 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
2549 struct intel_pipe_wm
*pipe_wm
;
2550 struct drm_device
*dev
= state
->dev
;
2551 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
2552 struct intel_plane
*intel_plane
;
2553 struct intel_plane_state
*pristate
= NULL
;
2554 struct intel_plane_state
*sprstate
= NULL
;
2555 struct intel_plane_state
*curstate
= NULL
;
2556 int level
, max_level
= ilk_wm_max_level(dev_priv
), usable_level
;
2557 struct ilk_wm_maximums max
;
2559 pipe_wm
= &cstate
->wm
.ilk
.optimal
;
2561 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
2562 struct intel_plane_state
*ps
;
2564 ps
= intel_atomic_get_existing_plane_state(state
,
2569 if (intel_plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
2571 else if (intel_plane
->base
.type
== DRM_PLANE_TYPE_OVERLAY
)
2573 else if (intel_plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
2577 pipe_wm
->pipe_enabled
= cstate
->base
.active
;
2579 pipe_wm
->sprites_enabled
= sprstate
->base
.visible
;
2580 pipe_wm
->sprites_scaled
= sprstate
->base
.visible
&&
2581 (drm_rect_width(&sprstate
->base
.dst
) != drm_rect_width(&sprstate
->base
.src
) >> 16 ||
2582 drm_rect_height(&sprstate
->base
.dst
) != drm_rect_height(&sprstate
->base
.src
) >> 16);
2585 usable_level
= max_level
;
2587 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2588 if (INTEL_GEN(dev_priv
) <= 6 && pipe_wm
->sprites_enabled
)
2591 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2592 if (pipe_wm
->sprites_scaled
)
2595 ilk_compute_wm_level(dev_priv
, intel_crtc
, 0, cstate
,
2596 pristate
, sprstate
, curstate
, &pipe_wm
->raw_wm
[0]);
2598 memset(&pipe_wm
->wm
, 0, sizeof(pipe_wm
->wm
));
2599 pipe_wm
->wm
[0] = pipe_wm
->raw_wm
[0];
2601 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
2602 pipe_wm
->linetime
= hsw_compute_linetime_wm(cstate
);
2604 if (!ilk_validate_pipe_wm(dev
, pipe_wm
))
2607 ilk_compute_wm_reg_maximums(dev_priv
, 1, &max
);
2609 for (level
= 1; level
<= max_level
; level
++) {
2610 struct intel_wm_level
*wm
= &pipe_wm
->raw_wm
[level
];
2612 ilk_compute_wm_level(dev_priv
, intel_crtc
, level
, cstate
,
2613 pristate
, sprstate
, curstate
, wm
);
2616 * Disable any watermark level that exceeds the
2617 * register maximums since such watermarks are
2620 if (level
> usable_level
)
2623 if (ilk_validate_wm_level(level
, &max
, wm
))
2624 pipe_wm
->wm
[level
] = *wm
;
2626 usable_level
= level
;
2633 * Build a set of 'intermediate' watermark values that satisfy both the old
2634 * state and the new state. These can be programmed to the hardware
2637 static int ilk_compute_intermediate_wm(struct drm_device
*dev
,
2638 struct intel_crtc
*intel_crtc
,
2639 struct intel_crtc_state
*newstate
)
2641 struct intel_pipe_wm
*a
= &newstate
->wm
.ilk
.intermediate
;
2642 struct intel_pipe_wm
*b
= &intel_crtc
->wm
.active
.ilk
;
2643 int level
, max_level
= ilk_wm_max_level(to_i915(dev
));
2646 * Start with the final, target watermarks, then combine with the
2647 * currently active watermarks to get values that are safe both before
2648 * and after the vblank.
2650 *a
= newstate
->wm
.ilk
.optimal
;
2651 a
->pipe_enabled
|= b
->pipe_enabled
;
2652 a
->sprites_enabled
|= b
->sprites_enabled
;
2653 a
->sprites_scaled
|= b
->sprites_scaled
;
2655 for (level
= 0; level
<= max_level
; level
++) {
2656 struct intel_wm_level
*a_wm
= &a
->wm
[level
];
2657 const struct intel_wm_level
*b_wm
= &b
->wm
[level
];
2659 a_wm
->enable
&= b_wm
->enable
;
2660 a_wm
->pri_val
= max(a_wm
->pri_val
, b_wm
->pri_val
);
2661 a_wm
->spr_val
= max(a_wm
->spr_val
, b_wm
->spr_val
);
2662 a_wm
->cur_val
= max(a_wm
->cur_val
, b_wm
->cur_val
);
2663 a_wm
->fbc_val
= max(a_wm
->fbc_val
, b_wm
->fbc_val
);
2667 * We need to make sure that these merged watermark values are
2668 * actually a valid configuration themselves. If they're not,
2669 * there's no safe way to transition from the old state to
2670 * the new state, so we need to fail the atomic transaction.
2672 if (!ilk_validate_pipe_wm(dev
, a
))
2676 * If our intermediate WM are identical to the final WM, then we can
2677 * omit the post-vblank programming; only update if it's different.
2679 if (memcmp(a
, &newstate
->wm
.ilk
.optimal
, sizeof(*a
)) != 0)
2680 newstate
->wm
.need_postvbl_update
= true;
2686 * Merge the watermarks from all active pipes for a specific level.
2688 static void ilk_merge_wm_level(struct drm_device
*dev
,
2690 struct intel_wm_level
*ret_wm
)
2692 const struct intel_crtc
*intel_crtc
;
2694 ret_wm
->enable
= true;
2696 for_each_intel_crtc(dev
, intel_crtc
) {
2697 const struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
.ilk
;
2698 const struct intel_wm_level
*wm
= &active
->wm
[level
];
2700 if (!active
->pipe_enabled
)
2704 * The watermark values may have been used in the past,
2705 * so we must maintain them in the registers for some
2706 * time even if the level is now disabled.
2709 ret_wm
->enable
= false;
2711 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
2712 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
2713 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
2714 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
2719 * Merge all low power watermarks for all active pipes.
2721 static void ilk_wm_merge(struct drm_device
*dev
,
2722 const struct intel_wm_config
*config
,
2723 const struct ilk_wm_maximums
*max
,
2724 struct intel_pipe_wm
*merged
)
2726 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2727 int level
, max_level
= ilk_wm_max_level(dev_priv
);
2728 int last_enabled_level
= max_level
;
2730 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2731 if ((INTEL_GEN(dev_priv
) <= 6 || IS_IVYBRIDGE(dev_priv
)) &&
2732 config
->num_pipes_active
> 1)
2733 last_enabled_level
= 0;
2735 /* ILK: FBC WM must be disabled always */
2736 merged
->fbc_wm_enabled
= INTEL_GEN(dev_priv
) >= 6;
2738 /* merge each WM1+ level */
2739 for (level
= 1; level
<= max_level
; level
++) {
2740 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2742 ilk_merge_wm_level(dev
, level
, wm
);
2744 if (level
> last_enabled_level
)
2746 else if (!ilk_validate_wm_level(level
, max
, wm
))
2747 /* make sure all following levels get disabled */
2748 last_enabled_level
= level
- 1;
2751 * The spec says it is preferred to disable
2752 * FBC WMs instead of disabling a WM level.
2754 if (wm
->fbc_val
> max
->fbc
) {
2756 merged
->fbc_wm_enabled
= false;
2761 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2763 * FIXME this is racy. FBC might get enabled later.
2764 * What we should check here is whether FBC can be
2765 * enabled sometime later.
2767 if (IS_GEN5(dev_priv
) && !merged
->fbc_wm_enabled
&&
2768 intel_fbc_is_active(dev_priv
)) {
2769 for (level
= 2; level
<= max_level
; level
++) {
2770 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2777 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
2779 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2780 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
2783 /* The value we need to program into the WM_LPx latency field */
2784 static unsigned int ilk_wm_lp_latency(struct drm_device
*dev
, int level
)
2786 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2788 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
2791 return dev_priv
->wm
.pri_latency
[level
];
2794 static void ilk_compute_wm_results(struct drm_device
*dev
,
2795 const struct intel_pipe_wm
*merged
,
2796 enum intel_ddb_partitioning partitioning
,
2797 struct ilk_wm_values
*results
)
2799 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2800 struct intel_crtc
*intel_crtc
;
2803 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
2804 results
->partitioning
= partitioning
;
2806 /* LP1+ register values */
2807 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2808 const struct intel_wm_level
*r
;
2810 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
2812 r
= &merged
->wm
[level
];
2815 * Maintain the watermark values even if the level is
2816 * disabled. Doing otherwise could cause underruns.
2818 results
->wm_lp
[wm_lp
- 1] =
2819 (ilk_wm_lp_latency(dev
, level
) << WM1_LP_LATENCY_SHIFT
) |
2820 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
2824 results
->wm_lp
[wm_lp
- 1] |= WM1_LP_SR_EN
;
2826 if (INTEL_GEN(dev_priv
) >= 8)
2827 results
->wm_lp
[wm_lp
- 1] |=
2828 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
2830 results
->wm_lp
[wm_lp
- 1] |=
2831 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
2834 * Always set WM1S_LP_EN when spr_val != 0, even if the
2835 * level is disabled. Doing otherwise could cause underruns.
2837 if (INTEL_GEN(dev_priv
) <= 6 && r
->spr_val
) {
2838 WARN_ON(wm_lp
!= 1);
2839 results
->wm_lp_spr
[wm_lp
- 1] = WM1S_LP_EN
| r
->spr_val
;
2841 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
2844 /* LP0 register values */
2845 for_each_intel_crtc(dev
, intel_crtc
) {
2846 enum pipe pipe
= intel_crtc
->pipe
;
2847 const struct intel_wm_level
*r
=
2848 &intel_crtc
->wm
.active
.ilk
.wm
[0];
2850 if (WARN_ON(!r
->enable
))
2853 results
->wm_linetime
[pipe
] = intel_crtc
->wm
.active
.ilk
.linetime
;
2855 results
->wm_pipe
[pipe
] =
2856 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
2857 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
2862 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2863 * case both are at the same level. Prefer r1 in case they're the same. */
2864 static struct intel_pipe_wm
*ilk_find_best_result(struct drm_device
*dev
,
2865 struct intel_pipe_wm
*r1
,
2866 struct intel_pipe_wm
*r2
)
2868 int level
, max_level
= ilk_wm_max_level(to_i915(dev
));
2869 int level1
= 0, level2
= 0;
2871 for (level
= 1; level
<= max_level
; level
++) {
2872 if (r1
->wm
[level
].enable
)
2874 if (r2
->wm
[level
].enable
)
2878 if (level1
== level2
) {
2879 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
2883 } else if (level1
> level2
) {
2890 /* dirty bits used to track which watermarks need changes */
2891 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2892 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2893 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2894 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2895 #define WM_DIRTY_FBC (1 << 24)
2896 #define WM_DIRTY_DDB (1 << 25)
2898 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private
*dev_priv
,
2899 const struct ilk_wm_values
*old
,
2900 const struct ilk_wm_values
*new)
2902 unsigned int dirty
= 0;
2906 for_each_pipe(dev_priv
, pipe
) {
2907 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
2908 dirty
|= WM_DIRTY_LINETIME(pipe
);
2909 /* Must disable LP1+ watermarks too */
2910 dirty
|= WM_DIRTY_LP_ALL
;
2913 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
2914 dirty
|= WM_DIRTY_PIPE(pipe
);
2915 /* Must disable LP1+ watermarks too */
2916 dirty
|= WM_DIRTY_LP_ALL
;
2920 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
2921 dirty
|= WM_DIRTY_FBC
;
2922 /* Must disable LP1+ watermarks too */
2923 dirty
|= WM_DIRTY_LP_ALL
;
2926 if (old
->partitioning
!= new->partitioning
) {
2927 dirty
|= WM_DIRTY_DDB
;
2928 /* Must disable LP1+ watermarks too */
2929 dirty
|= WM_DIRTY_LP_ALL
;
2932 /* LP1+ watermarks already deemed dirty, no need to continue */
2933 if (dirty
& WM_DIRTY_LP_ALL
)
2936 /* Find the lowest numbered LP1+ watermark in need of an update... */
2937 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2938 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
2939 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
2943 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2944 for (; wm_lp
<= 3; wm_lp
++)
2945 dirty
|= WM_DIRTY_LP(wm_lp
);
2950 static bool _ilk_disable_lp_wm(struct drm_i915_private
*dev_priv
,
2953 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2954 bool changed
= false;
2956 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] & WM1_LP_SR_EN
) {
2957 previous
->wm_lp
[2] &= ~WM1_LP_SR_EN
;
2958 I915_WRITE(WM3_LP_ILK
, previous
->wm_lp
[2]);
2961 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] & WM1_LP_SR_EN
) {
2962 previous
->wm_lp
[1] &= ~WM1_LP_SR_EN
;
2963 I915_WRITE(WM2_LP_ILK
, previous
->wm_lp
[1]);
2966 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] & WM1_LP_SR_EN
) {
2967 previous
->wm_lp
[0] &= ~WM1_LP_SR_EN
;
2968 I915_WRITE(WM1_LP_ILK
, previous
->wm_lp
[0]);
2973 * Don't touch WM1S_LP_EN here.
2974 * Doing so could cause underruns.
2981 * The spec says we shouldn't write when we don't need, because every write
2982 * causes WMs to be re-evaluated, expending some power.
2984 static void ilk_write_wm_values(struct drm_i915_private
*dev_priv
,
2985 struct ilk_wm_values
*results
)
2987 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2991 dirty
= ilk_compute_wm_dirty(dev_priv
, previous
, results
);
2995 _ilk_disable_lp_wm(dev_priv
, dirty
);
2997 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
2998 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
2999 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
3000 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
3001 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
3002 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
3004 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
3005 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
3006 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
3007 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
3008 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
3009 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
3011 if (dirty
& WM_DIRTY_DDB
) {
3012 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3013 val
= I915_READ(WM_MISC
);
3014 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
3015 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
3017 val
|= WM_MISC_DATA_PARTITION_5_6
;
3018 I915_WRITE(WM_MISC
, val
);
3020 val
= I915_READ(DISP_ARB_CTL2
);
3021 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
3022 val
&= ~DISP_DATA_PARTITION_5_6
;
3024 val
|= DISP_DATA_PARTITION_5_6
;
3025 I915_WRITE(DISP_ARB_CTL2
, val
);
3029 if (dirty
& WM_DIRTY_FBC
) {
3030 val
= I915_READ(DISP_ARB_CTL
);
3031 if (results
->enable_fbc_wm
)
3032 val
&= ~DISP_FBC_WM_DIS
;
3034 val
|= DISP_FBC_WM_DIS
;
3035 I915_WRITE(DISP_ARB_CTL
, val
);
3038 if (dirty
& WM_DIRTY_LP(1) &&
3039 previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
3040 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
3042 if (INTEL_GEN(dev_priv
) >= 7) {
3043 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
3044 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
3045 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
3046 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
3049 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != results
->wm_lp
[0])
3050 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
3051 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != results
->wm_lp
[1])
3052 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
3053 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != results
->wm_lp
[2])
3054 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
3056 dev_priv
->wm
.hw
= *results
;
3059 bool ilk_disable_lp_wm(struct drm_device
*dev
)
3061 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3063 return _ilk_disable_lp_wm(dev_priv
, WM_DIRTY_LP_ALL
);
3066 #define SKL_SAGV_BLOCK_TIME 30 /* µs */
3069 * FIXME: We still don't have the proper code detect if we need to apply the WA,
3070 * so assume we'll always need it in order to avoid underruns.
3072 static bool skl_needs_memory_bw_wa(struct intel_atomic_state
*state
)
3074 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
3076 if (IS_GEN9_BC(dev_priv
) || IS_BROXTON(dev_priv
))
3083 intel_has_sagv(struct drm_i915_private
*dev_priv
)
3085 if (IS_KABYLAKE(dev_priv
))
3088 if (IS_SKYLAKE(dev_priv
) &&
3089 dev_priv
->sagv_status
!= I915_SAGV_NOT_CONTROLLED
)
3096 * SAGV dynamically adjusts the system agent voltage and clock frequencies
3097 * depending on power and performance requirements. The display engine access
3098 * to system memory is blocked during the adjustment time. Because of the
3099 * blocking time, having this enabled can cause full system hangs and/or pipe
3100 * underruns if we don't meet all of the following requirements:
3102 * - <= 1 pipe enabled
3103 * - All planes can enable watermarks for latencies >= SAGV engine block time
3104 * - We're not using an interlaced display configuration
3107 intel_enable_sagv(struct drm_i915_private
*dev_priv
)
3111 if (!intel_has_sagv(dev_priv
))
3114 if (dev_priv
->sagv_status
== I915_SAGV_ENABLED
)
3117 DRM_DEBUG_KMS("Enabling the SAGV\n");
3118 mutex_lock(&dev_priv
->rps
.hw_lock
);
3120 ret
= sandybridge_pcode_write(dev_priv
, GEN9_PCODE_SAGV_CONTROL
,
3123 /* We don't need to wait for the SAGV when enabling */
3124 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3127 * Some skl systems, pre-release machines in particular,
3128 * don't actually have an SAGV.
3130 if (IS_SKYLAKE(dev_priv
) && ret
== -ENXIO
) {
3131 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3132 dev_priv
->sagv_status
= I915_SAGV_NOT_CONTROLLED
;
3134 } else if (ret
< 0) {
3135 DRM_ERROR("Failed to enable the SAGV\n");
3139 dev_priv
->sagv_status
= I915_SAGV_ENABLED
;
3144 intel_disable_sagv(struct drm_i915_private
*dev_priv
)
3148 if (!intel_has_sagv(dev_priv
))
3151 if (dev_priv
->sagv_status
== I915_SAGV_DISABLED
)
3154 DRM_DEBUG_KMS("Disabling the SAGV\n");
3155 mutex_lock(&dev_priv
->rps
.hw_lock
);
3157 /* bspec says to keep retrying for at least 1 ms */
3158 ret
= skl_pcode_request(dev_priv
, GEN9_PCODE_SAGV_CONTROL
,
3160 GEN9_SAGV_IS_DISABLED
, GEN9_SAGV_IS_DISABLED
,
3162 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3165 * Some skl systems, pre-release machines in particular,
3166 * don't actually have an SAGV.
3168 if (IS_SKYLAKE(dev_priv
) && ret
== -ENXIO
) {
3169 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3170 dev_priv
->sagv_status
= I915_SAGV_NOT_CONTROLLED
;
3172 } else if (ret
< 0) {
3173 DRM_ERROR("Failed to disable the SAGV (%d)\n", ret
);
3177 dev_priv
->sagv_status
= I915_SAGV_DISABLED
;
3181 bool intel_can_enable_sagv(struct drm_atomic_state
*state
)
3183 struct drm_device
*dev
= state
->dev
;
3184 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3185 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
3186 struct intel_crtc
*crtc
;
3187 struct intel_plane
*plane
;
3188 struct intel_crtc_state
*cstate
;
3192 if (!intel_has_sagv(dev_priv
))
3196 * SKL workaround: bspec recommends we disable the SAGV when we have
3197 * more then one pipe enabled
3199 * If there are no active CRTCs, no additional checks need be performed
3201 if (hweight32(intel_state
->active_crtcs
) == 0)
3203 else if (hweight32(intel_state
->active_crtcs
) > 1)
3206 /* Since we're now guaranteed to only have one active CRTC... */
3207 pipe
= ffs(intel_state
->active_crtcs
) - 1;
3208 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
3209 cstate
= to_intel_crtc_state(crtc
->base
.state
);
3211 if (crtc
->base
.state
->adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
3214 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
3215 struct skl_plane_wm
*wm
=
3216 &cstate
->wm
.skl
.optimal
.planes
[plane
->id
];
3218 /* Skip this plane if it's not enabled */
3219 if (!wm
->wm
[0].plane_en
)
3222 /* Find the highest enabled wm level for this plane */
3223 for (level
= ilk_wm_max_level(dev_priv
);
3224 !wm
->wm
[level
].plane_en
; --level
)
3227 latency
= dev_priv
->wm
.skl_latency
[level
];
3229 if (skl_needs_memory_bw_wa(intel_state
) &&
3230 plane
->base
.state
->fb
->modifier
==
3231 I915_FORMAT_MOD_X_TILED
)
3235 * If any of the planes on this pipe don't enable wm levels
3236 * that incur memory latencies higher then 30µs we can't enable
3239 if (latency
< SKL_SAGV_BLOCK_TIME
)
3247 skl_ddb_get_pipe_allocation_limits(struct drm_device
*dev
,
3248 const struct intel_crtc_state
*cstate
,
3249 struct skl_ddb_entry
*alloc
, /* out */
3250 int *num_active
/* out */)
3252 struct drm_atomic_state
*state
= cstate
->base
.state
;
3253 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
3254 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3255 struct drm_crtc
*for_crtc
= cstate
->base
.crtc
;
3256 unsigned int pipe_size
, ddb_size
;
3257 int nth_active_pipe
;
3259 if (WARN_ON(!state
) || !cstate
->base
.active
) {
3262 *num_active
= hweight32(dev_priv
->active_crtcs
);
3266 if (intel_state
->active_pipe_changes
)
3267 *num_active
= hweight32(intel_state
->active_crtcs
);
3269 *num_active
= hweight32(dev_priv
->active_crtcs
);
3271 ddb_size
= INTEL_INFO(dev_priv
)->ddb_size
;
3272 WARN_ON(ddb_size
== 0);
3274 ddb_size
-= 4; /* 4 blocks for bypass path allocation */
3277 * If the state doesn't change the active CRTC's, then there's
3278 * no need to recalculate; the existing pipe allocation limits
3279 * should remain unchanged. Note that we're safe from racing
3280 * commits since any racing commit that changes the active CRTC
3281 * list would need to grab _all_ crtc locks, including the one
3282 * we currently hold.
3284 if (!intel_state
->active_pipe_changes
) {
3286 * alloc may be cleared by clear_intel_crtc_state,
3287 * copy from old state to be sure
3289 *alloc
= to_intel_crtc_state(for_crtc
->state
)->wm
.skl
.ddb
;
3293 nth_active_pipe
= hweight32(intel_state
->active_crtcs
&
3294 (drm_crtc_mask(for_crtc
) - 1));
3295 pipe_size
= ddb_size
/ hweight32(intel_state
->active_crtcs
);
3296 alloc
->start
= nth_active_pipe
* ddb_size
/ *num_active
;
3297 alloc
->end
= alloc
->start
+ pipe_size
;
3300 static unsigned int skl_cursor_allocation(int num_active
)
3302 if (num_active
== 1)
3308 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry
*entry
, u32 reg
)
3310 entry
->start
= reg
& 0x3ff;
3311 entry
->end
= (reg
>> 16) & 0x3ff;
3316 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
3317 struct skl_ddb_allocation
*ddb
/* out */)
3319 struct intel_crtc
*crtc
;
3321 memset(ddb
, 0, sizeof(*ddb
));
3323 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
3324 enum intel_display_power_domain power_domain
;
3325 enum plane_id plane_id
;
3326 enum pipe pipe
= crtc
->pipe
;
3328 power_domain
= POWER_DOMAIN_PIPE(pipe
);
3329 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
3332 for_each_plane_id_on_crtc(crtc
, plane_id
) {
3335 if (plane_id
!= PLANE_CURSOR
)
3336 val
= I915_READ(PLANE_BUF_CFG(pipe
, plane_id
));
3338 val
= I915_READ(CUR_BUF_CFG(pipe
));
3340 skl_ddb_entry_init_from_hw(&ddb
->plane
[pipe
][plane_id
], val
);
3343 intel_display_power_put(dev_priv
, power_domain
);
3348 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3349 * The bspec defines downscale amount as:
3352 * Horizontal down scale amount = maximum[1, Horizontal source size /
3353 * Horizontal destination size]
3354 * Vertical down scale amount = maximum[1, Vertical source size /
3355 * Vertical destination size]
3356 * Total down scale amount = Horizontal down scale amount *
3357 * Vertical down scale amount
3360 * Return value is provided in 16.16 fixed point form to retain fractional part.
3361 * Caller should take care of dividing & rounding off the value.
3364 skl_plane_downscale_amount(const struct intel_crtc_state
*cstate
,
3365 const struct intel_plane_state
*pstate
)
3367 struct intel_plane
*plane
= to_intel_plane(pstate
->base
.plane
);
3368 uint32_t downscale_h
, downscale_w
;
3369 uint32_t src_w
, src_h
, dst_w
, dst_h
;
3371 if (WARN_ON(!intel_wm_plane_visible(cstate
, pstate
)))
3372 return DRM_PLANE_HELPER_NO_SCALING
;
3374 /* n.b., src is 16.16 fixed point, dst is whole integer */
3375 if (plane
->id
== PLANE_CURSOR
) {
3377 * Cursors only support 0/180 degree rotation,
3378 * hence no need to account for rotation here.
3380 src_w
= pstate
->base
.src_w
;
3381 src_h
= pstate
->base
.src_h
;
3382 dst_w
= pstate
->base
.crtc_w
;
3383 dst_h
= pstate
->base
.crtc_h
;
3386 * Src coordinates are already rotated by 270 degrees for
3387 * the 90/270 degree plane rotation cases (to match the
3388 * GTT mapping), hence no need to account for rotation here.
3390 src_w
= drm_rect_width(&pstate
->base
.src
);
3391 src_h
= drm_rect_height(&pstate
->base
.src
);
3392 dst_w
= drm_rect_width(&pstate
->base
.dst
);
3393 dst_h
= drm_rect_height(&pstate
->base
.dst
);
3396 downscale_h
= max(src_h
/ dst_h
, (uint32_t)DRM_PLANE_HELPER_NO_SCALING
);
3397 downscale_w
= max(src_w
/ dst_w
, (uint32_t)DRM_PLANE_HELPER_NO_SCALING
);
3399 /* Provide result in 16.16 fixed point */
3400 return (uint64_t)downscale_w
* downscale_h
>> 16;
3404 skl_plane_relative_data_rate(const struct intel_crtc_state
*cstate
,
3405 const struct drm_plane_state
*pstate
,
3408 struct intel_plane
*plane
= to_intel_plane(pstate
->plane
);
3409 struct intel_plane_state
*intel_pstate
= to_intel_plane_state(pstate
);
3410 uint32_t down_scale_amount
, data_rate
;
3411 uint32_t width
= 0, height
= 0;
3412 struct drm_framebuffer
*fb
;
3415 if (!intel_pstate
->base
.visible
)
3419 format
= fb
->format
->format
;
3421 if (plane
->id
== PLANE_CURSOR
)
3423 if (y
&& format
!= DRM_FORMAT_NV12
)
3427 * Src coordinates are already rotated by 270 degrees for
3428 * the 90/270 degree plane rotation cases (to match the
3429 * GTT mapping), hence no need to account for rotation here.
3431 width
= drm_rect_width(&intel_pstate
->base
.src
) >> 16;
3432 height
= drm_rect_height(&intel_pstate
->base
.src
) >> 16;
3434 /* for planar format */
3435 if (format
== DRM_FORMAT_NV12
) {
3436 if (y
) /* y-plane data rate */
3437 data_rate
= width
* height
*
3439 else /* uv-plane data rate */
3440 data_rate
= (width
/ 2) * (height
/ 2) *
3443 /* for packed formats */
3444 data_rate
= width
* height
* fb
->format
->cpp
[0];
3447 down_scale_amount
= skl_plane_downscale_amount(cstate
, intel_pstate
);
3449 return (uint64_t)data_rate
* down_scale_amount
>> 16;
3453 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3454 * a 8192x4096@32bpp framebuffer:
3455 * 3 * 4096 * 8192 * 4 < 2^32
3458 skl_get_total_relative_data_rate(struct intel_crtc_state
*intel_cstate
,
3459 unsigned *plane_data_rate
,
3460 unsigned *plane_y_data_rate
)
3462 struct drm_crtc_state
*cstate
= &intel_cstate
->base
;
3463 struct drm_atomic_state
*state
= cstate
->state
;
3464 struct drm_plane
*plane
;
3465 const struct drm_plane_state
*pstate
;
3466 unsigned int total_data_rate
= 0;
3468 if (WARN_ON(!state
))
3471 /* Calculate and cache data rate for each plane */
3472 drm_atomic_crtc_state_for_each_plane_state(plane
, pstate
, cstate
) {
3473 enum plane_id plane_id
= to_intel_plane(plane
)->id
;
3477 rate
= skl_plane_relative_data_rate(intel_cstate
,
3479 plane_data_rate
[plane_id
] = rate
;
3481 total_data_rate
+= rate
;
3484 rate
= skl_plane_relative_data_rate(intel_cstate
,
3486 plane_y_data_rate
[plane_id
] = rate
;
3488 total_data_rate
+= rate
;
3491 return total_data_rate
;
3495 skl_ddb_min_alloc(const struct drm_plane_state
*pstate
,
3498 struct drm_framebuffer
*fb
= pstate
->fb
;
3499 struct intel_plane_state
*intel_pstate
= to_intel_plane_state(pstate
);
3500 uint32_t src_w
, src_h
;
3501 uint32_t min_scanlines
= 8;
3507 /* For packed formats, no y-plane, return 0 */
3508 if (y
&& fb
->format
->format
!= DRM_FORMAT_NV12
)
3511 /* For Non Y-tile return 8-blocks */
3512 if (fb
->modifier
!= I915_FORMAT_MOD_Y_TILED
&&
3513 fb
->modifier
!= I915_FORMAT_MOD_Yf_TILED
)
3517 * Src coordinates are already rotated by 270 degrees for
3518 * the 90/270 degree plane rotation cases (to match the
3519 * GTT mapping), hence no need to account for rotation here.
3521 src_w
= drm_rect_width(&intel_pstate
->base
.src
) >> 16;
3522 src_h
= drm_rect_height(&intel_pstate
->base
.src
) >> 16;
3524 /* Halve UV plane width and height for NV12 */
3525 if (fb
->format
->format
== DRM_FORMAT_NV12
&& !y
) {
3530 if (fb
->format
->format
== DRM_FORMAT_NV12
&& !y
)
3531 plane_bpp
= fb
->format
->cpp
[1];
3533 plane_bpp
= fb
->format
->cpp
[0];
3535 if (drm_rotation_90_or_270(pstate
->rotation
)) {
3536 switch (plane_bpp
) {
3550 WARN(1, "Unsupported pixel depth %u for rotation",
3556 return DIV_ROUND_UP((4 * src_w
* plane_bpp
), 512) * min_scanlines
/4 + 3;
3560 skl_ddb_calc_min(const struct intel_crtc_state
*cstate
, int num_active
,
3561 uint16_t *minimum
, uint16_t *y_minimum
)
3563 const struct drm_plane_state
*pstate
;
3564 struct drm_plane
*plane
;
3566 drm_atomic_crtc_state_for_each_plane_state(plane
, pstate
, &cstate
->base
) {
3567 enum plane_id plane_id
= to_intel_plane(plane
)->id
;
3569 if (plane_id
== PLANE_CURSOR
)
3572 if (!pstate
->visible
)
3575 minimum
[plane_id
] = skl_ddb_min_alloc(pstate
, 0);
3576 y_minimum
[plane_id
] = skl_ddb_min_alloc(pstate
, 1);
3579 minimum
[PLANE_CURSOR
] = skl_cursor_allocation(num_active
);
3583 skl_allocate_pipe_ddb(struct intel_crtc_state
*cstate
,
3584 struct skl_ddb_allocation
*ddb
/* out */)
3586 struct drm_atomic_state
*state
= cstate
->base
.state
;
3587 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
3588 struct drm_device
*dev
= crtc
->dev
;
3589 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3590 enum pipe pipe
= intel_crtc
->pipe
;
3591 struct skl_ddb_entry
*alloc
= &cstate
->wm
.skl
.ddb
;
3592 uint16_t alloc_size
, start
;
3593 uint16_t minimum
[I915_MAX_PLANES
] = {};
3594 uint16_t y_minimum
[I915_MAX_PLANES
] = {};
3595 unsigned int total_data_rate
;
3596 enum plane_id plane_id
;
3598 unsigned plane_data_rate
[I915_MAX_PLANES
] = {};
3599 unsigned plane_y_data_rate
[I915_MAX_PLANES
] = {};
3601 /* Clear the partitioning for disabled planes. */
3602 memset(ddb
->plane
[pipe
], 0, sizeof(ddb
->plane
[pipe
]));
3603 memset(ddb
->y_plane
[pipe
], 0, sizeof(ddb
->y_plane
[pipe
]));
3605 if (WARN_ON(!state
))
3608 if (!cstate
->base
.active
) {
3609 alloc
->start
= alloc
->end
= 0;
3613 skl_ddb_get_pipe_allocation_limits(dev
, cstate
, alloc
, &num_active
);
3614 alloc_size
= skl_ddb_entry_size(alloc
);
3615 if (alloc_size
== 0) {
3616 memset(ddb
->plane
[pipe
], 0, sizeof(ddb
->plane
[pipe
]));
3620 skl_ddb_calc_min(cstate
, num_active
, minimum
, y_minimum
);
3623 * 1. Allocate the mininum required blocks for each active plane
3624 * and allocate the cursor, it doesn't require extra allocation
3625 * proportional to the data rate.
3628 for_each_plane_id_on_crtc(intel_crtc
, plane_id
) {
3629 alloc_size
-= minimum
[plane_id
];
3630 alloc_size
-= y_minimum
[plane_id
];
3633 ddb
->plane
[pipe
][PLANE_CURSOR
].start
= alloc
->end
- minimum
[PLANE_CURSOR
];
3634 ddb
->plane
[pipe
][PLANE_CURSOR
].end
= alloc
->end
;
3637 * 2. Distribute the remaining space in proportion to the amount of
3638 * data each plane needs to fetch from memory.
3640 * FIXME: we may not allocate every single block here.
3642 total_data_rate
= skl_get_total_relative_data_rate(cstate
,
3645 if (total_data_rate
== 0)
3648 start
= alloc
->start
;
3649 for_each_plane_id_on_crtc(intel_crtc
, plane_id
) {
3650 unsigned int data_rate
, y_data_rate
;
3651 uint16_t plane_blocks
, y_plane_blocks
= 0;
3653 if (plane_id
== PLANE_CURSOR
)
3656 data_rate
= plane_data_rate
[plane_id
];
3659 * allocation for (packed formats) or (uv-plane part of planar format):
3660 * promote the expression to 64 bits to avoid overflowing, the
3661 * result is < available as data_rate / total_data_rate < 1
3663 plane_blocks
= minimum
[plane_id
];
3664 plane_blocks
+= div_u64((uint64_t)alloc_size
* data_rate
,
3667 /* Leave disabled planes at (0,0) */
3669 ddb
->plane
[pipe
][plane_id
].start
= start
;
3670 ddb
->plane
[pipe
][plane_id
].end
= start
+ plane_blocks
;
3673 start
+= plane_blocks
;
3676 * allocation for y_plane part of planar format:
3678 y_data_rate
= plane_y_data_rate
[plane_id
];
3680 y_plane_blocks
= y_minimum
[plane_id
];
3681 y_plane_blocks
+= div_u64((uint64_t)alloc_size
* y_data_rate
,
3685 ddb
->y_plane
[pipe
][plane_id
].start
= start
;
3686 ddb
->y_plane
[pipe
][plane_id
].end
= start
+ y_plane_blocks
;
3689 start
+= y_plane_blocks
;
3696 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3697 * for the read latency) and cpp should always be <= 8, so that
3698 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3699 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3701 static uint_fixed_16_16_t
skl_wm_method1(uint32_t pixel_rate
, uint8_t cpp
,
3704 uint32_t wm_intermediate_val
;
3705 uint_fixed_16_16_t ret
;
3708 return FP_16_16_MAX
;
3710 wm_intermediate_val
= latency
* pixel_rate
* cpp
;
3711 ret
= fixed_16_16_div_round_up_u64(wm_intermediate_val
, 1000 * 512);
3715 static uint_fixed_16_16_t
skl_wm_method2(uint32_t pixel_rate
,
3716 uint32_t pipe_htotal
,
3718 uint_fixed_16_16_t plane_blocks_per_line
)
3720 uint32_t wm_intermediate_val
;
3721 uint_fixed_16_16_t ret
;
3724 return FP_16_16_MAX
;
3726 wm_intermediate_val
= latency
* pixel_rate
;
3727 wm_intermediate_val
= DIV_ROUND_UP(wm_intermediate_val
,
3728 pipe_htotal
* 1000);
3729 ret
= mul_u32_fixed_16_16(wm_intermediate_val
, plane_blocks_per_line
);
3733 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state
*cstate
,
3734 struct intel_plane_state
*pstate
)
3736 uint64_t adjusted_pixel_rate
;
3737 uint64_t downscale_amount
;
3738 uint64_t pixel_rate
;
3740 /* Shouldn't reach here on disabled planes... */
3741 if (WARN_ON(!intel_wm_plane_visible(cstate
, pstate
)))
3745 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3746 * with additional adjustments for plane-specific scaling.
3748 adjusted_pixel_rate
= cstate
->pixel_rate
;
3749 downscale_amount
= skl_plane_downscale_amount(cstate
, pstate
);
3751 pixel_rate
= adjusted_pixel_rate
* downscale_amount
>> 16;
3752 WARN_ON(pixel_rate
!= clamp_t(uint32_t, pixel_rate
, 0, ~0));
3757 static int skl_compute_plane_wm(const struct drm_i915_private
*dev_priv
,
3758 struct intel_crtc_state
*cstate
,
3759 struct intel_plane_state
*intel_pstate
,
3760 uint16_t ddb_allocation
,
3762 uint16_t *out_blocks
, /* out */
3763 uint8_t *out_lines
, /* out */
3764 bool *enabled
/* out */)
3766 struct intel_plane
*plane
= to_intel_plane(intel_pstate
->base
.plane
);
3767 struct drm_plane_state
*pstate
= &intel_pstate
->base
;
3768 struct drm_framebuffer
*fb
= pstate
->fb
;
3769 uint32_t latency
= dev_priv
->wm
.skl_latency
[level
];
3770 uint_fixed_16_16_t method1
, method2
;
3771 uint_fixed_16_16_t plane_blocks_per_line
;
3772 uint_fixed_16_16_t selected_result
;
3773 uint32_t interm_pbpl
;
3774 uint32_t plane_bytes_per_line
;
3775 uint32_t res_blocks
, res_lines
;
3777 uint32_t width
= 0, height
= 0;
3778 uint32_t plane_pixel_rate
;
3779 uint_fixed_16_16_t y_tile_minimum
;
3780 uint32_t y_min_scanlines
;
3781 struct intel_atomic_state
*state
=
3782 to_intel_atomic_state(cstate
->base
.state
);
3783 bool apply_memory_bw_wa
= skl_needs_memory_bw_wa(state
);
3784 bool y_tiled
, x_tiled
;
3787 !intel_wm_plane_visible(cstate
, intel_pstate
)) {
3792 y_tiled
= fb
->modifier
== I915_FORMAT_MOD_Y_TILED
||
3793 fb
->modifier
== I915_FORMAT_MOD_Yf_TILED
;
3794 x_tiled
= fb
->modifier
== I915_FORMAT_MOD_X_TILED
;
3796 /* Display WA #1141: kbl. */
3797 if (IS_KABYLAKE(dev_priv
) && dev_priv
->ipc_enabled
)
3800 if (apply_memory_bw_wa
&& x_tiled
)
3803 if (plane
->id
== PLANE_CURSOR
) {
3804 width
= intel_pstate
->base
.crtc_w
;
3805 height
= intel_pstate
->base
.crtc_h
;
3808 * Src coordinates are already rotated by 270 degrees for
3809 * the 90/270 degree plane rotation cases (to match the
3810 * GTT mapping), hence no need to account for rotation here.
3812 width
= drm_rect_width(&intel_pstate
->base
.src
) >> 16;
3813 height
= drm_rect_height(&intel_pstate
->base
.src
) >> 16;
3816 cpp
= fb
->format
->cpp
[0];
3817 plane_pixel_rate
= skl_adjusted_plane_pixel_rate(cstate
, intel_pstate
);
3819 if (drm_rotation_90_or_270(pstate
->rotation
)) {
3820 int cpp
= (fb
->format
->format
== DRM_FORMAT_NV12
) ?
3821 fb
->format
->cpp
[1] :
3826 y_min_scanlines
= 16;
3829 y_min_scanlines
= 8;
3832 y_min_scanlines
= 4;
3839 y_min_scanlines
= 4;
3842 if (apply_memory_bw_wa
)
3843 y_min_scanlines
*= 2;
3845 plane_bytes_per_line
= width
* cpp
;
3847 interm_pbpl
= DIV_ROUND_UP(plane_bytes_per_line
*
3848 y_min_scanlines
, 512);
3849 plane_blocks_per_line
=
3850 fixed_16_16_div_round_up(interm_pbpl
, y_min_scanlines
);
3851 } else if (x_tiled
) {
3852 interm_pbpl
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
3853 plane_blocks_per_line
= u32_to_fixed_16_16(interm_pbpl
);
3855 interm_pbpl
= DIV_ROUND_UP(plane_bytes_per_line
, 512) + 1;
3856 plane_blocks_per_line
= u32_to_fixed_16_16(interm_pbpl
);
3859 method1
= skl_wm_method1(plane_pixel_rate
, cpp
, latency
);
3860 method2
= skl_wm_method2(plane_pixel_rate
,
3861 cstate
->base
.adjusted_mode
.crtc_htotal
,
3863 plane_blocks_per_line
);
3865 y_tile_minimum
= mul_u32_fixed_16_16(y_min_scanlines
,
3866 plane_blocks_per_line
);
3869 selected_result
= max_fixed_16_16(method2
, y_tile_minimum
);
3871 if ((cpp
* cstate
->base
.adjusted_mode
.crtc_htotal
/ 512 < 1) &&
3872 (plane_bytes_per_line
/ 512 < 1))
3873 selected_result
= method2
;
3874 else if ((ddb_allocation
/
3875 fixed_16_16_to_u32_round_up(plane_blocks_per_line
)) >= 1)
3876 selected_result
= min_fixed_16_16(method1
, method2
);
3878 selected_result
= method1
;
3881 res_blocks
= fixed_16_16_to_u32_round_up(selected_result
) + 1;
3882 res_lines
= DIV_ROUND_UP(selected_result
.val
,
3883 plane_blocks_per_line
.val
);
3885 if (level
>= 1 && level
<= 7) {
3887 res_blocks
+= fixed_16_16_to_u32_round_up(y_tile_minimum
);
3888 res_lines
+= y_min_scanlines
;
3894 if (res_blocks
>= ddb_allocation
|| res_lines
> 31) {
3898 * If there are no valid level 0 watermarks, then we can't
3899 * support this display configuration.
3904 struct drm_plane
*plane
= pstate
->plane
;
3906 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3907 DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n",
3908 plane
->base
.id
, plane
->name
,
3909 res_blocks
, ddb_allocation
, res_lines
);
3914 *out_blocks
= res_blocks
;
3915 *out_lines
= res_lines
;
3922 skl_compute_wm_level(const struct drm_i915_private
*dev_priv
,
3923 struct skl_ddb_allocation
*ddb
,
3924 struct intel_crtc_state
*cstate
,
3925 struct intel_plane
*intel_plane
,
3927 struct skl_wm_level
*result
)
3929 struct drm_atomic_state
*state
= cstate
->base
.state
;
3930 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
3931 struct drm_plane
*plane
= &intel_plane
->base
;
3932 struct intel_plane_state
*intel_pstate
= NULL
;
3933 uint16_t ddb_blocks
;
3934 enum pipe pipe
= intel_crtc
->pipe
;
3939 intel_atomic_get_existing_plane_state(state
,
3943 * Note: If we start supporting multiple pending atomic commits against
3944 * the same planes/CRTC's in the future, plane->state will no longer be
3945 * the correct pre-state to use for the calculations here and we'll
3946 * need to change where we get the 'unchanged' plane data from.
3948 * For now this is fine because we only allow one queued commit against
3949 * a CRTC. Even if the plane isn't modified by this transaction and we
3950 * don't have a plane lock, we still have the CRTC's lock, so we know
3951 * that no other transactions are racing with us to update it.
3954 intel_pstate
= to_intel_plane_state(plane
->state
);
3956 WARN_ON(!intel_pstate
->base
.fb
);
3958 ddb_blocks
= skl_ddb_entry_size(&ddb
->plane
[pipe
][intel_plane
->id
]);
3960 ret
= skl_compute_plane_wm(dev_priv
,
3965 &result
->plane_res_b
,
3966 &result
->plane_res_l
,
3975 skl_compute_linetime_wm(struct intel_crtc_state
*cstate
)
3977 struct drm_atomic_state
*state
= cstate
->base
.state
;
3978 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
3979 uint32_t pixel_rate
;
3980 uint32_t linetime_wm
;
3982 if (!cstate
->base
.active
)
3985 pixel_rate
= cstate
->pixel_rate
;
3987 if (WARN_ON(pixel_rate
== 0))
3990 linetime_wm
= DIV_ROUND_UP(8 * cstate
->base
.adjusted_mode
.crtc_htotal
*
3993 /* Display WA #1135: bxt. */
3994 if (IS_BROXTON(dev_priv
) && dev_priv
->ipc_enabled
)
3995 linetime_wm
= DIV_ROUND_UP(linetime_wm
, 2);
4000 static void skl_compute_transition_wm(struct intel_crtc_state
*cstate
,
4001 struct skl_wm_level
*trans_wm
/* out */)
4003 if (!cstate
->base
.active
)
4006 /* Until we know more, just disable transition WMs */
4007 trans_wm
->plane_en
= false;
4010 static int skl_build_pipe_wm(struct intel_crtc_state
*cstate
,
4011 struct skl_ddb_allocation
*ddb
,
4012 struct skl_pipe_wm
*pipe_wm
)
4014 struct drm_device
*dev
= cstate
->base
.crtc
->dev
;
4015 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
4016 struct intel_plane
*intel_plane
;
4017 struct skl_plane_wm
*wm
;
4018 int level
, max_level
= ilk_wm_max_level(dev_priv
);
4022 * We'll only calculate watermarks for planes that are actually
4023 * enabled, so make sure all other planes are set as disabled.
4025 memset(pipe_wm
->planes
, 0, sizeof(pipe_wm
->planes
));
4027 for_each_intel_plane_mask(&dev_priv
->drm
,
4029 cstate
->base
.plane_mask
) {
4030 wm
= &pipe_wm
->planes
[intel_plane
->id
];
4032 for (level
= 0; level
<= max_level
; level
++) {
4033 ret
= skl_compute_wm_level(dev_priv
, ddb
, cstate
,
4039 skl_compute_transition_wm(cstate
, &wm
->trans_wm
);
4041 pipe_wm
->linetime
= skl_compute_linetime_wm(cstate
);
4046 static void skl_ddb_entry_write(struct drm_i915_private
*dev_priv
,
4048 const struct skl_ddb_entry
*entry
)
4051 I915_WRITE(reg
, (entry
->end
- 1) << 16 | entry
->start
);
4056 static void skl_write_wm_level(struct drm_i915_private
*dev_priv
,
4058 const struct skl_wm_level
*level
)
4062 if (level
->plane_en
) {
4064 val
|= level
->plane_res_b
;
4065 val
|= level
->plane_res_l
<< PLANE_WM_LINES_SHIFT
;
4068 I915_WRITE(reg
, val
);
4071 static void skl_write_plane_wm(struct intel_crtc
*intel_crtc
,
4072 const struct skl_plane_wm
*wm
,
4073 const struct skl_ddb_allocation
*ddb
,
4074 enum plane_id plane_id
)
4076 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4077 struct drm_device
*dev
= crtc
->dev
;
4078 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4079 int level
, max_level
= ilk_wm_max_level(dev_priv
);
4080 enum pipe pipe
= intel_crtc
->pipe
;
4082 for (level
= 0; level
<= max_level
; level
++) {
4083 skl_write_wm_level(dev_priv
, PLANE_WM(pipe
, plane_id
, level
),
4086 skl_write_wm_level(dev_priv
, PLANE_WM_TRANS(pipe
, plane_id
),
4089 skl_ddb_entry_write(dev_priv
, PLANE_BUF_CFG(pipe
, plane_id
),
4090 &ddb
->plane
[pipe
][plane_id
]);
4091 skl_ddb_entry_write(dev_priv
, PLANE_NV12_BUF_CFG(pipe
, plane_id
),
4092 &ddb
->y_plane
[pipe
][plane_id
]);
4095 static void skl_write_cursor_wm(struct intel_crtc
*intel_crtc
,
4096 const struct skl_plane_wm
*wm
,
4097 const struct skl_ddb_allocation
*ddb
)
4099 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4100 struct drm_device
*dev
= crtc
->dev
;
4101 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4102 int level
, max_level
= ilk_wm_max_level(dev_priv
);
4103 enum pipe pipe
= intel_crtc
->pipe
;
4105 for (level
= 0; level
<= max_level
; level
++) {
4106 skl_write_wm_level(dev_priv
, CUR_WM(pipe
, level
),
4109 skl_write_wm_level(dev_priv
, CUR_WM_TRANS(pipe
), &wm
->trans_wm
);
4111 skl_ddb_entry_write(dev_priv
, CUR_BUF_CFG(pipe
),
4112 &ddb
->plane
[pipe
][PLANE_CURSOR
]);
4115 bool skl_wm_level_equals(const struct skl_wm_level
*l1
,
4116 const struct skl_wm_level
*l2
)
4118 if (l1
->plane_en
!= l2
->plane_en
)
4121 /* If both planes aren't enabled, the rest shouldn't matter */
4125 return (l1
->plane_res_l
== l2
->plane_res_l
&&
4126 l1
->plane_res_b
== l2
->plane_res_b
);
4129 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry
*a
,
4130 const struct skl_ddb_entry
*b
)
4132 return a
->start
< b
->end
&& b
->start
< a
->end
;
4135 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry
**entries
,
4136 const struct skl_ddb_entry
*ddb
,
4141 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
4142 if (i
!= ignore
&& entries
[i
] &&
4143 skl_ddb_entries_overlap(ddb
, entries
[i
]))
4149 static int skl_update_pipe_wm(struct drm_crtc_state
*cstate
,
4150 const struct skl_pipe_wm
*old_pipe_wm
,
4151 struct skl_pipe_wm
*pipe_wm
, /* out */
4152 struct skl_ddb_allocation
*ddb
, /* out */
4153 bool *changed
/* out */)
4155 struct intel_crtc_state
*intel_cstate
= to_intel_crtc_state(cstate
);
4158 ret
= skl_build_pipe_wm(intel_cstate
, ddb
, pipe_wm
);
4162 if (!memcmp(old_pipe_wm
, pipe_wm
, sizeof(*pipe_wm
)))
4171 pipes_modified(struct drm_atomic_state
*state
)
4173 struct drm_crtc
*crtc
;
4174 struct drm_crtc_state
*cstate
;
4175 uint32_t i
, ret
= 0;
4177 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
)
4178 ret
|= drm_crtc_mask(crtc
);
4184 skl_ddb_add_affected_planes(struct intel_crtc_state
*cstate
)
4186 struct drm_atomic_state
*state
= cstate
->base
.state
;
4187 struct drm_device
*dev
= state
->dev
;
4188 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
4189 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4190 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4191 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
4192 struct skl_ddb_allocation
*new_ddb
= &intel_state
->wm_results
.ddb
;
4193 struct skl_ddb_allocation
*cur_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
4194 struct drm_plane_state
*plane_state
;
4195 struct drm_plane
*plane
;
4196 enum pipe pipe
= intel_crtc
->pipe
;
4198 WARN_ON(!drm_atomic_get_existing_crtc_state(state
, crtc
));
4200 drm_for_each_plane_mask(plane
, dev
, cstate
->base
.plane_mask
) {
4201 enum plane_id plane_id
= to_intel_plane(plane
)->id
;
4203 if (skl_ddb_entry_equal(&cur_ddb
->plane
[pipe
][plane_id
],
4204 &new_ddb
->plane
[pipe
][plane_id
]) &&
4205 skl_ddb_entry_equal(&cur_ddb
->y_plane
[pipe
][plane_id
],
4206 &new_ddb
->y_plane
[pipe
][plane_id
]))
4209 plane_state
= drm_atomic_get_plane_state(state
, plane
);
4210 if (IS_ERR(plane_state
))
4211 return PTR_ERR(plane_state
);
4218 skl_compute_ddb(struct drm_atomic_state
*state
)
4220 struct drm_device
*dev
= state
->dev
;
4221 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4222 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
4223 struct intel_crtc
*intel_crtc
;
4224 struct skl_ddb_allocation
*ddb
= &intel_state
->wm_results
.ddb
;
4225 uint32_t realloc_pipes
= pipes_modified(state
);
4229 * If this is our first atomic update following hardware readout,
4230 * we can't trust the DDB that the BIOS programmed for us. Let's
4231 * pretend that all pipes switched active status so that we'll
4232 * ensure a full DDB recompute.
4234 if (dev_priv
->wm
.distrust_bios_wm
) {
4235 ret
= drm_modeset_lock(&dev
->mode_config
.connection_mutex
,
4236 state
->acquire_ctx
);
4240 intel_state
->active_pipe_changes
= ~0;
4243 * We usually only initialize intel_state->active_crtcs if we
4244 * we're doing a modeset; make sure this field is always
4245 * initialized during the sanitization process that happens
4246 * on the first commit too.
4248 if (!intel_state
->modeset
)
4249 intel_state
->active_crtcs
= dev_priv
->active_crtcs
;
4253 * If the modeset changes which CRTC's are active, we need to
4254 * recompute the DDB allocation for *all* active pipes, even
4255 * those that weren't otherwise being modified in any way by this
4256 * atomic commit. Due to the shrinking of the per-pipe allocations
4257 * when new active CRTC's are added, it's possible for a pipe that
4258 * we were already using and aren't changing at all here to suddenly
4259 * become invalid if its DDB needs exceeds its new allocation.
4261 * Note that if we wind up doing a full DDB recompute, we can't let
4262 * any other display updates race with this transaction, so we need
4263 * to grab the lock on *all* CRTC's.
4265 if (intel_state
->active_pipe_changes
) {
4267 intel_state
->wm_results
.dirty_pipes
= ~0;
4271 * We're not recomputing for the pipes not included in the commit, so
4272 * make sure we start with the current state.
4274 memcpy(ddb
, &dev_priv
->wm
.skl_hw
.ddb
, sizeof(*ddb
));
4276 for_each_intel_crtc_mask(dev
, intel_crtc
, realloc_pipes
) {
4277 struct intel_crtc_state
*cstate
;
4279 cstate
= intel_atomic_get_crtc_state(state
, intel_crtc
);
4281 return PTR_ERR(cstate
);
4283 ret
= skl_allocate_pipe_ddb(cstate
, ddb
);
4287 ret
= skl_ddb_add_affected_planes(cstate
);
4296 skl_copy_wm_for_pipe(struct skl_wm_values
*dst
,
4297 struct skl_wm_values
*src
,
4300 memcpy(dst
->ddb
.y_plane
[pipe
], src
->ddb
.y_plane
[pipe
],
4301 sizeof(dst
->ddb
.y_plane
[pipe
]));
4302 memcpy(dst
->ddb
.plane
[pipe
], src
->ddb
.plane
[pipe
],
4303 sizeof(dst
->ddb
.plane
[pipe
]));
4307 skl_print_wm_changes(const struct drm_atomic_state
*state
)
4309 const struct drm_device
*dev
= state
->dev
;
4310 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
4311 const struct intel_atomic_state
*intel_state
=
4312 to_intel_atomic_state(state
);
4313 const struct drm_crtc
*crtc
;
4314 const struct drm_crtc_state
*cstate
;
4315 const struct intel_plane
*intel_plane
;
4316 const struct skl_ddb_allocation
*old_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
4317 const struct skl_ddb_allocation
*new_ddb
= &intel_state
->wm_results
.ddb
;
4320 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
) {
4321 const struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4322 enum pipe pipe
= intel_crtc
->pipe
;
4324 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
4325 enum plane_id plane_id
= intel_plane
->id
;
4326 const struct skl_ddb_entry
*old
, *new;
4328 old
= &old_ddb
->plane
[pipe
][plane_id
];
4329 new = &new_ddb
->plane
[pipe
][plane_id
];
4331 if (skl_ddb_entry_equal(old
, new))
4334 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4335 intel_plane
->base
.base
.id
,
4336 intel_plane
->base
.name
,
4337 old
->start
, old
->end
,
4338 new->start
, new->end
);
4344 skl_compute_wm(struct drm_atomic_state
*state
)
4346 struct drm_crtc
*crtc
;
4347 struct drm_crtc_state
*cstate
;
4348 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
4349 struct skl_wm_values
*results
= &intel_state
->wm_results
;
4350 struct drm_device
*dev
= state
->dev
;
4351 struct skl_pipe_wm
*pipe_wm
;
4352 bool changed
= false;
4356 * When we distrust bios wm we always need to recompute to set the
4357 * expected DDB allocations for each CRTC.
4359 if (to_i915(dev
)->wm
.distrust_bios_wm
)
4363 * If this transaction isn't actually touching any CRTC's, don't
4364 * bother with watermark calculation. Note that if we pass this
4365 * test, we're guaranteed to hold at least one CRTC state mutex,
4366 * which means we can safely use values like dev_priv->active_crtcs
4367 * since any racing commits that want to update them would need to
4368 * hold _all_ CRTC state mutexes.
4370 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
)
4376 /* Clear all dirty flags */
4377 results
->dirty_pipes
= 0;
4379 ret
= skl_compute_ddb(state
);
4384 * Calculate WM's for all pipes that are part of this transaction.
4385 * Note that the DDB allocation above may have added more CRTC's that
4386 * weren't otherwise being modified (and set bits in dirty_pipes) if
4387 * pipe allocations had to change.
4389 * FIXME: Now that we're doing this in the atomic check phase, we
4390 * should allow skl_update_pipe_wm() to return failure in cases where
4391 * no suitable watermark values can be found.
4393 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
) {
4394 struct intel_crtc_state
*intel_cstate
=
4395 to_intel_crtc_state(cstate
);
4396 const struct skl_pipe_wm
*old_pipe_wm
=
4397 &to_intel_crtc_state(crtc
->state
)->wm
.skl
.optimal
;
4399 pipe_wm
= &intel_cstate
->wm
.skl
.optimal
;
4400 ret
= skl_update_pipe_wm(cstate
, old_pipe_wm
, pipe_wm
,
4401 &results
->ddb
, &changed
);
4406 results
->dirty_pipes
|= drm_crtc_mask(crtc
);
4408 if ((results
->dirty_pipes
& drm_crtc_mask(crtc
)) == 0)
4409 /* This pipe's WM's did not change */
4412 intel_cstate
->update_wm_pre
= true;
4415 skl_print_wm_changes(state
);
4420 static void skl_atomic_update_crtc_wm(struct intel_atomic_state
*state
,
4421 struct intel_crtc_state
*cstate
)
4423 struct intel_crtc
*crtc
= to_intel_crtc(cstate
->base
.crtc
);
4424 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
4425 struct skl_pipe_wm
*pipe_wm
= &cstate
->wm
.skl
.optimal
;
4426 const struct skl_ddb_allocation
*ddb
= &state
->wm_results
.ddb
;
4427 enum pipe pipe
= crtc
->pipe
;
4428 enum plane_id plane_id
;
4430 if (!(state
->wm_results
.dirty_pipes
& drm_crtc_mask(&crtc
->base
)))
4433 I915_WRITE(PIPE_WM_LINETIME(pipe
), pipe_wm
->linetime
);
4435 for_each_plane_id_on_crtc(crtc
, plane_id
) {
4436 if (plane_id
!= PLANE_CURSOR
)
4437 skl_write_plane_wm(crtc
, &pipe_wm
->planes
[plane_id
],
4440 skl_write_cursor_wm(crtc
, &pipe_wm
->planes
[plane_id
],
4445 static void skl_initial_wm(struct intel_atomic_state
*state
,
4446 struct intel_crtc_state
*cstate
)
4448 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
4449 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4450 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4451 struct skl_wm_values
*results
= &state
->wm_results
;
4452 struct skl_wm_values
*hw_vals
= &dev_priv
->wm
.skl_hw
;
4453 enum pipe pipe
= intel_crtc
->pipe
;
4455 if ((results
->dirty_pipes
& drm_crtc_mask(&intel_crtc
->base
)) == 0)
4458 mutex_lock(&dev_priv
->wm
.wm_mutex
);
4460 if (cstate
->base
.active_changed
)
4461 skl_atomic_update_crtc_wm(state
, cstate
);
4463 skl_copy_wm_for_pipe(hw_vals
, results
, pipe
);
4465 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
4468 static void ilk_compute_wm_config(struct drm_device
*dev
,
4469 struct intel_wm_config
*config
)
4471 struct intel_crtc
*crtc
;
4473 /* Compute the currently _active_ config */
4474 for_each_intel_crtc(dev
, crtc
) {
4475 const struct intel_pipe_wm
*wm
= &crtc
->wm
.active
.ilk
;
4477 if (!wm
->pipe_enabled
)
4480 config
->sprites_enabled
|= wm
->sprites_enabled
;
4481 config
->sprites_scaled
|= wm
->sprites_scaled
;
4482 config
->num_pipes_active
++;
4486 static void ilk_program_watermarks(struct drm_i915_private
*dev_priv
)
4488 struct drm_device
*dev
= &dev_priv
->drm
;
4489 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
4490 struct ilk_wm_maximums max
;
4491 struct intel_wm_config config
= {};
4492 struct ilk_wm_values results
= {};
4493 enum intel_ddb_partitioning partitioning
;
4495 ilk_compute_wm_config(dev
, &config
);
4497 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_1_2
, &max
);
4498 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_1_2
);
4500 /* 5/6 split only in single pipe config on IVB+ */
4501 if (INTEL_GEN(dev_priv
) >= 7 &&
4502 config
.num_pipes_active
== 1 && config
.sprites_enabled
) {
4503 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_5_6
, &max
);
4504 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_5_6
);
4506 best_lp_wm
= ilk_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
4508 best_lp_wm
= &lp_wm_1_2
;
4511 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
4512 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
4514 ilk_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
4516 ilk_write_wm_values(dev_priv
, &results
);
4519 static void ilk_initial_watermarks(struct intel_atomic_state
*state
,
4520 struct intel_crtc_state
*cstate
)
4522 struct drm_i915_private
*dev_priv
= to_i915(cstate
->base
.crtc
->dev
);
4523 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
4525 mutex_lock(&dev_priv
->wm
.wm_mutex
);
4526 intel_crtc
->wm
.active
.ilk
= cstate
->wm
.ilk
.intermediate
;
4527 ilk_program_watermarks(dev_priv
);
4528 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
4531 static void ilk_optimize_watermarks(struct intel_atomic_state
*state
,
4532 struct intel_crtc_state
*cstate
)
4534 struct drm_i915_private
*dev_priv
= to_i915(cstate
->base
.crtc
->dev
);
4535 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
4537 mutex_lock(&dev_priv
->wm
.wm_mutex
);
4538 if (cstate
->wm
.need_postvbl_update
) {
4539 intel_crtc
->wm
.active
.ilk
= cstate
->wm
.ilk
.optimal
;
4540 ilk_program_watermarks(dev_priv
);
4542 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
4545 static inline void skl_wm_level_from_reg_val(uint32_t val
,
4546 struct skl_wm_level
*level
)
4548 level
->plane_en
= val
& PLANE_WM_EN
;
4549 level
->plane_res_b
= val
& PLANE_WM_BLOCKS_MASK
;
4550 level
->plane_res_l
= (val
>> PLANE_WM_LINES_SHIFT
) &
4551 PLANE_WM_LINES_MASK
;
4554 void skl_pipe_wm_get_hw_state(struct drm_crtc
*crtc
,
4555 struct skl_pipe_wm
*out
)
4557 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
4558 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4559 enum pipe pipe
= intel_crtc
->pipe
;
4560 int level
, max_level
;
4561 enum plane_id plane_id
;
4564 max_level
= ilk_wm_max_level(dev_priv
);
4566 for_each_plane_id_on_crtc(intel_crtc
, plane_id
) {
4567 struct skl_plane_wm
*wm
= &out
->planes
[plane_id
];
4569 for (level
= 0; level
<= max_level
; level
++) {
4570 if (plane_id
!= PLANE_CURSOR
)
4571 val
= I915_READ(PLANE_WM(pipe
, plane_id
, level
));
4573 val
= I915_READ(CUR_WM(pipe
, level
));
4575 skl_wm_level_from_reg_val(val
, &wm
->wm
[level
]);
4578 if (plane_id
!= PLANE_CURSOR
)
4579 val
= I915_READ(PLANE_WM_TRANS(pipe
, plane_id
));
4581 val
= I915_READ(CUR_WM_TRANS(pipe
));
4583 skl_wm_level_from_reg_val(val
, &wm
->trans_wm
);
4586 if (!intel_crtc
->active
)
4589 out
->linetime
= I915_READ(PIPE_WM_LINETIME(pipe
));
4592 void skl_wm_get_hw_state(struct drm_device
*dev
)
4594 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4595 struct skl_wm_values
*hw
= &dev_priv
->wm
.skl_hw
;
4596 struct skl_ddb_allocation
*ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
4597 struct drm_crtc
*crtc
;
4598 struct intel_crtc
*intel_crtc
;
4599 struct intel_crtc_state
*cstate
;
4601 skl_ddb_get_hw_state(dev_priv
, ddb
);
4602 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4603 intel_crtc
= to_intel_crtc(crtc
);
4604 cstate
= to_intel_crtc_state(crtc
->state
);
4606 skl_pipe_wm_get_hw_state(crtc
, &cstate
->wm
.skl
.optimal
);
4608 if (intel_crtc
->active
)
4609 hw
->dirty_pipes
|= drm_crtc_mask(crtc
);
4612 if (dev_priv
->active_crtcs
) {
4613 /* Fully recompute DDB on first atomic commit */
4614 dev_priv
->wm
.distrust_bios_wm
= true;
4616 /* Easy/common case; just sanitize DDB now if everything off */
4617 memset(ddb
, 0, sizeof(*ddb
));
4621 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
4623 struct drm_device
*dev
= crtc
->dev
;
4624 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4625 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
4626 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4627 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
4628 struct intel_pipe_wm
*active
= &cstate
->wm
.ilk
.optimal
;
4629 enum pipe pipe
= intel_crtc
->pipe
;
4630 static const i915_reg_t wm0_pipe_reg
[] = {
4631 [PIPE_A
] = WM0_PIPEA_ILK
,
4632 [PIPE_B
] = WM0_PIPEB_ILK
,
4633 [PIPE_C
] = WM0_PIPEC_IVB
,
4636 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
4637 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
4638 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
4640 memset(active
, 0, sizeof(*active
));
4642 active
->pipe_enabled
= intel_crtc
->active
;
4644 if (active
->pipe_enabled
) {
4645 u32 tmp
= hw
->wm_pipe
[pipe
];
4648 * For active pipes LP0 watermark is marked as
4649 * enabled, and LP1+ watermaks as disabled since
4650 * we can't really reverse compute them in case
4651 * multiple pipes are active.
4653 active
->wm
[0].enable
= true;
4654 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
4655 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
4656 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
4657 active
->linetime
= hw
->wm_linetime
[pipe
];
4659 int level
, max_level
= ilk_wm_max_level(dev_priv
);
4662 * For inactive pipes, all watermark levels
4663 * should be marked as enabled but zeroed,
4664 * which is what we'd compute them to.
4666 for (level
= 0; level
<= max_level
; level
++)
4667 active
->wm
[level
].enable
= true;
4670 intel_crtc
->wm
.active
.ilk
= *active
;
4673 #define _FW_WM(value, plane) \
4674 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4675 #define _FW_WM_VLV(value, plane) \
4676 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4678 static void vlv_read_wm_values(struct drm_i915_private
*dev_priv
,
4679 struct vlv_wm_values
*wm
)
4684 for_each_pipe(dev_priv
, pipe
) {
4685 tmp
= I915_READ(VLV_DDL(pipe
));
4687 wm
->ddl
[pipe
].plane
[PLANE_PRIMARY
] =
4688 (tmp
>> DDL_PLANE_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4689 wm
->ddl
[pipe
].plane
[PLANE_CURSOR
] =
4690 (tmp
>> DDL_CURSOR_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4691 wm
->ddl
[pipe
].plane
[PLANE_SPRITE0
] =
4692 (tmp
>> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4693 wm
->ddl
[pipe
].plane
[PLANE_SPRITE1
] =
4694 (tmp
>> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4697 tmp
= I915_READ(DSPFW1
);
4698 wm
->sr
.plane
= _FW_WM(tmp
, SR
);
4699 wm
->pipe
[PIPE_B
].plane
[PLANE_CURSOR
] = _FW_WM(tmp
, CURSORB
);
4700 wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] = _FW_WM_VLV(tmp
, PLANEB
);
4701 wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] = _FW_WM_VLV(tmp
, PLANEA
);
4703 tmp
= I915_READ(DSPFW2
);
4704 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] = _FW_WM_VLV(tmp
, SPRITEB
);
4705 wm
->pipe
[PIPE_A
].plane
[PLANE_CURSOR
] = _FW_WM(tmp
, CURSORA
);
4706 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] = _FW_WM_VLV(tmp
, SPRITEA
);
4708 tmp
= I915_READ(DSPFW3
);
4709 wm
->sr
.cursor
= _FW_WM(tmp
, CURSOR_SR
);
4711 if (IS_CHERRYVIEW(dev_priv
)) {
4712 tmp
= I915_READ(DSPFW7_CHV
);
4713 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] = _FW_WM_VLV(tmp
, SPRITED
);
4714 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] = _FW_WM_VLV(tmp
, SPRITEC
);
4716 tmp
= I915_READ(DSPFW8_CHV
);
4717 wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE1
] = _FW_WM_VLV(tmp
, SPRITEF
);
4718 wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE0
] = _FW_WM_VLV(tmp
, SPRITEE
);
4720 tmp
= I915_READ(DSPFW9_CHV
);
4721 wm
->pipe
[PIPE_C
].plane
[PLANE_PRIMARY
] = _FW_WM_VLV(tmp
, PLANEC
);
4722 wm
->pipe
[PIPE_C
].plane
[PLANE_CURSOR
] = _FW_WM(tmp
, CURSORC
);
4724 tmp
= I915_READ(DSPHOWM
);
4725 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
4726 wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITEF_HI
) << 8;
4727 wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEE_HI
) << 8;
4728 wm
->pipe
[PIPE_C
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEC_HI
) << 8;
4729 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
4730 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
4731 wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEB_HI
) << 8;
4732 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
4733 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
4734 wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEA_HI
) << 8;
4736 tmp
= I915_READ(DSPFW7
);
4737 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] = _FW_WM_VLV(tmp
, SPRITED
);
4738 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] = _FW_WM_VLV(tmp
, SPRITEC
);
4740 tmp
= I915_READ(DSPHOWM
);
4741 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
4742 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
4743 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
4744 wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEB_HI
) << 8;
4745 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
4746 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
4747 wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEA_HI
) << 8;
4754 void vlv_wm_get_hw_state(struct drm_device
*dev
)
4756 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4757 struct vlv_wm_values
*wm
= &dev_priv
->wm
.vlv
;
4758 struct intel_crtc
*crtc
;
4761 vlv_read_wm_values(dev_priv
, wm
);
4763 wm
->cxsr
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
4764 wm
->level
= VLV_WM_LEVEL_PM2
;
4766 if (IS_CHERRYVIEW(dev_priv
)) {
4767 mutex_lock(&dev_priv
->rps
.hw_lock
);
4769 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4770 if (val
& DSP_MAXFIFO_PM5_ENABLE
)
4771 wm
->level
= VLV_WM_LEVEL_PM5
;
4774 * If DDR DVFS is disabled in the BIOS, Punit
4775 * will never ack the request. So if that happens
4776 * assume we don't have to enable/disable DDR DVFS
4777 * dynamically. To test that just set the REQ_ACK
4778 * bit to poke the Punit, but don't change the
4779 * HIGH/LOW bits so that we don't actually change
4780 * the current state.
4782 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
4783 val
|= FORCE_DDR_FREQ_REQ_ACK
;
4784 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
4786 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
4787 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3)) {
4788 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4789 "assuming DDR DVFS is disabled\n");
4790 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM5
;
4792 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
4793 if ((val
& FORCE_DDR_HIGH_FREQ
) == 0)
4794 wm
->level
= VLV_WM_LEVEL_DDR_DVFS
;
4797 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4800 for_each_intel_crtc(dev
, crtc
) {
4801 struct intel_crtc_state
*crtc_state
=
4802 to_intel_crtc_state(crtc
->base
.state
);
4803 struct vlv_wm_state
*active
= &crtc
->wm
.active
.vlv
;
4804 const struct vlv_fifo_state
*fifo_state
=
4805 &crtc_state
->wm
.vlv
.fifo_state
;
4806 enum pipe pipe
= crtc
->pipe
;
4807 enum plane_id plane_id
;
4810 vlv_get_fifo_size(crtc_state
);
4812 active
->num_levels
= wm
->level
+ 1;
4813 active
->cxsr
= wm
->cxsr
;
4815 for (level
= 0; level
< active
->num_levels
; level
++) {
4816 struct vlv_pipe_wm
*raw
=
4817 &crtc_state
->wm
.vlv
.raw
[level
];
4819 active
->sr
[level
].plane
= wm
->sr
.plane
;
4820 active
->sr
[level
].cursor
= wm
->sr
.cursor
;
4822 for_each_plane_id_on_crtc(crtc
, plane_id
) {
4823 active
->wm
[level
].plane
[plane_id
] =
4824 wm
->pipe
[pipe
].plane
[plane_id
];
4826 raw
->plane
[plane_id
] =
4827 vlv_invert_wm_value(active
->wm
[level
].plane
[plane_id
],
4828 fifo_state
->plane
[plane_id
]);
4832 for_each_plane_id_on_crtc(crtc
, plane_id
)
4833 vlv_raw_plane_wm_set(crtc_state
, level
,
4834 plane_id
, USHRT_MAX
);
4835 vlv_invalidate_wms(crtc
, active
, level
);
4837 crtc_state
->wm
.vlv
.optimal
= *active
;
4838 crtc_state
->wm
.vlv
.intermediate
= *active
;
4840 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4842 wm
->pipe
[pipe
].plane
[PLANE_PRIMARY
],
4843 wm
->pipe
[pipe
].plane
[PLANE_CURSOR
],
4844 wm
->pipe
[pipe
].plane
[PLANE_SPRITE0
],
4845 wm
->pipe
[pipe
].plane
[PLANE_SPRITE1
]);
4848 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4849 wm
->sr
.plane
, wm
->sr
.cursor
, wm
->level
, wm
->cxsr
);
4852 void vlv_wm_sanitize(struct drm_i915_private
*dev_priv
)
4854 struct intel_plane
*plane
;
4855 struct intel_crtc
*crtc
;
4857 mutex_lock(&dev_priv
->wm
.wm_mutex
);
4859 for_each_intel_plane(&dev_priv
->drm
, plane
) {
4860 struct intel_crtc
*crtc
=
4861 intel_get_crtc_for_pipe(dev_priv
, plane
->pipe
);
4862 struct intel_crtc_state
*crtc_state
=
4863 to_intel_crtc_state(crtc
->base
.state
);
4864 struct intel_plane_state
*plane_state
=
4865 to_intel_plane_state(plane
->base
.state
);
4866 struct vlv_wm_state
*wm_state
= &crtc_state
->wm
.vlv
.optimal
;
4867 const struct vlv_fifo_state
*fifo_state
=
4868 &crtc_state
->wm
.vlv
.fifo_state
;
4869 enum plane_id plane_id
= plane
->id
;
4872 if (plane_state
->base
.visible
)
4875 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
4876 struct vlv_pipe_wm
*raw
=
4877 &crtc_state
->wm
.vlv
.raw
[level
];
4879 raw
->plane
[plane_id
] = 0;
4881 wm_state
->wm
[level
].plane
[plane_id
] =
4882 vlv_invert_wm_value(raw
->plane
[plane_id
],
4883 fifo_state
->plane
[plane_id
]);
4887 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
4888 struct intel_crtc_state
*crtc_state
=
4889 to_intel_crtc_state(crtc
->base
.state
);
4891 crtc_state
->wm
.vlv
.intermediate
=
4892 crtc_state
->wm
.vlv
.optimal
;
4893 crtc
->wm
.active
.vlv
= crtc_state
->wm
.vlv
.optimal
;
4896 vlv_program_watermarks(dev_priv
);
4898 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
4901 void ilk_wm_get_hw_state(struct drm_device
*dev
)
4903 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4904 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
4905 struct drm_crtc
*crtc
;
4907 for_each_crtc(dev
, crtc
)
4908 ilk_pipe_wm_get_hw_state(crtc
);
4910 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
4911 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
4912 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
4914 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
4915 if (INTEL_GEN(dev_priv
) >= 7) {
4916 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
4917 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
4920 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
4921 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
4922 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
4923 else if (IS_IVYBRIDGE(dev_priv
))
4924 hw
->partitioning
= (I915_READ(DISP_ARB_CTL2
) & DISP_DATA_PARTITION_5_6
) ?
4925 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
4928 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
4932 * intel_update_watermarks - update FIFO watermark values based on current modes
4934 * Calculate watermark values for the various WM regs based on current mode
4935 * and plane configuration.
4937 * There are several cases to deal with here:
4938 * - normal (i.e. non-self-refresh)
4939 * - self-refresh (SR) mode
4940 * - lines are large relative to FIFO size (buffer can hold up to 2)
4941 * - lines are small relative to FIFO size (buffer can hold more than 2
4942 * lines), so need to account for TLB latency
4944 * The normal calculation is:
4945 * watermark = dotclock * bytes per pixel * latency
4946 * where latency is platform & configuration dependent (we assume pessimal
4949 * The SR calculation is:
4950 * watermark = (trunc(latency/line time)+1) * surface width *
4953 * line time = htotal / dotclock
4954 * surface width = hdisplay for normal plane and 64 for cursor
4955 * and latency is assumed to be high, as above.
4957 * The final value programmed to the register should always be rounded up,
4958 * and include an extra 2 entries to account for clock crossings.
4960 * We don't use the sprite, so we can ignore that. And on Crestline we have
4961 * to set the non-SR watermarks to 8.
4963 void intel_update_watermarks(struct intel_crtc
*crtc
)
4965 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4967 if (dev_priv
->display
.update_wm
)
4968 dev_priv
->display
.update_wm(crtc
);
4972 * Lock protecting IPS related data structures
4974 DEFINE_SPINLOCK(mchdev_lock
);
4976 /* Global for IPS driver to get at the current i915 device. Protected by
4978 static struct drm_i915_private
*i915_mch_dev
;
4980 bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
)
4984 lockdep_assert_held(&mchdev_lock
);
4986 rgvswctl
= I915_READ16(MEMSWCTL
);
4987 if (rgvswctl
& MEMCTL_CMD_STS
) {
4988 DRM_DEBUG("gpu busy, RCS change rejected\n");
4989 return false; /* still busy with another command */
4992 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
4993 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
4994 I915_WRITE16(MEMSWCTL
, rgvswctl
);
4995 POSTING_READ16(MEMSWCTL
);
4997 rgvswctl
|= MEMCTL_CMD_STS
;
4998 I915_WRITE16(MEMSWCTL
, rgvswctl
);
5003 static void ironlake_enable_drps(struct drm_i915_private
*dev_priv
)
5006 u8 fmax
, fmin
, fstart
, vstart
;
5008 spin_lock_irq(&mchdev_lock
);
5010 rgvmodectl
= I915_READ(MEMMODECTL
);
5012 /* Enable temp reporting */
5013 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
5014 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
5016 /* 100ms RC evaluation intervals */
5017 I915_WRITE(RCUPEI
, 100000);
5018 I915_WRITE(RCDNEI
, 100000);
5020 /* Set max/min thresholds to 90ms and 80ms respectively */
5021 I915_WRITE(RCBMAXAVG
, 90000);
5022 I915_WRITE(RCBMINAVG
, 80000);
5024 I915_WRITE(MEMIHYST
, 1);
5026 /* Set up min, max, and cur for interrupt handling */
5027 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
5028 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
5029 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
5030 MEMMODE_FSTART_SHIFT
;
5032 vstart
= (I915_READ(PXVFREQ(fstart
)) & PXVFREQ_PX_MASK
) >>
5035 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
5036 dev_priv
->ips
.fstart
= fstart
;
5038 dev_priv
->ips
.max_delay
= fstart
;
5039 dev_priv
->ips
.min_delay
= fmin
;
5040 dev_priv
->ips
.cur_delay
= fstart
;
5042 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5043 fmax
, fmin
, fstart
);
5045 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
5048 * Interrupts will be enabled in ironlake_irq_postinstall
5051 I915_WRITE(VIDSTART
, vstart
);
5052 POSTING_READ(VIDSTART
);
5054 rgvmodectl
|= MEMMODE_SWMODE_EN
;
5055 I915_WRITE(MEMMODECTL
, rgvmodectl
);
5057 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
5058 DRM_ERROR("stuck trying to change perf mode\n");
5061 ironlake_set_drps(dev_priv
, fstart
);
5063 dev_priv
->ips
.last_count1
= I915_READ(DMIEC
) +
5064 I915_READ(DDREC
) + I915_READ(CSIEC
);
5065 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
5066 dev_priv
->ips
.last_count2
= I915_READ(GFXEC
);
5067 dev_priv
->ips
.last_time2
= ktime_get_raw_ns();
5069 spin_unlock_irq(&mchdev_lock
);
5072 static void ironlake_disable_drps(struct drm_i915_private
*dev_priv
)
5076 spin_lock_irq(&mchdev_lock
);
5078 rgvswctl
= I915_READ16(MEMSWCTL
);
5080 /* Ack interrupts, disable EFC interrupt */
5081 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
5082 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
5083 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
5084 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
5085 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
5087 /* Go back to the starting frequency */
5088 ironlake_set_drps(dev_priv
, dev_priv
->ips
.fstart
);
5090 rgvswctl
|= MEMCTL_CMD_STS
;
5091 I915_WRITE(MEMSWCTL
, rgvswctl
);
5094 spin_unlock_irq(&mchdev_lock
);
5097 /* There's a funny hw issue where the hw returns all 0 when reading from
5098 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
5099 * ourselves, instead of doing a rmw cycle (which might result in us clearing
5100 * all limits and the gpu stuck at whatever frequency it is at atm).
5102 static u32
intel_rps_limits(struct drm_i915_private
*dev_priv
, u8 val
)
5106 /* Only set the down limit when we've reached the lowest level to avoid
5107 * getting more interrupts, otherwise leave this clear. This prevents a
5108 * race in the hw when coming out of rc6: There's a tiny window where
5109 * the hw runs at the minimal clock before selecting the desired
5110 * frequency, if the down threshold expires in that window we will not
5111 * receive a down interrupt. */
5112 if (IS_GEN9(dev_priv
)) {
5113 limits
= (dev_priv
->rps
.max_freq_softlimit
) << 23;
5114 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
5115 limits
|= (dev_priv
->rps
.min_freq_softlimit
) << 14;
5117 limits
= dev_priv
->rps
.max_freq_softlimit
<< 24;
5118 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
5119 limits
|= dev_priv
->rps
.min_freq_softlimit
<< 16;
5125 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
5128 u32 threshold_up
= 0, threshold_down
= 0; /* in % */
5129 u32 ei_up
= 0, ei_down
= 0;
5131 new_power
= dev_priv
->rps
.power
;
5132 switch (dev_priv
->rps
.power
) {
5134 if (val
> dev_priv
->rps
.efficient_freq
+ 1 &&
5135 val
> dev_priv
->rps
.cur_freq
)
5136 new_power
= BETWEEN
;
5140 if (val
<= dev_priv
->rps
.efficient_freq
&&
5141 val
< dev_priv
->rps
.cur_freq
)
5142 new_power
= LOW_POWER
;
5143 else if (val
>= dev_priv
->rps
.rp0_freq
&&
5144 val
> dev_priv
->rps
.cur_freq
)
5145 new_power
= HIGH_POWER
;
5149 if (val
< (dev_priv
->rps
.rp1_freq
+ dev_priv
->rps
.rp0_freq
) >> 1 &&
5150 val
< dev_priv
->rps
.cur_freq
)
5151 new_power
= BETWEEN
;
5154 /* Max/min bins are special */
5155 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
5156 new_power
= LOW_POWER
;
5157 if (val
>= dev_priv
->rps
.max_freq_softlimit
)
5158 new_power
= HIGH_POWER
;
5159 if (new_power
== dev_priv
->rps
.power
)
5162 /* Note the units here are not exactly 1us, but 1280ns. */
5163 switch (new_power
) {
5165 /* Upclock if more than 95% busy over 16ms */
5169 /* Downclock if less than 85% busy over 32ms */
5171 threshold_down
= 85;
5175 /* Upclock if more than 90% busy over 13ms */
5179 /* Downclock if less than 75% busy over 32ms */
5181 threshold_down
= 75;
5185 /* Upclock if more than 85% busy over 10ms */
5189 /* Downclock if less than 60% busy over 32ms */
5191 threshold_down
= 60;
5195 /* When byt can survive without system hang with dynamic
5196 * sw freq adjustments, this restriction can be lifted.
5198 if (IS_VALLEYVIEW(dev_priv
))
5201 I915_WRITE(GEN6_RP_UP_EI
,
5202 GT_INTERVAL_FROM_US(dev_priv
, ei_up
));
5203 I915_WRITE(GEN6_RP_UP_THRESHOLD
,
5204 GT_INTERVAL_FROM_US(dev_priv
,
5205 ei_up
* threshold_up
/ 100));
5207 I915_WRITE(GEN6_RP_DOWN_EI
,
5208 GT_INTERVAL_FROM_US(dev_priv
, ei_down
));
5209 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
,
5210 GT_INTERVAL_FROM_US(dev_priv
,
5211 ei_down
* threshold_down
/ 100));
5213 I915_WRITE(GEN6_RP_CONTROL
,
5214 GEN6_RP_MEDIA_TURBO
|
5215 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
5216 GEN6_RP_MEDIA_IS_GFX
|
5218 GEN6_RP_UP_BUSY_AVG
|
5219 GEN6_RP_DOWN_IDLE_AVG
);
5222 dev_priv
->rps
.power
= new_power
;
5223 dev_priv
->rps
.up_threshold
= threshold_up
;
5224 dev_priv
->rps
.down_threshold
= threshold_down
;
5225 dev_priv
->rps
.last_adj
= 0;
5228 static u32
gen6_rps_pm_mask(struct drm_i915_private
*dev_priv
, u8 val
)
5232 /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
5233 if (val
> dev_priv
->rps
.min_freq_softlimit
)
5234 mask
|= GEN6_PM_RP_UP_EI_EXPIRED
| GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT
;
5235 if (val
< dev_priv
->rps
.max_freq_softlimit
)
5236 mask
|= GEN6_PM_RP_UP_EI_EXPIRED
| GEN6_PM_RP_UP_THRESHOLD
;
5238 mask
&= dev_priv
->pm_rps_events
;
5240 return gen6_sanitize_rps_pm_mask(dev_priv
, ~mask
);
5243 /* gen6_set_rps is called to update the frequency request, but should also be
5244 * called when the range (min_delay and max_delay) is modified so that we can
5245 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
5246 static int gen6_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
5248 /* min/max delay may still have been modified so be sure to
5249 * write the limits value.
5251 if (val
!= dev_priv
->rps
.cur_freq
) {
5252 gen6_set_rps_thresholds(dev_priv
, val
);
5254 if (IS_GEN9(dev_priv
))
5255 I915_WRITE(GEN6_RPNSWREQ
,
5256 GEN9_FREQUENCY(val
));
5257 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5258 I915_WRITE(GEN6_RPNSWREQ
,
5259 HSW_FREQUENCY(val
));
5261 I915_WRITE(GEN6_RPNSWREQ
,
5262 GEN6_FREQUENCY(val
) |
5264 GEN6_AGGRESSIVE_TURBO
);
5267 /* Make sure we continue to get interrupts
5268 * until we hit the minimum or maximum frequencies.
5270 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, intel_rps_limits(dev_priv
, val
));
5271 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
5273 dev_priv
->rps
.cur_freq
= val
;
5274 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
5279 static int valleyview_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
5283 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv
) && (val
& 1),
5284 "Odd GPU freq value\n"))
5287 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
5289 if (val
!= dev_priv
->rps
.cur_freq
) {
5290 err
= vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
5294 gen6_set_rps_thresholds(dev_priv
, val
);
5297 dev_priv
->rps
.cur_freq
= val
;
5298 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
5303 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
5305 * * If Gfx is Idle, then
5306 * 1. Forcewake Media well.
5307 * 2. Request idle freq.
5308 * 3. Release Forcewake of Media well.
5310 static void vlv_set_rps_idle(struct drm_i915_private
*dev_priv
)
5312 u32 val
= dev_priv
->rps
.idle_freq
;
5315 if (dev_priv
->rps
.cur_freq
<= val
)
5318 /* The punit delays the write of the frequency and voltage until it
5319 * determines the GPU is awake. During normal usage we don't want to
5320 * waste power changing the frequency if the GPU is sleeping (rc6).
5321 * However, the GPU and driver is now idle and we do not want to delay
5322 * switching to minimum voltage (reducing power whilst idle) as we do
5323 * not expect to be woken in the near future and so must flush the
5324 * change by waking the device.
5326 * We choose to take the media powerwell (either would do to trick the
5327 * punit into committing the voltage change) as that takes a lot less
5328 * power than the render powerwell.
5330 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_MEDIA
);
5331 err
= valleyview_set_rps(dev_priv
, val
);
5332 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_MEDIA
);
5335 DRM_ERROR("Failed to set RPS for idle\n");
5338 void gen6_rps_busy(struct drm_i915_private
*dev_priv
)
5340 mutex_lock(&dev_priv
->rps
.hw_lock
);
5341 if (dev_priv
->rps
.enabled
) {
5344 if (dev_priv
->pm_rps_events
& GEN6_PM_RP_UP_EI_EXPIRED
)
5345 gen6_rps_reset_ei(dev_priv
);
5346 I915_WRITE(GEN6_PMINTRMSK
,
5347 gen6_rps_pm_mask(dev_priv
, dev_priv
->rps
.cur_freq
));
5349 gen6_enable_rps_interrupts(dev_priv
);
5351 /* Use the user's desired frequency as a guide, but for better
5352 * performance, jump directly to RPe as our starting frequency.
5354 freq
= max(dev_priv
->rps
.cur_freq
,
5355 dev_priv
->rps
.efficient_freq
);
5357 if (intel_set_rps(dev_priv
,
5359 dev_priv
->rps
.min_freq_softlimit
,
5360 dev_priv
->rps
.max_freq_softlimit
)))
5361 DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
5363 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5366 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
5368 /* Flush our bottom-half so that it does not race with us
5369 * setting the idle frequency and so that it is bounded by
5370 * our rpm wakeref. And then disable the interrupts to stop any
5371 * futher RPS reclocking whilst we are asleep.
5373 gen6_disable_rps_interrupts(dev_priv
);
5375 mutex_lock(&dev_priv
->rps
.hw_lock
);
5376 if (dev_priv
->rps
.enabled
) {
5377 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5378 vlv_set_rps_idle(dev_priv
);
5380 gen6_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
5381 dev_priv
->rps
.last_adj
= 0;
5382 I915_WRITE(GEN6_PMINTRMSK
,
5383 gen6_sanitize_rps_pm_mask(dev_priv
, ~0));
5385 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5387 spin_lock(&dev_priv
->rps
.client_lock
);
5388 while (!list_empty(&dev_priv
->rps
.clients
))
5389 list_del_init(dev_priv
->rps
.clients
.next
);
5390 spin_unlock(&dev_priv
->rps
.client_lock
);
5393 void gen6_rps_boost(struct drm_i915_private
*dev_priv
,
5394 struct intel_rps_client
*rps
,
5395 unsigned long submitted
)
5397 /* This is intentionally racy! We peek at the state here, then
5398 * validate inside the RPS worker.
5400 if (!(dev_priv
->gt
.awake
&&
5401 dev_priv
->rps
.enabled
&&
5402 dev_priv
->rps
.cur_freq
< dev_priv
->rps
.boost_freq
))
5405 /* Force a RPS boost (and don't count it against the client) if
5406 * the GPU is severely congested.
5408 if (rps
&& time_after(jiffies
, submitted
+ DRM_I915_THROTTLE_JIFFIES
))
5411 spin_lock(&dev_priv
->rps
.client_lock
);
5412 if (rps
== NULL
|| list_empty(&rps
->link
)) {
5413 spin_lock_irq(&dev_priv
->irq_lock
);
5414 if (dev_priv
->rps
.interrupts_enabled
) {
5415 dev_priv
->rps
.client_boost
= true;
5416 schedule_work(&dev_priv
->rps
.work
);
5418 spin_unlock_irq(&dev_priv
->irq_lock
);
5421 list_add(&rps
->link
, &dev_priv
->rps
.clients
);
5424 dev_priv
->rps
.boosts
++;
5426 spin_unlock(&dev_priv
->rps
.client_lock
);
5429 int intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
5433 lockdep_assert_held(&dev_priv
->rps
.hw_lock
);
5434 GEM_BUG_ON(val
> dev_priv
->rps
.max_freq
);
5435 GEM_BUG_ON(val
< dev_priv
->rps
.min_freq
);
5437 if (!dev_priv
->rps
.enabled
) {
5438 dev_priv
->rps
.cur_freq
= val
;
5442 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5443 err
= valleyview_set_rps(dev_priv
, val
);
5445 err
= gen6_set_rps(dev_priv
, val
);
5450 static void gen9_disable_rc6(struct drm_i915_private
*dev_priv
)
5452 I915_WRITE(GEN6_RC_CONTROL
, 0);
5453 I915_WRITE(GEN9_PG_ENABLE
, 0);
5456 static void gen9_disable_rps(struct drm_i915_private
*dev_priv
)
5458 I915_WRITE(GEN6_RP_CONTROL
, 0);
5461 static void gen6_disable_rps(struct drm_i915_private
*dev_priv
)
5463 I915_WRITE(GEN6_RC_CONTROL
, 0);
5464 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
5465 I915_WRITE(GEN6_RP_CONTROL
, 0);
5468 static void cherryview_disable_rps(struct drm_i915_private
*dev_priv
)
5470 I915_WRITE(GEN6_RC_CONTROL
, 0);
5473 static void valleyview_disable_rps(struct drm_i915_private
*dev_priv
)
5475 /* we're doing forcewake before Disabling RC6,
5476 * This what the BIOS expects when going into suspend */
5477 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5479 I915_WRITE(GEN6_RC_CONTROL
, 0);
5481 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5484 static void intel_print_rc6_info(struct drm_i915_private
*dev_priv
, u32 mode
)
5486 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5487 if (mode
& (GEN7_RC_CTL_TO_MODE
| GEN6_RC_CTL_EI_MODE(1)))
5488 mode
= GEN6_RC_CTL_RC6_ENABLE
;
5492 if (HAS_RC6p(dev_priv
))
5493 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5494 "RC6 %s RC6p %s RC6pp %s\n",
5495 onoff(mode
& GEN6_RC_CTL_RC6_ENABLE
),
5496 onoff(mode
& GEN6_RC_CTL_RC6p_ENABLE
),
5497 onoff(mode
& GEN6_RC_CTL_RC6pp_ENABLE
));
5500 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5501 onoff(mode
& GEN6_RC_CTL_RC6_ENABLE
));
5504 static bool bxt_check_bios_rc6_setup(struct drm_i915_private
*dev_priv
)
5506 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
5507 bool enable_rc6
= true;
5508 unsigned long rc6_ctx_base
;
5512 rc_ctl
= I915_READ(GEN6_RC_CONTROL
);
5513 rc_sw_target
= (I915_READ(GEN6_RC_STATE
) & RC_SW_TARGET_STATE_MASK
) >>
5514 RC_SW_TARGET_STATE_SHIFT
;
5515 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5516 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5517 onoff(rc_ctl
& GEN6_RC_CTL_HW_ENABLE
),
5518 onoff(rc_ctl
& GEN6_RC_CTL_RC6_ENABLE
),
5521 if (!(I915_READ(RC6_LOCATION
) & RC6_CTX_IN_DRAM
)) {
5522 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5527 * The exact context size is not known for BXT, so assume a page size
5530 rc6_ctx_base
= I915_READ(RC6_CTX_BASE
) & RC6_CTX_BASE_MASK
;
5531 if (!((rc6_ctx_base
>= ggtt
->stolen_reserved_base
) &&
5532 (rc6_ctx_base
+ PAGE_SIZE
<= ggtt
->stolen_reserved_base
+
5533 ggtt
->stolen_reserved_size
))) {
5534 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5538 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT
) & IDLE_TIME_MASK
) > 1) &&
5539 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0
) & IDLE_TIME_MASK
) > 1) &&
5540 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT
) & IDLE_TIME_MASK
) > 1) &&
5541 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT
) & IDLE_TIME_MASK
) > 1))) {
5542 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5546 if (!I915_READ(GEN8_PUSHBUS_CONTROL
) ||
5547 !I915_READ(GEN8_PUSHBUS_ENABLE
) ||
5548 !I915_READ(GEN8_PUSHBUS_SHIFT
)) {
5549 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5553 if (!I915_READ(GEN6_GFXPAUSE
)) {
5554 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5558 if (!I915_READ(GEN8_MISC_CTRL0
)) {
5559 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5566 int sanitize_rc6_option(struct drm_i915_private
*dev_priv
, int enable_rc6
)
5568 /* No RC6 before Ironlake and code is gone for ilk. */
5569 if (INTEL_INFO(dev_priv
)->gen
< 6)
5575 if (IS_GEN9_LP(dev_priv
) && !bxt_check_bios_rc6_setup(dev_priv
)) {
5576 DRM_INFO("RC6 disabled by BIOS\n");
5580 /* Respect the kernel parameter if it is set */
5581 if (enable_rc6
>= 0) {
5584 if (HAS_RC6p(dev_priv
))
5585 mask
= INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
|
5588 mask
= INTEL_RC6_ENABLE
;
5590 if ((enable_rc6
& mask
) != enable_rc6
)
5591 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5592 "(requested %d, valid %d)\n",
5593 enable_rc6
& mask
, enable_rc6
, mask
);
5595 return enable_rc6
& mask
;
5598 if (IS_IVYBRIDGE(dev_priv
))
5599 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
5601 return INTEL_RC6_ENABLE
;
5604 static void gen6_init_rps_frequencies(struct drm_i915_private
*dev_priv
)
5606 /* All of these values are in units of 50MHz */
5608 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5609 if (IS_GEN9_LP(dev_priv
)) {
5610 u32 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
5611 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 16) & 0xff;
5612 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
5613 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 0) & 0xff;
5615 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
5616 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 0) & 0xff;
5617 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
5618 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 16) & 0xff;
5620 /* hw_max = RP0 until we check for overclocking */
5621 dev_priv
->rps
.max_freq
= dev_priv
->rps
.rp0_freq
;
5623 dev_priv
->rps
.efficient_freq
= dev_priv
->rps
.rp1_freq
;
5624 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
) ||
5625 IS_GEN9_BC(dev_priv
)) {
5626 u32 ddcc_status
= 0;
5628 if (sandybridge_pcode_read(dev_priv
,
5629 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL
,
5631 dev_priv
->rps
.efficient_freq
=
5633 ((ddcc_status
>> 8) & 0xff),
5634 dev_priv
->rps
.min_freq
,
5635 dev_priv
->rps
.max_freq
);
5638 if (IS_GEN9_BC(dev_priv
)) {
5639 /* Store the frequency values in 16.66 MHZ units, which is
5640 * the natural hardware unit for SKL
5642 dev_priv
->rps
.rp0_freq
*= GEN9_FREQ_SCALER
;
5643 dev_priv
->rps
.rp1_freq
*= GEN9_FREQ_SCALER
;
5644 dev_priv
->rps
.min_freq
*= GEN9_FREQ_SCALER
;
5645 dev_priv
->rps
.max_freq
*= GEN9_FREQ_SCALER
;
5646 dev_priv
->rps
.efficient_freq
*= GEN9_FREQ_SCALER
;
5650 static void reset_rps(struct drm_i915_private
*dev_priv
,
5651 int (*set
)(struct drm_i915_private
*, u8
))
5653 u8 freq
= dev_priv
->rps
.cur_freq
;
5656 dev_priv
->rps
.power
= -1;
5657 dev_priv
->rps
.cur_freq
= -1;
5659 if (set(dev_priv
, freq
))
5660 DRM_ERROR("Failed to reset RPS to initial values\n");
5663 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5664 static void gen9_enable_rps(struct drm_i915_private
*dev_priv
)
5666 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5668 /* Program defaults and thresholds for RPS*/
5669 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
5670 GEN9_FREQUENCY(dev_priv
->rps
.rp1_freq
));
5672 /* 1 second timeout*/
5673 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,
5674 GT_INTERVAL_FROM_US(dev_priv
, 1000000));
5676 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 0xa);
5678 /* Leaning on the below call to gen6_set_rps to program/setup the
5679 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5680 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5681 reset_rps(dev_priv
, gen6_set_rps
);
5683 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5686 static void gen9_enable_rc6(struct drm_i915_private
*dev_priv
)
5688 struct intel_engine_cs
*engine
;
5689 enum intel_engine_id id
;
5690 uint32_t rc6_mask
= 0;
5692 /* 1a: Software RC state - RC0 */
5693 I915_WRITE(GEN6_RC_STATE
, 0);
5695 /* 1b: Get forcewake during program sequence. Although the driver
5696 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5697 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5699 /* 2a: Disable RC states. */
5700 I915_WRITE(GEN6_RC_CONTROL
, 0);
5702 /* 2b: Program RC6 thresholds.*/
5704 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5705 if (IS_SKYLAKE(dev_priv
))
5706 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 108 << 16);
5708 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 54 << 16);
5709 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
5710 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
5711 for_each_engine(engine
, dev_priv
, id
)
5712 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
5714 if (HAS_GUC(dev_priv
))
5715 I915_WRITE(GUC_MAX_IDLE_COUNT
, 0xA);
5717 I915_WRITE(GEN6_RC_SLEEP
, 0);
5719 /* 2c: Program Coarse Power Gating Policies. */
5720 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS
, 25);
5721 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS
, 25);
5723 /* 3a: Enable RC6 */
5724 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
5725 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
5726 DRM_INFO("RC6 %s\n", onoff(rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
));
5727 I915_WRITE(GEN6_RC6_THRESHOLD
, 37500); /* 37.5/125ms per EI */
5728 I915_WRITE(GEN6_RC_CONTROL
,
5729 GEN6_RC_CTL_HW_ENABLE
| GEN6_RC_CTL_EI_MODE(1) | rc6_mask
);
5732 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5733 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5735 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv
))
5736 I915_WRITE(GEN9_PG_ENABLE
, 0);
5738 I915_WRITE(GEN9_PG_ENABLE
, (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ?
5739 (GEN9_RENDER_PG_ENABLE
| GEN9_MEDIA_PG_ENABLE
) : 0);
5741 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5744 static void gen8_enable_rps(struct drm_i915_private
*dev_priv
)
5746 struct intel_engine_cs
*engine
;
5747 enum intel_engine_id id
;
5748 uint32_t rc6_mask
= 0;
5750 /* 1a: Software RC state - RC0 */
5751 I915_WRITE(GEN6_RC_STATE
, 0);
5753 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5754 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5755 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5757 /* 2a: Disable RC states. */
5758 I915_WRITE(GEN6_RC_CONTROL
, 0);
5760 /* 2b: Program RC6 thresholds.*/
5761 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
5762 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
5763 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
5764 for_each_engine(engine
, dev_priv
, id
)
5765 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
5766 I915_WRITE(GEN6_RC_SLEEP
, 0);
5767 if (IS_BROADWELL(dev_priv
))
5768 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us/1.28 for TO */
5770 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
5773 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
5774 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
5775 intel_print_rc6_info(dev_priv
, rc6_mask
);
5776 if (IS_BROADWELL(dev_priv
))
5777 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
5778 GEN7_RC_CTL_TO_MODE
|
5781 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
5782 GEN6_RC_CTL_EI_MODE(1) |
5785 /* 4 Program defaults and thresholds for RPS*/
5786 I915_WRITE(GEN6_RPNSWREQ
,
5787 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
5788 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
5789 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
5790 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5791 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 100000000 / 128); /* 1 second timeout */
5793 /* Docs recommend 900MHz, and 300 MHz respectively */
5794 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
5795 dev_priv
->rps
.max_freq_softlimit
<< 24 |
5796 dev_priv
->rps
.min_freq_softlimit
<< 16);
5798 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 7600000 / 128); /* 76ms busyness per EI, 90% */
5799 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5800 I915_WRITE(GEN6_RP_UP_EI
, 66000); /* 84.48ms, XXX: random? */
5801 I915_WRITE(GEN6_RP_DOWN_EI
, 350000); /* 448ms, XXX: random? */
5803 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5806 I915_WRITE(GEN6_RP_CONTROL
,
5807 GEN6_RP_MEDIA_TURBO
|
5808 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
5809 GEN6_RP_MEDIA_IS_GFX
|
5811 GEN6_RP_UP_BUSY_AVG
|
5812 GEN6_RP_DOWN_IDLE_AVG
);
5814 /* 6: Ring frequency + overclocking (our driver does this later */
5816 reset_rps(dev_priv
, gen6_set_rps
);
5818 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5821 static void gen6_enable_rps(struct drm_i915_private
*dev_priv
)
5823 struct intel_engine_cs
*engine
;
5824 enum intel_engine_id id
;
5825 u32 rc6vids
, rc6_mask
= 0;
5830 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5832 /* Here begins a magic sequence of register writes to enable
5833 * auto-downclocking.
5835 * Perhaps there might be some value in exposing these to
5838 I915_WRITE(GEN6_RC_STATE
, 0);
5840 /* Clear the DBG now so we don't confuse earlier errors */
5841 gtfifodbg
= I915_READ(GTFIFODBG
);
5843 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
5844 I915_WRITE(GTFIFODBG
, gtfifodbg
);
5847 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5849 /* disable the counters and set deterministic thresholds */
5850 I915_WRITE(GEN6_RC_CONTROL
, 0);
5852 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
5853 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
5854 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
5855 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
5856 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
5858 for_each_engine(engine
, dev_priv
, id
)
5859 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
5861 I915_WRITE(GEN6_RC_SLEEP
, 0);
5862 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
5863 if (IS_IVYBRIDGE(dev_priv
))
5864 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
5866 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
5867 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
5868 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
5870 /* Check if we are enabling RC6 */
5871 rc6_mode
= intel_enable_rc6();
5872 if (rc6_mode
& INTEL_RC6_ENABLE
)
5873 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
5875 /* We don't use those on Haswell */
5876 if (!IS_HASWELL(dev_priv
)) {
5877 if (rc6_mode
& INTEL_RC6p_ENABLE
)
5878 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
5880 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
5881 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
5884 intel_print_rc6_info(dev_priv
, rc6_mask
);
5886 I915_WRITE(GEN6_RC_CONTROL
,
5888 GEN6_RC_CTL_EI_MODE(1) |
5889 GEN6_RC_CTL_HW_ENABLE
);
5891 /* Power down if completely idle for over 50ms */
5892 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
5893 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5895 reset_rps(dev_priv
, gen6_set_rps
);
5898 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
5899 if (IS_GEN6(dev_priv
) && ret
) {
5900 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5901 } else if (IS_GEN6(dev_priv
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
5902 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5903 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
5904 rc6vids
&= 0xffff00;
5905 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
5906 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
5908 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5911 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5914 static void gen6_update_ring_freq(struct drm_i915_private
*dev_priv
)
5917 unsigned int gpu_freq
;
5918 unsigned int max_ia_freq
, min_ring_freq
;
5919 unsigned int max_gpu_freq
, min_gpu_freq
;
5920 int scaling_factor
= 180;
5921 struct cpufreq_policy
*policy
;
5923 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5925 policy
= cpufreq_cpu_get(0);
5927 max_ia_freq
= policy
->cpuinfo
.max_freq
;
5928 cpufreq_cpu_put(policy
);
5931 * Default to measured freq if none found, PCU will ensure we
5934 max_ia_freq
= tsc_khz
;
5937 /* Convert from kHz to MHz */
5938 max_ia_freq
/= 1000;
5940 min_ring_freq
= I915_READ(DCLK
) & 0xf;
5941 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5942 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
5944 if (IS_GEN9_BC(dev_priv
)) {
5945 /* Convert GT frequency to 50 HZ units */
5946 min_gpu_freq
= dev_priv
->rps
.min_freq
/ GEN9_FREQ_SCALER
;
5947 max_gpu_freq
= dev_priv
->rps
.max_freq
/ GEN9_FREQ_SCALER
;
5949 min_gpu_freq
= dev_priv
->rps
.min_freq
;
5950 max_gpu_freq
= dev_priv
->rps
.max_freq
;
5954 * For each potential GPU frequency, load a ring frequency we'd like
5955 * to use for memory access. We do this by specifying the IA frequency
5956 * the PCU should use as a reference to determine the ring frequency.
5958 for (gpu_freq
= max_gpu_freq
; gpu_freq
>= min_gpu_freq
; gpu_freq
--) {
5959 int diff
= max_gpu_freq
- gpu_freq
;
5960 unsigned int ia_freq
= 0, ring_freq
= 0;
5962 if (IS_GEN9_BC(dev_priv
)) {
5964 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5965 * No floor required for ring frequency on SKL.
5967 ring_freq
= gpu_freq
;
5968 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
5969 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5970 ring_freq
= max(min_ring_freq
, gpu_freq
);
5971 } else if (IS_HASWELL(dev_priv
)) {
5972 ring_freq
= mult_frac(gpu_freq
, 5, 4);
5973 ring_freq
= max(min_ring_freq
, ring_freq
);
5974 /* leave ia_freq as the default, chosen by cpufreq */
5976 /* On older processors, there is no separate ring
5977 * clock domain, so in order to boost the bandwidth
5978 * of the ring, we need to upclock the CPU (ia_freq).
5980 * For GPU frequencies less than 750MHz,
5981 * just use the lowest ring freq.
5983 if (gpu_freq
< min_freq
)
5986 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
5987 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
5990 sandybridge_pcode_write(dev_priv
,
5991 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
5992 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
5993 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
5998 static int cherryview_rps_max_freq(struct drm_i915_private
*dev_priv
)
6002 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
6004 switch (INTEL_INFO(dev_priv
)->sseu
.eu_total
) {
6006 /* (2 * 4) config */
6007 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT
);
6010 /* (2 * 6) config */
6011 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT
);
6014 /* (2 * 8) config */
6016 /* Setting (2 * 8) Min RP0 for any other combination */
6017 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT
);
6021 rp0
= (rp0
& FB_GFX_FREQ_FUSE_MASK
);
6026 static int cherryview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
6030 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_DUTYCYCLE_REG
);
6031 rpe
= (val
>> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT
) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK
;
6036 static int cherryview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
6040 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
6041 rp1
= (val
& FB_GFX_FREQ_FUSE_MASK
);
6046 static u32
cherryview_rps_min_freq(struct drm_i915_private
*dev_priv
)
6050 val
= vlv_punit_read(dev_priv
, FB_GFX_FMIN_AT_VMIN_FUSE
);
6051 rpn
= ((val
>> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT
) &
6052 FB_GFX_FREQ_FUSE_MASK
);
6057 static int valleyview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
6061 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
6063 rp1
= (val
& FB_GFX_FGUARANTEED_FREQ_FUSE_MASK
) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT
;
6068 static int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
6072 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
6074 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
6076 rp0
= min_t(u32
, rp0
, 0xea);
6081 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
6085 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
6086 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
6087 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
6088 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
6093 static int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
6097 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
6099 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
6100 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
6101 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
6102 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
6103 * to make sure it matches what Punit accepts.
6105 return max_t(u32
, val
, 0xc0);
6108 /* Check that the pctx buffer wasn't move under us. */
6109 static void valleyview_check_pctx(struct drm_i915_private
*dev_priv
)
6111 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
6113 WARN_ON(pctx_addr
!= dev_priv
->mm
.stolen_base
+
6114 dev_priv
->vlv_pctx
->stolen
->start
);
6118 /* Check that the pcbr address is not empty. */
6119 static void cherryview_check_pctx(struct drm_i915_private
*dev_priv
)
6121 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
6123 WARN_ON((pctx_addr
>> VLV_PCBR_ADDR_SHIFT
) == 0);
6126 static void cherryview_setup_pctx(struct drm_i915_private
*dev_priv
)
6128 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
6129 unsigned long pctx_paddr
, paddr
;
6131 int pctx_size
= 32*1024;
6133 pcbr
= I915_READ(VLV_PCBR
);
6134 if ((pcbr
>> VLV_PCBR_ADDR_SHIFT
) == 0) {
6135 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
6136 paddr
= (dev_priv
->mm
.stolen_base
+
6137 (ggtt
->stolen_size
- pctx_size
));
6139 pctx_paddr
= (paddr
& (~4095));
6140 I915_WRITE(VLV_PCBR
, pctx_paddr
);
6143 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
6146 static void valleyview_setup_pctx(struct drm_i915_private
*dev_priv
)
6148 struct drm_i915_gem_object
*pctx
;
6149 unsigned long pctx_paddr
;
6151 int pctx_size
= 24*1024;
6153 pcbr
= I915_READ(VLV_PCBR
);
6155 /* BIOS set it up already, grab the pre-alloc'd space */
6158 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
6159 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
,
6161 I915_GTT_OFFSET_NONE
,
6166 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
6169 * From the Gunit register HAS:
6170 * The Gfx driver is expected to program this register and ensure
6171 * proper allocation within Gfx stolen memory. For example, this
6172 * register should be programmed such than the PCBR range does not
6173 * overlap with other ranges, such as the frame buffer, protected
6174 * memory, or any other relevant ranges.
6176 pctx
= i915_gem_object_create_stolen(dev_priv
, pctx_size
);
6178 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
6182 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
6183 I915_WRITE(VLV_PCBR
, pctx_paddr
);
6186 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
6187 dev_priv
->vlv_pctx
= pctx
;
6190 static void valleyview_cleanup_pctx(struct drm_i915_private
*dev_priv
)
6192 if (WARN_ON(!dev_priv
->vlv_pctx
))
6195 i915_gem_object_put(dev_priv
->vlv_pctx
);
6196 dev_priv
->vlv_pctx
= NULL
;
6199 static void vlv_init_gpll_ref_freq(struct drm_i915_private
*dev_priv
)
6201 dev_priv
->rps
.gpll_ref_freq
=
6202 vlv_get_cck_clock(dev_priv
, "GPLL ref",
6203 CCK_GPLL_CLOCK_CONTROL
,
6204 dev_priv
->czclk_freq
);
6206 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
6207 dev_priv
->rps
.gpll_ref_freq
);
6210 static void valleyview_init_gt_powersave(struct drm_i915_private
*dev_priv
)
6214 valleyview_setup_pctx(dev_priv
);
6216 vlv_init_gpll_ref_freq(dev_priv
);
6218 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
6219 switch ((val
>> 6) & 3) {
6222 dev_priv
->mem_freq
= 800;
6225 dev_priv
->mem_freq
= 1066;
6228 dev_priv
->mem_freq
= 1333;
6231 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
6233 dev_priv
->rps
.max_freq
= valleyview_rps_max_freq(dev_priv
);
6234 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
6235 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
6236 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
6237 dev_priv
->rps
.max_freq
);
6239 dev_priv
->rps
.efficient_freq
= valleyview_rps_rpe_freq(dev_priv
);
6240 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
6241 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
6242 dev_priv
->rps
.efficient_freq
);
6244 dev_priv
->rps
.rp1_freq
= valleyview_rps_guar_freq(dev_priv
);
6245 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
6246 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
6247 dev_priv
->rps
.rp1_freq
);
6249 dev_priv
->rps
.min_freq
= valleyview_rps_min_freq(dev_priv
);
6250 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
6251 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
6252 dev_priv
->rps
.min_freq
);
6255 static void cherryview_init_gt_powersave(struct drm_i915_private
*dev_priv
)
6259 cherryview_setup_pctx(dev_priv
);
6261 vlv_init_gpll_ref_freq(dev_priv
);
6263 mutex_lock(&dev_priv
->sb_lock
);
6264 val
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
);
6265 mutex_unlock(&dev_priv
->sb_lock
);
6267 switch ((val
>> 2) & 0x7) {
6269 dev_priv
->mem_freq
= 2000;
6272 dev_priv
->mem_freq
= 1600;
6275 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
6277 dev_priv
->rps
.max_freq
= cherryview_rps_max_freq(dev_priv
);
6278 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
6279 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
6280 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
6281 dev_priv
->rps
.max_freq
);
6283 dev_priv
->rps
.efficient_freq
= cherryview_rps_rpe_freq(dev_priv
);
6284 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
6285 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
6286 dev_priv
->rps
.efficient_freq
);
6288 dev_priv
->rps
.rp1_freq
= cherryview_rps_guar_freq(dev_priv
);
6289 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
6290 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
6291 dev_priv
->rps
.rp1_freq
);
6293 dev_priv
->rps
.min_freq
= cherryview_rps_min_freq(dev_priv
);
6294 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
6295 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
6296 dev_priv
->rps
.min_freq
);
6298 WARN_ONCE((dev_priv
->rps
.max_freq
|
6299 dev_priv
->rps
.efficient_freq
|
6300 dev_priv
->rps
.rp1_freq
|
6301 dev_priv
->rps
.min_freq
) & 1,
6302 "Odd GPU freq values\n");
6305 static void valleyview_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
)
6307 valleyview_cleanup_pctx(dev_priv
);
6310 static void cherryview_enable_rps(struct drm_i915_private
*dev_priv
)
6312 struct intel_engine_cs
*engine
;
6313 enum intel_engine_id id
;
6314 u32 gtfifodbg
, val
, rc6_mode
= 0, pcbr
;
6316 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6318 gtfifodbg
= I915_READ(GTFIFODBG
) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV
|
6319 GT_FIFO_FREE_ENTRIES_CHV
);
6321 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6323 I915_WRITE(GTFIFODBG
, gtfifodbg
);
6326 cherryview_check_pctx(dev_priv
);
6328 /* 1a & 1b: Get forcewake during program sequence. Although the driver
6329 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6330 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6332 /* Disable RC states. */
6333 I915_WRITE(GEN6_RC_CONTROL
, 0);
6335 /* 2a: Program RC6 thresholds.*/
6336 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
6337 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
6338 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
6340 for_each_engine(engine
, dev_priv
, id
)
6341 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
6342 I915_WRITE(GEN6_RC_SLEEP
, 0);
6344 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6345 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x186);
6347 /* allows RC6 residency counter to work */
6348 I915_WRITE(VLV_COUNTER_CONTROL
,
6349 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
6350 VLV_MEDIA_RC6_COUNT_EN
|
6351 VLV_RENDER_RC6_COUNT_EN
));
6353 /* For now we assume BIOS is allocating and populating the PCBR */
6354 pcbr
= I915_READ(VLV_PCBR
);
6357 if ((intel_enable_rc6() & INTEL_RC6_ENABLE
) &&
6358 (pcbr
>> VLV_PCBR_ADDR_SHIFT
))
6359 rc6_mode
= GEN7_RC_CTL_TO_MODE
;
6361 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
6363 /* 4 Program defaults and thresholds for RPS*/
6364 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
6365 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
6366 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
6367 I915_WRITE(GEN6_RP_UP_EI
, 66000);
6368 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
6370 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
6373 I915_WRITE(GEN6_RP_CONTROL
,
6374 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
6375 GEN6_RP_MEDIA_IS_GFX
|
6377 GEN6_RP_UP_BUSY_AVG
|
6378 GEN6_RP_DOWN_IDLE_AVG
);
6380 /* Setting Fixed Bias */
6381 val
= VLV_OVERRIDE_EN
|
6383 CHV_BIAS_CPU_50_SOC_50
;
6384 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
6386 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
6388 /* RPS code assumes GPLL is used */
6389 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
6391 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
6392 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
6394 reset_rps(dev_priv
, valleyview_set_rps
);
6396 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6399 static void valleyview_enable_rps(struct drm_i915_private
*dev_priv
)
6401 struct intel_engine_cs
*engine
;
6402 enum intel_engine_id id
;
6403 u32 gtfifodbg
, val
, rc6_mode
= 0;
6405 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6407 valleyview_check_pctx(dev_priv
);
6409 gtfifodbg
= I915_READ(GTFIFODBG
);
6411 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6413 I915_WRITE(GTFIFODBG
, gtfifodbg
);
6416 /* If VLV, Forcewake all wells, else re-direct to regular path */
6417 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6419 /* Disable RC states. */
6420 I915_WRITE(GEN6_RC_CONTROL
, 0);
6422 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
6423 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
6424 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
6425 I915_WRITE(GEN6_RP_UP_EI
, 66000);
6426 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
6428 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
6430 I915_WRITE(GEN6_RP_CONTROL
,
6431 GEN6_RP_MEDIA_TURBO
|
6432 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
6433 GEN6_RP_MEDIA_IS_GFX
|
6435 GEN6_RP_UP_BUSY_AVG
|
6436 GEN6_RP_DOWN_IDLE_CONT
);
6438 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
6439 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
6440 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
6442 for_each_engine(engine
, dev_priv
, id
)
6443 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
6445 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
6447 /* allows RC6 residency counter to work */
6448 I915_WRITE(VLV_COUNTER_CONTROL
,
6449 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
6450 VLV_MEDIA_RC0_COUNT_EN
|
6451 VLV_RENDER_RC0_COUNT_EN
|
6452 VLV_MEDIA_RC6_COUNT_EN
|
6453 VLV_RENDER_RC6_COUNT_EN
));
6455 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
6456 rc6_mode
= GEN7_RC_CTL_TO_MODE
| VLV_RC_CTL_CTX_RST_PARALLEL
;
6458 intel_print_rc6_info(dev_priv
, rc6_mode
);
6460 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
6462 /* Setting Fixed Bias */
6463 val
= VLV_OVERRIDE_EN
|
6465 VLV_BIAS_CPU_125_SOC_875
;
6466 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
6468 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
6470 /* RPS code assumes GPLL is used */
6471 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
6473 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
6474 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
6476 reset_rps(dev_priv
, valleyview_set_rps
);
6478 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6481 static unsigned long intel_pxfreq(u32 vidfreq
)
6484 int div
= (vidfreq
& 0x3f0000) >> 16;
6485 int post
= (vidfreq
& 0x3000) >> 12;
6486 int pre
= (vidfreq
& 0x7);
6491 freq
= ((div
* 133333) / ((1<<post
) * pre
));
6496 static const struct cparams
{
6502 { 1, 1333, 301, 28664 },
6503 { 1, 1066, 294, 24460 },
6504 { 1, 800, 294, 25192 },
6505 { 0, 1333, 276, 27605 },
6506 { 0, 1066, 276, 27605 },
6507 { 0, 800, 231, 23784 },
6510 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
6512 u64 total_count
, diff
, ret
;
6513 u32 count1
, count2
, count3
, m
= 0, c
= 0;
6514 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
6517 lockdep_assert_held(&mchdev_lock
);
6519 diff1
= now
- dev_priv
->ips
.last_time1
;
6521 /* Prevent division-by-zero if we are asking too fast.
6522 * Also, we don't get interesting results if we are polling
6523 * faster than once in 10ms, so just return the saved value
6527 return dev_priv
->ips
.chipset_power
;
6529 count1
= I915_READ(DMIEC
);
6530 count2
= I915_READ(DDREC
);
6531 count3
= I915_READ(CSIEC
);
6533 total_count
= count1
+ count2
+ count3
;
6535 /* FIXME: handle per-counter overflow */
6536 if (total_count
< dev_priv
->ips
.last_count1
) {
6537 diff
= ~0UL - dev_priv
->ips
.last_count1
;
6538 diff
+= total_count
;
6540 diff
= total_count
- dev_priv
->ips
.last_count1
;
6543 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
6544 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
6545 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
6552 diff
= div_u64(diff
, diff1
);
6553 ret
= ((m
* diff
) + c
);
6554 ret
= div_u64(ret
, 10);
6556 dev_priv
->ips
.last_count1
= total_count
;
6557 dev_priv
->ips
.last_time1
= now
;
6559 dev_priv
->ips
.chipset_power
= ret
;
6564 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
6568 if (INTEL_INFO(dev_priv
)->gen
!= 5)
6571 spin_lock_irq(&mchdev_lock
);
6573 val
= __i915_chipset_val(dev_priv
);
6575 spin_unlock_irq(&mchdev_lock
);
6580 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
6582 unsigned long m
, x
, b
;
6585 tsfs
= I915_READ(TSFS
);
6587 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
6588 x
= I915_READ8(TR1
);
6590 b
= tsfs
& TSFS_INTR_MASK
;
6592 return ((m
* x
) / 127) - b
;
6595 static int _pxvid_to_vd(u8 pxvid
)
6600 if (pxvid
>= 8 && pxvid
< 31)
6603 return (pxvid
+ 2) * 125;
6606 static u32
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
6608 const int vd
= _pxvid_to_vd(pxvid
);
6609 const int vm
= vd
- 1125;
6611 if (INTEL_INFO(dev_priv
)->is_mobile
)
6612 return vm
> 0 ? vm
: 0;
6617 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
6619 u64 now
, diff
, diffms
;
6622 lockdep_assert_held(&mchdev_lock
);
6624 now
= ktime_get_raw_ns();
6625 diffms
= now
- dev_priv
->ips
.last_time2
;
6626 do_div(diffms
, NSEC_PER_MSEC
);
6628 /* Don't divide by 0 */
6632 count
= I915_READ(GFXEC
);
6634 if (count
< dev_priv
->ips
.last_count2
) {
6635 diff
= ~0UL - dev_priv
->ips
.last_count2
;
6638 diff
= count
- dev_priv
->ips
.last_count2
;
6641 dev_priv
->ips
.last_count2
= count
;
6642 dev_priv
->ips
.last_time2
= now
;
6644 /* More magic constants... */
6646 diff
= div_u64(diff
, diffms
* 10);
6647 dev_priv
->ips
.gfx_power
= diff
;
6650 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
6652 if (INTEL_INFO(dev_priv
)->gen
!= 5)
6655 spin_lock_irq(&mchdev_lock
);
6657 __i915_update_gfx_val(dev_priv
);
6659 spin_unlock_irq(&mchdev_lock
);
6662 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
6664 unsigned long t
, corr
, state1
, corr2
, state2
;
6667 lockdep_assert_held(&mchdev_lock
);
6669 pxvid
= I915_READ(PXVFREQ(dev_priv
->rps
.cur_freq
));
6670 pxvid
= (pxvid
>> 24) & 0x7f;
6671 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
6675 t
= i915_mch_val(dev_priv
);
6677 /* Revel in the empirically derived constants */
6679 /* Correction factor in 1/100000 units */
6681 corr
= ((t
* 2349) + 135940);
6683 corr
= ((t
* 964) + 29317);
6685 corr
= ((t
* 301) + 1004);
6687 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
6689 corr2
= (corr
* dev_priv
->ips
.corr
);
6691 state2
= (corr2
* state1
) / 10000;
6692 state2
/= 100; /* convert to mW */
6694 __i915_update_gfx_val(dev_priv
);
6696 return dev_priv
->ips
.gfx_power
+ state2
;
6699 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
6703 if (INTEL_INFO(dev_priv
)->gen
!= 5)
6706 spin_lock_irq(&mchdev_lock
);
6708 val
= __i915_gfx_val(dev_priv
);
6710 spin_unlock_irq(&mchdev_lock
);
6716 * i915_read_mch_val - return value for IPS use
6718 * Calculate and return a value for the IPS driver to use when deciding whether
6719 * we have thermal and power headroom to increase CPU or GPU power budget.
6721 unsigned long i915_read_mch_val(void)
6723 struct drm_i915_private
*dev_priv
;
6724 unsigned long chipset_val
, graphics_val
, ret
= 0;
6726 spin_lock_irq(&mchdev_lock
);
6729 dev_priv
= i915_mch_dev
;
6731 chipset_val
= __i915_chipset_val(dev_priv
);
6732 graphics_val
= __i915_gfx_val(dev_priv
);
6734 ret
= chipset_val
+ graphics_val
;
6737 spin_unlock_irq(&mchdev_lock
);
6741 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
6744 * i915_gpu_raise - raise GPU frequency limit
6746 * Raise the limit; IPS indicates we have thermal headroom.
6748 bool i915_gpu_raise(void)
6750 struct drm_i915_private
*dev_priv
;
6753 spin_lock_irq(&mchdev_lock
);
6754 if (!i915_mch_dev
) {
6758 dev_priv
= i915_mch_dev
;
6760 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
6761 dev_priv
->ips
.max_delay
--;
6764 spin_unlock_irq(&mchdev_lock
);
6768 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
6771 * i915_gpu_lower - lower GPU frequency limit
6773 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6774 * frequency maximum.
6776 bool i915_gpu_lower(void)
6778 struct drm_i915_private
*dev_priv
;
6781 spin_lock_irq(&mchdev_lock
);
6782 if (!i915_mch_dev
) {
6786 dev_priv
= i915_mch_dev
;
6788 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
6789 dev_priv
->ips
.max_delay
++;
6792 spin_unlock_irq(&mchdev_lock
);
6796 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
6799 * i915_gpu_busy - indicate GPU business to IPS
6801 * Tell the IPS driver whether or not the GPU is busy.
6803 bool i915_gpu_busy(void)
6807 spin_lock_irq(&mchdev_lock
);
6809 ret
= i915_mch_dev
->gt
.awake
;
6810 spin_unlock_irq(&mchdev_lock
);
6814 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
6817 * i915_gpu_turbo_disable - disable graphics turbo
6819 * Disable graphics turbo by resetting the max frequency and setting the
6820 * current frequency to the default.
6822 bool i915_gpu_turbo_disable(void)
6824 struct drm_i915_private
*dev_priv
;
6827 spin_lock_irq(&mchdev_lock
);
6828 if (!i915_mch_dev
) {
6832 dev_priv
= i915_mch_dev
;
6834 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
6836 if (!ironlake_set_drps(dev_priv
, dev_priv
->ips
.fstart
))
6840 spin_unlock_irq(&mchdev_lock
);
6844 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
6847 * Tells the intel_ips driver that the i915 driver is now loaded, if
6848 * IPS got loaded first.
6850 * This awkward dance is so that neither module has to depend on the
6851 * other in order for IPS to do the appropriate communication of
6852 * GPU turbo limits to i915.
6855 ips_ping_for_i915_load(void)
6859 link
= symbol_get(ips_link_to_i915_driver
);
6862 symbol_put(ips_link_to_i915_driver
);
6866 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
6868 /* We only register the i915 ips part with intel-ips once everything is
6869 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6870 spin_lock_irq(&mchdev_lock
);
6871 i915_mch_dev
= dev_priv
;
6872 spin_unlock_irq(&mchdev_lock
);
6874 ips_ping_for_i915_load();
6877 void intel_gpu_ips_teardown(void)
6879 spin_lock_irq(&mchdev_lock
);
6880 i915_mch_dev
= NULL
;
6881 spin_unlock_irq(&mchdev_lock
);
6884 static void intel_init_emon(struct drm_i915_private
*dev_priv
)
6890 /* Disable to program */
6894 /* Program energy weights for various events */
6895 I915_WRITE(SDEW
, 0x15040d00);
6896 I915_WRITE(CSIEW0
, 0x007f0000);
6897 I915_WRITE(CSIEW1
, 0x1e220004);
6898 I915_WRITE(CSIEW2
, 0x04000004);
6900 for (i
= 0; i
< 5; i
++)
6901 I915_WRITE(PEW(i
), 0);
6902 for (i
= 0; i
< 3; i
++)
6903 I915_WRITE(DEW(i
), 0);
6905 /* Program P-state weights to account for frequency power adjustment */
6906 for (i
= 0; i
< 16; i
++) {
6907 u32 pxvidfreq
= I915_READ(PXVFREQ(i
));
6908 unsigned long freq
= intel_pxfreq(pxvidfreq
);
6909 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
6914 val
*= (freq
/ 1000);
6916 val
/= (127*127*900);
6918 DRM_ERROR("bad pxval: %ld\n", val
);
6921 /* Render standby states get 0 weight */
6925 for (i
= 0; i
< 4; i
++) {
6926 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
6927 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
6928 I915_WRITE(PXW(i
), val
);
6931 /* Adjust magic regs to magic values (more experimental results) */
6932 I915_WRITE(OGW0
, 0);
6933 I915_WRITE(OGW1
, 0);
6934 I915_WRITE(EG0
, 0x00007f00);
6935 I915_WRITE(EG1
, 0x0000000e);
6936 I915_WRITE(EG2
, 0x000e0000);
6937 I915_WRITE(EG3
, 0x68000300);
6938 I915_WRITE(EG4
, 0x42000000);
6939 I915_WRITE(EG5
, 0x00140031);
6943 for (i
= 0; i
< 8; i
++)
6944 I915_WRITE(PXWL(i
), 0);
6946 /* Enable PMON + select events */
6947 I915_WRITE(ECR
, 0x80000019);
6949 lcfuse
= I915_READ(LCFUSE02
);
6951 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
6954 void intel_init_gt_powersave(struct drm_i915_private
*dev_priv
)
6957 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6960 if (!i915
.enable_rc6
) {
6961 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6962 intel_runtime_pm_get(dev_priv
);
6965 mutex_lock(&dev_priv
->drm
.struct_mutex
);
6966 mutex_lock(&dev_priv
->rps
.hw_lock
);
6968 /* Initialize RPS limits (for userspace) */
6969 if (IS_CHERRYVIEW(dev_priv
))
6970 cherryview_init_gt_powersave(dev_priv
);
6971 else if (IS_VALLEYVIEW(dev_priv
))
6972 valleyview_init_gt_powersave(dev_priv
);
6973 else if (INTEL_GEN(dev_priv
) >= 6)
6974 gen6_init_rps_frequencies(dev_priv
);
6976 /* Derive initial user preferences/limits from the hardware limits */
6977 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
6978 dev_priv
->rps
.cur_freq
= dev_priv
->rps
.idle_freq
;
6980 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
6981 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
6983 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
6984 dev_priv
->rps
.min_freq_softlimit
=
6986 dev_priv
->rps
.efficient_freq
,
6987 intel_freq_opcode(dev_priv
, 450));
6989 /* After setting max-softlimit, find the overclock max freq */
6990 if (IS_GEN6(dev_priv
) ||
6991 IS_IVYBRIDGE(dev_priv
) || IS_HASWELL(dev_priv
)) {
6994 sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, ¶ms
);
6995 if (params
& BIT(31)) { /* OC supported */
6996 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6997 (dev_priv
->rps
.max_freq
& 0xff) * 50,
6998 (params
& 0xff) * 50);
6999 dev_priv
->rps
.max_freq
= params
& 0xff;
7003 /* Finally allow us to boost to max by default */
7004 dev_priv
->rps
.boost_freq
= dev_priv
->rps
.max_freq
;
7006 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7007 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
7009 intel_autoenable_gt_powersave(dev_priv
);
7012 void intel_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
)
7014 if (IS_VALLEYVIEW(dev_priv
))
7015 valleyview_cleanup_gt_powersave(dev_priv
);
7017 if (!i915
.enable_rc6
)
7018 intel_runtime_pm_put(dev_priv
);
7022 * intel_suspend_gt_powersave - suspend PM work and helper threads
7023 * @dev_priv: i915 device
7025 * We don't want to disable RC6 or other features here, we just want
7026 * to make sure any work we've queued has finished and won't bother
7027 * us while we're suspended.
7029 void intel_suspend_gt_powersave(struct drm_i915_private
*dev_priv
)
7031 if (INTEL_GEN(dev_priv
) < 6)
7034 if (cancel_delayed_work_sync(&dev_priv
->rps
.autoenable_work
))
7035 intel_runtime_pm_put(dev_priv
);
7037 /* gen6_rps_idle() will be called later to disable interrupts */
7040 void intel_sanitize_gt_powersave(struct drm_i915_private
*dev_priv
)
7042 dev_priv
->rps
.enabled
= true; /* force disabling */
7043 intel_disable_gt_powersave(dev_priv
);
7045 gen6_reset_rps_interrupts(dev_priv
);
7048 void intel_disable_gt_powersave(struct drm_i915_private
*dev_priv
)
7050 if (!READ_ONCE(dev_priv
->rps
.enabled
))
7053 mutex_lock(&dev_priv
->rps
.hw_lock
);
7055 if (INTEL_GEN(dev_priv
) >= 9) {
7056 gen9_disable_rc6(dev_priv
);
7057 gen9_disable_rps(dev_priv
);
7058 } else if (IS_CHERRYVIEW(dev_priv
)) {
7059 cherryview_disable_rps(dev_priv
);
7060 } else if (IS_VALLEYVIEW(dev_priv
)) {
7061 valleyview_disable_rps(dev_priv
);
7062 } else if (INTEL_GEN(dev_priv
) >= 6) {
7063 gen6_disable_rps(dev_priv
);
7064 } else if (IS_IRONLAKE_M(dev_priv
)) {
7065 ironlake_disable_drps(dev_priv
);
7068 dev_priv
->rps
.enabled
= false;
7069 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7072 void intel_enable_gt_powersave(struct drm_i915_private
*dev_priv
)
7074 /* We shouldn't be disabling as we submit, so this should be less
7075 * racy than it appears!
7077 if (READ_ONCE(dev_priv
->rps
.enabled
))
7080 /* Powersaving is controlled by the host when inside a VM */
7081 if (intel_vgpu_active(dev_priv
))
7084 mutex_lock(&dev_priv
->rps
.hw_lock
);
7086 if (IS_CHERRYVIEW(dev_priv
)) {
7087 cherryview_enable_rps(dev_priv
);
7088 } else if (IS_VALLEYVIEW(dev_priv
)) {
7089 valleyview_enable_rps(dev_priv
);
7090 } else if (INTEL_GEN(dev_priv
) >= 9) {
7091 gen9_enable_rc6(dev_priv
);
7092 gen9_enable_rps(dev_priv
);
7093 if (IS_GEN9_BC(dev_priv
))
7094 gen6_update_ring_freq(dev_priv
);
7095 } else if (IS_BROADWELL(dev_priv
)) {
7096 gen8_enable_rps(dev_priv
);
7097 gen6_update_ring_freq(dev_priv
);
7098 } else if (INTEL_GEN(dev_priv
) >= 6) {
7099 gen6_enable_rps(dev_priv
);
7100 gen6_update_ring_freq(dev_priv
);
7101 } else if (IS_IRONLAKE_M(dev_priv
)) {
7102 ironlake_enable_drps(dev_priv
);
7103 intel_init_emon(dev_priv
);
7106 WARN_ON(dev_priv
->rps
.max_freq
< dev_priv
->rps
.min_freq
);
7107 WARN_ON(dev_priv
->rps
.idle_freq
> dev_priv
->rps
.max_freq
);
7109 WARN_ON(dev_priv
->rps
.efficient_freq
< dev_priv
->rps
.min_freq
);
7110 WARN_ON(dev_priv
->rps
.efficient_freq
> dev_priv
->rps
.max_freq
);
7112 dev_priv
->rps
.enabled
= true;
7113 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7116 static void __intel_autoenable_gt_powersave(struct work_struct
*work
)
7118 struct drm_i915_private
*dev_priv
=
7119 container_of(work
, typeof(*dev_priv
), rps
.autoenable_work
.work
);
7120 struct intel_engine_cs
*rcs
;
7121 struct drm_i915_gem_request
*req
;
7123 if (READ_ONCE(dev_priv
->rps
.enabled
))
7126 rcs
= dev_priv
->engine
[RCS
];
7127 if (rcs
->last_retired_context
)
7130 if (!rcs
->init_context
)
7133 mutex_lock(&dev_priv
->drm
.struct_mutex
);
7135 req
= i915_gem_request_alloc(rcs
, dev_priv
->kernel_context
);
7139 if (!i915
.enable_execlists
&& i915_switch_context(req
) == 0)
7140 rcs
->init_context(req
);
7142 /* Mark the device busy, calling intel_enable_gt_powersave() */
7143 i915_add_request(req
);
7146 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
7148 intel_runtime_pm_put(dev_priv
);
7151 void intel_autoenable_gt_powersave(struct drm_i915_private
*dev_priv
)
7153 if (READ_ONCE(dev_priv
->rps
.enabled
))
7156 if (IS_IRONLAKE_M(dev_priv
)) {
7157 ironlake_enable_drps(dev_priv
);
7158 intel_init_emon(dev_priv
);
7159 } else if (INTEL_INFO(dev_priv
)->gen
>= 6) {
7161 * PCU communication is slow and this doesn't need to be
7162 * done at any specific time, so do this out of our fast path
7163 * to make resume and init faster.
7165 * We depend on the HW RC6 power context save/restore
7166 * mechanism when entering D3 through runtime PM suspend. So
7167 * disable RPM until RPS/RC6 is properly setup. We can only
7168 * get here via the driver load/system resume/runtime resume
7169 * paths, so the _noresume version is enough (and in case of
7170 * runtime resume it's necessary).
7172 if (queue_delayed_work(dev_priv
->wq
,
7173 &dev_priv
->rps
.autoenable_work
,
7174 round_jiffies_up_relative(HZ
)))
7175 intel_runtime_pm_get_noresume(dev_priv
);
7179 static void ibx_init_clock_gating(struct drm_i915_private
*dev_priv
)
7182 * On Ibex Peak and Cougar Point, we need to disable clock
7183 * gating for the panel power sequencer or it will fail to
7184 * start up when no ports are active.
7186 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
7189 static void g4x_disable_trickle_feed(struct drm_i915_private
*dev_priv
)
7193 for_each_pipe(dev_priv
, pipe
) {
7194 I915_WRITE(DSPCNTR(pipe
),
7195 I915_READ(DSPCNTR(pipe
)) |
7196 DISPPLANE_TRICKLE_FEED_DISABLE
);
7198 I915_WRITE(DSPSURF(pipe
), I915_READ(DSPSURF(pipe
)));
7199 POSTING_READ(DSPSURF(pipe
));
7203 static void ilk_init_lp_watermarks(struct drm_i915_private
*dev_priv
)
7205 I915_WRITE(WM3_LP_ILK
, I915_READ(WM3_LP_ILK
) & ~WM1_LP_SR_EN
);
7206 I915_WRITE(WM2_LP_ILK
, I915_READ(WM2_LP_ILK
) & ~WM1_LP_SR_EN
);
7207 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
7210 * Don't touch WM1S_LP_EN here.
7211 * Doing so could cause underruns.
7215 static void ironlake_init_clock_gating(struct drm_i915_private
*dev_priv
)
7217 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
7221 * WaFbcDisableDpfcClockGating:ilk
7223 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
7224 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
7225 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
7227 I915_WRITE(PCH_3DCGDIS0
,
7228 MARIUNIT_CLOCK_GATE_DISABLE
|
7229 SVSMUNIT_CLOCK_GATE_DISABLE
);
7230 I915_WRITE(PCH_3DCGDIS1
,
7231 VFMUNIT_CLOCK_GATE_DISABLE
);
7234 * According to the spec the following bits should be set in
7235 * order to enable memory self-refresh
7236 * The bit 22/21 of 0x42004
7237 * The bit 5 of 0x42020
7238 * The bit 15 of 0x45000
7240 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7241 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
7242 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
7243 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
7244 I915_WRITE(DISP_ARB_CTL
,
7245 (I915_READ(DISP_ARB_CTL
) |
7248 ilk_init_lp_watermarks(dev_priv
);
7251 * Based on the document from hardware guys the following bits
7252 * should be set unconditionally in order to enable FBC.
7253 * The bit 22 of 0x42000
7254 * The bit 22 of 0x42004
7255 * The bit 7,8,9 of 0x42020.
7257 if (IS_IRONLAKE_M(dev_priv
)) {
7258 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
7259 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
7260 I915_READ(ILK_DISPLAY_CHICKEN1
) |
7262 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7263 I915_READ(ILK_DISPLAY_CHICKEN2
) |
7267 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
7269 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7270 I915_READ(ILK_DISPLAY_CHICKEN2
) |
7271 ILK_ELPIN_409_SELECT
);
7272 I915_WRITE(_3D_CHICKEN2
,
7273 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
7274 _3D_CHICKEN2_WM_READ_PIPELINED
);
7276 /* WaDisableRenderCachePipelinedFlush:ilk */
7277 I915_WRITE(CACHE_MODE_0
,
7278 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
7280 /* WaDisable_RenderCache_OperationalFlush:ilk */
7281 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7283 g4x_disable_trickle_feed(dev_priv
);
7285 ibx_init_clock_gating(dev_priv
);
7288 static void cpt_init_clock_gating(struct drm_i915_private
*dev_priv
)
7294 * On Ibex Peak and Cougar Point, we need to disable clock
7295 * gating for the panel power sequencer or it will fail to
7296 * start up when no ports are active.
7298 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
7299 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
7300 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
7301 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
7302 DPLS_EDP_PPS_FIX_DIS
);
7303 /* The below fixes the weird display corruption, a few pixels shifted
7304 * downward, on (only) LVDS of some HP laptops with IVY.
7306 for_each_pipe(dev_priv
, pipe
) {
7307 val
= I915_READ(TRANS_CHICKEN2(pipe
));
7308 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
7309 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
7310 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
7311 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
7312 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
7313 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
7314 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
7315 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
7317 /* WADP0ClockGatingDisable */
7318 for_each_pipe(dev_priv
, pipe
) {
7319 I915_WRITE(TRANS_CHICKEN1(pipe
),
7320 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
7324 static void gen6_check_mch_setup(struct drm_i915_private
*dev_priv
)
7328 tmp
= I915_READ(MCH_SSKPD
);
7329 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
)
7330 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7334 static void gen6_init_clock_gating(struct drm_i915_private
*dev_priv
)
7336 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
7338 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
7340 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7341 I915_READ(ILK_DISPLAY_CHICKEN2
) |
7342 ILK_ELPIN_409_SELECT
);
7344 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
7345 I915_WRITE(_3D_CHICKEN
,
7346 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
7348 /* WaDisable_RenderCache_OperationalFlush:snb */
7349 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7352 * BSpec recoomends 8x4 when MSAA is used,
7353 * however in practice 16x4 seems fastest.
7355 * Note that PS/WM thread counts depend on the WIZ hashing
7356 * disable bit, which we don't touch here, but it's good
7357 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7359 I915_WRITE(GEN6_GT_MODE
,
7360 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
7362 ilk_init_lp_watermarks(dev_priv
);
7364 I915_WRITE(CACHE_MODE_0
,
7365 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
7367 I915_WRITE(GEN6_UCGCTL1
,
7368 I915_READ(GEN6_UCGCTL1
) |
7369 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
7370 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
7372 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7373 * gating disable must be set. Failure to set it results in
7374 * flickering pixels due to Z write ordering failures after
7375 * some amount of runtime in the Mesa "fire" demo, and Unigine
7376 * Sanctuary and Tropics, and apparently anything else with
7377 * alpha test or pixel discard.
7379 * According to the spec, bit 11 (RCCUNIT) must also be set,
7380 * but we didn't debug actual testcases to find it out.
7382 * WaDisableRCCUnitClockGating:snb
7383 * WaDisableRCPBUnitClockGating:snb
7385 I915_WRITE(GEN6_UCGCTL2
,
7386 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
7387 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
7389 /* WaStripsFansDisableFastClipPerformanceFix:snb */
7390 I915_WRITE(_3D_CHICKEN3
,
7391 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
));
7395 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7396 * 3DSTATE_SF number of SF output attributes is more than 16."
7398 I915_WRITE(_3D_CHICKEN3
,
7399 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH
));
7402 * According to the spec the following bits should be
7403 * set in order to enable memory self-refresh and fbc:
7404 * The bit21 and bit22 of 0x42000
7405 * The bit21 and bit22 of 0x42004
7406 * The bit5 and bit7 of 0x42020
7407 * The bit14 of 0x70180
7408 * The bit14 of 0x71180
7410 * WaFbcAsynchFlipDisableFbcQueue:snb
7412 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
7413 I915_READ(ILK_DISPLAY_CHICKEN1
) |
7414 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
7415 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7416 I915_READ(ILK_DISPLAY_CHICKEN2
) |
7417 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
7418 I915_WRITE(ILK_DSPCLK_GATE_D
,
7419 I915_READ(ILK_DSPCLK_GATE_D
) |
7420 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
7421 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
7423 g4x_disable_trickle_feed(dev_priv
);
7425 cpt_init_clock_gating(dev_priv
);
7427 gen6_check_mch_setup(dev_priv
);
7430 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
7432 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
7435 * WaVSThreadDispatchOverride:ivb,vlv
7437 * This actually overrides the dispatch
7438 * mode for all thread types.
7440 reg
&= ~GEN7_FF_SCHED_MASK
;
7441 reg
|= GEN7_FF_TS_SCHED_HW
;
7442 reg
|= GEN7_FF_VS_SCHED_HW
;
7443 reg
|= GEN7_FF_DS_SCHED_HW
;
7445 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
7448 static void lpt_init_clock_gating(struct drm_i915_private
*dev_priv
)
7451 * TODO: this bit should only be enabled when really needed, then
7452 * disabled when not needed anymore in order to save power.
7454 if (HAS_PCH_LPT_LP(dev_priv
))
7455 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
7456 I915_READ(SOUTH_DSPCLK_GATE_D
) |
7457 PCH_LP_PARTITION_LEVEL_DISABLE
);
7459 /* WADPOClockGatingDisable:hsw */
7460 I915_WRITE(TRANS_CHICKEN1(PIPE_A
),
7461 I915_READ(TRANS_CHICKEN1(PIPE_A
)) |
7462 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
7465 static void lpt_suspend_hw(struct drm_i915_private
*dev_priv
)
7467 if (HAS_PCH_LPT_LP(dev_priv
)) {
7468 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7470 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
7471 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7475 static void gen8_set_l3sqc_credits(struct drm_i915_private
*dev_priv
,
7476 int general_prio_credits
,
7477 int high_prio_credits
)
7481 /* WaTempDisableDOPClkGating:bdw */
7482 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
7483 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
7485 I915_WRITE(GEN8_L3SQCREG1
,
7486 L3_GENERAL_PRIO_CREDITS(general_prio_credits
) |
7487 L3_HIGH_PRIO_CREDITS(high_prio_credits
));
7490 * Wait at least 100 clocks before re-enabling clock gating.
7491 * See the definition of L3SQCREG1 in BSpec.
7493 POSTING_READ(GEN8_L3SQCREG1
);
7495 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
7498 static void kabylake_init_clock_gating(struct drm_i915_private
*dev_priv
)
7500 gen9_init_clock_gating(dev_priv
);
7502 /* WaDisableSDEUnitClockGating:kbl */
7503 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
7504 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
7505 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
7507 /* WaDisableGamClockGating:kbl */
7508 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
7509 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
7510 GEN6_GAMUNIT_CLOCK_GATE_DISABLE
);
7512 /* WaFbcNukeOnHostModify:kbl */
7513 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
7514 ILK_DPFC_NUKE_ON_ANY_MODIFICATION
);
7517 static void skylake_init_clock_gating(struct drm_i915_private
*dev_priv
)
7519 gen9_init_clock_gating(dev_priv
);
7521 /* WAC6entrylatency:skl */
7522 I915_WRITE(FBC_LLC_READ_CTRL
, I915_READ(FBC_LLC_READ_CTRL
) |
7523 FBC_LLC_FULLY_OPEN
);
7525 /* WaFbcNukeOnHostModify:skl */
7526 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
7527 ILK_DPFC_NUKE_ON_ANY_MODIFICATION
);
7530 static void broadwell_init_clock_gating(struct drm_i915_private
*dev_priv
)
7534 ilk_init_lp_watermarks(dev_priv
);
7536 /* WaSwitchSolVfFArbitrationPriority:bdw */
7537 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
7539 /* WaPsrDPAMaskVBlankInSRD:bdw */
7540 I915_WRITE(CHICKEN_PAR1_1
,
7541 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
7543 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7544 for_each_pipe(dev_priv
, pipe
) {
7545 I915_WRITE(CHICKEN_PIPESL_1(pipe
),
7546 I915_READ(CHICKEN_PIPESL_1(pipe
)) |
7547 BDW_DPRS_MASK_VBLANK_SRD
);
7550 /* WaVSRefCountFullforceMissDisable:bdw */
7551 /* WaDSRefCountFullforceMissDisable:bdw */
7552 I915_WRITE(GEN7_FF_THREAD_MODE
,
7553 I915_READ(GEN7_FF_THREAD_MODE
) &
7554 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
7556 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
7557 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
7559 /* WaDisableSDEUnitClockGating:bdw */
7560 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
7561 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
7563 /* WaProgramL3SqcReg1Default:bdw */
7564 gen8_set_l3sqc_credits(dev_priv
, 30, 2);
7567 * WaGttCachingOffByDefault:bdw
7568 * GTT cache may not work with big pages, so if those
7569 * are ever enabled GTT cache may need to be disabled.
7571 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
7573 /* WaKVMNotificationOnConfigChange:bdw */
7574 I915_WRITE(CHICKEN_PAR2_1
, I915_READ(CHICKEN_PAR2_1
)
7575 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT
);
7577 lpt_init_clock_gating(dev_priv
);
7579 /* WaDisableDopClockGating:bdw
7581 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
7584 I915_WRITE(GEN6_UCGCTL1
,
7585 I915_READ(GEN6_UCGCTL1
) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE
);
7588 static void haswell_init_clock_gating(struct drm_i915_private
*dev_priv
)
7590 ilk_init_lp_watermarks(dev_priv
);
7592 /* L3 caching of data atomics doesn't work -- disable it. */
7593 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
7594 I915_WRITE(HSW_ROW_CHICKEN3
,
7595 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
7597 /* This is required by WaCatErrorRejectionIssue:hsw */
7598 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
7599 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
7600 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
7602 /* WaVSRefCountFullforceMissDisable:hsw */
7603 I915_WRITE(GEN7_FF_THREAD_MODE
,
7604 I915_READ(GEN7_FF_THREAD_MODE
) & ~GEN7_FF_VS_REF_CNT_FFME
);
7606 /* WaDisable_RenderCache_OperationalFlush:hsw */
7607 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7609 /* enable HiZ Raw Stall Optimization */
7610 I915_WRITE(CACHE_MODE_0_GEN7
,
7611 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
7613 /* WaDisable4x2SubspanOptimization:hsw */
7614 I915_WRITE(CACHE_MODE_1
,
7615 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
7618 * BSpec recommends 8x4 when MSAA is used,
7619 * however in practice 16x4 seems fastest.
7621 * Note that PS/WM thread counts depend on the WIZ hashing
7622 * disable bit, which we don't touch here, but it's good
7623 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7625 I915_WRITE(GEN7_GT_MODE
,
7626 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
7628 /* WaSampleCChickenBitEnable:hsw */
7629 I915_WRITE(HALF_SLICE_CHICKEN3
,
7630 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE
));
7632 /* WaSwitchSolVfFArbitrationPriority:hsw */
7633 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
7635 /* WaRsPkgCStateDisplayPMReq:hsw */
7636 I915_WRITE(CHICKEN_PAR1_1
,
7637 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
7639 lpt_init_clock_gating(dev_priv
);
7642 static void ivybridge_init_clock_gating(struct drm_i915_private
*dev_priv
)
7646 ilk_init_lp_watermarks(dev_priv
);
7648 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
7650 /* WaDisableEarlyCull:ivb */
7651 I915_WRITE(_3D_CHICKEN3
,
7652 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
7654 /* WaDisableBackToBackFlipFix:ivb */
7655 I915_WRITE(IVB_CHICKEN3
,
7656 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
7657 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
7659 /* WaDisablePSDDualDispatchEnable:ivb */
7660 if (IS_IVB_GT1(dev_priv
))
7661 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
7662 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
7664 /* WaDisable_RenderCache_OperationalFlush:ivb */
7665 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7667 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7668 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
7669 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
7671 /* WaApplyL3ControlAndL3ChickenMode:ivb */
7672 I915_WRITE(GEN7_L3CNTLREG1
,
7673 GEN7_WA_FOR_GEN7_L3_CONTROL
);
7674 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
7675 GEN7_WA_L3_CHICKEN_MODE
);
7676 if (IS_IVB_GT1(dev_priv
))
7677 I915_WRITE(GEN7_ROW_CHICKEN2
,
7678 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
7680 /* must write both registers */
7681 I915_WRITE(GEN7_ROW_CHICKEN2
,
7682 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
7683 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
7684 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
7687 /* WaForceL3Serialization:ivb */
7688 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
7689 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
7692 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7693 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7695 I915_WRITE(GEN6_UCGCTL2
,
7696 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
7698 /* This is required by WaCatErrorRejectionIssue:ivb */
7699 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
7700 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
7701 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
7703 g4x_disable_trickle_feed(dev_priv
);
7705 gen7_setup_fixed_func_scheduler(dev_priv
);
7707 if (0) { /* causes HiZ corruption on ivb:gt1 */
7708 /* enable HiZ Raw Stall Optimization */
7709 I915_WRITE(CACHE_MODE_0_GEN7
,
7710 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
7713 /* WaDisable4x2SubspanOptimization:ivb */
7714 I915_WRITE(CACHE_MODE_1
,
7715 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
7718 * BSpec recommends 8x4 when MSAA is used,
7719 * however in practice 16x4 seems fastest.
7721 * Note that PS/WM thread counts depend on the WIZ hashing
7722 * disable bit, which we don't touch here, but it's good
7723 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7725 I915_WRITE(GEN7_GT_MODE
,
7726 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
7728 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
7729 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
7730 snpcr
|= GEN6_MBC_SNPCR_MED
;
7731 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
7733 if (!HAS_PCH_NOP(dev_priv
))
7734 cpt_init_clock_gating(dev_priv
);
7736 gen6_check_mch_setup(dev_priv
);
7739 static void valleyview_init_clock_gating(struct drm_i915_private
*dev_priv
)
7741 /* WaDisableEarlyCull:vlv */
7742 I915_WRITE(_3D_CHICKEN3
,
7743 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
7745 /* WaDisableBackToBackFlipFix:vlv */
7746 I915_WRITE(IVB_CHICKEN3
,
7747 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
7748 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
7750 /* WaPsdDispatchEnable:vlv */
7751 /* WaDisablePSDDualDispatchEnable:vlv */
7752 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
7753 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
7754 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
7756 /* WaDisable_RenderCache_OperationalFlush:vlv */
7757 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7759 /* WaForceL3Serialization:vlv */
7760 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
7761 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
7763 /* WaDisableDopClockGating:vlv */
7764 I915_WRITE(GEN7_ROW_CHICKEN2
,
7765 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
7767 /* This is required by WaCatErrorRejectionIssue:vlv */
7768 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
7769 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
7770 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
7772 gen7_setup_fixed_func_scheduler(dev_priv
);
7775 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7776 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7778 I915_WRITE(GEN6_UCGCTL2
,
7779 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
7781 /* WaDisableL3Bank2xClockGate:vlv
7782 * Disabling L3 clock gating- MMIO 940c[25] = 1
7783 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7784 I915_WRITE(GEN7_UCGCTL4
,
7785 I915_READ(GEN7_UCGCTL4
) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
7788 * BSpec says this must be set, even though
7789 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7791 I915_WRITE(CACHE_MODE_1
,
7792 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
7795 * BSpec recommends 8x4 when MSAA is used,
7796 * however in practice 16x4 seems fastest.
7798 * Note that PS/WM thread counts depend on the WIZ hashing
7799 * disable bit, which we don't touch here, but it's good
7800 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7802 I915_WRITE(GEN7_GT_MODE
,
7803 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
7806 * WaIncreaseL3CreditsForVLVB0:vlv
7807 * This is the hardware default actually.
7809 I915_WRITE(GEN7_L3SQCREG1
, VLV_B0_WA_L3SQCREG1_VALUE
);
7812 * WaDisableVLVClockGating_VBIIssue:vlv
7813 * Disable clock gating on th GCFG unit to prevent a delay
7814 * in the reporting of vblank events.
7816 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, GCFG_DIS
);
7819 static void cherryview_init_clock_gating(struct drm_i915_private
*dev_priv
)
7821 /* WaVSRefCountFullforceMissDisable:chv */
7822 /* WaDSRefCountFullforceMissDisable:chv */
7823 I915_WRITE(GEN7_FF_THREAD_MODE
,
7824 I915_READ(GEN7_FF_THREAD_MODE
) &
7825 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
7827 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7828 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
7829 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
7831 /* WaDisableCSUnitClockGating:chv */
7832 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
7833 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
7835 /* WaDisableSDEUnitClockGating:chv */
7836 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
7837 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
7840 * WaProgramL3SqcReg1Default:chv
7841 * See gfxspecs/Related Documents/Performance Guide/
7842 * LSQC Setting Recommendations.
7844 gen8_set_l3sqc_credits(dev_priv
, 38, 2);
7847 * GTT cache may not work with big pages, so if those
7848 * are ever enabled GTT cache may need to be disabled.
7850 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
7853 static void g4x_init_clock_gating(struct drm_i915_private
*dev_priv
)
7855 uint32_t dspclk_gate
;
7857 I915_WRITE(RENCLK_GATE_D1
, 0);
7858 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
7859 GS_UNIT_CLOCK_GATE_DISABLE
|
7860 CL_UNIT_CLOCK_GATE_DISABLE
);
7861 I915_WRITE(RAMCLK_GATE_D
, 0);
7862 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
7863 OVRUNIT_CLOCK_GATE_DISABLE
|
7864 OVCUNIT_CLOCK_GATE_DISABLE
;
7865 if (IS_GM45(dev_priv
))
7866 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
7867 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
7869 /* WaDisableRenderCachePipelinedFlush */
7870 I915_WRITE(CACHE_MODE_0
,
7871 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
7873 /* WaDisable_RenderCache_OperationalFlush:g4x */
7874 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7876 g4x_disable_trickle_feed(dev_priv
);
7879 static void crestline_init_clock_gating(struct drm_i915_private
*dev_priv
)
7881 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
7882 I915_WRITE(RENCLK_GATE_D2
, 0);
7883 I915_WRITE(DSPCLK_GATE_D
, 0);
7884 I915_WRITE(RAMCLK_GATE_D
, 0);
7885 I915_WRITE16(DEUC
, 0);
7886 I915_WRITE(MI_ARB_STATE
,
7887 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
7889 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7890 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7893 static void broadwater_init_clock_gating(struct drm_i915_private
*dev_priv
)
7895 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
7896 I965_RCC_CLOCK_GATE_DISABLE
|
7897 I965_RCPB_CLOCK_GATE_DISABLE
|
7898 I965_ISC_CLOCK_GATE_DISABLE
|
7899 I965_FBC_CLOCK_GATE_DISABLE
);
7900 I915_WRITE(RENCLK_GATE_D2
, 0);
7901 I915_WRITE(MI_ARB_STATE
,
7902 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
7904 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7905 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7908 static void gen3_init_clock_gating(struct drm_i915_private
*dev_priv
)
7910 u32 dstate
= I915_READ(D_STATE
);
7912 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
7913 DSTATE_DOT_CLOCK_GATING
;
7914 I915_WRITE(D_STATE
, dstate
);
7916 if (IS_PINEVIEW(dev_priv
))
7917 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
7919 /* IIR "flip pending" means done if this bit is set */
7920 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
7922 /* interrupts should cause a wake up from C3 */
7923 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN
));
7925 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7926 I915_WRITE(MI_ARB_STATE
, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
7928 I915_WRITE(MI_ARB_STATE
,
7929 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
7932 static void i85x_init_clock_gating(struct drm_i915_private
*dev_priv
)
7934 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
7936 /* interrupts should cause a wake up from C3 */
7937 I915_WRITE(MI_STATE
, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN
) |
7938 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE
));
7940 I915_WRITE(MEM_MODE
,
7941 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE
));
7944 static void i830_init_clock_gating(struct drm_i915_private
*dev_priv
)
7946 I915_WRITE(MEM_MODE
,
7947 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE
) |
7948 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE
));
7951 void intel_init_clock_gating(struct drm_i915_private
*dev_priv
)
7953 dev_priv
->display
.init_clock_gating(dev_priv
);
7956 void intel_suspend_hw(struct drm_i915_private
*dev_priv
)
7958 if (HAS_PCH_LPT(dev_priv
))
7959 lpt_suspend_hw(dev_priv
);
7962 static void nop_init_clock_gating(struct drm_i915_private
*dev_priv
)
7964 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7968 * intel_init_clock_gating_hooks - setup the clock gating hooks
7969 * @dev_priv: device private
7971 * Setup the hooks that configure which clocks of a given platform can be
7972 * gated and also apply various GT and display specific workarounds for these
7973 * platforms. Note that some GT specific workarounds are applied separately
7974 * when GPU contexts or batchbuffers start their execution.
7976 void intel_init_clock_gating_hooks(struct drm_i915_private
*dev_priv
)
7978 if (IS_SKYLAKE(dev_priv
))
7979 dev_priv
->display
.init_clock_gating
= skylake_init_clock_gating
;
7980 else if (IS_KABYLAKE(dev_priv
))
7981 dev_priv
->display
.init_clock_gating
= kabylake_init_clock_gating
;
7982 else if (IS_BROXTON(dev_priv
))
7983 dev_priv
->display
.init_clock_gating
= bxt_init_clock_gating
;
7984 else if (IS_GEMINILAKE(dev_priv
))
7985 dev_priv
->display
.init_clock_gating
= glk_init_clock_gating
;
7986 else if (IS_BROADWELL(dev_priv
))
7987 dev_priv
->display
.init_clock_gating
= broadwell_init_clock_gating
;
7988 else if (IS_CHERRYVIEW(dev_priv
))
7989 dev_priv
->display
.init_clock_gating
= cherryview_init_clock_gating
;
7990 else if (IS_HASWELL(dev_priv
))
7991 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
7992 else if (IS_IVYBRIDGE(dev_priv
))
7993 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
7994 else if (IS_VALLEYVIEW(dev_priv
))
7995 dev_priv
->display
.init_clock_gating
= valleyview_init_clock_gating
;
7996 else if (IS_GEN6(dev_priv
))
7997 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
7998 else if (IS_GEN5(dev_priv
))
7999 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
8000 else if (IS_G4X(dev_priv
))
8001 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
8002 else if (IS_I965GM(dev_priv
))
8003 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
8004 else if (IS_I965G(dev_priv
))
8005 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
8006 else if (IS_GEN3(dev_priv
))
8007 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
8008 else if (IS_I85X(dev_priv
) || IS_I865G(dev_priv
))
8009 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
8010 else if (IS_GEN2(dev_priv
))
8011 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
8013 MISSING_CASE(INTEL_DEVID(dev_priv
));
8014 dev_priv
->display
.init_clock_gating
= nop_init_clock_gating
;
8018 /* Set up chip specific power management-related functions */
8019 void intel_init_pm(struct drm_i915_private
*dev_priv
)
8021 intel_fbc_init(dev_priv
);
8024 if (IS_PINEVIEW(dev_priv
))
8025 i915_pineview_get_mem_freq(dev_priv
);
8026 else if (IS_GEN5(dev_priv
))
8027 i915_ironlake_get_mem_freq(dev_priv
);
8029 /* For FIFO watermark updates */
8030 if (INTEL_GEN(dev_priv
) >= 9) {
8031 skl_setup_wm_latency(dev_priv
);
8032 dev_priv
->display
.initial_watermarks
= skl_initial_wm
;
8033 dev_priv
->display
.atomic_update_watermarks
= skl_atomic_update_crtc_wm
;
8034 dev_priv
->display
.compute_global_watermarks
= skl_compute_wm
;
8035 } else if (HAS_PCH_SPLIT(dev_priv
)) {
8036 ilk_setup_wm_latency(dev_priv
);
8038 if ((IS_GEN5(dev_priv
) && dev_priv
->wm
.pri_latency
[1] &&
8039 dev_priv
->wm
.spr_latency
[1] && dev_priv
->wm
.cur_latency
[1]) ||
8040 (!IS_GEN5(dev_priv
) && dev_priv
->wm
.pri_latency
[0] &&
8041 dev_priv
->wm
.spr_latency
[0] && dev_priv
->wm
.cur_latency
[0])) {
8042 dev_priv
->display
.compute_pipe_wm
= ilk_compute_pipe_wm
;
8043 dev_priv
->display
.compute_intermediate_wm
=
8044 ilk_compute_intermediate_wm
;
8045 dev_priv
->display
.initial_watermarks
=
8046 ilk_initial_watermarks
;
8047 dev_priv
->display
.optimize_watermarks
=
8048 ilk_optimize_watermarks
;
8050 DRM_DEBUG_KMS("Failed to read display plane latency. "
8053 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
8054 vlv_setup_wm_latency(dev_priv
);
8055 dev_priv
->display
.compute_pipe_wm
= vlv_compute_pipe_wm
;
8056 dev_priv
->display
.compute_intermediate_wm
= vlv_compute_intermediate_wm
;
8057 dev_priv
->display
.initial_watermarks
= vlv_initial_watermarks
;
8058 dev_priv
->display
.optimize_watermarks
= vlv_optimize_watermarks
;
8059 dev_priv
->display
.atomic_update_watermarks
= vlv_atomic_update_fifo
;
8060 } else if (IS_PINEVIEW(dev_priv
)) {
8061 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv
),
8064 dev_priv
->mem_freq
)) {
8065 DRM_INFO("failed to find known CxSR latency "
8066 "(found ddr%s fsb freq %d, mem freq %d), "
8068 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
8069 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
8070 /* Disable CxSR and never update its watermark again */
8071 intel_set_memory_cxsr(dev_priv
, false);
8072 dev_priv
->display
.update_wm
= NULL
;
8074 dev_priv
->display
.update_wm
= pineview_update_wm
;
8075 } else if (IS_G4X(dev_priv
)) {
8076 dev_priv
->display
.update_wm
= g4x_update_wm
;
8077 } else if (IS_GEN4(dev_priv
)) {
8078 dev_priv
->display
.update_wm
= i965_update_wm
;
8079 } else if (IS_GEN3(dev_priv
)) {
8080 dev_priv
->display
.update_wm
= i9xx_update_wm
;
8081 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
8082 } else if (IS_GEN2(dev_priv
)) {
8083 if (INTEL_INFO(dev_priv
)->num_pipes
== 1) {
8084 dev_priv
->display
.update_wm
= i845_update_wm
;
8085 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
8087 dev_priv
->display
.update_wm
= i9xx_update_wm
;
8088 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
8091 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
8095 static inline int gen6_check_mailbox_status(struct drm_i915_private
*dev_priv
)
8098 I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_ERROR_MASK
;
8101 case GEN6_PCODE_SUCCESS
:
8103 case GEN6_PCODE_UNIMPLEMENTED_CMD
:
8104 case GEN6_PCODE_ILLEGAL_CMD
:
8106 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
:
8107 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
:
8109 case GEN6_PCODE_TIMEOUT
:
8112 MISSING_CASE(flags
);
8117 static inline int gen7_check_mailbox_status(struct drm_i915_private
*dev_priv
)
8120 I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_ERROR_MASK
;
8123 case GEN6_PCODE_SUCCESS
:
8125 case GEN6_PCODE_ILLEGAL_CMD
:
8127 case GEN7_PCODE_TIMEOUT
:
8129 case GEN7_PCODE_ILLEGAL_DATA
:
8131 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
:
8134 MISSING_CASE(flags
);
8139 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
)
8143 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
8145 /* GEN6_PCODE_* are outside of the forcewake domain, we can
8146 * use te fw I915_READ variants to reduce the amount of work
8147 * required when reading/writing.
8150 if (I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
8151 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
8155 I915_WRITE_FW(GEN6_PCODE_DATA
, *val
);
8156 I915_WRITE_FW(GEN6_PCODE_DATA1
, 0);
8157 I915_WRITE_FW(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
8159 if (intel_wait_for_register_fw(dev_priv
,
8160 GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
, 0,
8162 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
8166 *val
= I915_READ_FW(GEN6_PCODE_DATA
);
8167 I915_WRITE_FW(GEN6_PCODE_DATA
, 0);
8169 if (INTEL_GEN(dev_priv
) > 6)
8170 status
= gen7_check_mailbox_status(dev_priv
);
8172 status
= gen6_check_mailbox_status(dev_priv
);
8175 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
8183 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
,
8188 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
8190 /* GEN6_PCODE_* are outside of the forcewake domain, we can
8191 * use te fw I915_READ variants to reduce the amount of work
8192 * required when reading/writing.
8195 if (I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
8196 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
8200 I915_WRITE_FW(GEN6_PCODE_DATA
, val
);
8201 I915_WRITE_FW(GEN6_PCODE_DATA1
, 0);
8202 I915_WRITE_FW(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
8204 if (intel_wait_for_register_fw(dev_priv
,
8205 GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
, 0,
8207 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
8211 I915_WRITE_FW(GEN6_PCODE_DATA
, 0);
8213 if (INTEL_GEN(dev_priv
) > 6)
8214 status
= gen7_check_mailbox_status(dev_priv
);
8216 status
= gen6_check_mailbox_status(dev_priv
);
8219 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
8227 static bool skl_pcode_try_request(struct drm_i915_private
*dev_priv
, u32 mbox
,
8228 u32 request
, u32 reply_mask
, u32 reply
,
8233 *status
= sandybridge_pcode_read(dev_priv
, mbox
, &val
);
8235 return *status
|| ((val
& reply_mask
) == reply
);
8239 * skl_pcode_request - send PCODE request until acknowledgment
8240 * @dev_priv: device private
8241 * @mbox: PCODE mailbox ID the request is targeted for
8242 * @request: request ID
8243 * @reply_mask: mask used to check for request acknowledgment
8244 * @reply: value used to check for request acknowledgment
8245 * @timeout_base_ms: timeout for polling with preemption enabled
8247 * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
8248 * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
8249 * The request is acknowledged once the PCODE reply dword equals @reply after
8250 * applying @reply_mask. Polling is first attempted with preemption enabled
8251 * for @timeout_base_ms and if this times out for another 50 ms with
8252 * preemption disabled.
8254 * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
8255 * other error as reported by PCODE.
8257 int skl_pcode_request(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 request
,
8258 u32 reply_mask
, u32 reply
, int timeout_base_ms
)
8263 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
8265 #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
8269 * Prime the PCODE by doing a request first. Normally it guarantees
8270 * that a subsequent request, at most @timeout_base_ms later, succeeds.
8271 * _wait_for() doesn't guarantee when its passed condition is evaluated
8272 * first, so send the first request explicitly.
8278 ret
= _wait_for(COND
, timeout_base_ms
* 1000, 10);
8283 * The above can time out if the number of requests was low (2 in the
8284 * worst case) _and_ PCODE was busy for some reason even after a
8285 * (queued) request and @timeout_base_ms delay. As a workaround retry
8286 * the poll with preemption disabled to maximize the number of
8287 * requests. Increase the timeout from @timeout_base_ms to 50ms to
8288 * account for interrupts that could reduce the number of these
8289 * requests, and for any quirks of the PCODE firmware that delays
8290 * the request completion.
8292 DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
8293 WARN_ON_ONCE(timeout_base_ms
> 3);
8295 ret
= wait_for_atomic(COND
, 50);
8299 return ret
? ret
: status
;
8303 static int byt_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
8307 * Slow = Fast = GPLL ref * N
8309 return DIV_ROUND_CLOSEST(dev_priv
->rps
.gpll_ref_freq
* (val
- 0xb7), 1000);
8312 static int byt_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
8314 return DIV_ROUND_CLOSEST(1000 * val
, dev_priv
->rps
.gpll_ref_freq
) + 0xb7;
8317 static int chv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
8321 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
8323 return DIV_ROUND_CLOSEST(dev_priv
->rps
.gpll_ref_freq
* val
, 2 * 2 * 1000);
8326 static int chv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
8328 /* CHV needs even values */
8329 return DIV_ROUND_CLOSEST(2 * 1000 * val
, dev_priv
->rps
.gpll_ref_freq
) * 2;
8332 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
8334 if (IS_GEN9(dev_priv
))
8335 return DIV_ROUND_CLOSEST(val
* GT_FREQUENCY_MULTIPLIER
,
8337 else if (IS_CHERRYVIEW(dev_priv
))
8338 return chv_gpu_freq(dev_priv
, val
);
8339 else if (IS_VALLEYVIEW(dev_priv
))
8340 return byt_gpu_freq(dev_priv
, val
);
8342 return val
* GT_FREQUENCY_MULTIPLIER
;
8345 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
8347 if (IS_GEN9(dev_priv
))
8348 return DIV_ROUND_CLOSEST(val
* GEN9_FREQ_SCALER
,
8349 GT_FREQUENCY_MULTIPLIER
);
8350 else if (IS_CHERRYVIEW(dev_priv
))
8351 return chv_freq_opcode(dev_priv
, val
);
8352 else if (IS_VALLEYVIEW(dev_priv
))
8353 return byt_freq_opcode(dev_priv
, val
);
8355 return DIV_ROUND_CLOSEST(val
, GT_FREQUENCY_MULTIPLIER
);
8358 struct request_boost
{
8359 struct work_struct work
;
8360 struct drm_i915_gem_request
*req
;
8363 static void __intel_rps_boost_work(struct work_struct
*work
)
8365 struct request_boost
*boost
= container_of(work
, struct request_boost
, work
);
8366 struct drm_i915_gem_request
*req
= boost
->req
;
8368 if (!i915_gem_request_completed(req
))
8369 gen6_rps_boost(req
->i915
, NULL
, req
->emitted_jiffies
);
8371 i915_gem_request_put(req
);
8375 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request
*req
)
8377 struct request_boost
*boost
;
8379 if (req
== NULL
|| INTEL_GEN(req
->i915
) < 6)
8382 if (i915_gem_request_completed(req
))
8385 boost
= kmalloc(sizeof(*boost
), GFP_ATOMIC
);
8389 boost
->req
= i915_gem_request_get(req
);
8391 INIT_WORK(&boost
->work
, __intel_rps_boost_work
);
8392 queue_work(req
->i915
->wq
, &boost
->work
);
8395 void intel_pm_setup(struct drm_i915_private
*dev_priv
)
8397 mutex_init(&dev_priv
->rps
.hw_lock
);
8398 spin_lock_init(&dev_priv
->rps
.client_lock
);
8400 INIT_DELAYED_WORK(&dev_priv
->rps
.autoenable_work
,
8401 __intel_autoenable_gt_powersave
);
8402 INIT_LIST_HEAD(&dev_priv
->rps
.clients
);
8404 dev_priv
->pm
.suspended
= false;
8405 atomic_set(&dev_priv
->pm
.wakeref_count
, 0);
8408 static u64
vlv_residency_raw(struct drm_i915_private
*dev_priv
,
8409 const i915_reg_t reg
)
8411 u32 lower
, upper
, tmp
;
8414 /* The register accessed do not need forcewake. We borrow
8415 * uncore lock to prevent concurrent access to range reg.
8417 spin_lock_irq(&dev_priv
->uncore
.lock
);
8419 /* vlv and chv residency counters are 40 bits in width.
8420 * With a control bit, we can choose between upper or lower
8421 * 32bit window into this counter.
8423 * Although we always use the counter in high-range mode elsewhere,
8424 * userspace may attempt to read the value before rc6 is initialised,
8425 * before we have set the default VLV_COUNTER_CONTROL value. So always
8426 * set the high bit to be safe.
8428 I915_WRITE_FW(VLV_COUNTER_CONTROL
,
8429 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
));
8430 upper
= I915_READ_FW(reg
);
8434 I915_WRITE_FW(VLV_COUNTER_CONTROL
,
8435 _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH
));
8436 lower
= I915_READ_FW(reg
);
8438 I915_WRITE_FW(VLV_COUNTER_CONTROL
,
8439 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
));
8440 upper
= I915_READ_FW(reg
);
8441 } while (upper
!= tmp
&& --loop
);
8443 /* Everywhere else we always use VLV_COUNTER_CONTROL with the
8444 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
8448 spin_unlock_irq(&dev_priv
->uncore
.lock
);
8450 return lower
| (u64
)upper
<< 8;
8453 u64
intel_rc6_residency_us(struct drm_i915_private
*dev_priv
,
8454 const i915_reg_t reg
)
8456 u64 time_hw
, units
, div
;
8458 if (!intel_enable_rc6())
8461 intel_runtime_pm_get(dev_priv
);
8463 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
8464 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
8466 div
= dev_priv
->czclk_freq
;
8468 time_hw
= vlv_residency_raw(dev_priv
, reg
);
8469 } else if (IS_GEN9_LP(dev_priv
)) {
8471 div
= 1200; /* 833.33ns */
8473 time_hw
= I915_READ(reg
);
8475 units
= 128000; /* 1.28us */
8478 time_hw
= I915_READ(reg
);
8481 intel_runtime_pm_put(dev_priv
);
8482 return DIV_ROUND_UP_ULL(time_hw
* units
, div
);