2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
29 #include <drm/drm_plane_helper.h>
31 #include "intel_drv.h"
32 #include "../../../platform/x86/intel_ips.h"
33 #include <linux/module.h>
34 #include <drm/drm_atomic_helper.h>
39 * RC6 is a special power stage which allows the GPU to enter an very
40 * low-voltage mode when idle, using down to 0V while at this stage. This
41 * stage is entered automatically when the GPU is idle when RC6 support is
42 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
44 * There are different RC6 modes available in Intel GPU, which differentiate
45 * among each other with the latency required to enter and leave RC6 and
46 * voltage consumed by the GPU in different states.
48 * The combination of the following flags define which states GPU is allowed
49 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
50 * RC6pp is deepest RC6. Their support by hardware varies according to the
51 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
52 * which brings the most power savings; deeper states save more power, but
53 * require higher latency to switch to and wake up.
55 #define INTEL_RC6_ENABLE (1<<0)
56 #define INTEL_RC6p_ENABLE (1<<1)
57 #define INTEL_RC6pp_ENABLE (1<<2)
59 static void gen9_init_clock_gating(struct drm_i915_private
*dev_priv
)
61 if (HAS_LLC(dev_priv
)) {
63 * WaCompressedResourceDisplayNewHashMode:skl,kbl
64 * Display WA#0390: skl,kbl
66 * Must match Sampler, Pixel Back End, and Media. See
67 * WaCompressedResourceSamplerPbeMediaNewHashMode.
69 I915_WRITE(CHICKEN_PAR1_1
,
70 I915_READ(CHICKEN_PAR1_1
) |
71 SKL_DE_COMPRESSED_HASH_MODE
);
74 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
75 I915_WRITE(CHICKEN_PAR1_1
,
76 I915_READ(CHICKEN_PAR1_1
) | SKL_EDP_PSR_FIX_RDWRAP
);
78 I915_WRITE(GEN8_CONFIG0
,
79 I915_READ(GEN8_CONFIG0
) | GEN9_DEFAULT_FIXES
);
81 /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
82 I915_WRITE(GEN8_CHICKEN_DCPR_1
,
83 I915_READ(GEN8_CHICKEN_DCPR_1
) | MASK_WAKEMEM
);
85 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
86 /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
87 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
89 DISP_FBC_MEMORY_WAKE
);
91 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
92 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
93 ILK_DPFC_DISABLE_DUMMY0
);
95 if (IS_SKYLAKE(dev_priv
)) {
96 /* WaDisableDopClockGating */
97 I915_WRITE(GEN7_MISCCPCTL
, I915_READ(GEN7_MISCCPCTL
)
98 & ~GEN7_DOP_CLOCK_GATE_ENABLE
);
102 static void bxt_init_clock_gating(struct drm_i915_private
*dev_priv
)
104 gen9_init_clock_gating(dev_priv
);
106 /* WaDisableSDEUnitClockGating:bxt */
107 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
108 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
112 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
114 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
115 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ
);
118 * Wa: Backlight PWM may stop in the asserted state, causing backlight
121 I915_WRITE(GEN9_CLKGATE_DIS_0
, I915_READ(GEN9_CLKGATE_DIS_0
) |
122 PWM1_GATING_DIS
| PWM2_GATING_DIS
);
125 static void glk_init_clock_gating(struct drm_i915_private
*dev_priv
)
128 gen9_init_clock_gating(dev_priv
);
131 * WaDisablePWMClockGating:glk
132 * Backlight PWM may stop in the asserted state, causing backlight
135 I915_WRITE(GEN9_CLKGATE_DIS_0
, I915_READ(GEN9_CLKGATE_DIS_0
) |
136 PWM1_GATING_DIS
| PWM2_GATING_DIS
);
138 /* WaDDIIOTimeout:glk */
139 if (IS_GLK_REVID(dev_priv
, 0, GLK_REVID_A1
)) {
140 u32 val
= I915_READ(CHICKEN_MISC_2
);
141 val
&= ~(GLK_CL0_PWR_DOWN
|
144 I915_WRITE(CHICKEN_MISC_2
, val
);
147 /* Display WA #1133: WaFbcSkipSegments:glk */
148 val
= I915_READ(ILK_DPFC_CHICKEN
);
149 val
&= ~GLK_SKIP_SEG_COUNT_MASK
;
150 val
|= GLK_SKIP_SEG_EN
| GLK_SKIP_SEG_COUNT(1);
151 I915_WRITE(ILK_DPFC_CHICKEN
, val
);
154 static void i915_pineview_get_mem_freq(struct drm_i915_private
*dev_priv
)
158 tmp
= I915_READ(CLKCFG
);
160 switch (tmp
& CLKCFG_FSB_MASK
) {
162 dev_priv
->fsb_freq
= 533; /* 133*4 */
165 dev_priv
->fsb_freq
= 800; /* 200*4 */
168 dev_priv
->fsb_freq
= 667; /* 167*4 */
171 dev_priv
->fsb_freq
= 400; /* 100*4 */
175 switch (tmp
& CLKCFG_MEM_MASK
) {
177 dev_priv
->mem_freq
= 533;
180 dev_priv
->mem_freq
= 667;
183 dev_priv
->mem_freq
= 800;
187 /* detect pineview DDR3 setting */
188 tmp
= I915_READ(CSHRDDR3CTL
);
189 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
192 static void i915_ironlake_get_mem_freq(struct drm_i915_private
*dev_priv
)
196 ddrpll
= I915_READ16(DDRMPLL1
);
197 csipll
= I915_READ16(CSIPLL0
);
199 switch (ddrpll
& 0xff) {
201 dev_priv
->mem_freq
= 800;
204 dev_priv
->mem_freq
= 1066;
207 dev_priv
->mem_freq
= 1333;
210 dev_priv
->mem_freq
= 1600;
213 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
215 dev_priv
->mem_freq
= 0;
219 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
221 switch (csipll
& 0x3ff) {
223 dev_priv
->fsb_freq
= 3200;
226 dev_priv
->fsb_freq
= 3733;
229 dev_priv
->fsb_freq
= 4266;
232 dev_priv
->fsb_freq
= 4800;
235 dev_priv
->fsb_freq
= 5333;
238 dev_priv
->fsb_freq
= 5866;
241 dev_priv
->fsb_freq
= 6400;
244 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
246 dev_priv
->fsb_freq
= 0;
250 if (dev_priv
->fsb_freq
== 3200) {
251 dev_priv
->ips
.c_m
= 0;
252 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
253 dev_priv
->ips
.c_m
= 1;
255 dev_priv
->ips
.c_m
= 2;
259 static const struct cxsr_latency cxsr_latency_table
[] = {
260 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
261 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
262 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
263 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
264 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
266 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
267 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
268 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
269 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
270 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
272 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
273 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
274 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
275 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
276 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
278 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
279 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
280 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
281 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
282 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
284 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
285 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
286 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
287 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
288 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
290 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
291 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
292 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
293 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
294 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
297 static const struct cxsr_latency
*intel_get_cxsr_latency(bool is_desktop
,
302 const struct cxsr_latency
*latency
;
305 if (fsb
== 0 || mem
== 0)
308 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
309 latency
= &cxsr_latency_table
[i
];
310 if (is_desktop
== latency
->is_desktop
&&
311 is_ddr3
== latency
->is_ddr3
&&
312 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
316 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
321 static void chv_set_memory_dvfs(struct drm_i915_private
*dev_priv
, bool enable
)
325 mutex_lock(&dev_priv
->rps
.hw_lock
);
327 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
329 val
&= ~FORCE_DDR_HIGH_FREQ
;
331 val
|= FORCE_DDR_HIGH_FREQ
;
332 val
&= ~FORCE_DDR_LOW_FREQ
;
333 val
|= FORCE_DDR_FREQ_REQ_ACK
;
334 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
336 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
337 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3))
338 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
340 mutex_unlock(&dev_priv
->rps
.hw_lock
);
343 static void chv_set_memory_pm5(struct drm_i915_private
*dev_priv
, bool enable
)
347 mutex_lock(&dev_priv
->rps
.hw_lock
);
349 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
351 val
|= DSP_MAXFIFO_PM5_ENABLE
;
353 val
&= ~DSP_MAXFIFO_PM5_ENABLE
;
354 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
356 mutex_unlock(&dev_priv
->rps
.hw_lock
);
359 #define FW_WM(value, plane) \
360 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
362 static bool _intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
367 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
368 was_enabled
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
369 I915_WRITE(FW_BLC_SELF_VLV
, enable
? FW_CSPWRDWNEN
: 0);
370 POSTING_READ(FW_BLC_SELF_VLV
);
371 } else if (IS_G4X(dev_priv
) || IS_I965GM(dev_priv
)) {
372 was_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
373 I915_WRITE(FW_BLC_SELF
, enable
? FW_BLC_SELF_EN
: 0);
374 POSTING_READ(FW_BLC_SELF
);
375 } else if (IS_PINEVIEW(dev_priv
)) {
376 val
= I915_READ(DSPFW3
);
377 was_enabled
= val
& PINEVIEW_SELF_REFRESH_EN
;
379 val
|= PINEVIEW_SELF_REFRESH_EN
;
381 val
&= ~PINEVIEW_SELF_REFRESH_EN
;
382 I915_WRITE(DSPFW3
, val
);
383 POSTING_READ(DSPFW3
);
384 } else if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
)) {
385 was_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
386 val
= enable
? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN
) :
387 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN
);
388 I915_WRITE(FW_BLC_SELF
, val
);
389 POSTING_READ(FW_BLC_SELF
);
390 } else if (IS_I915GM(dev_priv
)) {
392 * FIXME can't find a bit like this for 915G, and
393 * and yet it does have the related watermark in
394 * FW_BLC_SELF. What's going on?
396 was_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
397 val
= enable
? _MASKED_BIT_ENABLE(INSTPM_SELF_EN
) :
398 _MASKED_BIT_DISABLE(INSTPM_SELF_EN
);
399 I915_WRITE(INSTPM
, val
);
400 POSTING_READ(INSTPM
);
405 trace_intel_memory_cxsr(dev_priv
, was_enabled
, enable
);
407 DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
408 enableddisabled(enable
),
409 enableddisabled(was_enabled
));
415 * intel_set_memory_cxsr - Configure CxSR state
416 * @dev_priv: i915 device
417 * @enable: Allow vs. disallow CxSR
419 * Allow or disallow the system to enter a special CxSR
420 * (C-state self refresh) state. What typically happens in CxSR mode
421 * is that several display FIFOs may get combined into a single larger
422 * FIFO for a particular plane (so called max FIFO mode) to allow the
423 * system to defer memory fetches longer, and the memory will enter
426 * Note that enabling CxSR does not guarantee that the system enter
427 * this special mode, nor does it guarantee that the system stays
428 * in that mode once entered. So this just allows/disallows the system
429 * to autonomously utilize the CxSR mode. Other factors such as core
430 * C-states will affect when/if the system actually enters/exits the
433 * Note that on VLV/CHV this actually only controls the max FIFO mode,
434 * and the system is free to enter/exit memory self refresh at any time
435 * even when the use of CxSR has been disallowed.
437 * While the system is actually in the CxSR/max FIFO mode, some plane
438 * control registers will not get latched on vblank. Thus in order to
439 * guarantee the system will respond to changes in the plane registers
440 * we must always disallow CxSR prior to making changes to those registers.
441 * Unfortunately the system will re-evaluate the CxSR conditions at
442 * frame start which happens after vblank start (which is when the plane
443 * registers would get latched), so we can't proceed with the plane update
444 * during the same frame where we disallowed CxSR.
446 * Certain platforms also have a deeper HPLL SR mode. Fortunately the
447 * HPLL SR mode depends on CxSR itself, so we don't have to hand hold
448 * the hardware w.r.t. HPLL SR when writing to plane registers.
449 * Disallowing just CxSR is sufficient.
451 bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
455 mutex_lock(&dev_priv
->wm
.wm_mutex
);
456 ret
= _intel_set_memory_cxsr(dev_priv
, enable
);
457 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
458 dev_priv
->wm
.vlv
.cxsr
= enable
;
459 else if (IS_G4X(dev_priv
))
460 dev_priv
->wm
.g4x
.cxsr
= enable
;
461 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
467 * Latency for FIFO fetches is dependent on several factors:
468 * - memory configuration (speed, channels)
470 * - current MCH state
471 * It can be fairly high in some situations, so here we assume a fairly
472 * pessimal value. It's a tradeoff between extra memory fetches (if we
473 * set this value too high, the FIFO will fetch frequently to stay full)
474 * and power consumption (set it too low to save power and we might see
475 * FIFO underruns and display "flicker").
477 * A value of 5us seems to be a good balance; safe for very low end
478 * platforms but not overly aggressive on lower latency configs.
480 static const int pessimal_latency_ns
= 5000;
482 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
483 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
485 static void vlv_get_fifo_size(struct intel_crtc_state
*crtc_state
)
487 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
488 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
489 struct vlv_fifo_state
*fifo_state
= &crtc_state
->wm
.vlv
.fifo_state
;
490 enum pipe pipe
= crtc
->pipe
;
491 int sprite0_start
, sprite1_start
;
494 uint32_t dsparb
, dsparb2
, dsparb3
;
496 dsparb
= I915_READ(DSPARB
);
497 dsparb2
= I915_READ(DSPARB2
);
498 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 0, 0);
499 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 8, 4);
502 dsparb
= I915_READ(DSPARB
);
503 dsparb2
= I915_READ(DSPARB2
);
504 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 16, 8);
505 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 24, 12);
508 dsparb2
= I915_READ(DSPARB2
);
509 dsparb3
= I915_READ(DSPARB3
);
510 sprite0_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 0, 16);
511 sprite1_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 8, 20);
518 fifo_state
->plane
[PLANE_PRIMARY
] = sprite0_start
;
519 fifo_state
->plane
[PLANE_SPRITE0
] = sprite1_start
- sprite0_start
;
520 fifo_state
->plane
[PLANE_SPRITE1
] = 511 - sprite1_start
;
521 fifo_state
->plane
[PLANE_CURSOR
] = 63;
524 static int i9xx_get_fifo_size(struct drm_i915_private
*dev_priv
, int plane
)
526 uint32_t dsparb
= I915_READ(DSPARB
);
529 size
= dsparb
& 0x7f;
531 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
533 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
534 plane
? "B" : "A", size
);
539 static int i830_get_fifo_size(struct drm_i915_private
*dev_priv
, int plane
)
541 uint32_t dsparb
= I915_READ(DSPARB
);
544 size
= dsparb
& 0x1ff;
546 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
547 size
>>= 1; /* Convert to cachelines */
549 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
550 plane
? "B" : "A", size
);
555 static int i845_get_fifo_size(struct drm_i915_private
*dev_priv
, int plane
)
557 uint32_t dsparb
= I915_READ(DSPARB
);
560 size
= dsparb
& 0x7f;
561 size
>>= 2; /* Convert to cachelines */
563 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
570 /* Pineview has different values for various configs */
571 static const struct intel_watermark_params pineview_display_wm
= {
572 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
573 .max_wm
= PINEVIEW_MAX_WM
,
574 .default_wm
= PINEVIEW_DFT_WM
,
575 .guard_size
= PINEVIEW_GUARD_WM
,
576 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
578 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
579 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
580 .max_wm
= PINEVIEW_MAX_WM
,
581 .default_wm
= PINEVIEW_DFT_HPLLOFF_WM
,
582 .guard_size
= PINEVIEW_GUARD_WM
,
583 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
585 static const struct intel_watermark_params pineview_cursor_wm
= {
586 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
587 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
588 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
589 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
590 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
592 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
593 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
594 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
595 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
596 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
597 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
599 static const struct intel_watermark_params i965_cursor_wm_info
= {
600 .fifo_size
= I965_CURSOR_FIFO
,
601 .max_wm
= I965_CURSOR_MAX_WM
,
602 .default_wm
= I965_CURSOR_DFT_WM
,
604 .cacheline_size
= I915_FIFO_LINE_SIZE
,
606 static const struct intel_watermark_params i945_wm_info
= {
607 .fifo_size
= I945_FIFO_SIZE
,
608 .max_wm
= I915_MAX_WM
,
611 .cacheline_size
= I915_FIFO_LINE_SIZE
,
613 static const struct intel_watermark_params i915_wm_info
= {
614 .fifo_size
= I915_FIFO_SIZE
,
615 .max_wm
= I915_MAX_WM
,
618 .cacheline_size
= I915_FIFO_LINE_SIZE
,
620 static const struct intel_watermark_params i830_a_wm_info
= {
621 .fifo_size
= I855GM_FIFO_SIZE
,
622 .max_wm
= I915_MAX_WM
,
625 .cacheline_size
= I830_FIFO_LINE_SIZE
,
627 static const struct intel_watermark_params i830_bc_wm_info
= {
628 .fifo_size
= I855GM_FIFO_SIZE
,
629 .max_wm
= I915_MAX_WM
/2,
632 .cacheline_size
= I830_FIFO_LINE_SIZE
,
634 static const struct intel_watermark_params i845_wm_info
= {
635 .fifo_size
= I830_FIFO_SIZE
,
636 .max_wm
= I915_MAX_WM
,
639 .cacheline_size
= I830_FIFO_LINE_SIZE
,
643 * intel_wm_method1 - Method 1 / "small buffer" watermark formula
644 * @pixel_rate: Pipe pixel rate in kHz
645 * @cpp: Plane bytes per pixel
646 * @latency: Memory wakeup latency in 0.1us units
648 * Compute the watermark using the method 1 or "small buffer"
649 * formula. The caller may additonally add extra cachelines
650 * to account for TLB misses and clock crossings.
652 * This method is concerned with the short term drain rate
653 * of the FIFO, ie. it does not account for blanking periods
654 * which would effectively reduce the average drain rate across
655 * a longer period. The name "small" refers to the fact the
656 * FIFO is relatively small compared to the amount of data
659 * The FIFO level vs. time graph might look something like:
663 * __---__---__ (- plane active, _ blanking)
666 * or perhaps like this:
669 * __----__----__ (- plane active, _ blanking)
673 * The watermark in bytes
675 static unsigned int intel_wm_method1(unsigned int pixel_rate
,
677 unsigned int latency
)
681 ret
= (uint64_t) pixel_rate
* cpp
* latency
;
682 ret
= DIV_ROUND_UP_ULL(ret
, 10000);
688 * intel_wm_method2 - Method 2 / "large buffer" watermark formula
689 * @pixel_rate: Pipe pixel rate in kHz
690 * @htotal: Pipe horizontal total
691 * @width: Plane width in pixels
692 * @cpp: Plane bytes per pixel
693 * @latency: Memory wakeup latency in 0.1us units
695 * Compute the watermark using the method 2 or "large buffer"
696 * formula. The caller may additonally add extra cachelines
697 * to account for TLB misses and clock crossings.
699 * This method is concerned with the long term drain rate
700 * of the FIFO, ie. it does account for blanking periods
701 * which effectively reduce the average drain rate across
702 * a longer period. The name "large" refers to the fact the
703 * FIFO is relatively large compared to the amount of data
706 * The FIFO level vs. time graph might look something like:
711 * __ --__--__--__--__--__--__ (- plane active, _ blanking)
715 * The watermark in bytes
717 static unsigned int intel_wm_method2(unsigned int pixel_rate
,
721 unsigned int latency
)
726 * FIXME remove once all users are computing
727 * watermarks in the correct place.
729 if (WARN_ON_ONCE(htotal
== 0))
732 ret
= (latency
* pixel_rate
) / (htotal
* 10000);
733 ret
= (ret
+ 1) * width
* cpp
;
739 * intel_calculate_wm - calculate watermark level
740 * @pixel_rate: pixel clock
741 * @wm: chip FIFO params
742 * @cpp: bytes per pixel
743 * @latency_ns: memory latency for the platform
745 * Calculate the watermark level (the level at which the display plane will
746 * start fetching from memory again). Each chip has a different display
747 * FIFO size and allocation, so the caller needs to figure that out and pass
748 * in the correct intel_watermark_params structure.
750 * As the pixel clock runs, the FIFO will be drained at a rate that depends
751 * on the pixel size. When it reaches the watermark level, it'll start
752 * fetching FIFO line sized based chunks from memory until the FIFO fills
753 * past the watermark point. If the FIFO drains completely, a FIFO underrun
754 * will occur, and a display engine hang could result.
756 static unsigned int intel_calculate_wm(int pixel_rate
,
757 const struct intel_watermark_params
*wm
,
758 int fifo_size
, int cpp
,
759 unsigned int latency_ns
)
761 int entries
, wm_size
;
764 * Note: we need to make sure we don't overflow for various clock &
766 * clocks go from a few thousand to several hundred thousand.
767 * latency is usually a few thousand
769 entries
= intel_wm_method1(pixel_rate
, cpp
,
771 entries
= DIV_ROUND_UP(entries
, wm
->cacheline_size
) +
773 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries
);
775 wm_size
= fifo_size
- entries
;
776 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size
);
778 /* Don't promote wm_size to unsigned... */
779 if (wm_size
> wm
->max_wm
)
780 wm_size
= wm
->max_wm
;
782 wm_size
= wm
->default_wm
;
785 * Bspec seems to indicate that the value shouldn't be lower than
786 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
787 * Lets go for 8 which is the burst size since certain platforms
788 * already use a hardcoded 8 (which is what the spec says should be
797 static bool is_disabling(int old
, int new, int threshold
)
799 return old
>= threshold
&& new < threshold
;
802 static bool is_enabling(int old
, int new, int threshold
)
804 return old
< threshold
&& new >= threshold
;
807 static int intel_wm_num_levels(struct drm_i915_private
*dev_priv
)
809 return dev_priv
->wm
.max_level
+ 1;
812 static bool intel_wm_plane_visible(const struct intel_crtc_state
*crtc_state
,
813 const struct intel_plane_state
*plane_state
)
815 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
817 /* FIXME check the 'enable' instead */
818 if (!crtc_state
->base
.active
)
822 * Treat cursor with fb as always visible since cursor updates
823 * can happen faster than the vrefresh rate, and the current
824 * watermark code doesn't handle that correctly. Cursor updates
825 * which set/clear the fb or change the cursor size are going
826 * to get throttled by intel_legacy_cursor_update() to work
827 * around this problem with the watermark code.
829 if (plane
->id
== PLANE_CURSOR
)
830 return plane_state
->base
.fb
!= NULL
;
832 return plane_state
->base
.visible
;
835 static struct intel_crtc
*single_enabled_crtc(struct drm_i915_private
*dev_priv
)
837 struct intel_crtc
*crtc
, *enabled
= NULL
;
839 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
840 if (intel_crtc_active(crtc
)) {
850 static void pineview_update_wm(struct intel_crtc
*unused_crtc
)
852 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
853 struct intel_crtc
*crtc
;
854 const struct cxsr_latency
*latency
;
858 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv
),
863 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
864 intel_set_memory_cxsr(dev_priv
, false);
868 crtc
= single_enabled_crtc(dev_priv
);
870 const struct drm_display_mode
*adjusted_mode
=
871 &crtc
->config
->base
.adjusted_mode
;
872 const struct drm_framebuffer
*fb
=
873 crtc
->base
.primary
->state
->fb
;
874 int cpp
= fb
->format
->cpp
[0];
875 int clock
= adjusted_mode
->crtc_clock
;
878 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
879 pineview_display_wm
.fifo_size
,
880 cpp
, latency
->display_sr
);
881 reg
= I915_READ(DSPFW1
);
882 reg
&= ~DSPFW_SR_MASK
;
883 reg
|= FW_WM(wm
, SR
);
884 I915_WRITE(DSPFW1
, reg
);
885 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
888 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
889 pineview_display_wm
.fifo_size
,
890 4, latency
->cursor_sr
);
891 reg
= I915_READ(DSPFW3
);
892 reg
&= ~DSPFW_CURSOR_SR_MASK
;
893 reg
|= FW_WM(wm
, CURSOR_SR
);
894 I915_WRITE(DSPFW3
, reg
);
896 /* Display HPLL off SR */
897 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
898 pineview_display_hplloff_wm
.fifo_size
,
899 cpp
, latency
->display_hpll_disable
);
900 reg
= I915_READ(DSPFW3
);
901 reg
&= ~DSPFW_HPLL_SR_MASK
;
902 reg
|= FW_WM(wm
, HPLL_SR
);
903 I915_WRITE(DSPFW3
, reg
);
905 /* cursor HPLL off SR */
906 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
907 pineview_display_hplloff_wm
.fifo_size
,
908 4, latency
->cursor_hpll_disable
);
909 reg
= I915_READ(DSPFW3
);
910 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
911 reg
|= FW_WM(wm
, HPLL_CURSOR
);
912 I915_WRITE(DSPFW3
, reg
);
913 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
915 intel_set_memory_cxsr(dev_priv
, true);
917 intel_set_memory_cxsr(dev_priv
, false);
922 * Documentation says:
923 * "If the line size is small, the TLB fetches can get in the way of the
924 * data fetches, causing some lag in the pixel data return which is not
925 * accounted for in the above formulas. The following adjustment only
926 * needs to be applied if eight whole lines fit in the buffer at once.
927 * The WM is adjusted upwards by the difference between the FIFO size
928 * and the size of 8 whole lines. This adjustment is always performed
929 * in the actual pixel depth regardless of whether FBC is enabled or not."
931 static int g4x_tlb_miss_wa(int fifo_size
, int width
, int cpp
)
933 int tlb_miss
= fifo_size
* 64 - width
* cpp
* 8;
935 return max(0, tlb_miss
);
938 static void g4x_write_wm_values(struct drm_i915_private
*dev_priv
,
939 const struct g4x_wm_values
*wm
)
943 for_each_pipe(dev_priv
, pipe
)
944 trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv
, pipe
), wm
);
947 FW_WM(wm
->sr
.plane
, SR
) |
948 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_CURSOR
], CURSORB
) |
949 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
], PLANEB
) |
950 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
], PLANEA
));
952 (wm
->fbc_en
? DSPFW_FBC_SR_EN
: 0) |
953 FW_WM(wm
->sr
.fbc
, FBC_SR
) |
954 FW_WM(wm
->hpll
.fbc
, FBC_HPLL_SR
) |
955 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
], SPRITEB
) |
956 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_CURSOR
], CURSORA
) |
957 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
], SPRITEA
));
959 (wm
->hpll_en
? DSPFW_HPLL_SR_EN
: 0) |
960 FW_WM(wm
->sr
.cursor
, CURSOR_SR
) |
961 FW_WM(wm
->hpll
.cursor
, HPLL_CURSOR
) |
962 FW_WM(wm
->hpll
.plane
, HPLL_SR
));
964 POSTING_READ(DSPFW1
);
967 #define FW_WM_VLV(value, plane) \
968 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
970 static void vlv_write_wm_values(struct drm_i915_private
*dev_priv
,
971 const struct vlv_wm_values
*wm
)
975 for_each_pipe(dev_priv
, pipe
) {
976 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv
, pipe
), wm
);
978 I915_WRITE(VLV_DDL(pipe
),
979 (wm
->ddl
[pipe
].plane
[PLANE_CURSOR
] << DDL_CURSOR_SHIFT
) |
980 (wm
->ddl
[pipe
].plane
[PLANE_SPRITE1
] << DDL_SPRITE_SHIFT(1)) |
981 (wm
->ddl
[pipe
].plane
[PLANE_SPRITE0
] << DDL_SPRITE_SHIFT(0)) |
982 (wm
->ddl
[pipe
].plane
[PLANE_PRIMARY
] << DDL_PLANE_SHIFT
));
986 * Zero the (unused) WM1 watermarks, and also clear all the
987 * high order bits so that there are no out of bounds values
988 * present in the registers during the reprogramming.
990 I915_WRITE(DSPHOWM
, 0);
991 I915_WRITE(DSPHOWM1
, 0);
992 I915_WRITE(DSPFW4
, 0);
993 I915_WRITE(DSPFW5
, 0);
994 I915_WRITE(DSPFW6
, 0);
997 FW_WM(wm
->sr
.plane
, SR
) |
998 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_CURSOR
], CURSORB
) |
999 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
], PLANEB
) |
1000 FW_WM_VLV(wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
], PLANEA
));
1002 FW_WM_VLV(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
], SPRITEB
) |
1003 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_CURSOR
], CURSORA
) |
1004 FW_WM_VLV(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
], SPRITEA
));
1006 FW_WM(wm
->sr
.cursor
, CURSOR_SR
));
1008 if (IS_CHERRYVIEW(dev_priv
)) {
1009 I915_WRITE(DSPFW7_CHV
,
1010 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
], SPRITED
) |
1011 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
], SPRITEC
));
1012 I915_WRITE(DSPFW8_CHV
,
1013 FW_WM_VLV(wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE1
], SPRITEF
) |
1014 FW_WM_VLV(wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE0
], SPRITEE
));
1015 I915_WRITE(DSPFW9_CHV
,
1016 FW_WM_VLV(wm
->pipe
[PIPE_C
].plane
[PLANE_PRIMARY
], PLANEC
) |
1017 FW_WM(wm
->pipe
[PIPE_C
].plane
[PLANE_CURSOR
], CURSORC
));
1019 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
1020 FW_WM(wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE1
] >> 8, SPRITEF_HI
) |
1021 FW_WM(wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE0
] >> 8, SPRITEE_HI
) |
1022 FW_WM(wm
->pipe
[PIPE_C
].plane
[PLANE_PRIMARY
] >> 8, PLANEC_HI
) |
1023 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] >> 8, SPRITED_HI
) |
1024 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] >> 8, SPRITEC_HI
) |
1025 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] >> 8, PLANEB_HI
) |
1026 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] >> 8, SPRITEB_HI
) |
1027 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] >> 8, SPRITEA_HI
) |
1028 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] >> 8, PLANEA_HI
));
1031 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
], SPRITED
) |
1032 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
], SPRITEC
));
1034 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
1035 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] >> 8, SPRITED_HI
) |
1036 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] >> 8, SPRITEC_HI
) |
1037 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] >> 8, PLANEB_HI
) |
1038 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] >> 8, SPRITEB_HI
) |
1039 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] >> 8, SPRITEA_HI
) |
1040 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] >> 8, PLANEA_HI
));
1043 POSTING_READ(DSPFW1
);
1048 static void g4x_setup_wm_latency(struct drm_i915_private
*dev_priv
)
1050 /* all latencies in usec */
1051 dev_priv
->wm
.pri_latency
[G4X_WM_LEVEL_NORMAL
] = 5;
1052 dev_priv
->wm
.pri_latency
[G4X_WM_LEVEL_SR
] = 12;
1053 dev_priv
->wm
.pri_latency
[G4X_WM_LEVEL_HPLL
] = 35;
1055 dev_priv
->wm
.max_level
= G4X_WM_LEVEL_HPLL
;
1058 static int g4x_plane_fifo_size(enum plane_id plane_id
, int level
)
1061 * DSPCNTR[13] supposedly controls whether the
1062 * primary plane can use the FIFO space otherwise
1063 * reserved for the sprite plane. It's not 100% clear
1064 * what the actual FIFO size is, but it looks like we
1065 * can happily set both primary and sprite watermarks
1066 * up to 127 cachelines. So that would seem to mean
1067 * that either DSPCNTR[13] doesn't do anything, or that
1068 * the total FIFO is >= 256 cachelines in size. Either
1069 * way, we don't seem to have to worry about this
1070 * repartitioning as the maximum watermark value the
1071 * register can hold for each plane is lower than the
1072 * minimum FIFO size.
1078 return level
== G4X_WM_LEVEL_NORMAL
? 127 : 511;
1080 return level
== G4X_WM_LEVEL_NORMAL
? 127 : 0;
1082 MISSING_CASE(plane_id
);
1087 static int g4x_fbc_fifo_size(int level
)
1090 case G4X_WM_LEVEL_SR
:
1092 case G4X_WM_LEVEL_HPLL
:
1095 MISSING_CASE(level
);
1100 static uint16_t g4x_compute_wm(const struct intel_crtc_state
*crtc_state
,
1101 const struct intel_plane_state
*plane_state
,
1104 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
1105 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
1106 const struct drm_display_mode
*adjusted_mode
=
1107 &crtc_state
->base
.adjusted_mode
;
1108 int clock
, htotal
, cpp
, width
, wm
;
1109 int latency
= dev_priv
->wm
.pri_latency
[level
] * 10;
1114 if (!intel_wm_plane_visible(crtc_state
, plane_state
))
1118 * Not 100% sure which way ELK should go here as the
1119 * spec only says CL/CTG should assume 32bpp and BW
1120 * doesn't need to. But as these things followed the
1121 * mobile vs. desktop lines on gen3 as well, let's
1122 * assume ELK doesn't need this.
1124 * The spec also fails to list such a restriction for
1125 * the HPLL watermark, which seems a little strange.
1126 * Let's use 32bpp for the HPLL watermark as well.
1128 if (IS_GM45(dev_priv
) && plane
->id
== PLANE_PRIMARY
&&
1129 level
!= G4X_WM_LEVEL_NORMAL
)
1132 cpp
= plane_state
->base
.fb
->format
->cpp
[0];
1134 clock
= adjusted_mode
->crtc_clock
;
1135 htotal
= adjusted_mode
->crtc_htotal
;
1137 if (plane
->id
== PLANE_CURSOR
)
1138 width
= plane_state
->base
.crtc_w
;
1140 width
= drm_rect_width(&plane_state
->base
.dst
);
1142 if (plane
->id
== PLANE_CURSOR
) {
1143 wm
= intel_wm_method2(clock
, htotal
, width
, cpp
, latency
);
1144 } else if (plane
->id
== PLANE_PRIMARY
&&
1145 level
== G4X_WM_LEVEL_NORMAL
) {
1146 wm
= intel_wm_method1(clock
, cpp
, latency
);
1150 small
= intel_wm_method1(clock
, cpp
, latency
);
1151 large
= intel_wm_method2(clock
, htotal
, width
, cpp
, latency
);
1153 wm
= min(small
, large
);
1156 wm
+= g4x_tlb_miss_wa(g4x_plane_fifo_size(plane
->id
, level
),
1159 wm
= DIV_ROUND_UP(wm
, 64) + 2;
1161 return min_t(int, wm
, USHRT_MAX
);
1164 static bool g4x_raw_plane_wm_set(struct intel_crtc_state
*crtc_state
,
1165 int level
, enum plane_id plane_id
, u16 value
)
1167 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1170 for (; level
< intel_wm_num_levels(dev_priv
); level
++) {
1171 struct g4x_pipe_wm
*raw
= &crtc_state
->wm
.g4x
.raw
[level
];
1173 dirty
|= raw
->plane
[plane_id
] != value
;
1174 raw
->plane
[plane_id
] = value
;
1180 static bool g4x_raw_fbc_wm_set(struct intel_crtc_state
*crtc_state
,
1181 int level
, u16 value
)
1183 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1186 /* NORMAL level doesn't have an FBC watermark */
1187 level
= max(level
, G4X_WM_LEVEL_SR
);
1189 for (; level
< intel_wm_num_levels(dev_priv
); level
++) {
1190 struct g4x_pipe_wm
*raw
= &crtc_state
->wm
.g4x
.raw
[level
];
1192 dirty
|= raw
->fbc
!= value
;
1199 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state
*cstate
,
1200 const struct intel_plane_state
*pstate
,
1203 static bool g4x_raw_plane_wm_compute(struct intel_crtc_state
*crtc_state
,
1204 const struct intel_plane_state
*plane_state
)
1206 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
1207 int num_levels
= intel_wm_num_levels(to_i915(plane
->base
.dev
));
1208 enum plane_id plane_id
= plane
->id
;
1212 if (!intel_wm_plane_visible(crtc_state
, plane_state
)) {
1213 dirty
|= g4x_raw_plane_wm_set(crtc_state
, 0, plane_id
, 0);
1214 if (plane_id
== PLANE_PRIMARY
)
1215 dirty
|= g4x_raw_fbc_wm_set(crtc_state
, 0, 0);
1219 for (level
= 0; level
< num_levels
; level
++) {
1220 struct g4x_pipe_wm
*raw
= &crtc_state
->wm
.g4x
.raw
[level
];
1223 wm
= g4x_compute_wm(crtc_state
, plane_state
, level
);
1224 max_wm
= g4x_plane_fifo_size(plane_id
, level
);
1229 dirty
|= raw
->plane
[plane_id
] != wm
;
1230 raw
->plane
[plane_id
] = wm
;
1232 if (plane_id
!= PLANE_PRIMARY
||
1233 level
== G4X_WM_LEVEL_NORMAL
)
1236 wm
= ilk_compute_fbc_wm(crtc_state
, plane_state
,
1237 raw
->plane
[plane_id
]);
1238 max_wm
= g4x_fbc_fifo_size(level
);
1241 * FBC wm is not mandatory as we
1242 * can always just disable its use.
1247 dirty
|= raw
->fbc
!= wm
;
1251 /* mark watermarks as invalid */
1252 dirty
|= g4x_raw_plane_wm_set(crtc_state
, level
, plane_id
, USHRT_MAX
);
1254 if (plane_id
== PLANE_PRIMARY
)
1255 dirty
|= g4x_raw_fbc_wm_set(crtc_state
, level
, USHRT_MAX
);
1259 DRM_DEBUG_KMS("%s watermarks: normal=%d, SR=%d, HPLL=%d\n",
1261 crtc_state
->wm
.g4x
.raw
[G4X_WM_LEVEL_NORMAL
].plane
[plane_id
],
1262 crtc_state
->wm
.g4x
.raw
[G4X_WM_LEVEL_SR
].plane
[plane_id
],
1263 crtc_state
->wm
.g4x
.raw
[G4X_WM_LEVEL_HPLL
].plane
[plane_id
]);
1265 if (plane_id
== PLANE_PRIMARY
)
1266 DRM_DEBUG_KMS("FBC watermarks: SR=%d, HPLL=%d\n",
1267 crtc_state
->wm
.g4x
.raw
[G4X_WM_LEVEL_SR
].fbc
,
1268 crtc_state
->wm
.g4x
.raw
[G4X_WM_LEVEL_HPLL
].fbc
);
1274 static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state
*crtc_state
,
1275 enum plane_id plane_id
, int level
)
1277 const struct g4x_pipe_wm
*raw
= &crtc_state
->wm
.g4x
.raw
[level
];
1279 return raw
->plane
[plane_id
] <= g4x_plane_fifo_size(plane_id
, level
);
1282 static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state
*crtc_state
,
1285 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1287 if (level
> dev_priv
->wm
.max_level
)
1290 return g4x_raw_plane_wm_is_valid(crtc_state
, PLANE_PRIMARY
, level
) &&
1291 g4x_raw_plane_wm_is_valid(crtc_state
, PLANE_SPRITE0
, level
) &&
1292 g4x_raw_plane_wm_is_valid(crtc_state
, PLANE_CURSOR
, level
);
1295 /* mark all levels starting from 'level' as invalid */
1296 static void g4x_invalidate_wms(struct intel_crtc
*crtc
,
1297 struct g4x_wm_state
*wm_state
, int level
)
1299 if (level
<= G4X_WM_LEVEL_NORMAL
) {
1300 enum plane_id plane_id
;
1302 for_each_plane_id_on_crtc(crtc
, plane_id
)
1303 wm_state
->wm
.plane
[plane_id
] = USHRT_MAX
;
1306 if (level
<= G4X_WM_LEVEL_SR
) {
1307 wm_state
->cxsr
= false;
1308 wm_state
->sr
.cursor
= USHRT_MAX
;
1309 wm_state
->sr
.plane
= USHRT_MAX
;
1310 wm_state
->sr
.fbc
= USHRT_MAX
;
1313 if (level
<= G4X_WM_LEVEL_HPLL
) {
1314 wm_state
->hpll_en
= false;
1315 wm_state
->hpll
.cursor
= USHRT_MAX
;
1316 wm_state
->hpll
.plane
= USHRT_MAX
;
1317 wm_state
->hpll
.fbc
= USHRT_MAX
;
1321 static int g4x_compute_pipe_wm(struct intel_crtc_state
*crtc_state
)
1323 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1324 struct intel_atomic_state
*state
=
1325 to_intel_atomic_state(crtc_state
->base
.state
);
1326 struct g4x_wm_state
*wm_state
= &crtc_state
->wm
.g4x
.optimal
;
1327 int num_active_planes
= hweight32(crtc_state
->active_planes
&
1328 ~BIT(PLANE_CURSOR
));
1329 const struct g4x_pipe_wm
*raw
;
1330 const struct intel_plane_state
*old_plane_state
;
1331 const struct intel_plane_state
*new_plane_state
;
1332 struct intel_plane
*plane
;
1333 enum plane_id plane_id
;
1335 unsigned int dirty
= 0;
1337 for_each_oldnew_intel_plane_in_state(state
, plane
,
1339 new_plane_state
, i
) {
1340 if (new_plane_state
->base
.crtc
!= &crtc
->base
&&
1341 old_plane_state
->base
.crtc
!= &crtc
->base
)
1344 if (g4x_raw_plane_wm_compute(crtc_state
, new_plane_state
))
1345 dirty
|= BIT(plane
->id
);
1351 level
= G4X_WM_LEVEL_NORMAL
;
1352 if (!g4x_raw_crtc_wm_is_valid(crtc_state
, level
))
1355 raw
= &crtc_state
->wm
.g4x
.raw
[level
];
1356 for_each_plane_id_on_crtc(crtc
, plane_id
)
1357 wm_state
->wm
.plane
[plane_id
] = raw
->plane
[plane_id
];
1359 level
= G4X_WM_LEVEL_SR
;
1361 if (!g4x_raw_crtc_wm_is_valid(crtc_state
, level
))
1364 raw
= &crtc_state
->wm
.g4x
.raw
[level
];
1365 wm_state
->sr
.plane
= raw
->plane
[PLANE_PRIMARY
];
1366 wm_state
->sr
.cursor
= raw
->plane
[PLANE_CURSOR
];
1367 wm_state
->sr
.fbc
= raw
->fbc
;
1369 wm_state
->cxsr
= num_active_planes
== BIT(PLANE_PRIMARY
);
1371 level
= G4X_WM_LEVEL_HPLL
;
1373 if (!g4x_raw_crtc_wm_is_valid(crtc_state
, level
))
1376 raw
= &crtc_state
->wm
.g4x
.raw
[level
];
1377 wm_state
->hpll
.plane
= raw
->plane
[PLANE_PRIMARY
];
1378 wm_state
->hpll
.cursor
= raw
->plane
[PLANE_CURSOR
];
1379 wm_state
->hpll
.fbc
= raw
->fbc
;
1381 wm_state
->hpll_en
= wm_state
->cxsr
;
1386 if (level
== G4X_WM_LEVEL_NORMAL
)
1389 /* invalidate the higher levels */
1390 g4x_invalidate_wms(crtc
, wm_state
, level
);
1393 * Determine if the FBC watermark(s) can be used. IF
1394 * this isn't the case we prefer to disable the FBC
1395 ( watermark(s) rather than disable the SR/HPLL
1396 * level(s) entirely.
1398 wm_state
->fbc_en
= level
> G4X_WM_LEVEL_NORMAL
;
1400 if (level
>= G4X_WM_LEVEL_SR
&&
1401 wm_state
->sr
.fbc
> g4x_fbc_fifo_size(G4X_WM_LEVEL_SR
))
1402 wm_state
->fbc_en
= false;
1403 else if (level
>= G4X_WM_LEVEL_HPLL
&&
1404 wm_state
->hpll
.fbc
> g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL
))
1405 wm_state
->fbc_en
= false;
1410 static int g4x_compute_intermediate_wm(struct drm_device
*dev
,
1411 struct intel_crtc
*crtc
,
1412 struct intel_crtc_state
*crtc_state
)
1414 struct g4x_wm_state
*intermediate
= &crtc_state
->wm
.g4x
.intermediate
;
1415 const struct g4x_wm_state
*optimal
= &crtc_state
->wm
.g4x
.optimal
;
1416 const struct g4x_wm_state
*active
= &crtc
->wm
.active
.g4x
;
1417 enum plane_id plane_id
;
1419 intermediate
->cxsr
= optimal
->cxsr
&& active
->cxsr
&&
1420 !crtc_state
->disable_cxsr
;
1421 intermediate
->hpll_en
= optimal
->hpll_en
&& active
->hpll_en
&&
1422 !crtc_state
->disable_cxsr
;
1423 intermediate
->fbc_en
= optimal
->fbc_en
&& active
->fbc_en
;
1425 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1426 intermediate
->wm
.plane
[plane_id
] =
1427 max(optimal
->wm
.plane
[plane_id
],
1428 active
->wm
.plane
[plane_id
]);
1430 WARN_ON(intermediate
->wm
.plane
[plane_id
] >
1431 g4x_plane_fifo_size(plane_id
, G4X_WM_LEVEL_NORMAL
));
1434 intermediate
->sr
.plane
= max(optimal
->sr
.plane
,
1436 intermediate
->sr
.cursor
= max(optimal
->sr
.cursor
,
1438 intermediate
->sr
.fbc
= max(optimal
->sr
.fbc
,
1441 intermediate
->hpll
.plane
= max(optimal
->hpll
.plane
,
1442 active
->hpll
.plane
);
1443 intermediate
->hpll
.cursor
= max(optimal
->hpll
.cursor
,
1444 active
->hpll
.cursor
);
1445 intermediate
->hpll
.fbc
= max(optimal
->hpll
.fbc
,
1448 WARN_ON((intermediate
->sr
.plane
>
1449 g4x_plane_fifo_size(PLANE_PRIMARY
, G4X_WM_LEVEL_SR
) ||
1450 intermediate
->sr
.cursor
>
1451 g4x_plane_fifo_size(PLANE_CURSOR
, G4X_WM_LEVEL_SR
)) &&
1452 intermediate
->cxsr
);
1453 WARN_ON((intermediate
->sr
.plane
>
1454 g4x_plane_fifo_size(PLANE_PRIMARY
, G4X_WM_LEVEL_HPLL
) ||
1455 intermediate
->sr
.cursor
>
1456 g4x_plane_fifo_size(PLANE_CURSOR
, G4X_WM_LEVEL_HPLL
)) &&
1457 intermediate
->hpll_en
);
1459 WARN_ON(intermediate
->sr
.fbc
> g4x_fbc_fifo_size(1) &&
1460 intermediate
->fbc_en
&& intermediate
->cxsr
);
1461 WARN_ON(intermediate
->hpll
.fbc
> g4x_fbc_fifo_size(2) &&
1462 intermediate
->fbc_en
&& intermediate
->hpll_en
);
1465 * If our intermediate WM are identical to the final WM, then we can
1466 * omit the post-vblank programming; only update if it's different.
1468 if (memcmp(intermediate
, optimal
, sizeof(*intermediate
)) != 0)
1469 crtc_state
->wm
.need_postvbl_update
= true;
1474 static void g4x_merge_wm(struct drm_i915_private
*dev_priv
,
1475 struct g4x_wm_values
*wm
)
1477 struct intel_crtc
*crtc
;
1478 int num_active_crtcs
= 0;
1484 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
1485 const struct g4x_wm_state
*wm_state
= &crtc
->wm
.active
.g4x
;
1490 if (!wm_state
->cxsr
)
1492 if (!wm_state
->hpll_en
)
1493 wm
->hpll_en
= false;
1494 if (!wm_state
->fbc_en
)
1500 if (num_active_crtcs
!= 1) {
1502 wm
->hpll_en
= false;
1506 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
1507 const struct g4x_wm_state
*wm_state
= &crtc
->wm
.active
.g4x
;
1508 enum pipe pipe
= crtc
->pipe
;
1510 wm
->pipe
[pipe
] = wm_state
->wm
;
1511 if (crtc
->active
&& wm
->cxsr
)
1512 wm
->sr
= wm_state
->sr
;
1513 if (crtc
->active
&& wm
->hpll_en
)
1514 wm
->hpll
= wm_state
->hpll
;
1518 static void g4x_program_watermarks(struct drm_i915_private
*dev_priv
)
1520 struct g4x_wm_values
*old_wm
= &dev_priv
->wm
.g4x
;
1521 struct g4x_wm_values new_wm
= {};
1523 g4x_merge_wm(dev_priv
, &new_wm
);
1525 if (memcmp(old_wm
, &new_wm
, sizeof(new_wm
)) == 0)
1528 if (is_disabling(old_wm
->cxsr
, new_wm
.cxsr
, true))
1529 _intel_set_memory_cxsr(dev_priv
, false);
1531 g4x_write_wm_values(dev_priv
, &new_wm
);
1533 if (is_enabling(old_wm
->cxsr
, new_wm
.cxsr
, true))
1534 _intel_set_memory_cxsr(dev_priv
, true);
1539 static void g4x_initial_watermarks(struct intel_atomic_state
*state
,
1540 struct intel_crtc_state
*crtc_state
)
1542 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1543 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1545 mutex_lock(&dev_priv
->wm
.wm_mutex
);
1546 crtc
->wm
.active
.g4x
= crtc_state
->wm
.g4x
.intermediate
;
1547 g4x_program_watermarks(dev_priv
);
1548 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
1551 static void g4x_optimize_watermarks(struct intel_atomic_state
*state
,
1552 struct intel_crtc_state
*crtc_state
)
1554 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1555 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1557 if (!crtc_state
->wm
.need_postvbl_update
)
1560 mutex_lock(&dev_priv
->wm
.wm_mutex
);
1561 intel_crtc
->wm
.active
.g4x
= crtc_state
->wm
.g4x
.optimal
;
1562 g4x_program_watermarks(dev_priv
);
1563 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
1566 /* latency must be in 0.1us units. */
1567 static unsigned int vlv_wm_method2(unsigned int pixel_rate
,
1568 unsigned int htotal
,
1571 unsigned int latency
)
1575 ret
= intel_wm_method2(pixel_rate
, htotal
,
1576 width
, cpp
, latency
);
1577 ret
= DIV_ROUND_UP(ret
, 64);
1582 static void vlv_setup_wm_latency(struct drm_i915_private
*dev_priv
)
1584 /* all latencies in usec */
1585 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM2
] = 3;
1587 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM2
;
1589 if (IS_CHERRYVIEW(dev_priv
)) {
1590 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM5
] = 12;
1591 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_DDR_DVFS
] = 33;
1593 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_DDR_DVFS
;
1597 static uint16_t vlv_compute_wm_level(const struct intel_crtc_state
*crtc_state
,
1598 const struct intel_plane_state
*plane_state
,
1601 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
1602 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
1603 const struct drm_display_mode
*adjusted_mode
=
1604 &crtc_state
->base
.adjusted_mode
;
1605 int clock
, htotal
, cpp
, width
, wm
;
1607 if (dev_priv
->wm
.pri_latency
[level
] == 0)
1610 if (!intel_wm_plane_visible(crtc_state
, plane_state
))
1613 cpp
= plane_state
->base
.fb
->format
->cpp
[0];
1614 clock
= adjusted_mode
->crtc_clock
;
1615 htotal
= adjusted_mode
->crtc_htotal
;
1616 width
= crtc_state
->pipe_src_w
;
1618 if (plane
->id
== PLANE_CURSOR
) {
1620 * FIXME the formula gives values that are
1621 * too big for the cursor FIFO, and hence we
1622 * would never be able to use cursors. For
1623 * now just hardcode the watermark.
1627 wm
= vlv_wm_method2(clock
, htotal
, width
, cpp
,
1628 dev_priv
->wm
.pri_latency
[level
] * 10);
1631 return min_t(int, wm
, USHRT_MAX
);
1634 static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes
)
1636 return (active_planes
& (BIT(PLANE_SPRITE0
) |
1637 BIT(PLANE_SPRITE1
))) == BIT(PLANE_SPRITE1
);
1640 static int vlv_compute_fifo(struct intel_crtc_state
*crtc_state
)
1642 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1643 const struct g4x_pipe_wm
*raw
=
1644 &crtc_state
->wm
.vlv
.raw
[VLV_WM_LEVEL_PM2
];
1645 struct vlv_fifo_state
*fifo_state
= &crtc_state
->wm
.vlv
.fifo_state
;
1646 unsigned int active_planes
= crtc_state
->active_planes
& ~BIT(PLANE_CURSOR
);
1647 int num_active_planes
= hweight32(active_planes
);
1648 const int fifo_size
= 511;
1649 int fifo_extra
, fifo_left
= fifo_size
;
1650 int sprite0_fifo_extra
= 0;
1651 unsigned int total_rate
;
1652 enum plane_id plane_id
;
1655 * When enabling sprite0 after sprite1 has already been enabled
1656 * we tend to get an underrun unless sprite0 already has some
1657 * FIFO space allcoated. Hence we always allocate at least one
1658 * cacheline for sprite0 whenever sprite1 is enabled.
1660 * All other plane enable sequences appear immune to this problem.
1662 if (vlv_need_sprite0_fifo_workaround(active_planes
))
1663 sprite0_fifo_extra
= 1;
1665 total_rate
= raw
->plane
[PLANE_PRIMARY
] +
1666 raw
->plane
[PLANE_SPRITE0
] +
1667 raw
->plane
[PLANE_SPRITE1
] +
1670 if (total_rate
> fifo_size
)
1673 if (total_rate
== 0)
1676 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1679 if ((active_planes
& BIT(plane_id
)) == 0) {
1680 fifo_state
->plane
[plane_id
] = 0;
1684 rate
= raw
->plane
[plane_id
];
1685 fifo_state
->plane
[plane_id
] = fifo_size
* rate
/ total_rate
;
1686 fifo_left
-= fifo_state
->plane
[plane_id
];
1689 fifo_state
->plane
[PLANE_SPRITE0
] += sprite0_fifo_extra
;
1690 fifo_left
-= sprite0_fifo_extra
;
1692 fifo_state
->plane
[PLANE_CURSOR
] = 63;
1694 fifo_extra
= DIV_ROUND_UP(fifo_left
, num_active_planes
?: 1);
1696 /* spread the remainder evenly */
1697 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1703 if ((active_planes
& BIT(plane_id
)) == 0)
1706 plane_extra
= min(fifo_extra
, fifo_left
);
1707 fifo_state
->plane
[plane_id
] += plane_extra
;
1708 fifo_left
-= plane_extra
;
1711 WARN_ON(active_planes
!= 0 && fifo_left
!= 0);
1713 /* give it all to the first plane if none are active */
1714 if (active_planes
== 0) {
1715 WARN_ON(fifo_left
!= fifo_size
);
1716 fifo_state
->plane
[PLANE_PRIMARY
] = fifo_left
;
1722 /* mark all levels starting from 'level' as invalid */
1723 static void vlv_invalidate_wms(struct intel_crtc
*crtc
,
1724 struct vlv_wm_state
*wm_state
, int level
)
1726 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1728 for (; level
< intel_wm_num_levels(dev_priv
); level
++) {
1729 enum plane_id plane_id
;
1731 for_each_plane_id_on_crtc(crtc
, plane_id
)
1732 wm_state
->wm
[level
].plane
[plane_id
] = USHRT_MAX
;
1734 wm_state
->sr
[level
].cursor
= USHRT_MAX
;
1735 wm_state
->sr
[level
].plane
= USHRT_MAX
;
1739 static u16
vlv_invert_wm_value(u16 wm
, u16 fifo_size
)
1744 return fifo_size
- wm
;
1748 * Starting from 'level' set all higher
1749 * levels to 'value' in the "raw" watermarks.
1751 static bool vlv_raw_plane_wm_set(struct intel_crtc_state
*crtc_state
,
1752 int level
, enum plane_id plane_id
, u16 value
)
1754 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1755 int num_levels
= intel_wm_num_levels(dev_priv
);
1758 for (; level
< num_levels
; level
++) {
1759 struct g4x_pipe_wm
*raw
= &crtc_state
->wm
.vlv
.raw
[level
];
1761 dirty
|= raw
->plane
[plane_id
] != value
;
1762 raw
->plane
[plane_id
] = value
;
1768 static bool vlv_raw_plane_wm_compute(struct intel_crtc_state
*crtc_state
,
1769 const struct intel_plane_state
*plane_state
)
1771 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
1772 enum plane_id plane_id
= plane
->id
;
1773 int num_levels
= intel_wm_num_levels(to_i915(plane
->base
.dev
));
1777 if (!intel_wm_plane_visible(crtc_state
, plane_state
)) {
1778 dirty
|= vlv_raw_plane_wm_set(crtc_state
, 0, plane_id
, 0);
1782 for (level
= 0; level
< num_levels
; level
++) {
1783 struct g4x_pipe_wm
*raw
= &crtc_state
->wm
.vlv
.raw
[level
];
1784 int wm
= vlv_compute_wm_level(crtc_state
, plane_state
, level
);
1785 int max_wm
= plane_id
== PLANE_CURSOR
? 63 : 511;
1790 dirty
|= raw
->plane
[plane_id
] != wm
;
1791 raw
->plane
[plane_id
] = wm
;
1794 /* mark all higher levels as invalid */
1795 dirty
|= vlv_raw_plane_wm_set(crtc_state
, level
, plane_id
, USHRT_MAX
);
1799 DRM_DEBUG_KMS("%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n",
1801 crtc_state
->wm
.vlv
.raw
[VLV_WM_LEVEL_PM2
].plane
[plane_id
],
1802 crtc_state
->wm
.vlv
.raw
[VLV_WM_LEVEL_PM5
].plane
[plane_id
],
1803 crtc_state
->wm
.vlv
.raw
[VLV_WM_LEVEL_DDR_DVFS
].plane
[plane_id
]);
1808 static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state
*crtc_state
,
1809 enum plane_id plane_id
, int level
)
1811 const struct g4x_pipe_wm
*raw
=
1812 &crtc_state
->wm
.vlv
.raw
[level
];
1813 const struct vlv_fifo_state
*fifo_state
=
1814 &crtc_state
->wm
.vlv
.fifo_state
;
1816 return raw
->plane
[plane_id
] <= fifo_state
->plane
[plane_id
];
1819 static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state
*crtc_state
, int level
)
1821 return vlv_raw_plane_wm_is_valid(crtc_state
, PLANE_PRIMARY
, level
) &&
1822 vlv_raw_plane_wm_is_valid(crtc_state
, PLANE_SPRITE0
, level
) &&
1823 vlv_raw_plane_wm_is_valid(crtc_state
, PLANE_SPRITE1
, level
) &&
1824 vlv_raw_plane_wm_is_valid(crtc_state
, PLANE_CURSOR
, level
);
1827 static int vlv_compute_pipe_wm(struct intel_crtc_state
*crtc_state
)
1829 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1830 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1831 struct intel_atomic_state
*state
=
1832 to_intel_atomic_state(crtc_state
->base
.state
);
1833 struct vlv_wm_state
*wm_state
= &crtc_state
->wm
.vlv
.optimal
;
1834 const struct vlv_fifo_state
*fifo_state
=
1835 &crtc_state
->wm
.vlv
.fifo_state
;
1836 int num_active_planes
= hweight32(crtc_state
->active_planes
&
1837 ~BIT(PLANE_CURSOR
));
1838 bool needs_modeset
= drm_atomic_crtc_needs_modeset(&crtc_state
->base
);
1839 const struct intel_plane_state
*old_plane_state
;
1840 const struct intel_plane_state
*new_plane_state
;
1841 struct intel_plane
*plane
;
1842 enum plane_id plane_id
;
1844 unsigned int dirty
= 0;
1846 for_each_oldnew_intel_plane_in_state(state
, plane
,
1848 new_plane_state
, i
) {
1849 if (new_plane_state
->base
.crtc
!= &crtc
->base
&&
1850 old_plane_state
->base
.crtc
!= &crtc
->base
)
1853 if (vlv_raw_plane_wm_compute(crtc_state
, new_plane_state
))
1854 dirty
|= BIT(plane
->id
);
1858 * DSPARB registers may have been reset due to the
1859 * power well being turned off. Make sure we restore
1860 * them to a consistent state even if no primary/sprite
1861 * planes are initially active.
1864 crtc_state
->fifo_changed
= true;
1869 /* cursor changes don't warrant a FIFO recompute */
1870 if (dirty
& ~BIT(PLANE_CURSOR
)) {
1871 const struct intel_crtc_state
*old_crtc_state
=
1872 intel_atomic_get_old_crtc_state(state
, crtc
);
1873 const struct vlv_fifo_state
*old_fifo_state
=
1874 &old_crtc_state
->wm
.vlv
.fifo_state
;
1876 ret
= vlv_compute_fifo(crtc_state
);
1880 if (needs_modeset
||
1881 memcmp(old_fifo_state
, fifo_state
,
1882 sizeof(*fifo_state
)) != 0)
1883 crtc_state
->fifo_changed
= true;
1886 /* initially allow all levels */
1887 wm_state
->num_levels
= intel_wm_num_levels(dev_priv
);
1889 * Note that enabling cxsr with no primary/sprite planes
1890 * enabled can wedge the pipe. Hence we only allow cxsr
1891 * with exactly one enabled primary/sprite plane.
1893 wm_state
->cxsr
= crtc
->pipe
!= PIPE_C
&& num_active_planes
== 1;
1895 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1896 const struct g4x_pipe_wm
*raw
= &crtc_state
->wm
.vlv
.raw
[level
];
1897 const int sr_fifo_size
= INTEL_INFO(dev_priv
)->num_pipes
* 512 - 1;
1899 if (!vlv_raw_crtc_wm_is_valid(crtc_state
, level
))
1902 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1903 wm_state
->wm
[level
].plane
[plane_id
] =
1904 vlv_invert_wm_value(raw
->plane
[plane_id
],
1905 fifo_state
->plane
[plane_id
]);
1908 wm_state
->sr
[level
].plane
=
1909 vlv_invert_wm_value(max3(raw
->plane
[PLANE_PRIMARY
],
1910 raw
->plane
[PLANE_SPRITE0
],
1911 raw
->plane
[PLANE_SPRITE1
]),
1914 wm_state
->sr
[level
].cursor
=
1915 vlv_invert_wm_value(raw
->plane
[PLANE_CURSOR
],
1922 /* limit to only levels we can actually handle */
1923 wm_state
->num_levels
= level
;
1925 /* invalidate the higher levels */
1926 vlv_invalidate_wms(crtc
, wm_state
, level
);
1931 #define VLV_FIFO(plane, value) \
1932 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1934 static void vlv_atomic_update_fifo(struct intel_atomic_state
*state
,
1935 struct intel_crtc_state
*crtc_state
)
1937 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1938 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1939 const struct vlv_fifo_state
*fifo_state
=
1940 &crtc_state
->wm
.vlv
.fifo_state
;
1941 int sprite0_start
, sprite1_start
, fifo_size
;
1943 if (!crtc_state
->fifo_changed
)
1946 sprite0_start
= fifo_state
->plane
[PLANE_PRIMARY
];
1947 sprite1_start
= fifo_state
->plane
[PLANE_SPRITE0
] + sprite0_start
;
1948 fifo_size
= fifo_state
->plane
[PLANE_SPRITE1
] + sprite1_start
;
1950 WARN_ON(fifo_state
->plane
[PLANE_CURSOR
] != 63);
1951 WARN_ON(fifo_size
!= 511);
1953 trace_vlv_fifo_size(crtc
, sprite0_start
, sprite1_start
, fifo_size
);
1956 * uncore.lock serves a double purpose here. It allows us to
1957 * use the less expensive I915_{READ,WRITE}_FW() functions, and
1958 * it protects the DSPARB registers from getting clobbered by
1959 * parallel updates from multiple pipes.
1961 * intel_pipe_update_start() has already disabled interrupts
1962 * for us, so a plain spin_lock() is sufficient here.
1964 spin_lock(&dev_priv
->uncore
.lock
);
1966 switch (crtc
->pipe
) {
1967 uint32_t dsparb
, dsparb2
, dsparb3
;
1969 dsparb
= I915_READ_FW(DSPARB
);
1970 dsparb2
= I915_READ_FW(DSPARB2
);
1972 dsparb
&= ~(VLV_FIFO(SPRITEA
, 0xff) |
1973 VLV_FIFO(SPRITEB
, 0xff));
1974 dsparb
|= (VLV_FIFO(SPRITEA
, sprite0_start
) |
1975 VLV_FIFO(SPRITEB
, sprite1_start
));
1977 dsparb2
&= ~(VLV_FIFO(SPRITEA_HI
, 0x1) |
1978 VLV_FIFO(SPRITEB_HI
, 0x1));
1979 dsparb2
|= (VLV_FIFO(SPRITEA_HI
, sprite0_start
>> 8) |
1980 VLV_FIFO(SPRITEB_HI
, sprite1_start
>> 8));
1982 I915_WRITE_FW(DSPARB
, dsparb
);
1983 I915_WRITE_FW(DSPARB2
, dsparb2
);
1986 dsparb
= I915_READ_FW(DSPARB
);
1987 dsparb2
= I915_READ_FW(DSPARB2
);
1989 dsparb
&= ~(VLV_FIFO(SPRITEC
, 0xff) |
1990 VLV_FIFO(SPRITED
, 0xff));
1991 dsparb
|= (VLV_FIFO(SPRITEC
, sprite0_start
) |
1992 VLV_FIFO(SPRITED
, sprite1_start
));
1994 dsparb2
&= ~(VLV_FIFO(SPRITEC_HI
, 0xff) |
1995 VLV_FIFO(SPRITED_HI
, 0xff));
1996 dsparb2
|= (VLV_FIFO(SPRITEC_HI
, sprite0_start
>> 8) |
1997 VLV_FIFO(SPRITED_HI
, sprite1_start
>> 8));
1999 I915_WRITE_FW(DSPARB
, dsparb
);
2000 I915_WRITE_FW(DSPARB2
, dsparb2
);
2003 dsparb3
= I915_READ_FW(DSPARB3
);
2004 dsparb2
= I915_READ_FW(DSPARB2
);
2006 dsparb3
&= ~(VLV_FIFO(SPRITEE
, 0xff) |
2007 VLV_FIFO(SPRITEF
, 0xff));
2008 dsparb3
|= (VLV_FIFO(SPRITEE
, sprite0_start
) |
2009 VLV_FIFO(SPRITEF
, sprite1_start
));
2011 dsparb2
&= ~(VLV_FIFO(SPRITEE_HI
, 0xff) |
2012 VLV_FIFO(SPRITEF_HI
, 0xff));
2013 dsparb2
|= (VLV_FIFO(SPRITEE_HI
, sprite0_start
>> 8) |
2014 VLV_FIFO(SPRITEF_HI
, sprite1_start
>> 8));
2016 I915_WRITE_FW(DSPARB3
, dsparb3
);
2017 I915_WRITE_FW(DSPARB2
, dsparb2
);
2023 POSTING_READ_FW(DSPARB
);
2025 spin_unlock(&dev_priv
->uncore
.lock
);
2030 static int vlv_compute_intermediate_wm(struct drm_device
*dev
,
2031 struct intel_crtc
*crtc
,
2032 struct intel_crtc_state
*crtc_state
)
2034 struct vlv_wm_state
*intermediate
= &crtc_state
->wm
.vlv
.intermediate
;
2035 const struct vlv_wm_state
*optimal
= &crtc_state
->wm
.vlv
.optimal
;
2036 const struct vlv_wm_state
*active
= &crtc
->wm
.active
.vlv
;
2039 intermediate
->num_levels
= min(optimal
->num_levels
, active
->num_levels
);
2040 intermediate
->cxsr
= optimal
->cxsr
&& active
->cxsr
&&
2041 !crtc_state
->disable_cxsr
;
2043 for (level
= 0; level
< intermediate
->num_levels
; level
++) {
2044 enum plane_id plane_id
;
2046 for_each_plane_id_on_crtc(crtc
, plane_id
) {
2047 intermediate
->wm
[level
].plane
[plane_id
] =
2048 min(optimal
->wm
[level
].plane
[plane_id
],
2049 active
->wm
[level
].plane
[plane_id
]);
2052 intermediate
->sr
[level
].plane
= min(optimal
->sr
[level
].plane
,
2053 active
->sr
[level
].plane
);
2054 intermediate
->sr
[level
].cursor
= min(optimal
->sr
[level
].cursor
,
2055 active
->sr
[level
].cursor
);
2058 vlv_invalidate_wms(crtc
, intermediate
, level
);
2061 * If our intermediate WM are identical to the final WM, then we can
2062 * omit the post-vblank programming; only update if it's different.
2064 if (memcmp(intermediate
, optimal
, sizeof(*intermediate
)) != 0)
2065 crtc_state
->wm
.need_postvbl_update
= true;
2070 static void vlv_merge_wm(struct drm_i915_private
*dev_priv
,
2071 struct vlv_wm_values
*wm
)
2073 struct intel_crtc
*crtc
;
2074 int num_active_crtcs
= 0;
2076 wm
->level
= dev_priv
->wm
.max_level
;
2079 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
2080 const struct vlv_wm_state
*wm_state
= &crtc
->wm
.active
.vlv
;
2085 if (!wm_state
->cxsr
)
2089 wm
->level
= min_t(int, wm
->level
, wm_state
->num_levels
- 1);
2092 if (num_active_crtcs
!= 1)
2095 if (num_active_crtcs
> 1)
2096 wm
->level
= VLV_WM_LEVEL_PM2
;
2098 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
2099 const struct vlv_wm_state
*wm_state
= &crtc
->wm
.active
.vlv
;
2100 enum pipe pipe
= crtc
->pipe
;
2102 wm
->pipe
[pipe
] = wm_state
->wm
[wm
->level
];
2103 if (crtc
->active
&& wm
->cxsr
)
2104 wm
->sr
= wm_state
->sr
[wm
->level
];
2106 wm
->ddl
[pipe
].plane
[PLANE_PRIMARY
] = DDL_PRECISION_HIGH
| 2;
2107 wm
->ddl
[pipe
].plane
[PLANE_SPRITE0
] = DDL_PRECISION_HIGH
| 2;
2108 wm
->ddl
[pipe
].plane
[PLANE_SPRITE1
] = DDL_PRECISION_HIGH
| 2;
2109 wm
->ddl
[pipe
].plane
[PLANE_CURSOR
] = DDL_PRECISION_HIGH
| 2;
2113 static void vlv_program_watermarks(struct drm_i915_private
*dev_priv
)
2115 struct vlv_wm_values
*old_wm
= &dev_priv
->wm
.vlv
;
2116 struct vlv_wm_values new_wm
= {};
2118 vlv_merge_wm(dev_priv
, &new_wm
);
2120 if (memcmp(old_wm
, &new_wm
, sizeof(new_wm
)) == 0)
2123 if (is_disabling(old_wm
->level
, new_wm
.level
, VLV_WM_LEVEL_DDR_DVFS
))
2124 chv_set_memory_dvfs(dev_priv
, false);
2126 if (is_disabling(old_wm
->level
, new_wm
.level
, VLV_WM_LEVEL_PM5
))
2127 chv_set_memory_pm5(dev_priv
, false);
2129 if (is_disabling(old_wm
->cxsr
, new_wm
.cxsr
, true))
2130 _intel_set_memory_cxsr(dev_priv
, false);
2132 vlv_write_wm_values(dev_priv
, &new_wm
);
2134 if (is_enabling(old_wm
->cxsr
, new_wm
.cxsr
, true))
2135 _intel_set_memory_cxsr(dev_priv
, true);
2137 if (is_enabling(old_wm
->level
, new_wm
.level
, VLV_WM_LEVEL_PM5
))
2138 chv_set_memory_pm5(dev_priv
, true);
2140 if (is_enabling(old_wm
->level
, new_wm
.level
, VLV_WM_LEVEL_DDR_DVFS
))
2141 chv_set_memory_dvfs(dev_priv
, true);
2146 static void vlv_initial_watermarks(struct intel_atomic_state
*state
,
2147 struct intel_crtc_state
*crtc_state
)
2149 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
2150 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
2152 mutex_lock(&dev_priv
->wm
.wm_mutex
);
2153 crtc
->wm
.active
.vlv
= crtc_state
->wm
.vlv
.intermediate
;
2154 vlv_program_watermarks(dev_priv
);
2155 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
2158 static void vlv_optimize_watermarks(struct intel_atomic_state
*state
,
2159 struct intel_crtc_state
*crtc_state
)
2161 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
2162 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
2164 if (!crtc_state
->wm
.need_postvbl_update
)
2167 mutex_lock(&dev_priv
->wm
.wm_mutex
);
2168 intel_crtc
->wm
.active
.vlv
= crtc_state
->wm
.vlv
.optimal
;
2169 vlv_program_watermarks(dev_priv
);
2170 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
2173 static void i965_update_wm(struct intel_crtc
*unused_crtc
)
2175 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
2176 struct intel_crtc
*crtc
;
2181 /* Calc sr entries for one plane configs */
2182 crtc
= single_enabled_crtc(dev_priv
);
2184 /* self-refresh has much higher latency */
2185 static const int sr_latency_ns
= 12000;
2186 const struct drm_display_mode
*adjusted_mode
=
2187 &crtc
->config
->base
.adjusted_mode
;
2188 const struct drm_framebuffer
*fb
=
2189 crtc
->base
.primary
->state
->fb
;
2190 int clock
= adjusted_mode
->crtc_clock
;
2191 int htotal
= adjusted_mode
->crtc_htotal
;
2192 int hdisplay
= crtc
->config
->pipe_src_w
;
2193 int cpp
= fb
->format
->cpp
[0];
2196 entries
= intel_wm_method2(clock
, htotal
,
2197 hdisplay
, cpp
, sr_latency_ns
/ 100);
2198 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
2199 srwm
= I965_FIFO_SIZE
- entries
;
2203 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
2206 entries
= intel_wm_method2(clock
, htotal
,
2207 crtc
->base
.cursor
->state
->crtc_w
, 4,
2208 sr_latency_ns
/ 100);
2209 entries
= DIV_ROUND_UP(entries
,
2210 i965_cursor_wm_info
.cacheline_size
) +
2211 i965_cursor_wm_info
.guard_size
;
2213 cursor_sr
= i965_cursor_wm_info
.fifo_size
- entries
;
2214 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
2215 cursor_sr
= i965_cursor_wm_info
.max_wm
;
2217 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
2218 "cursor %d\n", srwm
, cursor_sr
);
2220 cxsr_enabled
= true;
2222 cxsr_enabled
= false;
2223 /* Turn off self refresh if both pipes are enabled */
2224 intel_set_memory_cxsr(dev_priv
, false);
2227 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2230 /* 965 has limitations... */
2231 I915_WRITE(DSPFW1
, FW_WM(srwm
, SR
) |
2235 I915_WRITE(DSPFW2
, FW_WM(8, CURSORA
) |
2236 FW_WM(8, PLANEC_OLD
));
2237 /* update cursor SR watermark */
2238 I915_WRITE(DSPFW3
, FW_WM(cursor_sr
, CURSOR_SR
));
2241 intel_set_memory_cxsr(dev_priv
, true);
2246 static void i9xx_update_wm(struct intel_crtc
*unused_crtc
)
2248 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
2249 const struct intel_watermark_params
*wm_info
;
2254 int planea_wm
, planeb_wm
;
2255 struct intel_crtc
*crtc
, *enabled
= NULL
;
2257 if (IS_I945GM(dev_priv
))
2258 wm_info
= &i945_wm_info
;
2259 else if (!IS_GEN2(dev_priv
))
2260 wm_info
= &i915_wm_info
;
2262 wm_info
= &i830_a_wm_info
;
2264 fifo_size
= dev_priv
->display
.get_fifo_size(dev_priv
, 0);
2265 crtc
= intel_get_crtc_for_plane(dev_priv
, 0);
2266 if (intel_crtc_active(crtc
)) {
2267 const struct drm_display_mode
*adjusted_mode
=
2268 &crtc
->config
->base
.adjusted_mode
;
2269 const struct drm_framebuffer
*fb
=
2270 crtc
->base
.primary
->state
->fb
;
2273 if (IS_GEN2(dev_priv
))
2276 cpp
= fb
->format
->cpp
[0];
2278 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
2279 wm_info
, fifo_size
, cpp
,
2280 pessimal_latency_ns
);
2283 planea_wm
= fifo_size
- wm_info
->guard_size
;
2284 if (planea_wm
> (long)wm_info
->max_wm
)
2285 planea_wm
= wm_info
->max_wm
;
2288 if (IS_GEN2(dev_priv
))
2289 wm_info
= &i830_bc_wm_info
;
2291 fifo_size
= dev_priv
->display
.get_fifo_size(dev_priv
, 1);
2292 crtc
= intel_get_crtc_for_plane(dev_priv
, 1);
2293 if (intel_crtc_active(crtc
)) {
2294 const struct drm_display_mode
*adjusted_mode
=
2295 &crtc
->config
->base
.adjusted_mode
;
2296 const struct drm_framebuffer
*fb
=
2297 crtc
->base
.primary
->state
->fb
;
2300 if (IS_GEN2(dev_priv
))
2303 cpp
= fb
->format
->cpp
[0];
2305 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
2306 wm_info
, fifo_size
, cpp
,
2307 pessimal_latency_ns
);
2308 if (enabled
== NULL
)
2313 planeb_wm
= fifo_size
- wm_info
->guard_size
;
2314 if (planeb_wm
> (long)wm_info
->max_wm
)
2315 planeb_wm
= wm_info
->max_wm
;
2318 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
2320 if (IS_I915GM(dev_priv
) && enabled
) {
2321 struct drm_i915_gem_object
*obj
;
2323 obj
= intel_fb_obj(enabled
->base
.primary
->state
->fb
);
2325 /* self-refresh seems busted with untiled */
2326 if (!i915_gem_object_is_tiled(obj
))
2331 * Overlay gets an aggressive default since video jitter is bad.
2335 /* Play safe and disable self-refresh before adjusting watermarks. */
2336 intel_set_memory_cxsr(dev_priv
, false);
2338 /* Calc sr entries for one plane configs */
2339 if (HAS_FW_BLC(dev_priv
) && enabled
) {
2340 /* self-refresh has much higher latency */
2341 static const int sr_latency_ns
= 6000;
2342 const struct drm_display_mode
*adjusted_mode
=
2343 &enabled
->config
->base
.adjusted_mode
;
2344 const struct drm_framebuffer
*fb
=
2345 enabled
->base
.primary
->state
->fb
;
2346 int clock
= adjusted_mode
->crtc_clock
;
2347 int htotal
= adjusted_mode
->crtc_htotal
;
2348 int hdisplay
= enabled
->config
->pipe_src_w
;
2352 if (IS_I915GM(dev_priv
) || IS_I945GM(dev_priv
))
2355 cpp
= fb
->format
->cpp
[0];
2357 entries
= intel_wm_method2(clock
, htotal
, hdisplay
, cpp
,
2358 sr_latency_ns
/ 100);
2359 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
2360 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
2361 srwm
= wm_info
->fifo_size
- entries
;
2365 if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
))
2366 I915_WRITE(FW_BLC_SELF
,
2367 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
2369 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
2372 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2373 planea_wm
, planeb_wm
, cwm
, srwm
);
2375 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
2376 fwater_hi
= (cwm
& 0x1f);
2378 /* Set request length to 8 cachelines per fetch */
2379 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
2380 fwater_hi
= fwater_hi
| (1 << 8);
2382 I915_WRITE(FW_BLC
, fwater_lo
);
2383 I915_WRITE(FW_BLC2
, fwater_hi
);
2386 intel_set_memory_cxsr(dev_priv
, true);
2389 static void i845_update_wm(struct intel_crtc
*unused_crtc
)
2391 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
2392 struct intel_crtc
*crtc
;
2393 const struct drm_display_mode
*adjusted_mode
;
2397 crtc
= single_enabled_crtc(dev_priv
);
2401 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
2402 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
2404 dev_priv
->display
.get_fifo_size(dev_priv
, 0),
2405 4, pessimal_latency_ns
);
2406 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
2407 fwater_lo
|= (3<<8) | planea_wm
;
2409 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
2411 I915_WRITE(FW_BLC
, fwater_lo
);
2414 /* latency must be in 0.1us units. */
2415 static unsigned int ilk_wm_method1(unsigned int pixel_rate
,
2417 unsigned int latency
)
2421 ret
= intel_wm_method1(pixel_rate
, cpp
, latency
);
2422 ret
= DIV_ROUND_UP(ret
, 64) + 2;
2427 /* latency must be in 0.1us units. */
2428 static unsigned int ilk_wm_method2(unsigned int pixel_rate
,
2429 unsigned int htotal
,
2432 unsigned int latency
)
2436 ret
= intel_wm_method2(pixel_rate
, htotal
,
2437 width
, cpp
, latency
);
2438 ret
= DIV_ROUND_UP(ret
, 64) + 2;
2443 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
2447 * Neither of these should be possible since this function shouldn't be
2448 * called if the CRTC is off or the plane is invisible. But let's be
2449 * extra paranoid to avoid a potential divide-by-zero if we screw up
2450 * elsewhere in the driver.
2454 if (WARN_ON(!horiz_pixels
))
2457 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* cpp
) + 2;
2460 struct ilk_wm_maximums
{
2468 * For both WM_PIPE and WM_LP.
2469 * mem_value must be in 0.1us units.
2471 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state
*cstate
,
2472 const struct intel_plane_state
*pstate
,
2476 uint32_t method1
, method2
;
2479 if (!intel_wm_plane_visible(cstate
, pstate
))
2482 cpp
= pstate
->base
.fb
->format
->cpp
[0];
2484 method1
= ilk_wm_method1(cstate
->pixel_rate
, cpp
, mem_value
);
2489 method2
= ilk_wm_method2(cstate
->pixel_rate
,
2490 cstate
->base
.adjusted_mode
.crtc_htotal
,
2491 drm_rect_width(&pstate
->base
.dst
),
2494 return min(method1
, method2
);
2498 * For both WM_PIPE and WM_LP.
2499 * mem_value must be in 0.1us units.
2501 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state
*cstate
,
2502 const struct intel_plane_state
*pstate
,
2505 uint32_t method1
, method2
;
2508 if (!intel_wm_plane_visible(cstate
, pstate
))
2511 cpp
= pstate
->base
.fb
->format
->cpp
[0];
2513 method1
= ilk_wm_method1(cstate
->pixel_rate
, cpp
, mem_value
);
2514 method2
= ilk_wm_method2(cstate
->pixel_rate
,
2515 cstate
->base
.adjusted_mode
.crtc_htotal
,
2516 drm_rect_width(&pstate
->base
.dst
),
2518 return min(method1
, method2
);
2522 * For both WM_PIPE and WM_LP.
2523 * mem_value must be in 0.1us units.
2525 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state
*cstate
,
2526 const struct intel_plane_state
*pstate
,
2531 if (!intel_wm_plane_visible(cstate
, pstate
))
2534 cpp
= pstate
->base
.fb
->format
->cpp
[0];
2536 return ilk_wm_method2(cstate
->pixel_rate
,
2537 cstate
->base
.adjusted_mode
.crtc_htotal
,
2538 pstate
->base
.crtc_w
, cpp
, mem_value
);
2541 /* Only for WM_LP. */
2542 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state
*cstate
,
2543 const struct intel_plane_state
*pstate
,
2548 if (!intel_wm_plane_visible(cstate
, pstate
))
2551 cpp
= pstate
->base
.fb
->format
->cpp
[0];
2553 return ilk_wm_fbc(pri_val
, drm_rect_width(&pstate
->base
.dst
), cpp
);
2557 ilk_display_fifo_size(const struct drm_i915_private
*dev_priv
)
2559 if (INTEL_GEN(dev_priv
) >= 8)
2561 else if (INTEL_GEN(dev_priv
) >= 7)
2568 ilk_plane_wm_reg_max(const struct drm_i915_private
*dev_priv
,
2569 int level
, bool is_sprite
)
2571 if (INTEL_GEN(dev_priv
) >= 8)
2572 /* BDW primary/sprite plane watermarks */
2573 return level
== 0 ? 255 : 2047;
2574 else if (INTEL_GEN(dev_priv
) >= 7)
2575 /* IVB/HSW primary/sprite plane watermarks */
2576 return level
== 0 ? 127 : 1023;
2577 else if (!is_sprite
)
2578 /* ILK/SNB primary plane watermarks */
2579 return level
== 0 ? 127 : 511;
2581 /* ILK/SNB sprite plane watermarks */
2582 return level
== 0 ? 63 : 255;
2586 ilk_cursor_wm_reg_max(const struct drm_i915_private
*dev_priv
, int level
)
2588 if (INTEL_GEN(dev_priv
) >= 7)
2589 return level
== 0 ? 63 : 255;
2591 return level
== 0 ? 31 : 63;
2594 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private
*dev_priv
)
2596 if (INTEL_GEN(dev_priv
) >= 8)
2602 /* Calculate the maximum primary/sprite plane watermark */
2603 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
2605 const struct intel_wm_config
*config
,
2606 enum intel_ddb_partitioning ddb_partitioning
,
2609 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2610 unsigned int fifo_size
= ilk_display_fifo_size(dev_priv
);
2612 /* if sprites aren't enabled, sprites get nothing */
2613 if (is_sprite
&& !config
->sprites_enabled
)
2616 /* HSW allows LP1+ watermarks even with multiple pipes */
2617 if (level
== 0 || config
->num_pipes_active
> 1) {
2618 fifo_size
/= INTEL_INFO(dev_priv
)->num_pipes
;
2621 * For some reason the non self refresh
2622 * FIFO size is only half of the self
2623 * refresh FIFO size on ILK/SNB.
2625 if (INTEL_GEN(dev_priv
) <= 6)
2629 if (config
->sprites_enabled
) {
2630 /* level 0 is always calculated with 1:1 split */
2631 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
2640 /* clamp to max that the registers can hold */
2641 return min(fifo_size
, ilk_plane_wm_reg_max(dev_priv
, level
, is_sprite
));
2644 /* Calculate the maximum cursor plane watermark */
2645 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
2647 const struct intel_wm_config
*config
)
2649 /* HSW LP1+ watermarks w/ multiple pipes */
2650 if (level
> 0 && config
->num_pipes_active
> 1)
2653 /* otherwise just report max that registers can hold */
2654 return ilk_cursor_wm_reg_max(to_i915(dev
), level
);
2657 static void ilk_compute_wm_maximums(const struct drm_device
*dev
,
2659 const struct intel_wm_config
*config
,
2660 enum intel_ddb_partitioning ddb_partitioning
,
2661 struct ilk_wm_maximums
*max
)
2663 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
2664 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
2665 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
2666 max
->fbc
= ilk_fbc_wm_reg_max(to_i915(dev
));
2669 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private
*dev_priv
,
2671 struct ilk_wm_maximums
*max
)
2673 max
->pri
= ilk_plane_wm_reg_max(dev_priv
, level
, false);
2674 max
->spr
= ilk_plane_wm_reg_max(dev_priv
, level
, true);
2675 max
->cur
= ilk_cursor_wm_reg_max(dev_priv
, level
);
2676 max
->fbc
= ilk_fbc_wm_reg_max(dev_priv
);
2679 static bool ilk_validate_wm_level(int level
,
2680 const struct ilk_wm_maximums
*max
,
2681 struct intel_wm_level
*result
)
2685 /* already determined to be invalid? */
2686 if (!result
->enable
)
2689 result
->enable
= result
->pri_val
<= max
->pri
&&
2690 result
->spr_val
<= max
->spr
&&
2691 result
->cur_val
<= max
->cur
;
2693 ret
= result
->enable
;
2696 * HACK until we can pre-compute everything,
2697 * and thus fail gracefully if LP0 watermarks
2700 if (level
== 0 && !result
->enable
) {
2701 if (result
->pri_val
> max
->pri
)
2702 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2703 level
, result
->pri_val
, max
->pri
);
2704 if (result
->spr_val
> max
->spr
)
2705 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2706 level
, result
->spr_val
, max
->spr
);
2707 if (result
->cur_val
> max
->cur
)
2708 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2709 level
, result
->cur_val
, max
->cur
);
2711 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
2712 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
2713 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
2714 result
->enable
= true;
2720 static void ilk_compute_wm_level(const struct drm_i915_private
*dev_priv
,
2721 const struct intel_crtc
*intel_crtc
,
2723 struct intel_crtc_state
*cstate
,
2724 struct intel_plane_state
*pristate
,
2725 struct intel_plane_state
*sprstate
,
2726 struct intel_plane_state
*curstate
,
2727 struct intel_wm_level
*result
)
2729 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
2730 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
2731 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
2733 /* WM1+ latency values stored in 0.5us units */
2741 result
->pri_val
= ilk_compute_pri_wm(cstate
, pristate
,
2742 pri_latency
, level
);
2743 result
->fbc_val
= ilk_compute_fbc_wm(cstate
, pristate
, result
->pri_val
);
2747 result
->spr_val
= ilk_compute_spr_wm(cstate
, sprstate
, spr_latency
);
2750 result
->cur_val
= ilk_compute_cur_wm(cstate
, curstate
, cur_latency
);
2752 result
->enable
= true;
2756 hsw_compute_linetime_wm(const struct intel_crtc_state
*cstate
)
2758 const struct intel_atomic_state
*intel_state
=
2759 to_intel_atomic_state(cstate
->base
.state
);
2760 const struct drm_display_mode
*adjusted_mode
=
2761 &cstate
->base
.adjusted_mode
;
2762 u32 linetime
, ips_linetime
;
2764 if (!cstate
->base
.active
)
2766 if (WARN_ON(adjusted_mode
->crtc_clock
== 0))
2768 if (WARN_ON(intel_state
->cdclk
.logical
.cdclk
== 0))
2771 /* The WM are computed with base on how long it takes to fill a single
2772 * row at the given clock rate, multiplied by 8.
2774 linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2775 adjusted_mode
->crtc_clock
);
2776 ips_linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2777 intel_state
->cdclk
.logical
.cdclk
);
2779 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2780 PIPE_WM_LINETIME_TIME(linetime
);
2783 static void intel_read_wm_latency(struct drm_i915_private
*dev_priv
,
2786 if (INTEL_GEN(dev_priv
) >= 9) {
2789 int level
, max_level
= ilk_wm_max_level(dev_priv
);
2791 /* read the first set of memory latencies[0:3] */
2792 val
= 0; /* data0 to be programmed to 0 for first set */
2793 mutex_lock(&dev_priv
->rps
.hw_lock
);
2794 ret
= sandybridge_pcode_read(dev_priv
,
2795 GEN9_PCODE_READ_MEM_LATENCY
,
2797 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2800 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2804 wm
[0] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2805 wm
[1] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2806 GEN9_MEM_LATENCY_LEVEL_MASK
;
2807 wm
[2] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2808 GEN9_MEM_LATENCY_LEVEL_MASK
;
2809 wm
[3] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2810 GEN9_MEM_LATENCY_LEVEL_MASK
;
2812 /* read the second set of memory latencies[4:7] */
2813 val
= 1; /* data0 to be programmed to 1 for second set */
2814 mutex_lock(&dev_priv
->rps
.hw_lock
);
2815 ret
= sandybridge_pcode_read(dev_priv
,
2816 GEN9_PCODE_READ_MEM_LATENCY
,
2818 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2820 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2824 wm
[4] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2825 wm
[5] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2826 GEN9_MEM_LATENCY_LEVEL_MASK
;
2827 wm
[6] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2828 GEN9_MEM_LATENCY_LEVEL_MASK
;
2829 wm
[7] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2830 GEN9_MEM_LATENCY_LEVEL_MASK
;
2833 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2834 * need to be disabled. We make sure to sanitize the values out
2835 * of the punit to satisfy this requirement.
2837 for (level
= 1; level
<= max_level
; level
++) {
2838 if (wm
[level
] == 0) {
2839 for (i
= level
+ 1; i
<= max_level
; i
++)
2846 * WaWmMemoryReadLatency:skl+,glk
2848 * punit doesn't take into account the read latency so we need
2849 * to add 2us to the various latency levels we retrieve from the
2850 * punit when level 0 response data us 0us.
2854 for (level
= 1; level
<= max_level
; level
++) {
2861 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2862 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2864 wm
[0] = (sskpd
>> 56) & 0xFF;
2866 wm
[0] = sskpd
& 0xF;
2867 wm
[1] = (sskpd
>> 4) & 0xFF;
2868 wm
[2] = (sskpd
>> 12) & 0xFF;
2869 wm
[3] = (sskpd
>> 20) & 0x1FF;
2870 wm
[4] = (sskpd
>> 32) & 0x1FF;
2871 } else if (INTEL_GEN(dev_priv
) >= 6) {
2872 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
2874 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
2875 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
2876 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
2877 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
2878 } else if (INTEL_GEN(dev_priv
) >= 5) {
2879 uint32_t mltr
= I915_READ(MLTR_ILK
);
2881 /* ILK primary LP0 latency is 700 ns */
2883 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
2884 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
2886 MISSING_CASE(INTEL_DEVID(dev_priv
));
2890 static void intel_fixup_spr_wm_latency(struct drm_i915_private
*dev_priv
,
2893 /* ILK sprite LP0 latency is 1300 ns */
2894 if (IS_GEN5(dev_priv
))
2898 static void intel_fixup_cur_wm_latency(struct drm_i915_private
*dev_priv
,
2901 /* ILK cursor LP0 latency is 1300 ns */
2902 if (IS_GEN5(dev_priv
))
2905 /* WaDoubleCursorLP3Latency:ivb */
2906 if (IS_IVYBRIDGE(dev_priv
))
2910 int ilk_wm_max_level(const struct drm_i915_private
*dev_priv
)
2912 /* how many WM levels are we expecting */
2913 if (INTEL_GEN(dev_priv
) >= 9)
2915 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
2917 else if (INTEL_GEN(dev_priv
) >= 6)
2923 static void intel_print_wm_latency(struct drm_i915_private
*dev_priv
,
2925 const uint16_t wm
[8])
2927 int level
, max_level
= ilk_wm_max_level(dev_priv
);
2929 for (level
= 0; level
<= max_level
; level
++) {
2930 unsigned int latency
= wm
[level
];
2933 DRM_ERROR("%s WM%d latency not provided\n",
2939 * - latencies are in us on gen9.
2940 * - before then, WM1+ latency values are in 0.5us units
2942 if (INTEL_GEN(dev_priv
) >= 9)
2947 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2948 name
, level
, wm
[level
],
2949 latency
/ 10, latency
% 10);
2953 static bool ilk_increase_wm_latency(struct drm_i915_private
*dev_priv
,
2954 uint16_t wm
[5], uint16_t min
)
2956 int level
, max_level
= ilk_wm_max_level(dev_priv
);
2961 wm
[0] = max(wm
[0], min
);
2962 for (level
= 1; level
<= max_level
; level
++)
2963 wm
[level
] = max_t(uint16_t, wm
[level
], DIV_ROUND_UP(min
, 5));
2968 static void snb_wm_latency_quirk(struct drm_i915_private
*dev_priv
)
2973 * The BIOS provided WM memory latency values are often
2974 * inadequate for high resolution displays. Adjust them.
2976 changed
= ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
, 12) |
2977 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
, 12) |
2978 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
, 12);
2983 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2984 intel_print_wm_latency(dev_priv
, "Primary", dev_priv
->wm
.pri_latency
);
2985 intel_print_wm_latency(dev_priv
, "Sprite", dev_priv
->wm
.spr_latency
);
2986 intel_print_wm_latency(dev_priv
, "Cursor", dev_priv
->wm
.cur_latency
);
2989 static void ilk_setup_wm_latency(struct drm_i915_private
*dev_priv
)
2991 intel_read_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
);
2993 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
2994 sizeof(dev_priv
->wm
.pri_latency
));
2995 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
2996 sizeof(dev_priv
->wm
.pri_latency
));
2998 intel_fixup_spr_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
);
2999 intel_fixup_cur_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
);
3001 intel_print_wm_latency(dev_priv
, "Primary", dev_priv
->wm
.pri_latency
);
3002 intel_print_wm_latency(dev_priv
, "Sprite", dev_priv
->wm
.spr_latency
);
3003 intel_print_wm_latency(dev_priv
, "Cursor", dev_priv
->wm
.cur_latency
);
3005 if (IS_GEN6(dev_priv
))
3006 snb_wm_latency_quirk(dev_priv
);
3009 static void skl_setup_wm_latency(struct drm_i915_private
*dev_priv
)
3011 intel_read_wm_latency(dev_priv
, dev_priv
->wm
.skl_latency
);
3012 intel_print_wm_latency(dev_priv
, "Gen9 Plane", dev_priv
->wm
.skl_latency
);
3015 static bool ilk_validate_pipe_wm(struct drm_device
*dev
,
3016 struct intel_pipe_wm
*pipe_wm
)
3018 /* LP0 watermark maximums depend on this pipe alone */
3019 const struct intel_wm_config config
= {
3020 .num_pipes_active
= 1,
3021 .sprites_enabled
= pipe_wm
->sprites_enabled
,
3022 .sprites_scaled
= pipe_wm
->sprites_scaled
,
3024 struct ilk_wm_maximums max
;
3026 /* LP0 watermarks always use 1/2 DDB partitioning */
3027 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
3029 /* At least LP0 must be valid */
3030 if (!ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0])) {
3031 DRM_DEBUG_KMS("LP0 watermark invalid\n");
3038 /* Compute new watermarks for the pipe */
3039 static int ilk_compute_pipe_wm(struct intel_crtc_state
*cstate
)
3041 struct drm_atomic_state
*state
= cstate
->base
.state
;
3042 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
3043 struct intel_pipe_wm
*pipe_wm
;
3044 struct drm_device
*dev
= state
->dev
;
3045 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
3046 struct intel_plane
*intel_plane
;
3047 struct intel_plane_state
*pristate
= NULL
;
3048 struct intel_plane_state
*sprstate
= NULL
;
3049 struct intel_plane_state
*curstate
= NULL
;
3050 int level
, max_level
= ilk_wm_max_level(dev_priv
), usable_level
;
3051 struct ilk_wm_maximums max
;
3053 pipe_wm
= &cstate
->wm
.ilk
.optimal
;
3055 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3056 struct intel_plane_state
*ps
;
3058 ps
= intel_atomic_get_existing_plane_state(state
,
3063 if (intel_plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
3065 else if (intel_plane
->base
.type
== DRM_PLANE_TYPE_OVERLAY
)
3067 else if (intel_plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
3071 pipe_wm
->pipe_enabled
= cstate
->base
.active
;
3073 pipe_wm
->sprites_enabled
= sprstate
->base
.visible
;
3074 pipe_wm
->sprites_scaled
= sprstate
->base
.visible
&&
3075 (drm_rect_width(&sprstate
->base
.dst
) != drm_rect_width(&sprstate
->base
.src
) >> 16 ||
3076 drm_rect_height(&sprstate
->base
.dst
) != drm_rect_height(&sprstate
->base
.src
) >> 16);
3079 usable_level
= max_level
;
3081 /* ILK/SNB: LP2+ watermarks only w/o sprites */
3082 if (INTEL_GEN(dev_priv
) <= 6 && pipe_wm
->sprites_enabled
)
3085 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
3086 if (pipe_wm
->sprites_scaled
)
3089 ilk_compute_wm_level(dev_priv
, intel_crtc
, 0, cstate
,
3090 pristate
, sprstate
, curstate
, &pipe_wm
->raw_wm
[0]);
3092 memset(&pipe_wm
->wm
, 0, sizeof(pipe_wm
->wm
));
3093 pipe_wm
->wm
[0] = pipe_wm
->raw_wm
[0];
3095 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
3096 pipe_wm
->linetime
= hsw_compute_linetime_wm(cstate
);
3098 if (!ilk_validate_pipe_wm(dev
, pipe_wm
))
3101 ilk_compute_wm_reg_maximums(dev_priv
, 1, &max
);
3103 for (level
= 1; level
<= max_level
; level
++) {
3104 struct intel_wm_level
*wm
= &pipe_wm
->raw_wm
[level
];
3106 ilk_compute_wm_level(dev_priv
, intel_crtc
, level
, cstate
,
3107 pristate
, sprstate
, curstate
, wm
);
3110 * Disable any watermark level that exceeds the
3111 * register maximums since such watermarks are
3114 if (level
> usable_level
)
3117 if (ilk_validate_wm_level(level
, &max
, wm
))
3118 pipe_wm
->wm
[level
] = *wm
;
3120 usable_level
= level
;
3127 * Build a set of 'intermediate' watermark values that satisfy both the old
3128 * state and the new state. These can be programmed to the hardware
3131 static int ilk_compute_intermediate_wm(struct drm_device
*dev
,
3132 struct intel_crtc
*intel_crtc
,
3133 struct intel_crtc_state
*newstate
)
3135 struct intel_pipe_wm
*a
= &newstate
->wm
.ilk
.intermediate
;
3136 struct intel_pipe_wm
*b
= &intel_crtc
->wm
.active
.ilk
;
3137 int level
, max_level
= ilk_wm_max_level(to_i915(dev
));
3140 * Start with the final, target watermarks, then combine with the
3141 * currently active watermarks to get values that are safe both before
3142 * and after the vblank.
3144 *a
= newstate
->wm
.ilk
.optimal
;
3145 a
->pipe_enabled
|= b
->pipe_enabled
;
3146 a
->sprites_enabled
|= b
->sprites_enabled
;
3147 a
->sprites_scaled
|= b
->sprites_scaled
;
3149 for (level
= 0; level
<= max_level
; level
++) {
3150 struct intel_wm_level
*a_wm
= &a
->wm
[level
];
3151 const struct intel_wm_level
*b_wm
= &b
->wm
[level
];
3153 a_wm
->enable
&= b_wm
->enable
;
3154 a_wm
->pri_val
= max(a_wm
->pri_val
, b_wm
->pri_val
);
3155 a_wm
->spr_val
= max(a_wm
->spr_val
, b_wm
->spr_val
);
3156 a_wm
->cur_val
= max(a_wm
->cur_val
, b_wm
->cur_val
);
3157 a_wm
->fbc_val
= max(a_wm
->fbc_val
, b_wm
->fbc_val
);
3161 * We need to make sure that these merged watermark values are
3162 * actually a valid configuration themselves. If they're not,
3163 * there's no safe way to transition from the old state to
3164 * the new state, so we need to fail the atomic transaction.
3166 if (!ilk_validate_pipe_wm(dev
, a
))
3170 * If our intermediate WM are identical to the final WM, then we can
3171 * omit the post-vblank programming; only update if it's different.
3173 if (memcmp(a
, &newstate
->wm
.ilk
.optimal
, sizeof(*a
)) != 0)
3174 newstate
->wm
.need_postvbl_update
= true;
3180 * Merge the watermarks from all active pipes for a specific level.
3182 static void ilk_merge_wm_level(struct drm_device
*dev
,
3184 struct intel_wm_level
*ret_wm
)
3186 const struct intel_crtc
*intel_crtc
;
3188 ret_wm
->enable
= true;
3190 for_each_intel_crtc(dev
, intel_crtc
) {
3191 const struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
.ilk
;
3192 const struct intel_wm_level
*wm
= &active
->wm
[level
];
3194 if (!active
->pipe_enabled
)
3198 * The watermark values may have been used in the past,
3199 * so we must maintain them in the registers for some
3200 * time even if the level is now disabled.
3203 ret_wm
->enable
= false;
3205 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
3206 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
3207 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
3208 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
3213 * Merge all low power watermarks for all active pipes.
3215 static void ilk_wm_merge(struct drm_device
*dev
,
3216 const struct intel_wm_config
*config
,
3217 const struct ilk_wm_maximums
*max
,
3218 struct intel_pipe_wm
*merged
)
3220 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3221 int level
, max_level
= ilk_wm_max_level(dev_priv
);
3222 int last_enabled_level
= max_level
;
3224 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
3225 if ((INTEL_GEN(dev_priv
) <= 6 || IS_IVYBRIDGE(dev_priv
)) &&
3226 config
->num_pipes_active
> 1)
3227 last_enabled_level
= 0;
3229 /* ILK: FBC WM must be disabled always */
3230 merged
->fbc_wm_enabled
= INTEL_GEN(dev_priv
) >= 6;
3232 /* merge each WM1+ level */
3233 for (level
= 1; level
<= max_level
; level
++) {
3234 struct intel_wm_level
*wm
= &merged
->wm
[level
];
3236 ilk_merge_wm_level(dev
, level
, wm
);
3238 if (level
> last_enabled_level
)
3240 else if (!ilk_validate_wm_level(level
, max
, wm
))
3241 /* make sure all following levels get disabled */
3242 last_enabled_level
= level
- 1;
3245 * The spec says it is preferred to disable
3246 * FBC WMs instead of disabling a WM level.
3248 if (wm
->fbc_val
> max
->fbc
) {
3250 merged
->fbc_wm_enabled
= false;
3255 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
3257 * FIXME this is racy. FBC might get enabled later.
3258 * What we should check here is whether FBC can be
3259 * enabled sometime later.
3261 if (IS_GEN5(dev_priv
) && !merged
->fbc_wm_enabled
&&
3262 intel_fbc_is_active(dev_priv
)) {
3263 for (level
= 2; level
<= max_level
; level
++) {
3264 struct intel_wm_level
*wm
= &merged
->wm
[level
];
3271 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
3273 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
3274 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
3277 /* The value we need to program into the WM_LPx latency field */
3278 static unsigned int ilk_wm_lp_latency(struct drm_device
*dev
, int level
)
3280 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3282 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
3285 return dev_priv
->wm
.pri_latency
[level
];
3288 static void ilk_compute_wm_results(struct drm_device
*dev
,
3289 const struct intel_pipe_wm
*merged
,
3290 enum intel_ddb_partitioning partitioning
,
3291 struct ilk_wm_values
*results
)
3293 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3294 struct intel_crtc
*intel_crtc
;
3297 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
3298 results
->partitioning
= partitioning
;
3300 /* LP1+ register values */
3301 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
3302 const struct intel_wm_level
*r
;
3304 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
3306 r
= &merged
->wm
[level
];
3309 * Maintain the watermark values even if the level is
3310 * disabled. Doing otherwise could cause underruns.
3312 results
->wm_lp
[wm_lp
- 1] =
3313 (ilk_wm_lp_latency(dev
, level
) << WM1_LP_LATENCY_SHIFT
) |
3314 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
3318 results
->wm_lp
[wm_lp
- 1] |= WM1_LP_SR_EN
;
3320 if (INTEL_GEN(dev_priv
) >= 8)
3321 results
->wm_lp
[wm_lp
- 1] |=
3322 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
3324 results
->wm_lp
[wm_lp
- 1] |=
3325 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
3328 * Always set WM1S_LP_EN when spr_val != 0, even if the
3329 * level is disabled. Doing otherwise could cause underruns.
3331 if (INTEL_GEN(dev_priv
) <= 6 && r
->spr_val
) {
3332 WARN_ON(wm_lp
!= 1);
3333 results
->wm_lp_spr
[wm_lp
- 1] = WM1S_LP_EN
| r
->spr_val
;
3335 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
3338 /* LP0 register values */
3339 for_each_intel_crtc(dev
, intel_crtc
) {
3340 enum pipe pipe
= intel_crtc
->pipe
;
3341 const struct intel_wm_level
*r
=
3342 &intel_crtc
->wm
.active
.ilk
.wm
[0];
3344 if (WARN_ON(!r
->enable
))
3347 results
->wm_linetime
[pipe
] = intel_crtc
->wm
.active
.ilk
.linetime
;
3349 results
->wm_pipe
[pipe
] =
3350 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
3351 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
3356 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
3357 * case both are at the same level. Prefer r1 in case they're the same. */
3358 static struct intel_pipe_wm
*ilk_find_best_result(struct drm_device
*dev
,
3359 struct intel_pipe_wm
*r1
,
3360 struct intel_pipe_wm
*r2
)
3362 int level
, max_level
= ilk_wm_max_level(to_i915(dev
));
3363 int level1
= 0, level2
= 0;
3365 for (level
= 1; level
<= max_level
; level
++) {
3366 if (r1
->wm
[level
].enable
)
3368 if (r2
->wm
[level
].enable
)
3372 if (level1
== level2
) {
3373 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
3377 } else if (level1
> level2
) {
3384 /* dirty bits used to track which watermarks need changes */
3385 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
3386 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
3387 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
3388 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
3389 #define WM_DIRTY_FBC (1 << 24)
3390 #define WM_DIRTY_DDB (1 << 25)
3392 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private
*dev_priv
,
3393 const struct ilk_wm_values
*old
,
3394 const struct ilk_wm_values
*new)
3396 unsigned int dirty
= 0;
3400 for_each_pipe(dev_priv
, pipe
) {
3401 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
3402 dirty
|= WM_DIRTY_LINETIME(pipe
);
3403 /* Must disable LP1+ watermarks too */
3404 dirty
|= WM_DIRTY_LP_ALL
;
3407 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
3408 dirty
|= WM_DIRTY_PIPE(pipe
);
3409 /* Must disable LP1+ watermarks too */
3410 dirty
|= WM_DIRTY_LP_ALL
;
3414 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
3415 dirty
|= WM_DIRTY_FBC
;
3416 /* Must disable LP1+ watermarks too */
3417 dirty
|= WM_DIRTY_LP_ALL
;
3420 if (old
->partitioning
!= new->partitioning
) {
3421 dirty
|= WM_DIRTY_DDB
;
3422 /* Must disable LP1+ watermarks too */
3423 dirty
|= WM_DIRTY_LP_ALL
;
3426 /* LP1+ watermarks already deemed dirty, no need to continue */
3427 if (dirty
& WM_DIRTY_LP_ALL
)
3430 /* Find the lowest numbered LP1+ watermark in need of an update... */
3431 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
3432 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
3433 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
3437 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
3438 for (; wm_lp
<= 3; wm_lp
++)
3439 dirty
|= WM_DIRTY_LP(wm_lp
);
3444 static bool _ilk_disable_lp_wm(struct drm_i915_private
*dev_priv
,
3447 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
3448 bool changed
= false;
3450 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] & WM1_LP_SR_EN
) {
3451 previous
->wm_lp
[2] &= ~WM1_LP_SR_EN
;
3452 I915_WRITE(WM3_LP_ILK
, previous
->wm_lp
[2]);
3455 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] & WM1_LP_SR_EN
) {
3456 previous
->wm_lp
[1] &= ~WM1_LP_SR_EN
;
3457 I915_WRITE(WM2_LP_ILK
, previous
->wm_lp
[1]);
3460 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] & WM1_LP_SR_EN
) {
3461 previous
->wm_lp
[0] &= ~WM1_LP_SR_EN
;
3462 I915_WRITE(WM1_LP_ILK
, previous
->wm_lp
[0]);
3467 * Don't touch WM1S_LP_EN here.
3468 * Doing so could cause underruns.
3475 * The spec says we shouldn't write when we don't need, because every write
3476 * causes WMs to be re-evaluated, expending some power.
3478 static void ilk_write_wm_values(struct drm_i915_private
*dev_priv
,
3479 struct ilk_wm_values
*results
)
3481 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
3485 dirty
= ilk_compute_wm_dirty(dev_priv
, previous
, results
);
3489 _ilk_disable_lp_wm(dev_priv
, dirty
);
3491 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
3492 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
3493 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
3494 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
3495 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
3496 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
3498 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
3499 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
3500 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
3501 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
3502 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
3503 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
3505 if (dirty
& WM_DIRTY_DDB
) {
3506 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3507 val
= I915_READ(WM_MISC
);
3508 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
3509 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
3511 val
|= WM_MISC_DATA_PARTITION_5_6
;
3512 I915_WRITE(WM_MISC
, val
);
3514 val
= I915_READ(DISP_ARB_CTL2
);
3515 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
3516 val
&= ~DISP_DATA_PARTITION_5_6
;
3518 val
|= DISP_DATA_PARTITION_5_6
;
3519 I915_WRITE(DISP_ARB_CTL2
, val
);
3523 if (dirty
& WM_DIRTY_FBC
) {
3524 val
= I915_READ(DISP_ARB_CTL
);
3525 if (results
->enable_fbc_wm
)
3526 val
&= ~DISP_FBC_WM_DIS
;
3528 val
|= DISP_FBC_WM_DIS
;
3529 I915_WRITE(DISP_ARB_CTL
, val
);
3532 if (dirty
& WM_DIRTY_LP(1) &&
3533 previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
3534 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
3536 if (INTEL_GEN(dev_priv
) >= 7) {
3537 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
3538 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
3539 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
3540 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
3543 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != results
->wm_lp
[0])
3544 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
3545 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != results
->wm_lp
[1])
3546 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
3547 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != results
->wm_lp
[2])
3548 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
3550 dev_priv
->wm
.hw
= *results
;
3553 bool ilk_disable_lp_wm(struct drm_device
*dev
)
3555 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3557 return _ilk_disable_lp_wm(dev_priv
, WM_DIRTY_LP_ALL
);
3561 * FIXME: We still don't have the proper code detect if we need to apply the WA,
3562 * so assume we'll always need it in order to avoid underruns.
3564 static bool skl_needs_memory_bw_wa(struct intel_atomic_state
*state
)
3566 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
3568 if (IS_GEN9_BC(dev_priv
) || IS_BROXTON(dev_priv
))
3575 intel_has_sagv(struct drm_i915_private
*dev_priv
)
3577 if (IS_KABYLAKE(dev_priv
) || IS_COFFEELAKE(dev_priv
) ||
3578 IS_CANNONLAKE(dev_priv
))
3581 if (IS_SKYLAKE(dev_priv
) &&
3582 dev_priv
->sagv_status
!= I915_SAGV_NOT_CONTROLLED
)
3589 * SAGV dynamically adjusts the system agent voltage and clock frequencies
3590 * depending on power and performance requirements. The display engine access
3591 * to system memory is blocked during the adjustment time. Because of the
3592 * blocking time, having this enabled can cause full system hangs and/or pipe
3593 * underruns if we don't meet all of the following requirements:
3595 * - <= 1 pipe enabled
3596 * - All planes can enable watermarks for latencies >= SAGV engine block time
3597 * - We're not using an interlaced display configuration
3600 intel_enable_sagv(struct drm_i915_private
*dev_priv
)
3604 if (!intel_has_sagv(dev_priv
))
3607 if (dev_priv
->sagv_status
== I915_SAGV_ENABLED
)
3610 DRM_DEBUG_KMS("Enabling the SAGV\n");
3611 mutex_lock(&dev_priv
->rps
.hw_lock
);
3613 ret
= sandybridge_pcode_write(dev_priv
, GEN9_PCODE_SAGV_CONTROL
,
3616 /* We don't need to wait for the SAGV when enabling */
3617 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3620 * Some skl systems, pre-release machines in particular,
3621 * don't actually have an SAGV.
3623 if (IS_SKYLAKE(dev_priv
) && ret
== -ENXIO
) {
3624 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3625 dev_priv
->sagv_status
= I915_SAGV_NOT_CONTROLLED
;
3627 } else if (ret
< 0) {
3628 DRM_ERROR("Failed to enable the SAGV\n");
3632 dev_priv
->sagv_status
= I915_SAGV_ENABLED
;
3637 intel_disable_sagv(struct drm_i915_private
*dev_priv
)
3641 if (!intel_has_sagv(dev_priv
))
3644 if (dev_priv
->sagv_status
== I915_SAGV_DISABLED
)
3647 DRM_DEBUG_KMS("Disabling the SAGV\n");
3648 mutex_lock(&dev_priv
->rps
.hw_lock
);
3650 /* bspec says to keep retrying for at least 1 ms */
3651 ret
= skl_pcode_request(dev_priv
, GEN9_PCODE_SAGV_CONTROL
,
3653 GEN9_SAGV_IS_DISABLED
, GEN9_SAGV_IS_DISABLED
,
3655 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3658 * Some skl systems, pre-release machines in particular,
3659 * don't actually have an SAGV.
3661 if (IS_SKYLAKE(dev_priv
) && ret
== -ENXIO
) {
3662 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3663 dev_priv
->sagv_status
= I915_SAGV_NOT_CONTROLLED
;
3665 } else if (ret
< 0) {
3666 DRM_ERROR("Failed to disable the SAGV (%d)\n", ret
);
3670 dev_priv
->sagv_status
= I915_SAGV_DISABLED
;
3674 bool intel_can_enable_sagv(struct drm_atomic_state
*state
)
3676 struct drm_device
*dev
= state
->dev
;
3677 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3678 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
3679 struct intel_crtc
*crtc
;
3680 struct intel_plane
*plane
;
3681 struct intel_crtc_state
*cstate
;
3684 int sagv_block_time_us
= IS_GEN9(dev_priv
) ? 30 : 20;
3686 if (!intel_has_sagv(dev_priv
))
3690 * SKL+ workaround: bspec recommends we disable the SAGV when we have
3691 * more then one pipe enabled
3693 * If there are no active CRTCs, no additional checks need be performed
3695 if (hweight32(intel_state
->active_crtcs
) == 0)
3697 else if (hweight32(intel_state
->active_crtcs
) > 1)
3700 /* Since we're now guaranteed to only have one active CRTC... */
3701 pipe
= ffs(intel_state
->active_crtcs
) - 1;
3702 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
3703 cstate
= to_intel_crtc_state(crtc
->base
.state
);
3705 if (crtc
->base
.state
->adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
3708 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
3709 struct skl_plane_wm
*wm
=
3710 &cstate
->wm
.skl
.optimal
.planes
[plane
->id
];
3712 /* Skip this plane if it's not enabled */
3713 if (!wm
->wm
[0].plane_en
)
3716 /* Find the highest enabled wm level for this plane */
3717 for (level
= ilk_wm_max_level(dev_priv
);
3718 !wm
->wm
[level
].plane_en
; --level
)
3721 latency
= dev_priv
->wm
.skl_latency
[level
];
3723 if (skl_needs_memory_bw_wa(intel_state
) &&
3724 plane
->base
.state
->fb
->modifier
==
3725 I915_FORMAT_MOD_X_TILED
)
3729 * If any of the planes on this pipe don't enable wm levels that
3730 * incur memory latencies higher than sagv_block_time_us we
3731 * can't enable the SAGV.
3733 if (latency
< sagv_block_time_us
)
3741 skl_ddb_get_pipe_allocation_limits(struct drm_device
*dev
,
3742 const struct intel_crtc_state
*cstate
,
3743 struct skl_ddb_entry
*alloc
, /* out */
3744 int *num_active
/* out */)
3746 struct drm_atomic_state
*state
= cstate
->base
.state
;
3747 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
3748 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3749 struct drm_crtc
*for_crtc
= cstate
->base
.crtc
;
3750 unsigned int pipe_size
, ddb_size
;
3751 int nth_active_pipe
;
3753 if (WARN_ON(!state
) || !cstate
->base
.active
) {
3756 *num_active
= hweight32(dev_priv
->active_crtcs
);
3760 if (intel_state
->active_pipe_changes
)
3761 *num_active
= hweight32(intel_state
->active_crtcs
);
3763 *num_active
= hweight32(dev_priv
->active_crtcs
);
3765 ddb_size
= INTEL_INFO(dev_priv
)->ddb_size
;
3766 WARN_ON(ddb_size
== 0);
3768 ddb_size
-= 4; /* 4 blocks for bypass path allocation */
3771 * If the state doesn't change the active CRTC's, then there's
3772 * no need to recalculate; the existing pipe allocation limits
3773 * should remain unchanged. Note that we're safe from racing
3774 * commits since any racing commit that changes the active CRTC
3775 * list would need to grab _all_ crtc locks, including the one
3776 * we currently hold.
3778 if (!intel_state
->active_pipe_changes
) {
3780 * alloc may be cleared by clear_intel_crtc_state,
3781 * copy from old state to be sure
3783 *alloc
= to_intel_crtc_state(for_crtc
->state
)->wm
.skl
.ddb
;
3787 nth_active_pipe
= hweight32(intel_state
->active_crtcs
&
3788 (drm_crtc_mask(for_crtc
) - 1));
3789 pipe_size
= ddb_size
/ hweight32(intel_state
->active_crtcs
);
3790 alloc
->start
= nth_active_pipe
* ddb_size
/ *num_active
;
3791 alloc
->end
= alloc
->start
+ pipe_size
;
3794 static unsigned int skl_cursor_allocation(int num_active
)
3796 if (num_active
== 1)
3802 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry
*entry
, u32 reg
)
3804 entry
->start
= reg
& 0x3ff;
3805 entry
->end
= (reg
>> 16) & 0x3ff;
3810 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
3811 struct skl_ddb_allocation
*ddb
/* out */)
3813 struct intel_crtc
*crtc
;
3815 memset(ddb
, 0, sizeof(*ddb
));
3817 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
3818 enum intel_display_power_domain power_domain
;
3819 enum plane_id plane_id
;
3820 enum pipe pipe
= crtc
->pipe
;
3822 power_domain
= POWER_DOMAIN_PIPE(pipe
);
3823 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
3826 for_each_plane_id_on_crtc(crtc
, plane_id
) {
3829 if (plane_id
!= PLANE_CURSOR
)
3830 val
= I915_READ(PLANE_BUF_CFG(pipe
, plane_id
));
3832 val
= I915_READ(CUR_BUF_CFG(pipe
));
3834 skl_ddb_entry_init_from_hw(&ddb
->plane
[pipe
][plane_id
], val
);
3837 intel_display_power_put(dev_priv
, power_domain
);
3842 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3843 * The bspec defines downscale amount as:
3846 * Horizontal down scale amount = maximum[1, Horizontal source size /
3847 * Horizontal destination size]
3848 * Vertical down scale amount = maximum[1, Vertical source size /
3849 * Vertical destination size]
3850 * Total down scale amount = Horizontal down scale amount *
3851 * Vertical down scale amount
3854 * Return value is provided in 16.16 fixed point form to retain fractional part.
3855 * Caller should take care of dividing & rounding off the value.
3857 static uint_fixed_16_16_t
3858 skl_plane_downscale_amount(const struct intel_crtc_state
*cstate
,
3859 const struct intel_plane_state
*pstate
)
3861 struct intel_plane
*plane
= to_intel_plane(pstate
->base
.plane
);
3862 uint32_t src_w
, src_h
, dst_w
, dst_h
;
3863 uint_fixed_16_16_t fp_w_ratio
, fp_h_ratio
;
3864 uint_fixed_16_16_t downscale_h
, downscale_w
;
3866 if (WARN_ON(!intel_wm_plane_visible(cstate
, pstate
)))
3867 return u32_to_fixed16(0);
3869 /* n.b., src is 16.16 fixed point, dst is whole integer */
3870 if (plane
->id
== PLANE_CURSOR
) {
3872 * Cursors only support 0/180 degree rotation,
3873 * hence no need to account for rotation here.
3875 src_w
= pstate
->base
.src_w
>> 16;
3876 src_h
= pstate
->base
.src_h
>> 16;
3877 dst_w
= pstate
->base
.crtc_w
;
3878 dst_h
= pstate
->base
.crtc_h
;
3881 * Src coordinates are already rotated by 270 degrees for
3882 * the 90/270 degree plane rotation cases (to match the
3883 * GTT mapping), hence no need to account for rotation here.
3885 src_w
= drm_rect_width(&pstate
->base
.src
) >> 16;
3886 src_h
= drm_rect_height(&pstate
->base
.src
) >> 16;
3887 dst_w
= drm_rect_width(&pstate
->base
.dst
);
3888 dst_h
= drm_rect_height(&pstate
->base
.dst
);
3891 fp_w_ratio
= div_fixed16(src_w
, dst_w
);
3892 fp_h_ratio
= div_fixed16(src_h
, dst_h
);
3893 downscale_w
= max_fixed16(fp_w_ratio
, u32_to_fixed16(1));
3894 downscale_h
= max_fixed16(fp_h_ratio
, u32_to_fixed16(1));
3896 return mul_fixed16(downscale_w
, downscale_h
);
3899 static uint_fixed_16_16_t
3900 skl_pipe_downscale_amount(const struct intel_crtc_state
*crtc_state
)
3902 uint_fixed_16_16_t pipe_downscale
= u32_to_fixed16(1);
3904 if (!crtc_state
->base
.enable
)
3905 return pipe_downscale
;
3907 if (crtc_state
->pch_pfit
.enabled
) {
3908 uint32_t src_w
, src_h
, dst_w
, dst_h
;
3909 uint32_t pfit_size
= crtc_state
->pch_pfit
.size
;
3910 uint_fixed_16_16_t fp_w_ratio
, fp_h_ratio
;
3911 uint_fixed_16_16_t downscale_h
, downscale_w
;
3913 src_w
= crtc_state
->pipe_src_w
;
3914 src_h
= crtc_state
->pipe_src_h
;
3915 dst_w
= pfit_size
>> 16;
3916 dst_h
= pfit_size
& 0xffff;
3918 if (!dst_w
|| !dst_h
)
3919 return pipe_downscale
;
3921 fp_w_ratio
= div_fixed16(src_w
, dst_w
);
3922 fp_h_ratio
= div_fixed16(src_h
, dst_h
);
3923 downscale_w
= max_fixed16(fp_w_ratio
, u32_to_fixed16(1));
3924 downscale_h
= max_fixed16(fp_h_ratio
, u32_to_fixed16(1));
3926 pipe_downscale
= mul_fixed16(downscale_w
, downscale_h
);
3929 return pipe_downscale
;
3932 int skl_check_pipe_max_pixel_rate(struct intel_crtc
*intel_crtc
,
3933 struct intel_crtc_state
*cstate
)
3935 struct drm_crtc_state
*crtc_state
= &cstate
->base
;
3936 struct drm_atomic_state
*state
= crtc_state
->state
;
3937 struct drm_plane
*plane
;
3938 const struct drm_plane_state
*pstate
;
3939 struct intel_plane_state
*intel_pstate
;
3940 int crtc_clock
, dotclk
;
3941 uint32_t pipe_max_pixel_rate
;
3942 uint_fixed_16_16_t pipe_downscale
;
3943 uint_fixed_16_16_t max_downscale
= u32_to_fixed16(1);
3945 if (!cstate
->base
.enable
)
3948 drm_atomic_crtc_state_for_each_plane_state(plane
, pstate
, crtc_state
) {
3949 uint_fixed_16_16_t plane_downscale
;
3950 uint_fixed_16_16_t fp_9_div_8
= div_fixed16(9, 8);
3953 if (!intel_wm_plane_visible(cstate
,
3954 to_intel_plane_state(pstate
)))
3957 if (WARN_ON(!pstate
->fb
))
3960 intel_pstate
= to_intel_plane_state(pstate
);
3961 plane_downscale
= skl_plane_downscale_amount(cstate
,
3963 bpp
= pstate
->fb
->format
->cpp
[0] * 8;
3965 plane_downscale
= mul_fixed16(plane_downscale
,
3968 max_downscale
= max_fixed16(plane_downscale
, max_downscale
);
3970 pipe_downscale
= skl_pipe_downscale_amount(cstate
);
3972 pipe_downscale
= mul_fixed16(pipe_downscale
, max_downscale
);
3974 crtc_clock
= crtc_state
->adjusted_mode
.crtc_clock
;
3975 dotclk
= to_intel_atomic_state(state
)->cdclk
.logical
.cdclk
;
3977 if (IS_GEMINILAKE(to_i915(intel_crtc
->base
.dev
)))
3980 pipe_max_pixel_rate
= div_round_up_u32_fixed16(dotclk
, pipe_downscale
);
3982 if (pipe_max_pixel_rate
< crtc_clock
) {
3983 DRM_DEBUG_KMS("Max supported pixel clock with scaling exceeded\n");
3991 skl_plane_relative_data_rate(const struct intel_crtc_state
*cstate
,
3992 const struct drm_plane_state
*pstate
,
3995 struct intel_plane
*plane
= to_intel_plane(pstate
->plane
);
3996 struct intel_plane_state
*intel_pstate
= to_intel_plane_state(pstate
);
3998 uint32_t width
= 0, height
= 0;
3999 struct drm_framebuffer
*fb
;
4001 uint_fixed_16_16_t down_scale_amount
;
4003 if (!intel_pstate
->base
.visible
)
4007 format
= fb
->format
->format
;
4009 if (plane
->id
== PLANE_CURSOR
)
4011 if (y
&& format
!= DRM_FORMAT_NV12
)
4015 * Src coordinates are already rotated by 270 degrees for
4016 * the 90/270 degree plane rotation cases (to match the
4017 * GTT mapping), hence no need to account for rotation here.
4019 width
= drm_rect_width(&intel_pstate
->base
.src
) >> 16;
4020 height
= drm_rect_height(&intel_pstate
->base
.src
) >> 16;
4022 /* for planar format */
4023 if (format
== DRM_FORMAT_NV12
) {
4024 if (y
) /* y-plane data rate */
4025 data_rate
= width
* height
*
4027 else /* uv-plane data rate */
4028 data_rate
= (width
/ 2) * (height
/ 2) *
4031 /* for packed formats */
4032 data_rate
= width
* height
* fb
->format
->cpp
[0];
4035 down_scale_amount
= skl_plane_downscale_amount(cstate
, intel_pstate
);
4037 return mul_round_up_u32_fixed16(data_rate
, down_scale_amount
);
4041 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
4042 * a 8192x4096@32bpp framebuffer:
4043 * 3 * 4096 * 8192 * 4 < 2^32
4046 skl_get_total_relative_data_rate(struct intel_crtc_state
*intel_cstate
,
4047 unsigned *plane_data_rate
,
4048 unsigned *plane_y_data_rate
)
4050 struct drm_crtc_state
*cstate
= &intel_cstate
->base
;
4051 struct drm_atomic_state
*state
= cstate
->state
;
4052 struct drm_plane
*plane
;
4053 const struct drm_plane_state
*pstate
;
4054 unsigned int total_data_rate
= 0;
4056 if (WARN_ON(!state
))
4059 /* Calculate and cache data rate for each plane */
4060 drm_atomic_crtc_state_for_each_plane_state(plane
, pstate
, cstate
) {
4061 enum plane_id plane_id
= to_intel_plane(plane
)->id
;
4065 rate
= skl_plane_relative_data_rate(intel_cstate
,
4067 plane_data_rate
[plane_id
] = rate
;
4069 total_data_rate
+= rate
;
4072 rate
= skl_plane_relative_data_rate(intel_cstate
,
4074 plane_y_data_rate
[plane_id
] = rate
;
4076 total_data_rate
+= rate
;
4079 return total_data_rate
;
4083 skl_ddb_min_alloc(const struct drm_plane_state
*pstate
,
4086 struct drm_framebuffer
*fb
= pstate
->fb
;
4087 struct intel_plane_state
*intel_pstate
= to_intel_plane_state(pstate
);
4088 uint32_t src_w
, src_h
;
4089 uint32_t min_scanlines
= 8;
4095 /* For packed formats, no y-plane, return 0 */
4096 if (y
&& fb
->format
->format
!= DRM_FORMAT_NV12
)
4099 /* For Non Y-tile return 8-blocks */
4100 if (fb
->modifier
!= I915_FORMAT_MOD_Y_TILED
&&
4101 fb
->modifier
!= I915_FORMAT_MOD_Yf_TILED
&&
4102 fb
->modifier
!= I915_FORMAT_MOD_Y_TILED_CCS
&&
4103 fb
->modifier
!= I915_FORMAT_MOD_Yf_TILED_CCS
)
4107 * Src coordinates are already rotated by 270 degrees for
4108 * the 90/270 degree plane rotation cases (to match the
4109 * GTT mapping), hence no need to account for rotation here.
4111 src_w
= drm_rect_width(&intel_pstate
->base
.src
) >> 16;
4112 src_h
= drm_rect_height(&intel_pstate
->base
.src
) >> 16;
4114 /* Halve UV plane width and height for NV12 */
4115 if (fb
->format
->format
== DRM_FORMAT_NV12
&& !y
) {
4120 if (fb
->format
->format
== DRM_FORMAT_NV12
&& !y
)
4121 plane_bpp
= fb
->format
->cpp
[1];
4123 plane_bpp
= fb
->format
->cpp
[0];
4125 if (drm_rotation_90_or_270(pstate
->rotation
)) {
4126 switch (plane_bpp
) {
4140 WARN(1, "Unsupported pixel depth %u for rotation",
4146 return DIV_ROUND_UP((4 * src_w
* plane_bpp
), 512) * min_scanlines
/4 + 3;
4150 skl_ddb_calc_min(const struct intel_crtc_state
*cstate
, int num_active
,
4151 uint16_t *minimum
, uint16_t *y_minimum
)
4153 const struct drm_plane_state
*pstate
;
4154 struct drm_plane
*plane
;
4156 drm_atomic_crtc_state_for_each_plane_state(plane
, pstate
, &cstate
->base
) {
4157 enum plane_id plane_id
= to_intel_plane(plane
)->id
;
4159 if (plane_id
== PLANE_CURSOR
)
4162 if (!pstate
->visible
)
4165 minimum
[plane_id
] = skl_ddb_min_alloc(pstate
, 0);
4166 y_minimum
[plane_id
] = skl_ddb_min_alloc(pstate
, 1);
4169 minimum
[PLANE_CURSOR
] = skl_cursor_allocation(num_active
);
4173 skl_allocate_pipe_ddb(struct intel_crtc_state
*cstate
,
4174 struct skl_ddb_allocation
*ddb
/* out */)
4176 struct drm_atomic_state
*state
= cstate
->base
.state
;
4177 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
4178 struct drm_device
*dev
= crtc
->dev
;
4179 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4180 enum pipe pipe
= intel_crtc
->pipe
;
4181 struct skl_ddb_entry
*alloc
= &cstate
->wm
.skl
.ddb
;
4182 uint16_t alloc_size
, start
;
4183 uint16_t minimum
[I915_MAX_PLANES
] = {};
4184 uint16_t y_minimum
[I915_MAX_PLANES
] = {};
4185 unsigned int total_data_rate
;
4186 enum plane_id plane_id
;
4188 unsigned plane_data_rate
[I915_MAX_PLANES
] = {};
4189 unsigned plane_y_data_rate
[I915_MAX_PLANES
] = {};
4190 uint16_t total_min_blocks
= 0;
4192 /* Clear the partitioning for disabled planes. */
4193 memset(ddb
->plane
[pipe
], 0, sizeof(ddb
->plane
[pipe
]));
4194 memset(ddb
->y_plane
[pipe
], 0, sizeof(ddb
->y_plane
[pipe
]));
4196 if (WARN_ON(!state
))
4199 if (!cstate
->base
.active
) {
4200 alloc
->start
= alloc
->end
= 0;
4204 skl_ddb_get_pipe_allocation_limits(dev
, cstate
, alloc
, &num_active
);
4205 alloc_size
= skl_ddb_entry_size(alloc
);
4206 if (alloc_size
== 0)
4209 skl_ddb_calc_min(cstate
, num_active
, minimum
, y_minimum
);
4212 * 1. Allocate the mininum required blocks for each active plane
4213 * and allocate the cursor, it doesn't require extra allocation
4214 * proportional to the data rate.
4217 for_each_plane_id_on_crtc(intel_crtc
, plane_id
) {
4218 total_min_blocks
+= minimum
[plane_id
];
4219 total_min_blocks
+= y_minimum
[plane_id
];
4222 if (total_min_blocks
> alloc_size
) {
4223 DRM_DEBUG_KMS("Requested display configuration exceeds system DDB limitations");
4224 DRM_DEBUG_KMS("minimum required %d/%d\n", total_min_blocks
,
4229 alloc_size
-= total_min_blocks
;
4230 ddb
->plane
[pipe
][PLANE_CURSOR
].start
= alloc
->end
- minimum
[PLANE_CURSOR
];
4231 ddb
->plane
[pipe
][PLANE_CURSOR
].end
= alloc
->end
;
4234 * 2. Distribute the remaining space in proportion to the amount of
4235 * data each plane needs to fetch from memory.
4237 * FIXME: we may not allocate every single block here.
4239 total_data_rate
= skl_get_total_relative_data_rate(cstate
,
4242 if (total_data_rate
== 0)
4245 start
= alloc
->start
;
4246 for_each_plane_id_on_crtc(intel_crtc
, plane_id
) {
4247 unsigned int data_rate
, y_data_rate
;
4248 uint16_t plane_blocks
, y_plane_blocks
= 0;
4250 if (plane_id
== PLANE_CURSOR
)
4253 data_rate
= plane_data_rate
[plane_id
];
4256 * allocation for (packed formats) or (uv-plane part of planar format):
4257 * promote the expression to 64 bits to avoid overflowing, the
4258 * result is < available as data_rate / total_data_rate < 1
4260 plane_blocks
= minimum
[plane_id
];
4261 plane_blocks
+= div_u64((uint64_t)alloc_size
* data_rate
,
4264 /* Leave disabled planes at (0,0) */
4266 ddb
->plane
[pipe
][plane_id
].start
= start
;
4267 ddb
->plane
[pipe
][plane_id
].end
= start
+ plane_blocks
;
4270 start
+= plane_blocks
;
4273 * allocation for y_plane part of planar format:
4275 y_data_rate
= plane_y_data_rate
[plane_id
];
4277 y_plane_blocks
= y_minimum
[plane_id
];
4278 y_plane_blocks
+= div_u64((uint64_t)alloc_size
* y_data_rate
,
4282 ddb
->y_plane
[pipe
][plane_id
].start
= start
;
4283 ddb
->y_plane
[pipe
][plane_id
].end
= start
+ y_plane_blocks
;
4286 start
+= y_plane_blocks
;
4293 * The max latency should be 257 (max the punit can code is 255 and we add 2us
4294 * for the read latency) and cpp should always be <= 8, so that
4295 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
4296 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
4298 static uint_fixed_16_16_t
4299 skl_wm_method1(const struct drm_i915_private
*dev_priv
, uint32_t pixel_rate
,
4300 uint8_t cpp
, uint32_t latency
)
4302 uint32_t wm_intermediate_val
;
4303 uint_fixed_16_16_t ret
;
4306 return FP_16_16_MAX
;
4308 wm_intermediate_val
= latency
* pixel_rate
* cpp
;
4309 ret
= div_fixed16(wm_intermediate_val
, 1000 * 512);
4311 if (INTEL_GEN(dev_priv
) >= 10)
4312 ret
= add_fixed16_u32(ret
, 1);
4317 static uint_fixed_16_16_t
skl_wm_method2(uint32_t pixel_rate
,
4318 uint32_t pipe_htotal
,
4320 uint_fixed_16_16_t plane_blocks_per_line
)
4322 uint32_t wm_intermediate_val
;
4323 uint_fixed_16_16_t ret
;
4326 return FP_16_16_MAX
;
4328 wm_intermediate_val
= latency
* pixel_rate
;
4329 wm_intermediate_val
= DIV_ROUND_UP(wm_intermediate_val
,
4330 pipe_htotal
* 1000);
4331 ret
= mul_u32_fixed16(wm_intermediate_val
, plane_blocks_per_line
);
4335 static uint_fixed_16_16_t
4336 intel_get_linetime_us(struct intel_crtc_state
*cstate
)
4338 uint32_t pixel_rate
;
4339 uint32_t crtc_htotal
;
4340 uint_fixed_16_16_t linetime_us
;
4342 if (!cstate
->base
.active
)
4343 return u32_to_fixed16(0);
4345 pixel_rate
= cstate
->pixel_rate
;
4347 if (WARN_ON(pixel_rate
== 0))
4348 return u32_to_fixed16(0);
4350 crtc_htotal
= cstate
->base
.adjusted_mode
.crtc_htotal
;
4351 linetime_us
= div_fixed16(crtc_htotal
* 1000, pixel_rate
);
4357 skl_adjusted_plane_pixel_rate(const struct intel_crtc_state
*cstate
,
4358 const struct intel_plane_state
*pstate
)
4360 uint64_t adjusted_pixel_rate
;
4361 uint_fixed_16_16_t downscale_amount
;
4363 /* Shouldn't reach here on disabled planes... */
4364 if (WARN_ON(!intel_wm_plane_visible(cstate
, pstate
)))
4368 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
4369 * with additional adjustments for plane-specific scaling.
4371 adjusted_pixel_rate
= cstate
->pixel_rate
;
4372 downscale_amount
= skl_plane_downscale_amount(cstate
, pstate
);
4374 return mul_round_up_u32_fixed16(adjusted_pixel_rate
,
4379 skl_compute_plane_wm_params(const struct drm_i915_private
*dev_priv
,
4380 struct intel_crtc_state
*cstate
,
4381 const struct intel_plane_state
*intel_pstate
,
4382 struct skl_wm_params
*wp
)
4384 struct intel_plane
*plane
= to_intel_plane(intel_pstate
->base
.plane
);
4385 const struct drm_plane_state
*pstate
= &intel_pstate
->base
;
4386 const struct drm_framebuffer
*fb
= pstate
->fb
;
4387 uint32_t interm_pbpl
;
4388 struct intel_atomic_state
*state
=
4389 to_intel_atomic_state(cstate
->base
.state
);
4390 bool apply_memory_bw_wa
= skl_needs_memory_bw_wa(state
);
4392 if (!intel_wm_plane_visible(cstate
, intel_pstate
))
4395 wp
->y_tiled
= fb
->modifier
== I915_FORMAT_MOD_Y_TILED
||
4396 fb
->modifier
== I915_FORMAT_MOD_Yf_TILED
||
4397 fb
->modifier
== I915_FORMAT_MOD_Y_TILED_CCS
||
4398 fb
->modifier
== I915_FORMAT_MOD_Yf_TILED_CCS
;
4399 wp
->x_tiled
= fb
->modifier
== I915_FORMAT_MOD_X_TILED
;
4400 wp
->rc_surface
= fb
->modifier
== I915_FORMAT_MOD_Y_TILED_CCS
||
4401 fb
->modifier
== I915_FORMAT_MOD_Yf_TILED_CCS
;
4403 if (plane
->id
== PLANE_CURSOR
) {
4404 wp
->width
= intel_pstate
->base
.crtc_w
;
4407 * Src coordinates are already rotated by 270 degrees for
4408 * the 90/270 degree plane rotation cases (to match the
4409 * GTT mapping), hence no need to account for rotation here.
4411 wp
->width
= drm_rect_width(&intel_pstate
->base
.src
) >> 16;
4414 wp
->cpp
= (fb
->format
->format
== DRM_FORMAT_NV12
) ? fb
->format
->cpp
[1] :
4416 wp
->plane_pixel_rate
= skl_adjusted_plane_pixel_rate(cstate
,
4419 if (drm_rotation_90_or_270(pstate
->rotation
)) {
4423 wp
->y_min_scanlines
= 16;
4426 wp
->y_min_scanlines
= 8;
4429 wp
->y_min_scanlines
= 4;
4432 MISSING_CASE(wp
->cpp
);
4436 wp
->y_min_scanlines
= 4;
4439 if (apply_memory_bw_wa
)
4440 wp
->y_min_scanlines
*= 2;
4442 wp
->plane_bytes_per_line
= wp
->width
* wp
->cpp
;
4444 interm_pbpl
= DIV_ROUND_UP(wp
->plane_bytes_per_line
*
4445 wp
->y_min_scanlines
, 512);
4447 if (INTEL_GEN(dev_priv
) >= 10)
4450 wp
->plane_blocks_per_line
= div_fixed16(interm_pbpl
,
4451 wp
->y_min_scanlines
);
4452 } else if (wp
->x_tiled
&& IS_GEN9(dev_priv
)) {
4453 interm_pbpl
= DIV_ROUND_UP(wp
->plane_bytes_per_line
, 512);
4454 wp
->plane_blocks_per_line
= u32_to_fixed16(interm_pbpl
);
4456 interm_pbpl
= DIV_ROUND_UP(wp
->plane_bytes_per_line
, 512) + 1;
4457 wp
->plane_blocks_per_line
= u32_to_fixed16(interm_pbpl
);
4460 wp
->y_tile_minimum
= mul_u32_fixed16(wp
->y_min_scanlines
,
4461 wp
->plane_blocks_per_line
);
4462 wp
->linetime_us
= fixed16_to_u32_round_up(
4463 intel_get_linetime_us(cstate
));
4468 static int skl_compute_plane_wm(const struct drm_i915_private
*dev_priv
,
4469 struct intel_crtc_state
*cstate
,
4470 const struct intel_plane_state
*intel_pstate
,
4471 uint16_t ddb_allocation
,
4473 const struct skl_wm_params
*wp
,
4474 uint16_t *out_blocks
, /* out */
4475 uint8_t *out_lines
, /* out */
4476 bool *enabled
/* out */)
4478 const struct drm_plane_state
*pstate
= &intel_pstate
->base
;
4479 uint32_t latency
= dev_priv
->wm
.skl_latency
[level
];
4480 uint_fixed_16_16_t method1
, method2
;
4481 uint_fixed_16_16_t selected_result
;
4482 uint32_t res_blocks
, res_lines
;
4483 struct intel_atomic_state
*state
=
4484 to_intel_atomic_state(cstate
->base
.state
);
4485 bool apply_memory_bw_wa
= skl_needs_memory_bw_wa(state
);
4488 !intel_wm_plane_visible(cstate
, intel_pstate
)) {
4493 /* Display WA #1141: kbl,cfl */
4494 if ((IS_KABYLAKE(dev_priv
) || IS_COFFEELAKE(dev_priv
) ||
4495 IS_CNL_REVID(dev_priv
, CNL_REVID_A0
, CNL_REVID_B0
)) &&
4496 dev_priv
->ipc_enabled
)
4499 if (apply_memory_bw_wa
&& wp
->x_tiled
)
4502 method1
= skl_wm_method1(dev_priv
, wp
->plane_pixel_rate
,
4504 method2
= skl_wm_method2(wp
->plane_pixel_rate
,
4505 cstate
->base
.adjusted_mode
.crtc_htotal
,
4507 wp
->plane_blocks_per_line
);
4510 selected_result
= max_fixed16(method2
, wp
->y_tile_minimum
);
4512 if ((wp
->cpp
* cstate
->base
.adjusted_mode
.crtc_htotal
/
4513 512 < 1) && (wp
->plane_bytes_per_line
/ 512 < 1))
4514 selected_result
= method2
;
4515 else if (ddb_allocation
>=
4516 fixed16_to_u32_round_up(wp
->plane_blocks_per_line
))
4517 selected_result
= min_fixed16(method1
, method2
);
4518 else if (latency
>= wp
->linetime_us
)
4519 selected_result
= min_fixed16(method1
, method2
);
4521 selected_result
= method1
;
4524 res_blocks
= fixed16_to_u32_round_up(selected_result
) + 1;
4525 res_lines
= div_round_up_fixed16(selected_result
,
4526 wp
->plane_blocks_per_line
);
4528 /* Display WA #1125: skl,bxt,kbl,glk */
4529 if (level
== 0 && wp
->rc_surface
)
4530 res_blocks
+= fixed16_to_u32_round_up(wp
->y_tile_minimum
);
4532 /* Display WA #1126: skl,bxt,kbl,glk */
4533 if (level
>= 1 && level
<= 7) {
4535 res_blocks
+= fixed16_to_u32_round_up(
4536 wp
->y_tile_minimum
);
4537 res_lines
+= wp
->y_min_scanlines
;
4543 if (res_blocks
>= ddb_allocation
|| res_lines
> 31) {
4547 * If there are no valid level 0 watermarks, then we can't
4548 * support this display configuration.
4553 struct drm_plane
*plane
= pstate
->plane
;
4555 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
4556 DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n",
4557 plane
->base
.id
, plane
->name
,
4558 res_blocks
, ddb_allocation
, res_lines
);
4563 *out_blocks
= res_blocks
;
4564 *out_lines
= res_lines
;
4571 skl_compute_wm_levels(const struct drm_i915_private
*dev_priv
,
4572 struct skl_ddb_allocation
*ddb
,
4573 struct intel_crtc_state
*cstate
,
4574 const struct intel_plane_state
*intel_pstate
,
4575 const struct skl_wm_params
*wm_params
,
4576 struct skl_plane_wm
*wm
)
4578 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
4579 struct drm_plane
*plane
= intel_pstate
->base
.plane
;
4580 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
4581 uint16_t ddb_blocks
;
4582 enum pipe pipe
= intel_crtc
->pipe
;
4583 int level
, max_level
= ilk_wm_max_level(dev_priv
);
4586 if (WARN_ON(!intel_pstate
->base
.fb
))
4589 ddb_blocks
= skl_ddb_entry_size(&ddb
->plane
[pipe
][intel_plane
->id
]);
4591 for (level
= 0; level
<= max_level
; level
++) {
4592 struct skl_wm_level
*result
= &wm
->wm
[level
];
4594 ret
= skl_compute_plane_wm(dev_priv
,
4600 &result
->plane_res_b
,
4601 &result
->plane_res_l
,
4611 skl_compute_linetime_wm(struct intel_crtc_state
*cstate
)
4613 struct drm_atomic_state
*state
= cstate
->base
.state
;
4614 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
4615 uint_fixed_16_16_t linetime_us
;
4616 uint32_t linetime_wm
;
4618 linetime_us
= intel_get_linetime_us(cstate
);
4620 if (is_fixed16_zero(linetime_us
))
4623 linetime_wm
= fixed16_to_u32_round_up(mul_u32_fixed16(8, linetime_us
));
4625 /* Display WA #1135: bxt:ALL GLK:ALL */
4626 if ((IS_BROXTON(dev_priv
) || IS_GEMINILAKE(dev_priv
)) &&
4627 dev_priv
->ipc_enabled
)
4633 static void skl_compute_transition_wm(struct intel_crtc_state
*cstate
,
4634 struct skl_wm_params
*wp
,
4635 struct skl_wm_level
*wm_l0
,
4636 uint16_t ddb_allocation
,
4637 struct skl_wm_level
*trans_wm
/* out */)
4639 struct drm_device
*dev
= cstate
->base
.crtc
->dev
;
4640 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
4641 uint16_t trans_min
, trans_y_tile_min
;
4642 const uint16_t trans_amount
= 10; /* This is configurable amount */
4643 uint16_t trans_offset_b
, res_blocks
;
4645 if (!cstate
->base
.active
)
4648 /* Transition WM are not recommended by HW team for GEN9 */
4649 if (INTEL_GEN(dev_priv
) <= 9)
4652 /* Transition WM don't make any sense if ipc is disabled */
4653 if (!dev_priv
->ipc_enabled
)
4656 if (INTEL_GEN(dev_priv
) >= 10)
4659 trans_offset_b
= trans_min
+ trans_amount
;
4662 trans_y_tile_min
= (uint16_t) mul_round_up_u32_fixed16(2,
4663 wp
->y_tile_minimum
);
4664 res_blocks
= max(wm_l0
->plane_res_b
, trans_y_tile_min
) +
4667 res_blocks
= wm_l0
->plane_res_b
+ trans_offset_b
;
4669 /* WA BUG:1938466 add one block for non y-tile planes */
4670 if (IS_CNL_REVID(dev_priv
, CNL_REVID_A0
, CNL_REVID_A0
))
4677 if (res_blocks
< ddb_allocation
) {
4678 trans_wm
->plane_res_b
= res_blocks
;
4679 trans_wm
->plane_en
= true;
4684 trans_wm
->plane_en
= false;
4687 static int skl_build_pipe_wm(struct intel_crtc_state
*cstate
,
4688 struct skl_ddb_allocation
*ddb
,
4689 struct skl_pipe_wm
*pipe_wm
)
4691 struct drm_device
*dev
= cstate
->base
.crtc
->dev
;
4692 struct drm_crtc_state
*crtc_state
= &cstate
->base
;
4693 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
4694 struct drm_plane
*plane
;
4695 const struct drm_plane_state
*pstate
;
4696 struct skl_plane_wm
*wm
;
4700 * We'll only calculate watermarks for planes that are actually
4701 * enabled, so make sure all other planes are set as disabled.
4703 memset(pipe_wm
->planes
, 0, sizeof(pipe_wm
->planes
));
4705 drm_atomic_crtc_state_for_each_plane_state(plane
, pstate
, crtc_state
) {
4706 const struct intel_plane_state
*intel_pstate
=
4707 to_intel_plane_state(pstate
);
4708 enum plane_id plane_id
= to_intel_plane(plane
)->id
;
4709 struct skl_wm_params wm_params
;
4710 enum pipe pipe
= to_intel_crtc(cstate
->base
.crtc
)->pipe
;
4711 uint16_t ddb_blocks
;
4713 wm
= &pipe_wm
->planes
[plane_id
];
4714 ddb_blocks
= skl_ddb_entry_size(&ddb
->plane
[pipe
][plane_id
]);
4715 memset(&wm_params
, 0, sizeof(struct skl_wm_params
));
4717 ret
= skl_compute_plane_wm_params(dev_priv
, cstate
,
4718 intel_pstate
, &wm_params
);
4722 ret
= skl_compute_wm_levels(dev_priv
, ddb
, cstate
,
4723 intel_pstate
, &wm_params
, wm
);
4726 skl_compute_transition_wm(cstate
, &wm_params
, &wm
->wm
[0],
4727 ddb_blocks
, &wm
->trans_wm
);
4729 pipe_wm
->linetime
= skl_compute_linetime_wm(cstate
);
4734 static void skl_ddb_entry_write(struct drm_i915_private
*dev_priv
,
4736 const struct skl_ddb_entry
*entry
)
4739 I915_WRITE(reg
, (entry
->end
- 1) << 16 | entry
->start
);
4744 static void skl_write_wm_level(struct drm_i915_private
*dev_priv
,
4746 const struct skl_wm_level
*level
)
4750 if (level
->plane_en
) {
4752 val
|= level
->plane_res_b
;
4753 val
|= level
->plane_res_l
<< PLANE_WM_LINES_SHIFT
;
4756 I915_WRITE(reg
, val
);
4759 static void skl_write_plane_wm(struct intel_crtc
*intel_crtc
,
4760 const struct skl_plane_wm
*wm
,
4761 const struct skl_ddb_allocation
*ddb
,
4762 enum plane_id plane_id
)
4764 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4765 struct drm_device
*dev
= crtc
->dev
;
4766 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4767 int level
, max_level
= ilk_wm_max_level(dev_priv
);
4768 enum pipe pipe
= intel_crtc
->pipe
;
4770 for (level
= 0; level
<= max_level
; level
++) {
4771 skl_write_wm_level(dev_priv
, PLANE_WM(pipe
, plane_id
, level
),
4774 skl_write_wm_level(dev_priv
, PLANE_WM_TRANS(pipe
, plane_id
),
4777 skl_ddb_entry_write(dev_priv
, PLANE_BUF_CFG(pipe
, plane_id
),
4778 &ddb
->plane
[pipe
][plane_id
]);
4779 skl_ddb_entry_write(dev_priv
, PLANE_NV12_BUF_CFG(pipe
, plane_id
),
4780 &ddb
->y_plane
[pipe
][plane_id
]);
4783 static void skl_write_cursor_wm(struct intel_crtc
*intel_crtc
,
4784 const struct skl_plane_wm
*wm
,
4785 const struct skl_ddb_allocation
*ddb
)
4787 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4788 struct drm_device
*dev
= crtc
->dev
;
4789 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4790 int level
, max_level
= ilk_wm_max_level(dev_priv
);
4791 enum pipe pipe
= intel_crtc
->pipe
;
4793 for (level
= 0; level
<= max_level
; level
++) {
4794 skl_write_wm_level(dev_priv
, CUR_WM(pipe
, level
),
4797 skl_write_wm_level(dev_priv
, CUR_WM_TRANS(pipe
), &wm
->trans_wm
);
4799 skl_ddb_entry_write(dev_priv
, CUR_BUF_CFG(pipe
),
4800 &ddb
->plane
[pipe
][PLANE_CURSOR
]);
4803 bool skl_wm_level_equals(const struct skl_wm_level
*l1
,
4804 const struct skl_wm_level
*l2
)
4806 if (l1
->plane_en
!= l2
->plane_en
)
4809 /* If both planes aren't enabled, the rest shouldn't matter */
4813 return (l1
->plane_res_l
== l2
->plane_res_l
&&
4814 l1
->plane_res_b
== l2
->plane_res_b
);
4817 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry
*a
,
4818 const struct skl_ddb_entry
*b
)
4820 return a
->start
< b
->end
&& b
->start
< a
->end
;
4823 bool skl_ddb_allocation_overlaps(struct drm_i915_private
*dev_priv
,
4824 const struct skl_ddb_entry
**entries
,
4825 const struct skl_ddb_entry
*ddb
,
4830 for_each_pipe(dev_priv
, pipe
) {
4831 if (pipe
!= ignore
&& entries
[pipe
] &&
4832 skl_ddb_entries_overlap(ddb
, entries
[pipe
]))
4839 static int skl_update_pipe_wm(struct drm_crtc_state
*cstate
,
4840 const struct skl_pipe_wm
*old_pipe_wm
,
4841 struct skl_pipe_wm
*pipe_wm
, /* out */
4842 struct skl_ddb_allocation
*ddb
, /* out */
4843 bool *changed
/* out */)
4845 struct intel_crtc_state
*intel_cstate
= to_intel_crtc_state(cstate
);
4848 ret
= skl_build_pipe_wm(intel_cstate
, ddb
, pipe_wm
);
4852 if (!memcmp(old_pipe_wm
, pipe_wm
, sizeof(*pipe_wm
)))
4861 pipes_modified(struct drm_atomic_state
*state
)
4863 struct drm_crtc
*crtc
;
4864 struct drm_crtc_state
*cstate
;
4865 uint32_t i
, ret
= 0;
4867 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
)
4868 ret
|= drm_crtc_mask(crtc
);
4874 skl_ddb_add_affected_planes(struct intel_crtc_state
*cstate
)
4876 struct drm_atomic_state
*state
= cstate
->base
.state
;
4877 struct drm_device
*dev
= state
->dev
;
4878 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
4879 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4880 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4881 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
4882 struct skl_ddb_allocation
*new_ddb
= &intel_state
->wm_results
.ddb
;
4883 struct skl_ddb_allocation
*cur_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
4884 struct drm_plane_state
*plane_state
;
4885 struct drm_plane
*plane
;
4886 enum pipe pipe
= intel_crtc
->pipe
;
4888 WARN_ON(!drm_atomic_get_existing_crtc_state(state
, crtc
));
4890 drm_for_each_plane_mask(plane
, dev
, cstate
->base
.plane_mask
) {
4891 enum plane_id plane_id
= to_intel_plane(plane
)->id
;
4893 if (skl_ddb_entry_equal(&cur_ddb
->plane
[pipe
][plane_id
],
4894 &new_ddb
->plane
[pipe
][plane_id
]) &&
4895 skl_ddb_entry_equal(&cur_ddb
->y_plane
[pipe
][plane_id
],
4896 &new_ddb
->y_plane
[pipe
][plane_id
]))
4899 plane_state
= drm_atomic_get_plane_state(state
, plane
);
4900 if (IS_ERR(plane_state
))
4901 return PTR_ERR(plane_state
);
4908 skl_compute_ddb(struct drm_atomic_state
*state
)
4910 struct drm_device
*dev
= state
->dev
;
4911 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4912 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
4913 struct intel_crtc
*intel_crtc
;
4914 struct skl_ddb_allocation
*ddb
= &intel_state
->wm_results
.ddb
;
4915 uint32_t realloc_pipes
= pipes_modified(state
);
4919 * If this is our first atomic update following hardware readout,
4920 * we can't trust the DDB that the BIOS programmed for us. Let's
4921 * pretend that all pipes switched active status so that we'll
4922 * ensure a full DDB recompute.
4924 if (dev_priv
->wm
.distrust_bios_wm
) {
4925 ret
= drm_modeset_lock(&dev
->mode_config
.connection_mutex
,
4926 state
->acquire_ctx
);
4930 intel_state
->active_pipe_changes
= ~0;
4933 * We usually only initialize intel_state->active_crtcs if we
4934 * we're doing a modeset; make sure this field is always
4935 * initialized during the sanitization process that happens
4936 * on the first commit too.
4938 if (!intel_state
->modeset
)
4939 intel_state
->active_crtcs
= dev_priv
->active_crtcs
;
4943 * If the modeset changes which CRTC's are active, we need to
4944 * recompute the DDB allocation for *all* active pipes, even
4945 * those that weren't otherwise being modified in any way by this
4946 * atomic commit. Due to the shrinking of the per-pipe allocations
4947 * when new active CRTC's are added, it's possible for a pipe that
4948 * we were already using and aren't changing at all here to suddenly
4949 * become invalid if its DDB needs exceeds its new allocation.
4951 * Note that if we wind up doing a full DDB recompute, we can't let
4952 * any other display updates race with this transaction, so we need
4953 * to grab the lock on *all* CRTC's.
4955 if (intel_state
->active_pipe_changes
) {
4957 intel_state
->wm_results
.dirty_pipes
= ~0;
4961 * We're not recomputing for the pipes not included in the commit, so
4962 * make sure we start with the current state.
4964 memcpy(ddb
, &dev_priv
->wm
.skl_hw
.ddb
, sizeof(*ddb
));
4966 for_each_intel_crtc_mask(dev
, intel_crtc
, realloc_pipes
) {
4967 struct intel_crtc_state
*cstate
;
4969 cstate
= intel_atomic_get_crtc_state(state
, intel_crtc
);
4971 return PTR_ERR(cstate
);
4973 ret
= skl_allocate_pipe_ddb(cstate
, ddb
);
4977 ret
= skl_ddb_add_affected_planes(cstate
);
4986 skl_copy_wm_for_pipe(struct skl_wm_values
*dst
,
4987 struct skl_wm_values
*src
,
4990 memcpy(dst
->ddb
.y_plane
[pipe
], src
->ddb
.y_plane
[pipe
],
4991 sizeof(dst
->ddb
.y_plane
[pipe
]));
4992 memcpy(dst
->ddb
.plane
[pipe
], src
->ddb
.plane
[pipe
],
4993 sizeof(dst
->ddb
.plane
[pipe
]));
4997 skl_print_wm_changes(const struct drm_atomic_state
*state
)
4999 const struct drm_device
*dev
= state
->dev
;
5000 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
5001 const struct intel_atomic_state
*intel_state
=
5002 to_intel_atomic_state(state
);
5003 const struct drm_crtc
*crtc
;
5004 const struct drm_crtc_state
*cstate
;
5005 const struct intel_plane
*intel_plane
;
5006 const struct skl_ddb_allocation
*old_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
5007 const struct skl_ddb_allocation
*new_ddb
= &intel_state
->wm_results
.ddb
;
5010 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
) {
5011 const struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5012 enum pipe pipe
= intel_crtc
->pipe
;
5014 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
5015 enum plane_id plane_id
= intel_plane
->id
;
5016 const struct skl_ddb_entry
*old
, *new;
5018 old
= &old_ddb
->plane
[pipe
][plane_id
];
5019 new = &new_ddb
->plane
[pipe
][plane_id
];
5021 if (skl_ddb_entry_equal(old
, new))
5024 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
5025 intel_plane
->base
.base
.id
,
5026 intel_plane
->base
.name
,
5027 old
->start
, old
->end
,
5028 new->start
, new->end
);
5034 skl_compute_wm(struct drm_atomic_state
*state
)
5036 struct drm_crtc
*crtc
;
5037 struct drm_crtc_state
*cstate
;
5038 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
5039 struct skl_wm_values
*results
= &intel_state
->wm_results
;
5040 struct drm_device
*dev
= state
->dev
;
5041 struct skl_pipe_wm
*pipe_wm
;
5042 bool changed
= false;
5046 * When we distrust bios wm we always need to recompute to set the
5047 * expected DDB allocations for each CRTC.
5049 if (to_i915(dev
)->wm
.distrust_bios_wm
)
5053 * If this transaction isn't actually touching any CRTC's, don't
5054 * bother with watermark calculation. Note that if we pass this
5055 * test, we're guaranteed to hold at least one CRTC state mutex,
5056 * which means we can safely use values like dev_priv->active_crtcs
5057 * since any racing commits that want to update them would need to
5058 * hold _all_ CRTC state mutexes.
5060 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
)
5066 /* Clear all dirty flags */
5067 results
->dirty_pipes
= 0;
5069 ret
= skl_compute_ddb(state
);
5074 * Calculate WM's for all pipes that are part of this transaction.
5075 * Note that the DDB allocation above may have added more CRTC's that
5076 * weren't otherwise being modified (and set bits in dirty_pipes) if
5077 * pipe allocations had to change.
5079 * FIXME: Now that we're doing this in the atomic check phase, we
5080 * should allow skl_update_pipe_wm() to return failure in cases where
5081 * no suitable watermark values can be found.
5083 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
) {
5084 struct intel_crtc_state
*intel_cstate
=
5085 to_intel_crtc_state(cstate
);
5086 const struct skl_pipe_wm
*old_pipe_wm
=
5087 &to_intel_crtc_state(crtc
->state
)->wm
.skl
.optimal
;
5089 pipe_wm
= &intel_cstate
->wm
.skl
.optimal
;
5090 ret
= skl_update_pipe_wm(cstate
, old_pipe_wm
, pipe_wm
,
5091 &results
->ddb
, &changed
);
5096 results
->dirty_pipes
|= drm_crtc_mask(crtc
);
5098 if ((results
->dirty_pipes
& drm_crtc_mask(crtc
)) == 0)
5099 /* This pipe's WM's did not change */
5102 intel_cstate
->update_wm_pre
= true;
5105 skl_print_wm_changes(state
);
5110 static void skl_atomic_update_crtc_wm(struct intel_atomic_state
*state
,
5111 struct intel_crtc_state
*cstate
)
5113 struct intel_crtc
*crtc
= to_intel_crtc(cstate
->base
.crtc
);
5114 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
5115 struct skl_pipe_wm
*pipe_wm
= &cstate
->wm
.skl
.optimal
;
5116 const struct skl_ddb_allocation
*ddb
= &state
->wm_results
.ddb
;
5117 enum pipe pipe
= crtc
->pipe
;
5118 enum plane_id plane_id
;
5120 if (!(state
->wm_results
.dirty_pipes
& drm_crtc_mask(&crtc
->base
)))
5123 I915_WRITE(PIPE_WM_LINETIME(pipe
), pipe_wm
->linetime
);
5125 for_each_plane_id_on_crtc(crtc
, plane_id
) {
5126 if (plane_id
!= PLANE_CURSOR
)
5127 skl_write_plane_wm(crtc
, &pipe_wm
->planes
[plane_id
],
5130 skl_write_cursor_wm(crtc
, &pipe_wm
->planes
[plane_id
],
5135 static void skl_initial_wm(struct intel_atomic_state
*state
,
5136 struct intel_crtc_state
*cstate
)
5138 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
5139 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5140 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5141 struct skl_wm_values
*results
= &state
->wm_results
;
5142 struct skl_wm_values
*hw_vals
= &dev_priv
->wm
.skl_hw
;
5143 enum pipe pipe
= intel_crtc
->pipe
;
5145 if ((results
->dirty_pipes
& drm_crtc_mask(&intel_crtc
->base
)) == 0)
5148 mutex_lock(&dev_priv
->wm
.wm_mutex
);
5150 if (cstate
->base
.active_changed
)
5151 skl_atomic_update_crtc_wm(state
, cstate
);
5153 skl_copy_wm_for_pipe(hw_vals
, results
, pipe
);
5155 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
5158 static void ilk_compute_wm_config(struct drm_device
*dev
,
5159 struct intel_wm_config
*config
)
5161 struct intel_crtc
*crtc
;
5163 /* Compute the currently _active_ config */
5164 for_each_intel_crtc(dev
, crtc
) {
5165 const struct intel_pipe_wm
*wm
= &crtc
->wm
.active
.ilk
;
5167 if (!wm
->pipe_enabled
)
5170 config
->sprites_enabled
|= wm
->sprites_enabled
;
5171 config
->sprites_scaled
|= wm
->sprites_scaled
;
5172 config
->num_pipes_active
++;
5176 static void ilk_program_watermarks(struct drm_i915_private
*dev_priv
)
5178 struct drm_device
*dev
= &dev_priv
->drm
;
5179 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
5180 struct ilk_wm_maximums max
;
5181 struct intel_wm_config config
= {};
5182 struct ilk_wm_values results
= {};
5183 enum intel_ddb_partitioning partitioning
;
5185 ilk_compute_wm_config(dev
, &config
);
5187 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_1_2
, &max
);
5188 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_1_2
);
5190 /* 5/6 split only in single pipe config on IVB+ */
5191 if (INTEL_GEN(dev_priv
) >= 7 &&
5192 config
.num_pipes_active
== 1 && config
.sprites_enabled
) {
5193 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_5_6
, &max
);
5194 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_5_6
);
5196 best_lp_wm
= ilk_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
5198 best_lp_wm
= &lp_wm_1_2
;
5201 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
5202 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
5204 ilk_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
5206 ilk_write_wm_values(dev_priv
, &results
);
5209 static void ilk_initial_watermarks(struct intel_atomic_state
*state
,
5210 struct intel_crtc_state
*cstate
)
5212 struct drm_i915_private
*dev_priv
= to_i915(cstate
->base
.crtc
->dev
);
5213 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
5215 mutex_lock(&dev_priv
->wm
.wm_mutex
);
5216 intel_crtc
->wm
.active
.ilk
= cstate
->wm
.ilk
.intermediate
;
5217 ilk_program_watermarks(dev_priv
);
5218 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
5221 static void ilk_optimize_watermarks(struct intel_atomic_state
*state
,
5222 struct intel_crtc_state
*cstate
)
5224 struct drm_i915_private
*dev_priv
= to_i915(cstate
->base
.crtc
->dev
);
5225 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
5227 mutex_lock(&dev_priv
->wm
.wm_mutex
);
5228 if (cstate
->wm
.need_postvbl_update
) {
5229 intel_crtc
->wm
.active
.ilk
= cstate
->wm
.ilk
.optimal
;
5230 ilk_program_watermarks(dev_priv
);
5232 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
5235 static inline void skl_wm_level_from_reg_val(uint32_t val
,
5236 struct skl_wm_level
*level
)
5238 level
->plane_en
= val
& PLANE_WM_EN
;
5239 level
->plane_res_b
= val
& PLANE_WM_BLOCKS_MASK
;
5240 level
->plane_res_l
= (val
>> PLANE_WM_LINES_SHIFT
) &
5241 PLANE_WM_LINES_MASK
;
5244 void skl_pipe_wm_get_hw_state(struct drm_crtc
*crtc
,
5245 struct skl_pipe_wm
*out
)
5247 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
5248 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5249 enum pipe pipe
= intel_crtc
->pipe
;
5250 int level
, max_level
;
5251 enum plane_id plane_id
;
5254 max_level
= ilk_wm_max_level(dev_priv
);
5256 for_each_plane_id_on_crtc(intel_crtc
, plane_id
) {
5257 struct skl_plane_wm
*wm
= &out
->planes
[plane_id
];
5259 for (level
= 0; level
<= max_level
; level
++) {
5260 if (plane_id
!= PLANE_CURSOR
)
5261 val
= I915_READ(PLANE_WM(pipe
, plane_id
, level
));
5263 val
= I915_READ(CUR_WM(pipe
, level
));
5265 skl_wm_level_from_reg_val(val
, &wm
->wm
[level
]);
5268 if (plane_id
!= PLANE_CURSOR
)
5269 val
= I915_READ(PLANE_WM_TRANS(pipe
, plane_id
));
5271 val
= I915_READ(CUR_WM_TRANS(pipe
));
5273 skl_wm_level_from_reg_val(val
, &wm
->trans_wm
);
5276 if (!intel_crtc
->active
)
5279 out
->linetime
= I915_READ(PIPE_WM_LINETIME(pipe
));
5282 void skl_wm_get_hw_state(struct drm_device
*dev
)
5284 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5285 struct skl_wm_values
*hw
= &dev_priv
->wm
.skl_hw
;
5286 struct skl_ddb_allocation
*ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
5287 struct drm_crtc
*crtc
;
5288 struct intel_crtc
*intel_crtc
;
5289 struct intel_crtc_state
*cstate
;
5291 skl_ddb_get_hw_state(dev_priv
, ddb
);
5292 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
5293 intel_crtc
= to_intel_crtc(crtc
);
5294 cstate
= to_intel_crtc_state(crtc
->state
);
5296 skl_pipe_wm_get_hw_state(crtc
, &cstate
->wm
.skl
.optimal
);
5298 if (intel_crtc
->active
)
5299 hw
->dirty_pipes
|= drm_crtc_mask(crtc
);
5302 if (dev_priv
->active_crtcs
) {
5303 /* Fully recompute DDB on first atomic commit */
5304 dev_priv
->wm
.distrust_bios_wm
= true;
5306 /* Easy/common case; just sanitize DDB now if everything off */
5307 memset(ddb
, 0, sizeof(*ddb
));
5311 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
5313 struct drm_device
*dev
= crtc
->dev
;
5314 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5315 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
5316 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5317 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
5318 struct intel_pipe_wm
*active
= &cstate
->wm
.ilk
.optimal
;
5319 enum pipe pipe
= intel_crtc
->pipe
;
5320 static const i915_reg_t wm0_pipe_reg
[] = {
5321 [PIPE_A
] = WM0_PIPEA_ILK
,
5322 [PIPE_B
] = WM0_PIPEB_ILK
,
5323 [PIPE_C
] = WM0_PIPEC_IVB
,
5326 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
5327 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5328 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
5330 memset(active
, 0, sizeof(*active
));
5332 active
->pipe_enabled
= intel_crtc
->active
;
5334 if (active
->pipe_enabled
) {
5335 u32 tmp
= hw
->wm_pipe
[pipe
];
5338 * For active pipes LP0 watermark is marked as
5339 * enabled, and LP1+ watermaks as disabled since
5340 * we can't really reverse compute them in case
5341 * multiple pipes are active.
5343 active
->wm
[0].enable
= true;
5344 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
5345 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
5346 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
5347 active
->linetime
= hw
->wm_linetime
[pipe
];
5349 int level
, max_level
= ilk_wm_max_level(dev_priv
);
5352 * For inactive pipes, all watermark levels
5353 * should be marked as enabled but zeroed,
5354 * which is what we'd compute them to.
5356 for (level
= 0; level
<= max_level
; level
++)
5357 active
->wm
[level
].enable
= true;
5360 intel_crtc
->wm
.active
.ilk
= *active
;
5363 #define _FW_WM(value, plane) \
5364 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
5365 #define _FW_WM_VLV(value, plane) \
5366 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
5368 static void g4x_read_wm_values(struct drm_i915_private
*dev_priv
,
5369 struct g4x_wm_values
*wm
)
5373 tmp
= I915_READ(DSPFW1
);
5374 wm
->sr
.plane
= _FW_WM(tmp
, SR
);
5375 wm
->pipe
[PIPE_B
].plane
[PLANE_CURSOR
] = _FW_WM(tmp
, CURSORB
);
5376 wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] = _FW_WM(tmp
, PLANEB
);
5377 wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] = _FW_WM(tmp
, PLANEA
);
5379 tmp
= I915_READ(DSPFW2
);
5380 wm
->fbc_en
= tmp
& DSPFW_FBC_SR_EN
;
5381 wm
->sr
.fbc
= _FW_WM(tmp
, FBC_SR
);
5382 wm
->hpll
.fbc
= _FW_WM(tmp
, FBC_HPLL_SR
);
5383 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] = _FW_WM(tmp
, SPRITEB
);
5384 wm
->pipe
[PIPE_A
].plane
[PLANE_CURSOR
] = _FW_WM(tmp
, CURSORA
);
5385 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] = _FW_WM(tmp
, SPRITEA
);
5387 tmp
= I915_READ(DSPFW3
);
5388 wm
->hpll_en
= tmp
& DSPFW_HPLL_SR_EN
;
5389 wm
->sr
.cursor
= _FW_WM(tmp
, CURSOR_SR
);
5390 wm
->hpll
.cursor
= _FW_WM(tmp
, HPLL_CURSOR
);
5391 wm
->hpll
.plane
= _FW_WM(tmp
, HPLL_SR
);
5394 static void vlv_read_wm_values(struct drm_i915_private
*dev_priv
,
5395 struct vlv_wm_values
*wm
)
5400 for_each_pipe(dev_priv
, pipe
) {
5401 tmp
= I915_READ(VLV_DDL(pipe
));
5403 wm
->ddl
[pipe
].plane
[PLANE_PRIMARY
] =
5404 (tmp
>> DDL_PLANE_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
5405 wm
->ddl
[pipe
].plane
[PLANE_CURSOR
] =
5406 (tmp
>> DDL_CURSOR_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
5407 wm
->ddl
[pipe
].plane
[PLANE_SPRITE0
] =
5408 (tmp
>> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
5409 wm
->ddl
[pipe
].plane
[PLANE_SPRITE1
] =
5410 (tmp
>> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
5413 tmp
= I915_READ(DSPFW1
);
5414 wm
->sr
.plane
= _FW_WM(tmp
, SR
);
5415 wm
->pipe
[PIPE_B
].plane
[PLANE_CURSOR
] = _FW_WM(tmp
, CURSORB
);
5416 wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] = _FW_WM_VLV(tmp
, PLANEB
);
5417 wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] = _FW_WM_VLV(tmp
, PLANEA
);
5419 tmp
= I915_READ(DSPFW2
);
5420 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] = _FW_WM_VLV(tmp
, SPRITEB
);
5421 wm
->pipe
[PIPE_A
].plane
[PLANE_CURSOR
] = _FW_WM(tmp
, CURSORA
);
5422 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] = _FW_WM_VLV(tmp
, SPRITEA
);
5424 tmp
= I915_READ(DSPFW3
);
5425 wm
->sr
.cursor
= _FW_WM(tmp
, CURSOR_SR
);
5427 if (IS_CHERRYVIEW(dev_priv
)) {
5428 tmp
= I915_READ(DSPFW7_CHV
);
5429 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] = _FW_WM_VLV(tmp
, SPRITED
);
5430 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] = _FW_WM_VLV(tmp
, SPRITEC
);
5432 tmp
= I915_READ(DSPFW8_CHV
);
5433 wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE1
] = _FW_WM_VLV(tmp
, SPRITEF
);
5434 wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE0
] = _FW_WM_VLV(tmp
, SPRITEE
);
5436 tmp
= I915_READ(DSPFW9_CHV
);
5437 wm
->pipe
[PIPE_C
].plane
[PLANE_PRIMARY
] = _FW_WM_VLV(tmp
, PLANEC
);
5438 wm
->pipe
[PIPE_C
].plane
[PLANE_CURSOR
] = _FW_WM(tmp
, CURSORC
);
5440 tmp
= I915_READ(DSPHOWM
);
5441 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
5442 wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITEF_HI
) << 8;
5443 wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEE_HI
) << 8;
5444 wm
->pipe
[PIPE_C
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEC_HI
) << 8;
5445 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
5446 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
5447 wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEB_HI
) << 8;
5448 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
5449 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
5450 wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEA_HI
) << 8;
5452 tmp
= I915_READ(DSPFW7
);
5453 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] = _FW_WM_VLV(tmp
, SPRITED
);
5454 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] = _FW_WM_VLV(tmp
, SPRITEC
);
5456 tmp
= I915_READ(DSPHOWM
);
5457 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
5458 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
5459 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
5460 wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEB_HI
) << 8;
5461 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
5462 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
5463 wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEA_HI
) << 8;
5470 void g4x_wm_get_hw_state(struct drm_device
*dev
)
5472 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5473 struct g4x_wm_values
*wm
= &dev_priv
->wm
.g4x
;
5474 struct intel_crtc
*crtc
;
5476 g4x_read_wm_values(dev_priv
, wm
);
5478 wm
->cxsr
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
5480 for_each_intel_crtc(dev
, crtc
) {
5481 struct intel_crtc_state
*crtc_state
=
5482 to_intel_crtc_state(crtc
->base
.state
);
5483 struct g4x_wm_state
*active
= &crtc
->wm
.active
.g4x
;
5484 struct g4x_pipe_wm
*raw
;
5485 enum pipe pipe
= crtc
->pipe
;
5486 enum plane_id plane_id
;
5487 int level
, max_level
;
5489 active
->cxsr
= wm
->cxsr
;
5490 active
->hpll_en
= wm
->hpll_en
;
5491 active
->fbc_en
= wm
->fbc_en
;
5493 active
->sr
= wm
->sr
;
5494 active
->hpll
= wm
->hpll
;
5496 for_each_plane_id_on_crtc(crtc
, plane_id
) {
5497 active
->wm
.plane
[plane_id
] =
5498 wm
->pipe
[pipe
].plane
[plane_id
];
5501 if (wm
->cxsr
&& wm
->hpll_en
)
5502 max_level
= G4X_WM_LEVEL_HPLL
;
5504 max_level
= G4X_WM_LEVEL_SR
;
5506 max_level
= G4X_WM_LEVEL_NORMAL
;
5508 level
= G4X_WM_LEVEL_NORMAL
;
5509 raw
= &crtc_state
->wm
.g4x
.raw
[level
];
5510 for_each_plane_id_on_crtc(crtc
, plane_id
)
5511 raw
->plane
[plane_id
] = active
->wm
.plane
[plane_id
];
5513 if (++level
> max_level
)
5516 raw
= &crtc_state
->wm
.g4x
.raw
[level
];
5517 raw
->plane
[PLANE_PRIMARY
] = active
->sr
.plane
;
5518 raw
->plane
[PLANE_CURSOR
] = active
->sr
.cursor
;
5519 raw
->plane
[PLANE_SPRITE0
] = 0;
5520 raw
->fbc
= active
->sr
.fbc
;
5522 if (++level
> max_level
)
5525 raw
= &crtc_state
->wm
.g4x
.raw
[level
];
5526 raw
->plane
[PLANE_PRIMARY
] = active
->hpll
.plane
;
5527 raw
->plane
[PLANE_CURSOR
] = active
->hpll
.cursor
;
5528 raw
->plane
[PLANE_SPRITE0
] = 0;
5529 raw
->fbc
= active
->hpll
.fbc
;
5532 for_each_plane_id_on_crtc(crtc
, plane_id
)
5533 g4x_raw_plane_wm_set(crtc_state
, level
,
5534 plane_id
, USHRT_MAX
);
5535 g4x_raw_fbc_wm_set(crtc_state
, level
, USHRT_MAX
);
5537 crtc_state
->wm
.g4x
.optimal
= *active
;
5538 crtc_state
->wm
.g4x
.intermediate
= *active
;
5540 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n",
5542 wm
->pipe
[pipe
].plane
[PLANE_PRIMARY
],
5543 wm
->pipe
[pipe
].plane
[PLANE_CURSOR
],
5544 wm
->pipe
[pipe
].plane
[PLANE_SPRITE0
]);
5547 DRM_DEBUG_KMS("Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n",
5548 wm
->sr
.plane
, wm
->sr
.cursor
, wm
->sr
.fbc
);
5549 DRM_DEBUG_KMS("Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n",
5550 wm
->hpll
.plane
, wm
->hpll
.cursor
, wm
->hpll
.fbc
);
5551 DRM_DEBUG_KMS("Initial SR=%s HPLL=%s FBC=%s\n",
5552 yesno(wm
->cxsr
), yesno(wm
->hpll_en
), yesno(wm
->fbc_en
));
5555 void g4x_wm_sanitize(struct drm_i915_private
*dev_priv
)
5557 struct intel_plane
*plane
;
5558 struct intel_crtc
*crtc
;
5560 mutex_lock(&dev_priv
->wm
.wm_mutex
);
5562 for_each_intel_plane(&dev_priv
->drm
, plane
) {
5563 struct intel_crtc
*crtc
=
5564 intel_get_crtc_for_pipe(dev_priv
, plane
->pipe
);
5565 struct intel_crtc_state
*crtc_state
=
5566 to_intel_crtc_state(crtc
->base
.state
);
5567 struct intel_plane_state
*plane_state
=
5568 to_intel_plane_state(plane
->base
.state
);
5569 struct g4x_wm_state
*wm_state
= &crtc_state
->wm
.g4x
.optimal
;
5570 enum plane_id plane_id
= plane
->id
;
5573 if (plane_state
->base
.visible
)
5576 for (level
= 0; level
< 3; level
++) {
5577 struct g4x_pipe_wm
*raw
=
5578 &crtc_state
->wm
.g4x
.raw
[level
];
5580 raw
->plane
[plane_id
] = 0;
5581 wm_state
->wm
.plane
[plane_id
] = 0;
5584 if (plane_id
== PLANE_PRIMARY
) {
5585 for (level
= 0; level
< 3; level
++) {
5586 struct g4x_pipe_wm
*raw
=
5587 &crtc_state
->wm
.g4x
.raw
[level
];
5591 wm_state
->sr
.fbc
= 0;
5592 wm_state
->hpll
.fbc
= 0;
5593 wm_state
->fbc_en
= false;
5597 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
5598 struct intel_crtc_state
*crtc_state
=
5599 to_intel_crtc_state(crtc
->base
.state
);
5601 crtc_state
->wm
.g4x
.intermediate
=
5602 crtc_state
->wm
.g4x
.optimal
;
5603 crtc
->wm
.active
.g4x
= crtc_state
->wm
.g4x
.optimal
;
5606 g4x_program_watermarks(dev_priv
);
5608 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
5611 void vlv_wm_get_hw_state(struct drm_device
*dev
)
5613 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5614 struct vlv_wm_values
*wm
= &dev_priv
->wm
.vlv
;
5615 struct intel_crtc
*crtc
;
5618 vlv_read_wm_values(dev_priv
, wm
);
5620 wm
->cxsr
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
5621 wm
->level
= VLV_WM_LEVEL_PM2
;
5623 if (IS_CHERRYVIEW(dev_priv
)) {
5624 mutex_lock(&dev_priv
->rps
.hw_lock
);
5626 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5627 if (val
& DSP_MAXFIFO_PM5_ENABLE
)
5628 wm
->level
= VLV_WM_LEVEL_PM5
;
5631 * If DDR DVFS is disabled in the BIOS, Punit
5632 * will never ack the request. So if that happens
5633 * assume we don't have to enable/disable DDR DVFS
5634 * dynamically. To test that just set the REQ_ACK
5635 * bit to poke the Punit, but don't change the
5636 * HIGH/LOW bits so that we don't actually change
5637 * the current state.
5639 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
5640 val
|= FORCE_DDR_FREQ_REQ_ACK
;
5641 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
5643 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
5644 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3)) {
5645 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
5646 "assuming DDR DVFS is disabled\n");
5647 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM5
;
5649 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
5650 if ((val
& FORCE_DDR_HIGH_FREQ
) == 0)
5651 wm
->level
= VLV_WM_LEVEL_DDR_DVFS
;
5654 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5657 for_each_intel_crtc(dev
, crtc
) {
5658 struct intel_crtc_state
*crtc_state
=
5659 to_intel_crtc_state(crtc
->base
.state
);
5660 struct vlv_wm_state
*active
= &crtc
->wm
.active
.vlv
;
5661 const struct vlv_fifo_state
*fifo_state
=
5662 &crtc_state
->wm
.vlv
.fifo_state
;
5663 enum pipe pipe
= crtc
->pipe
;
5664 enum plane_id plane_id
;
5667 vlv_get_fifo_size(crtc_state
);
5669 active
->num_levels
= wm
->level
+ 1;
5670 active
->cxsr
= wm
->cxsr
;
5672 for (level
= 0; level
< active
->num_levels
; level
++) {
5673 struct g4x_pipe_wm
*raw
=
5674 &crtc_state
->wm
.vlv
.raw
[level
];
5676 active
->sr
[level
].plane
= wm
->sr
.plane
;
5677 active
->sr
[level
].cursor
= wm
->sr
.cursor
;
5679 for_each_plane_id_on_crtc(crtc
, plane_id
) {
5680 active
->wm
[level
].plane
[plane_id
] =
5681 wm
->pipe
[pipe
].plane
[plane_id
];
5683 raw
->plane
[plane_id
] =
5684 vlv_invert_wm_value(active
->wm
[level
].plane
[plane_id
],
5685 fifo_state
->plane
[plane_id
]);
5689 for_each_plane_id_on_crtc(crtc
, plane_id
)
5690 vlv_raw_plane_wm_set(crtc_state
, level
,
5691 plane_id
, USHRT_MAX
);
5692 vlv_invalidate_wms(crtc
, active
, level
);
5694 crtc_state
->wm
.vlv
.optimal
= *active
;
5695 crtc_state
->wm
.vlv
.intermediate
= *active
;
5697 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
5699 wm
->pipe
[pipe
].plane
[PLANE_PRIMARY
],
5700 wm
->pipe
[pipe
].plane
[PLANE_CURSOR
],
5701 wm
->pipe
[pipe
].plane
[PLANE_SPRITE0
],
5702 wm
->pipe
[pipe
].plane
[PLANE_SPRITE1
]);
5705 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
5706 wm
->sr
.plane
, wm
->sr
.cursor
, wm
->level
, wm
->cxsr
);
5709 void vlv_wm_sanitize(struct drm_i915_private
*dev_priv
)
5711 struct intel_plane
*plane
;
5712 struct intel_crtc
*crtc
;
5714 mutex_lock(&dev_priv
->wm
.wm_mutex
);
5716 for_each_intel_plane(&dev_priv
->drm
, plane
) {
5717 struct intel_crtc
*crtc
=
5718 intel_get_crtc_for_pipe(dev_priv
, plane
->pipe
);
5719 struct intel_crtc_state
*crtc_state
=
5720 to_intel_crtc_state(crtc
->base
.state
);
5721 struct intel_plane_state
*plane_state
=
5722 to_intel_plane_state(plane
->base
.state
);
5723 struct vlv_wm_state
*wm_state
= &crtc_state
->wm
.vlv
.optimal
;
5724 const struct vlv_fifo_state
*fifo_state
=
5725 &crtc_state
->wm
.vlv
.fifo_state
;
5726 enum plane_id plane_id
= plane
->id
;
5729 if (plane_state
->base
.visible
)
5732 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
5733 struct g4x_pipe_wm
*raw
=
5734 &crtc_state
->wm
.vlv
.raw
[level
];
5736 raw
->plane
[plane_id
] = 0;
5738 wm_state
->wm
[level
].plane
[plane_id
] =
5739 vlv_invert_wm_value(raw
->plane
[plane_id
],
5740 fifo_state
->plane
[plane_id
]);
5744 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
5745 struct intel_crtc_state
*crtc_state
=
5746 to_intel_crtc_state(crtc
->base
.state
);
5748 crtc_state
->wm
.vlv
.intermediate
=
5749 crtc_state
->wm
.vlv
.optimal
;
5750 crtc
->wm
.active
.vlv
= crtc_state
->wm
.vlv
.optimal
;
5753 vlv_program_watermarks(dev_priv
);
5755 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
5758 void ilk_wm_get_hw_state(struct drm_device
*dev
)
5760 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5761 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
5762 struct drm_crtc
*crtc
;
5764 for_each_crtc(dev
, crtc
)
5765 ilk_pipe_wm_get_hw_state(crtc
);
5767 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
5768 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
5769 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
5771 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
5772 if (INTEL_GEN(dev_priv
) >= 7) {
5773 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
5774 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
5777 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5778 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
5779 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
5780 else if (IS_IVYBRIDGE(dev_priv
))
5781 hw
->partitioning
= (I915_READ(DISP_ARB_CTL2
) & DISP_DATA_PARTITION_5_6
) ?
5782 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
5785 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
5789 * intel_update_watermarks - update FIFO watermark values based on current modes
5791 * Calculate watermark values for the various WM regs based on current mode
5792 * and plane configuration.
5794 * There are several cases to deal with here:
5795 * - normal (i.e. non-self-refresh)
5796 * - self-refresh (SR) mode
5797 * - lines are large relative to FIFO size (buffer can hold up to 2)
5798 * - lines are small relative to FIFO size (buffer can hold more than 2
5799 * lines), so need to account for TLB latency
5801 * The normal calculation is:
5802 * watermark = dotclock * bytes per pixel * latency
5803 * where latency is platform & configuration dependent (we assume pessimal
5806 * The SR calculation is:
5807 * watermark = (trunc(latency/line time)+1) * surface width *
5810 * line time = htotal / dotclock
5811 * surface width = hdisplay for normal plane and 64 for cursor
5812 * and latency is assumed to be high, as above.
5814 * The final value programmed to the register should always be rounded up,
5815 * and include an extra 2 entries to account for clock crossings.
5817 * We don't use the sprite, so we can ignore that. And on Crestline we have
5818 * to set the non-SR watermarks to 8.
5820 void intel_update_watermarks(struct intel_crtc
*crtc
)
5822 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5824 if (dev_priv
->display
.update_wm
)
5825 dev_priv
->display
.update_wm(crtc
);
5828 void intel_enable_ipc(struct drm_i915_private
*dev_priv
)
5832 /* Display WA #0477 WaDisableIPC: skl */
5833 if (IS_SKYLAKE(dev_priv
)) {
5834 dev_priv
->ipc_enabled
= false;
5838 val
= I915_READ(DISP_ARB_CTL2
);
5840 if (dev_priv
->ipc_enabled
)
5841 val
|= DISP_IPC_ENABLE
;
5843 val
&= ~DISP_IPC_ENABLE
;
5845 I915_WRITE(DISP_ARB_CTL2
, val
);
5848 void intel_init_ipc(struct drm_i915_private
*dev_priv
)
5850 dev_priv
->ipc_enabled
= false;
5851 if (!HAS_IPC(dev_priv
))
5854 dev_priv
->ipc_enabled
= true;
5855 intel_enable_ipc(dev_priv
);
5859 * Lock protecting IPS related data structures
5861 DEFINE_SPINLOCK(mchdev_lock
);
5863 /* Global for IPS driver to get at the current i915 device. Protected by
5865 static struct drm_i915_private
*i915_mch_dev
;
5867 bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
)
5871 lockdep_assert_held(&mchdev_lock
);
5873 rgvswctl
= I915_READ16(MEMSWCTL
);
5874 if (rgvswctl
& MEMCTL_CMD_STS
) {
5875 DRM_DEBUG("gpu busy, RCS change rejected\n");
5876 return false; /* still busy with another command */
5879 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
5880 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
5881 I915_WRITE16(MEMSWCTL
, rgvswctl
);
5882 POSTING_READ16(MEMSWCTL
);
5884 rgvswctl
|= MEMCTL_CMD_STS
;
5885 I915_WRITE16(MEMSWCTL
, rgvswctl
);
5890 static void ironlake_enable_drps(struct drm_i915_private
*dev_priv
)
5893 u8 fmax
, fmin
, fstart
, vstart
;
5895 spin_lock_irq(&mchdev_lock
);
5897 rgvmodectl
= I915_READ(MEMMODECTL
);
5899 /* Enable temp reporting */
5900 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
5901 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
5903 /* 100ms RC evaluation intervals */
5904 I915_WRITE(RCUPEI
, 100000);
5905 I915_WRITE(RCDNEI
, 100000);
5907 /* Set max/min thresholds to 90ms and 80ms respectively */
5908 I915_WRITE(RCBMAXAVG
, 90000);
5909 I915_WRITE(RCBMINAVG
, 80000);
5911 I915_WRITE(MEMIHYST
, 1);
5913 /* Set up min, max, and cur for interrupt handling */
5914 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
5915 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
5916 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
5917 MEMMODE_FSTART_SHIFT
;
5919 vstart
= (I915_READ(PXVFREQ(fstart
)) & PXVFREQ_PX_MASK
) >>
5922 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
5923 dev_priv
->ips
.fstart
= fstart
;
5925 dev_priv
->ips
.max_delay
= fstart
;
5926 dev_priv
->ips
.min_delay
= fmin
;
5927 dev_priv
->ips
.cur_delay
= fstart
;
5929 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5930 fmax
, fmin
, fstart
);
5932 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
5935 * Interrupts will be enabled in ironlake_irq_postinstall
5938 I915_WRITE(VIDSTART
, vstart
);
5939 POSTING_READ(VIDSTART
);
5941 rgvmodectl
|= MEMMODE_SWMODE_EN
;
5942 I915_WRITE(MEMMODECTL
, rgvmodectl
);
5944 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
5945 DRM_ERROR("stuck trying to change perf mode\n");
5948 ironlake_set_drps(dev_priv
, fstart
);
5950 dev_priv
->ips
.last_count1
= I915_READ(DMIEC
) +
5951 I915_READ(DDREC
) + I915_READ(CSIEC
);
5952 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
5953 dev_priv
->ips
.last_count2
= I915_READ(GFXEC
);
5954 dev_priv
->ips
.last_time2
= ktime_get_raw_ns();
5956 spin_unlock_irq(&mchdev_lock
);
5959 static void ironlake_disable_drps(struct drm_i915_private
*dev_priv
)
5963 spin_lock_irq(&mchdev_lock
);
5965 rgvswctl
= I915_READ16(MEMSWCTL
);
5967 /* Ack interrupts, disable EFC interrupt */
5968 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
5969 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
5970 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
5971 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
5972 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
5974 /* Go back to the starting frequency */
5975 ironlake_set_drps(dev_priv
, dev_priv
->ips
.fstart
);
5977 rgvswctl
|= MEMCTL_CMD_STS
;
5978 I915_WRITE(MEMSWCTL
, rgvswctl
);
5981 spin_unlock_irq(&mchdev_lock
);
5984 /* There's a funny hw issue where the hw returns all 0 when reading from
5985 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
5986 * ourselves, instead of doing a rmw cycle (which might result in us clearing
5987 * all limits and the gpu stuck at whatever frequency it is at atm).
5989 static u32
intel_rps_limits(struct drm_i915_private
*dev_priv
, u8 val
)
5993 /* Only set the down limit when we've reached the lowest level to avoid
5994 * getting more interrupts, otherwise leave this clear. This prevents a
5995 * race in the hw when coming out of rc6: There's a tiny window where
5996 * the hw runs at the minimal clock before selecting the desired
5997 * frequency, if the down threshold expires in that window we will not
5998 * receive a down interrupt. */
5999 if (INTEL_GEN(dev_priv
) >= 9) {
6000 limits
= (dev_priv
->rps
.max_freq_softlimit
) << 23;
6001 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
6002 limits
|= (dev_priv
->rps
.min_freq_softlimit
) << 14;
6004 limits
= dev_priv
->rps
.max_freq_softlimit
<< 24;
6005 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
6006 limits
|= dev_priv
->rps
.min_freq_softlimit
<< 16;
6012 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
6015 u32 threshold_up
= 0, threshold_down
= 0; /* in % */
6016 u32 ei_up
= 0, ei_down
= 0;
6018 new_power
= dev_priv
->rps
.power
;
6019 switch (dev_priv
->rps
.power
) {
6021 if (val
> dev_priv
->rps
.efficient_freq
+ 1 &&
6022 val
> dev_priv
->rps
.cur_freq
)
6023 new_power
= BETWEEN
;
6027 if (val
<= dev_priv
->rps
.efficient_freq
&&
6028 val
< dev_priv
->rps
.cur_freq
)
6029 new_power
= LOW_POWER
;
6030 else if (val
>= dev_priv
->rps
.rp0_freq
&&
6031 val
> dev_priv
->rps
.cur_freq
)
6032 new_power
= HIGH_POWER
;
6036 if (val
< (dev_priv
->rps
.rp1_freq
+ dev_priv
->rps
.rp0_freq
) >> 1 &&
6037 val
< dev_priv
->rps
.cur_freq
)
6038 new_power
= BETWEEN
;
6041 /* Max/min bins are special */
6042 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
6043 new_power
= LOW_POWER
;
6044 if (val
>= dev_priv
->rps
.max_freq_softlimit
)
6045 new_power
= HIGH_POWER
;
6046 if (new_power
== dev_priv
->rps
.power
)
6049 /* Note the units here are not exactly 1us, but 1280ns. */
6050 switch (new_power
) {
6052 /* Upclock if more than 95% busy over 16ms */
6056 /* Downclock if less than 85% busy over 32ms */
6058 threshold_down
= 85;
6062 /* Upclock if more than 90% busy over 13ms */
6066 /* Downclock if less than 75% busy over 32ms */
6068 threshold_down
= 75;
6072 /* Upclock if more than 85% busy over 10ms */
6076 /* Downclock if less than 60% busy over 32ms */
6078 threshold_down
= 60;
6082 /* When byt can survive without system hang with dynamic
6083 * sw freq adjustments, this restriction can be lifted.
6085 if (IS_VALLEYVIEW(dev_priv
))
6088 I915_WRITE(GEN6_RP_UP_EI
,
6089 GT_INTERVAL_FROM_US(dev_priv
, ei_up
));
6090 I915_WRITE(GEN6_RP_UP_THRESHOLD
,
6091 GT_INTERVAL_FROM_US(dev_priv
,
6092 ei_up
* threshold_up
/ 100));
6094 I915_WRITE(GEN6_RP_DOWN_EI
,
6095 GT_INTERVAL_FROM_US(dev_priv
, ei_down
));
6096 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
,
6097 GT_INTERVAL_FROM_US(dev_priv
,
6098 ei_down
* threshold_down
/ 100));
6100 I915_WRITE(GEN6_RP_CONTROL
,
6101 GEN6_RP_MEDIA_TURBO
|
6102 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
6103 GEN6_RP_MEDIA_IS_GFX
|
6105 GEN6_RP_UP_BUSY_AVG
|
6106 GEN6_RP_DOWN_IDLE_AVG
);
6109 dev_priv
->rps
.power
= new_power
;
6110 dev_priv
->rps
.up_threshold
= threshold_up
;
6111 dev_priv
->rps
.down_threshold
= threshold_down
;
6112 dev_priv
->rps
.last_adj
= 0;
6115 static u32
gen6_rps_pm_mask(struct drm_i915_private
*dev_priv
, u8 val
)
6119 /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
6120 if (val
> dev_priv
->rps
.min_freq_softlimit
)
6121 mask
|= GEN6_PM_RP_UP_EI_EXPIRED
| GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT
;
6122 if (val
< dev_priv
->rps
.max_freq_softlimit
)
6123 mask
|= GEN6_PM_RP_UP_EI_EXPIRED
| GEN6_PM_RP_UP_THRESHOLD
;
6125 mask
&= dev_priv
->pm_rps_events
;
6127 return gen6_sanitize_rps_pm_mask(dev_priv
, ~mask
);
6130 /* gen6_set_rps is called to update the frequency request, but should also be
6131 * called when the range (min_delay and max_delay) is modified so that we can
6132 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
6133 static int gen6_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
6135 /* min/max delay may still have been modified so be sure to
6136 * write the limits value.
6138 if (val
!= dev_priv
->rps
.cur_freq
) {
6139 gen6_set_rps_thresholds(dev_priv
, val
);
6141 if (INTEL_GEN(dev_priv
) >= 9)
6142 I915_WRITE(GEN6_RPNSWREQ
,
6143 GEN9_FREQUENCY(val
));
6144 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
6145 I915_WRITE(GEN6_RPNSWREQ
,
6146 HSW_FREQUENCY(val
));
6148 I915_WRITE(GEN6_RPNSWREQ
,
6149 GEN6_FREQUENCY(val
) |
6151 GEN6_AGGRESSIVE_TURBO
);
6154 /* Make sure we continue to get interrupts
6155 * until we hit the minimum or maximum frequencies.
6157 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, intel_rps_limits(dev_priv
, val
));
6158 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
6160 dev_priv
->rps
.cur_freq
= val
;
6161 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
6166 static int valleyview_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
6170 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv
) && (val
& 1),
6171 "Odd GPU freq value\n"))
6174 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
6176 if (val
!= dev_priv
->rps
.cur_freq
) {
6177 err
= vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
6181 gen6_set_rps_thresholds(dev_priv
, val
);
6184 dev_priv
->rps
.cur_freq
= val
;
6185 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
6190 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
6192 * * If Gfx is Idle, then
6193 * 1. Forcewake Media well.
6194 * 2. Request idle freq.
6195 * 3. Release Forcewake of Media well.
6197 static void vlv_set_rps_idle(struct drm_i915_private
*dev_priv
)
6199 u32 val
= dev_priv
->rps
.idle_freq
;
6202 if (dev_priv
->rps
.cur_freq
<= val
)
6205 /* The punit delays the write of the frequency and voltage until it
6206 * determines the GPU is awake. During normal usage we don't want to
6207 * waste power changing the frequency if the GPU is sleeping (rc6).
6208 * However, the GPU and driver is now idle and we do not want to delay
6209 * switching to minimum voltage (reducing power whilst idle) as we do
6210 * not expect to be woken in the near future and so must flush the
6211 * change by waking the device.
6213 * We choose to take the media powerwell (either would do to trick the
6214 * punit into committing the voltage change) as that takes a lot less
6215 * power than the render powerwell.
6217 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_MEDIA
);
6218 err
= valleyview_set_rps(dev_priv
, val
);
6219 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_MEDIA
);
6222 DRM_ERROR("Failed to set RPS for idle\n");
6225 void gen6_rps_busy(struct drm_i915_private
*dev_priv
)
6227 mutex_lock(&dev_priv
->rps
.hw_lock
);
6228 if (dev_priv
->rps
.enabled
) {
6231 if (dev_priv
->pm_rps_events
& GEN6_PM_RP_UP_EI_EXPIRED
)
6232 gen6_rps_reset_ei(dev_priv
);
6233 I915_WRITE(GEN6_PMINTRMSK
,
6234 gen6_rps_pm_mask(dev_priv
, dev_priv
->rps
.cur_freq
));
6236 gen6_enable_rps_interrupts(dev_priv
);
6238 /* Use the user's desired frequency as a guide, but for better
6239 * performance, jump directly to RPe as our starting frequency.
6241 freq
= max(dev_priv
->rps
.cur_freq
,
6242 dev_priv
->rps
.efficient_freq
);
6244 if (intel_set_rps(dev_priv
,
6246 dev_priv
->rps
.min_freq_softlimit
,
6247 dev_priv
->rps
.max_freq_softlimit
)))
6248 DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
6250 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6253 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
6255 /* Flush our bottom-half so that it does not race with us
6256 * setting the idle frequency and so that it is bounded by
6257 * our rpm wakeref. And then disable the interrupts to stop any
6258 * futher RPS reclocking whilst we are asleep.
6260 gen6_disable_rps_interrupts(dev_priv
);
6262 mutex_lock(&dev_priv
->rps
.hw_lock
);
6263 if (dev_priv
->rps
.enabled
) {
6264 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
6265 vlv_set_rps_idle(dev_priv
);
6267 gen6_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
6268 dev_priv
->rps
.last_adj
= 0;
6269 I915_WRITE(GEN6_PMINTRMSK
,
6270 gen6_sanitize_rps_pm_mask(dev_priv
, ~0));
6272 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6275 void gen6_rps_boost(struct drm_i915_gem_request
*rq
,
6276 struct intel_rps_client
*rps
)
6278 struct drm_i915_private
*i915
= rq
->i915
;
6279 unsigned long flags
;
6282 /* This is intentionally racy! We peek at the state here, then
6283 * validate inside the RPS worker.
6285 if (!i915
->rps
.enabled
)
6289 spin_lock_irqsave(&rq
->lock
, flags
);
6290 if (!rq
->waitboost
&& !i915_gem_request_completed(rq
)) {
6291 atomic_inc(&i915
->rps
.num_waiters
);
6292 rq
->waitboost
= true;
6295 spin_unlock_irqrestore(&rq
->lock
, flags
);
6299 if (READ_ONCE(i915
->rps
.cur_freq
) < i915
->rps
.boost_freq
)
6300 schedule_work(&i915
->rps
.work
);
6302 atomic_inc(rps
? &rps
->boosts
: &i915
->rps
.boosts
);
6305 int intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
6309 lockdep_assert_held(&dev_priv
->rps
.hw_lock
);
6310 GEM_BUG_ON(val
> dev_priv
->rps
.max_freq
);
6311 GEM_BUG_ON(val
< dev_priv
->rps
.min_freq
);
6313 if (!dev_priv
->rps
.enabled
) {
6314 dev_priv
->rps
.cur_freq
= val
;
6318 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
6319 err
= valleyview_set_rps(dev_priv
, val
);
6321 err
= gen6_set_rps(dev_priv
, val
);
6326 static void gen9_disable_rc6(struct drm_i915_private
*dev_priv
)
6328 I915_WRITE(GEN6_RC_CONTROL
, 0);
6329 I915_WRITE(GEN9_PG_ENABLE
, 0);
6332 static void gen9_disable_rps(struct drm_i915_private
*dev_priv
)
6334 I915_WRITE(GEN6_RP_CONTROL
, 0);
6337 static void gen6_disable_rc6(struct drm_i915_private
*dev_priv
)
6339 I915_WRITE(GEN6_RC_CONTROL
, 0);
6342 static void gen6_disable_rps(struct drm_i915_private
*dev_priv
)
6344 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
6345 I915_WRITE(GEN6_RP_CONTROL
, 0);
6348 static void cherryview_disable_rps(struct drm_i915_private
*dev_priv
)
6350 I915_WRITE(GEN6_RC_CONTROL
, 0);
6353 static void valleyview_disable_rc6(struct drm_i915_private
*dev_priv
)
6355 /* We're doing forcewake before Disabling RC6,
6356 * This what the BIOS expects when going into suspend */
6357 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6359 I915_WRITE(GEN6_RC_CONTROL
, 0);
6361 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6364 static void valleyview_disable_rps(struct drm_i915_private
*dev_priv
)
6366 I915_WRITE(GEN6_RP_CONTROL
, 0);
6369 static void intel_print_rc6_info(struct drm_i915_private
*dev_priv
, u32 mode
)
6371 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
6372 if (mode
& (GEN7_RC_CTL_TO_MODE
| GEN6_RC_CTL_EI_MODE(1)))
6373 mode
= GEN6_RC_CTL_RC6_ENABLE
;
6377 if (HAS_RC6p(dev_priv
))
6378 DRM_DEBUG_DRIVER("Enabling RC6 states: "
6379 "RC6 %s RC6p %s RC6pp %s\n",
6380 onoff(mode
& GEN6_RC_CTL_RC6_ENABLE
),
6381 onoff(mode
& GEN6_RC_CTL_RC6p_ENABLE
),
6382 onoff(mode
& GEN6_RC_CTL_RC6pp_ENABLE
));
6385 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
6386 onoff(mode
& GEN6_RC_CTL_RC6_ENABLE
));
6389 static bool bxt_check_bios_rc6_setup(struct drm_i915_private
*dev_priv
)
6391 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
6392 bool enable_rc6
= true;
6393 unsigned long rc6_ctx_base
;
6397 rc_ctl
= I915_READ(GEN6_RC_CONTROL
);
6398 rc_sw_target
= (I915_READ(GEN6_RC_STATE
) & RC_SW_TARGET_STATE_MASK
) >>
6399 RC_SW_TARGET_STATE_SHIFT
;
6400 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
6401 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
6402 onoff(rc_ctl
& GEN6_RC_CTL_HW_ENABLE
),
6403 onoff(rc_ctl
& GEN6_RC_CTL_RC6_ENABLE
),
6406 if (!(I915_READ(RC6_LOCATION
) & RC6_CTX_IN_DRAM
)) {
6407 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
6412 * The exact context size is not known for BXT, so assume a page size
6415 rc6_ctx_base
= I915_READ(RC6_CTX_BASE
) & RC6_CTX_BASE_MASK
;
6416 if (!((rc6_ctx_base
>= ggtt
->stolen_reserved_base
) &&
6417 (rc6_ctx_base
+ PAGE_SIZE
<= ggtt
->stolen_reserved_base
+
6418 ggtt
->stolen_reserved_size
))) {
6419 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
6423 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT
) & IDLE_TIME_MASK
) > 1) &&
6424 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0
) & IDLE_TIME_MASK
) > 1) &&
6425 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT
) & IDLE_TIME_MASK
) > 1) &&
6426 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT
) & IDLE_TIME_MASK
) > 1))) {
6427 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
6431 if (!I915_READ(GEN8_PUSHBUS_CONTROL
) ||
6432 !I915_READ(GEN8_PUSHBUS_ENABLE
) ||
6433 !I915_READ(GEN8_PUSHBUS_SHIFT
)) {
6434 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
6438 if (!I915_READ(GEN6_GFXPAUSE
)) {
6439 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
6443 if (!I915_READ(GEN8_MISC_CTRL0
)) {
6444 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
6451 int sanitize_rc6_option(struct drm_i915_private
*dev_priv
, int enable_rc6
)
6453 /* No RC6 before Ironlake and code is gone for ilk. */
6454 if (INTEL_INFO(dev_priv
)->gen
< 6)
6460 if (IS_GEN9_LP(dev_priv
) && !bxt_check_bios_rc6_setup(dev_priv
)) {
6461 DRM_INFO("RC6 disabled by BIOS\n");
6465 /* Respect the kernel parameter if it is set */
6466 if (enable_rc6
>= 0) {
6469 if (HAS_RC6p(dev_priv
))
6470 mask
= INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
|
6473 mask
= INTEL_RC6_ENABLE
;
6475 if ((enable_rc6
& mask
) != enable_rc6
)
6476 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
6477 "(requested %d, valid %d)\n",
6478 enable_rc6
& mask
, enable_rc6
, mask
);
6480 return enable_rc6
& mask
;
6483 if (IS_IVYBRIDGE(dev_priv
))
6484 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
6486 return INTEL_RC6_ENABLE
;
6489 static void gen6_init_rps_frequencies(struct drm_i915_private
*dev_priv
)
6491 /* All of these values are in units of 50MHz */
6493 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
6494 if (IS_GEN9_LP(dev_priv
)) {
6495 u32 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
6496 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 16) & 0xff;
6497 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
6498 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 0) & 0xff;
6500 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
6501 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 0) & 0xff;
6502 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
6503 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 16) & 0xff;
6505 /* hw_max = RP0 until we check for overclocking */
6506 dev_priv
->rps
.max_freq
= dev_priv
->rps
.rp0_freq
;
6508 dev_priv
->rps
.efficient_freq
= dev_priv
->rps
.rp1_freq
;
6509 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
) ||
6510 IS_GEN9_BC(dev_priv
) || IS_CANNONLAKE(dev_priv
)) {
6511 u32 ddcc_status
= 0;
6513 if (sandybridge_pcode_read(dev_priv
,
6514 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL
,
6516 dev_priv
->rps
.efficient_freq
=
6518 ((ddcc_status
>> 8) & 0xff),
6519 dev_priv
->rps
.min_freq
,
6520 dev_priv
->rps
.max_freq
);
6523 if (IS_GEN9_BC(dev_priv
) || IS_CANNONLAKE(dev_priv
)) {
6524 /* Store the frequency values in 16.66 MHZ units, which is
6525 * the natural hardware unit for SKL
6527 dev_priv
->rps
.rp0_freq
*= GEN9_FREQ_SCALER
;
6528 dev_priv
->rps
.rp1_freq
*= GEN9_FREQ_SCALER
;
6529 dev_priv
->rps
.min_freq
*= GEN9_FREQ_SCALER
;
6530 dev_priv
->rps
.max_freq
*= GEN9_FREQ_SCALER
;
6531 dev_priv
->rps
.efficient_freq
*= GEN9_FREQ_SCALER
;
6535 static void reset_rps(struct drm_i915_private
*dev_priv
,
6536 int (*set
)(struct drm_i915_private
*, u8
))
6538 u8 freq
= dev_priv
->rps
.cur_freq
;
6541 dev_priv
->rps
.power
= -1;
6542 dev_priv
->rps
.cur_freq
= -1;
6544 if (set(dev_priv
, freq
))
6545 DRM_ERROR("Failed to reset RPS to initial values\n");
6548 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
6549 static void gen9_enable_rps(struct drm_i915_private
*dev_priv
)
6551 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6553 /* Program defaults and thresholds for RPS*/
6554 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
6555 GEN9_FREQUENCY(dev_priv
->rps
.rp1_freq
));
6557 /* 1 second timeout*/
6558 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,
6559 GT_INTERVAL_FROM_US(dev_priv
, 1000000));
6561 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 0xa);
6563 /* Leaning on the below call to gen6_set_rps to program/setup the
6564 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
6565 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
6566 reset_rps(dev_priv
, gen6_set_rps
);
6568 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6571 static void gen9_enable_rc6(struct drm_i915_private
*dev_priv
)
6573 struct intel_engine_cs
*engine
;
6574 enum intel_engine_id id
;
6575 uint32_t rc6_mask
= 0;
6577 /* 1a: Software RC state - RC0 */
6578 I915_WRITE(GEN6_RC_STATE
, 0);
6580 /* 1b: Get forcewake during program sequence. Although the driver
6581 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6582 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6584 /* 2a: Disable RC states. */
6585 I915_WRITE(GEN6_RC_CONTROL
, 0);
6587 /* 2b: Program RC6 thresholds.*/
6589 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
6590 if (IS_SKYLAKE(dev_priv
))
6591 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 108 << 16);
6593 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 54 << 16);
6594 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
6595 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
6596 for_each_engine(engine
, dev_priv
, id
)
6597 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
6599 if (HAS_GUC(dev_priv
))
6600 I915_WRITE(GUC_MAX_IDLE_COUNT
, 0xA);
6602 I915_WRITE(GEN6_RC_SLEEP
, 0);
6604 /* 2c: Program Coarse Power Gating Policies. */
6605 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS
, 25);
6606 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS
, 25);
6608 /* 3a: Enable RC6 */
6609 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
6610 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
6611 DRM_INFO("RC6 %s\n", onoff(rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
));
6612 I915_WRITE(GEN6_RC6_THRESHOLD
, 37500); /* 37.5/125ms per EI */
6613 I915_WRITE(GEN6_RC_CONTROL
,
6614 GEN6_RC_CTL_HW_ENABLE
| GEN6_RC_CTL_EI_MODE(1) | rc6_mask
);
6617 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
6618 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
6620 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv
))
6621 I915_WRITE(GEN9_PG_ENABLE
, 0);
6623 I915_WRITE(GEN9_PG_ENABLE
, (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ?
6624 (GEN9_RENDER_PG_ENABLE
| GEN9_MEDIA_PG_ENABLE
) : 0);
6626 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6629 static void gen8_enable_rc6(struct drm_i915_private
*dev_priv
)
6631 struct intel_engine_cs
*engine
;
6632 enum intel_engine_id id
;
6633 uint32_t rc6_mask
= 0;
6635 /* 1a: Software RC state - RC0 */
6636 I915_WRITE(GEN6_RC_STATE
, 0);
6638 /* 1b: Get forcewake during program sequence. Although the driver
6639 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6640 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6642 /* 2a: Disable RC states. */
6643 I915_WRITE(GEN6_RC_CONTROL
, 0);
6645 /* 2b: Program RC6 thresholds.*/
6646 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
6647 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
6648 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
6649 for_each_engine(engine
, dev_priv
, id
)
6650 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
6651 I915_WRITE(GEN6_RC_SLEEP
, 0);
6652 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us/1.28 for TO */
6655 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
6656 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
6657 intel_print_rc6_info(dev_priv
, rc6_mask
);
6659 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
6660 GEN7_RC_CTL_TO_MODE
|
6663 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6666 static void gen8_enable_rps(struct drm_i915_private
*dev_priv
)
6668 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6670 /* 1 Program defaults and thresholds for RPS*/
6671 I915_WRITE(GEN6_RPNSWREQ
,
6672 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
6673 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
6674 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
6675 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
6676 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 100000000 / 128); /* 1 second timeout */
6678 /* Docs recommend 900MHz, and 300 MHz respectively */
6679 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
6680 dev_priv
->rps
.max_freq_softlimit
<< 24 |
6681 dev_priv
->rps
.min_freq_softlimit
<< 16);
6683 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 7600000 / 128); /* 76ms busyness per EI, 90% */
6684 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 31300000 / 128); /* 313ms busyness per EI, 70%*/
6685 I915_WRITE(GEN6_RP_UP_EI
, 66000); /* 84.48ms, XXX: random? */
6686 I915_WRITE(GEN6_RP_DOWN_EI
, 350000); /* 448ms, XXX: random? */
6688 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
6691 I915_WRITE(GEN6_RP_CONTROL
,
6692 GEN6_RP_MEDIA_TURBO
|
6693 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
6694 GEN6_RP_MEDIA_IS_GFX
|
6696 GEN6_RP_UP_BUSY_AVG
|
6697 GEN6_RP_DOWN_IDLE_AVG
);
6699 reset_rps(dev_priv
, gen6_set_rps
);
6701 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6704 static void gen6_enable_rc6(struct drm_i915_private
*dev_priv
)
6706 struct intel_engine_cs
*engine
;
6707 enum intel_engine_id id
;
6708 u32 rc6vids
, rc6_mask
= 0;
6713 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6715 I915_WRITE(GEN6_RC_STATE
, 0);
6717 /* Clear the DBG now so we don't confuse earlier errors */
6718 gtfifodbg
= I915_READ(GTFIFODBG
);
6720 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
6721 I915_WRITE(GTFIFODBG
, gtfifodbg
);
6724 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6726 /* disable the counters and set deterministic thresholds */
6727 I915_WRITE(GEN6_RC_CONTROL
, 0);
6729 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
6730 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
6731 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
6732 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
6733 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
6735 for_each_engine(engine
, dev_priv
, id
)
6736 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
6738 I915_WRITE(GEN6_RC_SLEEP
, 0);
6739 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
6740 if (IS_IVYBRIDGE(dev_priv
))
6741 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
6743 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
6744 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
6745 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
6747 /* Check if we are enabling RC6 */
6748 rc6_mode
= intel_enable_rc6();
6749 if (rc6_mode
& INTEL_RC6_ENABLE
)
6750 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
6752 /* We don't use those on Haswell */
6753 if (!IS_HASWELL(dev_priv
)) {
6754 if (rc6_mode
& INTEL_RC6p_ENABLE
)
6755 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
6757 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
6758 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
6761 intel_print_rc6_info(dev_priv
, rc6_mask
);
6763 I915_WRITE(GEN6_RC_CONTROL
,
6765 GEN6_RC_CTL_EI_MODE(1) |
6766 GEN6_RC_CTL_HW_ENABLE
);
6769 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
6770 if (IS_GEN6(dev_priv
) && ret
) {
6771 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
6772 } else if (IS_GEN6(dev_priv
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
6773 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
6774 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
6775 rc6vids
&= 0xffff00;
6776 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
6777 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
6779 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
6782 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6785 static void gen6_enable_rps(struct drm_i915_private
*dev_priv
)
6787 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6789 /* Here begins a magic sequence of register writes to enable
6790 * auto-downclocking.
6792 * Perhaps there might be some value in exposing these to
6795 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6797 /* Power down if completely idle for over 50ms */
6798 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
6799 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
6801 reset_rps(dev_priv
, gen6_set_rps
);
6803 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6806 static void gen6_update_ring_freq(struct drm_i915_private
*dev_priv
)
6809 unsigned int gpu_freq
;
6810 unsigned int max_ia_freq
, min_ring_freq
;
6811 unsigned int max_gpu_freq
, min_gpu_freq
;
6812 int scaling_factor
= 180;
6813 struct cpufreq_policy
*policy
;
6815 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6817 policy
= cpufreq_cpu_get(0);
6819 max_ia_freq
= policy
->cpuinfo
.max_freq
;
6820 cpufreq_cpu_put(policy
);
6823 * Default to measured freq if none found, PCU will ensure we
6826 max_ia_freq
= tsc_khz
;
6829 /* Convert from kHz to MHz */
6830 max_ia_freq
/= 1000;
6832 min_ring_freq
= I915_READ(DCLK
) & 0xf;
6833 /* convert DDR frequency from units of 266.6MHz to bandwidth */
6834 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
6836 if (IS_GEN9_BC(dev_priv
) || IS_CANNONLAKE(dev_priv
)) {
6837 /* Convert GT frequency to 50 HZ units */
6838 min_gpu_freq
= dev_priv
->rps
.min_freq
/ GEN9_FREQ_SCALER
;
6839 max_gpu_freq
= dev_priv
->rps
.max_freq
/ GEN9_FREQ_SCALER
;
6841 min_gpu_freq
= dev_priv
->rps
.min_freq
;
6842 max_gpu_freq
= dev_priv
->rps
.max_freq
;
6846 * For each potential GPU frequency, load a ring frequency we'd like
6847 * to use for memory access. We do this by specifying the IA frequency
6848 * the PCU should use as a reference to determine the ring frequency.
6850 for (gpu_freq
= max_gpu_freq
; gpu_freq
>= min_gpu_freq
; gpu_freq
--) {
6851 int diff
= max_gpu_freq
- gpu_freq
;
6852 unsigned int ia_freq
= 0, ring_freq
= 0;
6854 if (IS_GEN9_BC(dev_priv
) || IS_CANNONLAKE(dev_priv
)) {
6856 * ring_freq = 2 * GT. ring_freq is in 100MHz units
6857 * No floor required for ring frequency on SKL.
6859 ring_freq
= gpu_freq
;
6860 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
6861 /* max(2 * GT, DDR). NB: GT is 50MHz units */
6862 ring_freq
= max(min_ring_freq
, gpu_freq
);
6863 } else if (IS_HASWELL(dev_priv
)) {
6864 ring_freq
= mult_frac(gpu_freq
, 5, 4);
6865 ring_freq
= max(min_ring_freq
, ring_freq
);
6866 /* leave ia_freq as the default, chosen by cpufreq */
6868 /* On older processors, there is no separate ring
6869 * clock domain, so in order to boost the bandwidth
6870 * of the ring, we need to upclock the CPU (ia_freq).
6872 * For GPU frequencies less than 750MHz,
6873 * just use the lowest ring freq.
6875 if (gpu_freq
< min_freq
)
6878 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
6879 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
6882 sandybridge_pcode_write(dev_priv
,
6883 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
6884 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
6885 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
6890 static int cherryview_rps_max_freq(struct drm_i915_private
*dev_priv
)
6894 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
6896 switch (INTEL_INFO(dev_priv
)->sseu
.eu_total
) {
6898 /* (2 * 4) config */
6899 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT
);
6902 /* (2 * 6) config */
6903 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT
);
6906 /* (2 * 8) config */
6908 /* Setting (2 * 8) Min RP0 for any other combination */
6909 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT
);
6913 rp0
= (rp0
& FB_GFX_FREQ_FUSE_MASK
);
6918 static int cherryview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
6922 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_DUTYCYCLE_REG
);
6923 rpe
= (val
>> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT
) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK
;
6928 static int cherryview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
6932 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
6933 rp1
= (val
& FB_GFX_FREQ_FUSE_MASK
);
6938 static u32
cherryview_rps_min_freq(struct drm_i915_private
*dev_priv
)
6942 val
= vlv_punit_read(dev_priv
, FB_GFX_FMIN_AT_VMIN_FUSE
);
6943 rpn
= ((val
>> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT
) &
6944 FB_GFX_FREQ_FUSE_MASK
);
6949 static int valleyview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
6953 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
6955 rp1
= (val
& FB_GFX_FGUARANTEED_FREQ_FUSE_MASK
) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT
;
6960 static int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
6964 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
6966 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
6968 rp0
= min_t(u32
, rp0
, 0xea);
6973 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
6977 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
6978 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
6979 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
6980 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
6985 static int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
6989 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
6991 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
6992 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
6993 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
6994 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
6995 * to make sure it matches what Punit accepts.
6997 return max_t(u32
, val
, 0xc0);
7000 /* Check that the pctx buffer wasn't move under us. */
7001 static void valleyview_check_pctx(struct drm_i915_private
*dev_priv
)
7003 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
7005 WARN_ON(pctx_addr
!= dev_priv
->mm
.stolen_base
+
7006 dev_priv
->vlv_pctx
->stolen
->start
);
7010 /* Check that the pcbr address is not empty. */
7011 static void cherryview_check_pctx(struct drm_i915_private
*dev_priv
)
7013 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
7015 WARN_ON((pctx_addr
>> VLV_PCBR_ADDR_SHIFT
) == 0);
7018 static void cherryview_setup_pctx(struct drm_i915_private
*dev_priv
)
7020 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
7021 unsigned long pctx_paddr
, paddr
;
7023 int pctx_size
= 32*1024;
7025 pcbr
= I915_READ(VLV_PCBR
);
7026 if ((pcbr
>> VLV_PCBR_ADDR_SHIFT
) == 0) {
7027 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
7028 paddr
= (dev_priv
->mm
.stolen_base
+
7029 (ggtt
->stolen_size
- pctx_size
));
7031 pctx_paddr
= (paddr
& (~4095));
7032 I915_WRITE(VLV_PCBR
, pctx_paddr
);
7035 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
7038 static void valleyview_setup_pctx(struct drm_i915_private
*dev_priv
)
7040 struct drm_i915_gem_object
*pctx
;
7041 unsigned long pctx_paddr
;
7043 int pctx_size
= 24*1024;
7045 pcbr
= I915_READ(VLV_PCBR
);
7047 /* BIOS set it up already, grab the pre-alloc'd space */
7050 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
7051 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
,
7053 I915_GTT_OFFSET_NONE
,
7058 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
7061 * From the Gunit register HAS:
7062 * The Gfx driver is expected to program this register and ensure
7063 * proper allocation within Gfx stolen memory. For example, this
7064 * register should be programmed such than the PCBR range does not
7065 * overlap with other ranges, such as the frame buffer, protected
7066 * memory, or any other relevant ranges.
7068 pctx
= i915_gem_object_create_stolen(dev_priv
, pctx_size
);
7070 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
7074 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
7075 I915_WRITE(VLV_PCBR
, pctx_paddr
);
7078 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
7079 dev_priv
->vlv_pctx
= pctx
;
7082 static void valleyview_cleanup_pctx(struct drm_i915_private
*dev_priv
)
7084 if (WARN_ON(!dev_priv
->vlv_pctx
))
7087 i915_gem_object_put(dev_priv
->vlv_pctx
);
7088 dev_priv
->vlv_pctx
= NULL
;
7091 static void vlv_init_gpll_ref_freq(struct drm_i915_private
*dev_priv
)
7093 dev_priv
->rps
.gpll_ref_freq
=
7094 vlv_get_cck_clock(dev_priv
, "GPLL ref",
7095 CCK_GPLL_CLOCK_CONTROL
,
7096 dev_priv
->czclk_freq
);
7098 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
7099 dev_priv
->rps
.gpll_ref_freq
);
7102 static void valleyview_init_gt_powersave(struct drm_i915_private
*dev_priv
)
7106 valleyview_setup_pctx(dev_priv
);
7108 vlv_init_gpll_ref_freq(dev_priv
);
7110 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
7111 switch ((val
>> 6) & 3) {
7114 dev_priv
->mem_freq
= 800;
7117 dev_priv
->mem_freq
= 1066;
7120 dev_priv
->mem_freq
= 1333;
7123 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
7125 dev_priv
->rps
.max_freq
= valleyview_rps_max_freq(dev_priv
);
7126 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
7127 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7128 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
7129 dev_priv
->rps
.max_freq
);
7131 dev_priv
->rps
.efficient_freq
= valleyview_rps_rpe_freq(dev_priv
);
7132 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7133 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
7134 dev_priv
->rps
.efficient_freq
);
7136 dev_priv
->rps
.rp1_freq
= valleyview_rps_guar_freq(dev_priv
);
7137 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7138 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
7139 dev_priv
->rps
.rp1_freq
);
7141 dev_priv
->rps
.min_freq
= valleyview_rps_min_freq(dev_priv
);
7142 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7143 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
7144 dev_priv
->rps
.min_freq
);
7147 static void cherryview_init_gt_powersave(struct drm_i915_private
*dev_priv
)
7151 cherryview_setup_pctx(dev_priv
);
7153 vlv_init_gpll_ref_freq(dev_priv
);
7155 mutex_lock(&dev_priv
->sb_lock
);
7156 val
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
);
7157 mutex_unlock(&dev_priv
->sb_lock
);
7159 switch ((val
>> 2) & 0x7) {
7161 dev_priv
->mem_freq
= 2000;
7164 dev_priv
->mem_freq
= 1600;
7167 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
7169 dev_priv
->rps
.max_freq
= cherryview_rps_max_freq(dev_priv
);
7170 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
7171 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7172 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
7173 dev_priv
->rps
.max_freq
);
7175 dev_priv
->rps
.efficient_freq
= cherryview_rps_rpe_freq(dev_priv
);
7176 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7177 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
7178 dev_priv
->rps
.efficient_freq
);
7180 dev_priv
->rps
.rp1_freq
= cherryview_rps_guar_freq(dev_priv
);
7181 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7182 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
7183 dev_priv
->rps
.rp1_freq
);
7185 dev_priv
->rps
.min_freq
= cherryview_rps_min_freq(dev_priv
);
7186 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7187 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
7188 dev_priv
->rps
.min_freq
);
7190 WARN_ONCE((dev_priv
->rps
.max_freq
|
7191 dev_priv
->rps
.efficient_freq
|
7192 dev_priv
->rps
.rp1_freq
|
7193 dev_priv
->rps
.min_freq
) & 1,
7194 "Odd GPU freq values\n");
7197 static void valleyview_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
)
7199 valleyview_cleanup_pctx(dev_priv
);
7202 static void cherryview_enable_rps(struct drm_i915_private
*dev_priv
)
7204 struct intel_engine_cs
*engine
;
7205 enum intel_engine_id id
;
7206 u32 gtfifodbg
, val
, rc6_mode
= 0, pcbr
;
7208 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7210 gtfifodbg
= I915_READ(GTFIFODBG
) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV
|
7211 GT_FIFO_FREE_ENTRIES_CHV
);
7213 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
7215 I915_WRITE(GTFIFODBG
, gtfifodbg
);
7218 cherryview_check_pctx(dev_priv
);
7220 /* 1a & 1b: Get forcewake during program sequence. Although the driver
7221 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
7222 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
7224 /* Disable RC states. */
7225 I915_WRITE(GEN6_RC_CONTROL
, 0);
7227 /* 2a: Program RC6 thresholds.*/
7228 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
7229 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
7230 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
7232 for_each_engine(engine
, dev_priv
, id
)
7233 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
7234 I915_WRITE(GEN6_RC_SLEEP
, 0);
7236 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
7237 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x186);
7239 /* allows RC6 residency counter to work */
7240 I915_WRITE(VLV_COUNTER_CONTROL
,
7241 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
7242 VLV_MEDIA_RC6_COUNT_EN
|
7243 VLV_RENDER_RC6_COUNT_EN
));
7245 /* For now we assume BIOS is allocating and populating the PCBR */
7246 pcbr
= I915_READ(VLV_PCBR
);
7249 if ((intel_enable_rc6() & INTEL_RC6_ENABLE
) &&
7250 (pcbr
>> VLV_PCBR_ADDR_SHIFT
))
7251 rc6_mode
= GEN7_RC_CTL_TO_MODE
;
7253 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
7255 /* 4 Program defaults and thresholds for RPS*/
7256 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
7257 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
7258 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
7259 I915_WRITE(GEN6_RP_UP_EI
, 66000);
7260 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
7262 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
7265 I915_WRITE(GEN6_RP_CONTROL
,
7266 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
7267 GEN6_RP_MEDIA_IS_GFX
|
7269 GEN6_RP_UP_BUSY_AVG
|
7270 GEN6_RP_DOWN_IDLE_AVG
);
7272 /* Setting Fixed Bias */
7273 val
= VLV_OVERRIDE_EN
|
7275 CHV_BIAS_CPU_50_SOC_50
;
7276 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
7278 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
7280 /* RPS code assumes GPLL is used */
7281 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
7283 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
7284 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
7286 reset_rps(dev_priv
, valleyview_set_rps
);
7288 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
7291 static void valleyview_enable_rc6(struct drm_i915_private
*dev_priv
)
7293 struct intel_engine_cs
*engine
;
7294 enum intel_engine_id id
;
7295 u32 gtfifodbg
, rc6_mode
= 0;
7297 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7299 valleyview_check_pctx(dev_priv
);
7301 gtfifodbg
= I915_READ(GTFIFODBG
);
7303 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
7305 I915_WRITE(GTFIFODBG
, gtfifodbg
);
7308 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
7310 /* Disable RC states. */
7311 I915_WRITE(GEN6_RC_CONTROL
, 0);
7313 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
7314 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
7315 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
7317 for_each_engine(engine
, dev_priv
, id
)
7318 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
7320 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
7322 /* Allows RC6 residency counter to work */
7323 I915_WRITE(VLV_COUNTER_CONTROL
,
7324 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
7325 VLV_MEDIA_RC0_COUNT_EN
|
7326 VLV_RENDER_RC0_COUNT_EN
|
7327 VLV_MEDIA_RC6_COUNT_EN
|
7328 VLV_RENDER_RC6_COUNT_EN
));
7330 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
7331 rc6_mode
= GEN7_RC_CTL_TO_MODE
| VLV_RC_CTL_CTX_RST_PARALLEL
;
7333 intel_print_rc6_info(dev_priv
, rc6_mode
);
7335 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
7337 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
7340 static void valleyview_enable_rps(struct drm_i915_private
*dev_priv
)
7344 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7346 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
7348 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
7349 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
7350 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
7351 I915_WRITE(GEN6_RP_UP_EI
, 66000);
7352 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
7354 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
7356 I915_WRITE(GEN6_RP_CONTROL
,
7357 GEN6_RP_MEDIA_TURBO
|
7358 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
7359 GEN6_RP_MEDIA_IS_GFX
|
7361 GEN6_RP_UP_BUSY_AVG
|
7362 GEN6_RP_DOWN_IDLE_CONT
);
7364 /* Setting Fixed Bias */
7365 val
= VLV_OVERRIDE_EN
|
7367 VLV_BIAS_CPU_125_SOC_875
;
7368 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
7370 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
7372 /* RPS code assumes GPLL is used */
7373 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
7375 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
7376 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
7378 reset_rps(dev_priv
, valleyview_set_rps
);
7380 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
7383 static unsigned long intel_pxfreq(u32 vidfreq
)
7386 int div
= (vidfreq
& 0x3f0000) >> 16;
7387 int post
= (vidfreq
& 0x3000) >> 12;
7388 int pre
= (vidfreq
& 0x7);
7393 freq
= ((div
* 133333) / ((1<<post
) * pre
));
7398 static const struct cparams
{
7404 { 1, 1333, 301, 28664 },
7405 { 1, 1066, 294, 24460 },
7406 { 1, 800, 294, 25192 },
7407 { 0, 1333, 276, 27605 },
7408 { 0, 1066, 276, 27605 },
7409 { 0, 800, 231, 23784 },
7412 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
7414 u64 total_count
, diff
, ret
;
7415 u32 count1
, count2
, count3
, m
= 0, c
= 0;
7416 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
7419 lockdep_assert_held(&mchdev_lock
);
7421 diff1
= now
- dev_priv
->ips
.last_time1
;
7423 /* Prevent division-by-zero if we are asking too fast.
7424 * Also, we don't get interesting results if we are polling
7425 * faster than once in 10ms, so just return the saved value
7429 return dev_priv
->ips
.chipset_power
;
7431 count1
= I915_READ(DMIEC
);
7432 count2
= I915_READ(DDREC
);
7433 count3
= I915_READ(CSIEC
);
7435 total_count
= count1
+ count2
+ count3
;
7437 /* FIXME: handle per-counter overflow */
7438 if (total_count
< dev_priv
->ips
.last_count1
) {
7439 diff
= ~0UL - dev_priv
->ips
.last_count1
;
7440 diff
+= total_count
;
7442 diff
= total_count
- dev_priv
->ips
.last_count1
;
7445 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
7446 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
7447 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
7454 diff
= div_u64(diff
, diff1
);
7455 ret
= ((m
* diff
) + c
);
7456 ret
= div_u64(ret
, 10);
7458 dev_priv
->ips
.last_count1
= total_count
;
7459 dev_priv
->ips
.last_time1
= now
;
7461 dev_priv
->ips
.chipset_power
= ret
;
7466 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
7470 if (INTEL_INFO(dev_priv
)->gen
!= 5)
7473 spin_lock_irq(&mchdev_lock
);
7475 val
= __i915_chipset_val(dev_priv
);
7477 spin_unlock_irq(&mchdev_lock
);
7482 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
7484 unsigned long m
, x
, b
;
7487 tsfs
= I915_READ(TSFS
);
7489 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
7490 x
= I915_READ8(TR1
);
7492 b
= tsfs
& TSFS_INTR_MASK
;
7494 return ((m
* x
) / 127) - b
;
7497 static int _pxvid_to_vd(u8 pxvid
)
7502 if (pxvid
>= 8 && pxvid
< 31)
7505 return (pxvid
+ 2) * 125;
7508 static u32
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
7510 const int vd
= _pxvid_to_vd(pxvid
);
7511 const int vm
= vd
- 1125;
7513 if (INTEL_INFO(dev_priv
)->is_mobile
)
7514 return vm
> 0 ? vm
: 0;
7519 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
7521 u64 now
, diff
, diffms
;
7524 lockdep_assert_held(&mchdev_lock
);
7526 now
= ktime_get_raw_ns();
7527 diffms
= now
- dev_priv
->ips
.last_time2
;
7528 do_div(diffms
, NSEC_PER_MSEC
);
7530 /* Don't divide by 0 */
7534 count
= I915_READ(GFXEC
);
7536 if (count
< dev_priv
->ips
.last_count2
) {
7537 diff
= ~0UL - dev_priv
->ips
.last_count2
;
7540 diff
= count
- dev_priv
->ips
.last_count2
;
7543 dev_priv
->ips
.last_count2
= count
;
7544 dev_priv
->ips
.last_time2
= now
;
7546 /* More magic constants... */
7548 diff
= div_u64(diff
, diffms
* 10);
7549 dev_priv
->ips
.gfx_power
= diff
;
7552 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
7554 if (INTEL_INFO(dev_priv
)->gen
!= 5)
7557 spin_lock_irq(&mchdev_lock
);
7559 __i915_update_gfx_val(dev_priv
);
7561 spin_unlock_irq(&mchdev_lock
);
7564 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
7566 unsigned long t
, corr
, state1
, corr2
, state2
;
7569 lockdep_assert_held(&mchdev_lock
);
7571 pxvid
= I915_READ(PXVFREQ(dev_priv
->rps
.cur_freq
));
7572 pxvid
= (pxvid
>> 24) & 0x7f;
7573 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
7577 t
= i915_mch_val(dev_priv
);
7579 /* Revel in the empirically derived constants */
7581 /* Correction factor in 1/100000 units */
7583 corr
= ((t
* 2349) + 135940);
7585 corr
= ((t
* 964) + 29317);
7587 corr
= ((t
* 301) + 1004);
7589 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
7591 corr2
= (corr
* dev_priv
->ips
.corr
);
7593 state2
= (corr2
* state1
) / 10000;
7594 state2
/= 100; /* convert to mW */
7596 __i915_update_gfx_val(dev_priv
);
7598 return dev_priv
->ips
.gfx_power
+ state2
;
7601 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
7605 if (INTEL_INFO(dev_priv
)->gen
!= 5)
7608 spin_lock_irq(&mchdev_lock
);
7610 val
= __i915_gfx_val(dev_priv
);
7612 spin_unlock_irq(&mchdev_lock
);
7618 * i915_read_mch_val - return value for IPS use
7620 * Calculate and return a value for the IPS driver to use when deciding whether
7621 * we have thermal and power headroom to increase CPU or GPU power budget.
7623 unsigned long i915_read_mch_val(void)
7625 struct drm_i915_private
*dev_priv
;
7626 unsigned long chipset_val
, graphics_val
, ret
= 0;
7628 spin_lock_irq(&mchdev_lock
);
7631 dev_priv
= i915_mch_dev
;
7633 chipset_val
= __i915_chipset_val(dev_priv
);
7634 graphics_val
= __i915_gfx_val(dev_priv
);
7636 ret
= chipset_val
+ graphics_val
;
7639 spin_unlock_irq(&mchdev_lock
);
7643 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
7646 * i915_gpu_raise - raise GPU frequency limit
7648 * Raise the limit; IPS indicates we have thermal headroom.
7650 bool i915_gpu_raise(void)
7652 struct drm_i915_private
*dev_priv
;
7655 spin_lock_irq(&mchdev_lock
);
7656 if (!i915_mch_dev
) {
7660 dev_priv
= i915_mch_dev
;
7662 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
7663 dev_priv
->ips
.max_delay
--;
7666 spin_unlock_irq(&mchdev_lock
);
7670 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
7673 * i915_gpu_lower - lower GPU frequency limit
7675 * IPS indicates we're close to a thermal limit, so throttle back the GPU
7676 * frequency maximum.
7678 bool i915_gpu_lower(void)
7680 struct drm_i915_private
*dev_priv
;
7683 spin_lock_irq(&mchdev_lock
);
7684 if (!i915_mch_dev
) {
7688 dev_priv
= i915_mch_dev
;
7690 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
7691 dev_priv
->ips
.max_delay
++;
7694 spin_unlock_irq(&mchdev_lock
);
7698 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
7701 * i915_gpu_busy - indicate GPU business to IPS
7703 * Tell the IPS driver whether or not the GPU is busy.
7705 bool i915_gpu_busy(void)
7709 spin_lock_irq(&mchdev_lock
);
7711 ret
= i915_mch_dev
->gt
.awake
;
7712 spin_unlock_irq(&mchdev_lock
);
7716 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
7719 * i915_gpu_turbo_disable - disable graphics turbo
7721 * Disable graphics turbo by resetting the max frequency and setting the
7722 * current frequency to the default.
7724 bool i915_gpu_turbo_disable(void)
7726 struct drm_i915_private
*dev_priv
;
7729 spin_lock_irq(&mchdev_lock
);
7730 if (!i915_mch_dev
) {
7734 dev_priv
= i915_mch_dev
;
7736 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
7738 if (!ironlake_set_drps(dev_priv
, dev_priv
->ips
.fstart
))
7742 spin_unlock_irq(&mchdev_lock
);
7746 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
7749 * Tells the intel_ips driver that the i915 driver is now loaded, if
7750 * IPS got loaded first.
7752 * This awkward dance is so that neither module has to depend on the
7753 * other in order for IPS to do the appropriate communication of
7754 * GPU turbo limits to i915.
7757 ips_ping_for_i915_load(void)
7761 link
= symbol_get(ips_link_to_i915_driver
);
7764 symbol_put(ips_link_to_i915_driver
);
7768 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
7770 /* We only register the i915 ips part with intel-ips once everything is
7771 * set up, to avoid intel-ips sneaking in and reading bogus values. */
7772 spin_lock_irq(&mchdev_lock
);
7773 i915_mch_dev
= dev_priv
;
7774 spin_unlock_irq(&mchdev_lock
);
7776 ips_ping_for_i915_load();
7779 void intel_gpu_ips_teardown(void)
7781 spin_lock_irq(&mchdev_lock
);
7782 i915_mch_dev
= NULL
;
7783 spin_unlock_irq(&mchdev_lock
);
7786 static void intel_init_emon(struct drm_i915_private
*dev_priv
)
7792 /* Disable to program */
7796 /* Program energy weights for various events */
7797 I915_WRITE(SDEW
, 0x15040d00);
7798 I915_WRITE(CSIEW0
, 0x007f0000);
7799 I915_WRITE(CSIEW1
, 0x1e220004);
7800 I915_WRITE(CSIEW2
, 0x04000004);
7802 for (i
= 0; i
< 5; i
++)
7803 I915_WRITE(PEW(i
), 0);
7804 for (i
= 0; i
< 3; i
++)
7805 I915_WRITE(DEW(i
), 0);
7807 /* Program P-state weights to account for frequency power adjustment */
7808 for (i
= 0; i
< 16; i
++) {
7809 u32 pxvidfreq
= I915_READ(PXVFREQ(i
));
7810 unsigned long freq
= intel_pxfreq(pxvidfreq
);
7811 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
7816 val
*= (freq
/ 1000);
7818 val
/= (127*127*900);
7820 DRM_ERROR("bad pxval: %ld\n", val
);
7823 /* Render standby states get 0 weight */
7827 for (i
= 0; i
< 4; i
++) {
7828 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
7829 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
7830 I915_WRITE(PXW(i
), val
);
7833 /* Adjust magic regs to magic values (more experimental results) */
7834 I915_WRITE(OGW0
, 0);
7835 I915_WRITE(OGW1
, 0);
7836 I915_WRITE(EG0
, 0x00007f00);
7837 I915_WRITE(EG1
, 0x0000000e);
7838 I915_WRITE(EG2
, 0x000e0000);
7839 I915_WRITE(EG3
, 0x68000300);
7840 I915_WRITE(EG4
, 0x42000000);
7841 I915_WRITE(EG5
, 0x00140031);
7845 for (i
= 0; i
< 8; i
++)
7846 I915_WRITE(PXWL(i
), 0);
7848 /* Enable PMON + select events */
7849 I915_WRITE(ECR
, 0x80000019);
7851 lcfuse
= I915_READ(LCFUSE02
);
7853 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
7856 void intel_init_gt_powersave(struct drm_i915_private
*dev_priv
)
7859 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7862 if (!i915_modparams
.enable_rc6
) {
7863 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7864 intel_runtime_pm_get(dev_priv
);
7867 mutex_lock(&dev_priv
->drm
.struct_mutex
);
7868 mutex_lock(&dev_priv
->rps
.hw_lock
);
7870 /* Initialize RPS limits (for userspace) */
7871 if (IS_CHERRYVIEW(dev_priv
))
7872 cherryview_init_gt_powersave(dev_priv
);
7873 else if (IS_VALLEYVIEW(dev_priv
))
7874 valleyview_init_gt_powersave(dev_priv
);
7875 else if (INTEL_GEN(dev_priv
) >= 6)
7876 gen6_init_rps_frequencies(dev_priv
);
7878 /* Derive initial user preferences/limits from the hardware limits */
7879 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
7880 dev_priv
->rps
.cur_freq
= dev_priv
->rps
.idle_freq
;
7882 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
7883 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
7885 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
7886 dev_priv
->rps
.min_freq_softlimit
=
7888 dev_priv
->rps
.efficient_freq
,
7889 intel_freq_opcode(dev_priv
, 450));
7891 /* After setting max-softlimit, find the overclock max freq */
7892 if (IS_GEN6(dev_priv
) ||
7893 IS_IVYBRIDGE(dev_priv
) || IS_HASWELL(dev_priv
)) {
7896 sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, ¶ms
);
7897 if (params
& BIT(31)) { /* OC supported */
7898 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
7899 (dev_priv
->rps
.max_freq
& 0xff) * 50,
7900 (params
& 0xff) * 50);
7901 dev_priv
->rps
.max_freq
= params
& 0xff;
7905 /* Finally allow us to boost to max by default */
7906 dev_priv
->rps
.boost_freq
= dev_priv
->rps
.max_freq
;
7908 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7909 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
7911 intel_autoenable_gt_powersave(dev_priv
);
7914 void intel_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
)
7916 if (IS_VALLEYVIEW(dev_priv
))
7917 valleyview_cleanup_gt_powersave(dev_priv
);
7919 if (!i915_modparams
.enable_rc6
)
7920 intel_runtime_pm_put(dev_priv
);
7924 * intel_suspend_gt_powersave - suspend PM work and helper threads
7925 * @dev_priv: i915 device
7927 * We don't want to disable RC6 or other features here, we just want
7928 * to make sure any work we've queued has finished and won't bother
7929 * us while we're suspended.
7931 void intel_suspend_gt_powersave(struct drm_i915_private
*dev_priv
)
7933 if (INTEL_GEN(dev_priv
) < 6)
7936 if (cancel_delayed_work_sync(&dev_priv
->rps
.autoenable_work
))
7937 intel_runtime_pm_put(dev_priv
);
7939 /* gen6_rps_idle() will be called later to disable interrupts */
7942 void intel_sanitize_gt_powersave(struct drm_i915_private
*dev_priv
)
7944 dev_priv
->rps
.enabled
= true; /* force disabling */
7945 intel_disable_gt_powersave(dev_priv
);
7947 gen6_reset_rps_interrupts(dev_priv
);
7950 void intel_disable_gt_powersave(struct drm_i915_private
*dev_priv
)
7952 if (!READ_ONCE(dev_priv
->rps
.enabled
))
7955 mutex_lock(&dev_priv
->rps
.hw_lock
);
7957 if (INTEL_GEN(dev_priv
) >= 9) {
7958 gen9_disable_rc6(dev_priv
);
7959 gen9_disable_rps(dev_priv
);
7960 } else if (IS_CHERRYVIEW(dev_priv
)) {
7961 cherryview_disable_rps(dev_priv
);
7962 } else if (IS_VALLEYVIEW(dev_priv
)) {
7963 valleyview_disable_rc6(dev_priv
);
7964 valleyview_disable_rps(dev_priv
);
7965 } else if (INTEL_GEN(dev_priv
) >= 6) {
7966 gen6_disable_rc6(dev_priv
);
7967 gen6_disable_rps(dev_priv
);
7968 } else if (IS_IRONLAKE_M(dev_priv
)) {
7969 ironlake_disable_drps(dev_priv
);
7972 dev_priv
->rps
.enabled
= false;
7973 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7976 void intel_enable_gt_powersave(struct drm_i915_private
*dev_priv
)
7978 /* We shouldn't be disabling as we submit, so this should be less
7979 * racy than it appears!
7981 if (READ_ONCE(dev_priv
->rps
.enabled
))
7984 /* Powersaving is controlled by the host when inside a VM */
7985 if (intel_vgpu_active(dev_priv
))
7988 mutex_lock(&dev_priv
->rps
.hw_lock
);
7990 if (IS_CHERRYVIEW(dev_priv
)) {
7991 cherryview_enable_rps(dev_priv
);
7992 } else if (IS_VALLEYVIEW(dev_priv
)) {
7993 valleyview_enable_rc6(dev_priv
);
7994 valleyview_enable_rps(dev_priv
);
7995 } else if (INTEL_GEN(dev_priv
) >= 9) {
7996 gen9_enable_rc6(dev_priv
);
7997 gen9_enable_rps(dev_priv
);
7998 if (IS_GEN9_BC(dev_priv
) || IS_CANNONLAKE(dev_priv
))
7999 gen6_update_ring_freq(dev_priv
);
8000 } else if (IS_BROADWELL(dev_priv
)) {
8001 gen8_enable_rc6(dev_priv
);
8002 gen8_enable_rps(dev_priv
);
8003 gen6_update_ring_freq(dev_priv
);
8004 } else if (INTEL_GEN(dev_priv
) >= 6) {
8005 gen6_enable_rc6(dev_priv
);
8006 gen6_enable_rps(dev_priv
);
8007 gen6_update_ring_freq(dev_priv
);
8008 } else if (IS_IRONLAKE_M(dev_priv
)) {
8009 ironlake_enable_drps(dev_priv
);
8010 intel_init_emon(dev_priv
);
8013 WARN_ON(dev_priv
->rps
.max_freq
< dev_priv
->rps
.min_freq
);
8014 WARN_ON(dev_priv
->rps
.idle_freq
> dev_priv
->rps
.max_freq
);
8016 WARN_ON(dev_priv
->rps
.efficient_freq
< dev_priv
->rps
.min_freq
);
8017 WARN_ON(dev_priv
->rps
.efficient_freq
> dev_priv
->rps
.max_freq
);
8019 dev_priv
->rps
.enabled
= true;
8020 mutex_unlock(&dev_priv
->rps
.hw_lock
);
8023 static void __intel_autoenable_gt_powersave(struct work_struct
*work
)
8025 struct drm_i915_private
*dev_priv
=
8026 container_of(work
, typeof(*dev_priv
), rps
.autoenable_work
.work
);
8027 struct intel_engine_cs
*rcs
;
8028 struct drm_i915_gem_request
*req
;
8030 if (READ_ONCE(dev_priv
->rps
.enabled
))
8033 rcs
= dev_priv
->engine
[RCS
];
8034 if (rcs
->last_retired_context
)
8037 if (!rcs
->init_context
)
8040 mutex_lock(&dev_priv
->drm
.struct_mutex
);
8042 req
= i915_gem_request_alloc(rcs
, dev_priv
->kernel_context
);
8046 if (!i915_modparams
.enable_execlists
&& i915_switch_context(req
) == 0)
8047 rcs
->init_context(req
);
8049 /* Mark the device busy, calling intel_enable_gt_powersave() */
8050 i915_add_request(req
);
8053 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
8055 intel_runtime_pm_put(dev_priv
);
8058 void intel_autoenable_gt_powersave(struct drm_i915_private
*dev_priv
)
8060 if (READ_ONCE(dev_priv
->rps
.enabled
))
8063 if (IS_IRONLAKE_M(dev_priv
)) {
8064 ironlake_enable_drps(dev_priv
);
8065 intel_init_emon(dev_priv
);
8066 } else if (INTEL_INFO(dev_priv
)->gen
>= 6) {
8068 * PCU communication is slow and this doesn't need to be
8069 * done at any specific time, so do this out of our fast path
8070 * to make resume and init faster.
8072 * We depend on the HW RC6 power context save/restore
8073 * mechanism when entering D3 through runtime PM suspend. So
8074 * disable RPM until RPS/RC6 is properly setup. We can only
8075 * get here via the driver load/system resume/runtime resume
8076 * paths, so the _noresume version is enough (and in case of
8077 * runtime resume it's necessary).
8079 if (queue_delayed_work(dev_priv
->wq
,
8080 &dev_priv
->rps
.autoenable_work
,
8081 round_jiffies_up_relative(HZ
)))
8082 intel_runtime_pm_get_noresume(dev_priv
);
8086 static void ibx_init_clock_gating(struct drm_i915_private
*dev_priv
)
8089 * On Ibex Peak and Cougar Point, we need to disable clock
8090 * gating for the panel power sequencer or it will fail to
8091 * start up when no ports are active.
8093 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
8096 static void g4x_disable_trickle_feed(struct drm_i915_private
*dev_priv
)
8100 for_each_pipe(dev_priv
, pipe
) {
8101 I915_WRITE(DSPCNTR(pipe
),
8102 I915_READ(DSPCNTR(pipe
)) |
8103 DISPPLANE_TRICKLE_FEED_DISABLE
);
8105 I915_WRITE(DSPSURF(pipe
), I915_READ(DSPSURF(pipe
)));
8106 POSTING_READ(DSPSURF(pipe
));
8110 static void ilk_init_lp_watermarks(struct drm_i915_private
*dev_priv
)
8112 I915_WRITE(WM3_LP_ILK
, I915_READ(WM3_LP_ILK
) & ~WM1_LP_SR_EN
);
8113 I915_WRITE(WM2_LP_ILK
, I915_READ(WM2_LP_ILK
) & ~WM1_LP_SR_EN
);
8114 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
8117 * Don't touch WM1S_LP_EN here.
8118 * Doing so could cause underruns.
8122 static void ilk_init_clock_gating(struct drm_i915_private
*dev_priv
)
8124 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
8128 * WaFbcDisableDpfcClockGating:ilk
8130 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
8131 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
8132 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
8134 I915_WRITE(PCH_3DCGDIS0
,
8135 MARIUNIT_CLOCK_GATE_DISABLE
|
8136 SVSMUNIT_CLOCK_GATE_DISABLE
);
8137 I915_WRITE(PCH_3DCGDIS1
,
8138 VFMUNIT_CLOCK_GATE_DISABLE
);
8141 * According to the spec the following bits should be set in
8142 * order to enable memory self-refresh
8143 * The bit 22/21 of 0x42004
8144 * The bit 5 of 0x42020
8145 * The bit 15 of 0x45000
8147 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8148 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
8149 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
8150 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
8151 I915_WRITE(DISP_ARB_CTL
,
8152 (I915_READ(DISP_ARB_CTL
) |
8155 ilk_init_lp_watermarks(dev_priv
);
8158 * Based on the document from hardware guys the following bits
8159 * should be set unconditionally in order to enable FBC.
8160 * The bit 22 of 0x42000
8161 * The bit 22 of 0x42004
8162 * The bit 7,8,9 of 0x42020.
8164 if (IS_IRONLAKE_M(dev_priv
)) {
8165 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
8166 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
8167 I915_READ(ILK_DISPLAY_CHICKEN1
) |
8169 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8170 I915_READ(ILK_DISPLAY_CHICKEN2
) |
8174 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
8176 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8177 I915_READ(ILK_DISPLAY_CHICKEN2
) |
8178 ILK_ELPIN_409_SELECT
);
8179 I915_WRITE(_3D_CHICKEN2
,
8180 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
8181 _3D_CHICKEN2_WM_READ_PIPELINED
);
8183 /* WaDisableRenderCachePipelinedFlush:ilk */
8184 I915_WRITE(CACHE_MODE_0
,
8185 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
8187 /* WaDisable_RenderCache_OperationalFlush:ilk */
8188 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8190 g4x_disable_trickle_feed(dev_priv
);
8192 ibx_init_clock_gating(dev_priv
);
8195 static void cpt_init_clock_gating(struct drm_i915_private
*dev_priv
)
8201 * On Ibex Peak and Cougar Point, we need to disable clock
8202 * gating for the panel power sequencer or it will fail to
8203 * start up when no ports are active.
8205 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
8206 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
8207 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
8208 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
8209 DPLS_EDP_PPS_FIX_DIS
);
8210 /* The below fixes the weird display corruption, a few pixels shifted
8211 * downward, on (only) LVDS of some HP laptops with IVY.
8213 for_each_pipe(dev_priv
, pipe
) {
8214 val
= I915_READ(TRANS_CHICKEN2(pipe
));
8215 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
8216 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
8217 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
8218 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
8219 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
8220 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
8221 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
8222 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
8224 /* WADP0ClockGatingDisable */
8225 for_each_pipe(dev_priv
, pipe
) {
8226 I915_WRITE(TRANS_CHICKEN1(pipe
),
8227 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
8231 static void gen6_check_mch_setup(struct drm_i915_private
*dev_priv
)
8235 tmp
= I915_READ(MCH_SSKPD
);
8236 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
)
8237 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
8241 static void gen6_init_clock_gating(struct drm_i915_private
*dev_priv
)
8243 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
8245 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
8247 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8248 I915_READ(ILK_DISPLAY_CHICKEN2
) |
8249 ILK_ELPIN_409_SELECT
);
8251 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
8252 I915_WRITE(_3D_CHICKEN
,
8253 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
8255 /* WaDisable_RenderCache_OperationalFlush:snb */
8256 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8259 * BSpec recoomends 8x4 when MSAA is used,
8260 * however in practice 16x4 seems fastest.
8262 * Note that PS/WM thread counts depend on the WIZ hashing
8263 * disable bit, which we don't touch here, but it's good
8264 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8266 I915_WRITE(GEN6_GT_MODE
,
8267 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
8269 ilk_init_lp_watermarks(dev_priv
);
8271 I915_WRITE(CACHE_MODE_0
,
8272 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
8274 I915_WRITE(GEN6_UCGCTL1
,
8275 I915_READ(GEN6_UCGCTL1
) |
8276 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
8277 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
8279 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8280 * gating disable must be set. Failure to set it results in
8281 * flickering pixels due to Z write ordering failures after
8282 * some amount of runtime in the Mesa "fire" demo, and Unigine
8283 * Sanctuary and Tropics, and apparently anything else with
8284 * alpha test or pixel discard.
8286 * According to the spec, bit 11 (RCCUNIT) must also be set,
8287 * but we didn't debug actual testcases to find it out.
8289 * WaDisableRCCUnitClockGating:snb
8290 * WaDisableRCPBUnitClockGating:snb
8292 I915_WRITE(GEN6_UCGCTL2
,
8293 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
8294 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
8296 /* WaStripsFansDisableFastClipPerformanceFix:snb */
8297 I915_WRITE(_3D_CHICKEN3
,
8298 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
));
8302 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
8303 * 3DSTATE_SF number of SF output attributes is more than 16."
8305 I915_WRITE(_3D_CHICKEN3
,
8306 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH
));
8309 * According to the spec the following bits should be
8310 * set in order to enable memory self-refresh and fbc:
8311 * The bit21 and bit22 of 0x42000
8312 * The bit21 and bit22 of 0x42004
8313 * The bit5 and bit7 of 0x42020
8314 * The bit14 of 0x70180
8315 * The bit14 of 0x71180
8317 * WaFbcAsynchFlipDisableFbcQueue:snb
8319 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
8320 I915_READ(ILK_DISPLAY_CHICKEN1
) |
8321 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
8322 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8323 I915_READ(ILK_DISPLAY_CHICKEN2
) |
8324 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
8325 I915_WRITE(ILK_DSPCLK_GATE_D
,
8326 I915_READ(ILK_DSPCLK_GATE_D
) |
8327 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
8328 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
8330 g4x_disable_trickle_feed(dev_priv
);
8332 cpt_init_clock_gating(dev_priv
);
8334 gen6_check_mch_setup(dev_priv
);
8337 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
8339 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
8342 * WaVSThreadDispatchOverride:ivb,vlv
8344 * This actually overrides the dispatch
8345 * mode for all thread types.
8347 reg
&= ~GEN7_FF_SCHED_MASK
;
8348 reg
|= GEN7_FF_TS_SCHED_HW
;
8349 reg
|= GEN7_FF_VS_SCHED_HW
;
8350 reg
|= GEN7_FF_DS_SCHED_HW
;
8352 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
8355 static void lpt_init_clock_gating(struct drm_i915_private
*dev_priv
)
8358 * TODO: this bit should only be enabled when really needed, then
8359 * disabled when not needed anymore in order to save power.
8361 if (HAS_PCH_LPT_LP(dev_priv
))
8362 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
8363 I915_READ(SOUTH_DSPCLK_GATE_D
) |
8364 PCH_LP_PARTITION_LEVEL_DISABLE
);
8366 /* WADPOClockGatingDisable:hsw */
8367 I915_WRITE(TRANS_CHICKEN1(PIPE_A
),
8368 I915_READ(TRANS_CHICKEN1(PIPE_A
)) |
8369 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
8372 static void lpt_suspend_hw(struct drm_i915_private
*dev_priv
)
8374 if (HAS_PCH_LPT_LP(dev_priv
)) {
8375 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
8377 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
8378 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
8382 static void gen8_set_l3sqc_credits(struct drm_i915_private
*dev_priv
,
8383 int general_prio_credits
,
8384 int high_prio_credits
)
8388 /* WaTempDisableDOPClkGating:bdw */
8389 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
8390 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
8392 I915_WRITE(GEN8_L3SQCREG1
,
8393 L3_GENERAL_PRIO_CREDITS(general_prio_credits
) |
8394 L3_HIGH_PRIO_CREDITS(high_prio_credits
));
8397 * Wait at least 100 clocks before re-enabling clock gating.
8398 * See the definition of L3SQCREG1 in BSpec.
8400 POSTING_READ(GEN8_L3SQCREG1
);
8402 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
8405 static void cnp_init_clock_gating(struct drm_i915_private
*dev_priv
)
8407 if (!HAS_PCH_CNP(dev_priv
))
8411 I915_WRITE(SOUTH_DSPCLK_GATE_D
, I915_READ(SOUTH_DSPCLK_GATE_D
) |
8412 CNP_PWM_CGE_GATING_DISABLE
);
8415 static void cnl_init_clock_gating(struct drm_i915_private
*dev_priv
)
8418 cnp_init_clock_gating(dev_priv
);
8420 /* This is not an Wa. Enable for better image quality */
8421 I915_WRITE(_3D_CHICKEN3
,
8422 _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE
));
8424 /* WaEnableChickenDCPR:cnl */
8425 I915_WRITE(GEN8_CHICKEN_DCPR_1
,
8426 I915_READ(GEN8_CHICKEN_DCPR_1
) | MASK_WAKEMEM
);
8428 /* WaFbcWakeMemOn:cnl */
8429 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
8430 DISP_FBC_MEMORY_WAKE
);
8432 /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
8433 if (IS_CNL_REVID(dev_priv
, CNL_REVID_A0
, CNL_REVID_B0
))
8434 I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE
,
8435 I915_READ(SLICE_UNIT_LEVEL_CLKGATE
) |
8436 SARBUNIT_CLKGATE_DIS
);
8438 /* Display WA #1133: WaFbcSkipSegments:cnl */
8439 val
= I915_READ(ILK_DPFC_CHICKEN
);
8440 val
&= ~GLK_SKIP_SEG_COUNT_MASK
;
8441 val
|= GLK_SKIP_SEG_EN
| GLK_SKIP_SEG_COUNT(1);
8442 I915_WRITE(ILK_DPFC_CHICKEN
, val
);
8445 static void cfl_init_clock_gating(struct drm_i915_private
*dev_priv
)
8447 cnp_init_clock_gating(dev_priv
);
8448 gen9_init_clock_gating(dev_priv
);
8450 /* WaFbcNukeOnHostModify:cfl */
8451 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
8452 ILK_DPFC_NUKE_ON_ANY_MODIFICATION
);
8455 static void kbl_init_clock_gating(struct drm_i915_private
*dev_priv
)
8457 gen9_init_clock_gating(dev_priv
);
8459 /* WaDisableSDEUnitClockGating:kbl */
8460 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
8461 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
8462 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
8464 /* WaDisableGamClockGating:kbl */
8465 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
8466 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
8467 GEN6_GAMUNIT_CLOCK_GATE_DISABLE
);
8469 /* WaFbcNukeOnHostModify:kbl */
8470 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
8471 ILK_DPFC_NUKE_ON_ANY_MODIFICATION
);
8474 static void skl_init_clock_gating(struct drm_i915_private
*dev_priv
)
8476 gen9_init_clock_gating(dev_priv
);
8478 /* WAC6entrylatency:skl */
8479 I915_WRITE(FBC_LLC_READ_CTRL
, I915_READ(FBC_LLC_READ_CTRL
) |
8480 FBC_LLC_FULLY_OPEN
);
8482 /* WaFbcNukeOnHostModify:skl */
8483 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
8484 ILK_DPFC_NUKE_ON_ANY_MODIFICATION
);
8487 static void bdw_init_clock_gating(struct drm_i915_private
*dev_priv
)
8489 /* The GTT cache must be disabled if the system is using 2M pages. */
8490 bool can_use_gtt_cache
= !HAS_PAGE_SIZES(dev_priv
,
8491 I915_GTT_PAGE_SIZE_2M
);
8494 ilk_init_lp_watermarks(dev_priv
);
8496 /* WaSwitchSolVfFArbitrationPriority:bdw */
8497 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
8499 /* WaPsrDPAMaskVBlankInSRD:bdw */
8500 I915_WRITE(CHICKEN_PAR1_1
,
8501 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
8503 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
8504 for_each_pipe(dev_priv
, pipe
) {
8505 I915_WRITE(CHICKEN_PIPESL_1(pipe
),
8506 I915_READ(CHICKEN_PIPESL_1(pipe
)) |
8507 BDW_DPRS_MASK_VBLANK_SRD
);
8510 /* WaVSRefCountFullforceMissDisable:bdw */
8511 /* WaDSRefCountFullforceMissDisable:bdw */
8512 I915_WRITE(GEN7_FF_THREAD_MODE
,
8513 I915_READ(GEN7_FF_THREAD_MODE
) &
8514 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
8516 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
8517 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
8519 /* WaDisableSDEUnitClockGating:bdw */
8520 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
8521 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
8523 /* WaProgramL3SqcReg1Default:bdw */
8524 gen8_set_l3sqc_credits(dev_priv
, 30, 2);
8526 /* WaGttCachingOffByDefault:bdw */
8527 I915_WRITE(HSW_GTT_CACHE_EN
, can_use_gtt_cache
? GTT_CACHE_EN_ALL
: 0);
8529 /* WaKVMNotificationOnConfigChange:bdw */
8530 I915_WRITE(CHICKEN_PAR2_1
, I915_READ(CHICKEN_PAR2_1
)
8531 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT
);
8533 lpt_init_clock_gating(dev_priv
);
8535 /* WaDisableDopClockGating:bdw
8537 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
8540 I915_WRITE(GEN6_UCGCTL1
,
8541 I915_READ(GEN6_UCGCTL1
) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE
);
8544 static void hsw_init_clock_gating(struct drm_i915_private
*dev_priv
)
8546 ilk_init_lp_watermarks(dev_priv
);
8548 /* L3 caching of data atomics doesn't work -- disable it. */
8549 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
8550 I915_WRITE(HSW_ROW_CHICKEN3
,
8551 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
8553 /* This is required by WaCatErrorRejectionIssue:hsw */
8554 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
8555 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
8556 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
8558 /* WaVSRefCountFullforceMissDisable:hsw */
8559 I915_WRITE(GEN7_FF_THREAD_MODE
,
8560 I915_READ(GEN7_FF_THREAD_MODE
) & ~GEN7_FF_VS_REF_CNT_FFME
);
8562 /* WaDisable_RenderCache_OperationalFlush:hsw */
8563 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8565 /* enable HiZ Raw Stall Optimization */
8566 I915_WRITE(CACHE_MODE_0_GEN7
,
8567 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
8569 /* WaDisable4x2SubspanOptimization:hsw */
8570 I915_WRITE(CACHE_MODE_1
,
8571 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
8574 * BSpec recommends 8x4 when MSAA is used,
8575 * however in practice 16x4 seems fastest.
8577 * Note that PS/WM thread counts depend on the WIZ hashing
8578 * disable bit, which we don't touch here, but it's good
8579 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8581 I915_WRITE(GEN7_GT_MODE
,
8582 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
8584 /* WaSampleCChickenBitEnable:hsw */
8585 I915_WRITE(HALF_SLICE_CHICKEN3
,
8586 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE
));
8588 /* WaSwitchSolVfFArbitrationPriority:hsw */
8589 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
8591 /* WaRsPkgCStateDisplayPMReq:hsw */
8592 I915_WRITE(CHICKEN_PAR1_1
,
8593 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
8595 lpt_init_clock_gating(dev_priv
);
8598 static void ivb_init_clock_gating(struct drm_i915_private
*dev_priv
)
8602 ilk_init_lp_watermarks(dev_priv
);
8604 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
8606 /* WaDisableEarlyCull:ivb */
8607 I915_WRITE(_3D_CHICKEN3
,
8608 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
8610 /* WaDisableBackToBackFlipFix:ivb */
8611 I915_WRITE(IVB_CHICKEN3
,
8612 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
8613 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
8615 /* WaDisablePSDDualDispatchEnable:ivb */
8616 if (IS_IVB_GT1(dev_priv
))
8617 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
8618 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
8620 /* WaDisable_RenderCache_OperationalFlush:ivb */
8621 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8623 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
8624 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
8625 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
8627 /* WaApplyL3ControlAndL3ChickenMode:ivb */
8628 I915_WRITE(GEN7_L3CNTLREG1
,
8629 GEN7_WA_FOR_GEN7_L3_CONTROL
);
8630 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
8631 GEN7_WA_L3_CHICKEN_MODE
);
8632 if (IS_IVB_GT1(dev_priv
))
8633 I915_WRITE(GEN7_ROW_CHICKEN2
,
8634 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
8636 /* must write both registers */
8637 I915_WRITE(GEN7_ROW_CHICKEN2
,
8638 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
8639 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
8640 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
8643 /* WaForceL3Serialization:ivb */
8644 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
8645 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
8648 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8649 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
8651 I915_WRITE(GEN6_UCGCTL2
,
8652 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
8654 /* This is required by WaCatErrorRejectionIssue:ivb */
8655 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
8656 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
8657 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
8659 g4x_disable_trickle_feed(dev_priv
);
8661 gen7_setup_fixed_func_scheduler(dev_priv
);
8663 if (0) { /* causes HiZ corruption on ivb:gt1 */
8664 /* enable HiZ Raw Stall Optimization */
8665 I915_WRITE(CACHE_MODE_0_GEN7
,
8666 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
8669 /* WaDisable4x2SubspanOptimization:ivb */
8670 I915_WRITE(CACHE_MODE_1
,
8671 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
8674 * BSpec recommends 8x4 when MSAA is used,
8675 * however in practice 16x4 seems fastest.
8677 * Note that PS/WM thread counts depend on the WIZ hashing
8678 * disable bit, which we don't touch here, but it's good
8679 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8681 I915_WRITE(GEN7_GT_MODE
,
8682 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
8684 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
8685 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
8686 snpcr
|= GEN6_MBC_SNPCR_MED
;
8687 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
8689 if (!HAS_PCH_NOP(dev_priv
))
8690 cpt_init_clock_gating(dev_priv
);
8692 gen6_check_mch_setup(dev_priv
);
8695 static void vlv_init_clock_gating(struct drm_i915_private
*dev_priv
)
8697 /* WaDisableEarlyCull:vlv */
8698 I915_WRITE(_3D_CHICKEN3
,
8699 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
8701 /* WaDisableBackToBackFlipFix:vlv */
8702 I915_WRITE(IVB_CHICKEN3
,
8703 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
8704 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
8706 /* WaPsdDispatchEnable:vlv */
8707 /* WaDisablePSDDualDispatchEnable:vlv */
8708 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
8709 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
8710 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
8712 /* WaDisable_RenderCache_OperationalFlush:vlv */
8713 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8715 /* WaForceL3Serialization:vlv */
8716 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
8717 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
8719 /* WaDisableDopClockGating:vlv */
8720 I915_WRITE(GEN7_ROW_CHICKEN2
,
8721 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
8723 /* This is required by WaCatErrorRejectionIssue:vlv */
8724 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
8725 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
8726 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
8728 gen7_setup_fixed_func_scheduler(dev_priv
);
8731 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8732 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
8734 I915_WRITE(GEN6_UCGCTL2
,
8735 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
8737 /* WaDisableL3Bank2xClockGate:vlv
8738 * Disabling L3 clock gating- MMIO 940c[25] = 1
8739 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
8740 I915_WRITE(GEN7_UCGCTL4
,
8741 I915_READ(GEN7_UCGCTL4
) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
8744 * BSpec says this must be set, even though
8745 * WaDisable4x2SubspanOptimization isn't listed for VLV.
8747 I915_WRITE(CACHE_MODE_1
,
8748 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
8751 * BSpec recommends 8x4 when MSAA is used,
8752 * however in practice 16x4 seems fastest.
8754 * Note that PS/WM thread counts depend on the WIZ hashing
8755 * disable bit, which we don't touch here, but it's good
8756 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8758 I915_WRITE(GEN7_GT_MODE
,
8759 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
8762 * WaIncreaseL3CreditsForVLVB0:vlv
8763 * This is the hardware default actually.
8765 I915_WRITE(GEN7_L3SQCREG1
, VLV_B0_WA_L3SQCREG1_VALUE
);
8768 * WaDisableVLVClockGating_VBIIssue:vlv
8769 * Disable clock gating on th GCFG unit to prevent a delay
8770 * in the reporting of vblank events.
8772 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, GCFG_DIS
);
8775 static void chv_init_clock_gating(struct drm_i915_private
*dev_priv
)
8777 /* WaVSRefCountFullforceMissDisable:chv */
8778 /* WaDSRefCountFullforceMissDisable:chv */
8779 I915_WRITE(GEN7_FF_THREAD_MODE
,
8780 I915_READ(GEN7_FF_THREAD_MODE
) &
8781 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
8783 /* WaDisableSemaphoreAndSyncFlipWait:chv */
8784 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
8785 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
8787 /* WaDisableCSUnitClockGating:chv */
8788 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
8789 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
8791 /* WaDisableSDEUnitClockGating:chv */
8792 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
8793 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
8796 * WaProgramL3SqcReg1Default:chv
8797 * See gfxspecs/Related Documents/Performance Guide/
8798 * LSQC Setting Recommendations.
8800 gen8_set_l3sqc_credits(dev_priv
, 38, 2);
8803 * GTT cache may not work with big pages, so if those
8804 * are ever enabled GTT cache may need to be disabled.
8806 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
8809 static void g4x_init_clock_gating(struct drm_i915_private
*dev_priv
)
8811 uint32_t dspclk_gate
;
8813 I915_WRITE(RENCLK_GATE_D1
, 0);
8814 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
8815 GS_UNIT_CLOCK_GATE_DISABLE
|
8816 CL_UNIT_CLOCK_GATE_DISABLE
);
8817 I915_WRITE(RAMCLK_GATE_D
, 0);
8818 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
8819 OVRUNIT_CLOCK_GATE_DISABLE
|
8820 OVCUNIT_CLOCK_GATE_DISABLE
;
8821 if (IS_GM45(dev_priv
))
8822 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
8823 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
8825 /* WaDisableRenderCachePipelinedFlush */
8826 I915_WRITE(CACHE_MODE_0
,
8827 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
8829 /* WaDisable_RenderCache_OperationalFlush:g4x */
8830 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8832 g4x_disable_trickle_feed(dev_priv
);
8835 static void i965gm_init_clock_gating(struct drm_i915_private
*dev_priv
)
8837 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
8838 I915_WRITE(RENCLK_GATE_D2
, 0);
8839 I915_WRITE(DSPCLK_GATE_D
, 0);
8840 I915_WRITE(RAMCLK_GATE_D
, 0);
8841 I915_WRITE16(DEUC
, 0);
8842 I915_WRITE(MI_ARB_STATE
,
8843 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
8845 /* WaDisable_RenderCache_OperationalFlush:gen4 */
8846 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8849 static void i965g_init_clock_gating(struct drm_i915_private
*dev_priv
)
8851 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
8852 I965_RCC_CLOCK_GATE_DISABLE
|
8853 I965_RCPB_CLOCK_GATE_DISABLE
|
8854 I965_ISC_CLOCK_GATE_DISABLE
|
8855 I965_FBC_CLOCK_GATE_DISABLE
);
8856 I915_WRITE(RENCLK_GATE_D2
, 0);
8857 I915_WRITE(MI_ARB_STATE
,
8858 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
8860 /* WaDisable_RenderCache_OperationalFlush:gen4 */
8861 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
8864 static void gen3_init_clock_gating(struct drm_i915_private
*dev_priv
)
8866 u32 dstate
= I915_READ(D_STATE
);
8868 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
8869 DSTATE_DOT_CLOCK_GATING
;
8870 I915_WRITE(D_STATE
, dstate
);
8872 if (IS_PINEVIEW(dev_priv
))
8873 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
8875 /* IIR "flip pending" means done if this bit is set */
8876 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
8878 /* interrupts should cause a wake up from C3 */
8879 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN
));
8881 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
8882 I915_WRITE(MI_ARB_STATE
, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
8884 I915_WRITE(MI_ARB_STATE
,
8885 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
8888 static void i85x_init_clock_gating(struct drm_i915_private
*dev_priv
)
8890 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
8892 /* interrupts should cause a wake up from C3 */
8893 I915_WRITE(MI_STATE
, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN
) |
8894 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE
));
8896 I915_WRITE(MEM_MODE
,
8897 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE
));
8900 static void i830_init_clock_gating(struct drm_i915_private
*dev_priv
)
8902 I915_WRITE(MEM_MODE
,
8903 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE
) |
8904 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE
));
8907 void intel_init_clock_gating(struct drm_i915_private
*dev_priv
)
8909 dev_priv
->display
.init_clock_gating(dev_priv
);
8912 void intel_suspend_hw(struct drm_i915_private
*dev_priv
)
8914 if (HAS_PCH_LPT(dev_priv
))
8915 lpt_suspend_hw(dev_priv
);
8918 static void nop_init_clock_gating(struct drm_i915_private
*dev_priv
)
8920 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
8924 * intel_init_clock_gating_hooks - setup the clock gating hooks
8925 * @dev_priv: device private
8927 * Setup the hooks that configure which clocks of a given platform can be
8928 * gated and also apply various GT and display specific workarounds for these
8929 * platforms. Note that some GT specific workarounds are applied separately
8930 * when GPU contexts or batchbuffers start their execution.
8932 void intel_init_clock_gating_hooks(struct drm_i915_private
*dev_priv
)
8934 if (IS_CANNONLAKE(dev_priv
))
8935 dev_priv
->display
.init_clock_gating
= cnl_init_clock_gating
;
8936 else if (IS_COFFEELAKE(dev_priv
))
8937 dev_priv
->display
.init_clock_gating
= cfl_init_clock_gating
;
8938 else if (IS_SKYLAKE(dev_priv
))
8939 dev_priv
->display
.init_clock_gating
= skl_init_clock_gating
;
8940 else if (IS_KABYLAKE(dev_priv
))
8941 dev_priv
->display
.init_clock_gating
= kbl_init_clock_gating
;
8942 else if (IS_BROXTON(dev_priv
))
8943 dev_priv
->display
.init_clock_gating
= bxt_init_clock_gating
;
8944 else if (IS_GEMINILAKE(dev_priv
))
8945 dev_priv
->display
.init_clock_gating
= glk_init_clock_gating
;
8946 else if (IS_BROADWELL(dev_priv
))
8947 dev_priv
->display
.init_clock_gating
= bdw_init_clock_gating
;
8948 else if (IS_CHERRYVIEW(dev_priv
))
8949 dev_priv
->display
.init_clock_gating
= chv_init_clock_gating
;
8950 else if (IS_HASWELL(dev_priv
))
8951 dev_priv
->display
.init_clock_gating
= hsw_init_clock_gating
;
8952 else if (IS_IVYBRIDGE(dev_priv
))
8953 dev_priv
->display
.init_clock_gating
= ivb_init_clock_gating
;
8954 else if (IS_VALLEYVIEW(dev_priv
))
8955 dev_priv
->display
.init_clock_gating
= vlv_init_clock_gating
;
8956 else if (IS_GEN6(dev_priv
))
8957 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
8958 else if (IS_GEN5(dev_priv
))
8959 dev_priv
->display
.init_clock_gating
= ilk_init_clock_gating
;
8960 else if (IS_G4X(dev_priv
))
8961 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
8962 else if (IS_I965GM(dev_priv
))
8963 dev_priv
->display
.init_clock_gating
= i965gm_init_clock_gating
;
8964 else if (IS_I965G(dev_priv
))
8965 dev_priv
->display
.init_clock_gating
= i965g_init_clock_gating
;
8966 else if (IS_GEN3(dev_priv
))
8967 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
8968 else if (IS_I85X(dev_priv
) || IS_I865G(dev_priv
))
8969 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
8970 else if (IS_GEN2(dev_priv
))
8971 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
8973 MISSING_CASE(INTEL_DEVID(dev_priv
));
8974 dev_priv
->display
.init_clock_gating
= nop_init_clock_gating
;
8978 /* Set up chip specific power management-related functions */
8979 void intel_init_pm(struct drm_i915_private
*dev_priv
)
8981 intel_fbc_init(dev_priv
);
8984 if (IS_PINEVIEW(dev_priv
))
8985 i915_pineview_get_mem_freq(dev_priv
);
8986 else if (IS_GEN5(dev_priv
))
8987 i915_ironlake_get_mem_freq(dev_priv
);
8989 /* For FIFO watermark updates */
8990 if (INTEL_GEN(dev_priv
) >= 9) {
8991 skl_setup_wm_latency(dev_priv
);
8992 dev_priv
->display
.initial_watermarks
= skl_initial_wm
;
8993 dev_priv
->display
.atomic_update_watermarks
= skl_atomic_update_crtc_wm
;
8994 dev_priv
->display
.compute_global_watermarks
= skl_compute_wm
;
8995 } else if (HAS_PCH_SPLIT(dev_priv
)) {
8996 ilk_setup_wm_latency(dev_priv
);
8998 if ((IS_GEN5(dev_priv
) && dev_priv
->wm
.pri_latency
[1] &&
8999 dev_priv
->wm
.spr_latency
[1] && dev_priv
->wm
.cur_latency
[1]) ||
9000 (!IS_GEN5(dev_priv
) && dev_priv
->wm
.pri_latency
[0] &&
9001 dev_priv
->wm
.spr_latency
[0] && dev_priv
->wm
.cur_latency
[0])) {
9002 dev_priv
->display
.compute_pipe_wm
= ilk_compute_pipe_wm
;
9003 dev_priv
->display
.compute_intermediate_wm
=
9004 ilk_compute_intermediate_wm
;
9005 dev_priv
->display
.initial_watermarks
=
9006 ilk_initial_watermarks
;
9007 dev_priv
->display
.optimize_watermarks
=
9008 ilk_optimize_watermarks
;
9010 DRM_DEBUG_KMS("Failed to read display plane latency. "
9013 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
9014 vlv_setup_wm_latency(dev_priv
);
9015 dev_priv
->display
.compute_pipe_wm
= vlv_compute_pipe_wm
;
9016 dev_priv
->display
.compute_intermediate_wm
= vlv_compute_intermediate_wm
;
9017 dev_priv
->display
.initial_watermarks
= vlv_initial_watermarks
;
9018 dev_priv
->display
.optimize_watermarks
= vlv_optimize_watermarks
;
9019 dev_priv
->display
.atomic_update_watermarks
= vlv_atomic_update_fifo
;
9020 } else if (IS_G4X(dev_priv
)) {
9021 g4x_setup_wm_latency(dev_priv
);
9022 dev_priv
->display
.compute_pipe_wm
= g4x_compute_pipe_wm
;
9023 dev_priv
->display
.compute_intermediate_wm
= g4x_compute_intermediate_wm
;
9024 dev_priv
->display
.initial_watermarks
= g4x_initial_watermarks
;
9025 dev_priv
->display
.optimize_watermarks
= g4x_optimize_watermarks
;
9026 } else if (IS_PINEVIEW(dev_priv
)) {
9027 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv
),
9030 dev_priv
->mem_freq
)) {
9031 DRM_INFO("failed to find known CxSR latency "
9032 "(found ddr%s fsb freq %d, mem freq %d), "
9034 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
9035 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
9036 /* Disable CxSR and never update its watermark again */
9037 intel_set_memory_cxsr(dev_priv
, false);
9038 dev_priv
->display
.update_wm
= NULL
;
9040 dev_priv
->display
.update_wm
= pineview_update_wm
;
9041 } else if (IS_GEN4(dev_priv
)) {
9042 dev_priv
->display
.update_wm
= i965_update_wm
;
9043 } else if (IS_GEN3(dev_priv
)) {
9044 dev_priv
->display
.update_wm
= i9xx_update_wm
;
9045 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
9046 } else if (IS_GEN2(dev_priv
)) {
9047 if (INTEL_INFO(dev_priv
)->num_pipes
== 1) {
9048 dev_priv
->display
.update_wm
= i845_update_wm
;
9049 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
9051 dev_priv
->display
.update_wm
= i9xx_update_wm
;
9052 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
9055 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
9059 static inline int gen6_check_mailbox_status(struct drm_i915_private
*dev_priv
)
9062 I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_ERROR_MASK
;
9065 case GEN6_PCODE_SUCCESS
:
9067 case GEN6_PCODE_UNIMPLEMENTED_CMD
:
9069 case GEN6_PCODE_ILLEGAL_CMD
:
9071 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
:
9072 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
:
9074 case GEN6_PCODE_TIMEOUT
:
9077 MISSING_CASE(flags
);
9082 static inline int gen7_check_mailbox_status(struct drm_i915_private
*dev_priv
)
9085 I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_ERROR_MASK
;
9088 case GEN6_PCODE_SUCCESS
:
9090 case GEN6_PCODE_ILLEGAL_CMD
:
9092 case GEN7_PCODE_TIMEOUT
:
9094 case GEN7_PCODE_ILLEGAL_DATA
:
9096 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
:
9099 MISSING_CASE(flags
);
9104 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
)
9108 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
9110 /* GEN6_PCODE_* are outside of the forcewake domain, we can
9111 * use te fw I915_READ variants to reduce the amount of work
9112 * required when reading/writing.
9115 if (I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
9116 DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps\n",
9117 mbox
, __builtin_return_address(0));
9121 I915_WRITE_FW(GEN6_PCODE_DATA
, *val
);
9122 I915_WRITE_FW(GEN6_PCODE_DATA1
, 0);
9123 I915_WRITE_FW(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
9125 if (__intel_wait_for_register_fw(dev_priv
,
9126 GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
, 0,
9128 DRM_ERROR("timeout waiting for pcode read (from mbox %x) to finish for %ps\n",
9129 mbox
, __builtin_return_address(0));
9133 *val
= I915_READ_FW(GEN6_PCODE_DATA
);
9134 I915_WRITE_FW(GEN6_PCODE_DATA
, 0);
9136 if (INTEL_GEN(dev_priv
) > 6)
9137 status
= gen7_check_mailbox_status(dev_priv
);
9139 status
= gen6_check_mailbox_status(dev_priv
);
9142 DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
9143 mbox
, __builtin_return_address(0), status
);
9150 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
,
9155 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
9157 /* GEN6_PCODE_* are outside of the forcewake domain, we can
9158 * use te fw I915_READ variants to reduce the amount of work
9159 * required when reading/writing.
9162 if (I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
9163 DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps\n",
9164 val
, mbox
, __builtin_return_address(0));
9168 I915_WRITE_FW(GEN6_PCODE_DATA
, val
);
9169 I915_WRITE_FW(GEN6_PCODE_DATA1
, 0);
9170 I915_WRITE_FW(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
9172 if (__intel_wait_for_register_fw(dev_priv
,
9173 GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
, 0,
9175 DRM_ERROR("timeout waiting for pcode write of 0x%08x to mbox %x to finish for %ps\n",
9176 val
, mbox
, __builtin_return_address(0));
9180 I915_WRITE_FW(GEN6_PCODE_DATA
, 0);
9182 if (INTEL_GEN(dev_priv
) > 6)
9183 status
= gen7_check_mailbox_status(dev_priv
);
9185 status
= gen6_check_mailbox_status(dev_priv
);
9188 DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
9189 val
, mbox
, __builtin_return_address(0), status
);
9196 static bool skl_pcode_try_request(struct drm_i915_private
*dev_priv
, u32 mbox
,
9197 u32 request
, u32 reply_mask
, u32 reply
,
9202 *status
= sandybridge_pcode_read(dev_priv
, mbox
, &val
);
9204 return *status
|| ((val
& reply_mask
) == reply
);
9208 * skl_pcode_request - send PCODE request until acknowledgment
9209 * @dev_priv: device private
9210 * @mbox: PCODE mailbox ID the request is targeted for
9211 * @request: request ID
9212 * @reply_mask: mask used to check for request acknowledgment
9213 * @reply: value used to check for request acknowledgment
9214 * @timeout_base_ms: timeout for polling with preemption enabled
9216 * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
9217 * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
9218 * The request is acknowledged once the PCODE reply dword equals @reply after
9219 * applying @reply_mask. Polling is first attempted with preemption enabled
9220 * for @timeout_base_ms and if this times out for another 50 ms with
9221 * preemption disabled.
9223 * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
9224 * other error as reported by PCODE.
9226 int skl_pcode_request(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 request
,
9227 u32 reply_mask
, u32 reply
, int timeout_base_ms
)
9232 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
9234 #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
9238 * Prime the PCODE by doing a request first. Normally it guarantees
9239 * that a subsequent request, at most @timeout_base_ms later, succeeds.
9240 * _wait_for() doesn't guarantee when its passed condition is evaluated
9241 * first, so send the first request explicitly.
9247 ret
= _wait_for(COND
, timeout_base_ms
* 1000, 10);
9252 * The above can time out if the number of requests was low (2 in the
9253 * worst case) _and_ PCODE was busy for some reason even after a
9254 * (queued) request and @timeout_base_ms delay. As a workaround retry
9255 * the poll with preemption disabled to maximize the number of
9256 * requests. Increase the timeout from @timeout_base_ms to 50ms to
9257 * account for interrupts that could reduce the number of these
9258 * requests, and for any quirks of the PCODE firmware that delays
9259 * the request completion.
9261 DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
9262 WARN_ON_ONCE(timeout_base_ms
> 3);
9264 ret
= wait_for_atomic(COND
, 50);
9268 return ret
? ret
: status
;
9272 static int byt_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
9276 * Slow = Fast = GPLL ref * N
9278 return DIV_ROUND_CLOSEST(dev_priv
->rps
.gpll_ref_freq
* (val
- 0xb7), 1000);
9281 static int byt_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
9283 return DIV_ROUND_CLOSEST(1000 * val
, dev_priv
->rps
.gpll_ref_freq
) + 0xb7;
9286 static int chv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
9290 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
9292 return DIV_ROUND_CLOSEST(dev_priv
->rps
.gpll_ref_freq
* val
, 2 * 2 * 1000);
9295 static int chv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
9297 /* CHV needs even values */
9298 return DIV_ROUND_CLOSEST(2 * 1000 * val
, dev_priv
->rps
.gpll_ref_freq
) * 2;
9301 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
9303 if (INTEL_GEN(dev_priv
) >= 9)
9304 return DIV_ROUND_CLOSEST(val
* GT_FREQUENCY_MULTIPLIER
,
9306 else if (IS_CHERRYVIEW(dev_priv
))
9307 return chv_gpu_freq(dev_priv
, val
);
9308 else if (IS_VALLEYVIEW(dev_priv
))
9309 return byt_gpu_freq(dev_priv
, val
);
9311 return val
* GT_FREQUENCY_MULTIPLIER
;
9314 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
9316 if (INTEL_GEN(dev_priv
) >= 9)
9317 return DIV_ROUND_CLOSEST(val
* GEN9_FREQ_SCALER
,
9318 GT_FREQUENCY_MULTIPLIER
);
9319 else if (IS_CHERRYVIEW(dev_priv
))
9320 return chv_freq_opcode(dev_priv
, val
);
9321 else if (IS_VALLEYVIEW(dev_priv
))
9322 return byt_freq_opcode(dev_priv
, val
);
9324 return DIV_ROUND_CLOSEST(val
, GT_FREQUENCY_MULTIPLIER
);
9327 void intel_pm_setup(struct drm_i915_private
*dev_priv
)
9329 mutex_init(&dev_priv
->rps
.hw_lock
);
9331 INIT_DELAYED_WORK(&dev_priv
->rps
.autoenable_work
,
9332 __intel_autoenable_gt_powersave
);
9333 atomic_set(&dev_priv
->rps
.num_waiters
, 0);
9335 dev_priv
->pm
.suspended
= false;
9336 atomic_set(&dev_priv
->pm
.wakeref_count
, 0);
9339 static u64
vlv_residency_raw(struct drm_i915_private
*dev_priv
,
9340 const i915_reg_t reg
)
9342 u32 lower
, upper
, tmp
;
9345 /* The register accessed do not need forcewake. We borrow
9346 * uncore lock to prevent concurrent access to range reg.
9348 spin_lock_irq(&dev_priv
->uncore
.lock
);
9350 /* vlv and chv residency counters are 40 bits in width.
9351 * With a control bit, we can choose between upper or lower
9352 * 32bit window into this counter.
9354 * Although we always use the counter in high-range mode elsewhere,
9355 * userspace may attempt to read the value before rc6 is initialised,
9356 * before we have set the default VLV_COUNTER_CONTROL value. So always
9357 * set the high bit to be safe.
9359 I915_WRITE_FW(VLV_COUNTER_CONTROL
,
9360 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
));
9361 upper
= I915_READ_FW(reg
);
9365 I915_WRITE_FW(VLV_COUNTER_CONTROL
,
9366 _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH
));
9367 lower
= I915_READ_FW(reg
);
9369 I915_WRITE_FW(VLV_COUNTER_CONTROL
,
9370 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
));
9371 upper
= I915_READ_FW(reg
);
9372 } while (upper
!= tmp
&& --loop
);
9374 /* Everywhere else we always use VLV_COUNTER_CONTROL with the
9375 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
9379 spin_unlock_irq(&dev_priv
->uncore
.lock
);
9381 return lower
| (u64
)upper
<< 8;
9384 u64
intel_rc6_residency_us(struct drm_i915_private
*dev_priv
,
9385 const i915_reg_t reg
)
9387 u64 time_hw
, units
, div
;
9389 if (!intel_enable_rc6())
9392 intel_runtime_pm_get(dev_priv
);
9394 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
9395 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
9397 div
= dev_priv
->czclk_freq
;
9399 time_hw
= vlv_residency_raw(dev_priv
, reg
);
9400 } else if (IS_GEN9_LP(dev_priv
)) {
9402 div
= 1200; /* 833.33ns */
9404 time_hw
= I915_READ(reg
);
9406 units
= 128000; /* 1.28us */
9409 time_hw
= I915_READ(reg
);
9412 intel_runtime_pm_put(dev_priv
);
9413 return DIV_ROUND_UP_ULL(time_hw
* units
, div
);