2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
29 #include <drm/drm_plane_helper.h>
31 #include "intel_drv.h"
32 #include "../../../platform/x86/intel_ips.h"
33 #include <linux/module.h>
34 #include <drm/drm_atomic_helper.h>
39 * RC6 is a special power stage which allows the GPU to enter an very
40 * low-voltage mode when idle, using down to 0V while at this stage. This
41 * stage is entered automatically when the GPU is idle when RC6 support is
42 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
44 * There are different RC6 modes available in Intel GPU, which differentiate
45 * among each other with the latency required to enter and leave RC6 and
46 * voltage consumed by the GPU in different states.
48 * The combination of the following flags define which states GPU is allowed
49 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
50 * RC6pp is deepest RC6. Their support by hardware varies according to the
51 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
52 * which brings the most power savings; deeper states save more power, but
53 * require higher latency to switch to and wake up.
55 #define INTEL_RC6_ENABLE (1<<0)
56 #define INTEL_RC6p_ENABLE (1<<1)
57 #define INTEL_RC6pp_ENABLE (1<<2)
59 static void gen9_init_clock_gating(struct drm_i915_private
*dev_priv
)
61 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
62 I915_WRITE(CHICKEN_PAR1_1
,
63 I915_READ(CHICKEN_PAR1_1
) | SKL_EDP_PSR_FIX_RDWRAP
);
65 I915_WRITE(GEN8_CONFIG0
,
66 I915_READ(GEN8_CONFIG0
) | GEN9_DEFAULT_FIXES
);
68 /* WaEnableChickenDCPR:skl,bxt,kbl,glk */
69 I915_WRITE(GEN8_CHICKEN_DCPR_1
,
70 I915_READ(GEN8_CHICKEN_DCPR_1
) | MASK_WAKEMEM
);
72 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
73 /* WaFbcWakeMemOn:skl,bxt,kbl,glk */
74 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
76 DISP_FBC_MEMORY_WAKE
);
78 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
79 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
80 ILK_DPFC_DISABLE_DUMMY0
);
83 static void bxt_init_clock_gating(struct drm_i915_private
*dev_priv
)
85 gen9_init_clock_gating(dev_priv
);
87 /* WaDisableSDEUnitClockGating:bxt */
88 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
89 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
93 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
95 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
96 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ
);
99 * Wa: Backlight PWM may stop in the asserted state, causing backlight
102 I915_WRITE(GEN9_CLKGATE_DIS_0
, I915_READ(GEN9_CLKGATE_DIS_0
) |
103 PWM1_GATING_DIS
| PWM2_GATING_DIS
);
106 static void glk_init_clock_gating(struct drm_i915_private
*dev_priv
)
108 gen9_init_clock_gating(dev_priv
);
111 * WaDisablePWMClockGating:glk
112 * Backlight PWM may stop in the asserted state, causing backlight
115 I915_WRITE(GEN9_CLKGATE_DIS_0
, I915_READ(GEN9_CLKGATE_DIS_0
) |
116 PWM1_GATING_DIS
| PWM2_GATING_DIS
);
118 /* WaDDIIOTimeout:glk */
119 if (IS_GLK_REVID(dev_priv
, 0, GLK_REVID_A1
)) {
120 u32 val
= I915_READ(CHICKEN_MISC_2
);
121 val
&= ~(GLK_CL0_PWR_DOWN
|
124 I915_WRITE(CHICKEN_MISC_2
, val
);
129 static void i915_pineview_get_mem_freq(struct drm_i915_private
*dev_priv
)
133 tmp
= I915_READ(CLKCFG
);
135 switch (tmp
& CLKCFG_FSB_MASK
) {
137 dev_priv
->fsb_freq
= 533; /* 133*4 */
140 dev_priv
->fsb_freq
= 800; /* 200*4 */
143 dev_priv
->fsb_freq
= 667; /* 167*4 */
146 dev_priv
->fsb_freq
= 400; /* 100*4 */
150 switch (tmp
& CLKCFG_MEM_MASK
) {
152 dev_priv
->mem_freq
= 533;
155 dev_priv
->mem_freq
= 667;
158 dev_priv
->mem_freq
= 800;
162 /* detect pineview DDR3 setting */
163 tmp
= I915_READ(CSHRDDR3CTL
);
164 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
167 static void i915_ironlake_get_mem_freq(struct drm_i915_private
*dev_priv
)
171 ddrpll
= I915_READ16(DDRMPLL1
);
172 csipll
= I915_READ16(CSIPLL0
);
174 switch (ddrpll
& 0xff) {
176 dev_priv
->mem_freq
= 800;
179 dev_priv
->mem_freq
= 1066;
182 dev_priv
->mem_freq
= 1333;
185 dev_priv
->mem_freq
= 1600;
188 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
190 dev_priv
->mem_freq
= 0;
194 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
196 switch (csipll
& 0x3ff) {
198 dev_priv
->fsb_freq
= 3200;
201 dev_priv
->fsb_freq
= 3733;
204 dev_priv
->fsb_freq
= 4266;
207 dev_priv
->fsb_freq
= 4800;
210 dev_priv
->fsb_freq
= 5333;
213 dev_priv
->fsb_freq
= 5866;
216 dev_priv
->fsb_freq
= 6400;
219 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
221 dev_priv
->fsb_freq
= 0;
225 if (dev_priv
->fsb_freq
== 3200) {
226 dev_priv
->ips
.c_m
= 0;
227 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
228 dev_priv
->ips
.c_m
= 1;
230 dev_priv
->ips
.c_m
= 2;
234 static const struct cxsr_latency cxsr_latency_table
[] = {
235 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
236 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
237 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
238 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
239 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
241 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
242 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
243 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
244 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
245 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
247 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
248 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
249 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
250 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
251 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
253 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
254 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
255 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
256 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
257 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
259 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
260 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
261 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
262 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
263 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
265 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
266 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
267 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
268 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
269 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
272 static const struct cxsr_latency
*intel_get_cxsr_latency(bool is_desktop
,
277 const struct cxsr_latency
*latency
;
280 if (fsb
== 0 || mem
== 0)
283 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
284 latency
= &cxsr_latency_table
[i
];
285 if (is_desktop
== latency
->is_desktop
&&
286 is_ddr3
== latency
->is_ddr3
&&
287 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
291 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
296 static void chv_set_memory_dvfs(struct drm_i915_private
*dev_priv
, bool enable
)
300 mutex_lock(&dev_priv
->rps
.hw_lock
);
302 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
304 val
&= ~FORCE_DDR_HIGH_FREQ
;
306 val
|= FORCE_DDR_HIGH_FREQ
;
307 val
&= ~FORCE_DDR_LOW_FREQ
;
308 val
|= FORCE_DDR_FREQ_REQ_ACK
;
309 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
311 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
312 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3))
313 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
315 mutex_unlock(&dev_priv
->rps
.hw_lock
);
318 static void chv_set_memory_pm5(struct drm_i915_private
*dev_priv
, bool enable
)
322 mutex_lock(&dev_priv
->rps
.hw_lock
);
324 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
326 val
|= DSP_MAXFIFO_PM5_ENABLE
;
328 val
&= ~DSP_MAXFIFO_PM5_ENABLE
;
329 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
331 mutex_unlock(&dev_priv
->rps
.hw_lock
);
334 #define FW_WM(value, plane) \
335 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
337 static bool _intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
342 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
343 was_enabled
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
344 I915_WRITE(FW_BLC_SELF_VLV
, enable
? FW_CSPWRDWNEN
: 0);
345 POSTING_READ(FW_BLC_SELF_VLV
);
346 } else if (IS_G4X(dev_priv
) || IS_I965GM(dev_priv
)) {
347 was_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
348 I915_WRITE(FW_BLC_SELF
, enable
? FW_BLC_SELF_EN
: 0);
349 POSTING_READ(FW_BLC_SELF
);
350 } else if (IS_PINEVIEW(dev_priv
)) {
351 val
= I915_READ(DSPFW3
);
352 was_enabled
= val
& PINEVIEW_SELF_REFRESH_EN
;
354 val
|= PINEVIEW_SELF_REFRESH_EN
;
356 val
&= ~PINEVIEW_SELF_REFRESH_EN
;
357 I915_WRITE(DSPFW3
, val
);
358 POSTING_READ(DSPFW3
);
359 } else if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
)) {
360 was_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
361 val
= enable
? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN
) :
362 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN
);
363 I915_WRITE(FW_BLC_SELF
, val
);
364 POSTING_READ(FW_BLC_SELF
);
365 } else if (IS_I915GM(dev_priv
)) {
367 * FIXME can't find a bit like this for 915G, and
368 * and yet it does have the related watermark in
369 * FW_BLC_SELF. What's going on?
371 was_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
372 val
= enable
? _MASKED_BIT_ENABLE(INSTPM_SELF_EN
) :
373 _MASKED_BIT_DISABLE(INSTPM_SELF_EN
);
374 I915_WRITE(INSTPM
, val
);
375 POSTING_READ(INSTPM
);
380 DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
381 enableddisabled(enable
),
382 enableddisabled(was_enabled
));
387 bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
391 mutex_lock(&dev_priv
->wm
.wm_mutex
);
392 ret
= _intel_set_memory_cxsr(dev_priv
, enable
);
393 dev_priv
->wm
.vlv
.cxsr
= enable
;
394 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
400 * Latency for FIFO fetches is dependent on several factors:
401 * - memory configuration (speed, channels)
403 * - current MCH state
404 * It can be fairly high in some situations, so here we assume a fairly
405 * pessimal value. It's a tradeoff between extra memory fetches (if we
406 * set this value too high, the FIFO will fetch frequently to stay full)
407 * and power consumption (set it too low to save power and we might see
408 * FIFO underruns and display "flicker").
410 * A value of 5us seems to be a good balance; safe for very low end
411 * platforms but not overly aggressive on lower latency configs.
413 static const int pessimal_latency_ns
= 5000;
415 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
416 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
418 static void vlv_get_fifo_size(struct intel_crtc_state
*crtc_state
)
420 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
421 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
422 struct vlv_fifo_state
*fifo_state
= &crtc_state
->wm
.vlv
.fifo_state
;
423 enum pipe pipe
= crtc
->pipe
;
424 int sprite0_start
, sprite1_start
;
427 uint32_t dsparb
, dsparb2
, dsparb3
;
429 dsparb
= I915_READ(DSPARB
);
430 dsparb2
= I915_READ(DSPARB2
);
431 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 0, 0);
432 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 8, 4);
435 dsparb
= I915_READ(DSPARB
);
436 dsparb2
= I915_READ(DSPARB2
);
437 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 16, 8);
438 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 24, 12);
441 dsparb2
= I915_READ(DSPARB2
);
442 dsparb3
= I915_READ(DSPARB3
);
443 sprite0_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 0, 16);
444 sprite1_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 8, 20);
451 fifo_state
->plane
[PLANE_PRIMARY
] = sprite0_start
;
452 fifo_state
->plane
[PLANE_SPRITE0
] = sprite1_start
- sprite0_start
;
453 fifo_state
->plane
[PLANE_SPRITE1
] = 511 - sprite1_start
;
454 fifo_state
->plane
[PLANE_CURSOR
] = 63;
456 DRM_DEBUG_KMS("Pipe %c FIFO size: %d/%d/%d/%d\n",
458 fifo_state
->plane
[PLANE_PRIMARY
],
459 fifo_state
->plane
[PLANE_SPRITE0
],
460 fifo_state
->plane
[PLANE_SPRITE1
],
461 fifo_state
->plane
[PLANE_CURSOR
]);
464 static int i9xx_get_fifo_size(struct drm_i915_private
*dev_priv
, int plane
)
466 uint32_t dsparb
= I915_READ(DSPARB
);
469 size
= dsparb
& 0x7f;
471 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
473 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
474 plane
? "B" : "A", size
);
479 static int i830_get_fifo_size(struct drm_i915_private
*dev_priv
, int plane
)
481 uint32_t dsparb
= I915_READ(DSPARB
);
484 size
= dsparb
& 0x1ff;
486 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
487 size
>>= 1; /* Convert to cachelines */
489 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
490 plane
? "B" : "A", size
);
495 static int i845_get_fifo_size(struct drm_i915_private
*dev_priv
, int plane
)
497 uint32_t dsparb
= I915_READ(DSPARB
);
500 size
= dsparb
& 0x7f;
501 size
>>= 2; /* Convert to cachelines */
503 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
510 /* Pineview has different values for various configs */
511 static const struct intel_watermark_params pineview_display_wm
= {
512 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
513 .max_wm
= PINEVIEW_MAX_WM
,
514 .default_wm
= PINEVIEW_DFT_WM
,
515 .guard_size
= PINEVIEW_GUARD_WM
,
516 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
518 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
519 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
520 .max_wm
= PINEVIEW_MAX_WM
,
521 .default_wm
= PINEVIEW_DFT_HPLLOFF_WM
,
522 .guard_size
= PINEVIEW_GUARD_WM
,
523 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
525 static const struct intel_watermark_params pineview_cursor_wm
= {
526 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
527 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
528 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
529 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
530 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
532 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
533 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
534 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
535 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
536 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
537 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
539 static const struct intel_watermark_params g4x_wm_info
= {
540 .fifo_size
= G4X_FIFO_SIZE
,
541 .max_wm
= G4X_MAX_WM
,
542 .default_wm
= G4X_MAX_WM
,
544 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
546 static const struct intel_watermark_params g4x_cursor_wm_info
= {
547 .fifo_size
= I965_CURSOR_FIFO
,
548 .max_wm
= I965_CURSOR_MAX_WM
,
549 .default_wm
= I965_CURSOR_DFT_WM
,
551 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
553 static const struct intel_watermark_params i965_cursor_wm_info
= {
554 .fifo_size
= I965_CURSOR_FIFO
,
555 .max_wm
= I965_CURSOR_MAX_WM
,
556 .default_wm
= I965_CURSOR_DFT_WM
,
558 .cacheline_size
= I915_FIFO_LINE_SIZE
,
560 static const struct intel_watermark_params i945_wm_info
= {
561 .fifo_size
= I945_FIFO_SIZE
,
562 .max_wm
= I915_MAX_WM
,
565 .cacheline_size
= I915_FIFO_LINE_SIZE
,
567 static const struct intel_watermark_params i915_wm_info
= {
568 .fifo_size
= I915_FIFO_SIZE
,
569 .max_wm
= I915_MAX_WM
,
572 .cacheline_size
= I915_FIFO_LINE_SIZE
,
574 static const struct intel_watermark_params i830_a_wm_info
= {
575 .fifo_size
= I855GM_FIFO_SIZE
,
576 .max_wm
= I915_MAX_WM
,
579 .cacheline_size
= I830_FIFO_LINE_SIZE
,
581 static const struct intel_watermark_params i830_bc_wm_info
= {
582 .fifo_size
= I855GM_FIFO_SIZE
,
583 .max_wm
= I915_MAX_WM
/2,
586 .cacheline_size
= I830_FIFO_LINE_SIZE
,
588 static const struct intel_watermark_params i845_wm_info
= {
589 .fifo_size
= I830_FIFO_SIZE
,
590 .max_wm
= I915_MAX_WM
,
593 .cacheline_size
= I830_FIFO_LINE_SIZE
,
597 * intel_calculate_wm - calculate watermark level
598 * @clock_in_khz: pixel clock
599 * @wm: chip FIFO params
600 * @cpp: bytes per pixel
601 * @latency_ns: memory latency for the platform
603 * Calculate the watermark level (the level at which the display plane will
604 * start fetching from memory again). Each chip has a different display
605 * FIFO size and allocation, so the caller needs to figure that out and pass
606 * in the correct intel_watermark_params structure.
608 * As the pixel clock runs, the FIFO will be drained at a rate that depends
609 * on the pixel size. When it reaches the watermark level, it'll start
610 * fetching FIFO line sized based chunks from memory until the FIFO fills
611 * past the watermark point. If the FIFO drains completely, a FIFO underrun
612 * will occur, and a display engine hang could result.
614 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
615 const struct intel_watermark_params
*wm
,
616 int fifo_size
, int cpp
,
617 unsigned long latency_ns
)
619 long entries_required
, wm_size
;
622 * Note: we need to make sure we don't overflow for various clock &
624 * clocks go from a few thousand to several hundred thousand.
625 * latency is usually a few thousand
627 entries_required
= ((clock_in_khz
/ 1000) * cpp
* latency_ns
) /
629 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
631 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
633 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
635 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
637 /* Don't promote wm_size to unsigned... */
638 if (wm_size
> (long)wm
->max_wm
)
639 wm_size
= wm
->max_wm
;
641 wm_size
= wm
->default_wm
;
644 * Bspec seems to indicate that the value shouldn't be lower than
645 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
646 * Lets go for 8 which is the burst size since certain platforms
647 * already use a hardcoded 8 (which is what the spec says should be
656 static struct intel_crtc
*single_enabled_crtc(struct drm_i915_private
*dev_priv
)
658 struct intel_crtc
*crtc
, *enabled
= NULL
;
660 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
661 if (intel_crtc_active(crtc
)) {
671 static void pineview_update_wm(struct intel_crtc
*unused_crtc
)
673 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
674 struct intel_crtc
*crtc
;
675 const struct cxsr_latency
*latency
;
679 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv
),
684 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
685 intel_set_memory_cxsr(dev_priv
, false);
689 crtc
= single_enabled_crtc(dev_priv
);
691 const struct drm_display_mode
*adjusted_mode
=
692 &crtc
->config
->base
.adjusted_mode
;
693 const struct drm_framebuffer
*fb
=
694 crtc
->base
.primary
->state
->fb
;
695 int cpp
= fb
->format
->cpp
[0];
696 int clock
= adjusted_mode
->crtc_clock
;
699 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
700 pineview_display_wm
.fifo_size
,
701 cpp
, latency
->display_sr
);
702 reg
= I915_READ(DSPFW1
);
703 reg
&= ~DSPFW_SR_MASK
;
704 reg
|= FW_WM(wm
, SR
);
705 I915_WRITE(DSPFW1
, reg
);
706 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
709 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
710 pineview_display_wm
.fifo_size
,
711 cpp
, latency
->cursor_sr
);
712 reg
= I915_READ(DSPFW3
);
713 reg
&= ~DSPFW_CURSOR_SR_MASK
;
714 reg
|= FW_WM(wm
, CURSOR_SR
);
715 I915_WRITE(DSPFW3
, reg
);
717 /* Display HPLL off SR */
718 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
719 pineview_display_hplloff_wm
.fifo_size
,
720 cpp
, latency
->display_hpll_disable
);
721 reg
= I915_READ(DSPFW3
);
722 reg
&= ~DSPFW_HPLL_SR_MASK
;
723 reg
|= FW_WM(wm
, HPLL_SR
);
724 I915_WRITE(DSPFW3
, reg
);
726 /* cursor HPLL off SR */
727 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
728 pineview_display_hplloff_wm
.fifo_size
,
729 cpp
, latency
->cursor_hpll_disable
);
730 reg
= I915_READ(DSPFW3
);
731 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
732 reg
|= FW_WM(wm
, HPLL_CURSOR
);
733 I915_WRITE(DSPFW3
, reg
);
734 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
736 intel_set_memory_cxsr(dev_priv
, true);
738 intel_set_memory_cxsr(dev_priv
, false);
742 static bool g4x_compute_wm0(struct drm_i915_private
*dev_priv
,
744 const struct intel_watermark_params
*display
,
745 int display_latency_ns
,
746 const struct intel_watermark_params
*cursor
,
747 int cursor_latency_ns
,
751 struct intel_crtc
*crtc
;
752 const struct drm_display_mode
*adjusted_mode
;
753 const struct drm_framebuffer
*fb
;
754 int htotal
, hdisplay
, clock
, cpp
;
755 int line_time_us
, line_count
;
756 int entries
, tlb_miss
;
758 crtc
= intel_get_crtc_for_plane(dev_priv
, plane
);
759 if (!intel_crtc_active(crtc
)) {
760 *cursor_wm
= cursor
->guard_size
;
761 *plane_wm
= display
->guard_size
;
765 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
766 fb
= crtc
->base
.primary
->state
->fb
;
767 clock
= adjusted_mode
->crtc_clock
;
768 htotal
= adjusted_mode
->crtc_htotal
;
769 hdisplay
= crtc
->config
->pipe_src_w
;
770 cpp
= fb
->format
->cpp
[0];
772 /* Use the small buffer method to calculate plane watermark */
773 entries
= ((clock
* cpp
/ 1000) * display_latency_ns
) / 1000;
774 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
777 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
778 *plane_wm
= entries
+ display
->guard_size
;
779 if (*plane_wm
> (int)display
->max_wm
)
780 *plane_wm
= display
->max_wm
;
782 /* Use the large buffer method to calculate cursor watermark */
783 line_time_us
= max(htotal
* 1000 / clock
, 1);
784 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
785 entries
= line_count
* crtc
->base
.cursor
->state
->crtc_w
* cpp
;
786 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
789 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
790 *cursor_wm
= entries
+ cursor
->guard_size
;
791 if (*cursor_wm
> (int)cursor
->max_wm
)
792 *cursor_wm
= (int)cursor
->max_wm
;
798 * Check the wm result.
800 * If any calculated watermark values is larger than the maximum value that
801 * can be programmed into the associated watermark register, that watermark
804 static bool g4x_check_srwm(struct drm_i915_private
*dev_priv
,
805 int display_wm
, int cursor_wm
,
806 const struct intel_watermark_params
*display
,
807 const struct intel_watermark_params
*cursor
)
809 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
810 display_wm
, cursor_wm
);
812 if (display_wm
> display
->max_wm
) {
813 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
814 display_wm
, display
->max_wm
);
818 if (cursor_wm
> cursor
->max_wm
) {
819 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
820 cursor_wm
, cursor
->max_wm
);
824 if (!(display_wm
|| cursor_wm
)) {
825 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
832 static bool g4x_compute_srwm(struct drm_i915_private
*dev_priv
,
835 const struct intel_watermark_params
*display
,
836 const struct intel_watermark_params
*cursor
,
837 int *display_wm
, int *cursor_wm
)
839 struct intel_crtc
*crtc
;
840 const struct drm_display_mode
*adjusted_mode
;
841 const struct drm_framebuffer
*fb
;
842 int hdisplay
, htotal
, cpp
, clock
;
843 unsigned long line_time_us
;
844 int line_count
, line_size
;
849 *display_wm
= *cursor_wm
= 0;
853 crtc
= intel_get_crtc_for_plane(dev_priv
, plane
);
854 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
855 fb
= crtc
->base
.primary
->state
->fb
;
856 clock
= adjusted_mode
->crtc_clock
;
857 htotal
= adjusted_mode
->crtc_htotal
;
858 hdisplay
= crtc
->config
->pipe_src_w
;
859 cpp
= fb
->format
->cpp
[0];
861 line_time_us
= max(htotal
* 1000 / clock
, 1);
862 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
863 line_size
= hdisplay
* cpp
;
865 /* Use the minimum of the small and large buffer method for primary */
866 small
= ((clock
* cpp
/ 1000) * latency_ns
) / 1000;
867 large
= line_count
* line_size
;
869 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
870 *display_wm
= entries
+ display
->guard_size
;
872 /* calculate the self-refresh watermark for display cursor */
873 entries
= line_count
* cpp
* crtc
->base
.cursor
->state
->crtc_w
;
874 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
875 *cursor_wm
= entries
+ cursor
->guard_size
;
877 return g4x_check_srwm(dev_priv
,
878 *display_wm
, *cursor_wm
,
882 #define FW_WM_VLV(value, plane) \
883 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
885 static void vlv_write_wm_values(struct drm_i915_private
*dev_priv
,
886 const struct vlv_wm_values
*wm
)
890 for_each_pipe(dev_priv
, pipe
) {
891 I915_WRITE(VLV_DDL(pipe
),
892 (wm
->ddl
[pipe
].plane
[PLANE_CURSOR
] << DDL_CURSOR_SHIFT
) |
893 (wm
->ddl
[pipe
].plane
[PLANE_SPRITE1
] << DDL_SPRITE_SHIFT(1)) |
894 (wm
->ddl
[pipe
].plane
[PLANE_SPRITE0
] << DDL_SPRITE_SHIFT(0)) |
895 (wm
->ddl
[pipe
].plane
[PLANE_PRIMARY
] << DDL_PLANE_SHIFT
));
899 * Zero the (unused) WM1 watermarks, and also clear all the
900 * high order bits so that there are no out of bounds values
901 * present in the registers during the reprogramming.
903 I915_WRITE(DSPHOWM
, 0);
904 I915_WRITE(DSPHOWM1
, 0);
905 I915_WRITE(DSPFW4
, 0);
906 I915_WRITE(DSPFW5
, 0);
907 I915_WRITE(DSPFW6
, 0);
910 FW_WM(wm
->sr
.plane
, SR
) |
911 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_CURSOR
], CURSORB
) |
912 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
], PLANEB
) |
913 FW_WM_VLV(wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
], PLANEA
));
915 FW_WM_VLV(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
], SPRITEB
) |
916 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_CURSOR
], CURSORA
) |
917 FW_WM_VLV(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
], SPRITEA
));
919 FW_WM(wm
->sr
.cursor
, CURSOR_SR
));
921 if (IS_CHERRYVIEW(dev_priv
)) {
922 I915_WRITE(DSPFW7_CHV
,
923 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
], SPRITED
) |
924 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
], SPRITEC
));
925 I915_WRITE(DSPFW8_CHV
,
926 FW_WM_VLV(wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE1
], SPRITEF
) |
927 FW_WM_VLV(wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE0
], SPRITEE
));
928 I915_WRITE(DSPFW9_CHV
,
929 FW_WM_VLV(wm
->pipe
[PIPE_C
].plane
[PLANE_PRIMARY
], PLANEC
) |
930 FW_WM(wm
->pipe
[PIPE_C
].plane
[PLANE_CURSOR
], CURSORC
));
932 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
933 FW_WM(wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE1
] >> 8, SPRITEF_HI
) |
934 FW_WM(wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE0
] >> 8, SPRITEE_HI
) |
935 FW_WM(wm
->pipe
[PIPE_C
].plane
[PLANE_PRIMARY
] >> 8, PLANEC_HI
) |
936 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] >> 8, SPRITED_HI
) |
937 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] >> 8, SPRITEC_HI
) |
938 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] >> 8, PLANEB_HI
) |
939 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] >> 8, SPRITEB_HI
) |
940 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] >> 8, SPRITEA_HI
) |
941 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] >> 8, PLANEA_HI
));
944 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
], SPRITED
) |
945 FW_WM_VLV(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
], SPRITEC
));
947 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
948 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] >> 8, SPRITED_HI
) |
949 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] >> 8, SPRITEC_HI
) |
950 FW_WM(wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] >> 8, PLANEB_HI
) |
951 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] >> 8, SPRITEB_HI
) |
952 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] >> 8, SPRITEA_HI
) |
953 FW_WM(wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] >> 8, PLANEA_HI
));
956 POSTING_READ(DSPFW1
);
961 /* latency must be in 0.1us units. */
962 static unsigned int vlv_wm_method2(unsigned int pixel_rate
,
963 unsigned int pipe_htotal
,
964 unsigned int horiz_pixels
,
966 unsigned int latency
)
970 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
971 ret
= (ret
+ 1) * horiz_pixels
* cpp
;
972 ret
= DIV_ROUND_UP(ret
, 64);
977 static void vlv_setup_wm_latency(struct drm_i915_private
*dev_priv
)
979 /* all latencies in usec */
980 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM2
] = 3;
982 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM2
;
984 if (IS_CHERRYVIEW(dev_priv
)) {
985 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM5
] = 12;
986 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_DDR_DVFS
] = 33;
988 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_DDR_DVFS
;
992 static uint16_t vlv_compute_wm_level(const struct intel_crtc_state
*crtc_state
,
993 const struct intel_plane_state
*plane_state
,
996 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
997 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
998 const struct drm_display_mode
*adjusted_mode
=
999 &crtc_state
->base
.adjusted_mode
;
1000 int clock
, htotal
, cpp
, width
, wm
;
1002 if (dev_priv
->wm
.pri_latency
[level
] == 0)
1005 if (!plane_state
->base
.visible
)
1008 cpp
= plane_state
->base
.fb
->format
->cpp
[0];
1009 clock
= adjusted_mode
->crtc_clock
;
1010 htotal
= adjusted_mode
->crtc_htotal
;
1011 width
= crtc_state
->pipe_src_w
;
1012 if (WARN_ON(htotal
== 0))
1015 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
1017 * FIXME the formula gives values that are
1018 * too big for the cursor FIFO, and hence we
1019 * would never be able to use cursors. For
1020 * now just hardcode the watermark.
1024 wm
= vlv_wm_method2(clock
, htotal
, width
, cpp
,
1025 dev_priv
->wm
.pri_latency
[level
] * 10);
1028 return min_t(int, wm
, USHRT_MAX
);
1031 static int vlv_compute_fifo(struct intel_crtc_state
*crtc_state
)
1033 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1034 const struct vlv_pipe_wm
*raw
=
1035 &crtc_state
->wm
.vlv
.raw
[VLV_WM_LEVEL_PM2
];
1036 struct vlv_fifo_state
*fifo_state
= &crtc_state
->wm
.vlv
.fifo_state
;
1037 unsigned int active_planes
= crtc_state
->active_planes
& ~BIT(PLANE_CURSOR
);
1038 int num_active_planes
= hweight32(active_planes
);
1039 const int fifo_size
= 511;
1040 int fifo_extra
, fifo_left
= fifo_size
;
1041 unsigned int total_rate
;
1042 enum plane_id plane_id
;
1044 total_rate
= raw
->plane
[PLANE_PRIMARY
] +
1045 raw
->plane
[PLANE_SPRITE0
] +
1046 raw
->plane
[PLANE_SPRITE1
];
1048 if (total_rate
> fifo_size
)
1051 if (total_rate
== 0)
1054 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1057 if ((active_planes
& BIT(plane_id
)) == 0) {
1058 fifo_state
->plane
[plane_id
] = 0;
1062 rate
= raw
->plane
[plane_id
];
1063 fifo_state
->plane
[plane_id
] = fifo_size
* rate
/ total_rate
;
1064 fifo_left
-= fifo_state
->plane
[plane_id
];
1067 fifo_state
->plane
[PLANE_CURSOR
] = 63;
1069 fifo_extra
= DIV_ROUND_UP(fifo_left
, num_active_planes
?: 1);
1071 /* spread the remainder evenly */
1072 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1078 if ((active_planes
& BIT(plane_id
)) == 0)
1081 plane_extra
= min(fifo_extra
, fifo_left
);
1082 fifo_state
->plane
[plane_id
] += plane_extra
;
1083 fifo_left
-= plane_extra
;
1086 WARN_ON(active_planes
!= 0 && fifo_left
!= 0);
1088 /* give it all to the first plane if none are active */
1089 if (active_planes
== 0) {
1090 WARN_ON(fifo_left
!= fifo_size
);
1091 fifo_state
->plane
[PLANE_PRIMARY
] = fifo_left
;
1097 static int vlv_num_wm_levels(struct drm_i915_private
*dev_priv
)
1099 return dev_priv
->wm
.max_level
+ 1;
1102 /* mark all levels starting from 'level' as invalid */
1103 static void vlv_invalidate_wms(struct intel_crtc
*crtc
,
1104 struct vlv_wm_state
*wm_state
, int level
)
1106 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1108 for (; level
< vlv_num_wm_levels(dev_priv
); level
++) {
1109 enum plane_id plane_id
;
1111 for_each_plane_id_on_crtc(crtc
, plane_id
)
1112 wm_state
->wm
[level
].plane
[plane_id
] = USHRT_MAX
;
1114 wm_state
->sr
[level
].cursor
= USHRT_MAX
;
1115 wm_state
->sr
[level
].plane
= USHRT_MAX
;
1119 static u16
vlv_invert_wm_value(u16 wm
, u16 fifo_size
)
1124 return fifo_size
- wm
;
1128 * Starting from 'level' set all higher
1129 * levels to 'value' in the "raw" watermarks.
1131 static bool vlv_raw_plane_wm_set(struct intel_crtc_state
*crtc_state
,
1132 int level
, enum plane_id plane_id
, u16 value
)
1134 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1135 int num_levels
= vlv_num_wm_levels(dev_priv
);
1138 for (; level
< num_levels
; level
++) {
1139 struct vlv_pipe_wm
*raw
= &crtc_state
->wm
.vlv
.raw
[level
];
1141 dirty
|= raw
->plane
[plane_id
] != value
;
1142 raw
->plane
[plane_id
] = value
;
1148 static bool vlv_plane_wm_compute(struct intel_crtc_state
*crtc_state
,
1149 const struct intel_plane_state
*plane_state
)
1151 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
1152 enum plane_id plane_id
= plane
->id
;
1153 int num_levels
= vlv_num_wm_levels(to_i915(plane
->base
.dev
));
1157 if (!plane_state
->base
.visible
) {
1158 dirty
|= vlv_raw_plane_wm_set(crtc_state
, 0, plane_id
, 0);
1162 for (level
= 0; level
< num_levels
; level
++) {
1163 struct vlv_pipe_wm
*raw
= &crtc_state
->wm
.vlv
.raw
[level
];
1164 int wm
= vlv_compute_wm_level(crtc_state
, plane_state
, level
);
1165 int max_wm
= plane_id
== PLANE_CURSOR
? 63 : 511;
1167 /* FIXME just bail */
1168 if (WARN_ON(level
== 0 && wm
> max_wm
))
1174 dirty
|= raw
->plane
[plane_id
] != wm
;
1175 raw
->plane
[plane_id
] = wm
;
1178 /* mark all higher levels as invalid */
1179 dirty
|= vlv_raw_plane_wm_set(crtc_state
, level
, plane_id
, USHRT_MAX
);
1183 DRM_DEBUG_KMS("%s wms: [0]=%d,[1]=%d,[2]=%d\n",
1185 crtc_state
->wm
.vlv
.raw
[VLV_WM_LEVEL_PM2
].plane
[plane_id
],
1186 crtc_state
->wm
.vlv
.raw
[VLV_WM_LEVEL_PM5
].plane
[plane_id
],
1187 crtc_state
->wm
.vlv
.raw
[VLV_WM_LEVEL_DDR_DVFS
].plane
[plane_id
]);
1192 static bool vlv_plane_wm_is_valid(const struct intel_crtc_state
*crtc_state
,
1193 enum plane_id plane_id
, int level
)
1195 const struct vlv_pipe_wm
*raw
=
1196 &crtc_state
->wm
.vlv
.raw
[level
];
1197 const struct vlv_fifo_state
*fifo_state
=
1198 &crtc_state
->wm
.vlv
.fifo_state
;
1200 return raw
->plane
[plane_id
] <= fifo_state
->plane
[plane_id
];
1203 static bool vlv_crtc_wm_is_valid(const struct intel_crtc_state
*crtc_state
, int level
)
1205 return vlv_plane_wm_is_valid(crtc_state
, PLANE_PRIMARY
, level
) &&
1206 vlv_plane_wm_is_valid(crtc_state
, PLANE_SPRITE0
, level
) &&
1207 vlv_plane_wm_is_valid(crtc_state
, PLANE_SPRITE1
, level
) &&
1208 vlv_plane_wm_is_valid(crtc_state
, PLANE_CURSOR
, level
);
1211 static int vlv_compute_pipe_wm(struct intel_crtc_state
*crtc_state
)
1213 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1214 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1215 struct intel_atomic_state
*state
=
1216 to_intel_atomic_state(crtc_state
->base
.state
);
1217 struct vlv_wm_state
*wm_state
= &crtc_state
->wm
.vlv
.optimal
;
1218 const struct vlv_fifo_state
*fifo_state
=
1219 &crtc_state
->wm
.vlv
.fifo_state
;
1220 int num_active_planes
= hweight32(crtc_state
->active_planes
&
1221 ~BIT(PLANE_CURSOR
));
1222 bool needs_modeset
= drm_atomic_crtc_needs_modeset(&crtc_state
->base
);
1223 struct intel_plane_state
*plane_state
;
1224 struct intel_plane
*plane
;
1225 enum plane_id plane_id
;
1227 unsigned int dirty
= 0;
1229 for_each_intel_plane_in_state(state
, plane
, plane_state
, i
) {
1230 const struct intel_plane_state
*old_plane_state
=
1231 to_intel_plane_state(plane
->base
.state
);
1233 if (plane_state
->base
.crtc
!= &crtc
->base
&&
1234 old_plane_state
->base
.crtc
!= &crtc
->base
)
1237 if (vlv_plane_wm_compute(crtc_state
, plane_state
))
1238 dirty
|= BIT(plane
->id
);
1242 * DSPARB registers may have been reset due to the
1243 * power well being turned off. Make sure we restore
1244 * them to a consistent state even if no primary/sprite
1245 * planes are initially active.
1248 crtc_state
->fifo_changed
= true;
1253 /* cursor changes don't warrant a FIFO recompute */
1254 if (dirty
& ~BIT(PLANE_CURSOR
)) {
1255 const struct intel_crtc_state
*old_crtc_state
=
1256 to_intel_crtc_state(crtc
->base
.state
);
1257 const struct vlv_fifo_state
*old_fifo_state
=
1258 &old_crtc_state
->wm
.vlv
.fifo_state
;
1260 ret
= vlv_compute_fifo(crtc_state
);
1264 if (needs_modeset
||
1265 memcmp(old_fifo_state
, fifo_state
,
1266 sizeof(*fifo_state
)) != 0)
1267 crtc_state
->fifo_changed
= true;
1270 /* initially allow all levels */
1271 wm_state
->num_levels
= vlv_num_wm_levels(dev_priv
);
1273 * Note that enabling cxsr with no primary/sprite planes
1274 * enabled can wedge the pipe. Hence we only allow cxsr
1275 * with exactly one enabled primary/sprite plane.
1277 wm_state
->cxsr
= crtc
->pipe
!= PIPE_C
&&
1278 crtc
->wm
.cxsr_allowed
&& num_active_planes
== 1;
1280 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1281 const struct vlv_pipe_wm
*raw
= &crtc_state
->wm
.vlv
.raw
[level
];
1282 const int sr_fifo_size
= INTEL_INFO(dev_priv
)->num_pipes
* 512 - 1;
1284 if (!vlv_crtc_wm_is_valid(crtc_state
, level
))
1287 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1288 wm_state
->wm
[level
].plane
[plane_id
] =
1289 vlv_invert_wm_value(raw
->plane
[plane_id
],
1290 fifo_state
->plane
[plane_id
]);
1293 wm_state
->sr
[level
].plane
=
1294 vlv_invert_wm_value(max3(raw
->plane
[PLANE_PRIMARY
],
1295 raw
->plane
[PLANE_SPRITE0
],
1296 raw
->plane
[PLANE_SPRITE1
]),
1299 wm_state
->sr
[level
].cursor
=
1300 vlv_invert_wm_value(raw
->plane
[PLANE_CURSOR
],
1307 /* limit to only levels we can actually handle */
1308 wm_state
->num_levels
= level
;
1310 /* invalidate the higher levels */
1311 vlv_invalidate_wms(crtc
, wm_state
, level
);
1316 #define VLV_FIFO(plane, value) \
1317 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1319 static void vlv_atomic_update_fifo(struct intel_atomic_state
*state
,
1320 struct intel_crtc_state
*crtc_state
)
1322 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1323 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1324 const struct vlv_fifo_state
*fifo_state
=
1325 &crtc_state
->wm
.vlv
.fifo_state
;
1326 int sprite0_start
, sprite1_start
, fifo_size
;
1328 if (!crtc_state
->fifo_changed
)
1331 sprite0_start
= fifo_state
->plane
[PLANE_PRIMARY
];
1332 sprite1_start
= fifo_state
->plane
[PLANE_SPRITE0
] + sprite0_start
;
1333 fifo_size
= fifo_state
->plane
[PLANE_SPRITE1
] + sprite1_start
;
1335 WARN_ON(fifo_state
->plane
[PLANE_CURSOR
] != 63);
1336 WARN_ON(fifo_size
!= 511);
1338 spin_lock(&dev_priv
->wm
.dsparb_lock
);
1340 switch (crtc
->pipe
) {
1341 uint32_t dsparb
, dsparb2
, dsparb3
;
1343 dsparb
= I915_READ(DSPARB
);
1344 dsparb2
= I915_READ(DSPARB2
);
1346 dsparb
&= ~(VLV_FIFO(SPRITEA
, 0xff) |
1347 VLV_FIFO(SPRITEB
, 0xff));
1348 dsparb
|= (VLV_FIFO(SPRITEA
, sprite0_start
) |
1349 VLV_FIFO(SPRITEB
, sprite1_start
));
1351 dsparb2
&= ~(VLV_FIFO(SPRITEA_HI
, 0x1) |
1352 VLV_FIFO(SPRITEB_HI
, 0x1));
1353 dsparb2
|= (VLV_FIFO(SPRITEA_HI
, sprite0_start
>> 8) |
1354 VLV_FIFO(SPRITEB_HI
, sprite1_start
>> 8));
1356 I915_WRITE(DSPARB
, dsparb
);
1357 I915_WRITE(DSPARB2
, dsparb2
);
1360 dsparb
= I915_READ(DSPARB
);
1361 dsparb2
= I915_READ(DSPARB2
);
1363 dsparb
&= ~(VLV_FIFO(SPRITEC
, 0xff) |
1364 VLV_FIFO(SPRITED
, 0xff));
1365 dsparb
|= (VLV_FIFO(SPRITEC
, sprite0_start
) |
1366 VLV_FIFO(SPRITED
, sprite1_start
));
1368 dsparb2
&= ~(VLV_FIFO(SPRITEC_HI
, 0xff) |
1369 VLV_FIFO(SPRITED_HI
, 0xff));
1370 dsparb2
|= (VLV_FIFO(SPRITEC_HI
, sprite0_start
>> 8) |
1371 VLV_FIFO(SPRITED_HI
, sprite1_start
>> 8));
1373 I915_WRITE(DSPARB
, dsparb
);
1374 I915_WRITE(DSPARB2
, dsparb2
);
1377 dsparb3
= I915_READ(DSPARB3
);
1378 dsparb2
= I915_READ(DSPARB2
);
1380 dsparb3
&= ~(VLV_FIFO(SPRITEE
, 0xff) |
1381 VLV_FIFO(SPRITEF
, 0xff));
1382 dsparb3
|= (VLV_FIFO(SPRITEE
, sprite0_start
) |
1383 VLV_FIFO(SPRITEF
, sprite1_start
));
1385 dsparb2
&= ~(VLV_FIFO(SPRITEE_HI
, 0xff) |
1386 VLV_FIFO(SPRITEF_HI
, 0xff));
1387 dsparb2
|= (VLV_FIFO(SPRITEE_HI
, sprite0_start
>> 8) |
1388 VLV_FIFO(SPRITEF_HI
, sprite1_start
>> 8));
1390 I915_WRITE(DSPARB3
, dsparb3
);
1391 I915_WRITE(DSPARB2
, dsparb2
);
1397 POSTING_READ(DSPARB
);
1399 spin_unlock(&dev_priv
->wm
.dsparb_lock
);
1404 static void vlv_merge_wm(struct drm_i915_private
*dev_priv
,
1405 struct vlv_wm_values
*wm
)
1407 struct intel_crtc
*crtc
;
1408 int num_active_crtcs
= 0;
1410 wm
->level
= dev_priv
->wm
.max_level
;
1413 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
1414 const struct vlv_wm_state
*wm_state
= &crtc
->wm
.active
.vlv
;
1419 if (!wm_state
->cxsr
)
1423 wm
->level
= min_t(int, wm
->level
, wm_state
->num_levels
- 1);
1426 if (num_active_crtcs
!= 1)
1429 if (num_active_crtcs
> 1)
1430 wm
->level
= VLV_WM_LEVEL_PM2
;
1432 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
1433 const struct vlv_wm_state
*wm_state
= &crtc
->wm
.active
.vlv
;
1434 enum pipe pipe
= crtc
->pipe
;
1436 wm
->pipe
[pipe
] = wm_state
->wm
[wm
->level
];
1437 if (crtc
->active
&& wm
->cxsr
)
1438 wm
->sr
= wm_state
->sr
[wm
->level
];
1440 wm
->ddl
[pipe
].plane
[PLANE_PRIMARY
] = DDL_PRECISION_HIGH
| 2;
1441 wm
->ddl
[pipe
].plane
[PLANE_SPRITE0
] = DDL_PRECISION_HIGH
| 2;
1442 wm
->ddl
[pipe
].plane
[PLANE_SPRITE1
] = DDL_PRECISION_HIGH
| 2;
1443 wm
->ddl
[pipe
].plane
[PLANE_CURSOR
] = DDL_PRECISION_HIGH
| 2;
1447 static bool is_disabling(int old
, int new, int threshold
)
1449 return old
>= threshold
&& new < threshold
;
1452 static bool is_enabling(int old
, int new, int threshold
)
1454 return old
< threshold
&& new >= threshold
;
1457 static void vlv_program_watermarks(struct drm_i915_private
*dev_priv
)
1459 struct vlv_wm_values
*old_wm
= &dev_priv
->wm
.vlv
;
1460 struct vlv_wm_values new_wm
= {};
1462 vlv_merge_wm(dev_priv
, &new_wm
);
1464 if (memcmp(old_wm
, &new_wm
, sizeof(new_wm
)) == 0)
1467 if (is_disabling(old_wm
->level
, new_wm
.level
, VLV_WM_LEVEL_DDR_DVFS
))
1468 chv_set_memory_dvfs(dev_priv
, false);
1470 if (is_disabling(old_wm
->level
, new_wm
.level
, VLV_WM_LEVEL_PM5
))
1471 chv_set_memory_pm5(dev_priv
, false);
1473 if (is_disabling(old_wm
->cxsr
, new_wm
.cxsr
, true))
1474 _intel_set_memory_cxsr(dev_priv
, false);
1476 vlv_write_wm_values(dev_priv
, &new_wm
);
1478 if (is_enabling(old_wm
->cxsr
, new_wm
.cxsr
, true))
1479 _intel_set_memory_cxsr(dev_priv
, true);
1481 if (is_enabling(old_wm
->level
, new_wm
.level
, VLV_WM_LEVEL_PM5
))
1482 chv_set_memory_pm5(dev_priv
, true);
1484 if (is_enabling(old_wm
->level
, new_wm
.level
, VLV_WM_LEVEL_DDR_DVFS
))
1485 chv_set_memory_dvfs(dev_priv
, true);
1490 static void vlv_initial_watermarks(struct intel_atomic_state
*state
,
1491 struct intel_crtc_state
*crtc_state
)
1493 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1494 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1496 mutex_lock(&dev_priv
->wm
.wm_mutex
);
1497 crtc
->wm
.active
.vlv
= crtc_state
->wm
.vlv
.optimal
;
1498 vlv_program_watermarks(dev_priv
);
1499 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
1502 #define single_plane_enabled(mask) is_power_of_2(mask)
1504 static void g4x_update_wm(struct intel_crtc
*crtc
)
1506 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1507 static const int sr_latency_ns
= 12000;
1508 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1509 int plane_sr
, cursor_sr
;
1510 unsigned int enabled
= 0;
1513 if (g4x_compute_wm0(dev_priv
, PIPE_A
,
1514 &g4x_wm_info
, pessimal_latency_ns
,
1515 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1516 &planea_wm
, &cursora_wm
))
1517 enabled
|= 1 << PIPE_A
;
1519 if (g4x_compute_wm0(dev_priv
, PIPE_B
,
1520 &g4x_wm_info
, pessimal_latency_ns
,
1521 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1522 &planeb_wm
, &cursorb_wm
))
1523 enabled
|= 1 << PIPE_B
;
1525 if (single_plane_enabled(enabled
) &&
1526 g4x_compute_srwm(dev_priv
, ffs(enabled
) - 1,
1529 &g4x_cursor_wm_info
,
1530 &plane_sr
, &cursor_sr
)) {
1531 cxsr_enabled
= true;
1533 cxsr_enabled
= false;
1534 intel_set_memory_cxsr(dev_priv
, false);
1535 plane_sr
= cursor_sr
= 0;
1538 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1539 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1540 planea_wm
, cursora_wm
,
1541 planeb_wm
, cursorb_wm
,
1542 plane_sr
, cursor_sr
);
1545 FW_WM(plane_sr
, SR
) |
1546 FW_WM(cursorb_wm
, CURSORB
) |
1547 FW_WM(planeb_wm
, PLANEB
) |
1548 FW_WM(planea_wm
, PLANEA
));
1550 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1551 FW_WM(cursora_wm
, CURSORA
));
1552 /* HPLL off in SR has some issues on G4x... disable it */
1554 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1555 FW_WM(cursor_sr
, CURSOR_SR
));
1558 intel_set_memory_cxsr(dev_priv
, true);
1561 static void i965_update_wm(struct intel_crtc
*unused_crtc
)
1563 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
1564 struct intel_crtc
*crtc
;
1569 /* Calc sr entries for one plane configs */
1570 crtc
= single_enabled_crtc(dev_priv
);
1572 /* self-refresh has much higher latency */
1573 static const int sr_latency_ns
= 12000;
1574 const struct drm_display_mode
*adjusted_mode
=
1575 &crtc
->config
->base
.adjusted_mode
;
1576 const struct drm_framebuffer
*fb
=
1577 crtc
->base
.primary
->state
->fb
;
1578 int clock
= adjusted_mode
->crtc_clock
;
1579 int htotal
= adjusted_mode
->crtc_htotal
;
1580 int hdisplay
= crtc
->config
->pipe_src_w
;
1581 int cpp
= fb
->format
->cpp
[0];
1582 unsigned long line_time_us
;
1585 line_time_us
= max(htotal
* 1000 / clock
, 1);
1587 /* Use ns/us then divide to preserve precision */
1588 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1590 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1591 srwm
= I965_FIFO_SIZE
- entries
;
1595 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1598 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1599 cpp
* crtc
->base
.cursor
->state
->crtc_w
;
1600 entries
= DIV_ROUND_UP(entries
,
1601 i965_cursor_wm_info
.cacheline_size
);
1602 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1603 (entries
+ i965_cursor_wm_info
.guard_size
);
1605 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1606 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1608 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1609 "cursor %d\n", srwm
, cursor_sr
);
1611 cxsr_enabled
= true;
1613 cxsr_enabled
= false;
1614 /* Turn off self refresh if both pipes are enabled */
1615 intel_set_memory_cxsr(dev_priv
, false);
1618 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1621 /* 965 has limitations... */
1622 I915_WRITE(DSPFW1
, FW_WM(srwm
, SR
) |
1626 I915_WRITE(DSPFW2
, FW_WM(8, CURSORA
) |
1627 FW_WM(8, PLANEC_OLD
));
1628 /* update cursor SR watermark */
1629 I915_WRITE(DSPFW3
, FW_WM(cursor_sr
, CURSOR_SR
));
1632 intel_set_memory_cxsr(dev_priv
, true);
1637 static void i9xx_update_wm(struct intel_crtc
*unused_crtc
)
1639 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
1640 const struct intel_watermark_params
*wm_info
;
1645 int planea_wm
, planeb_wm
;
1646 struct intel_crtc
*crtc
, *enabled
= NULL
;
1648 if (IS_I945GM(dev_priv
))
1649 wm_info
= &i945_wm_info
;
1650 else if (!IS_GEN2(dev_priv
))
1651 wm_info
= &i915_wm_info
;
1653 wm_info
= &i830_a_wm_info
;
1655 fifo_size
= dev_priv
->display
.get_fifo_size(dev_priv
, 0);
1656 crtc
= intel_get_crtc_for_plane(dev_priv
, 0);
1657 if (intel_crtc_active(crtc
)) {
1658 const struct drm_display_mode
*adjusted_mode
=
1659 &crtc
->config
->base
.adjusted_mode
;
1660 const struct drm_framebuffer
*fb
=
1661 crtc
->base
.primary
->state
->fb
;
1664 if (IS_GEN2(dev_priv
))
1667 cpp
= fb
->format
->cpp
[0];
1669 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1670 wm_info
, fifo_size
, cpp
,
1671 pessimal_latency_ns
);
1674 planea_wm
= fifo_size
- wm_info
->guard_size
;
1675 if (planea_wm
> (long)wm_info
->max_wm
)
1676 planea_wm
= wm_info
->max_wm
;
1679 if (IS_GEN2(dev_priv
))
1680 wm_info
= &i830_bc_wm_info
;
1682 fifo_size
= dev_priv
->display
.get_fifo_size(dev_priv
, 1);
1683 crtc
= intel_get_crtc_for_plane(dev_priv
, 1);
1684 if (intel_crtc_active(crtc
)) {
1685 const struct drm_display_mode
*adjusted_mode
=
1686 &crtc
->config
->base
.adjusted_mode
;
1687 const struct drm_framebuffer
*fb
=
1688 crtc
->base
.primary
->state
->fb
;
1691 if (IS_GEN2(dev_priv
))
1694 cpp
= fb
->format
->cpp
[0];
1696 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1697 wm_info
, fifo_size
, cpp
,
1698 pessimal_latency_ns
);
1699 if (enabled
== NULL
)
1704 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1705 if (planeb_wm
> (long)wm_info
->max_wm
)
1706 planeb_wm
= wm_info
->max_wm
;
1709 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1711 if (IS_I915GM(dev_priv
) && enabled
) {
1712 struct drm_i915_gem_object
*obj
;
1714 obj
= intel_fb_obj(enabled
->base
.primary
->state
->fb
);
1716 /* self-refresh seems busted with untiled */
1717 if (!i915_gem_object_is_tiled(obj
))
1722 * Overlay gets an aggressive default since video jitter is bad.
1726 /* Play safe and disable self-refresh before adjusting watermarks. */
1727 intel_set_memory_cxsr(dev_priv
, false);
1729 /* Calc sr entries for one plane configs */
1730 if (HAS_FW_BLC(dev_priv
) && enabled
) {
1731 /* self-refresh has much higher latency */
1732 static const int sr_latency_ns
= 6000;
1733 const struct drm_display_mode
*adjusted_mode
=
1734 &enabled
->config
->base
.adjusted_mode
;
1735 const struct drm_framebuffer
*fb
=
1736 enabled
->base
.primary
->state
->fb
;
1737 int clock
= adjusted_mode
->crtc_clock
;
1738 int htotal
= adjusted_mode
->crtc_htotal
;
1739 int hdisplay
= enabled
->config
->pipe_src_w
;
1741 unsigned long line_time_us
;
1744 if (IS_I915GM(dev_priv
) || IS_I945GM(dev_priv
))
1747 cpp
= fb
->format
->cpp
[0];
1749 line_time_us
= max(htotal
* 1000 / clock
, 1);
1751 /* Use ns/us then divide to preserve precision */
1752 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1754 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1755 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1756 srwm
= wm_info
->fifo_size
- entries
;
1760 if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
))
1761 I915_WRITE(FW_BLC_SELF
,
1762 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1764 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1767 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1768 planea_wm
, planeb_wm
, cwm
, srwm
);
1770 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1771 fwater_hi
= (cwm
& 0x1f);
1773 /* Set request length to 8 cachelines per fetch */
1774 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1775 fwater_hi
= fwater_hi
| (1 << 8);
1777 I915_WRITE(FW_BLC
, fwater_lo
);
1778 I915_WRITE(FW_BLC2
, fwater_hi
);
1781 intel_set_memory_cxsr(dev_priv
, true);
1784 static void i845_update_wm(struct intel_crtc
*unused_crtc
)
1786 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
1787 struct intel_crtc
*crtc
;
1788 const struct drm_display_mode
*adjusted_mode
;
1792 crtc
= single_enabled_crtc(dev_priv
);
1796 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
1797 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1799 dev_priv
->display
.get_fifo_size(dev_priv
, 0),
1800 4, pessimal_latency_ns
);
1801 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1802 fwater_lo
|= (3<<8) | planea_wm
;
1804 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1806 I915_WRITE(FW_BLC
, fwater_lo
);
1809 /* latency must be in 0.1us units. */
1810 static uint32_t ilk_wm_method1(uint32_t pixel_rate
, uint8_t cpp
, uint32_t latency
)
1814 if (WARN(latency
== 0, "Latency value missing\n"))
1817 ret
= (uint64_t) pixel_rate
* cpp
* latency
;
1818 ret
= DIV_ROUND_UP_ULL(ret
, 64 * 10000) + 2;
1823 /* latency must be in 0.1us units. */
1824 static uint32_t ilk_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
1825 uint32_t horiz_pixels
, uint8_t cpp
,
1830 if (WARN(latency
== 0, "Latency value missing\n"))
1832 if (WARN_ON(!pipe_htotal
))
1835 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
1836 ret
= (ret
+ 1) * horiz_pixels
* cpp
;
1837 ret
= DIV_ROUND_UP(ret
, 64) + 2;
1841 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
1845 * Neither of these should be possible since this function shouldn't be
1846 * called if the CRTC is off or the plane is invisible. But let's be
1847 * extra paranoid to avoid a potential divide-by-zero if we screw up
1848 * elsewhere in the driver.
1852 if (WARN_ON(!horiz_pixels
))
1855 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* cpp
) + 2;
1858 struct ilk_wm_maximums
{
1866 * For both WM_PIPE and WM_LP.
1867 * mem_value must be in 0.1us units.
1869 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state
*cstate
,
1870 const struct intel_plane_state
*pstate
,
1874 uint32_t method1
, method2
;
1877 if (!cstate
->base
.active
|| !pstate
->base
.visible
)
1880 cpp
= pstate
->base
.fb
->format
->cpp
[0];
1882 method1
= ilk_wm_method1(cstate
->pixel_rate
, cpp
, mem_value
);
1887 method2
= ilk_wm_method2(cstate
->pixel_rate
,
1888 cstate
->base
.adjusted_mode
.crtc_htotal
,
1889 drm_rect_width(&pstate
->base
.dst
),
1892 return min(method1
, method2
);
1896 * For both WM_PIPE and WM_LP.
1897 * mem_value must be in 0.1us units.
1899 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state
*cstate
,
1900 const struct intel_plane_state
*pstate
,
1903 uint32_t method1
, method2
;
1906 if (!cstate
->base
.active
|| !pstate
->base
.visible
)
1909 cpp
= pstate
->base
.fb
->format
->cpp
[0];
1911 method1
= ilk_wm_method1(cstate
->pixel_rate
, cpp
, mem_value
);
1912 method2
= ilk_wm_method2(cstate
->pixel_rate
,
1913 cstate
->base
.adjusted_mode
.crtc_htotal
,
1914 drm_rect_width(&pstate
->base
.dst
),
1916 return min(method1
, method2
);
1920 * For both WM_PIPE and WM_LP.
1921 * mem_value must be in 0.1us units.
1923 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state
*cstate
,
1924 const struct intel_plane_state
*pstate
,
1930 * Treat cursor with fb as always visible since cursor updates
1931 * can happen faster than the vrefresh rate, and the current
1932 * watermark code doesn't handle that correctly. Cursor updates
1933 * which set/clear the fb or change the cursor size are going
1934 * to get throttled by intel_legacy_cursor_update() to work
1935 * around this problem with the watermark code.
1937 if (!cstate
->base
.active
|| !pstate
->base
.fb
)
1940 cpp
= pstate
->base
.fb
->format
->cpp
[0];
1942 return ilk_wm_method2(cstate
->pixel_rate
,
1943 cstate
->base
.adjusted_mode
.crtc_htotal
,
1944 pstate
->base
.crtc_w
, cpp
, mem_value
);
1947 /* Only for WM_LP. */
1948 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state
*cstate
,
1949 const struct intel_plane_state
*pstate
,
1954 if (!cstate
->base
.active
|| !pstate
->base
.visible
)
1957 cpp
= pstate
->base
.fb
->format
->cpp
[0];
1959 return ilk_wm_fbc(pri_val
, drm_rect_width(&pstate
->base
.dst
), cpp
);
1963 ilk_display_fifo_size(const struct drm_i915_private
*dev_priv
)
1965 if (INTEL_GEN(dev_priv
) >= 8)
1967 else if (INTEL_GEN(dev_priv
) >= 7)
1974 ilk_plane_wm_reg_max(const struct drm_i915_private
*dev_priv
,
1975 int level
, bool is_sprite
)
1977 if (INTEL_GEN(dev_priv
) >= 8)
1978 /* BDW primary/sprite plane watermarks */
1979 return level
== 0 ? 255 : 2047;
1980 else if (INTEL_GEN(dev_priv
) >= 7)
1981 /* IVB/HSW primary/sprite plane watermarks */
1982 return level
== 0 ? 127 : 1023;
1983 else if (!is_sprite
)
1984 /* ILK/SNB primary plane watermarks */
1985 return level
== 0 ? 127 : 511;
1987 /* ILK/SNB sprite plane watermarks */
1988 return level
== 0 ? 63 : 255;
1992 ilk_cursor_wm_reg_max(const struct drm_i915_private
*dev_priv
, int level
)
1994 if (INTEL_GEN(dev_priv
) >= 7)
1995 return level
== 0 ? 63 : 255;
1997 return level
== 0 ? 31 : 63;
2000 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private
*dev_priv
)
2002 if (INTEL_GEN(dev_priv
) >= 8)
2008 /* Calculate the maximum primary/sprite plane watermark */
2009 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
2011 const struct intel_wm_config
*config
,
2012 enum intel_ddb_partitioning ddb_partitioning
,
2015 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2016 unsigned int fifo_size
= ilk_display_fifo_size(dev_priv
);
2018 /* if sprites aren't enabled, sprites get nothing */
2019 if (is_sprite
&& !config
->sprites_enabled
)
2022 /* HSW allows LP1+ watermarks even with multiple pipes */
2023 if (level
== 0 || config
->num_pipes_active
> 1) {
2024 fifo_size
/= INTEL_INFO(dev_priv
)->num_pipes
;
2027 * For some reason the non self refresh
2028 * FIFO size is only half of the self
2029 * refresh FIFO size on ILK/SNB.
2031 if (INTEL_GEN(dev_priv
) <= 6)
2035 if (config
->sprites_enabled
) {
2036 /* level 0 is always calculated with 1:1 split */
2037 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
2046 /* clamp to max that the registers can hold */
2047 return min(fifo_size
, ilk_plane_wm_reg_max(dev_priv
, level
, is_sprite
));
2050 /* Calculate the maximum cursor plane watermark */
2051 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
2053 const struct intel_wm_config
*config
)
2055 /* HSW LP1+ watermarks w/ multiple pipes */
2056 if (level
> 0 && config
->num_pipes_active
> 1)
2059 /* otherwise just report max that registers can hold */
2060 return ilk_cursor_wm_reg_max(to_i915(dev
), level
);
2063 static void ilk_compute_wm_maximums(const struct drm_device
*dev
,
2065 const struct intel_wm_config
*config
,
2066 enum intel_ddb_partitioning ddb_partitioning
,
2067 struct ilk_wm_maximums
*max
)
2069 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
2070 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
2071 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
2072 max
->fbc
= ilk_fbc_wm_reg_max(to_i915(dev
));
2075 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private
*dev_priv
,
2077 struct ilk_wm_maximums
*max
)
2079 max
->pri
= ilk_plane_wm_reg_max(dev_priv
, level
, false);
2080 max
->spr
= ilk_plane_wm_reg_max(dev_priv
, level
, true);
2081 max
->cur
= ilk_cursor_wm_reg_max(dev_priv
, level
);
2082 max
->fbc
= ilk_fbc_wm_reg_max(dev_priv
);
2085 static bool ilk_validate_wm_level(int level
,
2086 const struct ilk_wm_maximums
*max
,
2087 struct intel_wm_level
*result
)
2091 /* already determined to be invalid? */
2092 if (!result
->enable
)
2095 result
->enable
= result
->pri_val
<= max
->pri
&&
2096 result
->spr_val
<= max
->spr
&&
2097 result
->cur_val
<= max
->cur
;
2099 ret
= result
->enable
;
2102 * HACK until we can pre-compute everything,
2103 * and thus fail gracefully if LP0 watermarks
2106 if (level
== 0 && !result
->enable
) {
2107 if (result
->pri_val
> max
->pri
)
2108 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2109 level
, result
->pri_val
, max
->pri
);
2110 if (result
->spr_val
> max
->spr
)
2111 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2112 level
, result
->spr_val
, max
->spr
);
2113 if (result
->cur_val
> max
->cur
)
2114 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2115 level
, result
->cur_val
, max
->cur
);
2117 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
2118 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
2119 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
2120 result
->enable
= true;
2126 static void ilk_compute_wm_level(const struct drm_i915_private
*dev_priv
,
2127 const struct intel_crtc
*intel_crtc
,
2129 struct intel_crtc_state
*cstate
,
2130 struct intel_plane_state
*pristate
,
2131 struct intel_plane_state
*sprstate
,
2132 struct intel_plane_state
*curstate
,
2133 struct intel_wm_level
*result
)
2135 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
2136 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
2137 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
2139 /* WM1+ latency values stored in 0.5us units */
2147 result
->pri_val
= ilk_compute_pri_wm(cstate
, pristate
,
2148 pri_latency
, level
);
2149 result
->fbc_val
= ilk_compute_fbc_wm(cstate
, pristate
, result
->pri_val
);
2153 result
->spr_val
= ilk_compute_spr_wm(cstate
, sprstate
, spr_latency
);
2156 result
->cur_val
= ilk_compute_cur_wm(cstate
, curstate
, cur_latency
);
2158 result
->enable
= true;
2162 hsw_compute_linetime_wm(const struct intel_crtc_state
*cstate
)
2164 const struct intel_atomic_state
*intel_state
=
2165 to_intel_atomic_state(cstate
->base
.state
);
2166 const struct drm_display_mode
*adjusted_mode
=
2167 &cstate
->base
.adjusted_mode
;
2168 u32 linetime
, ips_linetime
;
2170 if (!cstate
->base
.active
)
2172 if (WARN_ON(adjusted_mode
->crtc_clock
== 0))
2174 if (WARN_ON(intel_state
->cdclk
.logical
.cdclk
== 0))
2177 /* The WM are computed with base on how long it takes to fill a single
2178 * row at the given clock rate, multiplied by 8.
2180 linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2181 adjusted_mode
->crtc_clock
);
2182 ips_linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2183 intel_state
->cdclk
.logical
.cdclk
);
2185 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2186 PIPE_WM_LINETIME_TIME(linetime
);
2189 static void intel_read_wm_latency(struct drm_i915_private
*dev_priv
,
2192 if (IS_GEN9(dev_priv
)) {
2195 int level
, max_level
= ilk_wm_max_level(dev_priv
);
2197 /* read the first set of memory latencies[0:3] */
2198 val
= 0; /* data0 to be programmed to 0 for first set */
2199 mutex_lock(&dev_priv
->rps
.hw_lock
);
2200 ret
= sandybridge_pcode_read(dev_priv
,
2201 GEN9_PCODE_READ_MEM_LATENCY
,
2203 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2206 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2210 wm
[0] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2211 wm
[1] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2212 GEN9_MEM_LATENCY_LEVEL_MASK
;
2213 wm
[2] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2214 GEN9_MEM_LATENCY_LEVEL_MASK
;
2215 wm
[3] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2216 GEN9_MEM_LATENCY_LEVEL_MASK
;
2218 /* read the second set of memory latencies[4:7] */
2219 val
= 1; /* data0 to be programmed to 1 for second set */
2220 mutex_lock(&dev_priv
->rps
.hw_lock
);
2221 ret
= sandybridge_pcode_read(dev_priv
,
2222 GEN9_PCODE_READ_MEM_LATENCY
,
2224 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2226 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2230 wm
[4] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2231 wm
[5] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2232 GEN9_MEM_LATENCY_LEVEL_MASK
;
2233 wm
[6] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2234 GEN9_MEM_LATENCY_LEVEL_MASK
;
2235 wm
[7] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2236 GEN9_MEM_LATENCY_LEVEL_MASK
;
2239 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2240 * need to be disabled. We make sure to sanitize the values out
2241 * of the punit to satisfy this requirement.
2243 for (level
= 1; level
<= max_level
; level
++) {
2244 if (wm
[level
] == 0) {
2245 for (i
= level
+ 1; i
<= max_level
; i
++)
2252 * WaWmMemoryReadLatency:skl,glk
2254 * punit doesn't take into account the read latency so we need
2255 * to add 2us to the various latency levels we retrieve from the
2256 * punit when level 0 response data us 0us.
2260 for (level
= 1; level
<= max_level
; level
++) {
2267 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2268 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2270 wm
[0] = (sskpd
>> 56) & 0xFF;
2272 wm
[0] = sskpd
& 0xF;
2273 wm
[1] = (sskpd
>> 4) & 0xFF;
2274 wm
[2] = (sskpd
>> 12) & 0xFF;
2275 wm
[3] = (sskpd
>> 20) & 0x1FF;
2276 wm
[4] = (sskpd
>> 32) & 0x1FF;
2277 } else if (INTEL_GEN(dev_priv
) >= 6) {
2278 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
2280 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
2281 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
2282 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
2283 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
2284 } else if (INTEL_GEN(dev_priv
) >= 5) {
2285 uint32_t mltr
= I915_READ(MLTR_ILK
);
2287 /* ILK primary LP0 latency is 700 ns */
2289 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
2290 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
2294 static void intel_fixup_spr_wm_latency(struct drm_i915_private
*dev_priv
,
2297 /* ILK sprite LP0 latency is 1300 ns */
2298 if (IS_GEN5(dev_priv
))
2302 static void intel_fixup_cur_wm_latency(struct drm_i915_private
*dev_priv
,
2305 /* ILK cursor LP0 latency is 1300 ns */
2306 if (IS_GEN5(dev_priv
))
2309 /* WaDoubleCursorLP3Latency:ivb */
2310 if (IS_IVYBRIDGE(dev_priv
))
2314 int ilk_wm_max_level(const struct drm_i915_private
*dev_priv
)
2316 /* how many WM levels are we expecting */
2317 if (INTEL_GEN(dev_priv
) >= 9)
2319 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
2321 else if (INTEL_GEN(dev_priv
) >= 6)
2327 static void intel_print_wm_latency(struct drm_i915_private
*dev_priv
,
2329 const uint16_t wm
[8])
2331 int level
, max_level
= ilk_wm_max_level(dev_priv
);
2333 for (level
= 0; level
<= max_level
; level
++) {
2334 unsigned int latency
= wm
[level
];
2337 DRM_ERROR("%s WM%d latency not provided\n",
2343 * - latencies are in us on gen9.
2344 * - before then, WM1+ latency values are in 0.5us units
2346 if (IS_GEN9(dev_priv
))
2351 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2352 name
, level
, wm
[level
],
2353 latency
/ 10, latency
% 10);
2357 static bool ilk_increase_wm_latency(struct drm_i915_private
*dev_priv
,
2358 uint16_t wm
[5], uint16_t min
)
2360 int level
, max_level
= ilk_wm_max_level(dev_priv
);
2365 wm
[0] = max(wm
[0], min
);
2366 for (level
= 1; level
<= max_level
; level
++)
2367 wm
[level
] = max_t(uint16_t, wm
[level
], DIV_ROUND_UP(min
, 5));
2372 static void snb_wm_latency_quirk(struct drm_i915_private
*dev_priv
)
2377 * The BIOS provided WM memory latency values are often
2378 * inadequate for high resolution displays. Adjust them.
2380 changed
= ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
, 12) |
2381 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
, 12) |
2382 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
, 12);
2387 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2388 intel_print_wm_latency(dev_priv
, "Primary", dev_priv
->wm
.pri_latency
);
2389 intel_print_wm_latency(dev_priv
, "Sprite", dev_priv
->wm
.spr_latency
);
2390 intel_print_wm_latency(dev_priv
, "Cursor", dev_priv
->wm
.cur_latency
);
2393 static void ilk_setup_wm_latency(struct drm_i915_private
*dev_priv
)
2395 intel_read_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
);
2397 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
2398 sizeof(dev_priv
->wm
.pri_latency
));
2399 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
2400 sizeof(dev_priv
->wm
.pri_latency
));
2402 intel_fixup_spr_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
);
2403 intel_fixup_cur_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
);
2405 intel_print_wm_latency(dev_priv
, "Primary", dev_priv
->wm
.pri_latency
);
2406 intel_print_wm_latency(dev_priv
, "Sprite", dev_priv
->wm
.spr_latency
);
2407 intel_print_wm_latency(dev_priv
, "Cursor", dev_priv
->wm
.cur_latency
);
2409 if (IS_GEN6(dev_priv
))
2410 snb_wm_latency_quirk(dev_priv
);
2413 static void skl_setup_wm_latency(struct drm_i915_private
*dev_priv
)
2415 intel_read_wm_latency(dev_priv
, dev_priv
->wm
.skl_latency
);
2416 intel_print_wm_latency(dev_priv
, "Gen9 Plane", dev_priv
->wm
.skl_latency
);
2419 static bool ilk_validate_pipe_wm(struct drm_device
*dev
,
2420 struct intel_pipe_wm
*pipe_wm
)
2422 /* LP0 watermark maximums depend on this pipe alone */
2423 const struct intel_wm_config config
= {
2424 .num_pipes_active
= 1,
2425 .sprites_enabled
= pipe_wm
->sprites_enabled
,
2426 .sprites_scaled
= pipe_wm
->sprites_scaled
,
2428 struct ilk_wm_maximums max
;
2430 /* LP0 watermarks always use 1/2 DDB partitioning */
2431 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
2433 /* At least LP0 must be valid */
2434 if (!ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0])) {
2435 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2442 /* Compute new watermarks for the pipe */
2443 static int ilk_compute_pipe_wm(struct intel_crtc_state
*cstate
)
2445 struct drm_atomic_state
*state
= cstate
->base
.state
;
2446 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
2447 struct intel_pipe_wm
*pipe_wm
;
2448 struct drm_device
*dev
= state
->dev
;
2449 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
2450 struct intel_plane
*intel_plane
;
2451 struct intel_plane_state
*pristate
= NULL
;
2452 struct intel_plane_state
*sprstate
= NULL
;
2453 struct intel_plane_state
*curstate
= NULL
;
2454 int level
, max_level
= ilk_wm_max_level(dev_priv
), usable_level
;
2455 struct ilk_wm_maximums max
;
2457 pipe_wm
= &cstate
->wm
.ilk
.optimal
;
2459 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
2460 struct intel_plane_state
*ps
;
2462 ps
= intel_atomic_get_existing_plane_state(state
,
2467 if (intel_plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
2469 else if (intel_plane
->base
.type
== DRM_PLANE_TYPE_OVERLAY
)
2471 else if (intel_plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
2475 pipe_wm
->pipe_enabled
= cstate
->base
.active
;
2477 pipe_wm
->sprites_enabled
= sprstate
->base
.visible
;
2478 pipe_wm
->sprites_scaled
= sprstate
->base
.visible
&&
2479 (drm_rect_width(&sprstate
->base
.dst
) != drm_rect_width(&sprstate
->base
.src
) >> 16 ||
2480 drm_rect_height(&sprstate
->base
.dst
) != drm_rect_height(&sprstate
->base
.src
) >> 16);
2483 usable_level
= max_level
;
2485 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2486 if (INTEL_GEN(dev_priv
) <= 6 && pipe_wm
->sprites_enabled
)
2489 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2490 if (pipe_wm
->sprites_scaled
)
2493 ilk_compute_wm_level(dev_priv
, intel_crtc
, 0, cstate
,
2494 pristate
, sprstate
, curstate
, &pipe_wm
->raw_wm
[0]);
2496 memset(&pipe_wm
->wm
, 0, sizeof(pipe_wm
->wm
));
2497 pipe_wm
->wm
[0] = pipe_wm
->raw_wm
[0];
2499 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
2500 pipe_wm
->linetime
= hsw_compute_linetime_wm(cstate
);
2502 if (!ilk_validate_pipe_wm(dev
, pipe_wm
))
2505 ilk_compute_wm_reg_maximums(dev_priv
, 1, &max
);
2507 for (level
= 1; level
<= max_level
; level
++) {
2508 struct intel_wm_level
*wm
= &pipe_wm
->raw_wm
[level
];
2510 ilk_compute_wm_level(dev_priv
, intel_crtc
, level
, cstate
,
2511 pristate
, sprstate
, curstate
, wm
);
2514 * Disable any watermark level that exceeds the
2515 * register maximums since such watermarks are
2518 if (level
> usable_level
)
2521 if (ilk_validate_wm_level(level
, &max
, wm
))
2522 pipe_wm
->wm
[level
] = *wm
;
2524 usable_level
= level
;
2531 * Build a set of 'intermediate' watermark values that satisfy both the old
2532 * state and the new state. These can be programmed to the hardware
2535 static int ilk_compute_intermediate_wm(struct drm_device
*dev
,
2536 struct intel_crtc
*intel_crtc
,
2537 struct intel_crtc_state
*newstate
)
2539 struct intel_pipe_wm
*a
= &newstate
->wm
.ilk
.intermediate
;
2540 struct intel_pipe_wm
*b
= &intel_crtc
->wm
.active
.ilk
;
2541 int level
, max_level
= ilk_wm_max_level(to_i915(dev
));
2544 * Start with the final, target watermarks, then combine with the
2545 * currently active watermarks to get values that are safe both before
2546 * and after the vblank.
2548 *a
= newstate
->wm
.ilk
.optimal
;
2549 a
->pipe_enabled
|= b
->pipe_enabled
;
2550 a
->sprites_enabled
|= b
->sprites_enabled
;
2551 a
->sprites_scaled
|= b
->sprites_scaled
;
2553 for (level
= 0; level
<= max_level
; level
++) {
2554 struct intel_wm_level
*a_wm
= &a
->wm
[level
];
2555 const struct intel_wm_level
*b_wm
= &b
->wm
[level
];
2557 a_wm
->enable
&= b_wm
->enable
;
2558 a_wm
->pri_val
= max(a_wm
->pri_val
, b_wm
->pri_val
);
2559 a_wm
->spr_val
= max(a_wm
->spr_val
, b_wm
->spr_val
);
2560 a_wm
->cur_val
= max(a_wm
->cur_val
, b_wm
->cur_val
);
2561 a_wm
->fbc_val
= max(a_wm
->fbc_val
, b_wm
->fbc_val
);
2565 * We need to make sure that these merged watermark values are
2566 * actually a valid configuration themselves. If they're not,
2567 * there's no safe way to transition from the old state to
2568 * the new state, so we need to fail the atomic transaction.
2570 if (!ilk_validate_pipe_wm(dev
, a
))
2574 * If our intermediate WM are identical to the final WM, then we can
2575 * omit the post-vblank programming; only update if it's different.
2577 if (memcmp(a
, &newstate
->wm
.ilk
.optimal
, sizeof(*a
)) == 0)
2578 newstate
->wm
.need_postvbl_update
= false;
2584 * Merge the watermarks from all active pipes for a specific level.
2586 static void ilk_merge_wm_level(struct drm_device
*dev
,
2588 struct intel_wm_level
*ret_wm
)
2590 const struct intel_crtc
*intel_crtc
;
2592 ret_wm
->enable
= true;
2594 for_each_intel_crtc(dev
, intel_crtc
) {
2595 const struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
.ilk
;
2596 const struct intel_wm_level
*wm
= &active
->wm
[level
];
2598 if (!active
->pipe_enabled
)
2602 * The watermark values may have been used in the past,
2603 * so we must maintain them in the registers for some
2604 * time even if the level is now disabled.
2607 ret_wm
->enable
= false;
2609 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
2610 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
2611 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
2612 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
2617 * Merge all low power watermarks for all active pipes.
2619 static void ilk_wm_merge(struct drm_device
*dev
,
2620 const struct intel_wm_config
*config
,
2621 const struct ilk_wm_maximums
*max
,
2622 struct intel_pipe_wm
*merged
)
2624 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2625 int level
, max_level
= ilk_wm_max_level(dev_priv
);
2626 int last_enabled_level
= max_level
;
2628 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2629 if ((INTEL_GEN(dev_priv
) <= 6 || IS_IVYBRIDGE(dev_priv
)) &&
2630 config
->num_pipes_active
> 1)
2631 last_enabled_level
= 0;
2633 /* ILK: FBC WM must be disabled always */
2634 merged
->fbc_wm_enabled
= INTEL_GEN(dev_priv
) >= 6;
2636 /* merge each WM1+ level */
2637 for (level
= 1; level
<= max_level
; level
++) {
2638 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2640 ilk_merge_wm_level(dev
, level
, wm
);
2642 if (level
> last_enabled_level
)
2644 else if (!ilk_validate_wm_level(level
, max
, wm
))
2645 /* make sure all following levels get disabled */
2646 last_enabled_level
= level
- 1;
2649 * The spec says it is preferred to disable
2650 * FBC WMs instead of disabling a WM level.
2652 if (wm
->fbc_val
> max
->fbc
) {
2654 merged
->fbc_wm_enabled
= false;
2659 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2661 * FIXME this is racy. FBC might get enabled later.
2662 * What we should check here is whether FBC can be
2663 * enabled sometime later.
2665 if (IS_GEN5(dev_priv
) && !merged
->fbc_wm_enabled
&&
2666 intel_fbc_is_active(dev_priv
)) {
2667 for (level
= 2; level
<= max_level
; level
++) {
2668 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2675 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
2677 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2678 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
2681 /* The value we need to program into the WM_LPx latency field */
2682 static unsigned int ilk_wm_lp_latency(struct drm_device
*dev
, int level
)
2684 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2686 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
2689 return dev_priv
->wm
.pri_latency
[level
];
2692 static void ilk_compute_wm_results(struct drm_device
*dev
,
2693 const struct intel_pipe_wm
*merged
,
2694 enum intel_ddb_partitioning partitioning
,
2695 struct ilk_wm_values
*results
)
2697 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2698 struct intel_crtc
*intel_crtc
;
2701 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
2702 results
->partitioning
= partitioning
;
2704 /* LP1+ register values */
2705 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2706 const struct intel_wm_level
*r
;
2708 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
2710 r
= &merged
->wm
[level
];
2713 * Maintain the watermark values even if the level is
2714 * disabled. Doing otherwise could cause underruns.
2716 results
->wm_lp
[wm_lp
- 1] =
2717 (ilk_wm_lp_latency(dev
, level
) << WM1_LP_LATENCY_SHIFT
) |
2718 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
2722 results
->wm_lp
[wm_lp
- 1] |= WM1_LP_SR_EN
;
2724 if (INTEL_GEN(dev_priv
) >= 8)
2725 results
->wm_lp
[wm_lp
- 1] |=
2726 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
2728 results
->wm_lp
[wm_lp
- 1] |=
2729 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
2732 * Always set WM1S_LP_EN when spr_val != 0, even if the
2733 * level is disabled. Doing otherwise could cause underruns.
2735 if (INTEL_GEN(dev_priv
) <= 6 && r
->spr_val
) {
2736 WARN_ON(wm_lp
!= 1);
2737 results
->wm_lp_spr
[wm_lp
- 1] = WM1S_LP_EN
| r
->spr_val
;
2739 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
2742 /* LP0 register values */
2743 for_each_intel_crtc(dev
, intel_crtc
) {
2744 enum pipe pipe
= intel_crtc
->pipe
;
2745 const struct intel_wm_level
*r
=
2746 &intel_crtc
->wm
.active
.ilk
.wm
[0];
2748 if (WARN_ON(!r
->enable
))
2751 results
->wm_linetime
[pipe
] = intel_crtc
->wm
.active
.ilk
.linetime
;
2753 results
->wm_pipe
[pipe
] =
2754 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
2755 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
2760 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2761 * case both are at the same level. Prefer r1 in case they're the same. */
2762 static struct intel_pipe_wm
*ilk_find_best_result(struct drm_device
*dev
,
2763 struct intel_pipe_wm
*r1
,
2764 struct intel_pipe_wm
*r2
)
2766 int level
, max_level
= ilk_wm_max_level(to_i915(dev
));
2767 int level1
= 0, level2
= 0;
2769 for (level
= 1; level
<= max_level
; level
++) {
2770 if (r1
->wm
[level
].enable
)
2772 if (r2
->wm
[level
].enable
)
2776 if (level1
== level2
) {
2777 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
2781 } else if (level1
> level2
) {
2788 /* dirty bits used to track which watermarks need changes */
2789 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2790 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2791 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2792 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2793 #define WM_DIRTY_FBC (1 << 24)
2794 #define WM_DIRTY_DDB (1 << 25)
2796 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private
*dev_priv
,
2797 const struct ilk_wm_values
*old
,
2798 const struct ilk_wm_values
*new)
2800 unsigned int dirty
= 0;
2804 for_each_pipe(dev_priv
, pipe
) {
2805 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
2806 dirty
|= WM_DIRTY_LINETIME(pipe
);
2807 /* Must disable LP1+ watermarks too */
2808 dirty
|= WM_DIRTY_LP_ALL
;
2811 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
2812 dirty
|= WM_DIRTY_PIPE(pipe
);
2813 /* Must disable LP1+ watermarks too */
2814 dirty
|= WM_DIRTY_LP_ALL
;
2818 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
2819 dirty
|= WM_DIRTY_FBC
;
2820 /* Must disable LP1+ watermarks too */
2821 dirty
|= WM_DIRTY_LP_ALL
;
2824 if (old
->partitioning
!= new->partitioning
) {
2825 dirty
|= WM_DIRTY_DDB
;
2826 /* Must disable LP1+ watermarks too */
2827 dirty
|= WM_DIRTY_LP_ALL
;
2830 /* LP1+ watermarks already deemed dirty, no need to continue */
2831 if (dirty
& WM_DIRTY_LP_ALL
)
2834 /* Find the lowest numbered LP1+ watermark in need of an update... */
2835 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2836 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
2837 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
2841 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2842 for (; wm_lp
<= 3; wm_lp
++)
2843 dirty
|= WM_DIRTY_LP(wm_lp
);
2848 static bool _ilk_disable_lp_wm(struct drm_i915_private
*dev_priv
,
2851 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2852 bool changed
= false;
2854 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] & WM1_LP_SR_EN
) {
2855 previous
->wm_lp
[2] &= ~WM1_LP_SR_EN
;
2856 I915_WRITE(WM3_LP_ILK
, previous
->wm_lp
[2]);
2859 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] & WM1_LP_SR_EN
) {
2860 previous
->wm_lp
[1] &= ~WM1_LP_SR_EN
;
2861 I915_WRITE(WM2_LP_ILK
, previous
->wm_lp
[1]);
2864 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] & WM1_LP_SR_EN
) {
2865 previous
->wm_lp
[0] &= ~WM1_LP_SR_EN
;
2866 I915_WRITE(WM1_LP_ILK
, previous
->wm_lp
[0]);
2871 * Don't touch WM1S_LP_EN here.
2872 * Doing so could cause underruns.
2879 * The spec says we shouldn't write when we don't need, because every write
2880 * causes WMs to be re-evaluated, expending some power.
2882 static void ilk_write_wm_values(struct drm_i915_private
*dev_priv
,
2883 struct ilk_wm_values
*results
)
2885 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2889 dirty
= ilk_compute_wm_dirty(dev_priv
, previous
, results
);
2893 _ilk_disable_lp_wm(dev_priv
, dirty
);
2895 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
2896 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
2897 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
2898 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
2899 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
2900 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
2902 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
2903 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
2904 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
2905 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
2906 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
2907 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
2909 if (dirty
& WM_DIRTY_DDB
) {
2910 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2911 val
= I915_READ(WM_MISC
);
2912 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2913 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
2915 val
|= WM_MISC_DATA_PARTITION_5_6
;
2916 I915_WRITE(WM_MISC
, val
);
2918 val
= I915_READ(DISP_ARB_CTL2
);
2919 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2920 val
&= ~DISP_DATA_PARTITION_5_6
;
2922 val
|= DISP_DATA_PARTITION_5_6
;
2923 I915_WRITE(DISP_ARB_CTL2
, val
);
2927 if (dirty
& WM_DIRTY_FBC
) {
2928 val
= I915_READ(DISP_ARB_CTL
);
2929 if (results
->enable_fbc_wm
)
2930 val
&= ~DISP_FBC_WM_DIS
;
2932 val
|= DISP_FBC_WM_DIS
;
2933 I915_WRITE(DISP_ARB_CTL
, val
);
2936 if (dirty
& WM_DIRTY_LP(1) &&
2937 previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
2938 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
2940 if (INTEL_GEN(dev_priv
) >= 7) {
2941 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
2942 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
2943 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
2944 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
2947 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != results
->wm_lp
[0])
2948 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
2949 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != results
->wm_lp
[1])
2950 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
2951 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != results
->wm_lp
[2])
2952 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
2954 dev_priv
->wm
.hw
= *results
;
2957 bool ilk_disable_lp_wm(struct drm_device
*dev
)
2959 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2961 return _ilk_disable_lp_wm(dev_priv
, WM_DIRTY_LP_ALL
);
2964 #define SKL_SAGV_BLOCK_TIME 30 /* µs */
2967 * FIXME: We still don't have the proper code detect if we need to apply the WA,
2968 * so assume we'll always need it in order to avoid underruns.
2970 static bool skl_needs_memory_bw_wa(struct intel_atomic_state
*state
)
2972 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
2974 if (IS_GEN9_BC(dev_priv
) || IS_BROXTON(dev_priv
))
2981 intel_has_sagv(struct drm_i915_private
*dev_priv
)
2983 if (IS_KABYLAKE(dev_priv
))
2986 if (IS_SKYLAKE(dev_priv
) &&
2987 dev_priv
->sagv_status
!= I915_SAGV_NOT_CONTROLLED
)
2994 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2995 * depending on power and performance requirements. The display engine access
2996 * to system memory is blocked during the adjustment time. Because of the
2997 * blocking time, having this enabled can cause full system hangs and/or pipe
2998 * underruns if we don't meet all of the following requirements:
3000 * - <= 1 pipe enabled
3001 * - All planes can enable watermarks for latencies >= SAGV engine block time
3002 * - We're not using an interlaced display configuration
3005 intel_enable_sagv(struct drm_i915_private
*dev_priv
)
3009 if (!intel_has_sagv(dev_priv
))
3012 if (dev_priv
->sagv_status
== I915_SAGV_ENABLED
)
3015 DRM_DEBUG_KMS("Enabling the SAGV\n");
3016 mutex_lock(&dev_priv
->rps
.hw_lock
);
3018 ret
= sandybridge_pcode_write(dev_priv
, GEN9_PCODE_SAGV_CONTROL
,
3021 /* We don't need to wait for the SAGV when enabling */
3022 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3025 * Some skl systems, pre-release machines in particular,
3026 * don't actually have an SAGV.
3028 if (IS_SKYLAKE(dev_priv
) && ret
== -ENXIO
) {
3029 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3030 dev_priv
->sagv_status
= I915_SAGV_NOT_CONTROLLED
;
3032 } else if (ret
< 0) {
3033 DRM_ERROR("Failed to enable the SAGV\n");
3037 dev_priv
->sagv_status
= I915_SAGV_ENABLED
;
3042 intel_disable_sagv(struct drm_i915_private
*dev_priv
)
3046 if (!intel_has_sagv(dev_priv
))
3049 if (dev_priv
->sagv_status
== I915_SAGV_DISABLED
)
3052 DRM_DEBUG_KMS("Disabling the SAGV\n");
3053 mutex_lock(&dev_priv
->rps
.hw_lock
);
3055 /* bspec says to keep retrying for at least 1 ms */
3056 ret
= skl_pcode_request(dev_priv
, GEN9_PCODE_SAGV_CONTROL
,
3058 GEN9_SAGV_IS_DISABLED
, GEN9_SAGV_IS_DISABLED
,
3060 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3063 * Some skl systems, pre-release machines in particular,
3064 * don't actually have an SAGV.
3066 if (IS_SKYLAKE(dev_priv
) && ret
== -ENXIO
) {
3067 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3068 dev_priv
->sagv_status
= I915_SAGV_NOT_CONTROLLED
;
3070 } else if (ret
< 0) {
3071 DRM_ERROR("Failed to disable the SAGV (%d)\n", ret
);
3075 dev_priv
->sagv_status
= I915_SAGV_DISABLED
;
3079 bool intel_can_enable_sagv(struct drm_atomic_state
*state
)
3081 struct drm_device
*dev
= state
->dev
;
3082 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3083 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
3084 struct intel_crtc
*crtc
;
3085 struct intel_plane
*plane
;
3086 struct intel_crtc_state
*cstate
;
3090 if (!intel_has_sagv(dev_priv
))
3094 * SKL workaround: bspec recommends we disable the SAGV when we have
3095 * more then one pipe enabled
3097 * If there are no active CRTCs, no additional checks need be performed
3099 if (hweight32(intel_state
->active_crtcs
) == 0)
3101 else if (hweight32(intel_state
->active_crtcs
) > 1)
3104 /* Since we're now guaranteed to only have one active CRTC... */
3105 pipe
= ffs(intel_state
->active_crtcs
) - 1;
3106 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
3107 cstate
= to_intel_crtc_state(crtc
->base
.state
);
3109 if (crtc
->base
.state
->adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
3112 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
3113 struct skl_plane_wm
*wm
=
3114 &cstate
->wm
.skl
.optimal
.planes
[plane
->id
];
3116 /* Skip this plane if it's not enabled */
3117 if (!wm
->wm
[0].plane_en
)
3120 /* Find the highest enabled wm level for this plane */
3121 for (level
= ilk_wm_max_level(dev_priv
);
3122 !wm
->wm
[level
].plane_en
; --level
)
3125 latency
= dev_priv
->wm
.skl_latency
[level
];
3127 if (skl_needs_memory_bw_wa(intel_state
) &&
3128 plane
->base
.state
->fb
->modifier
==
3129 I915_FORMAT_MOD_X_TILED
)
3133 * If any of the planes on this pipe don't enable wm levels
3134 * that incur memory latencies higher then 30µs we can't enable
3137 if (latency
< SKL_SAGV_BLOCK_TIME
)
3145 skl_ddb_get_pipe_allocation_limits(struct drm_device
*dev
,
3146 const struct intel_crtc_state
*cstate
,
3147 struct skl_ddb_entry
*alloc
, /* out */
3148 int *num_active
/* out */)
3150 struct drm_atomic_state
*state
= cstate
->base
.state
;
3151 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
3152 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3153 struct drm_crtc
*for_crtc
= cstate
->base
.crtc
;
3154 unsigned int pipe_size
, ddb_size
;
3155 int nth_active_pipe
;
3157 if (WARN_ON(!state
) || !cstate
->base
.active
) {
3160 *num_active
= hweight32(dev_priv
->active_crtcs
);
3164 if (intel_state
->active_pipe_changes
)
3165 *num_active
= hweight32(intel_state
->active_crtcs
);
3167 *num_active
= hweight32(dev_priv
->active_crtcs
);
3169 ddb_size
= INTEL_INFO(dev_priv
)->ddb_size
;
3170 WARN_ON(ddb_size
== 0);
3172 ddb_size
-= 4; /* 4 blocks for bypass path allocation */
3175 * If the state doesn't change the active CRTC's, then there's
3176 * no need to recalculate; the existing pipe allocation limits
3177 * should remain unchanged. Note that we're safe from racing
3178 * commits since any racing commit that changes the active CRTC
3179 * list would need to grab _all_ crtc locks, including the one
3180 * we currently hold.
3182 if (!intel_state
->active_pipe_changes
) {
3184 * alloc may be cleared by clear_intel_crtc_state,
3185 * copy from old state to be sure
3187 *alloc
= to_intel_crtc_state(for_crtc
->state
)->wm
.skl
.ddb
;
3191 nth_active_pipe
= hweight32(intel_state
->active_crtcs
&
3192 (drm_crtc_mask(for_crtc
) - 1));
3193 pipe_size
= ddb_size
/ hweight32(intel_state
->active_crtcs
);
3194 alloc
->start
= nth_active_pipe
* ddb_size
/ *num_active
;
3195 alloc
->end
= alloc
->start
+ pipe_size
;
3198 static unsigned int skl_cursor_allocation(int num_active
)
3200 if (num_active
== 1)
3206 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry
*entry
, u32 reg
)
3208 entry
->start
= reg
& 0x3ff;
3209 entry
->end
= (reg
>> 16) & 0x3ff;
3214 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
3215 struct skl_ddb_allocation
*ddb
/* out */)
3217 struct intel_crtc
*crtc
;
3219 memset(ddb
, 0, sizeof(*ddb
));
3221 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
3222 enum intel_display_power_domain power_domain
;
3223 enum plane_id plane_id
;
3224 enum pipe pipe
= crtc
->pipe
;
3226 power_domain
= POWER_DOMAIN_PIPE(pipe
);
3227 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
3230 for_each_plane_id_on_crtc(crtc
, plane_id
) {
3233 if (plane_id
!= PLANE_CURSOR
)
3234 val
= I915_READ(PLANE_BUF_CFG(pipe
, plane_id
));
3236 val
= I915_READ(CUR_BUF_CFG(pipe
));
3238 skl_ddb_entry_init_from_hw(&ddb
->plane
[pipe
][plane_id
], val
);
3241 intel_display_power_put(dev_priv
, power_domain
);
3246 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3247 * The bspec defines downscale amount as:
3250 * Horizontal down scale amount = maximum[1, Horizontal source size /
3251 * Horizontal destination size]
3252 * Vertical down scale amount = maximum[1, Vertical source size /
3253 * Vertical destination size]
3254 * Total down scale amount = Horizontal down scale amount *
3255 * Vertical down scale amount
3258 * Return value is provided in 16.16 fixed point form to retain fractional part.
3259 * Caller should take care of dividing & rounding off the value.
3262 skl_plane_downscale_amount(const struct intel_plane_state
*pstate
)
3264 uint32_t downscale_h
, downscale_w
;
3265 uint32_t src_w
, src_h
, dst_w
, dst_h
;
3267 if (WARN_ON(!pstate
->base
.visible
))
3268 return DRM_PLANE_HELPER_NO_SCALING
;
3270 /* n.b., src is 16.16 fixed point, dst is whole integer */
3271 src_w
= drm_rect_width(&pstate
->base
.src
);
3272 src_h
= drm_rect_height(&pstate
->base
.src
);
3273 dst_w
= drm_rect_width(&pstate
->base
.dst
);
3274 dst_h
= drm_rect_height(&pstate
->base
.dst
);
3275 if (drm_rotation_90_or_270(pstate
->base
.rotation
))
3278 downscale_h
= max(src_h
/ dst_h
, (uint32_t)DRM_PLANE_HELPER_NO_SCALING
);
3279 downscale_w
= max(src_w
/ dst_w
, (uint32_t)DRM_PLANE_HELPER_NO_SCALING
);
3281 /* Provide result in 16.16 fixed point */
3282 return (uint64_t)downscale_w
* downscale_h
>> 16;
3286 skl_plane_relative_data_rate(const struct intel_crtc_state
*cstate
,
3287 const struct drm_plane_state
*pstate
,
3290 struct intel_plane_state
*intel_pstate
= to_intel_plane_state(pstate
);
3291 uint32_t down_scale_amount
, data_rate
;
3292 uint32_t width
= 0, height
= 0;
3293 struct drm_framebuffer
*fb
;
3296 if (!intel_pstate
->base
.visible
)
3300 format
= fb
->format
->format
;
3302 if (pstate
->plane
->type
== DRM_PLANE_TYPE_CURSOR
)
3304 if (y
&& format
!= DRM_FORMAT_NV12
)
3307 width
= drm_rect_width(&intel_pstate
->base
.src
) >> 16;
3308 height
= drm_rect_height(&intel_pstate
->base
.src
) >> 16;
3310 if (drm_rotation_90_or_270(pstate
->rotation
))
3311 swap(width
, height
);
3313 /* for planar format */
3314 if (format
== DRM_FORMAT_NV12
) {
3315 if (y
) /* y-plane data rate */
3316 data_rate
= width
* height
*
3318 else /* uv-plane data rate */
3319 data_rate
= (width
/ 2) * (height
/ 2) *
3322 /* for packed formats */
3323 data_rate
= width
* height
* fb
->format
->cpp
[0];
3326 down_scale_amount
= skl_plane_downscale_amount(intel_pstate
);
3328 return (uint64_t)data_rate
* down_scale_amount
>> 16;
3332 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3333 * a 8192x4096@32bpp framebuffer:
3334 * 3 * 4096 * 8192 * 4 < 2^32
3337 skl_get_total_relative_data_rate(struct intel_crtc_state
*intel_cstate
,
3338 unsigned *plane_data_rate
,
3339 unsigned *plane_y_data_rate
)
3341 struct drm_crtc_state
*cstate
= &intel_cstate
->base
;
3342 struct drm_atomic_state
*state
= cstate
->state
;
3343 struct drm_plane
*plane
;
3344 const struct drm_plane_state
*pstate
;
3345 unsigned int total_data_rate
= 0;
3347 if (WARN_ON(!state
))
3350 /* Calculate and cache data rate for each plane */
3351 drm_atomic_crtc_state_for_each_plane_state(plane
, pstate
, cstate
) {
3352 enum plane_id plane_id
= to_intel_plane(plane
)->id
;
3356 rate
= skl_plane_relative_data_rate(intel_cstate
,
3358 plane_data_rate
[plane_id
] = rate
;
3360 total_data_rate
+= rate
;
3363 rate
= skl_plane_relative_data_rate(intel_cstate
,
3365 plane_y_data_rate
[plane_id
] = rate
;
3367 total_data_rate
+= rate
;
3370 return total_data_rate
;
3374 skl_ddb_min_alloc(const struct drm_plane_state
*pstate
,
3377 struct drm_framebuffer
*fb
= pstate
->fb
;
3378 struct intel_plane_state
*intel_pstate
= to_intel_plane_state(pstate
);
3379 uint32_t src_w
, src_h
;
3380 uint32_t min_scanlines
= 8;
3386 /* For packed formats, no y-plane, return 0 */
3387 if (y
&& fb
->format
->format
!= DRM_FORMAT_NV12
)
3390 /* For Non Y-tile return 8-blocks */
3391 if (fb
->modifier
!= I915_FORMAT_MOD_Y_TILED
&&
3392 fb
->modifier
!= I915_FORMAT_MOD_Yf_TILED
)
3395 src_w
= drm_rect_width(&intel_pstate
->base
.src
) >> 16;
3396 src_h
= drm_rect_height(&intel_pstate
->base
.src
) >> 16;
3398 if (drm_rotation_90_or_270(pstate
->rotation
))
3401 /* Halve UV plane width and height for NV12 */
3402 if (fb
->format
->format
== DRM_FORMAT_NV12
&& !y
) {
3407 if (fb
->format
->format
== DRM_FORMAT_NV12
&& !y
)
3408 plane_bpp
= fb
->format
->cpp
[1];
3410 plane_bpp
= fb
->format
->cpp
[0];
3412 if (drm_rotation_90_or_270(pstate
->rotation
)) {
3413 switch (plane_bpp
) {
3427 WARN(1, "Unsupported pixel depth %u for rotation",
3433 return DIV_ROUND_UP((4 * src_w
* plane_bpp
), 512) * min_scanlines
/4 + 3;
3437 skl_ddb_calc_min(const struct intel_crtc_state
*cstate
, int num_active
,
3438 uint16_t *minimum
, uint16_t *y_minimum
)
3440 const struct drm_plane_state
*pstate
;
3441 struct drm_plane
*plane
;
3443 drm_atomic_crtc_state_for_each_plane_state(plane
, pstate
, &cstate
->base
) {
3444 enum plane_id plane_id
= to_intel_plane(plane
)->id
;
3446 if (plane_id
== PLANE_CURSOR
)
3449 if (!pstate
->visible
)
3452 minimum
[plane_id
] = skl_ddb_min_alloc(pstate
, 0);
3453 y_minimum
[plane_id
] = skl_ddb_min_alloc(pstate
, 1);
3456 minimum
[PLANE_CURSOR
] = skl_cursor_allocation(num_active
);
3460 skl_allocate_pipe_ddb(struct intel_crtc_state
*cstate
,
3461 struct skl_ddb_allocation
*ddb
/* out */)
3463 struct drm_atomic_state
*state
= cstate
->base
.state
;
3464 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
3465 struct drm_device
*dev
= crtc
->dev
;
3466 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3467 enum pipe pipe
= intel_crtc
->pipe
;
3468 struct skl_ddb_entry
*alloc
= &cstate
->wm
.skl
.ddb
;
3469 uint16_t alloc_size
, start
;
3470 uint16_t minimum
[I915_MAX_PLANES
] = {};
3471 uint16_t y_minimum
[I915_MAX_PLANES
] = {};
3472 unsigned int total_data_rate
;
3473 enum plane_id plane_id
;
3475 unsigned plane_data_rate
[I915_MAX_PLANES
] = {};
3476 unsigned plane_y_data_rate
[I915_MAX_PLANES
] = {};
3478 /* Clear the partitioning for disabled planes. */
3479 memset(ddb
->plane
[pipe
], 0, sizeof(ddb
->plane
[pipe
]));
3480 memset(ddb
->y_plane
[pipe
], 0, sizeof(ddb
->y_plane
[pipe
]));
3482 if (WARN_ON(!state
))
3485 if (!cstate
->base
.active
) {
3486 alloc
->start
= alloc
->end
= 0;
3490 skl_ddb_get_pipe_allocation_limits(dev
, cstate
, alloc
, &num_active
);
3491 alloc_size
= skl_ddb_entry_size(alloc
);
3492 if (alloc_size
== 0) {
3493 memset(ddb
->plane
[pipe
], 0, sizeof(ddb
->plane
[pipe
]));
3497 skl_ddb_calc_min(cstate
, num_active
, minimum
, y_minimum
);
3500 * 1. Allocate the mininum required blocks for each active plane
3501 * and allocate the cursor, it doesn't require extra allocation
3502 * proportional to the data rate.
3505 for_each_plane_id_on_crtc(intel_crtc
, plane_id
) {
3506 alloc_size
-= minimum
[plane_id
];
3507 alloc_size
-= y_minimum
[plane_id
];
3510 ddb
->plane
[pipe
][PLANE_CURSOR
].start
= alloc
->end
- minimum
[PLANE_CURSOR
];
3511 ddb
->plane
[pipe
][PLANE_CURSOR
].end
= alloc
->end
;
3514 * 2. Distribute the remaining space in proportion to the amount of
3515 * data each plane needs to fetch from memory.
3517 * FIXME: we may not allocate every single block here.
3519 total_data_rate
= skl_get_total_relative_data_rate(cstate
,
3522 if (total_data_rate
== 0)
3525 start
= alloc
->start
;
3526 for_each_plane_id_on_crtc(intel_crtc
, plane_id
) {
3527 unsigned int data_rate
, y_data_rate
;
3528 uint16_t plane_blocks
, y_plane_blocks
= 0;
3530 if (plane_id
== PLANE_CURSOR
)
3533 data_rate
= plane_data_rate
[plane_id
];
3536 * allocation for (packed formats) or (uv-plane part of planar format):
3537 * promote the expression to 64 bits to avoid overflowing, the
3538 * result is < available as data_rate / total_data_rate < 1
3540 plane_blocks
= minimum
[plane_id
];
3541 plane_blocks
+= div_u64((uint64_t)alloc_size
* data_rate
,
3544 /* Leave disabled planes at (0,0) */
3546 ddb
->plane
[pipe
][plane_id
].start
= start
;
3547 ddb
->plane
[pipe
][plane_id
].end
= start
+ plane_blocks
;
3550 start
+= plane_blocks
;
3553 * allocation for y_plane part of planar format:
3555 y_data_rate
= plane_y_data_rate
[plane_id
];
3557 y_plane_blocks
= y_minimum
[plane_id
];
3558 y_plane_blocks
+= div_u64((uint64_t)alloc_size
* y_data_rate
,
3562 ddb
->y_plane
[pipe
][plane_id
].start
= start
;
3563 ddb
->y_plane
[pipe
][plane_id
].end
= start
+ y_plane_blocks
;
3566 start
+= y_plane_blocks
;
3573 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3574 * for the read latency) and cpp should always be <= 8, so that
3575 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3576 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3578 static uint_fixed_16_16_t
skl_wm_method1(uint32_t pixel_rate
, uint8_t cpp
,
3581 uint32_t wm_intermediate_val
;
3582 uint_fixed_16_16_t ret
;
3585 return FP_16_16_MAX
;
3587 wm_intermediate_val
= latency
* pixel_rate
* cpp
;
3588 ret
= fixed_16_16_div_round_up_u64(wm_intermediate_val
, 1000 * 512);
3592 static uint_fixed_16_16_t
skl_wm_method2(uint32_t pixel_rate
,
3593 uint32_t pipe_htotal
,
3595 uint_fixed_16_16_t plane_blocks_per_line
)
3597 uint32_t wm_intermediate_val
;
3598 uint_fixed_16_16_t ret
;
3601 return FP_16_16_MAX
;
3603 wm_intermediate_val
= latency
* pixel_rate
;
3604 wm_intermediate_val
= DIV_ROUND_UP(wm_intermediate_val
,
3605 pipe_htotal
* 1000);
3606 ret
= mul_u32_fixed_16_16(wm_intermediate_val
, plane_blocks_per_line
);
3610 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state
*cstate
,
3611 struct intel_plane_state
*pstate
)
3613 uint64_t adjusted_pixel_rate
;
3614 uint64_t downscale_amount
;
3615 uint64_t pixel_rate
;
3617 /* Shouldn't reach here on disabled planes... */
3618 if (WARN_ON(!pstate
->base
.visible
))
3622 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3623 * with additional adjustments for plane-specific scaling.
3625 adjusted_pixel_rate
= cstate
->pixel_rate
;
3626 downscale_amount
= skl_plane_downscale_amount(pstate
);
3628 pixel_rate
= adjusted_pixel_rate
* downscale_amount
>> 16;
3629 WARN_ON(pixel_rate
!= clamp_t(uint32_t, pixel_rate
, 0, ~0));
3634 static int skl_compute_plane_wm(const struct drm_i915_private
*dev_priv
,
3635 struct intel_crtc_state
*cstate
,
3636 struct intel_plane_state
*intel_pstate
,
3637 uint16_t ddb_allocation
,
3639 uint16_t *out_blocks
, /* out */
3640 uint8_t *out_lines
, /* out */
3641 bool *enabled
/* out */)
3643 struct drm_plane_state
*pstate
= &intel_pstate
->base
;
3644 struct drm_framebuffer
*fb
= pstate
->fb
;
3645 uint32_t latency
= dev_priv
->wm
.skl_latency
[level
];
3646 uint_fixed_16_16_t method1
, method2
;
3647 uint_fixed_16_16_t plane_blocks_per_line
;
3648 uint_fixed_16_16_t selected_result
;
3649 uint32_t interm_pbpl
;
3650 uint32_t plane_bytes_per_line
;
3651 uint32_t res_blocks
, res_lines
;
3653 uint32_t width
= 0, height
= 0;
3654 uint32_t plane_pixel_rate
;
3655 uint_fixed_16_16_t y_tile_minimum
;
3656 uint32_t y_min_scanlines
;
3657 struct intel_atomic_state
*state
=
3658 to_intel_atomic_state(cstate
->base
.state
);
3659 bool apply_memory_bw_wa
= skl_needs_memory_bw_wa(state
);
3660 bool y_tiled
, x_tiled
;
3662 if (latency
== 0 || !cstate
->base
.active
|| !intel_pstate
->base
.visible
) {
3667 y_tiled
= fb
->modifier
== I915_FORMAT_MOD_Y_TILED
||
3668 fb
->modifier
== I915_FORMAT_MOD_Yf_TILED
;
3669 x_tiled
= fb
->modifier
== I915_FORMAT_MOD_X_TILED
;
3671 /* Display WA #1141: kbl. */
3672 if (IS_KABYLAKE(dev_priv
) && dev_priv
->ipc_enabled
)
3675 if (apply_memory_bw_wa
&& x_tiled
)
3678 width
= drm_rect_width(&intel_pstate
->base
.src
) >> 16;
3679 height
= drm_rect_height(&intel_pstate
->base
.src
) >> 16;
3681 if (drm_rotation_90_or_270(pstate
->rotation
))
3682 swap(width
, height
);
3684 cpp
= fb
->format
->cpp
[0];
3685 plane_pixel_rate
= skl_adjusted_plane_pixel_rate(cstate
, intel_pstate
);
3687 if (drm_rotation_90_or_270(pstate
->rotation
)) {
3688 int cpp
= (fb
->format
->format
== DRM_FORMAT_NV12
) ?
3689 fb
->format
->cpp
[1] :
3694 y_min_scanlines
= 16;
3697 y_min_scanlines
= 8;
3700 y_min_scanlines
= 4;
3707 y_min_scanlines
= 4;
3710 if (apply_memory_bw_wa
)
3711 y_min_scanlines
*= 2;
3713 plane_bytes_per_line
= width
* cpp
;
3715 interm_pbpl
= DIV_ROUND_UP(plane_bytes_per_line
*
3716 y_min_scanlines
, 512);
3717 plane_blocks_per_line
=
3718 fixed_16_16_div_round_up(interm_pbpl
, y_min_scanlines
);
3719 } else if (x_tiled
) {
3720 interm_pbpl
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
3721 plane_blocks_per_line
= u32_to_fixed_16_16(interm_pbpl
);
3723 interm_pbpl
= DIV_ROUND_UP(plane_bytes_per_line
, 512) + 1;
3724 plane_blocks_per_line
= u32_to_fixed_16_16(interm_pbpl
);
3727 method1
= skl_wm_method1(plane_pixel_rate
, cpp
, latency
);
3728 method2
= skl_wm_method2(plane_pixel_rate
,
3729 cstate
->base
.adjusted_mode
.crtc_htotal
,
3731 plane_blocks_per_line
);
3733 y_tile_minimum
= mul_u32_fixed_16_16(y_min_scanlines
,
3734 plane_blocks_per_line
);
3737 selected_result
= max_fixed_16_16(method2
, y_tile_minimum
);
3739 if ((cpp
* cstate
->base
.adjusted_mode
.crtc_htotal
/ 512 < 1) &&
3740 (plane_bytes_per_line
/ 512 < 1))
3741 selected_result
= method2
;
3742 else if ((ddb_allocation
/
3743 fixed_16_16_to_u32_round_up(plane_blocks_per_line
)) >= 1)
3744 selected_result
= min_fixed_16_16(method1
, method2
);
3746 selected_result
= method1
;
3749 res_blocks
= fixed_16_16_to_u32_round_up(selected_result
) + 1;
3750 res_lines
= DIV_ROUND_UP(selected_result
.val
,
3751 plane_blocks_per_line
.val
);
3753 if (level
>= 1 && level
<= 7) {
3755 res_blocks
+= fixed_16_16_to_u32_round_up(y_tile_minimum
);
3756 res_lines
+= y_min_scanlines
;
3762 if (res_blocks
>= ddb_allocation
|| res_lines
> 31) {
3766 * If there are no valid level 0 watermarks, then we can't
3767 * support this display configuration.
3772 struct drm_plane
*plane
= pstate
->plane
;
3774 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3775 DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n",
3776 plane
->base
.id
, plane
->name
,
3777 res_blocks
, ddb_allocation
, res_lines
);
3782 *out_blocks
= res_blocks
;
3783 *out_lines
= res_lines
;
3790 skl_compute_wm_level(const struct drm_i915_private
*dev_priv
,
3791 struct skl_ddb_allocation
*ddb
,
3792 struct intel_crtc_state
*cstate
,
3793 struct intel_plane
*intel_plane
,
3795 struct skl_wm_level
*result
)
3797 struct drm_atomic_state
*state
= cstate
->base
.state
;
3798 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
3799 struct drm_plane
*plane
= &intel_plane
->base
;
3800 struct intel_plane_state
*intel_pstate
= NULL
;
3801 uint16_t ddb_blocks
;
3802 enum pipe pipe
= intel_crtc
->pipe
;
3807 intel_atomic_get_existing_plane_state(state
,
3811 * Note: If we start supporting multiple pending atomic commits against
3812 * the same planes/CRTC's in the future, plane->state will no longer be
3813 * the correct pre-state to use for the calculations here and we'll
3814 * need to change where we get the 'unchanged' plane data from.
3816 * For now this is fine because we only allow one queued commit against
3817 * a CRTC. Even if the plane isn't modified by this transaction and we
3818 * don't have a plane lock, we still have the CRTC's lock, so we know
3819 * that no other transactions are racing with us to update it.
3822 intel_pstate
= to_intel_plane_state(plane
->state
);
3824 WARN_ON(!intel_pstate
->base
.fb
);
3826 ddb_blocks
= skl_ddb_entry_size(&ddb
->plane
[pipe
][intel_plane
->id
]);
3828 ret
= skl_compute_plane_wm(dev_priv
,
3833 &result
->plane_res_b
,
3834 &result
->plane_res_l
,
3843 skl_compute_linetime_wm(struct intel_crtc_state
*cstate
)
3845 struct drm_atomic_state
*state
= cstate
->base
.state
;
3846 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
3847 uint32_t pixel_rate
;
3848 uint32_t linetime_wm
;
3850 if (!cstate
->base
.active
)
3853 pixel_rate
= cstate
->pixel_rate
;
3855 if (WARN_ON(pixel_rate
== 0))
3858 linetime_wm
= DIV_ROUND_UP(8 * cstate
->base
.adjusted_mode
.crtc_htotal
*
3861 /* Display WA #1135: bxt. */
3862 if (IS_BROXTON(dev_priv
) && dev_priv
->ipc_enabled
)
3863 linetime_wm
= DIV_ROUND_UP(linetime_wm
, 2);
3868 static void skl_compute_transition_wm(struct intel_crtc_state
*cstate
,
3869 struct skl_wm_level
*trans_wm
/* out */)
3871 if (!cstate
->base
.active
)
3874 /* Until we know more, just disable transition WMs */
3875 trans_wm
->plane_en
= false;
3878 static int skl_build_pipe_wm(struct intel_crtc_state
*cstate
,
3879 struct skl_ddb_allocation
*ddb
,
3880 struct skl_pipe_wm
*pipe_wm
)
3882 struct drm_device
*dev
= cstate
->base
.crtc
->dev
;
3883 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
3884 struct intel_plane
*intel_plane
;
3885 struct skl_plane_wm
*wm
;
3886 int level
, max_level
= ilk_wm_max_level(dev_priv
);
3890 * We'll only calculate watermarks for planes that are actually
3891 * enabled, so make sure all other planes are set as disabled.
3893 memset(pipe_wm
->planes
, 0, sizeof(pipe_wm
->planes
));
3895 for_each_intel_plane_mask(&dev_priv
->drm
,
3897 cstate
->base
.plane_mask
) {
3898 wm
= &pipe_wm
->planes
[intel_plane
->id
];
3900 for (level
= 0; level
<= max_level
; level
++) {
3901 ret
= skl_compute_wm_level(dev_priv
, ddb
, cstate
,
3907 skl_compute_transition_wm(cstate
, &wm
->trans_wm
);
3909 pipe_wm
->linetime
= skl_compute_linetime_wm(cstate
);
3914 static void skl_ddb_entry_write(struct drm_i915_private
*dev_priv
,
3916 const struct skl_ddb_entry
*entry
)
3919 I915_WRITE(reg
, (entry
->end
- 1) << 16 | entry
->start
);
3924 static void skl_write_wm_level(struct drm_i915_private
*dev_priv
,
3926 const struct skl_wm_level
*level
)
3930 if (level
->plane_en
) {
3932 val
|= level
->plane_res_b
;
3933 val
|= level
->plane_res_l
<< PLANE_WM_LINES_SHIFT
;
3936 I915_WRITE(reg
, val
);
3939 static void skl_write_plane_wm(struct intel_crtc
*intel_crtc
,
3940 const struct skl_plane_wm
*wm
,
3941 const struct skl_ddb_allocation
*ddb
,
3942 enum plane_id plane_id
)
3944 struct drm_crtc
*crtc
= &intel_crtc
->base
;
3945 struct drm_device
*dev
= crtc
->dev
;
3946 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3947 int level
, max_level
= ilk_wm_max_level(dev_priv
);
3948 enum pipe pipe
= intel_crtc
->pipe
;
3950 for (level
= 0; level
<= max_level
; level
++) {
3951 skl_write_wm_level(dev_priv
, PLANE_WM(pipe
, plane_id
, level
),
3954 skl_write_wm_level(dev_priv
, PLANE_WM_TRANS(pipe
, plane_id
),
3957 skl_ddb_entry_write(dev_priv
, PLANE_BUF_CFG(pipe
, plane_id
),
3958 &ddb
->plane
[pipe
][plane_id
]);
3959 skl_ddb_entry_write(dev_priv
, PLANE_NV12_BUF_CFG(pipe
, plane_id
),
3960 &ddb
->y_plane
[pipe
][plane_id
]);
3963 static void skl_write_cursor_wm(struct intel_crtc
*intel_crtc
,
3964 const struct skl_plane_wm
*wm
,
3965 const struct skl_ddb_allocation
*ddb
)
3967 struct drm_crtc
*crtc
= &intel_crtc
->base
;
3968 struct drm_device
*dev
= crtc
->dev
;
3969 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3970 int level
, max_level
= ilk_wm_max_level(dev_priv
);
3971 enum pipe pipe
= intel_crtc
->pipe
;
3973 for (level
= 0; level
<= max_level
; level
++) {
3974 skl_write_wm_level(dev_priv
, CUR_WM(pipe
, level
),
3977 skl_write_wm_level(dev_priv
, CUR_WM_TRANS(pipe
), &wm
->trans_wm
);
3979 skl_ddb_entry_write(dev_priv
, CUR_BUF_CFG(pipe
),
3980 &ddb
->plane
[pipe
][PLANE_CURSOR
]);
3983 bool skl_wm_level_equals(const struct skl_wm_level
*l1
,
3984 const struct skl_wm_level
*l2
)
3986 if (l1
->plane_en
!= l2
->plane_en
)
3989 /* If both planes aren't enabled, the rest shouldn't matter */
3993 return (l1
->plane_res_l
== l2
->plane_res_l
&&
3994 l1
->plane_res_b
== l2
->plane_res_b
);
3997 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry
*a
,
3998 const struct skl_ddb_entry
*b
)
4000 return a
->start
< b
->end
&& b
->start
< a
->end
;
4003 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry
**entries
,
4004 const struct skl_ddb_entry
*ddb
,
4009 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
4010 if (i
!= ignore
&& entries
[i
] &&
4011 skl_ddb_entries_overlap(ddb
, entries
[i
]))
4017 static int skl_update_pipe_wm(struct drm_crtc_state
*cstate
,
4018 const struct skl_pipe_wm
*old_pipe_wm
,
4019 struct skl_pipe_wm
*pipe_wm
, /* out */
4020 struct skl_ddb_allocation
*ddb
, /* out */
4021 bool *changed
/* out */)
4023 struct intel_crtc_state
*intel_cstate
= to_intel_crtc_state(cstate
);
4026 ret
= skl_build_pipe_wm(intel_cstate
, ddb
, pipe_wm
);
4030 if (!memcmp(old_pipe_wm
, pipe_wm
, sizeof(*pipe_wm
)))
4039 pipes_modified(struct drm_atomic_state
*state
)
4041 struct drm_crtc
*crtc
;
4042 struct drm_crtc_state
*cstate
;
4043 uint32_t i
, ret
= 0;
4045 for_each_crtc_in_state(state
, crtc
, cstate
, i
)
4046 ret
|= drm_crtc_mask(crtc
);
4052 skl_ddb_add_affected_planes(struct intel_crtc_state
*cstate
)
4054 struct drm_atomic_state
*state
= cstate
->base
.state
;
4055 struct drm_device
*dev
= state
->dev
;
4056 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
4057 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4058 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4059 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
4060 struct skl_ddb_allocation
*new_ddb
= &intel_state
->wm_results
.ddb
;
4061 struct skl_ddb_allocation
*cur_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
4062 struct drm_plane_state
*plane_state
;
4063 struct drm_plane
*plane
;
4064 enum pipe pipe
= intel_crtc
->pipe
;
4066 WARN_ON(!drm_atomic_get_existing_crtc_state(state
, crtc
));
4068 drm_for_each_plane_mask(plane
, dev
, cstate
->base
.plane_mask
) {
4069 enum plane_id plane_id
= to_intel_plane(plane
)->id
;
4071 if (skl_ddb_entry_equal(&cur_ddb
->plane
[pipe
][plane_id
],
4072 &new_ddb
->plane
[pipe
][plane_id
]) &&
4073 skl_ddb_entry_equal(&cur_ddb
->y_plane
[pipe
][plane_id
],
4074 &new_ddb
->y_plane
[pipe
][plane_id
]))
4077 plane_state
= drm_atomic_get_plane_state(state
, plane
);
4078 if (IS_ERR(plane_state
))
4079 return PTR_ERR(plane_state
);
4086 skl_compute_ddb(struct drm_atomic_state
*state
)
4088 struct drm_device
*dev
= state
->dev
;
4089 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4090 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
4091 struct intel_crtc
*intel_crtc
;
4092 struct skl_ddb_allocation
*ddb
= &intel_state
->wm_results
.ddb
;
4093 uint32_t realloc_pipes
= pipes_modified(state
);
4097 * If this is our first atomic update following hardware readout,
4098 * we can't trust the DDB that the BIOS programmed for us. Let's
4099 * pretend that all pipes switched active status so that we'll
4100 * ensure a full DDB recompute.
4102 if (dev_priv
->wm
.distrust_bios_wm
) {
4103 ret
= drm_modeset_lock(&dev
->mode_config
.connection_mutex
,
4104 state
->acquire_ctx
);
4108 intel_state
->active_pipe_changes
= ~0;
4111 * We usually only initialize intel_state->active_crtcs if we
4112 * we're doing a modeset; make sure this field is always
4113 * initialized during the sanitization process that happens
4114 * on the first commit too.
4116 if (!intel_state
->modeset
)
4117 intel_state
->active_crtcs
= dev_priv
->active_crtcs
;
4121 * If the modeset changes which CRTC's are active, we need to
4122 * recompute the DDB allocation for *all* active pipes, even
4123 * those that weren't otherwise being modified in any way by this
4124 * atomic commit. Due to the shrinking of the per-pipe allocations
4125 * when new active CRTC's are added, it's possible for a pipe that
4126 * we were already using and aren't changing at all here to suddenly
4127 * become invalid if its DDB needs exceeds its new allocation.
4129 * Note that if we wind up doing a full DDB recompute, we can't let
4130 * any other display updates race with this transaction, so we need
4131 * to grab the lock on *all* CRTC's.
4133 if (intel_state
->active_pipe_changes
) {
4135 intel_state
->wm_results
.dirty_pipes
= ~0;
4139 * We're not recomputing for the pipes not included in the commit, so
4140 * make sure we start with the current state.
4142 memcpy(ddb
, &dev_priv
->wm
.skl_hw
.ddb
, sizeof(*ddb
));
4144 for_each_intel_crtc_mask(dev
, intel_crtc
, realloc_pipes
) {
4145 struct intel_crtc_state
*cstate
;
4147 cstate
= intel_atomic_get_crtc_state(state
, intel_crtc
);
4149 return PTR_ERR(cstate
);
4151 ret
= skl_allocate_pipe_ddb(cstate
, ddb
);
4155 ret
= skl_ddb_add_affected_planes(cstate
);
4164 skl_copy_wm_for_pipe(struct skl_wm_values
*dst
,
4165 struct skl_wm_values
*src
,
4168 memcpy(dst
->ddb
.y_plane
[pipe
], src
->ddb
.y_plane
[pipe
],
4169 sizeof(dst
->ddb
.y_plane
[pipe
]));
4170 memcpy(dst
->ddb
.plane
[pipe
], src
->ddb
.plane
[pipe
],
4171 sizeof(dst
->ddb
.plane
[pipe
]));
4175 skl_print_wm_changes(const struct drm_atomic_state
*state
)
4177 const struct drm_device
*dev
= state
->dev
;
4178 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
4179 const struct intel_atomic_state
*intel_state
=
4180 to_intel_atomic_state(state
);
4181 const struct drm_crtc
*crtc
;
4182 const struct drm_crtc_state
*cstate
;
4183 const struct intel_plane
*intel_plane
;
4184 const struct skl_ddb_allocation
*old_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
4185 const struct skl_ddb_allocation
*new_ddb
= &intel_state
->wm_results
.ddb
;
4188 for_each_crtc_in_state(state
, crtc
, cstate
, i
) {
4189 const struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4190 enum pipe pipe
= intel_crtc
->pipe
;
4192 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
4193 enum plane_id plane_id
= intel_plane
->id
;
4194 const struct skl_ddb_entry
*old
, *new;
4196 old
= &old_ddb
->plane
[pipe
][plane_id
];
4197 new = &new_ddb
->plane
[pipe
][plane_id
];
4199 if (skl_ddb_entry_equal(old
, new))
4202 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4203 intel_plane
->base
.base
.id
,
4204 intel_plane
->base
.name
,
4205 old
->start
, old
->end
,
4206 new->start
, new->end
);
4212 skl_compute_wm(struct drm_atomic_state
*state
)
4214 struct drm_crtc
*crtc
;
4215 struct drm_crtc_state
*cstate
;
4216 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
4217 struct skl_wm_values
*results
= &intel_state
->wm_results
;
4218 struct skl_pipe_wm
*pipe_wm
;
4219 bool changed
= false;
4223 * If this transaction isn't actually touching any CRTC's, don't
4224 * bother with watermark calculation. Note that if we pass this
4225 * test, we're guaranteed to hold at least one CRTC state mutex,
4226 * which means we can safely use values like dev_priv->active_crtcs
4227 * since any racing commits that want to update them would need to
4228 * hold _all_ CRTC state mutexes.
4230 for_each_crtc_in_state(state
, crtc
, cstate
, i
)
4235 /* Clear all dirty flags */
4236 results
->dirty_pipes
= 0;
4238 ret
= skl_compute_ddb(state
);
4243 * Calculate WM's for all pipes that are part of this transaction.
4244 * Note that the DDB allocation above may have added more CRTC's that
4245 * weren't otherwise being modified (and set bits in dirty_pipes) if
4246 * pipe allocations had to change.
4248 * FIXME: Now that we're doing this in the atomic check phase, we
4249 * should allow skl_update_pipe_wm() to return failure in cases where
4250 * no suitable watermark values can be found.
4252 for_each_crtc_in_state(state
, crtc
, cstate
, i
) {
4253 struct intel_crtc_state
*intel_cstate
=
4254 to_intel_crtc_state(cstate
);
4255 const struct skl_pipe_wm
*old_pipe_wm
=
4256 &to_intel_crtc_state(crtc
->state
)->wm
.skl
.optimal
;
4258 pipe_wm
= &intel_cstate
->wm
.skl
.optimal
;
4259 ret
= skl_update_pipe_wm(cstate
, old_pipe_wm
, pipe_wm
,
4260 &results
->ddb
, &changed
);
4265 results
->dirty_pipes
|= drm_crtc_mask(crtc
);
4267 if ((results
->dirty_pipes
& drm_crtc_mask(crtc
)) == 0)
4268 /* This pipe's WM's did not change */
4271 intel_cstate
->update_wm_pre
= true;
4274 skl_print_wm_changes(state
);
4279 static void skl_atomic_update_crtc_wm(struct intel_atomic_state
*state
,
4280 struct intel_crtc_state
*cstate
)
4282 struct intel_crtc
*crtc
= to_intel_crtc(cstate
->base
.crtc
);
4283 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
4284 struct skl_pipe_wm
*pipe_wm
= &cstate
->wm
.skl
.optimal
;
4285 const struct skl_ddb_allocation
*ddb
= &state
->wm_results
.ddb
;
4286 enum pipe pipe
= crtc
->pipe
;
4287 enum plane_id plane_id
;
4289 if (!(state
->wm_results
.dirty_pipes
& drm_crtc_mask(&crtc
->base
)))
4292 I915_WRITE(PIPE_WM_LINETIME(pipe
), pipe_wm
->linetime
);
4294 for_each_plane_id_on_crtc(crtc
, plane_id
) {
4295 if (plane_id
!= PLANE_CURSOR
)
4296 skl_write_plane_wm(crtc
, &pipe_wm
->planes
[plane_id
],
4299 skl_write_cursor_wm(crtc
, &pipe_wm
->planes
[plane_id
],
4304 static void skl_initial_wm(struct intel_atomic_state
*state
,
4305 struct intel_crtc_state
*cstate
)
4307 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
4308 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4309 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4310 struct skl_wm_values
*results
= &state
->wm_results
;
4311 struct skl_wm_values
*hw_vals
= &dev_priv
->wm
.skl_hw
;
4312 enum pipe pipe
= intel_crtc
->pipe
;
4314 if ((results
->dirty_pipes
& drm_crtc_mask(&intel_crtc
->base
)) == 0)
4317 mutex_lock(&dev_priv
->wm
.wm_mutex
);
4319 if (cstate
->base
.active_changed
)
4320 skl_atomic_update_crtc_wm(state
, cstate
);
4322 skl_copy_wm_for_pipe(hw_vals
, results
, pipe
);
4324 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
4327 static void ilk_compute_wm_config(struct drm_device
*dev
,
4328 struct intel_wm_config
*config
)
4330 struct intel_crtc
*crtc
;
4332 /* Compute the currently _active_ config */
4333 for_each_intel_crtc(dev
, crtc
) {
4334 const struct intel_pipe_wm
*wm
= &crtc
->wm
.active
.ilk
;
4336 if (!wm
->pipe_enabled
)
4339 config
->sprites_enabled
|= wm
->sprites_enabled
;
4340 config
->sprites_scaled
|= wm
->sprites_scaled
;
4341 config
->num_pipes_active
++;
4345 static void ilk_program_watermarks(struct drm_i915_private
*dev_priv
)
4347 struct drm_device
*dev
= &dev_priv
->drm
;
4348 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
4349 struct ilk_wm_maximums max
;
4350 struct intel_wm_config config
= {};
4351 struct ilk_wm_values results
= {};
4352 enum intel_ddb_partitioning partitioning
;
4354 ilk_compute_wm_config(dev
, &config
);
4356 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_1_2
, &max
);
4357 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_1_2
);
4359 /* 5/6 split only in single pipe config on IVB+ */
4360 if (INTEL_GEN(dev_priv
) >= 7 &&
4361 config
.num_pipes_active
== 1 && config
.sprites_enabled
) {
4362 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_5_6
, &max
);
4363 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_5_6
);
4365 best_lp_wm
= ilk_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
4367 best_lp_wm
= &lp_wm_1_2
;
4370 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
4371 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
4373 ilk_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
4375 ilk_write_wm_values(dev_priv
, &results
);
4378 static void ilk_initial_watermarks(struct intel_atomic_state
*state
,
4379 struct intel_crtc_state
*cstate
)
4381 struct drm_i915_private
*dev_priv
= to_i915(cstate
->base
.crtc
->dev
);
4382 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
4384 mutex_lock(&dev_priv
->wm
.wm_mutex
);
4385 intel_crtc
->wm
.active
.ilk
= cstate
->wm
.ilk
.intermediate
;
4386 ilk_program_watermarks(dev_priv
);
4387 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
4390 static void ilk_optimize_watermarks(struct intel_atomic_state
*state
,
4391 struct intel_crtc_state
*cstate
)
4393 struct drm_i915_private
*dev_priv
= to_i915(cstate
->base
.crtc
->dev
);
4394 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
4396 mutex_lock(&dev_priv
->wm
.wm_mutex
);
4397 if (cstate
->wm
.need_postvbl_update
) {
4398 intel_crtc
->wm
.active
.ilk
= cstate
->wm
.ilk
.optimal
;
4399 ilk_program_watermarks(dev_priv
);
4401 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
4404 static inline void skl_wm_level_from_reg_val(uint32_t val
,
4405 struct skl_wm_level
*level
)
4407 level
->plane_en
= val
& PLANE_WM_EN
;
4408 level
->plane_res_b
= val
& PLANE_WM_BLOCKS_MASK
;
4409 level
->plane_res_l
= (val
>> PLANE_WM_LINES_SHIFT
) &
4410 PLANE_WM_LINES_MASK
;
4413 void skl_pipe_wm_get_hw_state(struct drm_crtc
*crtc
,
4414 struct skl_pipe_wm
*out
)
4416 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
4417 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4418 enum pipe pipe
= intel_crtc
->pipe
;
4419 int level
, max_level
;
4420 enum plane_id plane_id
;
4423 max_level
= ilk_wm_max_level(dev_priv
);
4425 for_each_plane_id_on_crtc(intel_crtc
, plane_id
) {
4426 struct skl_plane_wm
*wm
= &out
->planes
[plane_id
];
4428 for (level
= 0; level
<= max_level
; level
++) {
4429 if (plane_id
!= PLANE_CURSOR
)
4430 val
= I915_READ(PLANE_WM(pipe
, plane_id
, level
));
4432 val
= I915_READ(CUR_WM(pipe
, level
));
4434 skl_wm_level_from_reg_val(val
, &wm
->wm
[level
]);
4437 if (plane_id
!= PLANE_CURSOR
)
4438 val
= I915_READ(PLANE_WM_TRANS(pipe
, plane_id
));
4440 val
= I915_READ(CUR_WM_TRANS(pipe
));
4442 skl_wm_level_from_reg_val(val
, &wm
->trans_wm
);
4445 if (!intel_crtc
->active
)
4448 out
->linetime
= I915_READ(PIPE_WM_LINETIME(pipe
));
4451 void skl_wm_get_hw_state(struct drm_device
*dev
)
4453 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4454 struct skl_wm_values
*hw
= &dev_priv
->wm
.skl_hw
;
4455 struct skl_ddb_allocation
*ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
4456 struct drm_crtc
*crtc
;
4457 struct intel_crtc
*intel_crtc
;
4458 struct intel_crtc_state
*cstate
;
4460 skl_ddb_get_hw_state(dev_priv
, ddb
);
4461 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4462 intel_crtc
= to_intel_crtc(crtc
);
4463 cstate
= to_intel_crtc_state(crtc
->state
);
4465 skl_pipe_wm_get_hw_state(crtc
, &cstate
->wm
.skl
.optimal
);
4467 if (intel_crtc
->active
)
4468 hw
->dirty_pipes
|= drm_crtc_mask(crtc
);
4471 if (dev_priv
->active_crtcs
) {
4472 /* Fully recompute DDB on first atomic commit */
4473 dev_priv
->wm
.distrust_bios_wm
= true;
4475 /* Easy/common case; just sanitize DDB now if everything off */
4476 memset(ddb
, 0, sizeof(*ddb
));
4480 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
4482 struct drm_device
*dev
= crtc
->dev
;
4483 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4484 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
4485 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4486 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
4487 struct intel_pipe_wm
*active
= &cstate
->wm
.ilk
.optimal
;
4488 enum pipe pipe
= intel_crtc
->pipe
;
4489 static const i915_reg_t wm0_pipe_reg
[] = {
4490 [PIPE_A
] = WM0_PIPEA_ILK
,
4491 [PIPE_B
] = WM0_PIPEB_ILK
,
4492 [PIPE_C
] = WM0_PIPEC_IVB
,
4495 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
4496 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
4497 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
4499 memset(active
, 0, sizeof(*active
));
4501 active
->pipe_enabled
= intel_crtc
->active
;
4503 if (active
->pipe_enabled
) {
4504 u32 tmp
= hw
->wm_pipe
[pipe
];
4507 * For active pipes LP0 watermark is marked as
4508 * enabled, and LP1+ watermaks as disabled since
4509 * we can't really reverse compute them in case
4510 * multiple pipes are active.
4512 active
->wm
[0].enable
= true;
4513 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
4514 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
4515 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
4516 active
->linetime
= hw
->wm_linetime
[pipe
];
4518 int level
, max_level
= ilk_wm_max_level(dev_priv
);
4521 * For inactive pipes, all watermark levels
4522 * should be marked as enabled but zeroed,
4523 * which is what we'd compute them to.
4525 for (level
= 0; level
<= max_level
; level
++)
4526 active
->wm
[level
].enable
= true;
4529 intel_crtc
->wm
.active
.ilk
= *active
;
4532 #define _FW_WM(value, plane) \
4533 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4534 #define _FW_WM_VLV(value, plane) \
4535 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4537 static void vlv_read_wm_values(struct drm_i915_private
*dev_priv
,
4538 struct vlv_wm_values
*wm
)
4543 for_each_pipe(dev_priv
, pipe
) {
4544 tmp
= I915_READ(VLV_DDL(pipe
));
4546 wm
->ddl
[pipe
].plane
[PLANE_PRIMARY
] =
4547 (tmp
>> DDL_PLANE_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4548 wm
->ddl
[pipe
].plane
[PLANE_CURSOR
] =
4549 (tmp
>> DDL_CURSOR_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4550 wm
->ddl
[pipe
].plane
[PLANE_SPRITE0
] =
4551 (tmp
>> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4552 wm
->ddl
[pipe
].plane
[PLANE_SPRITE1
] =
4553 (tmp
>> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4556 tmp
= I915_READ(DSPFW1
);
4557 wm
->sr
.plane
= _FW_WM(tmp
, SR
);
4558 wm
->pipe
[PIPE_B
].plane
[PLANE_CURSOR
] = _FW_WM(tmp
, CURSORB
);
4559 wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] = _FW_WM_VLV(tmp
, PLANEB
);
4560 wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] = _FW_WM_VLV(tmp
, PLANEA
);
4562 tmp
= I915_READ(DSPFW2
);
4563 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] = _FW_WM_VLV(tmp
, SPRITEB
);
4564 wm
->pipe
[PIPE_A
].plane
[PLANE_CURSOR
] = _FW_WM(tmp
, CURSORA
);
4565 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] = _FW_WM_VLV(tmp
, SPRITEA
);
4567 tmp
= I915_READ(DSPFW3
);
4568 wm
->sr
.cursor
= _FW_WM(tmp
, CURSOR_SR
);
4570 if (IS_CHERRYVIEW(dev_priv
)) {
4571 tmp
= I915_READ(DSPFW7_CHV
);
4572 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] = _FW_WM_VLV(tmp
, SPRITED
);
4573 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] = _FW_WM_VLV(tmp
, SPRITEC
);
4575 tmp
= I915_READ(DSPFW8_CHV
);
4576 wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE1
] = _FW_WM_VLV(tmp
, SPRITEF
);
4577 wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE0
] = _FW_WM_VLV(tmp
, SPRITEE
);
4579 tmp
= I915_READ(DSPFW9_CHV
);
4580 wm
->pipe
[PIPE_C
].plane
[PLANE_PRIMARY
] = _FW_WM_VLV(tmp
, PLANEC
);
4581 wm
->pipe
[PIPE_C
].plane
[PLANE_CURSOR
] = _FW_WM(tmp
, CURSORC
);
4583 tmp
= I915_READ(DSPHOWM
);
4584 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
4585 wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITEF_HI
) << 8;
4586 wm
->pipe
[PIPE_C
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEE_HI
) << 8;
4587 wm
->pipe
[PIPE_C
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEC_HI
) << 8;
4588 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
4589 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
4590 wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEB_HI
) << 8;
4591 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
4592 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
4593 wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEA_HI
) << 8;
4595 tmp
= I915_READ(DSPFW7
);
4596 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] = _FW_WM_VLV(tmp
, SPRITED
);
4597 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] = _FW_WM_VLV(tmp
, SPRITEC
);
4599 tmp
= I915_READ(DSPHOWM
);
4600 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
4601 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
4602 wm
->pipe
[PIPE_B
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
4603 wm
->pipe
[PIPE_B
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEB_HI
) << 8;
4604 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE1
] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
4605 wm
->pipe
[PIPE_A
].plane
[PLANE_SPRITE0
] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
4606 wm
->pipe
[PIPE_A
].plane
[PLANE_PRIMARY
] |= _FW_WM(tmp
, PLANEA_HI
) << 8;
4613 void vlv_wm_get_hw_state(struct drm_device
*dev
)
4615 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4616 struct vlv_wm_values
*wm
= &dev_priv
->wm
.vlv
;
4617 struct intel_crtc
*crtc
;
4620 vlv_read_wm_values(dev_priv
, wm
);
4622 wm
->cxsr
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
4623 wm
->level
= VLV_WM_LEVEL_PM2
;
4625 if (IS_CHERRYVIEW(dev_priv
)) {
4626 mutex_lock(&dev_priv
->rps
.hw_lock
);
4628 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4629 if (val
& DSP_MAXFIFO_PM5_ENABLE
)
4630 wm
->level
= VLV_WM_LEVEL_PM5
;
4633 * If DDR DVFS is disabled in the BIOS, Punit
4634 * will never ack the request. So if that happens
4635 * assume we don't have to enable/disable DDR DVFS
4636 * dynamically. To test that just set the REQ_ACK
4637 * bit to poke the Punit, but don't change the
4638 * HIGH/LOW bits so that we don't actually change
4639 * the current state.
4641 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
4642 val
|= FORCE_DDR_FREQ_REQ_ACK
;
4643 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
4645 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
4646 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3)) {
4647 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4648 "assuming DDR DVFS is disabled\n");
4649 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM5
;
4651 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
4652 if ((val
& FORCE_DDR_HIGH_FREQ
) == 0)
4653 wm
->level
= VLV_WM_LEVEL_DDR_DVFS
;
4656 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4659 for_each_intel_crtc(dev
, crtc
) {
4660 struct intel_crtc_state
*crtc_state
=
4661 to_intel_crtc_state(crtc
->base
.state
);
4662 struct vlv_wm_state
*active
= &crtc
->wm
.active
.vlv
;
4663 const struct vlv_fifo_state
*fifo_state
=
4664 &crtc_state
->wm
.vlv
.fifo_state
;
4665 enum pipe pipe
= crtc
->pipe
;
4666 enum plane_id plane_id
;
4669 vlv_get_fifo_size(crtc_state
);
4671 active
->num_levels
= wm
->level
+ 1;
4672 active
->cxsr
= wm
->cxsr
;
4674 /* FIXME sanitize things more */
4675 for (level
= 0; level
< active
->num_levels
; level
++) {
4676 struct vlv_pipe_wm
*raw
=
4677 &crtc_state
->wm
.vlv
.raw
[level
];
4679 active
->sr
[level
].plane
= wm
->sr
.plane
;
4680 active
->sr
[level
].cursor
= wm
->sr
.cursor
;
4682 for_each_plane_id_on_crtc(crtc
, plane_id
) {
4683 active
->wm
[level
].plane
[plane_id
] =
4684 wm
->pipe
[pipe
].plane
[plane_id
];
4686 raw
->plane
[plane_id
] =
4687 vlv_invert_wm_value(active
->wm
[level
].plane
[plane_id
],
4688 fifo_state
->plane
[plane_id
]);
4692 for_each_plane_id_on_crtc(crtc
, plane_id
)
4693 vlv_raw_plane_wm_set(crtc_state
, level
,
4694 plane_id
, USHRT_MAX
);
4695 vlv_invalidate_wms(crtc
, active
, level
);
4697 crtc_state
->wm
.vlv
.optimal
= *active
;
4699 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4701 wm
->pipe
[pipe
].plane
[PLANE_PRIMARY
],
4702 wm
->pipe
[pipe
].plane
[PLANE_CURSOR
],
4703 wm
->pipe
[pipe
].plane
[PLANE_SPRITE0
],
4704 wm
->pipe
[pipe
].plane
[PLANE_SPRITE1
]);
4707 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4708 wm
->sr
.plane
, wm
->sr
.cursor
, wm
->level
, wm
->cxsr
);
4711 void ilk_wm_get_hw_state(struct drm_device
*dev
)
4713 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4714 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
4715 struct drm_crtc
*crtc
;
4717 for_each_crtc(dev
, crtc
)
4718 ilk_pipe_wm_get_hw_state(crtc
);
4720 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
4721 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
4722 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
4724 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
4725 if (INTEL_GEN(dev_priv
) >= 7) {
4726 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
4727 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
4730 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
4731 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
4732 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
4733 else if (IS_IVYBRIDGE(dev_priv
))
4734 hw
->partitioning
= (I915_READ(DISP_ARB_CTL2
) & DISP_DATA_PARTITION_5_6
) ?
4735 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
4738 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
4742 * intel_update_watermarks - update FIFO watermark values based on current modes
4744 * Calculate watermark values for the various WM regs based on current mode
4745 * and plane configuration.
4747 * There are several cases to deal with here:
4748 * - normal (i.e. non-self-refresh)
4749 * - self-refresh (SR) mode
4750 * - lines are large relative to FIFO size (buffer can hold up to 2)
4751 * - lines are small relative to FIFO size (buffer can hold more than 2
4752 * lines), so need to account for TLB latency
4754 * The normal calculation is:
4755 * watermark = dotclock * bytes per pixel * latency
4756 * where latency is platform & configuration dependent (we assume pessimal
4759 * The SR calculation is:
4760 * watermark = (trunc(latency/line time)+1) * surface width *
4763 * line time = htotal / dotclock
4764 * surface width = hdisplay for normal plane and 64 for cursor
4765 * and latency is assumed to be high, as above.
4767 * The final value programmed to the register should always be rounded up,
4768 * and include an extra 2 entries to account for clock crossings.
4770 * We don't use the sprite, so we can ignore that. And on Crestline we have
4771 * to set the non-SR watermarks to 8.
4773 void intel_update_watermarks(struct intel_crtc
*crtc
)
4775 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4777 if (dev_priv
->display
.update_wm
)
4778 dev_priv
->display
.update_wm(crtc
);
4782 * Lock protecting IPS related data structures
4784 DEFINE_SPINLOCK(mchdev_lock
);
4786 /* Global for IPS driver to get at the current i915 device. Protected by
4788 static struct drm_i915_private
*i915_mch_dev
;
4790 bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
)
4794 lockdep_assert_held(&mchdev_lock
);
4796 rgvswctl
= I915_READ16(MEMSWCTL
);
4797 if (rgvswctl
& MEMCTL_CMD_STS
) {
4798 DRM_DEBUG("gpu busy, RCS change rejected\n");
4799 return false; /* still busy with another command */
4802 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
4803 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
4804 I915_WRITE16(MEMSWCTL
, rgvswctl
);
4805 POSTING_READ16(MEMSWCTL
);
4807 rgvswctl
|= MEMCTL_CMD_STS
;
4808 I915_WRITE16(MEMSWCTL
, rgvswctl
);
4813 static void ironlake_enable_drps(struct drm_i915_private
*dev_priv
)
4816 u8 fmax
, fmin
, fstart
, vstart
;
4818 spin_lock_irq(&mchdev_lock
);
4820 rgvmodectl
= I915_READ(MEMMODECTL
);
4822 /* Enable temp reporting */
4823 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
4824 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
4826 /* 100ms RC evaluation intervals */
4827 I915_WRITE(RCUPEI
, 100000);
4828 I915_WRITE(RCDNEI
, 100000);
4830 /* Set max/min thresholds to 90ms and 80ms respectively */
4831 I915_WRITE(RCBMAXAVG
, 90000);
4832 I915_WRITE(RCBMINAVG
, 80000);
4834 I915_WRITE(MEMIHYST
, 1);
4836 /* Set up min, max, and cur for interrupt handling */
4837 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
4838 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
4839 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
4840 MEMMODE_FSTART_SHIFT
;
4842 vstart
= (I915_READ(PXVFREQ(fstart
)) & PXVFREQ_PX_MASK
) >>
4845 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
4846 dev_priv
->ips
.fstart
= fstart
;
4848 dev_priv
->ips
.max_delay
= fstart
;
4849 dev_priv
->ips
.min_delay
= fmin
;
4850 dev_priv
->ips
.cur_delay
= fstart
;
4852 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4853 fmax
, fmin
, fstart
);
4855 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
4858 * Interrupts will be enabled in ironlake_irq_postinstall
4861 I915_WRITE(VIDSTART
, vstart
);
4862 POSTING_READ(VIDSTART
);
4864 rgvmodectl
|= MEMMODE_SWMODE_EN
;
4865 I915_WRITE(MEMMODECTL
, rgvmodectl
);
4867 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
4868 DRM_ERROR("stuck trying to change perf mode\n");
4871 ironlake_set_drps(dev_priv
, fstart
);
4873 dev_priv
->ips
.last_count1
= I915_READ(DMIEC
) +
4874 I915_READ(DDREC
) + I915_READ(CSIEC
);
4875 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
4876 dev_priv
->ips
.last_count2
= I915_READ(GFXEC
);
4877 dev_priv
->ips
.last_time2
= ktime_get_raw_ns();
4879 spin_unlock_irq(&mchdev_lock
);
4882 static void ironlake_disable_drps(struct drm_i915_private
*dev_priv
)
4886 spin_lock_irq(&mchdev_lock
);
4888 rgvswctl
= I915_READ16(MEMSWCTL
);
4890 /* Ack interrupts, disable EFC interrupt */
4891 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
4892 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
4893 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
4894 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
4895 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
4897 /* Go back to the starting frequency */
4898 ironlake_set_drps(dev_priv
, dev_priv
->ips
.fstart
);
4900 rgvswctl
|= MEMCTL_CMD_STS
;
4901 I915_WRITE(MEMSWCTL
, rgvswctl
);
4904 spin_unlock_irq(&mchdev_lock
);
4907 /* There's a funny hw issue where the hw returns all 0 when reading from
4908 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4909 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4910 * all limits and the gpu stuck at whatever frequency it is at atm).
4912 static u32
intel_rps_limits(struct drm_i915_private
*dev_priv
, u8 val
)
4916 /* Only set the down limit when we've reached the lowest level to avoid
4917 * getting more interrupts, otherwise leave this clear. This prevents a
4918 * race in the hw when coming out of rc6: There's a tiny window where
4919 * the hw runs at the minimal clock before selecting the desired
4920 * frequency, if the down threshold expires in that window we will not
4921 * receive a down interrupt. */
4922 if (IS_GEN9(dev_priv
)) {
4923 limits
= (dev_priv
->rps
.max_freq_softlimit
) << 23;
4924 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4925 limits
|= (dev_priv
->rps
.min_freq_softlimit
) << 14;
4927 limits
= dev_priv
->rps
.max_freq_softlimit
<< 24;
4928 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4929 limits
|= dev_priv
->rps
.min_freq_softlimit
<< 16;
4935 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
4938 u32 threshold_up
= 0, threshold_down
= 0; /* in % */
4939 u32 ei_up
= 0, ei_down
= 0;
4941 new_power
= dev_priv
->rps
.power
;
4942 switch (dev_priv
->rps
.power
) {
4944 if (val
> dev_priv
->rps
.efficient_freq
+ 1 &&
4945 val
> dev_priv
->rps
.cur_freq
)
4946 new_power
= BETWEEN
;
4950 if (val
<= dev_priv
->rps
.efficient_freq
&&
4951 val
< dev_priv
->rps
.cur_freq
)
4952 new_power
= LOW_POWER
;
4953 else if (val
>= dev_priv
->rps
.rp0_freq
&&
4954 val
> dev_priv
->rps
.cur_freq
)
4955 new_power
= HIGH_POWER
;
4959 if (val
< (dev_priv
->rps
.rp1_freq
+ dev_priv
->rps
.rp0_freq
) >> 1 &&
4960 val
< dev_priv
->rps
.cur_freq
)
4961 new_power
= BETWEEN
;
4964 /* Max/min bins are special */
4965 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4966 new_power
= LOW_POWER
;
4967 if (val
>= dev_priv
->rps
.max_freq_softlimit
)
4968 new_power
= HIGH_POWER
;
4969 if (new_power
== dev_priv
->rps
.power
)
4972 /* Note the units here are not exactly 1us, but 1280ns. */
4973 switch (new_power
) {
4975 /* Upclock if more than 95% busy over 16ms */
4979 /* Downclock if less than 85% busy over 32ms */
4981 threshold_down
= 85;
4985 /* Upclock if more than 90% busy over 13ms */
4989 /* Downclock if less than 75% busy over 32ms */
4991 threshold_down
= 75;
4995 /* Upclock if more than 85% busy over 10ms */
4999 /* Downclock if less than 60% busy over 32ms */
5001 threshold_down
= 60;
5005 /* When byt can survive without system hang with dynamic
5006 * sw freq adjustments, this restriction can be lifted.
5008 if (IS_VALLEYVIEW(dev_priv
))
5011 I915_WRITE(GEN6_RP_UP_EI
,
5012 GT_INTERVAL_FROM_US(dev_priv
, ei_up
));
5013 I915_WRITE(GEN6_RP_UP_THRESHOLD
,
5014 GT_INTERVAL_FROM_US(dev_priv
,
5015 ei_up
* threshold_up
/ 100));
5017 I915_WRITE(GEN6_RP_DOWN_EI
,
5018 GT_INTERVAL_FROM_US(dev_priv
, ei_down
));
5019 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
,
5020 GT_INTERVAL_FROM_US(dev_priv
,
5021 ei_down
* threshold_down
/ 100));
5023 I915_WRITE(GEN6_RP_CONTROL
,
5024 GEN6_RP_MEDIA_TURBO
|
5025 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
5026 GEN6_RP_MEDIA_IS_GFX
|
5028 GEN6_RP_UP_BUSY_AVG
|
5029 GEN6_RP_DOWN_IDLE_AVG
);
5032 dev_priv
->rps
.power
= new_power
;
5033 dev_priv
->rps
.up_threshold
= threshold_up
;
5034 dev_priv
->rps
.down_threshold
= threshold_down
;
5035 dev_priv
->rps
.last_adj
= 0;
5038 static u32
gen6_rps_pm_mask(struct drm_i915_private
*dev_priv
, u8 val
)
5042 if (val
> dev_priv
->rps
.min_freq_softlimit
)
5043 mask
|= GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT
;
5044 if (val
< dev_priv
->rps
.max_freq_softlimit
)
5045 mask
|= GEN6_PM_RP_UP_EI_EXPIRED
| GEN6_PM_RP_UP_THRESHOLD
;
5047 mask
&= dev_priv
->pm_rps_events
;
5049 return gen6_sanitize_rps_pm_mask(dev_priv
, ~mask
);
5052 /* gen6_set_rps is called to update the frequency request, but should also be
5053 * called when the range (min_delay and max_delay) is modified so that we can
5054 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
5055 static int gen6_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
5057 /* min/max delay may still have been modified so be sure to
5058 * write the limits value.
5060 if (val
!= dev_priv
->rps
.cur_freq
) {
5061 gen6_set_rps_thresholds(dev_priv
, val
);
5063 if (IS_GEN9(dev_priv
))
5064 I915_WRITE(GEN6_RPNSWREQ
,
5065 GEN9_FREQUENCY(val
));
5066 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5067 I915_WRITE(GEN6_RPNSWREQ
,
5068 HSW_FREQUENCY(val
));
5070 I915_WRITE(GEN6_RPNSWREQ
,
5071 GEN6_FREQUENCY(val
) |
5073 GEN6_AGGRESSIVE_TURBO
);
5076 /* Make sure we continue to get interrupts
5077 * until we hit the minimum or maximum frequencies.
5079 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, intel_rps_limits(dev_priv
, val
));
5080 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
5082 dev_priv
->rps
.cur_freq
= val
;
5083 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
5088 static int valleyview_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
5092 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv
) && (val
& 1),
5093 "Odd GPU freq value\n"))
5096 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
5098 if (val
!= dev_priv
->rps
.cur_freq
) {
5099 err
= vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
5103 gen6_set_rps_thresholds(dev_priv
, val
);
5106 dev_priv
->rps
.cur_freq
= val
;
5107 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
5112 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
5114 * * If Gfx is Idle, then
5115 * 1. Forcewake Media well.
5116 * 2. Request idle freq.
5117 * 3. Release Forcewake of Media well.
5119 static void vlv_set_rps_idle(struct drm_i915_private
*dev_priv
)
5121 u32 val
= dev_priv
->rps
.idle_freq
;
5124 if (dev_priv
->rps
.cur_freq
<= val
)
5127 /* The punit delays the write of the frequency and voltage until it
5128 * determines the GPU is awake. During normal usage we don't want to
5129 * waste power changing the frequency if the GPU is sleeping (rc6).
5130 * However, the GPU and driver is now idle and we do not want to delay
5131 * switching to minimum voltage (reducing power whilst idle) as we do
5132 * not expect to be woken in the near future and so must flush the
5133 * change by waking the device.
5135 * We choose to take the media powerwell (either would do to trick the
5136 * punit into committing the voltage change) as that takes a lot less
5137 * power than the render powerwell.
5139 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_MEDIA
);
5140 err
= valleyview_set_rps(dev_priv
, val
);
5141 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_MEDIA
);
5144 DRM_ERROR("Failed to set RPS for idle\n");
5147 void gen6_rps_busy(struct drm_i915_private
*dev_priv
)
5149 mutex_lock(&dev_priv
->rps
.hw_lock
);
5150 if (dev_priv
->rps
.enabled
) {
5153 if (dev_priv
->pm_rps_events
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
))
5154 gen6_rps_reset_ei(dev_priv
);
5155 I915_WRITE(GEN6_PMINTRMSK
,
5156 gen6_rps_pm_mask(dev_priv
, dev_priv
->rps
.cur_freq
));
5158 gen6_enable_rps_interrupts(dev_priv
);
5160 /* Use the user's desired frequency as a guide, but for better
5161 * performance, jump directly to RPe as our starting frequency.
5163 freq
= max(dev_priv
->rps
.cur_freq
,
5164 dev_priv
->rps
.efficient_freq
);
5166 if (intel_set_rps(dev_priv
,
5168 dev_priv
->rps
.min_freq_softlimit
,
5169 dev_priv
->rps
.max_freq_softlimit
)))
5170 DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
5172 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5175 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
5177 /* Flush our bottom-half so that it does not race with us
5178 * setting the idle frequency and so that it is bounded by
5179 * our rpm wakeref. And then disable the interrupts to stop any
5180 * futher RPS reclocking whilst we are asleep.
5182 gen6_disable_rps_interrupts(dev_priv
);
5184 mutex_lock(&dev_priv
->rps
.hw_lock
);
5185 if (dev_priv
->rps
.enabled
) {
5186 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5187 vlv_set_rps_idle(dev_priv
);
5189 gen6_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
5190 dev_priv
->rps
.last_adj
= 0;
5191 I915_WRITE(GEN6_PMINTRMSK
,
5192 gen6_sanitize_rps_pm_mask(dev_priv
, ~0));
5194 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5196 spin_lock(&dev_priv
->rps
.client_lock
);
5197 while (!list_empty(&dev_priv
->rps
.clients
))
5198 list_del_init(dev_priv
->rps
.clients
.next
);
5199 spin_unlock(&dev_priv
->rps
.client_lock
);
5202 void gen6_rps_boost(struct drm_i915_private
*dev_priv
,
5203 struct intel_rps_client
*rps
,
5204 unsigned long submitted
)
5206 /* This is intentionally racy! We peek at the state here, then
5207 * validate inside the RPS worker.
5209 if (!(dev_priv
->gt
.awake
&&
5210 dev_priv
->rps
.enabled
&&
5211 dev_priv
->rps
.cur_freq
< dev_priv
->rps
.boost_freq
))
5214 /* Force a RPS boost (and don't count it against the client) if
5215 * the GPU is severely congested.
5217 if (rps
&& time_after(jiffies
, submitted
+ DRM_I915_THROTTLE_JIFFIES
))
5220 spin_lock(&dev_priv
->rps
.client_lock
);
5221 if (rps
== NULL
|| list_empty(&rps
->link
)) {
5222 spin_lock_irq(&dev_priv
->irq_lock
);
5223 if (dev_priv
->rps
.interrupts_enabled
) {
5224 dev_priv
->rps
.client_boost
= true;
5225 schedule_work(&dev_priv
->rps
.work
);
5227 spin_unlock_irq(&dev_priv
->irq_lock
);
5230 list_add(&rps
->link
, &dev_priv
->rps
.clients
);
5233 dev_priv
->rps
.boosts
++;
5235 spin_unlock(&dev_priv
->rps
.client_lock
);
5238 int intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
5242 lockdep_assert_held(&dev_priv
->rps
.hw_lock
);
5243 GEM_BUG_ON(val
> dev_priv
->rps
.max_freq
);
5244 GEM_BUG_ON(val
< dev_priv
->rps
.min_freq
);
5246 if (!dev_priv
->rps
.enabled
) {
5247 dev_priv
->rps
.cur_freq
= val
;
5251 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5252 err
= valleyview_set_rps(dev_priv
, val
);
5254 err
= gen6_set_rps(dev_priv
, val
);
5259 static void gen9_disable_rc6(struct drm_i915_private
*dev_priv
)
5261 I915_WRITE(GEN6_RC_CONTROL
, 0);
5262 I915_WRITE(GEN9_PG_ENABLE
, 0);
5265 static void gen9_disable_rps(struct drm_i915_private
*dev_priv
)
5267 I915_WRITE(GEN6_RP_CONTROL
, 0);
5270 static void gen6_disable_rps(struct drm_i915_private
*dev_priv
)
5272 I915_WRITE(GEN6_RC_CONTROL
, 0);
5273 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
5274 I915_WRITE(GEN6_RP_CONTROL
, 0);
5277 static void cherryview_disable_rps(struct drm_i915_private
*dev_priv
)
5279 I915_WRITE(GEN6_RC_CONTROL
, 0);
5282 static void valleyview_disable_rps(struct drm_i915_private
*dev_priv
)
5284 /* we're doing forcewake before Disabling RC6,
5285 * This what the BIOS expects when going into suspend */
5286 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5288 I915_WRITE(GEN6_RC_CONTROL
, 0);
5290 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5293 static void intel_print_rc6_info(struct drm_i915_private
*dev_priv
, u32 mode
)
5295 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5296 if (mode
& (GEN7_RC_CTL_TO_MODE
| GEN6_RC_CTL_EI_MODE(1)))
5297 mode
= GEN6_RC_CTL_RC6_ENABLE
;
5301 if (HAS_RC6p(dev_priv
))
5302 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5303 "RC6 %s RC6p %s RC6pp %s\n",
5304 onoff(mode
& GEN6_RC_CTL_RC6_ENABLE
),
5305 onoff(mode
& GEN6_RC_CTL_RC6p_ENABLE
),
5306 onoff(mode
& GEN6_RC_CTL_RC6pp_ENABLE
));
5309 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5310 onoff(mode
& GEN6_RC_CTL_RC6_ENABLE
));
5313 static bool bxt_check_bios_rc6_setup(struct drm_i915_private
*dev_priv
)
5315 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
5316 bool enable_rc6
= true;
5317 unsigned long rc6_ctx_base
;
5321 rc_ctl
= I915_READ(GEN6_RC_CONTROL
);
5322 rc_sw_target
= (I915_READ(GEN6_RC_STATE
) & RC_SW_TARGET_STATE_MASK
) >>
5323 RC_SW_TARGET_STATE_SHIFT
;
5324 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5325 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5326 onoff(rc_ctl
& GEN6_RC_CTL_HW_ENABLE
),
5327 onoff(rc_ctl
& GEN6_RC_CTL_RC6_ENABLE
),
5330 if (!(I915_READ(RC6_LOCATION
) & RC6_CTX_IN_DRAM
)) {
5331 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5336 * The exact context size is not known for BXT, so assume a page size
5339 rc6_ctx_base
= I915_READ(RC6_CTX_BASE
) & RC6_CTX_BASE_MASK
;
5340 if (!((rc6_ctx_base
>= ggtt
->stolen_reserved_base
) &&
5341 (rc6_ctx_base
+ PAGE_SIZE
<= ggtt
->stolen_reserved_base
+
5342 ggtt
->stolen_reserved_size
))) {
5343 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5347 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT
) & IDLE_TIME_MASK
) > 1) &&
5348 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0
) & IDLE_TIME_MASK
) > 1) &&
5349 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT
) & IDLE_TIME_MASK
) > 1) &&
5350 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT
) & IDLE_TIME_MASK
) > 1))) {
5351 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5355 if (!I915_READ(GEN8_PUSHBUS_CONTROL
) ||
5356 !I915_READ(GEN8_PUSHBUS_ENABLE
) ||
5357 !I915_READ(GEN8_PUSHBUS_SHIFT
)) {
5358 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5362 if (!I915_READ(GEN6_GFXPAUSE
)) {
5363 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5367 if (!I915_READ(GEN8_MISC_CTRL0
)) {
5368 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5375 int sanitize_rc6_option(struct drm_i915_private
*dev_priv
, int enable_rc6
)
5377 /* No RC6 before Ironlake and code is gone for ilk. */
5378 if (INTEL_INFO(dev_priv
)->gen
< 6)
5384 if (IS_GEN9_LP(dev_priv
) && !bxt_check_bios_rc6_setup(dev_priv
)) {
5385 DRM_INFO("RC6 disabled by BIOS\n");
5389 /* Respect the kernel parameter if it is set */
5390 if (enable_rc6
>= 0) {
5393 if (HAS_RC6p(dev_priv
))
5394 mask
= INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
|
5397 mask
= INTEL_RC6_ENABLE
;
5399 if ((enable_rc6
& mask
) != enable_rc6
)
5400 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5401 "(requested %d, valid %d)\n",
5402 enable_rc6
& mask
, enable_rc6
, mask
);
5404 return enable_rc6
& mask
;
5407 if (IS_IVYBRIDGE(dev_priv
))
5408 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
5410 return INTEL_RC6_ENABLE
;
5413 static void gen6_init_rps_frequencies(struct drm_i915_private
*dev_priv
)
5415 /* All of these values are in units of 50MHz */
5417 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5418 if (IS_GEN9_LP(dev_priv
)) {
5419 u32 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
5420 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 16) & 0xff;
5421 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
5422 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 0) & 0xff;
5424 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
5425 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 0) & 0xff;
5426 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
5427 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 16) & 0xff;
5429 /* hw_max = RP0 until we check for overclocking */
5430 dev_priv
->rps
.max_freq
= dev_priv
->rps
.rp0_freq
;
5432 dev_priv
->rps
.efficient_freq
= dev_priv
->rps
.rp1_freq
;
5433 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
) ||
5434 IS_GEN9_BC(dev_priv
)) {
5435 u32 ddcc_status
= 0;
5437 if (sandybridge_pcode_read(dev_priv
,
5438 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL
,
5440 dev_priv
->rps
.efficient_freq
=
5442 ((ddcc_status
>> 8) & 0xff),
5443 dev_priv
->rps
.min_freq
,
5444 dev_priv
->rps
.max_freq
);
5447 if (IS_GEN9_BC(dev_priv
)) {
5448 /* Store the frequency values in 16.66 MHZ units, which is
5449 * the natural hardware unit for SKL
5451 dev_priv
->rps
.rp0_freq
*= GEN9_FREQ_SCALER
;
5452 dev_priv
->rps
.rp1_freq
*= GEN9_FREQ_SCALER
;
5453 dev_priv
->rps
.min_freq
*= GEN9_FREQ_SCALER
;
5454 dev_priv
->rps
.max_freq
*= GEN9_FREQ_SCALER
;
5455 dev_priv
->rps
.efficient_freq
*= GEN9_FREQ_SCALER
;
5459 static void reset_rps(struct drm_i915_private
*dev_priv
,
5460 int (*set
)(struct drm_i915_private
*, u8
))
5462 u8 freq
= dev_priv
->rps
.cur_freq
;
5465 dev_priv
->rps
.power
= -1;
5466 dev_priv
->rps
.cur_freq
= -1;
5468 if (set(dev_priv
, freq
))
5469 DRM_ERROR("Failed to reset RPS to initial values\n");
5472 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5473 static void gen9_enable_rps(struct drm_i915_private
*dev_priv
)
5475 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5477 /* Program defaults and thresholds for RPS*/
5478 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
5479 GEN9_FREQUENCY(dev_priv
->rps
.rp1_freq
));
5481 /* 1 second timeout*/
5482 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,
5483 GT_INTERVAL_FROM_US(dev_priv
, 1000000));
5485 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 0xa);
5487 /* Leaning on the below call to gen6_set_rps to program/setup the
5488 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5489 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5490 reset_rps(dev_priv
, gen6_set_rps
);
5492 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5495 static void gen9_enable_rc6(struct drm_i915_private
*dev_priv
)
5497 struct intel_engine_cs
*engine
;
5498 enum intel_engine_id id
;
5499 uint32_t rc6_mask
= 0;
5501 /* 1a: Software RC state - RC0 */
5502 I915_WRITE(GEN6_RC_STATE
, 0);
5504 /* 1b: Get forcewake during program sequence. Although the driver
5505 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5506 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5508 /* 2a: Disable RC states. */
5509 I915_WRITE(GEN6_RC_CONTROL
, 0);
5511 /* 2b: Program RC6 thresholds.*/
5513 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5514 if (IS_SKYLAKE(dev_priv
))
5515 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 108 << 16);
5517 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 54 << 16);
5518 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
5519 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
5520 for_each_engine(engine
, dev_priv
, id
)
5521 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
5523 if (HAS_GUC(dev_priv
))
5524 I915_WRITE(GUC_MAX_IDLE_COUNT
, 0xA);
5526 I915_WRITE(GEN6_RC_SLEEP
, 0);
5528 /* 2c: Program Coarse Power Gating Policies. */
5529 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS
, 25);
5530 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS
, 25);
5532 /* 3a: Enable RC6 */
5533 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
5534 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
5535 DRM_INFO("RC6 %s\n", onoff(rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
));
5536 I915_WRITE(GEN6_RC6_THRESHOLD
, 37500); /* 37.5/125ms per EI */
5537 I915_WRITE(GEN6_RC_CONTROL
,
5538 GEN6_RC_CTL_HW_ENABLE
| GEN6_RC_CTL_EI_MODE(1) | rc6_mask
);
5541 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5542 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5544 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv
))
5545 I915_WRITE(GEN9_PG_ENABLE
, 0);
5547 I915_WRITE(GEN9_PG_ENABLE
, (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ?
5548 (GEN9_RENDER_PG_ENABLE
| GEN9_MEDIA_PG_ENABLE
) : 0);
5550 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5553 static void gen8_enable_rps(struct drm_i915_private
*dev_priv
)
5555 struct intel_engine_cs
*engine
;
5556 enum intel_engine_id id
;
5557 uint32_t rc6_mask
= 0;
5559 /* 1a: Software RC state - RC0 */
5560 I915_WRITE(GEN6_RC_STATE
, 0);
5562 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5563 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5564 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5566 /* 2a: Disable RC states. */
5567 I915_WRITE(GEN6_RC_CONTROL
, 0);
5569 /* 2b: Program RC6 thresholds.*/
5570 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
5571 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
5572 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
5573 for_each_engine(engine
, dev_priv
, id
)
5574 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
5575 I915_WRITE(GEN6_RC_SLEEP
, 0);
5576 if (IS_BROADWELL(dev_priv
))
5577 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us/1.28 for TO */
5579 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
5582 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
5583 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
5584 intel_print_rc6_info(dev_priv
, rc6_mask
);
5585 if (IS_BROADWELL(dev_priv
))
5586 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
5587 GEN7_RC_CTL_TO_MODE
|
5590 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
5591 GEN6_RC_CTL_EI_MODE(1) |
5594 /* 4 Program defaults and thresholds for RPS*/
5595 I915_WRITE(GEN6_RPNSWREQ
,
5596 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
5597 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
5598 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
5599 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5600 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 100000000 / 128); /* 1 second timeout */
5602 /* Docs recommend 900MHz, and 300 MHz respectively */
5603 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
5604 dev_priv
->rps
.max_freq_softlimit
<< 24 |
5605 dev_priv
->rps
.min_freq_softlimit
<< 16);
5607 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 7600000 / 128); /* 76ms busyness per EI, 90% */
5608 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5609 I915_WRITE(GEN6_RP_UP_EI
, 66000); /* 84.48ms, XXX: random? */
5610 I915_WRITE(GEN6_RP_DOWN_EI
, 350000); /* 448ms, XXX: random? */
5612 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5615 I915_WRITE(GEN6_RP_CONTROL
,
5616 GEN6_RP_MEDIA_TURBO
|
5617 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
5618 GEN6_RP_MEDIA_IS_GFX
|
5620 GEN6_RP_UP_BUSY_AVG
|
5621 GEN6_RP_DOWN_IDLE_AVG
);
5623 /* 6: Ring frequency + overclocking (our driver does this later */
5625 reset_rps(dev_priv
, gen6_set_rps
);
5627 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5630 static void gen6_enable_rps(struct drm_i915_private
*dev_priv
)
5632 struct intel_engine_cs
*engine
;
5633 enum intel_engine_id id
;
5634 u32 rc6vids
, rc6_mask
= 0;
5639 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5641 /* Here begins a magic sequence of register writes to enable
5642 * auto-downclocking.
5644 * Perhaps there might be some value in exposing these to
5647 I915_WRITE(GEN6_RC_STATE
, 0);
5649 /* Clear the DBG now so we don't confuse earlier errors */
5650 gtfifodbg
= I915_READ(GTFIFODBG
);
5652 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
5653 I915_WRITE(GTFIFODBG
, gtfifodbg
);
5656 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5658 /* disable the counters and set deterministic thresholds */
5659 I915_WRITE(GEN6_RC_CONTROL
, 0);
5661 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
5662 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
5663 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
5664 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
5665 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
5667 for_each_engine(engine
, dev_priv
, id
)
5668 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
5670 I915_WRITE(GEN6_RC_SLEEP
, 0);
5671 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
5672 if (IS_IVYBRIDGE(dev_priv
))
5673 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
5675 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
5676 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
5677 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
5679 /* Check if we are enabling RC6 */
5680 rc6_mode
= intel_enable_rc6();
5681 if (rc6_mode
& INTEL_RC6_ENABLE
)
5682 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
5684 /* We don't use those on Haswell */
5685 if (!IS_HASWELL(dev_priv
)) {
5686 if (rc6_mode
& INTEL_RC6p_ENABLE
)
5687 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
5689 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
5690 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
5693 intel_print_rc6_info(dev_priv
, rc6_mask
);
5695 I915_WRITE(GEN6_RC_CONTROL
,
5697 GEN6_RC_CTL_EI_MODE(1) |
5698 GEN6_RC_CTL_HW_ENABLE
);
5700 /* Power down if completely idle for over 50ms */
5701 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
5702 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5704 reset_rps(dev_priv
, gen6_set_rps
);
5707 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
5708 if (IS_GEN6(dev_priv
) && ret
) {
5709 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5710 } else if (IS_GEN6(dev_priv
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
5711 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5712 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
5713 rc6vids
&= 0xffff00;
5714 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
5715 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
5717 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5720 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5723 static void gen6_update_ring_freq(struct drm_i915_private
*dev_priv
)
5726 unsigned int gpu_freq
;
5727 unsigned int max_ia_freq
, min_ring_freq
;
5728 unsigned int max_gpu_freq
, min_gpu_freq
;
5729 int scaling_factor
= 180;
5730 struct cpufreq_policy
*policy
;
5732 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5734 policy
= cpufreq_cpu_get(0);
5736 max_ia_freq
= policy
->cpuinfo
.max_freq
;
5737 cpufreq_cpu_put(policy
);
5740 * Default to measured freq if none found, PCU will ensure we
5743 max_ia_freq
= tsc_khz
;
5746 /* Convert from kHz to MHz */
5747 max_ia_freq
/= 1000;
5749 min_ring_freq
= I915_READ(DCLK
) & 0xf;
5750 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5751 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
5753 if (IS_GEN9_BC(dev_priv
)) {
5754 /* Convert GT frequency to 50 HZ units */
5755 min_gpu_freq
= dev_priv
->rps
.min_freq
/ GEN9_FREQ_SCALER
;
5756 max_gpu_freq
= dev_priv
->rps
.max_freq
/ GEN9_FREQ_SCALER
;
5758 min_gpu_freq
= dev_priv
->rps
.min_freq
;
5759 max_gpu_freq
= dev_priv
->rps
.max_freq
;
5763 * For each potential GPU frequency, load a ring frequency we'd like
5764 * to use for memory access. We do this by specifying the IA frequency
5765 * the PCU should use as a reference to determine the ring frequency.
5767 for (gpu_freq
= max_gpu_freq
; gpu_freq
>= min_gpu_freq
; gpu_freq
--) {
5768 int diff
= max_gpu_freq
- gpu_freq
;
5769 unsigned int ia_freq
= 0, ring_freq
= 0;
5771 if (IS_GEN9_BC(dev_priv
)) {
5773 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5774 * No floor required for ring frequency on SKL.
5776 ring_freq
= gpu_freq
;
5777 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
5778 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5779 ring_freq
= max(min_ring_freq
, gpu_freq
);
5780 } else if (IS_HASWELL(dev_priv
)) {
5781 ring_freq
= mult_frac(gpu_freq
, 5, 4);
5782 ring_freq
= max(min_ring_freq
, ring_freq
);
5783 /* leave ia_freq as the default, chosen by cpufreq */
5785 /* On older processors, there is no separate ring
5786 * clock domain, so in order to boost the bandwidth
5787 * of the ring, we need to upclock the CPU (ia_freq).
5789 * For GPU frequencies less than 750MHz,
5790 * just use the lowest ring freq.
5792 if (gpu_freq
< min_freq
)
5795 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
5796 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
5799 sandybridge_pcode_write(dev_priv
,
5800 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
5801 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
5802 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
5807 static int cherryview_rps_max_freq(struct drm_i915_private
*dev_priv
)
5811 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
5813 switch (INTEL_INFO(dev_priv
)->sseu
.eu_total
) {
5815 /* (2 * 4) config */
5816 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT
);
5819 /* (2 * 6) config */
5820 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT
);
5823 /* (2 * 8) config */
5825 /* Setting (2 * 8) Min RP0 for any other combination */
5826 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT
);
5830 rp0
= (rp0
& FB_GFX_FREQ_FUSE_MASK
);
5835 static int cherryview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
5839 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_DUTYCYCLE_REG
);
5840 rpe
= (val
>> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT
) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK
;
5845 static int cherryview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
5849 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
5850 rp1
= (val
& FB_GFX_FREQ_FUSE_MASK
);
5855 static u32
cherryview_rps_min_freq(struct drm_i915_private
*dev_priv
)
5859 val
= vlv_punit_read(dev_priv
, FB_GFX_FMIN_AT_VMIN_FUSE
);
5860 rpn
= ((val
>> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT
) &
5861 FB_GFX_FREQ_FUSE_MASK
);
5866 static int valleyview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
5870 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
5872 rp1
= (val
& FB_GFX_FGUARANTEED_FREQ_FUSE_MASK
) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT
;
5877 static int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
5881 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
5883 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
5885 rp0
= min_t(u32
, rp0
, 0xea);
5890 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
5894 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
5895 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
5896 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
5897 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
5902 static int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
5906 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
5908 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5909 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5910 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5911 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5912 * to make sure it matches what Punit accepts.
5914 return max_t(u32
, val
, 0xc0);
5917 /* Check that the pctx buffer wasn't move under us. */
5918 static void valleyview_check_pctx(struct drm_i915_private
*dev_priv
)
5920 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
5922 WARN_ON(pctx_addr
!= dev_priv
->mm
.stolen_base
+
5923 dev_priv
->vlv_pctx
->stolen
->start
);
5927 /* Check that the pcbr address is not empty. */
5928 static void cherryview_check_pctx(struct drm_i915_private
*dev_priv
)
5930 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
5932 WARN_ON((pctx_addr
>> VLV_PCBR_ADDR_SHIFT
) == 0);
5935 static void cherryview_setup_pctx(struct drm_i915_private
*dev_priv
)
5937 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
5938 unsigned long pctx_paddr
, paddr
;
5940 int pctx_size
= 32*1024;
5942 pcbr
= I915_READ(VLV_PCBR
);
5943 if ((pcbr
>> VLV_PCBR_ADDR_SHIFT
) == 0) {
5944 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5945 paddr
= (dev_priv
->mm
.stolen_base
+
5946 (ggtt
->stolen_size
- pctx_size
));
5948 pctx_paddr
= (paddr
& (~4095));
5949 I915_WRITE(VLV_PCBR
, pctx_paddr
);
5952 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
5955 static void valleyview_setup_pctx(struct drm_i915_private
*dev_priv
)
5957 struct drm_i915_gem_object
*pctx
;
5958 unsigned long pctx_paddr
;
5960 int pctx_size
= 24*1024;
5962 pcbr
= I915_READ(VLV_PCBR
);
5964 /* BIOS set it up already, grab the pre-alloc'd space */
5967 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
5968 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
,
5970 I915_GTT_OFFSET_NONE
,
5975 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5978 * From the Gunit register HAS:
5979 * The Gfx driver is expected to program this register and ensure
5980 * proper allocation within Gfx stolen memory. For example, this
5981 * register should be programmed such than the PCBR range does not
5982 * overlap with other ranges, such as the frame buffer, protected
5983 * memory, or any other relevant ranges.
5985 pctx
= i915_gem_object_create_stolen(dev_priv
, pctx_size
);
5987 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5991 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
5992 I915_WRITE(VLV_PCBR
, pctx_paddr
);
5995 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
5996 dev_priv
->vlv_pctx
= pctx
;
5999 static void valleyview_cleanup_pctx(struct drm_i915_private
*dev_priv
)
6001 if (WARN_ON(!dev_priv
->vlv_pctx
))
6004 i915_gem_object_put(dev_priv
->vlv_pctx
);
6005 dev_priv
->vlv_pctx
= NULL
;
6008 static void vlv_init_gpll_ref_freq(struct drm_i915_private
*dev_priv
)
6010 dev_priv
->rps
.gpll_ref_freq
=
6011 vlv_get_cck_clock(dev_priv
, "GPLL ref",
6012 CCK_GPLL_CLOCK_CONTROL
,
6013 dev_priv
->czclk_freq
);
6015 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
6016 dev_priv
->rps
.gpll_ref_freq
);
6019 static void valleyview_init_gt_powersave(struct drm_i915_private
*dev_priv
)
6023 valleyview_setup_pctx(dev_priv
);
6025 vlv_init_gpll_ref_freq(dev_priv
);
6027 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
6028 switch ((val
>> 6) & 3) {
6031 dev_priv
->mem_freq
= 800;
6034 dev_priv
->mem_freq
= 1066;
6037 dev_priv
->mem_freq
= 1333;
6040 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
6042 dev_priv
->rps
.max_freq
= valleyview_rps_max_freq(dev_priv
);
6043 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
6044 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
6045 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
6046 dev_priv
->rps
.max_freq
);
6048 dev_priv
->rps
.efficient_freq
= valleyview_rps_rpe_freq(dev_priv
);
6049 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
6050 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
6051 dev_priv
->rps
.efficient_freq
);
6053 dev_priv
->rps
.rp1_freq
= valleyview_rps_guar_freq(dev_priv
);
6054 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
6055 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
6056 dev_priv
->rps
.rp1_freq
);
6058 dev_priv
->rps
.min_freq
= valleyview_rps_min_freq(dev_priv
);
6059 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
6060 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
6061 dev_priv
->rps
.min_freq
);
6064 static void cherryview_init_gt_powersave(struct drm_i915_private
*dev_priv
)
6068 cherryview_setup_pctx(dev_priv
);
6070 vlv_init_gpll_ref_freq(dev_priv
);
6072 mutex_lock(&dev_priv
->sb_lock
);
6073 val
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
);
6074 mutex_unlock(&dev_priv
->sb_lock
);
6076 switch ((val
>> 2) & 0x7) {
6078 dev_priv
->mem_freq
= 2000;
6081 dev_priv
->mem_freq
= 1600;
6084 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
6086 dev_priv
->rps
.max_freq
= cherryview_rps_max_freq(dev_priv
);
6087 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
6088 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
6089 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
6090 dev_priv
->rps
.max_freq
);
6092 dev_priv
->rps
.efficient_freq
= cherryview_rps_rpe_freq(dev_priv
);
6093 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
6094 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
6095 dev_priv
->rps
.efficient_freq
);
6097 dev_priv
->rps
.rp1_freq
= cherryview_rps_guar_freq(dev_priv
);
6098 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
6099 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
6100 dev_priv
->rps
.rp1_freq
);
6102 dev_priv
->rps
.min_freq
= cherryview_rps_min_freq(dev_priv
);
6103 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
6104 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
6105 dev_priv
->rps
.min_freq
);
6107 WARN_ONCE((dev_priv
->rps
.max_freq
|
6108 dev_priv
->rps
.efficient_freq
|
6109 dev_priv
->rps
.rp1_freq
|
6110 dev_priv
->rps
.min_freq
) & 1,
6111 "Odd GPU freq values\n");
6114 static void valleyview_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
)
6116 valleyview_cleanup_pctx(dev_priv
);
6119 static void cherryview_enable_rps(struct drm_i915_private
*dev_priv
)
6121 struct intel_engine_cs
*engine
;
6122 enum intel_engine_id id
;
6123 u32 gtfifodbg
, val
, rc6_mode
= 0, pcbr
;
6125 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6127 gtfifodbg
= I915_READ(GTFIFODBG
) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV
|
6128 GT_FIFO_FREE_ENTRIES_CHV
);
6130 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6132 I915_WRITE(GTFIFODBG
, gtfifodbg
);
6135 cherryview_check_pctx(dev_priv
);
6137 /* 1a & 1b: Get forcewake during program sequence. Although the driver
6138 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6139 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6141 /* Disable RC states. */
6142 I915_WRITE(GEN6_RC_CONTROL
, 0);
6144 /* 2a: Program RC6 thresholds.*/
6145 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
6146 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
6147 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
6149 for_each_engine(engine
, dev_priv
, id
)
6150 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
6151 I915_WRITE(GEN6_RC_SLEEP
, 0);
6153 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6154 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x186);
6156 /* allows RC6 residency counter to work */
6157 I915_WRITE(VLV_COUNTER_CONTROL
,
6158 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
6159 VLV_MEDIA_RC6_COUNT_EN
|
6160 VLV_RENDER_RC6_COUNT_EN
));
6162 /* For now we assume BIOS is allocating and populating the PCBR */
6163 pcbr
= I915_READ(VLV_PCBR
);
6166 if ((intel_enable_rc6() & INTEL_RC6_ENABLE
) &&
6167 (pcbr
>> VLV_PCBR_ADDR_SHIFT
))
6168 rc6_mode
= GEN7_RC_CTL_TO_MODE
;
6170 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
6172 /* 4 Program defaults and thresholds for RPS*/
6173 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
6174 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
6175 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
6176 I915_WRITE(GEN6_RP_UP_EI
, 66000);
6177 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
6179 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
6182 I915_WRITE(GEN6_RP_CONTROL
,
6183 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
6184 GEN6_RP_MEDIA_IS_GFX
|
6186 GEN6_RP_UP_BUSY_AVG
|
6187 GEN6_RP_DOWN_IDLE_AVG
);
6189 /* Setting Fixed Bias */
6190 val
= VLV_OVERRIDE_EN
|
6192 CHV_BIAS_CPU_50_SOC_50
;
6193 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
6195 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
6197 /* RPS code assumes GPLL is used */
6198 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
6200 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
6201 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
6203 reset_rps(dev_priv
, valleyview_set_rps
);
6205 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6208 static void valleyview_enable_rps(struct drm_i915_private
*dev_priv
)
6210 struct intel_engine_cs
*engine
;
6211 enum intel_engine_id id
;
6212 u32 gtfifodbg
, val
, rc6_mode
= 0;
6214 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6216 valleyview_check_pctx(dev_priv
);
6218 gtfifodbg
= I915_READ(GTFIFODBG
);
6220 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6222 I915_WRITE(GTFIFODBG
, gtfifodbg
);
6225 /* If VLV, Forcewake all wells, else re-direct to regular path */
6226 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6228 /* Disable RC states. */
6229 I915_WRITE(GEN6_RC_CONTROL
, 0);
6231 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
6232 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
6233 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
6234 I915_WRITE(GEN6_RP_UP_EI
, 66000);
6235 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
6237 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
6239 I915_WRITE(GEN6_RP_CONTROL
,
6240 GEN6_RP_MEDIA_TURBO
|
6241 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
6242 GEN6_RP_MEDIA_IS_GFX
|
6244 GEN6_RP_UP_BUSY_AVG
|
6245 GEN6_RP_DOWN_IDLE_CONT
);
6247 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
6248 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
6249 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
6251 for_each_engine(engine
, dev_priv
, id
)
6252 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
6254 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
6256 /* allows RC6 residency counter to work */
6257 I915_WRITE(VLV_COUNTER_CONTROL
,
6258 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN
|
6259 VLV_RENDER_RC0_COUNT_EN
|
6260 VLV_MEDIA_RC6_COUNT_EN
|
6261 VLV_RENDER_RC6_COUNT_EN
));
6263 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
6264 rc6_mode
= GEN7_RC_CTL_TO_MODE
| VLV_RC_CTL_CTX_RST_PARALLEL
;
6266 intel_print_rc6_info(dev_priv
, rc6_mode
);
6268 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
6270 /* Setting Fixed Bias */
6271 val
= VLV_OVERRIDE_EN
|
6273 VLV_BIAS_CPU_125_SOC_875
;
6274 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
6276 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
6278 /* RPS code assumes GPLL is used */
6279 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
6281 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
6282 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
6284 reset_rps(dev_priv
, valleyview_set_rps
);
6286 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6289 static unsigned long intel_pxfreq(u32 vidfreq
)
6292 int div
= (vidfreq
& 0x3f0000) >> 16;
6293 int post
= (vidfreq
& 0x3000) >> 12;
6294 int pre
= (vidfreq
& 0x7);
6299 freq
= ((div
* 133333) / ((1<<post
) * pre
));
6304 static const struct cparams
{
6310 { 1, 1333, 301, 28664 },
6311 { 1, 1066, 294, 24460 },
6312 { 1, 800, 294, 25192 },
6313 { 0, 1333, 276, 27605 },
6314 { 0, 1066, 276, 27605 },
6315 { 0, 800, 231, 23784 },
6318 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
6320 u64 total_count
, diff
, ret
;
6321 u32 count1
, count2
, count3
, m
= 0, c
= 0;
6322 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
6325 lockdep_assert_held(&mchdev_lock
);
6327 diff1
= now
- dev_priv
->ips
.last_time1
;
6329 /* Prevent division-by-zero if we are asking too fast.
6330 * Also, we don't get interesting results if we are polling
6331 * faster than once in 10ms, so just return the saved value
6335 return dev_priv
->ips
.chipset_power
;
6337 count1
= I915_READ(DMIEC
);
6338 count2
= I915_READ(DDREC
);
6339 count3
= I915_READ(CSIEC
);
6341 total_count
= count1
+ count2
+ count3
;
6343 /* FIXME: handle per-counter overflow */
6344 if (total_count
< dev_priv
->ips
.last_count1
) {
6345 diff
= ~0UL - dev_priv
->ips
.last_count1
;
6346 diff
+= total_count
;
6348 diff
= total_count
- dev_priv
->ips
.last_count1
;
6351 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
6352 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
6353 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
6360 diff
= div_u64(diff
, diff1
);
6361 ret
= ((m
* diff
) + c
);
6362 ret
= div_u64(ret
, 10);
6364 dev_priv
->ips
.last_count1
= total_count
;
6365 dev_priv
->ips
.last_time1
= now
;
6367 dev_priv
->ips
.chipset_power
= ret
;
6372 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
6376 if (INTEL_INFO(dev_priv
)->gen
!= 5)
6379 spin_lock_irq(&mchdev_lock
);
6381 val
= __i915_chipset_val(dev_priv
);
6383 spin_unlock_irq(&mchdev_lock
);
6388 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
6390 unsigned long m
, x
, b
;
6393 tsfs
= I915_READ(TSFS
);
6395 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
6396 x
= I915_READ8(TR1
);
6398 b
= tsfs
& TSFS_INTR_MASK
;
6400 return ((m
* x
) / 127) - b
;
6403 static int _pxvid_to_vd(u8 pxvid
)
6408 if (pxvid
>= 8 && pxvid
< 31)
6411 return (pxvid
+ 2) * 125;
6414 static u32
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
6416 const int vd
= _pxvid_to_vd(pxvid
);
6417 const int vm
= vd
- 1125;
6419 if (INTEL_INFO(dev_priv
)->is_mobile
)
6420 return vm
> 0 ? vm
: 0;
6425 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
6427 u64 now
, diff
, diffms
;
6430 lockdep_assert_held(&mchdev_lock
);
6432 now
= ktime_get_raw_ns();
6433 diffms
= now
- dev_priv
->ips
.last_time2
;
6434 do_div(diffms
, NSEC_PER_MSEC
);
6436 /* Don't divide by 0 */
6440 count
= I915_READ(GFXEC
);
6442 if (count
< dev_priv
->ips
.last_count2
) {
6443 diff
= ~0UL - dev_priv
->ips
.last_count2
;
6446 diff
= count
- dev_priv
->ips
.last_count2
;
6449 dev_priv
->ips
.last_count2
= count
;
6450 dev_priv
->ips
.last_time2
= now
;
6452 /* More magic constants... */
6454 diff
= div_u64(diff
, diffms
* 10);
6455 dev_priv
->ips
.gfx_power
= diff
;
6458 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
6460 if (INTEL_INFO(dev_priv
)->gen
!= 5)
6463 spin_lock_irq(&mchdev_lock
);
6465 __i915_update_gfx_val(dev_priv
);
6467 spin_unlock_irq(&mchdev_lock
);
6470 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
6472 unsigned long t
, corr
, state1
, corr2
, state2
;
6475 lockdep_assert_held(&mchdev_lock
);
6477 pxvid
= I915_READ(PXVFREQ(dev_priv
->rps
.cur_freq
));
6478 pxvid
= (pxvid
>> 24) & 0x7f;
6479 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
6483 t
= i915_mch_val(dev_priv
);
6485 /* Revel in the empirically derived constants */
6487 /* Correction factor in 1/100000 units */
6489 corr
= ((t
* 2349) + 135940);
6491 corr
= ((t
* 964) + 29317);
6493 corr
= ((t
* 301) + 1004);
6495 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
6497 corr2
= (corr
* dev_priv
->ips
.corr
);
6499 state2
= (corr2
* state1
) / 10000;
6500 state2
/= 100; /* convert to mW */
6502 __i915_update_gfx_val(dev_priv
);
6504 return dev_priv
->ips
.gfx_power
+ state2
;
6507 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
6511 if (INTEL_INFO(dev_priv
)->gen
!= 5)
6514 spin_lock_irq(&mchdev_lock
);
6516 val
= __i915_gfx_val(dev_priv
);
6518 spin_unlock_irq(&mchdev_lock
);
6524 * i915_read_mch_val - return value for IPS use
6526 * Calculate and return a value for the IPS driver to use when deciding whether
6527 * we have thermal and power headroom to increase CPU or GPU power budget.
6529 unsigned long i915_read_mch_val(void)
6531 struct drm_i915_private
*dev_priv
;
6532 unsigned long chipset_val
, graphics_val
, ret
= 0;
6534 spin_lock_irq(&mchdev_lock
);
6537 dev_priv
= i915_mch_dev
;
6539 chipset_val
= __i915_chipset_val(dev_priv
);
6540 graphics_val
= __i915_gfx_val(dev_priv
);
6542 ret
= chipset_val
+ graphics_val
;
6545 spin_unlock_irq(&mchdev_lock
);
6549 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
6552 * i915_gpu_raise - raise GPU frequency limit
6554 * Raise the limit; IPS indicates we have thermal headroom.
6556 bool i915_gpu_raise(void)
6558 struct drm_i915_private
*dev_priv
;
6561 spin_lock_irq(&mchdev_lock
);
6562 if (!i915_mch_dev
) {
6566 dev_priv
= i915_mch_dev
;
6568 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
6569 dev_priv
->ips
.max_delay
--;
6572 spin_unlock_irq(&mchdev_lock
);
6576 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
6579 * i915_gpu_lower - lower GPU frequency limit
6581 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6582 * frequency maximum.
6584 bool i915_gpu_lower(void)
6586 struct drm_i915_private
*dev_priv
;
6589 spin_lock_irq(&mchdev_lock
);
6590 if (!i915_mch_dev
) {
6594 dev_priv
= i915_mch_dev
;
6596 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
6597 dev_priv
->ips
.max_delay
++;
6600 spin_unlock_irq(&mchdev_lock
);
6604 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
6607 * i915_gpu_busy - indicate GPU business to IPS
6609 * Tell the IPS driver whether or not the GPU is busy.
6611 bool i915_gpu_busy(void)
6615 spin_lock_irq(&mchdev_lock
);
6617 ret
= i915_mch_dev
->gt
.awake
;
6618 spin_unlock_irq(&mchdev_lock
);
6622 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
6625 * i915_gpu_turbo_disable - disable graphics turbo
6627 * Disable graphics turbo by resetting the max frequency and setting the
6628 * current frequency to the default.
6630 bool i915_gpu_turbo_disable(void)
6632 struct drm_i915_private
*dev_priv
;
6635 spin_lock_irq(&mchdev_lock
);
6636 if (!i915_mch_dev
) {
6640 dev_priv
= i915_mch_dev
;
6642 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
6644 if (!ironlake_set_drps(dev_priv
, dev_priv
->ips
.fstart
))
6648 spin_unlock_irq(&mchdev_lock
);
6652 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
6655 * Tells the intel_ips driver that the i915 driver is now loaded, if
6656 * IPS got loaded first.
6658 * This awkward dance is so that neither module has to depend on the
6659 * other in order for IPS to do the appropriate communication of
6660 * GPU turbo limits to i915.
6663 ips_ping_for_i915_load(void)
6667 link
= symbol_get(ips_link_to_i915_driver
);
6670 symbol_put(ips_link_to_i915_driver
);
6674 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
6676 /* We only register the i915 ips part with intel-ips once everything is
6677 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6678 spin_lock_irq(&mchdev_lock
);
6679 i915_mch_dev
= dev_priv
;
6680 spin_unlock_irq(&mchdev_lock
);
6682 ips_ping_for_i915_load();
6685 void intel_gpu_ips_teardown(void)
6687 spin_lock_irq(&mchdev_lock
);
6688 i915_mch_dev
= NULL
;
6689 spin_unlock_irq(&mchdev_lock
);
6692 static void intel_init_emon(struct drm_i915_private
*dev_priv
)
6698 /* Disable to program */
6702 /* Program energy weights for various events */
6703 I915_WRITE(SDEW
, 0x15040d00);
6704 I915_WRITE(CSIEW0
, 0x007f0000);
6705 I915_WRITE(CSIEW1
, 0x1e220004);
6706 I915_WRITE(CSIEW2
, 0x04000004);
6708 for (i
= 0; i
< 5; i
++)
6709 I915_WRITE(PEW(i
), 0);
6710 for (i
= 0; i
< 3; i
++)
6711 I915_WRITE(DEW(i
), 0);
6713 /* Program P-state weights to account for frequency power adjustment */
6714 for (i
= 0; i
< 16; i
++) {
6715 u32 pxvidfreq
= I915_READ(PXVFREQ(i
));
6716 unsigned long freq
= intel_pxfreq(pxvidfreq
);
6717 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
6722 val
*= (freq
/ 1000);
6724 val
/= (127*127*900);
6726 DRM_ERROR("bad pxval: %ld\n", val
);
6729 /* Render standby states get 0 weight */
6733 for (i
= 0; i
< 4; i
++) {
6734 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
6735 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
6736 I915_WRITE(PXW(i
), val
);
6739 /* Adjust magic regs to magic values (more experimental results) */
6740 I915_WRITE(OGW0
, 0);
6741 I915_WRITE(OGW1
, 0);
6742 I915_WRITE(EG0
, 0x00007f00);
6743 I915_WRITE(EG1
, 0x0000000e);
6744 I915_WRITE(EG2
, 0x000e0000);
6745 I915_WRITE(EG3
, 0x68000300);
6746 I915_WRITE(EG4
, 0x42000000);
6747 I915_WRITE(EG5
, 0x00140031);
6751 for (i
= 0; i
< 8; i
++)
6752 I915_WRITE(PXWL(i
), 0);
6754 /* Enable PMON + select events */
6755 I915_WRITE(ECR
, 0x80000019);
6757 lcfuse
= I915_READ(LCFUSE02
);
6759 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
6762 void intel_init_gt_powersave(struct drm_i915_private
*dev_priv
)
6765 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6768 if (!i915
.enable_rc6
) {
6769 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6770 intel_runtime_pm_get(dev_priv
);
6773 mutex_lock(&dev_priv
->drm
.struct_mutex
);
6774 mutex_lock(&dev_priv
->rps
.hw_lock
);
6776 /* Initialize RPS limits (for userspace) */
6777 if (IS_CHERRYVIEW(dev_priv
))
6778 cherryview_init_gt_powersave(dev_priv
);
6779 else if (IS_VALLEYVIEW(dev_priv
))
6780 valleyview_init_gt_powersave(dev_priv
);
6781 else if (INTEL_GEN(dev_priv
) >= 6)
6782 gen6_init_rps_frequencies(dev_priv
);
6784 /* Derive initial user preferences/limits from the hardware limits */
6785 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
6786 dev_priv
->rps
.cur_freq
= dev_priv
->rps
.idle_freq
;
6788 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
6789 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
6791 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
6792 dev_priv
->rps
.min_freq_softlimit
=
6794 dev_priv
->rps
.efficient_freq
,
6795 intel_freq_opcode(dev_priv
, 450));
6797 /* After setting max-softlimit, find the overclock max freq */
6798 if (IS_GEN6(dev_priv
) ||
6799 IS_IVYBRIDGE(dev_priv
) || IS_HASWELL(dev_priv
)) {
6802 sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, ¶ms
);
6803 if (params
& BIT(31)) { /* OC supported */
6804 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6805 (dev_priv
->rps
.max_freq
& 0xff) * 50,
6806 (params
& 0xff) * 50);
6807 dev_priv
->rps
.max_freq
= params
& 0xff;
6811 /* Finally allow us to boost to max by default */
6812 dev_priv
->rps
.boost_freq
= dev_priv
->rps
.max_freq
;
6814 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6815 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
6817 intel_autoenable_gt_powersave(dev_priv
);
6820 void intel_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
)
6822 if (IS_VALLEYVIEW(dev_priv
))
6823 valleyview_cleanup_gt_powersave(dev_priv
);
6825 if (!i915
.enable_rc6
)
6826 intel_runtime_pm_put(dev_priv
);
6830 * intel_suspend_gt_powersave - suspend PM work and helper threads
6831 * @dev_priv: i915 device
6833 * We don't want to disable RC6 or other features here, we just want
6834 * to make sure any work we've queued has finished and won't bother
6835 * us while we're suspended.
6837 void intel_suspend_gt_powersave(struct drm_i915_private
*dev_priv
)
6839 if (INTEL_GEN(dev_priv
) < 6)
6842 if (cancel_delayed_work_sync(&dev_priv
->rps
.autoenable_work
))
6843 intel_runtime_pm_put(dev_priv
);
6845 /* gen6_rps_idle() will be called later to disable interrupts */
6848 void intel_sanitize_gt_powersave(struct drm_i915_private
*dev_priv
)
6850 dev_priv
->rps
.enabled
= true; /* force disabling */
6851 intel_disable_gt_powersave(dev_priv
);
6853 gen6_reset_rps_interrupts(dev_priv
);
6856 void intel_disable_gt_powersave(struct drm_i915_private
*dev_priv
)
6858 if (!READ_ONCE(dev_priv
->rps
.enabled
))
6861 mutex_lock(&dev_priv
->rps
.hw_lock
);
6863 if (INTEL_GEN(dev_priv
) >= 9) {
6864 gen9_disable_rc6(dev_priv
);
6865 gen9_disable_rps(dev_priv
);
6866 } else if (IS_CHERRYVIEW(dev_priv
)) {
6867 cherryview_disable_rps(dev_priv
);
6868 } else if (IS_VALLEYVIEW(dev_priv
)) {
6869 valleyview_disable_rps(dev_priv
);
6870 } else if (INTEL_GEN(dev_priv
) >= 6) {
6871 gen6_disable_rps(dev_priv
);
6872 } else if (IS_IRONLAKE_M(dev_priv
)) {
6873 ironlake_disable_drps(dev_priv
);
6876 dev_priv
->rps
.enabled
= false;
6877 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6880 void intel_enable_gt_powersave(struct drm_i915_private
*dev_priv
)
6882 /* We shouldn't be disabling as we submit, so this should be less
6883 * racy than it appears!
6885 if (READ_ONCE(dev_priv
->rps
.enabled
))
6888 /* Powersaving is controlled by the host when inside a VM */
6889 if (intel_vgpu_active(dev_priv
))
6892 mutex_lock(&dev_priv
->rps
.hw_lock
);
6894 if (IS_CHERRYVIEW(dev_priv
)) {
6895 cherryview_enable_rps(dev_priv
);
6896 } else if (IS_VALLEYVIEW(dev_priv
)) {
6897 valleyview_enable_rps(dev_priv
);
6898 } else if (INTEL_GEN(dev_priv
) >= 9) {
6899 gen9_enable_rc6(dev_priv
);
6900 gen9_enable_rps(dev_priv
);
6901 if (IS_GEN9_BC(dev_priv
))
6902 gen6_update_ring_freq(dev_priv
);
6903 } else if (IS_BROADWELL(dev_priv
)) {
6904 gen8_enable_rps(dev_priv
);
6905 gen6_update_ring_freq(dev_priv
);
6906 } else if (INTEL_GEN(dev_priv
) >= 6) {
6907 gen6_enable_rps(dev_priv
);
6908 gen6_update_ring_freq(dev_priv
);
6909 } else if (IS_IRONLAKE_M(dev_priv
)) {
6910 ironlake_enable_drps(dev_priv
);
6911 intel_init_emon(dev_priv
);
6914 WARN_ON(dev_priv
->rps
.max_freq
< dev_priv
->rps
.min_freq
);
6915 WARN_ON(dev_priv
->rps
.idle_freq
> dev_priv
->rps
.max_freq
);
6917 WARN_ON(dev_priv
->rps
.efficient_freq
< dev_priv
->rps
.min_freq
);
6918 WARN_ON(dev_priv
->rps
.efficient_freq
> dev_priv
->rps
.max_freq
);
6920 dev_priv
->rps
.enabled
= true;
6921 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6924 static void __intel_autoenable_gt_powersave(struct work_struct
*work
)
6926 struct drm_i915_private
*dev_priv
=
6927 container_of(work
, typeof(*dev_priv
), rps
.autoenable_work
.work
);
6928 struct intel_engine_cs
*rcs
;
6929 struct drm_i915_gem_request
*req
;
6931 if (READ_ONCE(dev_priv
->rps
.enabled
))
6934 rcs
= dev_priv
->engine
[RCS
];
6935 if (rcs
->last_retired_context
)
6938 if (!rcs
->init_context
)
6941 mutex_lock(&dev_priv
->drm
.struct_mutex
);
6943 req
= i915_gem_request_alloc(rcs
, dev_priv
->kernel_context
);
6947 if (!i915
.enable_execlists
&& i915_switch_context(req
) == 0)
6948 rcs
->init_context(req
);
6950 /* Mark the device busy, calling intel_enable_gt_powersave() */
6951 i915_add_request_no_flush(req
);
6954 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
6956 intel_runtime_pm_put(dev_priv
);
6959 void intel_autoenable_gt_powersave(struct drm_i915_private
*dev_priv
)
6961 if (READ_ONCE(dev_priv
->rps
.enabled
))
6964 if (IS_IRONLAKE_M(dev_priv
)) {
6965 ironlake_enable_drps(dev_priv
);
6966 intel_init_emon(dev_priv
);
6967 } else if (INTEL_INFO(dev_priv
)->gen
>= 6) {
6969 * PCU communication is slow and this doesn't need to be
6970 * done at any specific time, so do this out of our fast path
6971 * to make resume and init faster.
6973 * We depend on the HW RC6 power context save/restore
6974 * mechanism when entering D3 through runtime PM suspend. So
6975 * disable RPM until RPS/RC6 is properly setup. We can only
6976 * get here via the driver load/system resume/runtime resume
6977 * paths, so the _noresume version is enough (and in case of
6978 * runtime resume it's necessary).
6980 if (queue_delayed_work(dev_priv
->wq
,
6981 &dev_priv
->rps
.autoenable_work
,
6982 round_jiffies_up_relative(HZ
)))
6983 intel_runtime_pm_get_noresume(dev_priv
);
6987 static void ibx_init_clock_gating(struct drm_i915_private
*dev_priv
)
6990 * On Ibex Peak and Cougar Point, we need to disable clock
6991 * gating for the panel power sequencer or it will fail to
6992 * start up when no ports are active.
6994 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
6997 static void g4x_disable_trickle_feed(struct drm_i915_private
*dev_priv
)
7001 for_each_pipe(dev_priv
, pipe
) {
7002 I915_WRITE(DSPCNTR(pipe
),
7003 I915_READ(DSPCNTR(pipe
)) |
7004 DISPPLANE_TRICKLE_FEED_DISABLE
);
7006 I915_WRITE(DSPSURF(pipe
), I915_READ(DSPSURF(pipe
)));
7007 POSTING_READ(DSPSURF(pipe
));
7011 static void ilk_init_lp_watermarks(struct drm_i915_private
*dev_priv
)
7013 I915_WRITE(WM3_LP_ILK
, I915_READ(WM3_LP_ILK
) & ~WM1_LP_SR_EN
);
7014 I915_WRITE(WM2_LP_ILK
, I915_READ(WM2_LP_ILK
) & ~WM1_LP_SR_EN
);
7015 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
7018 * Don't touch WM1S_LP_EN here.
7019 * Doing so could cause underruns.
7023 static void ironlake_init_clock_gating(struct drm_i915_private
*dev_priv
)
7025 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
7029 * WaFbcDisableDpfcClockGating:ilk
7031 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
7032 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
7033 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
7035 I915_WRITE(PCH_3DCGDIS0
,
7036 MARIUNIT_CLOCK_GATE_DISABLE
|
7037 SVSMUNIT_CLOCK_GATE_DISABLE
);
7038 I915_WRITE(PCH_3DCGDIS1
,
7039 VFMUNIT_CLOCK_GATE_DISABLE
);
7042 * According to the spec the following bits should be set in
7043 * order to enable memory self-refresh
7044 * The bit 22/21 of 0x42004
7045 * The bit 5 of 0x42020
7046 * The bit 15 of 0x45000
7048 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7049 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
7050 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
7051 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
7052 I915_WRITE(DISP_ARB_CTL
,
7053 (I915_READ(DISP_ARB_CTL
) |
7056 ilk_init_lp_watermarks(dev_priv
);
7059 * Based on the document from hardware guys the following bits
7060 * should be set unconditionally in order to enable FBC.
7061 * The bit 22 of 0x42000
7062 * The bit 22 of 0x42004
7063 * The bit 7,8,9 of 0x42020.
7065 if (IS_IRONLAKE_M(dev_priv
)) {
7066 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
7067 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
7068 I915_READ(ILK_DISPLAY_CHICKEN1
) |
7070 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7071 I915_READ(ILK_DISPLAY_CHICKEN2
) |
7075 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
7077 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7078 I915_READ(ILK_DISPLAY_CHICKEN2
) |
7079 ILK_ELPIN_409_SELECT
);
7080 I915_WRITE(_3D_CHICKEN2
,
7081 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
7082 _3D_CHICKEN2_WM_READ_PIPELINED
);
7084 /* WaDisableRenderCachePipelinedFlush:ilk */
7085 I915_WRITE(CACHE_MODE_0
,
7086 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
7088 /* WaDisable_RenderCache_OperationalFlush:ilk */
7089 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7091 g4x_disable_trickle_feed(dev_priv
);
7093 ibx_init_clock_gating(dev_priv
);
7096 static void cpt_init_clock_gating(struct drm_i915_private
*dev_priv
)
7102 * On Ibex Peak and Cougar Point, we need to disable clock
7103 * gating for the panel power sequencer or it will fail to
7104 * start up when no ports are active.
7106 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
7107 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
7108 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
7109 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
7110 DPLS_EDP_PPS_FIX_DIS
);
7111 /* The below fixes the weird display corruption, a few pixels shifted
7112 * downward, on (only) LVDS of some HP laptops with IVY.
7114 for_each_pipe(dev_priv
, pipe
) {
7115 val
= I915_READ(TRANS_CHICKEN2(pipe
));
7116 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
7117 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
7118 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
7119 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
7120 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
7121 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
7122 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
7123 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
7125 /* WADP0ClockGatingDisable */
7126 for_each_pipe(dev_priv
, pipe
) {
7127 I915_WRITE(TRANS_CHICKEN1(pipe
),
7128 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
7132 static void gen6_check_mch_setup(struct drm_i915_private
*dev_priv
)
7136 tmp
= I915_READ(MCH_SSKPD
);
7137 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
)
7138 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7142 static void gen6_init_clock_gating(struct drm_i915_private
*dev_priv
)
7144 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
7146 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
7148 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7149 I915_READ(ILK_DISPLAY_CHICKEN2
) |
7150 ILK_ELPIN_409_SELECT
);
7152 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
7153 I915_WRITE(_3D_CHICKEN
,
7154 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
7156 /* WaDisable_RenderCache_OperationalFlush:snb */
7157 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7160 * BSpec recoomends 8x4 when MSAA is used,
7161 * however in practice 16x4 seems fastest.
7163 * Note that PS/WM thread counts depend on the WIZ hashing
7164 * disable bit, which we don't touch here, but it's good
7165 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7167 I915_WRITE(GEN6_GT_MODE
,
7168 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
7170 ilk_init_lp_watermarks(dev_priv
);
7172 I915_WRITE(CACHE_MODE_0
,
7173 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
7175 I915_WRITE(GEN6_UCGCTL1
,
7176 I915_READ(GEN6_UCGCTL1
) |
7177 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
7178 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
7180 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7181 * gating disable must be set. Failure to set it results in
7182 * flickering pixels due to Z write ordering failures after
7183 * some amount of runtime in the Mesa "fire" demo, and Unigine
7184 * Sanctuary and Tropics, and apparently anything else with
7185 * alpha test or pixel discard.
7187 * According to the spec, bit 11 (RCCUNIT) must also be set,
7188 * but we didn't debug actual testcases to find it out.
7190 * WaDisableRCCUnitClockGating:snb
7191 * WaDisableRCPBUnitClockGating:snb
7193 I915_WRITE(GEN6_UCGCTL2
,
7194 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
7195 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
7197 /* WaStripsFansDisableFastClipPerformanceFix:snb */
7198 I915_WRITE(_3D_CHICKEN3
,
7199 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
));
7203 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7204 * 3DSTATE_SF number of SF output attributes is more than 16."
7206 I915_WRITE(_3D_CHICKEN3
,
7207 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH
));
7210 * According to the spec the following bits should be
7211 * set in order to enable memory self-refresh and fbc:
7212 * The bit21 and bit22 of 0x42000
7213 * The bit21 and bit22 of 0x42004
7214 * The bit5 and bit7 of 0x42020
7215 * The bit14 of 0x70180
7216 * The bit14 of 0x71180
7218 * WaFbcAsynchFlipDisableFbcQueue:snb
7220 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
7221 I915_READ(ILK_DISPLAY_CHICKEN1
) |
7222 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
7223 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7224 I915_READ(ILK_DISPLAY_CHICKEN2
) |
7225 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
7226 I915_WRITE(ILK_DSPCLK_GATE_D
,
7227 I915_READ(ILK_DSPCLK_GATE_D
) |
7228 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
7229 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
7231 g4x_disable_trickle_feed(dev_priv
);
7233 cpt_init_clock_gating(dev_priv
);
7235 gen6_check_mch_setup(dev_priv
);
7238 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
7240 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
7243 * WaVSThreadDispatchOverride:ivb,vlv
7245 * This actually overrides the dispatch
7246 * mode for all thread types.
7248 reg
&= ~GEN7_FF_SCHED_MASK
;
7249 reg
|= GEN7_FF_TS_SCHED_HW
;
7250 reg
|= GEN7_FF_VS_SCHED_HW
;
7251 reg
|= GEN7_FF_DS_SCHED_HW
;
7253 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
7256 static void lpt_init_clock_gating(struct drm_i915_private
*dev_priv
)
7259 * TODO: this bit should only be enabled when really needed, then
7260 * disabled when not needed anymore in order to save power.
7262 if (HAS_PCH_LPT_LP(dev_priv
))
7263 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
7264 I915_READ(SOUTH_DSPCLK_GATE_D
) |
7265 PCH_LP_PARTITION_LEVEL_DISABLE
);
7267 /* WADPOClockGatingDisable:hsw */
7268 I915_WRITE(TRANS_CHICKEN1(PIPE_A
),
7269 I915_READ(TRANS_CHICKEN1(PIPE_A
)) |
7270 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
7273 static void lpt_suspend_hw(struct drm_i915_private
*dev_priv
)
7275 if (HAS_PCH_LPT_LP(dev_priv
)) {
7276 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7278 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
7279 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7283 static void gen8_set_l3sqc_credits(struct drm_i915_private
*dev_priv
,
7284 int general_prio_credits
,
7285 int high_prio_credits
)
7289 /* WaTempDisableDOPClkGating:bdw */
7290 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
7291 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
7293 I915_WRITE(GEN8_L3SQCREG1
,
7294 L3_GENERAL_PRIO_CREDITS(general_prio_credits
) |
7295 L3_HIGH_PRIO_CREDITS(high_prio_credits
));
7298 * Wait at least 100 clocks before re-enabling clock gating.
7299 * See the definition of L3SQCREG1 in BSpec.
7301 POSTING_READ(GEN8_L3SQCREG1
);
7303 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
7306 static void kabylake_init_clock_gating(struct drm_i915_private
*dev_priv
)
7308 gen9_init_clock_gating(dev_priv
);
7310 /* WaDisableSDEUnitClockGating:kbl */
7311 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
7312 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
7313 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
7315 /* WaDisableGamClockGating:kbl */
7316 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
7317 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
7318 GEN6_GAMUNIT_CLOCK_GATE_DISABLE
);
7320 /* WaFbcNukeOnHostModify:kbl */
7321 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
7322 ILK_DPFC_NUKE_ON_ANY_MODIFICATION
);
7325 static void skylake_init_clock_gating(struct drm_i915_private
*dev_priv
)
7327 gen9_init_clock_gating(dev_priv
);
7329 /* WAC6entrylatency:skl */
7330 I915_WRITE(FBC_LLC_READ_CTRL
, I915_READ(FBC_LLC_READ_CTRL
) |
7331 FBC_LLC_FULLY_OPEN
);
7333 /* WaFbcNukeOnHostModify:skl */
7334 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
7335 ILK_DPFC_NUKE_ON_ANY_MODIFICATION
);
7338 static void broadwell_init_clock_gating(struct drm_i915_private
*dev_priv
)
7342 ilk_init_lp_watermarks(dev_priv
);
7344 /* WaSwitchSolVfFArbitrationPriority:bdw */
7345 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
7347 /* WaPsrDPAMaskVBlankInSRD:bdw */
7348 I915_WRITE(CHICKEN_PAR1_1
,
7349 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
7351 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7352 for_each_pipe(dev_priv
, pipe
) {
7353 I915_WRITE(CHICKEN_PIPESL_1(pipe
),
7354 I915_READ(CHICKEN_PIPESL_1(pipe
)) |
7355 BDW_DPRS_MASK_VBLANK_SRD
);
7358 /* WaVSRefCountFullforceMissDisable:bdw */
7359 /* WaDSRefCountFullforceMissDisable:bdw */
7360 I915_WRITE(GEN7_FF_THREAD_MODE
,
7361 I915_READ(GEN7_FF_THREAD_MODE
) &
7362 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
7364 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
7365 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
7367 /* WaDisableSDEUnitClockGating:bdw */
7368 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
7369 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
7371 /* WaProgramL3SqcReg1Default:bdw */
7372 gen8_set_l3sqc_credits(dev_priv
, 30, 2);
7375 * WaGttCachingOffByDefault:bdw
7376 * GTT cache may not work with big pages, so if those
7377 * are ever enabled GTT cache may need to be disabled.
7379 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
7381 /* WaKVMNotificationOnConfigChange:bdw */
7382 I915_WRITE(CHICKEN_PAR2_1
, I915_READ(CHICKEN_PAR2_1
)
7383 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT
);
7385 lpt_init_clock_gating(dev_priv
);
7387 /* WaDisableDopClockGating:bdw
7389 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
7392 I915_WRITE(GEN6_UCGCTL1
,
7393 I915_READ(GEN6_UCGCTL1
) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE
);
7396 static void haswell_init_clock_gating(struct drm_i915_private
*dev_priv
)
7398 ilk_init_lp_watermarks(dev_priv
);
7400 /* L3 caching of data atomics doesn't work -- disable it. */
7401 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
7402 I915_WRITE(HSW_ROW_CHICKEN3
,
7403 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
7405 /* This is required by WaCatErrorRejectionIssue:hsw */
7406 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
7407 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
7408 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
7410 /* WaVSRefCountFullforceMissDisable:hsw */
7411 I915_WRITE(GEN7_FF_THREAD_MODE
,
7412 I915_READ(GEN7_FF_THREAD_MODE
) & ~GEN7_FF_VS_REF_CNT_FFME
);
7414 /* WaDisable_RenderCache_OperationalFlush:hsw */
7415 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7417 /* enable HiZ Raw Stall Optimization */
7418 I915_WRITE(CACHE_MODE_0_GEN7
,
7419 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
7421 /* WaDisable4x2SubspanOptimization:hsw */
7422 I915_WRITE(CACHE_MODE_1
,
7423 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
7426 * BSpec recommends 8x4 when MSAA is used,
7427 * however in practice 16x4 seems fastest.
7429 * Note that PS/WM thread counts depend on the WIZ hashing
7430 * disable bit, which we don't touch here, but it's good
7431 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7433 I915_WRITE(GEN7_GT_MODE
,
7434 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
7436 /* WaSampleCChickenBitEnable:hsw */
7437 I915_WRITE(HALF_SLICE_CHICKEN3
,
7438 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE
));
7440 /* WaSwitchSolVfFArbitrationPriority:hsw */
7441 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
7443 /* WaRsPkgCStateDisplayPMReq:hsw */
7444 I915_WRITE(CHICKEN_PAR1_1
,
7445 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
7447 lpt_init_clock_gating(dev_priv
);
7450 static void ivybridge_init_clock_gating(struct drm_i915_private
*dev_priv
)
7454 ilk_init_lp_watermarks(dev_priv
);
7456 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
7458 /* WaDisableEarlyCull:ivb */
7459 I915_WRITE(_3D_CHICKEN3
,
7460 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
7462 /* WaDisableBackToBackFlipFix:ivb */
7463 I915_WRITE(IVB_CHICKEN3
,
7464 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
7465 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
7467 /* WaDisablePSDDualDispatchEnable:ivb */
7468 if (IS_IVB_GT1(dev_priv
))
7469 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
7470 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
7472 /* WaDisable_RenderCache_OperationalFlush:ivb */
7473 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7475 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7476 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
7477 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
7479 /* WaApplyL3ControlAndL3ChickenMode:ivb */
7480 I915_WRITE(GEN7_L3CNTLREG1
,
7481 GEN7_WA_FOR_GEN7_L3_CONTROL
);
7482 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
7483 GEN7_WA_L3_CHICKEN_MODE
);
7484 if (IS_IVB_GT1(dev_priv
))
7485 I915_WRITE(GEN7_ROW_CHICKEN2
,
7486 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
7488 /* must write both registers */
7489 I915_WRITE(GEN7_ROW_CHICKEN2
,
7490 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
7491 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
7492 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
7495 /* WaForceL3Serialization:ivb */
7496 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
7497 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
7500 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7501 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7503 I915_WRITE(GEN6_UCGCTL2
,
7504 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
7506 /* This is required by WaCatErrorRejectionIssue:ivb */
7507 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
7508 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
7509 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
7511 g4x_disable_trickle_feed(dev_priv
);
7513 gen7_setup_fixed_func_scheduler(dev_priv
);
7515 if (0) { /* causes HiZ corruption on ivb:gt1 */
7516 /* enable HiZ Raw Stall Optimization */
7517 I915_WRITE(CACHE_MODE_0_GEN7
,
7518 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
7521 /* WaDisable4x2SubspanOptimization:ivb */
7522 I915_WRITE(CACHE_MODE_1
,
7523 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
7526 * BSpec recommends 8x4 when MSAA is used,
7527 * however in practice 16x4 seems fastest.
7529 * Note that PS/WM thread counts depend on the WIZ hashing
7530 * disable bit, which we don't touch here, but it's good
7531 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7533 I915_WRITE(GEN7_GT_MODE
,
7534 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
7536 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
7537 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
7538 snpcr
|= GEN6_MBC_SNPCR_MED
;
7539 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
7541 if (!HAS_PCH_NOP(dev_priv
))
7542 cpt_init_clock_gating(dev_priv
);
7544 gen6_check_mch_setup(dev_priv
);
7547 static void valleyview_init_clock_gating(struct drm_i915_private
*dev_priv
)
7549 /* WaDisableEarlyCull:vlv */
7550 I915_WRITE(_3D_CHICKEN3
,
7551 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
7553 /* WaDisableBackToBackFlipFix:vlv */
7554 I915_WRITE(IVB_CHICKEN3
,
7555 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
7556 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
7558 /* WaPsdDispatchEnable:vlv */
7559 /* WaDisablePSDDualDispatchEnable:vlv */
7560 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
7561 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
7562 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
7564 /* WaDisable_RenderCache_OperationalFlush:vlv */
7565 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7567 /* WaForceL3Serialization:vlv */
7568 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
7569 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
7571 /* WaDisableDopClockGating:vlv */
7572 I915_WRITE(GEN7_ROW_CHICKEN2
,
7573 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
7575 /* This is required by WaCatErrorRejectionIssue:vlv */
7576 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
7577 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
7578 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
7580 gen7_setup_fixed_func_scheduler(dev_priv
);
7583 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7584 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7586 I915_WRITE(GEN6_UCGCTL2
,
7587 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
7589 /* WaDisableL3Bank2xClockGate:vlv
7590 * Disabling L3 clock gating- MMIO 940c[25] = 1
7591 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7592 I915_WRITE(GEN7_UCGCTL4
,
7593 I915_READ(GEN7_UCGCTL4
) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
7596 * BSpec says this must be set, even though
7597 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7599 I915_WRITE(CACHE_MODE_1
,
7600 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
7603 * BSpec recommends 8x4 when MSAA is used,
7604 * however in practice 16x4 seems fastest.
7606 * Note that PS/WM thread counts depend on the WIZ hashing
7607 * disable bit, which we don't touch here, but it's good
7608 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7610 I915_WRITE(GEN7_GT_MODE
,
7611 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
7614 * WaIncreaseL3CreditsForVLVB0:vlv
7615 * This is the hardware default actually.
7617 I915_WRITE(GEN7_L3SQCREG1
, VLV_B0_WA_L3SQCREG1_VALUE
);
7620 * WaDisableVLVClockGating_VBIIssue:vlv
7621 * Disable clock gating on th GCFG unit to prevent a delay
7622 * in the reporting of vblank events.
7624 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, GCFG_DIS
);
7627 static void cherryview_init_clock_gating(struct drm_i915_private
*dev_priv
)
7629 /* WaVSRefCountFullforceMissDisable:chv */
7630 /* WaDSRefCountFullforceMissDisable:chv */
7631 I915_WRITE(GEN7_FF_THREAD_MODE
,
7632 I915_READ(GEN7_FF_THREAD_MODE
) &
7633 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
7635 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7636 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
7637 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
7639 /* WaDisableCSUnitClockGating:chv */
7640 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
7641 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
7643 /* WaDisableSDEUnitClockGating:chv */
7644 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
7645 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
7648 * WaProgramL3SqcReg1Default:chv
7649 * See gfxspecs/Related Documents/Performance Guide/
7650 * LSQC Setting Recommendations.
7652 gen8_set_l3sqc_credits(dev_priv
, 38, 2);
7655 * GTT cache may not work with big pages, so if those
7656 * are ever enabled GTT cache may need to be disabled.
7658 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
7661 static void g4x_init_clock_gating(struct drm_i915_private
*dev_priv
)
7663 uint32_t dspclk_gate
;
7665 I915_WRITE(RENCLK_GATE_D1
, 0);
7666 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
7667 GS_UNIT_CLOCK_GATE_DISABLE
|
7668 CL_UNIT_CLOCK_GATE_DISABLE
);
7669 I915_WRITE(RAMCLK_GATE_D
, 0);
7670 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
7671 OVRUNIT_CLOCK_GATE_DISABLE
|
7672 OVCUNIT_CLOCK_GATE_DISABLE
;
7673 if (IS_GM45(dev_priv
))
7674 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
7675 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
7677 /* WaDisableRenderCachePipelinedFlush */
7678 I915_WRITE(CACHE_MODE_0
,
7679 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
7681 /* WaDisable_RenderCache_OperationalFlush:g4x */
7682 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7684 g4x_disable_trickle_feed(dev_priv
);
7687 static void crestline_init_clock_gating(struct drm_i915_private
*dev_priv
)
7689 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
7690 I915_WRITE(RENCLK_GATE_D2
, 0);
7691 I915_WRITE(DSPCLK_GATE_D
, 0);
7692 I915_WRITE(RAMCLK_GATE_D
, 0);
7693 I915_WRITE16(DEUC
, 0);
7694 I915_WRITE(MI_ARB_STATE
,
7695 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
7697 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7698 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7701 static void broadwater_init_clock_gating(struct drm_i915_private
*dev_priv
)
7703 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
7704 I965_RCC_CLOCK_GATE_DISABLE
|
7705 I965_RCPB_CLOCK_GATE_DISABLE
|
7706 I965_ISC_CLOCK_GATE_DISABLE
|
7707 I965_FBC_CLOCK_GATE_DISABLE
);
7708 I915_WRITE(RENCLK_GATE_D2
, 0);
7709 I915_WRITE(MI_ARB_STATE
,
7710 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
7712 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7713 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7716 static void gen3_init_clock_gating(struct drm_i915_private
*dev_priv
)
7718 u32 dstate
= I915_READ(D_STATE
);
7720 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
7721 DSTATE_DOT_CLOCK_GATING
;
7722 I915_WRITE(D_STATE
, dstate
);
7724 if (IS_PINEVIEW(dev_priv
))
7725 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
7727 /* IIR "flip pending" means done if this bit is set */
7728 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
7730 /* interrupts should cause a wake up from C3 */
7731 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN
));
7733 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7734 I915_WRITE(MI_ARB_STATE
, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
7736 I915_WRITE(MI_ARB_STATE
,
7737 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
7740 static void i85x_init_clock_gating(struct drm_i915_private
*dev_priv
)
7742 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
7744 /* interrupts should cause a wake up from C3 */
7745 I915_WRITE(MI_STATE
, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN
) |
7746 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE
));
7748 I915_WRITE(MEM_MODE
,
7749 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE
));
7752 static void i830_init_clock_gating(struct drm_i915_private
*dev_priv
)
7754 I915_WRITE(MEM_MODE
,
7755 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE
) |
7756 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE
));
7759 void intel_init_clock_gating(struct drm_i915_private
*dev_priv
)
7761 dev_priv
->display
.init_clock_gating(dev_priv
);
7764 void intel_suspend_hw(struct drm_i915_private
*dev_priv
)
7766 if (HAS_PCH_LPT(dev_priv
))
7767 lpt_suspend_hw(dev_priv
);
7770 static void nop_init_clock_gating(struct drm_i915_private
*dev_priv
)
7772 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7776 * intel_init_clock_gating_hooks - setup the clock gating hooks
7777 * @dev_priv: device private
7779 * Setup the hooks that configure which clocks of a given platform can be
7780 * gated and also apply various GT and display specific workarounds for these
7781 * platforms. Note that some GT specific workarounds are applied separately
7782 * when GPU contexts or batchbuffers start their execution.
7784 void intel_init_clock_gating_hooks(struct drm_i915_private
*dev_priv
)
7786 if (IS_SKYLAKE(dev_priv
))
7787 dev_priv
->display
.init_clock_gating
= skylake_init_clock_gating
;
7788 else if (IS_KABYLAKE(dev_priv
))
7789 dev_priv
->display
.init_clock_gating
= kabylake_init_clock_gating
;
7790 else if (IS_BROXTON(dev_priv
))
7791 dev_priv
->display
.init_clock_gating
= bxt_init_clock_gating
;
7792 else if (IS_GEMINILAKE(dev_priv
))
7793 dev_priv
->display
.init_clock_gating
= glk_init_clock_gating
;
7794 else if (IS_BROADWELL(dev_priv
))
7795 dev_priv
->display
.init_clock_gating
= broadwell_init_clock_gating
;
7796 else if (IS_CHERRYVIEW(dev_priv
))
7797 dev_priv
->display
.init_clock_gating
= cherryview_init_clock_gating
;
7798 else if (IS_HASWELL(dev_priv
))
7799 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
7800 else if (IS_IVYBRIDGE(dev_priv
))
7801 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
7802 else if (IS_VALLEYVIEW(dev_priv
))
7803 dev_priv
->display
.init_clock_gating
= valleyview_init_clock_gating
;
7804 else if (IS_GEN6(dev_priv
))
7805 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
7806 else if (IS_GEN5(dev_priv
))
7807 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
7808 else if (IS_G4X(dev_priv
))
7809 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
7810 else if (IS_I965GM(dev_priv
))
7811 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
7812 else if (IS_I965G(dev_priv
))
7813 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
7814 else if (IS_GEN3(dev_priv
))
7815 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
7816 else if (IS_I85X(dev_priv
) || IS_I865G(dev_priv
))
7817 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
7818 else if (IS_GEN2(dev_priv
))
7819 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
7821 MISSING_CASE(INTEL_DEVID(dev_priv
));
7822 dev_priv
->display
.init_clock_gating
= nop_init_clock_gating
;
7826 /* Set up chip specific power management-related functions */
7827 void intel_init_pm(struct drm_i915_private
*dev_priv
)
7829 intel_fbc_init(dev_priv
);
7832 if (IS_PINEVIEW(dev_priv
))
7833 i915_pineview_get_mem_freq(dev_priv
);
7834 else if (IS_GEN5(dev_priv
))
7835 i915_ironlake_get_mem_freq(dev_priv
);
7837 /* For FIFO watermark updates */
7838 if (INTEL_GEN(dev_priv
) >= 9) {
7839 skl_setup_wm_latency(dev_priv
);
7840 dev_priv
->display
.initial_watermarks
= skl_initial_wm
;
7841 dev_priv
->display
.atomic_update_watermarks
= skl_atomic_update_crtc_wm
;
7842 dev_priv
->display
.compute_global_watermarks
= skl_compute_wm
;
7843 } else if (HAS_PCH_SPLIT(dev_priv
)) {
7844 ilk_setup_wm_latency(dev_priv
);
7846 if ((IS_GEN5(dev_priv
) && dev_priv
->wm
.pri_latency
[1] &&
7847 dev_priv
->wm
.spr_latency
[1] && dev_priv
->wm
.cur_latency
[1]) ||
7848 (!IS_GEN5(dev_priv
) && dev_priv
->wm
.pri_latency
[0] &&
7849 dev_priv
->wm
.spr_latency
[0] && dev_priv
->wm
.cur_latency
[0])) {
7850 dev_priv
->display
.compute_pipe_wm
= ilk_compute_pipe_wm
;
7851 dev_priv
->display
.compute_intermediate_wm
=
7852 ilk_compute_intermediate_wm
;
7853 dev_priv
->display
.initial_watermarks
=
7854 ilk_initial_watermarks
;
7855 dev_priv
->display
.optimize_watermarks
=
7856 ilk_optimize_watermarks
;
7858 DRM_DEBUG_KMS("Failed to read display plane latency. "
7861 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
7862 vlv_setup_wm_latency(dev_priv
);
7863 dev_priv
->display
.compute_pipe_wm
= vlv_compute_pipe_wm
;
7864 dev_priv
->display
.initial_watermarks
= vlv_initial_watermarks
;
7865 dev_priv
->display
.atomic_update_watermarks
= vlv_atomic_update_fifo
;
7866 } else if (IS_PINEVIEW(dev_priv
)) {
7867 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv
),
7870 dev_priv
->mem_freq
)) {
7871 DRM_INFO("failed to find known CxSR latency "
7872 "(found ddr%s fsb freq %d, mem freq %d), "
7874 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
7875 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
7876 /* Disable CxSR and never update its watermark again */
7877 intel_set_memory_cxsr(dev_priv
, false);
7878 dev_priv
->display
.update_wm
= NULL
;
7880 dev_priv
->display
.update_wm
= pineview_update_wm
;
7881 } else if (IS_G4X(dev_priv
)) {
7882 dev_priv
->display
.update_wm
= g4x_update_wm
;
7883 } else if (IS_GEN4(dev_priv
)) {
7884 dev_priv
->display
.update_wm
= i965_update_wm
;
7885 } else if (IS_GEN3(dev_priv
)) {
7886 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7887 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
7888 } else if (IS_GEN2(dev_priv
)) {
7889 if (INTEL_INFO(dev_priv
)->num_pipes
== 1) {
7890 dev_priv
->display
.update_wm
= i845_update_wm
;
7891 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
7893 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7894 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
7897 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7901 static inline int gen6_check_mailbox_status(struct drm_i915_private
*dev_priv
)
7904 I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_ERROR_MASK
;
7907 case GEN6_PCODE_SUCCESS
:
7909 case GEN6_PCODE_UNIMPLEMENTED_CMD
:
7910 case GEN6_PCODE_ILLEGAL_CMD
:
7912 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
:
7913 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
:
7915 case GEN6_PCODE_TIMEOUT
:
7923 static inline int gen7_check_mailbox_status(struct drm_i915_private
*dev_priv
)
7926 I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_ERROR_MASK
;
7929 case GEN6_PCODE_SUCCESS
:
7931 case GEN6_PCODE_ILLEGAL_CMD
:
7933 case GEN7_PCODE_TIMEOUT
:
7935 case GEN7_PCODE_ILLEGAL_DATA
:
7937 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
:
7940 MISSING_CASE(flags
);
7945 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
)
7949 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7951 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7952 * use te fw I915_READ variants to reduce the amount of work
7953 * required when reading/writing.
7956 if (I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
7957 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7961 I915_WRITE_FW(GEN6_PCODE_DATA
, *val
);
7962 I915_WRITE_FW(GEN6_PCODE_DATA1
, 0);
7963 I915_WRITE_FW(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
7965 if (intel_wait_for_register_fw(dev_priv
,
7966 GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
, 0,
7968 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
7972 *val
= I915_READ_FW(GEN6_PCODE_DATA
);
7973 I915_WRITE_FW(GEN6_PCODE_DATA
, 0);
7975 if (INTEL_GEN(dev_priv
) > 6)
7976 status
= gen7_check_mailbox_status(dev_priv
);
7978 status
= gen6_check_mailbox_status(dev_priv
);
7981 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7989 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
,
7994 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7996 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7997 * use te fw I915_READ variants to reduce the amount of work
7998 * required when reading/writing.
8001 if (I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
8002 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
8006 I915_WRITE_FW(GEN6_PCODE_DATA
, val
);
8007 I915_WRITE_FW(GEN6_PCODE_DATA1
, 0);
8008 I915_WRITE_FW(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
8010 if (intel_wait_for_register_fw(dev_priv
,
8011 GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
, 0,
8013 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
8017 I915_WRITE_FW(GEN6_PCODE_DATA
, 0);
8019 if (INTEL_GEN(dev_priv
) > 6)
8020 status
= gen7_check_mailbox_status(dev_priv
);
8022 status
= gen6_check_mailbox_status(dev_priv
);
8025 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
8033 static bool skl_pcode_try_request(struct drm_i915_private
*dev_priv
, u32 mbox
,
8034 u32 request
, u32 reply_mask
, u32 reply
,
8039 *status
= sandybridge_pcode_read(dev_priv
, mbox
, &val
);
8041 return *status
|| ((val
& reply_mask
) == reply
);
8045 * skl_pcode_request - send PCODE request until acknowledgment
8046 * @dev_priv: device private
8047 * @mbox: PCODE mailbox ID the request is targeted for
8048 * @request: request ID
8049 * @reply_mask: mask used to check for request acknowledgment
8050 * @reply: value used to check for request acknowledgment
8051 * @timeout_base_ms: timeout for polling with preemption enabled
8053 * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
8054 * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
8055 * The request is acknowledged once the PCODE reply dword equals @reply after
8056 * applying @reply_mask. Polling is first attempted with preemption enabled
8057 * for @timeout_base_ms and if this times out for another 50 ms with
8058 * preemption disabled.
8060 * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
8061 * other error as reported by PCODE.
8063 int skl_pcode_request(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 request
,
8064 u32 reply_mask
, u32 reply
, int timeout_base_ms
)
8069 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
8071 #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
8075 * Prime the PCODE by doing a request first. Normally it guarantees
8076 * that a subsequent request, at most @timeout_base_ms later, succeeds.
8077 * _wait_for() doesn't guarantee when its passed condition is evaluated
8078 * first, so send the first request explicitly.
8084 ret
= _wait_for(COND
, timeout_base_ms
* 1000, 10);
8089 * The above can time out if the number of requests was low (2 in the
8090 * worst case) _and_ PCODE was busy for some reason even after a
8091 * (queued) request and @timeout_base_ms delay. As a workaround retry
8092 * the poll with preemption disabled to maximize the number of
8093 * requests. Increase the timeout from @timeout_base_ms to 50ms to
8094 * account for interrupts that could reduce the number of these
8095 * requests, and for any quirks of the PCODE firmware that delays
8096 * the request completion.
8098 DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
8099 WARN_ON_ONCE(timeout_base_ms
> 3);
8101 ret
= wait_for_atomic(COND
, 50);
8105 return ret
? ret
: status
;
8109 static int byt_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
8113 * Slow = Fast = GPLL ref * N
8115 return DIV_ROUND_CLOSEST(dev_priv
->rps
.gpll_ref_freq
* (val
- 0xb7), 1000);
8118 static int byt_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
8120 return DIV_ROUND_CLOSEST(1000 * val
, dev_priv
->rps
.gpll_ref_freq
) + 0xb7;
8123 static int chv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
8127 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
8129 return DIV_ROUND_CLOSEST(dev_priv
->rps
.gpll_ref_freq
* val
, 2 * 2 * 1000);
8132 static int chv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
8134 /* CHV needs even values */
8135 return DIV_ROUND_CLOSEST(2 * 1000 * val
, dev_priv
->rps
.gpll_ref_freq
) * 2;
8138 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
8140 if (IS_GEN9(dev_priv
))
8141 return DIV_ROUND_CLOSEST(val
* GT_FREQUENCY_MULTIPLIER
,
8143 else if (IS_CHERRYVIEW(dev_priv
))
8144 return chv_gpu_freq(dev_priv
, val
);
8145 else if (IS_VALLEYVIEW(dev_priv
))
8146 return byt_gpu_freq(dev_priv
, val
);
8148 return val
* GT_FREQUENCY_MULTIPLIER
;
8151 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
8153 if (IS_GEN9(dev_priv
))
8154 return DIV_ROUND_CLOSEST(val
* GEN9_FREQ_SCALER
,
8155 GT_FREQUENCY_MULTIPLIER
);
8156 else if (IS_CHERRYVIEW(dev_priv
))
8157 return chv_freq_opcode(dev_priv
, val
);
8158 else if (IS_VALLEYVIEW(dev_priv
))
8159 return byt_freq_opcode(dev_priv
, val
);
8161 return DIV_ROUND_CLOSEST(val
, GT_FREQUENCY_MULTIPLIER
);
8164 struct request_boost
{
8165 struct work_struct work
;
8166 struct drm_i915_gem_request
*req
;
8169 static void __intel_rps_boost_work(struct work_struct
*work
)
8171 struct request_boost
*boost
= container_of(work
, struct request_boost
, work
);
8172 struct drm_i915_gem_request
*req
= boost
->req
;
8174 if (!i915_gem_request_completed(req
))
8175 gen6_rps_boost(req
->i915
, NULL
, req
->emitted_jiffies
);
8177 i915_gem_request_put(req
);
8181 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request
*req
)
8183 struct request_boost
*boost
;
8185 if (req
== NULL
|| INTEL_GEN(req
->i915
) < 6)
8188 if (i915_gem_request_completed(req
))
8191 boost
= kmalloc(sizeof(*boost
), GFP_ATOMIC
);
8195 boost
->req
= i915_gem_request_get(req
);
8197 INIT_WORK(&boost
->work
, __intel_rps_boost_work
);
8198 queue_work(req
->i915
->wq
, &boost
->work
);
8201 void intel_pm_setup(struct drm_i915_private
*dev_priv
)
8203 mutex_init(&dev_priv
->rps
.hw_lock
);
8204 spin_lock_init(&dev_priv
->rps
.client_lock
);
8206 INIT_DELAYED_WORK(&dev_priv
->rps
.autoenable_work
,
8207 __intel_autoenable_gt_powersave
);
8208 INIT_LIST_HEAD(&dev_priv
->rps
.clients
);
8210 dev_priv
->pm
.suspended
= false;
8211 atomic_set(&dev_priv
->pm
.wakeref_count
, 0);